1 /*
2  * Copyright 2023-2024 NXP
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef HAL_NXP_DTS_NXP_S32_S32K344_172MQFP_PINCTRL_H_
8 #define HAL_NXP_DTS_NXP_S32_S32K344_172MQFP_PINCTRL_H_
9 
10 #include <zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h>
11 
12 /* SIUL */
13 #define PTA0_EIRQ0                      NXP_S32_PINMUX(0, 0, 0, 0, 16, 1)
14 #define PTA1_EIRQ1                      NXP_S32_PINMUX(0, 0, 1, 0, 17, 1)
15 #define PTA2_EIRQ2                      NXP_S32_PINMUX(0, 0, 2, 0, 18, 1)
16 #define PTA3_EIRQ3                      NXP_S32_PINMUX(0, 0, 3, 0, 19, 1)
17 #define PTA4_EIRQ4                      NXP_S32_PINMUX(0, 0, 4, 0, 20, 1)
18 #define PTA5_EIRQ5                      NXP_S32_PINMUX(0, 0, 5, 0, 21, 1)
19 #define PTA6_EIRQ6                      NXP_S32_PINMUX(0, 0, 6, 0, 22, 1)
20 #define PTA7_EIRQ7                      NXP_S32_PINMUX(0, 0, 7, 0, 23, 1)
21 #define PTA8_EIRQ16                     NXP_S32_PINMUX(0, 0, 8, 0, 32, 1)
22 #define PTA9_EIRQ17                     NXP_S32_PINMUX(0, 0, 9, 0, 33, 1)
23 #define PTA10_EIRQ18                    NXP_S32_PINMUX(0, 0, 10, 0, 34, 1)
24 #define PTA11_EIRQ19                    NXP_S32_PINMUX(0, 0, 11, 0, 35, 1)
25 #define PTA12_EIRQ20                    NXP_S32_PINMUX(0, 0, 12, 0, 36, 1)
26 #define PTA13_EIRQ21                    NXP_S32_PINMUX(0, 0, 13, 0, 37, 1)
27 #define PTA14_EIRQ22                    NXP_S32_PINMUX(0, 0, 14, 0, 38, 1)
28 #define PTA15_EIRQ23                    NXP_S32_PINMUX(0, 0, 15, 0, 39, 1)
29 #define PTA16_EIRQ4                     NXP_S32_PINMUX(0, 0, 16, 0, 20, 2)
30 #define PTA18_EIRQ0                     NXP_S32_PINMUX(0, 0, 18, 0, 16, 2)
31 #define PTA19_EIRQ1                     NXP_S32_PINMUX(0, 0, 19, 0, 17, 2)
32 #define PTA20_EIRQ2                     NXP_S32_PINMUX(0, 0, 20, 0, 18, 2)
33 #define PTA21_EIRQ3                     NXP_S32_PINMUX(0, 0, 21, 0, 19, 2)
34 #define PTA24_GPI24                     NXP_S32_PINMUX(0, 0, 23, 0, 24, 0)
35 #define PTA25_GPI25                     NXP_S32_PINMUX(0, 0, 23, 0, 25, 0)
36 #define PTA25_EIRQ5                     NXP_S32_PINMUX(0, 0, 23, 0, 21, 2)
37 #define PTA28_EIRQ6                     NXP_S32_PINMUX(0, 0, 28, 0, 22, 2)
38 #define PTA30_EIRQ7                     NXP_S32_PINMUX(0, 0, 30, 0, 23, 2)
39 #define PTB0_EIRQ8                      NXP_S32_PINMUX(0, 0, 32, 0, 24, 1)
40 #define PTB1_EIRQ9                      NXP_S32_PINMUX(0, 0, 33, 0, 25, 1)
41 #define PTB2_EIRQ10                     NXP_S32_PINMUX(0, 0, 34, 0, 26, 1)
42 #define PTB3_EIRQ11                     NXP_S32_PINMUX(0, 0, 35, 0, 27, 1)
43 #define PTB4_EIRQ12                     NXP_S32_PINMUX(0, 0, 36, 0, 28, 1)
44 #define PTB5_EIRQ13                     NXP_S32_PINMUX(0, 0, 37, 0, 29, 1)
45 #define PTB8_EIRQ14                     NXP_S32_PINMUX(0, 0, 40, 0, 30, 1)
46 #define PTB9_EIRQ15                     NXP_S32_PINMUX(0, 0, 41, 0, 31, 1)
47 #define PTB10_EIRQ24                    NXP_S32_PINMUX(0, 0, 42, 0, 40, 1)
48 #define PTB11_EIRQ25                    NXP_S32_PINMUX(0, 0, 43, 0, 41, 1)
49 #define PTB12_EIRQ26                    NXP_S32_PINMUX(0, 0, 44, 0, 42, 1)
50 #define PTB13_EIRQ27                    NXP_S32_PINMUX(0, 0, 45, 0, 43, 1)
51 #define PTB14_EIRQ28                    NXP_S32_PINMUX(0, 0, 46, 0, 44, 1)
52 #define PTB15_EIRQ29                    NXP_S32_PINMUX(0, 0, 47, 0, 45, 1)
53 #define PTB16_EIRQ30                    NXP_S32_PINMUX(0, 0, 48, 0, 46, 1)
54 #define PTB17_EIRQ31                    NXP_S32_PINMUX(0, 0, 49, 0, 47, 1)
55 #define PTB21_EIRQ8                     NXP_S32_PINMUX(0, 0, 53, 0, 24, 2)
56 #define PTB22_EIRQ9                     NXP_S32_PINMUX(0, 0, 54, 0, 25, 2)
57 #define PTB23_EIRQ10                    NXP_S32_PINMUX(0, 0, 55, 0, 26, 2)
58 #define PTB24_EIRQ11                    NXP_S32_PINMUX(0, 0, 56, 0, 27, 2)
59 #define PTB25_EIRQ12                    NXP_S32_PINMUX(0, 0, 57, 0, 28, 2)
60 #define PTB26_EIRQ13                    NXP_S32_PINMUX(0, 0, 58, 0, 29, 2)
61 #define PTB28_EIRQ14                    NXP_S32_PINMUX(0, 0, 60, 0, 30, 2)
62 #define PTC0_EIRQ0                      NXP_S32_PINMUX(0, 0, 64, 0, 16, 3)
63 #define PTC1_EIRQ1                      NXP_S32_PINMUX(0, 0, 65, 0, 17, 3)
64 #define PTC2_EIRQ2                      NXP_S32_PINMUX(0, 0, 66, 0, 18, 3)
65 #define PTC3_EIRQ3                      NXP_S32_PINMUX(0, 0, 67, 0, 19, 3)
66 #define PTC4_EIRQ4                      NXP_S32_PINMUX(0, 0, 68, 0, 20, 3)
67 #define PTC5_EIRQ5                      NXP_S32_PINMUX(0, 0, 69, 0, 21, 3)
68 #define PTC6_EIRQ6                      NXP_S32_PINMUX(0, 0, 70, 0, 22, 3)
69 #define PTC7_EIRQ7                      NXP_S32_PINMUX(0, 0, 71, 0, 23, 3)
70 #define PTC8_EIRQ16                     NXP_S32_PINMUX(0, 0, 72, 0, 32, 2)
71 #define PTC9_EIRQ17                     NXP_S32_PINMUX(0, 0, 73, 0, 33, 2)
72 #define PTC10_EIRQ18                    NXP_S32_PINMUX(0, 0, 74, 0, 34, 2)
73 #define PTC11_EIRQ19                    NXP_S32_PINMUX(0, 0, 75, 0, 35, 2)
74 #define PTC12_EIRQ20                    NXP_S32_PINMUX(0, 0, 76, 0, 36, 2)
75 #define PTC13_EIRQ21                    NXP_S32_PINMUX(0, 0, 77, 0, 37, 2)
76 #define PTC14_EIRQ22                    NXP_S32_PINMUX(0, 0, 78, 0, 38, 2)
77 #define PTC15_EIRQ23                    NXP_S32_PINMUX(0, 0, 79, 0, 39, 2)
78 #define PTC20_EIRQ16                    NXP_S32_PINMUX(0, 0, 84, 0, 32, 3)
79 #define PTC21_EIRQ17                    NXP_S32_PINMUX(0, 0, 85, 0, 33, 3)
80 #define PTC23_EIRQ18                    NXP_S32_PINMUX(0, 0, 87, 0, 34, 3)
81 #define PTC24_EIRQ19                    NXP_S32_PINMUX(0, 0, 88, 0, 35, 3)
82 #define PTC25_EIRQ20                    NXP_S32_PINMUX(0, 0, 89, 0, 36, 3)
83 #define PTC26_EIRQ21                    NXP_S32_PINMUX(0, 0, 90, 0, 37, 3)
84 #define PTC27_EIRQ22                    NXP_S32_PINMUX(0, 0, 91, 0, 38, 3)
85 #define PTC29_EIRQ23                    NXP_S32_PINMUX(0, 0, 93, 0, 39, 3)
86 #define PTD0_EIRQ8                      NXP_S32_PINMUX(0, 0, 96, 0, 24, 3)
87 #define PTD1_EIRQ9                      NXP_S32_PINMUX(0, 0, 97, 0, 25, 3)
88 #define PTD2_EIRQ10                     NXP_S32_PINMUX(0, 0, 98, 0, 26, 3)
89 #define PTD3_EIRQ11                     NXP_S32_PINMUX(0, 0, 99, 0, 27, 3)
90 #define PTD4_EIRQ12                     NXP_S32_PINMUX(0, 0, 100, 0, 28, 3)
91 #define PTD5_EIRQ13                     NXP_S32_PINMUX(0, 0, 101, 0, 29, 3)
92 #define PTD6_EIRQ14                     NXP_S32_PINMUX(0, 0, 102, 0, 30, 3)
93 #define PTD7_EIRQ15                     NXP_S32_PINMUX(0, 0, 103, 0, 31, 3)
94 #define PTD8_EIRQ24                     NXP_S32_PINMUX(0, 0, 104, 0, 40, 2)
95 #define PTD9_EIRQ25                     NXP_S32_PINMUX(0, 0, 105, 0, 41, 2)
96 #define PTD10_EIRQ26                    NXP_S32_PINMUX(0, 0, 106, 0, 42, 2)
97 #define PTD11_EIRQ27                    NXP_S32_PINMUX(0, 0, 107, 0, 43, 2)
98 #define PTD12_EIRQ28                    NXP_S32_PINMUX(0, 0, 108, 0, 44, 2)
99 #define PTD13_EIRQ29                    NXP_S32_PINMUX(0, 0, 109, 0, 45, 2)
100 #define PTD14_EIRQ30                    NXP_S32_PINMUX(0, 0, 110, 0, 46, 3)
101 #define PTD15_EIRQ31                    NXP_S32_PINMUX(0, 0, 111, 0, 47, 2)
102 #define PTD17_EIRQ24                    NXP_S32_PINMUX(0, 0, 113, 0, 40, 3)
103 #define PTD20_EIRQ25                    NXP_S32_PINMUX(0, 0, 116, 0, 41, 3)
104 #define PTD21_EIRQ26                    NXP_S32_PINMUX(0, 0, 117, 0, 42, 3)
105 #define PTD22_EIRQ27                    NXP_S32_PINMUX(0, 0, 118, 0, 43, 3)
106 #define PTD23_EIRQ28                    NXP_S32_PINMUX(0, 0, 119, 0, 44, 3)
107 #define PTD24_EIRQ29                    NXP_S32_PINMUX(0, 0, 120, 0, 45, 3)
108 #define PTD27_EIRQ30                    NXP_S32_PINMUX(0, 0, 123, 0, 46, 2)
109 #define PTD28_EIRQ31                    NXP_S32_PINMUX(0, 0, 124, 0, 47, 3)
110 #define PTE0_EIRQ0                      NXP_S32_PINMUX(0, 0, 128, 0, 16, 4)
111 #define PTE1_EIRQ1                      NXP_S32_PINMUX(0, 0, 129, 0, 17, 4)
112 #define PTE2_EIRQ2                      NXP_S32_PINMUX(0, 0, 130, 0, 18, 4)
113 #define PTE3_EIRQ3                      NXP_S32_PINMUX(0, 0, 131, 0, 19, 4)
114 #define PTE4_EIRQ4                      NXP_S32_PINMUX(0, 0, 132, 0, 20, 4)
115 #define PTE5_EIRQ5                      NXP_S32_PINMUX(0, 0, 133, 0, 21, 4)
116 #define PTE6_EIRQ6                      NXP_S32_PINMUX(0, 0, 134, 0, 22, 4)
117 #define PTE8_EIRQ7                      NXP_S32_PINMUX(0, 0, 136, 0, 23, 4)
118 #define PTE9_EIRQ8                      NXP_S32_PINMUX(0, 0, 137, 0, 24, 4)
119 #define PTE10_EIRQ9                     NXP_S32_PINMUX(0, 0, 138, 0, 25, 4)
120 #define PTE11_EIRQ10                    NXP_S32_PINMUX(0, 0, 139, 0, 26, 4)
121 #define PTE12_EIRQ11                    NXP_S32_PINMUX(0, 0, 140, 0, 27, 4)
122 #define PTE13_EIRQ12                    NXP_S32_PINMUX(0, 0, 141, 0, 28, 4)
123 #define PTE14_EIRQ13                    NXP_S32_PINMUX(0, 0, 142, 0, 29, 4)
124 #define PTE15_EIRQ14                    NXP_S32_PINMUX(0, 0, 143, 0, 30, 4)
125 #define PTE16_EIRQ15                    NXP_S32_PINMUX(0, 0, 144, 0, 31, 4)
126 
127 /* LPSPI4 */
128 #define PTA0_LPSPI4_PCS2_O              NXP_S32_PINMUX(0, 0, 0, 1, 0, 0)
129 #define PTA0_LPSPI4_PCS2_I              NXP_S32_PINMUX(0, 0, 0, 0, 257, 1)
130 #define PTA1_LPSPI4_PCS1_O              NXP_S32_PINMUX(0, 0, 1, 1, 0, 0)
131 #define PTA1_LPSPI4_PCS1_I              NXP_S32_PINMUX(0, 0, 1, 0, 256, 1)
132 #define PTA16_LPSPI4_PCS3_O             NXP_S32_PINMUX(0, 0, 16, 1, 0, 0)
133 #define PTA16_LPSPI4_PCS3_I             NXP_S32_PINMUX(0, 0, 16, 0, 258, 1)
134 #define PTB8_LPSPI4_PCS0_O              NXP_S32_PINMUX(0, 0, 40, 1, 0, 0)
135 #define PTB8_LPSPI4_PCS0_I              NXP_S32_PINMUX(0, 0, 40, 0, 255, 2)
136 #define PTB9_LPSPI4_SOUT_O              NXP_S32_PINMUX(0, 0, 41, 1, 0, 0)
137 #define PTB9_LPSPI4_SOUT_I              NXP_S32_PINMUX(0, 0, 41, 0, 261, 2)
138 #define PTB10_LPSPI4_SCK_O              NXP_S32_PINMUX(0, 0, 42, 1, 0, 0)
139 #define PTB10_LPSPI4_SCK_I              NXP_S32_PINMUX(0, 0, 42, 0, 259, 2)
140 #define PTB11_LPSPI4_SIN_O              NXP_S32_PINMUX(0, 0, 43, 1, 0, 0)
141 #define PTB11_LPSPI4_SIN_I              NXP_S32_PINMUX(0, 0, 43, 0, 260, 2)
142 #define PTC10_LPSPI4_PCS0_O             NXP_S32_PINMUX(0, 0, 74, 5, 0, 0)
143 #define PTC10_LPSPI4_PCS0_I             NXP_S32_PINMUX(0, 0, 74, 0, 255, 1)
144 #define PTC11_LPSPI4_SOUT_O             NXP_S32_PINMUX(0, 0, 75, 5, 0, 0)
145 #define PTC11_LPSPI4_SOUT_I             NXP_S32_PINMUX(0, 0, 75, 0, 261, 1)
146 #define PTC25_LPSPI4_PCS1_O             NXP_S32_PINMUX(0, 0, 89, 5, 0, 0)
147 #define PTC25_LPSPI4_PCS1_I             NXP_S32_PINMUX(0, 0, 89, 0, 256, 4)
148 #define PTC26_LPSPI4_SIN_O              NXP_S32_PINMUX(0, 0, 90, 7, 0, 0)
149 #define PTC26_LPSPI4_SIN_I              NXP_S32_PINMUX(0, 0, 90, 0, 260, 1)
150 #define PTC27_LPSPI4_SCK_O              NXP_S32_PINMUX(0, 0, 91, 7, 0, 0)
151 #define PTC27_LPSPI4_SCK_I              NXP_S32_PINMUX(0, 0, 91, 0, 259, 1)
152 #define PTE21_LPSPI4_SIN_O              NXP_S32_PINMUX(0, 0, 149, 6, 0, 0)
153 #define PTE21_LPSPI4_SIN_I              NXP_S32_PINMUX(0, 0, 149, 0, 260, 3)
154 #define PTE22_LPSPI4_SCK_O              NXP_S32_PINMUX(0, 0, 150, 6, 0, 0)
155 #define PTE22_LPSPI4_SCK_I              NXP_S32_PINMUX(0, 0, 150, 0, 259, 3)
156 #define PTE23_LPSPI4_PCS0_O             NXP_S32_PINMUX(0, 0, 151, 6, 0, 0)
157 #define PTE23_LPSPI4_PCS0_I             NXP_S32_PINMUX(0, 0, 151, 0, 255, 4)
158 #define PTE24_LPSPI4_PCS1_O             NXP_S32_PINMUX(0, 0, 152, 6, 0, 0)
159 #define PTE24_LPSPI4_PCS1_I             NXP_S32_PINMUX(0, 0, 152, 0, 256, 3)
160 #define PTE25_LPSPI4_SOUT_O             NXP_S32_PINMUX(0, 0, 153, 6, 0, 0)
161 #define PTE25_LPSPI4_SOUT_I             NXP_S32_PINMUX(0, 0, 153, 0, 261, 3)
162 
163 /* EMIOS_0 */
164 #define PTA0_EMIOS_0_CH17_Y_O           NXP_S32_PINMUX(0, 0, 0, 2, 0, 0)
165 #define PTA0_EMIOS_0_CH17_Y_I           NXP_S32_PINMUX(0, 0, 0, 0, 65, 2)
166 #define PTA1_EMIOS_0_CH9_H_O            NXP_S32_PINMUX(0, 0, 1, 2, 0, 0)
167 #define PTA1_EMIOS_0_CH9_H_I            NXP_S32_PINMUX(0, 0, 1, 0, 57, 1)
168 #define PTA10_EMIOS_0_CH12_H_O          NXP_S32_PINMUX(0, 0, 10, 2, 0, 0)
169 #define PTA10_EMIOS_0_CH12_H_I          NXP_S32_PINMUX(0, 0, 10, 0, 60, 2)
170 #define PTA11_EMIOS_0_CH13_H_O          NXP_S32_PINMUX(0, 0, 11, 2, 0, 0)
171 #define PTA11_EMIOS_0_CH13_H_I          NXP_S32_PINMUX(0, 0, 11, 0, 61, 1)
172 #define PTA12_EMIOS_0_CH14_H_O          NXP_S32_PINMUX(0, 0, 12, 2, 0, 0)
173 #define PTA12_EMIOS_0_CH14_H_I          NXP_S32_PINMUX(0, 0, 12, 0, 62, 1)
174 #define PTA13_EMIOS_0_CH15_H_O          NXP_S32_PINMUX(0, 0, 13, 2, 0, 0)
175 #define PTA13_EMIOS_0_CH15_H_I          NXP_S32_PINMUX(0, 0, 13, 0, 63, 2)
176 #define PTA15_EMIOS_0_CH10_H_O          NXP_S32_PINMUX(0, 0, 15, 2, 0, 0)
177 #define PTA15_EMIOS_0_CH10_H_I          NXP_S32_PINMUX(0, 0, 15, 0, 58, 2)
178 #define PTA16_EMIOS_0_CH11_H_O          NXP_S32_PINMUX(0, 0, 16, 2, 0, 0)
179 #define PTA16_EMIOS_0_CH11_H_I          NXP_S32_PINMUX(0, 0, 16, 0, 59, 2)
180 #define PTA17_EMIOS_0_CH6_G_O           NXP_S32_PINMUX(0, 0, 17, 2, 0, 0)
181 #define PTA17_EMIOS_0_CH6_G_I           NXP_S32_PINMUX(0, 0, 17, 0, 54, 2)
182 #define PTB0_EMIOS_0_CH3_G_O            NXP_S32_PINMUX(0, 0, 32, 4, 0, 0)
183 #define PTB0_EMIOS_0_CH3_G_I            NXP_S32_PINMUX(0, 0, 32, 0, 51, 4)
184 #define PTB1_EMIOS_0_CH7_G_O            NXP_S32_PINMUX(0, 0, 33, 4, 0, 0)
185 #define PTB1_EMIOS_0_CH7_G_I            NXP_S32_PINMUX(0, 0, 33, 0, 55, 3)
186 #define PTB2_EMIOS_0_CH8_X_O            NXP_S32_PINMUX(0, 0, 34, 2, 0, 0)
187 #define PTB2_EMIOS_0_CH8_X_I            NXP_S32_PINMUX(0, 0, 34, 0, 56, 1)
188 #define PTB3_EMIOS_0_CH9_H_O            NXP_S32_PINMUX(0, 0, 35, 2, 0, 0)
189 #define PTB3_EMIOS_0_CH9_H_I            NXP_S32_PINMUX(0, 0, 35, 0, 57, 2)
190 #define PTB4_EMIOS_0_CH4_G_O            NXP_S32_PINMUX(0, 0, 36, 2, 0, 0)
191 #define PTB4_EMIOS_0_CH4_G_I            NXP_S32_PINMUX(0, 0, 36, 0, 52, 1)
192 #define PTB5_EMIOS_0_CH5_G_O            NXP_S32_PINMUX(0, 0, 37, 2, 0, 0)
193 #define PTB5_EMIOS_0_CH5_G_I            NXP_S32_PINMUX(0, 0, 37, 0, 53, 1)
194 #define PTB12_EMIOS_0_CH0_X_O           NXP_S32_PINMUX(0, 0, 44, 2, 0, 0)
195 #define PTB12_EMIOS_0_CH0_X_I           NXP_S32_PINMUX(0, 0, 44, 0, 48, 1)
196 #define PTB13_EMIOS_0_CH1_G_O           NXP_S32_PINMUX(0, 0, 45, 2, 0, 0)
197 #define PTB13_EMIOS_0_CH1_G_I           NXP_S32_PINMUX(0, 0, 45, 0, 49, 2)
198 #define PTB14_EMIOS_0_CH2_G_O           NXP_S32_PINMUX(0, 0, 46, 2, 0, 0)
199 #define PTB14_EMIOS_0_CH2_G_I           NXP_S32_PINMUX(0, 0, 46, 0, 50, 3)
200 #define PTB15_EMIOS_0_CH3_G_O           NXP_S32_PINMUX(0, 0, 47, 2, 0, 0)
201 #define PTB15_EMIOS_0_CH3_G_I           NXP_S32_PINMUX(0, 0, 47, 0, 51, 1)
202 #define PTB16_EMIOS_0_CH4_G_O           NXP_S32_PINMUX(0, 0, 48, 2, 0, 0)
203 #define PTB16_EMIOS_0_CH4_G_I           NXP_S32_PINMUX(0, 0, 48, 0, 52, 2)
204 #define PTB17_EMIOS_0_CH5_G_O           NXP_S32_PINMUX(0, 0, 49, 2, 0, 0)
205 #define PTB17_EMIOS_0_CH5_G_I           NXP_S32_PINMUX(0, 0, 49, 0, 53, 2)
206 #define PTC0_EMIOS_0_CH0_X_O            NXP_S32_PINMUX(0, 0, 64, 2, 0, 0)
207 #define PTC0_EMIOS_0_CH14_H_O           NXP_S32_PINMUX(0, 0, 64, 6, 0, 0)
208 #define PTC0_EMIOS_0_CH0_X_I            NXP_S32_PINMUX(0, 0, 64, 0, 48, 3)
209 #define PTC0_EMIOS_0_CH14_H_I           NXP_S32_PINMUX(0, 0, 64, 0, 62, 2)
210 #define PTC1_EMIOS_0_CH1_G_O            NXP_S32_PINMUX(0, 0, 65, 2, 0, 0)
211 #define PTC1_EMIOS_0_CH15_H_O           NXP_S32_PINMUX(0, 0, 65, 6, 0, 0)
212 #define PTC1_EMIOS_0_CH1_G_I            NXP_S32_PINMUX(0, 0, 65, 0, 49, 1)
213 #define PTC1_EMIOS_0_CH15_H_I           NXP_S32_PINMUX(0, 0, 65, 0, 63, 1)
214 #define PTC2_EMIOS_0_CH2_G_O            NXP_S32_PINMUX(0, 0, 66, 2, 0, 0)
215 #define PTC2_EMIOS_0_CH2_G_I            NXP_S32_PINMUX(0, 0, 66, 0, 50, 2)
216 #define PTC3_EMIOS_0_CH3_G_O            NXP_S32_PINMUX(0, 0, 67, 2, 0, 0)
217 #define PTC3_EMIOS_0_CH3_G_I            NXP_S32_PINMUX(0, 0, 67, 0, 51, 3)
218 #define PTC4_EMIOS_0_CH8_X_O            NXP_S32_PINMUX(0, 0, 68, 2, 0, 0)
219 #define PTC4_EMIOS_0_CH8_X_I            NXP_S32_PINMUX(0, 0, 68, 0, 56, 2)
220 #define PTC5_EMIOS_0_CH16_X_O           NXP_S32_PINMUX(0, 0, 69, 2, 0, 0)
221 #define PTC5_EMIOS_0_CH16_X_I           NXP_S32_PINMUX(0, 0, 69, 0, 64, 2)
222 #define PTC10_EMIOS_0_CH6_G_O           NXP_S32_PINMUX(0, 0, 74, 1, 0, 0)
223 #define PTC10_EMIOS_0_CH6_G_I           NXP_S32_PINMUX(0, 0, 74, 0, 54, 4)
224 #define PTC12_EMIOS_0_CH22_X_O          NXP_S32_PINMUX(0, 0, 76, 3, 0, 0)
225 #define PTC12_EMIOS_0_CH22_X_I          NXP_S32_PINMUX(0, 0, 76, 0, 70, 2)
226 #define PTC13_EMIOS_0_CH23_X_O          NXP_S32_PINMUX(0, 0, 77, 3, 0, 0)
227 #define PTC13_EMIOS_0_CH23_X_I          NXP_S32_PINMUX(0, 0, 77, 0, 71, 1)
228 #define PTC14_EMIOS_0_CH10_H_O          NXP_S32_PINMUX(0, 0, 78, 2, 0, 0)
229 #define PTC14_EMIOS_0_CH10_H_I          NXP_S32_PINMUX(0, 0, 78, 0, 58, 1)
230 #define PTC15_EMIOS_0_CH11_H_O          NXP_S32_PINMUX(0, 0, 79, 2, 0, 0)
231 #define PTC15_EMIOS_0_CH11_H_I          NXP_S32_PINMUX(0, 0, 79, 0, 59, 1)
232 #define PTD0_EMIOS_0_CH2_G_O            NXP_S32_PINMUX(0, 0, 96, 2, 0, 0)
233 #define PTD0_EMIOS_0_CH16_X_O           NXP_S32_PINMUX(0, 0, 96, 4, 0, 0)
234 #define PTD0_EMIOS_0_CH2_G_I            NXP_S32_PINMUX(0, 0, 96, 0, 50, 1)
235 #define PTD0_EMIOS_0_CH16_X_I           NXP_S32_PINMUX(0, 0, 96, 0, 64, 1)
236 #define PTD1_EMIOS_0_CH3_G_O            NXP_S32_PINMUX(0, 0, 97, 2, 0, 0)
237 #define PTD1_EMIOS_0_CH17_Y_O           NXP_S32_PINMUX(0, 0, 97, 4, 0, 0)
238 #define PTD1_EMIOS_0_CH3_G_I            NXP_S32_PINMUX(0, 0, 97, 0, 51, 2)
239 #define PTD1_EMIOS_0_CH17_Y_I           NXP_S32_PINMUX(0, 0, 97, 0, 65, 1)
240 #define PTD5_EMIOS_0_CH19_Y_O           NXP_S32_PINMUX(0, 0, 101, 2, 0, 0)
241 #define PTD5_EMIOS_0_CH2_G_O            NXP_S32_PINMUX(0, 0, 101, 3, 0, 0)
242 #define PTD5_EMIOS_0_CH2_G_I            NXP_S32_PINMUX(0, 0, 101, 0, 50, 4)
243 #define PTD5_EMIOS_0_CH19_Y_I           NXP_S32_PINMUX(0, 0, 101, 0, 67, 2)
244 #define PTD8_EMIOS_0_CH12_H_O           NXP_S32_PINMUX(0, 0, 104, 6, 0, 0)
245 #define PTD8_EMIOS_0_CH12_H_I           NXP_S32_PINMUX(0, 0, 104, 0, 60, 1)
246 #define PTD9_EMIOS_0_CH13_H_O           NXP_S32_PINMUX(0, 0, 105, 6, 0, 0)
247 #define PTD9_EMIOS_0_CH13_H_I           NXP_S32_PINMUX(0, 0, 105, 0, 61, 2)
248 #define PTD10_EMIOS_0_CH16_X_O          NXP_S32_PINMUX(0, 0, 106, 2, 0, 0)
249 #define PTD10_EMIOS_0_CH16_X_I          NXP_S32_PINMUX(0, 0, 106, 0, 64, 3)
250 #define PTD11_EMIOS_0_CH17_Y_O          NXP_S32_PINMUX(0, 0, 107, 2, 0, 0)
251 #define PTD11_EMIOS_0_CH17_Y_I          NXP_S32_PINMUX(0, 0, 107, 0, 65, 3)
252 #define PTD12_EMIOS_0_CH18_Y_O          NXP_S32_PINMUX(0, 0, 108, 2, 0, 0)
253 #define PTD12_EMIOS_0_CH18_Y_I          NXP_S32_PINMUX(0, 0, 108, 0, 66, 1)
254 #define PTD13_EMIOS_0_CH20_Y_O          NXP_S32_PINMUX(0, 0, 109, 2, 0, 0)
255 #define PTD13_EMIOS_0_CH20_Y_I          NXP_S32_PINMUX(0, 0, 109, 0, 68, 1)
256 #define PTD14_EMIOS_0_CH21_Y_O          NXP_S32_PINMUX(0, 0, 110, 2, 0, 0)
257 #define PTD14_EMIOS_0_CH21_Y_I          NXP_S32_PINMUX(0, 0, 110, 0, 69, 1)
258 #define PTD15_EMIOS_0_CH0_X_O           NXP_S32_PINMUX(0, 0, 111, 2, 0, 0)
259 #define PTD15_EMIOS_0_CH0_X_I           NXP_S32_PINMUX(0, 0, 111, 0, 48, 2)
260 #define PTD16_EMIOS_0_CH1_G_O           NXP_S32_PINMUX(0, 0, 112, 2, 0, 0)
261 #define PTD16_EMIOS_0_CH1_G_I           NXP_S32_PINMUX(0, 0, 112, 0, 49, 3)
262 #define PTD17_EMIOS_0_CH18_Y_O          NXP_S32_PINMUX(0, 0, 113, 2, 0, 0)
263 #define PTD17_EMIOS_0_CH18_Y_I          NXP_S32_PINMUX(0, 0, 113, 0, 66, 3)
264 #define PTE2_EMIOS_0_CH3_G_O            NXP_S32_PINMUX(0, 0, 130, 3, 0, 0)
265 #define PTE2_EMIOS_0_CH3_G_I            NXP_S32_PINMUX(0, 0, 130, 0, 51, 5)
266 #define PTE3_EMIOS_0_CH19_Y_O           NXP_S32_PINMUX(0, 0, 131, 3, 0, 0)
267 #define PTE3_EMIOS_0_CH19_Y_I           NXP_S32_PINMUX(0, 0, 131, 0, 67, 4)
268 #define PTE4_EMIOS_0_CH18_Y_O           NXP_S32_PINMUX(0, 0, 132, 4, 0, 0)
269 #define PTE4_EMIOS_0_CH18_Y_I           NXP_S32_PINMUX(0, 0, 132, 0, 66, 2)
270 #define PTE5_EMIOS_0_CH19_Y_O           NXP_S32_PINMUX(0, 0, 133, 4, 0, 0)
271 #define PTE5_EMIOS_0_CH19_Y_I           NXP_S32_PINMUX(0, 0, 133, 0, 67, 1)
272 #define PTE7_EMIOS_0_CH7_G_O            NXP_S32_PINMUX(0, 0, 135, 2, 0, 0)
273 #define PTE7_EMIOS_0_CH7_G_I            NXP_S32_PINMUX(0, 0, 135, 0, 55, 2)
274 #define PTE8_EMIOS_0_CH6_G_O            NXP_S32_PINMUX(0, 0, 136, 2, 0, 0)
275 #define PTE8_EMIOS_0_CH6_G_I            NXP_S32_PINMUX(0, 0, 136, 0, 54, 1)
276 #define PTE9_EMIOS_0_CH7_G_O            NXP_S32_PINMUX(0, 0, 137, 2, 0, 0)
277 #define PTE9_EMIOS_0_CH7_G_I            NXP_S32_PINMUX(0, 0, 137, 0, 55, 1)
278 #define PTE10_EMIOS_0_CH20_Y_O          NXP_S32_PINMUX(0, 0, 138, 4, 0, 0)
279 #define PTE10_EMIOS_0_CH20_Y_I          NXP_S32_PINMUX(0, 0, 138, 0, 68, 2)
280 #define PTE11_EMIOS_0_CH1_G_O           NXP_S32_PINMUX(0, 0, 139, 3, 0, 0)
281 #define PTE11_EMIOS_0_CH21_Y_O          NXP_S32_PINMUX(0, 0, 139, 4, 0, 0)
282 #define PTE11_EMIOS_0_CH1_G_I           NXP_S32_PINMUX(0, 0, 139, 0, 49, 4)
283 #define PTE11_EMIOS_0_CH21_Y_I          NXP_S32_PINMUX(0, 0, 139, 0, 69, 2)
284 #define PTE14_EMIOS_0_CH19_Y_O          NXP_S32_PINMUX(0, 0, 142, 1, 0, 0)
285 #define PTE14_EMIOS_0_CH19_Y_I          NXP_S32_PINMUX(0, 0, 142, 0, 67, 3)
286 #define PTE15_EMIOS_0_CH22_X_O          NXP_S32_PINMUX(0, 0, 143, 4, 0, 0)
287 #define PTE15_EMIOS_0_CH22_X_I          NXP_S32_PINMUX(0, 0, 143, 0, 70, 1)
288 #define PTE16_EMIOS_0_CH23_X_O          NXP_S32_PINMUX(0, 0, 144, 4, 0, 0)
289 #define PTE16_EMIOS_0_CH23_X_I          NXP_S32_PINMUX(0, 0, 144, 0, 71, 2)
290 
291 /* LCU0 */
292 #define PTA0_LCU0_OUT4                  NXP_S32_PINMUX(0, 0, 0, 3, 0, 0)
293 #define PTA1_LCU0_OUT5                  NXP_S32_PINMUX(0, 0, 1, 5, 0, 0)
294 #define PTA2_LCU0_OUT3                  NXP_S32_PINMUX(0, 0, 2, 6, 0, 0)
295 #define PTA3_LCU0_OUT2                  NXP_S32_PINMUX(0, 0, 3, 4, 0, 0)
296 #define PTB8_LCU0_OUT11                 NXP_S32_PINMUX(0, 0, 40, 5, 0, 0)
297 #define PTB9_LCU0_OUT10                 NXP_S32_PINMUX(0, 0, 41, 6, 0, 0)
298 #define PTB10_LCU0_OUT9                 NXP_S32_PINMUX(0, 0, 42, 6, 0, 0)
299 #define PTB11_LCU0_OUT8                 NXP_S32_PINMUX(0, 0, 43, 5, 0, 0)
300 #define PTB12_LCU0_OUT2                 NXP_S32_PINMUX(0, 0, 44, 6, 0, 0)
301 #define PTB13_LCU0_OUT3                 NXP_S32_PINMUX(0, 0, 45, 5, 0, 0)
302 #define PTB14_LCU0_OUT7                 NXP_S32_PINMUX(0, 0, 46, 4, 0, 0)
303 #define PTC6_LCU0_OUT7                  NXP_S32_PINMUX(0, 0, 70, 4, 0, 0)
304 #define PTC7_LCU0_OUT6                  NXP_S32_PINMUX(0, 0, 71, 4, 0, 0)
305 #define PTD2_LCU0_OUT1                  NXP_S32_PINMUX(0, 0, 98, 1, 0, 0)
306 #define PTD3_LCU0_OUT0                  NXP_S32_PINMUX(0, 0, 99, 6, 0, 0)
307 #define PTD4_LCU0_OUT6                  NXP_S32_PINMUX(0, 0, 100, 5, 0, 0)
308 #define PTD21_LCU0_OUT4                 NXP_S32_PINMUX(0, 0, 117, 5, 0, 0)
309 #define PTD22_LCU0_OUT5                 NXP_S32_PINMUX(0, 0, 118, 6, 0, 0)
310 #define PTD23_LCU0_OUT10                NXP_S32_PINMUX(0, 0, 119, 6, 0, 0)
311 #define PTD24_LCU0_OUT11                NXP_S32_PINMUX(0, 0, 120, 6, 0, 0)
312 #define PTD26_LCU0_OUT0                 NXP_S32_PINMUX(0, 0, 122, 7, 0, 0)
313 #define PTD27_LCU0_OUT1                 NXP_S32_PINMUX(0, 0, 123, 7, 0, 0)
314 #define PTD28_LCU0_OUT2                 NXP_S32_PINMUX(0, 0, 124, 5, 0, 0)
315 #define PTD29_LCU0_OUT3                 NXP_S32_PINMUX(0, 0, 125, 5, 0, 0)
316 #define PTD30_LCU0_OUT8                 NXP_S32_PINMUX(0, 0, 126, 5, 0, 0)
317 #define PTD31_LCU0_OUT9                 NXP_S32_PINMUX(0, 0, 127, 5, 0, 0)
318 
319 /* FXIO */
320 #define PTA0_FXIO_D2_O                  NXP_S32_PINMUX(0, 0, 0, 4, 0, 0)
321 #define PTA0_FXIO_D2_I                  NXP_S32_PINMUX(0, 0, 0, 0, 154, 2)
322 #define PTA1_FXIO_D3_O                  NXP_S32_PINMUX(0, 0, 1, 4, 0, 0)
323 #define PTA1_FXIO_D3_I                  NXP_S32_PINMUX(0, 0, 1, 0, 155, 1)
324 #define PTA2_FXIO_D4_O                  NXP_S32_PINMUX(0, 0, 2, 5, 0, 0)
325 #define PTA2_FXIO_D4_I                  NXP_S32_PINMUX(0, 0, 2, 0, 156, 3)
326 #define PTA3_FXIO_D5_O                  NXP_S32_PINMUX(0, 0, 3, 5, 0, 0)
327 #define PTA3_FXIO_D5_I                  NXP_S32_PINMUX(0, 0, 3, 0, 157, 3)
328 #define PTA4_FXIO_D6_O                  NXP_S32_PINMUX(0, 0, 4, 3, 0, 0)
329 #define PTA4_FXIO_D6_I                  NXP_S32_PINMUX(0, 0, 4, 0, 158, 8)
330 #define PTA6_FXIO_D19_O                 NXP_S32_PINMUX(0, 0, 6, 5, 0, 0)
331 #define PTA6_FXIO_D19_I                 NXP_S32_PINMUX(0, 0, 6, 0, 171, 4)
332 #define PTA7_FXIO_D9_O                  NXP_S32_PINMUX(0, 0, 7, 6, 0, 0)
333 #define PTA7_FXIO_D9_I                  NXP_S32_PINMUX(0, 0, 7, 0, 161, 3)
334 #define PTA8_FXIO_D6_O                  NXP_S32_PINMUX(0, 0, 8, 4, 0, 0)
335 #define PTA8_FXIO_D6_I                  NXP_S32_PINMUX(0, 0, 8, 0, 158, 2)
336 #define PTA9_FXIO_D7_O                  NXP_S32_PINMUX(0, 0, 9, 4, 0, 0)
337 #define PTA9_FXIO_D7_I                  NXP_S32_PINMUX(0, 0, 9, 0, 159, 2)
338 #define PTA10_FXIO_D0_O                 NXP_S32_PINMUX(0, 0, 10, 4, 0, 0)
339 #define PTA10_FXIO_D0_I                 NXP_S32_PINMUX(0, 0, 10, 0, 152, 2)
340 #define PTA11_FXIO_D1_O                 NXP_S32_PINMUX(0, 0, 11, 4, 0, 0)
341 #define PTA11_FXIO_D1_I                 NXP_S32_PINMUX(0, 0, 11, 0, 153, 2)
342 #define PTA12_FXIO_D9_O                 NXP_S32_PINMUX(0, 0, 12, 5, 0, 0)
343 #define PTA12_FXIO_D9_I                 NXP_S32_PINMUX(0, 0, 12, 0, 161, 4)
344 #define PTA13_FXIO_D8_O                 NXP_S32_PINMUX(0, 0, 13, 5, 0, 0)
345 #define PTA13_FXIO_D8_I                 NXP_S32_PINMUX(0, 0, 13, 0, 160, 4)
346 #define PTA14_FXIO_D14_O                NXP_S32_PINMUX(0, 0, 14, 6, 0, 0)
347 #define PTA14_FXIO_D14_I                NXP_S32_PINMUX(0, 0, 14, 0, 166, 4)
348 #define PTA15_FXIO_D31_O                NXP_S32_PINMUX(0, 0, 15, 7, 0, 0)
349 #define PTA15_FXIO_D31_I                NXP_S32_PINMUX(0, 0, 15, 0, 183, 1)
350 #define PTA16_FXIO_D30_O                NXP_S32_PINMUX(0, 0, 16, 7, 0, 0)
351 #define PTA16_FXIO_D30_I                NXP_S32_PINMUX(0, 0, 16, 0, 182, 1)
352 #define PTA17_FXIO_D19_O                NXP_S32_PINMUX(0, 0, 17, 7, 0, 0)
353 #define PTA17_FXIO_D19_I                NXP_S32_PINMUX(0, 0, 17, 0, 171, 1)
354 #define PTA21_FXIO_D0_O                 NXP_S32_PINMUX(0, 0, 21, 3, 0, 0)
355 #define PTA21_FXIO_D0_I                 NXP_S32_PINMUX(0, 0, 21, 0, 152, 3)
356 #define PTA24_FXIO_D3                   NXP_S32_PINMUX(0, 0, 23, 0, 155, 3)
357 #define PTA25_FXIO_D2                   NXP_S32_PINMUX(0, 0, 23, 0, 154, 6)
358 #define PTA27_FXIO_D5_O                 NXP_S32_PINMUX(0, 0, 27, 1, 0, 0)
359 #define PTA27_FXIO_D5_I                 NXP_S32_PINMUX(0, 0, 27, 0, 157, 9)
360 #define PTA31_FXIO_D0_O                 NXP_S32_PINMUX(0, 0, 31, 3, 0, 0)
361 #define PTA31_FXIO_D0_I                 NXP_S32_PINMUX(0, 0, 31, 0, 152, 6)
362 #define PTB0_FXIO_D14_O                 NXP_S32_PINMUX(0, 0, 32, 2, 0, 0)
363 #define PTB0_FXIO_D14_I                 NXP_S32_PINMUX(0, 0, 32, 0, 166, 3)
364 #define PTB2_FXIO_D18_O                 NXP_S32_PINMUX(0, 0, 34, 7, 0, 0)
365 #define PTB2_FXIO_D18_I                 NXP_S32_PINMUX(0, 0, 34, 0, 170, 1)
366 #define PTB3_FXIO_D17_O                 NXP_S32_PINMUX(0, 0, 35, 7, 0, 0)
367 #define PTB3_FXIO_D17_I                 NXP_S32_PINMUX(0, 0, 35, 0, 169, 1)
368 #define PTB8_FXIO_D29_O                 NXP_S32_PINMUX(0, 0, 40, 7, 0, 0)
369 #define PTB8_FXIO_D29_I                 NXP_S32_PINMUX(0, 0, 40, 0, 181, 1)
370 #define PTB9_FXIO_D28_O                 NXP_S32_PINMUX(0, 0, 41, 7, 0, 0)
371 #define PTB9_FXIO_D28_I                 NXP_S32_PINMUX(0, 0, 41, 0, 180, 1)
372 #define PTB10_FXIO_D27_O                NXP_S32_PINMUX(0, 0, 42, 7, 0, 0)
373 #define PTB10_FXIO_D27_I                NXP_S32_PINMUX(0, 0, 42, 0, 179, 1)
374 #define PTB11_FXIO_D26_O                NXP_S32_PINMUX(0, 0, 43, 7, 0, 0)
375 #define PTB11_FXIO_D26_I                NXP_S32_PINMUX(0, 0, 43, 0, 178, 1)
376 #define PTB12_FXIO_D25_O                NXP_S32_PINMUX(0, 0, 44, 7, 0, 0)
377 #define PTB12_FXIO_D25_I                NXP_S32_PINMUX(0, 0, 44, 0, 177, 1)
378 #define PTB13_FXIO_D8_O                 NXP_S32_PINMUX(0, 0, 45, 3, 0, 0)
379 #define PTB13_FXIO_D24_O                NXP_S32_PINMUX(0, 0, 45, 7, 0, 0)
380 #define PTB13_FXIO_D8_I                 NXP_S32_PINMUX(0, 0, 45, 0, 160, 3)
381 #define PTB13_FXIO_D24_I                NXP_S32_PINMUX(0, 0, 45, 0, 176, 1)
382 #define PTB14_FXIO_D23_O                NXP_S32_PINMUX(0, 0, 46, 7, 0, 0)
383 #define PTB14_FXIO_D23_I                NXP_S32_PINMUX(0, 0, 46, 0, 175, 1)
384 #define PTB15_FXIO_D22_O                NXP_S32_PINMUX(0, 0, 47, 7, 0, 0)
385 #define PTB15_FXIO_D22_I                NXP_S32_PINMUX(0, 0, 47, 0, 174, 1)
386 #define PTB16_FXIO_D21_O                NXP_S32_PINMUX(0, 0, 48, 7, 0, 0)
387 #define PTB16_FXIO_D21_I                NXP_S32_PINMUX(0, 0, 48, 0, 173, 1)
388 #define PTB17_FXIO_D20_O                NXP_S32_PINMUX(0, 0, 49, 7, 0, 0)
389 #define PTB17_FXIO_D20_I                NXP_S32_PINMUX(0, 0, 49, 0, 172, 1)
390 #define PTB18_FXIO_D1_O                 NXP_S32_PINMUX(0, 0, 50, 3, 0, 0)
391 #define PTB18_FXIO_D1_I                 NXP_S32_PINMUX(0, 0, 50, 0, 153, 6)
392 #define PTB19_FXIO_D2_O                 NXP_S32_PINMUX(0, 0, 51, 3, 0, 0)
393 #define PTB19_FXIO_D2_I                 NXP_S32_PINMUX(0, 0, 51, 0, 154, 5)
394 #define PTB20_FXIO_D3_O                 NXP_S32_PINMUX(0, 0, 52, 3, 0, 0)
395 #define PTB20_FXIO_D3_I                 NXP_S32_PINMUX(0, 0, 52, 0, 155, 5)
396 #define PTB21_FXIO_D4_O                 NXP_S32_PINMUX(0, 0, 53, 3, 0, 0)
397 #define PTB21_FXIO_D4_I                 NXP_S32_PINMUX(0, 0, 53, 0, 156, 5)
398 #define PTB22_FXIO_D15_O                NXP_S32_PINMUX(0, 0, 54, 6, 0, 0)
399 #define PTB22_FXIO_D15_I                NXP_S32_PINMUX(0, 0, 54, 0, 167, 5)
400 #define PTB23_FXIO_D4_O                 NXP_S32_PINMUX(0, 0, 55, 3, 0, 0)
401 #define PTB23_FXIO_D4_I                 NXP_S32_PINMUX(0, 0, 55, 0, 156, 6)
402 #define PTB24_FXIO_D5_O                 NXP_S32_PINMUX(0, 0, 56, 3, 0, 0)
403 #define PTB24_FXIO_D5_I                 NXP_S32_PINMUX(0, 0, 56, 0, 157, 6)
404 #define PTB25_FXIO_D6_O                 NXP_S32_PINMUX(0, 0, 57, 3, 0, 0)
405 #define PTB25_FXIO_D6_I                 NXP_S32_PINMUX(0, 0, 57, 0, 158, 5)
406 #define PTB26_FXIO_D7_O                 NXP_S32_PINMUX(0, 0, 58, 3, 0, 0)
407 #define PTB26_FXIO_D7_I                 NXP_S32_PINMUX(0, 0, 58, 0, 159, 6)
408 #define PTB27_FXIO_D8_O                 NXP_S32_PINMUX(0, 0, 59, 3, 0, 0)
409 #define PTB27_FXIO_D8_I                 NXP_S32_PINMUX(0, 0, 59, 0, 160, 2)
410 #define PTB28_FXIO_D9_O                 NXP_S32_PINMUX(0, 0, 60, 3, 0, 0)
411 #define PTB28_FXIO_D9_I                 NXP_S32_PINMUX(0, 0, 60, 0, 161, 2)
412 #define PTB29_FXIO_D10_O                NXP_S32_PINMUX(0, 0, 61, 3, 0, 0)
413 #define PTB29_FXIO_D10_I                NXP_S32_PINMUX(0, 0, 61, 0, 162, 2)
414 #define PTC1_FXIO_D5_O                  NXP_S32_PINMUX(0, 0, 65, 4, 0, 0)
415 #define PTC1_FXIO_D5_I                  NXP_S32_PINMUX(0, 0, 65, 0, 157, 7)
416 #define PTC4_FXIO_D5_O                  NXP_S32_PINMUX(0, 0, 68, 4, 0, 0)
417 #define PTC4_FXIO_D5_I                  NXP_S32_PINMUX(0, 0, 68, 0, 157, 8)
418 #define PTC5_FXIO_D4_O                  NXP_S32_PINMUX(0, 0, 69, 4, 0, 0)
419 #define PTC5_FXIO_D4_I                  NXP_S32_PINMUX(0, 0, 69, 0, 156, 7)
420 #define PTC6_FXIO_D11_O                 NXP_S32_PINMUX(0, 0, 70, 2, 0, 0)
421 #define PTC6_FXIO_D11_I                 NXP_S32_PINMUX(0, 0, 70, 0, 163, 3)
422 #define PTC7_FXIO_D10_O                 NXP_S32_PINMUX(0, 0, 71, 1, 0, 0)
423 #define PTC7_FXIO_D10_I                 NXP_S32_PINMUX(0, 0, 71, 0, 162, 3)
424 #define PTC8_FXIO_D12_O                 NXP_S32_PINMUX(0, 0, 72, 7, 0, 0)
425 #define PTC8_FXIO_D12_I                 NXP_S32_PINMUX(0, 0, 72, 0, 164, 3)
426 #define PTC9_FXIO_D13_O                 NXP_S32_PINMUX(0, 0, 73, 7, 0, 0)
427 #define PTC9_FXIO_D13_I                 NXP_S32_PINMUX(0, 0, 73, 0, 165, 3)
428 #define PTC11_FXIO_D15_O                NXP_S32_PINMUX(0, 0, 75, 4, 0, 0)
429 #define PTC11_FXIO_D19_O                NXP_S32_PINMUX(0, 0, 75, 6, 0, 0)
430 #define PTC11_FXIO_D15_I                NXP_S32_PINMUX(0, 0, 75, 0, 167, 3)
431 #define PTC11_FXIO_D19_I                NXP_S32_PINMUX(0, 0, 75, 0, 171, 3)
432 #define PTC12_FXIO_D19_O                NXP_S32_PINMUX(0, 0, 76, 5, 0, 0)
433 #define PTC12_FXIO_D19_I                NXP_S32_PINMUX(0, 0, 76, 0, 171, 5)
434 #define PTC13_FXIO_D16_O                NXP_S32_PINMUX(0, 0, 77, 5, 0, 0)
435 #define PTC13_FXIO_D16_I                NXP_S32_PINMUX(0, 0, 77, 0, 168, 3)
436 #define PTC14_FXIO_D16_O                NXP_S32_PINMUX(0, 0, 78, 7, 0, 0)
437 #define PTC14_FXIO_D16_I                NXP_S32_PINMUX(0, 0, 78, 0, 168, 1)
438 #define PTC16_FXIO_D15_O                NXP_S32_PINMUX(0, 0, 80, 6, 0, 0)
439 #define PTC16_FXIO_D15_I                NXP_S32_PINMUX(0, 0, 80, 0, 167, 1)
440 #define PTC17_FXIO_D14_O                NXP_S32_PINMUX(0, 0, 81, 6, 0, 0)
441 #define PTC17_FXIO_D14_I                NXP_S32_PINMUX(0, 0, 81, 0, 166, 1)
442 #define PTC18_FXIO_D6_O                 NXP_S32_PINMUX(0, 0, 82, 2, 0, 0)
443 #define PTC18_FXIO_D12_O                NXP_S32_PINMUX(0, 0, 82, 3, 0, 0)
444 #define PTC18_FXIO_D6_I                 NXP_S32_PINMUX(0, 0, 82, 0, 158, 9)
445 #define PTC18_FXIO_D12_I                NXP_S32_PINMUX(0, 0, 82, 0, 164, 2)
446 #define PTC19_FXIO_D13_O                NXP_S32_PINMUX(0, 0, 83, 3, 0, 0)
447 #define PTC19_FXIO_D13_I                NXP_S32_PINMUX(0, 0, 83, 0, 165, 2)
448 #define PTC20_FXIO_D14_O                NXP_S32_PINMUX(0, 0, 84, 3, 0, 0)
449 #define PTC20_FXIO_D14_I                NXP_S32_PINMUX(0, 0, 84, 0, 166, 2)
450 #define PTC21_FXIO_D15_O                NXP_S32_PINMUX(0, 0, 85, 3, 0, 0)
451 #define PTC21_FXIO_D15_I                NXP_S32_PINMUX(0, 0, 85, 0, 167, 2)
452 #define PTC23_FXIO_D16_O                NXP_S32_PINMUX(0, 0, 87, 3, 0, 0)
453 #define PTC23_FXIO_D16_I                NXP_S32_PINMUX(0, 0, 87, 0, 168, 2)
454 #define PTC24_FXIO_D17_O                NXP_S32_PINMUX(0, 0, 88, 3, 0, 0)
455 #define PTC24_FXIO_D17_I                NXP_S32_PINMUX(0, 0, 88, 0, 169, 2)
456 #define PTC25_FXIO_D18_O                NXP_S32_PINMUX(0, 0, 89, 3, 0, 0)
457 #define PTC25_FXIO_D18_I                NXP_S32_PINMUX(0, 0, 89, 0, 170, 2)
458 #define PTC26_FXIO_D19_O                NXP_S32_PINMUX(0, 0, 90, 3, 0, 0)
459 #define PTC26_FXIO_D19_I                NXP_S32_PINMUX(0, 0, 90, 0, 171, 2)
460 #define PTC27_FXIO_D20_O                NXP_S32_PINMUX(0, 0, 91, 3, 0, 0)
461 #define PTC27_FXIO_D20_I                NXP_S32_PINMUX(0, 0, 91, 0, 172, 2)
462 #define PTC28_FXIO_D21_O                NXP_S32_PINMUX(0, 0, 92, 3, 0, 0)
463 #define PTC28_FXIO_D2_O                 NXP_S32_PINMUX(0, 0, 92, 4, 0, 0)
464 #define PTC28_FXIO_D2_I                 NXP_S32_PINMUX(0, 0, 92, 0, 154, 7)
465 #define PTC28_FXIO_D21_I                NXP_S32_PINMUX(0, 0, 92, 0, 173, 2)
466 #define PTC29_FXIO_D22_O                NXP_S32_PINMUX(0, 0, 93, 3, 0, 0)
467 #define PTC29_FXIO_D3_O                 NXP_S32_PINMUX(0, 0, 93, 7, 0, 0)
468 #define PTC29_FXIO_D3_I                 NXP_S32_PINMUX(0, 0, 93, 0, 155, 6)
469 #define PTC29_FXIO_D22_I                NXP_S32_PINMUX(0, 0, 93, 0, 174, 2)
470 #define PTC30_FXIO_D0_O                 NXP_S32_PINMUX(0, 0, 94, 3, 0, 0)
471 #define PTC30_FXIO_D23_O                NXP_S32_PINMUX(0, 0, 94, 7, 0, 0)
472 #define PTC30_FXIO_D0_I                 NXP_S32_PINMUX(0, 0, 94, 0, 152, 4)
473 #define PTC30_FXIO_D23_I                NXP_S32_PINMUX(0, 0, 94, 0, 175, 2)
474 #define PTC31_FXIO_D1_O                 NXP_S32_PINMUX(0, 0, 95, 3, 0, 0)
475 #define PTC31_FXIO_D24_O                NXP_S32_PINMUX(0, 0, 95, 7, 0, 0)
476 #define PTC31_FXIO_D1_I                 NXP_S32_PINMUX(0, 0, 95, 0, 153, 4)
477 #define PTC31_FXIO_D24_I                NXP_S32_PINMUX(0, 0, 95, 0, 176, 2)
478 #define PTD0_FXIO_D0_O                  NXP_S32_PINMUX(0, 0, 96, 6, 0, 0)
479 #define PTD0_FXIO_D0_I                  NXP_S32_PINMUX(0, 0, 96, 0, 152, 1)
480 #define PTD1_FXIO_D1_O                  NXP_S32_PINMUX(0, 0, 97, 6, 0, 0)
481 #define PTD1_FXIO_D1_I                  NXP_S32_PINMUX(0, 0, 97, 0, 153, 1)
482 #define PTD2_FXIO_D4_O                  NXP_S32_PINMUX(0, 0, 98, 4, 0, 0)
483 #define PTD2_FXIO_D6_O                  NXP_S32_PINMUX(0, 0, 98, 5, 0, 0)
484 #define PTD2_FXIO_D4_I                  NXP_S32_PINMUX(0, 0, 98, 0, 156, 1)
485 #define PTD2_FXIO_D6_I                  NXP_S32_PINMUX(0, 0, 98, 0, 158, 3)
486 #define PTD3_FXIO_D5_O                  NXP_S32_PINMUX(0, 0, 99, 4, 0, 0)
487 #define PTD3_FXIO_D7_O                  NXP_S32_PINMUX(0, 0, 99, 5, 0, 0)
488 #define PTD3_FXIO_D5_I                  NXP_S32_PINMUX(0, 0, 99, 0, 157, 2)
489 #define PTD3_FXIO_D7_I                  NXP_S32_PINMUX(0, 0, 99, 0, 159, 3)
490 #define PTD5_FXIO_D15_O                 NXP_S32_PINMUX(0, 0, 101, 6, 0, 0)
491 #define PTD5_FXIO_D15_I                 NXP_S32_PINMUX(0, 0, 101, 0, 167, 4)
492 #define PTD6_FXIO_D13_O                 NXP_S32_PINMUX(0, 0, 102, 6, 0, 0)
493 #define PTD6_FXIO_D13_I                 NXP_S32_PINMUX(0, 0, 102, 0, 165, 1)
494 #define PTD8_FXIO_D1_O                  NXP_S32_PINMUX(0, 0, 104, 5, 0, 0)
495 #define PTD8_FXIO_D11_O                 NXP_S32_PINMUX(0, 0, 104, 7, 0, 0)
496 #define PTD8_FXIO_D1_I                  NXP_S32_PINMUX(0, 0, 104, 0, 153, 5)
497 #define PTD8_FXIO_D11_I                 NXP_S32_PINMUX(0, 0, 104, 0, 163, 5)
498 #define PTD9_FXIO_D0_O                  NXP_S32_PINMUX(0, 0, 105, 3, 0, 0)
499 #define PTD9_FXIO_D10_O                 NXP_S32_PINMUX(0, 0, 105, 7, 0, 0)
500 #define PTD9_FXIO_D0_I                  NXP_S32_PINMUX(0, 0, 105, 0, 152, 5)
501 #define PTD9_FXIO_D10_I                 NXP_S32_PINMUX(0, 0, 105, 0, 162, 4)
502 #define PTD13_FXIO_D7_O                 NXP_S32_PINMUX(0, 0, 109, 3, 0, 0)
503 #define PTD13_FXIO_D7_I                 NXP_S32_PINMUX(0, 0, 109, 0, 159, 7)
504 #define PTD15_FXIO_D6_O                 NXP_S32_PINMUX(0, 0, 111, 1, 0, 0)
505 #define PTD15_FXIO_D10_O                NXP_S32_PINMUX(0, 0, 111, 7, 0, 0)
506 #define PTD15_FXIO_D6_I                 NXP_S32_PINMUX(0, 0, 111, 0, 158, 7)
507 #define PTD15_FXIO_D10_I                NXP_S32_PINMUX(0, 0, 111, 0, 162, 1)
508 #define PTD17_FXIO_D9_O                 NXP_S32_PINMUX(0, 0, 113, 6, 0, 0)
509 #define PTD17_FXIO_D9_I                 NXP_S32_PINMUX(0, 0, 113, 0, 161, 1)
510 #define PTD20_FXIO_D25_O                NXP_S32_PINMUX(0, 0, 116, 3, 0, 0)
511 #define PTD20_FXIO_D25_I                NXP_S32_PINMUX(0, 0, 116, 0, 177, 2)
512 #define PTD21_FXIO_D26_O                NXP_S32_PINMUX(0, 0, 117, 3, 0, 0)
513 #define PTD21_FXIO_D26_I                NXP_S32_PINMUX(0, 0, 117, 0, 178, 2)
514 #define PTD22_FXIO_D27_O                NXP_S32_PINMUX(0, 0, 118, 3, 0, 0)
515 #define PTD22_FXIO_D27_I                NXP_S32_PINMUX(0, 0, 118, 0, 179, 2)
516 #define PTD23_FXIO_D28_O                NXP_S32_PINMUX(0, 0, 119, 3, 0, 0)
517 #define PTD23_FXIO_D28_I                NXP_S32_PINMUX(0, 0, 119, 0, 180, 2)
518 #define PTD24_FXIO_D29_O                NXP_S32_PINMUX(0, 0, 120, 3, 0, 0)
519 #define PTD24_FXIO_D29_I                NXP_S32_PINMUX(0, 0, 120, 0, 181, 2)
520 #define PTD26_FXIO_D7_O                 NXP_S32_PINMUX(0, 0, 122, 3, 0, 0)
521 #define PTD26_FXIO_D30_O                NXP_S32_PINMUX(0, 0, 122, 5, 0, 0)
522 #define PTD26_FXIO_D7_I                 NXP_S32_PINMUX(0, 0, 122, 0, 159, 4)
523 #define PTD26_FXIO_D30_I                NXP_S32_PINMUX(0, 0, 122, 0, 182, 2)
524 #define PTD27_FXIO_D31_O                NXP_S32_PINMUX(0, 0, 123, 5, 0, 0)
525 #define PTD27_FXIO_D31_I                NXP_S32_PINMUX(0, 0, 123, 0, 183, 2)
526 #define PTD31_FXIO_D6_O                 NXP_S32_PINMUX(0, 0, 127, 3, 0, 0)
527 #define PTD31_FXIO_D6_I                 NXP_S32_PINMUX(0, 0, 127, 0, 158, 4)
528 #define PTE0_FXIO_D3_O                  NXP_S32_PINMUX(0, 0, 128, 3, 0, 0)
529 #define PTE0_FXIO_D3_I                  NXP_S32_PINMUX(0, 0, 128, 0, 155, 7)
530 #define PTE1_FXIO_D2_O                  NXP_S32_PINMUX(0, 0, 129, 3, 0, 0)
531 #define PTE1_FXIO_D2_I                  NXP_S32_PINMUX(0, 0, 129, 0, 154, 8)
532 #define PTE2_FXIO_D13_O                 NXP_S32_PINMUX(0, 0, 130, 6, 0, 0)
533 #define PTE2_FXIO_D13_I                 NXP_S32_PINMUX(0, 0, 130, 0, 165, 4)
534 #define PTE3_FXIO_D6_O                  NXP_S32_PINMUX(0, 0, 131, 4, 0, 0)
535 #define PTE3_FXIO_D6_I                  NXP_S32_PINMUX(0, 0, 131, 0, 158, 6)
536 #define PTE4_FXIO_D6_O                  NXP_S32_PINMUX(0, 0, 132, 6, 0, 0)
537 #define PTE4_FXIO_D6_I                  NXP_S32_PINMUX(0, 0, 132, 0, 158, 1)
538 #define PTE5_FXIO_D7_O                  NXP_S32_PINMUX(0, 0, 133, 6, 0, 0)
539 #define PTE5_FXIO_D7_I                  NXP_S32_PINMUX(0, 0, 133, 0, 159, 1)
540 #define PTE6_FXIO_D12_O                 NXP_S32_PINMUX(0, 0, 134, 6, 0, 0)
541 #define PTE6_FXIO_D12_I                 NXP_S32_PINMUX(0, 0, 134, 0, 164, 4)
542 #define PTE7_FXIO_D11_O                 NXP_S32_PINMUX(0, 0, 135, 7, 0, 0)
543 #define PTE7_FXIO_D11_I                 NXP_S32_PINMUX(0, 0, 135, 0, 163, 4)
544 #define PTE8_FXIO_D12_O                 NXP_S32_PINMUX(0, 0, 136, 4, 0, 0)
545 #define PTE8_FXIO_D8_O                  NXP_S32_PINMUX(0, 0, 136, 7, 0, 0)
546 #define PTE8_FXIO_D8_I                  NXP_S32_PINMUX(0, 0, 136, 0, 160, 5)
547 #define PTE8_FXIO_D12_I                 NXP_S32_PINMUX(0, 0, 136, 0, 164, 1)
548 #define PTE9_FXIO_D11_O                 NXP_S32_PINMUX(0, 0, 137, 7, 0, 0)
549 #define PTE9_FXIO_D11_I                 NXP_S32_PINMUX(0, 0, 137, 0, 163, 1)
550 #define PTE10_FXIO_D4_O                 NXP_S32_PINMUX(0, 0, 138, 6, 0, 0)
551 #define PTE10_FXIO_D4_I                 NXP_S32_PINMUX(0, 0, 138, 0, 156, 2)
552 #define PTE11_FXIO_D5_O                 NXP_S32_PINMUX(0, 0, 139, 6, 0, 0)
553 #define PTE11_FXIO_D5_I                 NXP_S32_PINMUX(0, 0, 139, 0, 157, 1)
554 #define PTE12_FXIO_D8_O                 NXP_S32_PINMUX(0, 0, 140, 6, 0, 0)
555 #define PTE12_FXIO_D8_I                 NXP_S32_PINMUX(0, 0, 140, 0, 160, 1)
556 #define PTE13_FXIO_D5_O                 NXP_S32_PINMUX(0, 0, 141, 6, 0, 0)
557 #define PTE13_FXIO_D5_I                 NXP_S32_PINMUX(0, 0, 141, 0, 157, 5)
558 #define PTE14_FXIO_D7_O                 NXP_S32_PINMUX(0, 0, 142, 6, 0, 0)
559 #define PTE14_FXIO_D7_I                 NXP_S32_PINMUX(0, 0, 142, 0, 159, 5)
560 #define PTE15_FXIO_D2_O                 NXP_S32_PINMUX(0, 0, 143, 6, 0, 0)
561 #define PTE15_FXIO_D2_I                 NXP_S32_PINMUX(0, 0, 143, 0, 154, 1)
562 #define PTE16_FXIO_D3_O                 NXP_S32_PINMUX(0, 0, 144, 6, 0, 0)
563 #define PTE16_FXIO_D3_I                 NXP_S32_PINMUX(0, 0, 144, 0, 155, 2)
564 #define PTE17_FXIO_D5_O                 NXP_S32_PINMUX(0, 0, 145, 3, 0, 0)
565 #define PTE17_FXIO_D5_I                 NXP_S32_PINMUX(0, 0, 145, 0, 157, 4)
566 #define PTE18_FXIO_D4_O                 NXP_S32_PINMUX(0, 0, 146, 3, 0, 0)
567 #define PTE18_FXIO_D4_I                 NXP_S32_PINMUX(0, 0, 146, 0, 156, 4)
568 #define PTE24_FXIO_D5_O                 NXP_S32_PINMUX(0, 0, 152, 5, 0, 0)
569 #define PTE24_FXIO_D11_O                NXP_S32_PINMUX(0, 0, 152, 7, 0, 0)
570 #define PTE24_FXIO_D5_I                 NXP_S32_PINMUX(0, 0, 152, 0, 157, 10)
571 #define PTE24_FXIO_D11_I                NXP_S32_PINMUX(0, 0, 152, 0, 163, 6)
572 
573 /* EMIOS_1 */
574 #define PTA0_EMIOS_1_CH0_X_O            NXP_S32_PINMUX(0, 0, 0, 5, 0, 0)
575 #define PTA0_EMIOS_1_CH0_X_I            NXP_S32_PINMUX(0, 0, 0, 0, 80, 3)
576 #define PTA2_EMIOS_1_CH19_Y_O           NXP_S32_PINMUX(0, 0, 2, 2, 0, 0)
577 #define PTA2_EMIOS_1_CH19_Y_I           NXP_S32_PINMUX(0, 0, 2, 0, 99, 4)
578 #define PTA3_EMIOS_1_CH20_Y_O           NXP_S32_PINMUX(0, 0, 3, 2, 0, 0)
579 #define PTA3_EMIOS_1_CH20_Y_I           NXP_S32_PINMUX(0, 0, 3, 0, 100, 4)
580 #define PTA6_EMIOS_1_CH13_H_O           NXP_S32_PINMUX(0, 0, 6, 4, 0, 0)
581 #define PTA6_EMIOS_1_CH13_H_I           NXP_S32_PINMUX(0, 0, 6, 0, 93, 1)
582 #define PTA7_EMIOS_1_CH11_H_O           NXP_S32_PINMUX(0, 0, 7, 3, 0, 0)
583 #define PTA7_EMIOS_1_CH11_H_I           NXP_S32_PINMUX(0, 0, 7, 0, 91, 1)
584 #define PTA8_EMIOS_1_CH12_H_O           NXP_S32_PINMUX(0, 0, 8, 2, 0, 0)
585 #define PTA8_EMIOS_1_CH12_H_I           NXP_S32_PINMUX(0, 0, 8, 0, 92, 2)
586 #define PTA11_EMIOS_1_CH1_H_O           NXP_S32_PINMUX(0, 0, 11, 3, 0, 0)
587 #define PTA11_EMIOS_1_CH1_H_I           NXP_S32_PINMUX(0, 0, 11, 0, 81, 3)
588 #define PTA12_EMIOS_1_CH2_H_O           NXP_S32_PINMUX(0, 0, 12, 6, 0, 0)
589 #define PTA12_EMIOS_1_CH2_H_I           NXP_S32_PINMUX(0, 0, 12, 0, 82, 4)
590 #define PTA13_EMIOS_1_CH3_H_O           NXP_S32_PINMUX(0, 0, 13, 6, 0, 0)
591 #define PTA13_EMIOS_1_CH3_H_I           NXP_S32_PINMUX(0, 0, 13, 0, 83, 4)
592 #define PTA14_EMIOS_1_CH4_H_O           NXP_S32_PINMUX(0, 0, 14, 2, 0, 0)
593 #define PTA14_EMIOS_1_CH4_H_I           NXP_S32_PINMUX(0, 0, 14, 0, 84, 7)
594 #define PTA18_EMIOS_1_CH0_X_O           NXP_S32_PINMUX(0, 0, 18, 2, 0, 0)
595 #define PTA18_EMIOS_1_CH16_X_O          NXP_S32_PINMUX(0, 0, 18, 5, 0, 0)
596 #define PTA18_EMIOS_1_CH0_X_I           NXP_S32_PINMUX(0, 0, 18, 0, 80, 1)
597 #define PTA18_EMIOS_1_CH16_X_I          NXP_S32_PINMUX(0, 0, 18, 0, 96, 1)
598 #define PTA19_EMIOS_1_CH1_H_O           NXP_S32_PINMUX(0, 0, 19, 2, 0, 0)
599 #define PTA19_EMIOS_1_CH1_H_I           NXP_S32_PINMUX(0, 0, 19, 0, 81, 1)
600 #define PTA20_EMIOS_1_CH2_H_O           NXP_S32_PINMUX(0, 0, 20, 2, 0, 0)
601 #define PTA20_EMIOS_1_CH2_H_I           NXP_S32_PINMUX(0, 0, 20, 0, 82, 2)
602 #define PTA21_EMIOS_1_CH3_H_O           NXP_S32_PINMUX(0, 0, 21, 2, 0, 0)
603 #define PTA21_EMIOS_1_CH3_H_I           NXP_S32_PINMUX(0, 0, 21, 0, 83, 1)
604 #define PTA24_EMIOS_1_CH7_H             NXP_S32_PINMUX(0, 0, 23, 0, 87, 2)
605 #define PTA25_EMIOS_1_CH8_X             NXP_S32_PINMUX(0, 0, 23, 0, 88, 2)
606 #define PTA27_EMIOS_1_CH10_H_O          NXP_S32_PINMUX(0, 0, 27, 2, 0, 0)
607 #define PTA27_EMIOS_1_CH10_H_I          NXP_S32_PINMUX(0, 0, 27, 0, 90, 3)
608 #define PTA28_EMIOS_1_CH11_H_O          NXP_S32_PINMUX(0, 0, 28, 2, 0, 0)
609 #define PTA28_EMIOS_1_CH11_H_I          NXP_S32_PINMUX(0, 0, 28, 0, 91, 2)
610 #define PTA29_EMIOS_1_CH12_H_O          NXP_S32_PINMUX(0, 0, 29, 2, 0, 0)
611 #define PTA29_EMIOS_1_CH12_H_I          NXP_S32_PINMUX(0, 0, 29, 0, 92, 3)
612 #define PTA30_EMIOS_1_CH13_H_O          NXP_S32_PINMUX(0, 0, 30, 2, 0, 0)
613 #define PTA30_EMIOS_1_CH13_H_I          NXP_S32_PINMUX(0, 0, 30, 0, 93, 2)
614 #define PTA31_EMIOS_1_CH14_H_O          NXP_S32_PINMUX(0, 0, 31, 2, 0, 0)
615 #define PTA31_EMIOS_1_CH14_H_I          NXP_S32_PINMUX(0, 0, 31, 0, 94, 2)
616 #define PTB0_EMIOS_1_CH6_H_O            NXP_S32_PINMUX(0, 0, 32, 6, 0, 0)
617 #define PTB0_EMIOS_1_CH6_H_I            NXP_S32_PINMUX(0, 0, 32, 0, 86, 1)
618 #define PTB1_EMIOS_1_CH5_H_O            NXP_S32_PINMUX(0, 0, 33, 6, 0, 0)
619 #define PTB1_EMIOS_1_CH5_H_I            NXP_S32_PINMUX(0, 0, 33, 0, 85, 1)
620 #define PTB4_EMIOS_1_CH10_H_O           NXP_S32_PINMUX(0, 0, 36, 6, 0, 0)
621 #define PTB4_EMIOS_1_CH10_H_I           NXP_S32_PINMUX(0, 0, 36, 0, 90, 6)
622 #define PTB5_EMIOS_1_CH11_H_O           NXP_S32_PINMUX(0, 0, 37, 6, 0, 0)
623 #define PTB5_EMIOS_1_CH11_H_I           NXP_S32_PINMUX(0, 0, 37, 0, 91, 5)
624 #define PTB8_EMIOS_1_CH15_H_O           NXP_S32_PINMUX(0, 0, 40, 2, 0, 0)
625 #define PTB8_EMIOS_1_CH15_H_I           NXP_S32_PINMUX(0, 0, 40, 0, 95, 6)
626 #define PTB9_EMIOS_1_CH16_X_O           NXP_S32_PINMUX(0, 0, 41, 2, 0, 0)
627 #define PTB9_EMIOS_1_CH16_X_I           NXP_S32_PINMUX(0, 0, 41, 0, 96, 5)
628 #define PTB10_EMIOS_1_CH17_Y_O          NXP_S32_PINMUX(0, 0, 42, 2, 0, 0)
629 #define PTB10_EMIOS_1_CH17_Y_I          NXP_S32_PINMUX(0, 0, 42, 0, 97, 4)
630 #define PTB11_EMIOS_1_CH18_Y_O          NXP_S32_PINMUX(0, 0, 43, 2, 0, 0)
631 #define PTB11_EMIOS_1_CH18_Y_I          NXP_S32_PINMUX(0, 0, 43, 0, 98, 4)
632 #define PTB17_EMIOS_1_CH7_H_O           NXP_S32_PINMUX(0, 0, 49, 4, 0, 0)
633 #define PTB17_EMIOS_1_CH7_H_I           NXP_S32_PINMUX(0, 0, 49, 0, 87, 7)
634 #define PTB18_EMIOS_1_CH15_H_O          NXP_S32_PINMUX(0, 0, 50, 2, 0, 0)
635 #define PTB18_EMIOS_1_CH15_H_I          NXP_S32_PINMUX(0, 0, 50, 0, 95, 2)
636 #define PTB19_EMIOS_1_CH15_H_O          NXP_S32_PINMUX(0, 0, 51, 2, 0, 0)
637 #define PTB19_EMIOS_1_CH15_H_I          NXP_S32_PINMUX(0, 0, 51, 0, 95, 3)
638 #define PTB20_EMIOS_1_CH16_X_O          NXP_S32_PINMUX(0, 0, 52, 2, 0, 0)
639 #define PTB20_EMIOS_1_CH16_X_I          NXP_S32_PINMUX(0, 0, 52, 0, 96, 3)
640 #define PTB21_EMIOS_1_CH17_Y_O          NXP_S32_PINMUX(0, 0, 53, 2, 0, 0)
641 #define PTB21_EMIOS_1_CH17_Y_I          NXP_S32_PINMUX(0, 0, 53, 0, 97, 2)
642 #define PTB22_EMIOS_1_CH18_Y_O          NXP_S32_PINMUX(0, 0, 54, 2, 0, 0)
643 #define PTB22_EMIOS_1_CH18_Y_I          NXP_S32_PINMUX(0, 0, 54, 0, 98, 2)
644 #define PTB23_EMIOS_1_CH19_Y_O          NXP_S32_PINMUX(0, 0, 55, 2, 0, 0)
645 #define PTB23_EMIOS_1_CH19_Y_I          NXP_S32_PINMUX(0, 0, 55, 0, 99, 2)
646 #define PTB24_EMIOS_1_CH20_Y_O          NXP_S32_PINMUX(0, 0, 56, 2, 0, 0)
647 #define PTB24_EMIOS_1_CH20_Y_I          NXP_S32_PINMUX(0, 0, 56, 0, 100, 2)
648 #define PTB25_EMIOS_1_CH21_Y_O          NXP_S32_PINMUX(0, 0, 57, 2, 0, 0)
649 #define PTB25_EMIOS_1_CH21_Y_I          NXP_S32_PINMUX(0, 0, 57, 0, 101, 2)
650 #define PTB26_EMIOS_1_CH22_X_O          NXP_S32_PINMUX(0, 0, 58, 2, 0, 0)
651 #define PTB26_EMIOS_1_CH22_X_I          NXP_S32_PINMUX(0, 0, 58, 0, 102, 2)
652 #define PTB27_EMIOS_1_CH23_X_O          NXP_S32_PINMUX(0, 0, 59, 2, 0, 0)
653 #define PTB27_EMIOS_1_CH23_X_I          NXP_S32_PINMUX(0, 0, 59, 0, 103, 2)
654 #define PTC6_EMIOS_1_CH6_H_O            NXP_S32_PINMUX(0, 0, 70, 5, 0, 0)
655 #define PTC6_EMIOS_1_CH6_H_I            NXP_S32_PINMUX(0, 0, 70, 0, 86, 4)
656 #define PTC7_EMIOS_1_CH7_H_O            NXP_S32_PINMUX(0, 0, 71, 5, 0, 0)
657 #define PTC7_EMIOS_1_CH7_H_I            NXP_S32_PINMUX(0, 0, 71, 0, 87, 4)
658 #define PTC8_EMIOS_1_CH9_H_O            NXP_S32_PINMUX(0, 0, 72, 4, 0, 0)
659 #define PTC8_EMIOS_1_CH9_H_I            NXP_S32_PINMUX(0, 0, 72, 0, 89, 1)
660 #define PTC9_EMIOS_1_CH8_X_O            NXP_S32_PINMUX(0, 0, 73, 4, 0, 0)
661 #define PTC9_EMIOS_1_CH8_X_I            NXP_S32_PINMUX(0, 0, 73, 0, 88, 1)
662 #define PTC10_EMIOS_1_CH0_X_O           NXP_S32_PINMUX(0, 0, 74, 7, 0, 0)
663 #define PTC10_EMIOS_1_CH0_X_I           NXP_S32_PINMUX(0, 0, 74, 0, 80, 6)
664 #define PTC11_EMIOS_1_CH1_H_O           NXP_S32_PINMUX(0, 0, 75, 3, 0, 0)
665 #define PTC11_EMIOS_1_CH1_H_I           NXP_S32_PINMUX(0, 0, 75, 0, 81, 7)
666 #define PTC12_EMIOS_1_CH2_H_O           NXP_S32_PINMUX(0, 0, 76, 2, 0, 0)
667 #define PTC12_EMIOS_1_CH2_H_I           NXP_S32_PINMUX(0, 0, 76, 0, 82, 1)
668 #define PTC13_EMIOS_1_CH3_H_O           NXP_S32_PINMUX(0, 0, 77, 2, 0, 0)
669 #define PTC13_EMIOS_1_CH3_H_I           NXP_S32_PINMUX(0, 0, 77, 0, 83, 7)
670 #define PTC14_EMIOS_1_CH4_H_O           NXP_S32_PINMUX(0, 0, 78, 5, 0, 0)
671 #define PTC14_EMIOS_1_CH4_H_I           NXP_S32_PINMUX(0, 0, 78, 0, 84, 8)
672 #define PTC16_EMIOS_1_CH9_H_O           NXP_S32_PINMUX(0, 0, 80, 2, 0, 0)
673 #define PTC16_EMIOS_1_CH9_H_I           NXP_S32_PINMUX(0, 0, 80, 0, 89, 5)
674 #define PTC24_EMIOS_1_CH0_X_O           NXP_S32_PINMUX(0, 0, 88, 2, 0, 0)
675 #define PTC24_EMIOS_1_CH0_X_I           NXP_S32_PINMUX(0, 0, 88, 0, 80, 4)
676 #define PTC25_EMIOS_1_CH1_H_O           NXP_S32_PINMUX(0, 0, 89, 2, 0, 0)
677 #define PTC25_EMIOS_1_CH1_H_I           NXP_S32_PINMUX(0, 0, 89, 0, 81, 4)
678 #define PTC26_EMIOS_1_CH3_H_O           NXP_S32_PINMUX(0, 0, 90, 2, 0, 0)
679 #define PTC26_EMIOS_1_CH3_H_I           NXP_S32_PINMUX(0, 0, 90, 0, 83, 3)
680 #define PTC27_EMIOS_1_CH4_H_O           NXP_S32_PINMUX(0, 0, 91, 2, 0, 0)
681 #define PTC27_EMIOS_1_CH4_H_I           NXP_S32_PINMUX(0, 0, 91, 0, 84, 2)
682 #define PTC28_EMIOS_1_CH7_H_O           NXP_S32_PINMUX(0, 0, 92, 2, 0, 0)
683 #define PTC28_EMIOS_1_CH7_H_I           NXP_S32_PINMUX(0, 0, 92, 0, 87, 3)
684 #define PTC29_EMIOS_1_CH10_H_O          NXP_S32_PINMUX(0, 0, 93, 2, 0, 0)
685 #define PTC29_EMIOS_1_CH10_H_I          NXP_S32_PINMUX(0, 0, 93, 0, 90, 1)
686 #define PTC30_EMIOS_1_CH12_H_O          NXP_S32_PINMUX(0, 0, 94, 2, 0, 0)
687 #define PTC30_EMIOS_1_CH12_H_I          NXP_S32_PINMUX(0, 0, 94, 0, 92, 1)
688 #define PTC31_EMIOS_1_CH14_H_O          NXP_S32_PINMUX(0, 0, 95, 2, 0, 0)
689 #define PTC31_EMIOS_1_CH14_H_I          NXP_S32_PINMUX(0, 0, 95, 0, 94, 1)
690 #define PTD2_EMIOS_1_CH21_Y_O           NXP_S32_PINMUX(0, 0, 98, 2, 0, 0)
691 #define PTD2_EMIOS_1_CH21_Y_I           NXP_S32_PINMUX(0, 0, 98, 0, 101, 4)
692 #define PTD3_EMIOS_1_CH22_X_O           NXP_S32_PINMUX(0, 0, 99, 2, 0, 0)
693 #define PTD3_EMIOS_1_CH22_X_I           NXP_S32_PINMUX(0, 0, 99, 0, 102, 4)
694 #define PTD4_EMIOS_1_CH23_X_O           NXP_S32_PINMUX(0, 0, 100, 2, 0, 0)
695 #define PTD4_EMIOS_1_CH23_X_I           NXP_S32_PINMUX(0, 0, 100, 0, 103, 4)
696 #define PTD6_EMIOS_1_CH12_H_O           NXP_S32_PINMUX(0, 0, 102, 3, 0, 0)
697 #define PTD6_EMIOS_1_CH12_H_I           NXP_S32_PINMUX(0, 0, 102, 0, 92, 5)
698 #define PTD10_EMIOS_1_CH10_H_O          NXP_S32_PINMUX(0, 0, 106, 3, 0, 0)
699 #define PTD10_EMIOS_1_CH10_H_I          NXP_S32_PINMUX(0, 0, 106, 0, 90, 2)
700 #define PTD15_EMIOS_1_CH14_H_O          NXP_S32_PINMUX(0, 0, 111, 3, 0, 0)
701 #define PTD15_EMIOS_1_CH14_H_I          NXP_S32_PINMUX(0, 0, 111, 0, 94, 6)
702 #define PTD16_EMIOS_1_CH15_H_O          NXP_S32_PINMUX(0, 0, 112, 5, 0, 0)
703 #define PTD16_EMIOS_1_CH15_H_I          NXP_S32_PINMUX(0, 0, 112, 0, 95, 7)
704 #define PTD20_EMIOS_1_CH17_Y_O          NXP_S32_PINMUX(0, 0, 116, 2, 0, 0)
705 #define PTD20_EMIOS_1_CH17_Y_I          NXP_S32_PINMUX(0, 0, 116, 0, 97, 1)
706 #define PTD21_EMIOS_1_CH18_Y_O          NXP_S32_PINMUX(0, 0, 117, 2, 0, 0)
707 #define PTD21_EMIOS_1_CH18_Y_I          NXP_S32_PINMUX(0, 0, 117, 0, 98, 1)
708 #define PTD22_EMIOS_1_CH19_Y_O          NXP_S32_PINMUX(0, 0, 118, 2, 0, 0)
709 #define PTD22_EMIOS_1_CH19_Y_I          NXP_S32_PINMUX(0, 0, 118, 0, 99, 1)
710 #define PTD23_EMIOS_1_CH20_Y_O          NXP_S32_PINMUX(0, 0, 119, 2, 0, 0)
711 #define PTD23_EMIOS_1_CH20_Y_I          NXP_S32_PINMUX(0, 0, 119, 0, 100, 1)
712 #define PTD24_EMIOS_1_CH21_Y_O          NXP_S32_PINMUX(0, 0, 120, 2, 0, 0)
713 #define PTD24_EMIOS_1_CH21_Y_I          NXP_S32_PINMUX(0, 0, 120, 0, 101, 1)
714 #define PTD26_EMIOS_1_CH23_X_O          NXP_S32_PINMUX(0, 0, 122, 2, 0, 0)
715 #define PTD26_EMIOS_1_CH23_X_I          NXP_S32_PINMUX(0, 0, 122, 0, 103, 1)
716 #define PTE2_EMIOS_1_CH8_X_O            NXP_S32_PINMUX(0, 0, 130, 4, 0, 0)
717 #define PTE2_EMIOS_1_CH8_X_I            NXP_S32_PINMUX(0, 0, 130, 0, 88, 4)
718 #define PTE4_EMIOS_1_CH4_H_O            NXP_S32_PINMUX(0, 0, 132, 3, 0, 0)
719 #define PTE4_EMIOS_1_CH4_H_I            NXP_S32_PINMUX(0, 0, 132, 0, 84, 4)
720 #define PTE5_EMIOS_1_CH5_H_O            NXP_S32_PINMUX(0, 0, 133, 3, 0, 0)
721 #define PTE5_EMIOS_1_CH5_H_I            NXP_S32_PINMUX(0, 0, 133, 0, 85, 4)
722 #define PTE6_EMIOS_1_CH14_H_O           NXP_S32_PINMUX(0, 0, 134, 4, 0, 0)
723 #define PTE6_EMIOS_1_CH14_H_I           NXP_S32_PINMUX(0, 0, 134, 0, 94, 5)
724 #define PTE9_EMIOS_1_CH13_H_O           NXP_S32_PINMUX(0, 0, 137, 3, 0, 0)
725 #define PTE9_EMIOS_1_CH13_H_I           NXP_S32_PINMUX(0, 0, 137, 0, 93, 5)
726 #define PTE12_EMIOS_1_CH5_H_O           NXP_S32_PINMUX(0, 0, 140, 4, 0, 0)
727 #define PTE12_EMIOS_1_CH5_H_I           NXP_S32_PINMUX(0, 0, 140, 0, 85, 5)
728 #define PTE13_EMIOS_1_CH5_H_O           NXP_S32_PINMUX(0, 0, 141, 2, 0, 0)
729 #define PTE13_EMIOS_1_CH5_H_I           NXP_S32_PINMUX(0, 0, 141, 0, 85, 3)
730 #define PTE21_EMIOS_1_CH1_H_O           NXP_S32_PINMUX(0, 0, 149, 2, 0, 0)
731 #define PTE21_EMIOS_1_CH1_H_I           NXP_S32_PINMUX(0, 0, 149, 0, 81, 2)
732 #define PTE22_EMIOS_1_CH2_H_O           NXP_S32_PINMUX(0, 0, 150, 2, 0, 0)
733 #define PTE22_EMIOS_1_CH2_H_I           NXP_S32_PINMUX(0, 0, 150, 0, 82, 3)
734 #define PTE23_EMIOS_1_CH3_H_O           NXP_S32_PINMUX(0, 0, 151, 2, 0, 0)
735 #define PTE23_EMIOS_1_CH3_H_I           NXP_S32_PINMUX(0, 0, 151, 0, 83, 2)
736 #define PTE24_EMIOS_1_CH4_H_O           NXP_S32_PINMUX(0, 0, 152, 2, 0, 0)
737 #define PTE24_EMIOS_1_CH4_H_I           NXP_S32_PINMUX(0, 0, 152, 0, 84, 3)
738 #define PTE25_EMIOS_1_CH5_H_O           NXP_S32_PINMUX(0, 0, 153, 2, 0, 0)
739 #define PTE25_EMIOS_1_CH5_H_I           NXP_S32_PINMUX(0, 0, 153, 0, 85, 2)
740 #define PTE26_EMIOS_1_CH6_H_O           NXP_S32_PINMUX(0, 0, 154, 2, 0, 0)
741 #define PTE26_EMIOS_1_CH6_H_I           NXP_S32_PINMUX(0, 0, 154, 0, 86, 3)
742 
743 /* LPSPI0 */
744 #define PTA0_LPSPI0_PCS7_O              NXP_S32_PINMUX(0, 0, 0, 6, 0, 0)
745 #define PTA0_LPSPI0_PCS7_I              NXP_S32_PINMUX(0, 0, 0, 0, 228, 1)
746 #define PTA1_LPSPI0_PCS6_O              NXP_S32_PINMUX(0, 0, 1, 6, 0, 0)
747 #define PTA1_LPSPI0_PCS6_I              NXP_S32_PINMUX(0, 0, 1, 0, 227, 1)
748 #define PTA7_LPSPI0_PCS1_O              NXP_S32_PINMUX(0, 0, 7, 2, 0, 0)
749 #define PTA7_LPSPI0_PCS1_I              NXP_S32_PINMUX(0, 0, 7, 0, 222, 3)
750 #define PTA15_LPSPI0_PCS3_O             NXP_S32_PINMUX(0, 0, 15, 3, 0, 0)
751 #define PTA15_LPSPI0_PCS3_I             NXP_S32_PINMUX(0, 0, 15, 0, 224, 1)
752 #define PTA16_LPSPI0_PCS4_O             NXP_S32_PINMUX(0, 0, 16, 4, 0, 0)
753 #define PTA16_LPSPI0_PCS4_I             NXP_S32_PINMUX(0, 0, 16, 0, 225, 1)
754 #define PTA30_LPSPI0_SOUT_O             NXP_S32_PINMUX(0, 0, 30, 4, 0, 0)
755 #define PTA30_LPSPI0_SOUT_I             NXP_S32_PINMUX(0, 0, 30, 0, 231, 4)
756 #define PTA31_LPSPI0_PCS1_O             NXP_S32_PINMUX(0, 0, 31, 4, 0, 0)
757 #define PTA31_LPSPI0_PCS1_I             NXP_S32_PINMUX(0, 0, 31, 0, 222, 2)
758 #define PTB0_LPSPI0_PCS0_O              NXP_S32_PINMUX(0, 0, 32, 3, 0, 0)
759 #define PTB0_LPSPI0_PCS0_I              NXP_S32_PINMUX(0, 0, 32, 0, 221, 1)
760 #define PTB1_LPSPI0_SOUT_O              NXP_S32_PINMUX(0, 0, 33, 3, 0, 0)
761 #define PTB1_LPSPI0_SOUT_I              NXP_S32_PINMUX(0, 0, 33, 0, 231, 3)
762 #define PTB4_LPSPI0_SOUT_O              NXP_S32_PINMUX(0, 0, 36, 3, 0, 0)
763 #define PTB4_LPSPI0_SOUT_I              NXP_S32_PINMUX(0, 0, 36, 0, 231, 2)
764 #define PTB5_LPSPI0_PCS1_O              NXP_S32_PINMUX(0, 0, 37, 3, 0, 0)
765 #define PTB5_LPSPI0_PCS0_O              NXP_S32_PINMUX(0, 0, 37, 4, 0, 0)
766 #define PTB5_LPSPI0_PCS0_I              NXP_S32_PINMUX(0, 0, 37, 0, 221, 2)
767 #define PTB5_LPSPI0_PCS1_I              NXP_S32_PINMUX(0, 0, 37, 0, 222, 1)
768 #define PTB8_LPSPI0_PCS5_O              NXP_S32_PINMUX(0, 0, 40, 6, 0, 0)
769 #define PTB8_LPSPI0_PCS5_I              NXP_S32_PINMUX(0, 0, 40, 0, 226, 1)
770 #define PTC2_LPSPI0_PCS2_O              NXP_S32_PINMUX(0, 0, 66, 4, 0, 0)
771 #define PTC2_LPSPI0_PCS2_I              NXP_S32_PINMUX(0, 0, 66, 0, 223, 2)
772 #define PTC6_LPSPI0_PCS1_O              NXP_S32_PINMUX(0, 0, 70, 6, 0, 0)
773 #define PTC6_LPSPI0_PCS1_I              NXP_S32_PINMUX(0, 0, 70, 0, 222, 4)
774 #define PTC7_LPSPI0_PCS0_O              NXP_S32_PINMUX(0, 0, 71, 6, 0, 0)
775 #define PTC7_LPSPI0_PCS0_I              NXP_S32_PINMUX(0, 0, 71, 0, 221, 6)
776 #define PTC8_LPSPI0_SCK_O               NXP_S32_PINMUX(0, 0, 72, 6, 0, 0)
777 #define PTC8_LPSPI0_SCK_I               NXP_S32_PINMUX(0, 0, 72, 0, 229, 1)
778 #define PTC9_LPSPI0_SIN_O               NXP_S32_PINMUX(0, 0, 73, 6, 0, 0)
779 #define PTC9_LPSPI0_SIN_I               NXP_S32_PINMUX(0, 0, 73, 0, 230, 2)
780 #define PTD5_LPSPI0_PCS1_O              NXP_S32_PINMUX(0, 0, 101, 7, 0, 0)
781 #define PTD5_LPSPI0_PCS1_I              NXP_S32_PINMUX(0, 0, 101, 0, 222, 5)
782 #define PTD6_LPSPI0_PCS0_O              NXP_S32_PINMUX(0, 0, 102, 7, 0, 0)
783 #define PTD6_LPSPI0_PCS0_I              NXP_S32_PINMUX(0, 0, 102, 0, 221, 7)
784 #define PTD7_LPSPI0_PCS3_O              NXP_S32_PINMUX(0, 0, 103, 4, 0, 0)
785 #define PTD7_LPSPI0_PCS3_I              NXP_S32_PINMUX(0, 0, 103, 0, 224, 2)
786 #define PTD10_LPSPI0_SIN_O              NXP_S32_PINMUX(0, 0, 106, 5, 0, 0)
787 #define PTD10_LPSPI0_SIN_I              NXP_S32_PINMUX(0, 0, 106, 0, 230, 4)
788 #define PTD11_LPSPI0_SCK_O              NXP_S32_PINMUX(0, 0, 107, 6, 0, 0)
789 #define PTD11_LPSPI0_SCK_I              NXP_S32_PINMUX(0, 0, 107, 0, 229, 5)
790 #define PTD12_LPSPI0_SOUT_O             NXP_S32_PINMUX(0, 0, 108, 6, 0, 0)
791 #define PTD12_LPSPI0_SOUT_I             NXP_S32_PINMUX(0, 0, 108, 0, 231, 5)
792 #define PTD15_LPSPI0_SCK_O              NXP_S32_PINMUX(0, 0, 111, 4, 0, 0)
793 #define PTD15_LPSPI0_SCK_I              NXP_S32_PINMUX(0, 0, 111, 0, 229, 3)
794 #define PTD16_LPSPI0_SIN_O              NXP_S32_PINMUX(0, 0, 112, 4, 0, 0)
795 #define PTD16_LPSPI0_SIN_I              NXP_S32_PINMUX(0, 0, 112, 0, 230, 3)
796 #define PTE0_LPSPI0_SIN_O               NXP_S32_PINMUX(0, 0, 128, 2, 0, 0)
797 #define PTE0_LPSPI0_SIN_I               NXP_S32_PINMUX(0, 0, 128, 0, 230, 1)
798 #define PTE1_LPSPI0_SCK_O               NXP_S32_PINMUX(0, 0, 129, 2, 0, 0)
799 #define PTE1_LPSPI0_SCK_I               NXP_S32_PINMUX(0, 0, 129, 0, 229, 2)
800 #define PTE2_LPSPI0_SOUT_O              NXP_S32_PINMUX(0, 0, 130, 2, 0, 0)
801 #define PTE2_LPSPI0_SOUT_I              NXP_S32_PINMUX(0, 0, 130, 0, 231, 1)
802 #define PTE4_LPSPI0_PCS0_O              NXP_S32_PINMUX(0, 0, 132, 1, 0, 0)
803 #define PTE4_LPSPI0_PCS0_I              NXP_S32_PINMUX(0, 0, 132, 0, 221, 5)
804 #define PTE6_LPSPI0_PCS2_O              NXP_S32_PINMUX(0, 0, 134, 2, 0, 0)
805 #define PTE6_LPSPI0_PCS2_I              NXP_S32_PINMUX(0, 0, 134, 0, 223, 1)
806 
807 /* TRGMUX */
808 #define PTA0_TRGMUX_OUT3                NXP_S32_PINMUX(0, 0, 0, 7, 0, 0)
809 #define PTA1_TRGMUX_OUT0                NXP_S32_PINMUX(0, 0, 1, 7, 0, 0)
810 #define PTA18_TRGMUX_IN12               NXP_S32_PINMUX(0, 0, 18, 0, 356, 1)
811 #define PTA19_TRGMUX_IN13               NXP_S32_PINMUX(0, 0, 19, 0, 357, 1)
812 #define PTA20_TRGMUX_IN14               NXP_S32_PINMUX(0, 0, 20, 0, 358, 1)
813 #define PTA21_TRGMUX_IN15               NXP_S32_PINMUX(0, 0, 21, 0, 359, 1)
814 #define PTA31_TRGMUX_OUT8               NXP_S32_PINMUX(0, 0, 31, 7, 0, 0)
815 #define PTB2_TRGMUX_IN3                 NXP_S32_PINMUX(0, 0, 34, 0, 347, 1)
816 #define PTB3_TRGMUX_IN2                 NXP_S32_PINMUX(0, 0, 35, 0, 346, 1)
817 #define PTB4_TRGMUX_IN1                 NXP_S32_PINMUX(0, 0, 36, 0, 345, 1)
818 #define PTB5_TRGMUX_IN0                 NXP_S32_PINMUX(0, 0, 37, 0, 344, 1)
819 #define PTB18_TRGMUX_OUT9               NXP_S32_PINMUX(0, 0, 50, 7, 0, 0)
820 #define PTB19_TRGMUX_OUT10              NXP_S32_PINMUX(0, 0, 51, 7, 0, 0)
821 #define PTB20_TRGMUX_OUT11              NXP_S32_PINMUX(0, 0, 52, 7, 0, 0)
822 #define PTB21_TRGMUX_OUT12              NXP_S32_PINMUX(0, 0, 53, 7, 0, 0)
823 #define PTB22_TRGMUX_OUT13              NXP_S32_PINMUX(0, 0, 54, 7, 0, 0)
824 #define PTB23_TRGMUX_OUT14              NXP_S32_PINMUX(0, 0, 55, 7, 0, 0)
825 #define PTC10_TRGMUX_IN11               NXP_S32_PINMUX(0, 0, 74, 0, 355, 1)
826 #define PTC11_TRGMUX_IN10               NXP_S32_PINMUX(0, 0, 75, 0, 354, 1)
827 #define PTC14_TRGMUX_IN9                NXP_S32_PINMUX(0, 0, 78, 0, 353, 1)
828 #define PTC15_TRGMUX_IN8                NXP_S32_PINMUX(0, 0, 79, 0, 352, 1)
829 #define PTC24_TRGMUX_OUT15              NXP_S32_PINMUX(0, 0, 88, 7, 0, 0)
830 #define PTD0_TRGMUX_OUT1                NXP_S32_PINMUX(0, 0, 96, 7, 0, 0)
831 #define PTD1_TRGMUX_OUT2                NXP_S32_PINMUX(0, 0, 97, 7, 0, 0)
832 #define PTD2_TRGMUX_IN5                 NXP_S32_PINMUX(0, 0, 98, 0, 349, 1)
833 #define PTD3_TRGMUX_IN4                 NXP_S32_PINMUX(0, 0, 99, 0, 348, 1)
834 #define PTD5_TRGMUX_IN7                 NXP_S32_PINMUX(0, 0, 101, 0, 351, 1)
835 #define PTE3_TRGMUX_IN6                 NXP_S32_PINMUX(0, 0, 131, 0, 350, 1)
836 #define PTE10_TRGMUX_OUT4               NXP_S32_PINMUX(0, 0, 138, 7, 0, 0)
837 #define PTE11_TRGMUX_OUT5               NXP_S32_PINMUX(0, 0, 139, 7, 0, 0)
838 #define PTE15_TRGMUX_OUT6               NXP_S32_PINMUX(0, 0, 143, 7, 0, 0)
839 #define PTE16_TRGMUX_OUT7               NXP_S32_PINMUX(0, 0, 144, 7, 0, 0)
840 
841 /* LPUART0 */
842 #define PTA0_LPUART0_CTS                NXP_S32_PINMUX(0, 0, 0, 0, 360, 1)
843 #define PTA1_LPUART0_RTS                NXP_S32_PINMUX(0, 0, 1, 3, 0, 0)
844 #define PTA2_LPUART0_RX                 NXP_S32_PINMUX(0, 0, 2, 0, 187, 1)
845 #define PTA3_LPUART0_TX_O               NXP_S32_PINMUX(0, 0, 3, 6, 0, 0)
846 #define PTA3_LPUART0_TX_I               NXP_S32_PINMUX(0, 0, 3, 0, 363, 1)
847 #define PTA27_LPUART0_TX_O              NXP_S32_PINMUX(0, 0, 27, 4, 0, 0)
848 #define PTA27_LPUART0_TX_I              NXP_S32_PINMUX(0, 0, 27, 0, 363, 4)
849 #define PTA28_LPUART0_RX                NXP_S32_PINMUX(0, 0, 28, 0, 187, 4)
850 #define PTB0_LPUART0_RX                 NXP_S32_PINMUX(0, 0, 32, 0, 187, 2)
851 #define PTB1_LPUART0_TX_O               NXP_S32_PINMUX(0, 0, 33, 2, 0, 0)
852 #define PTB1_LPUART0_TX_I               NXP_S32_PINMUX(0, 0, 33, 0, 363, 2)
853 #define PTC2_LPUART0_RX                 NXP_S32_PINMUX(0, 0, 66, 0, 187, 3)
854 #define PTC3_LPUART0_TX_O               NXP_S32_PINMUX(0, 0, 67, 4, 0, 0)
855 #define PTC3_LPUART0_TX_I               NXP_S32_PINMUX(0, 0, 67, 0, 363, 3)
856 #define PTC8_LPUART0_CTS                NXP_S32_PINMUX(0, 0, 72, 0, 360, 2)
857 #define PTC9_LPUART0_RTS                NXP_S32_PINMUX(0, 0, 73, 3, 0, 0)
858 
859 /* FCCU */
860 #define PTA2_FCCU_ERR0                  NXP_S32_PINMUX(0, 0, 2, 1, 0, 0)
861 #define PTA2_FCCU_ERR_IN0               NXP_S32_PINMUX(0, 0, 2, 0, 148, 1)
862 #define PTA3_FCCU_ERR1                  NXP_S32_PINMUX(0, 0, 3, 1, 0, 0)
863 #define PTA3_FCCU_ERR_IN1               NXP_S32_PINMUX(0, 0, 3, 0, 149, 1)
864 #define PTE15_FCCU_ERR0                 NXP_S32_PINMUX(0, 0, 143, 1, 0, 0)
865 #define PTE15_FCCU_ERR_IN0              NXP_S32_PINMUX(0, 0, 143, 0, 148, 2)
866 #define PTE16_FCCU_ERR1                 NXP_S32_PINMUX(0, 0, 144, 1, 0, 0)
867 #define PTE16_FCCU_ERR_IN1              NXP_S32_PINMUX(0, 0, 144, 0, 149, 2)
868 
869 /* LPSPI5 */
870 #define PTA2_LPSPI5_SIN_O               NXP_S32_PINMUX(0, 0, 2, 7, 0, 0)
871 #define PTA2_LPSPI5_SIN_I               NXP_S32_PINMUX(0, 0, 2, 0, 267, 2)
872 #define PTA3_LPSPI5_SCK_O               NXP_S32_PINMUX(0, 0, 3, 7, 0, 0)
873 #define PTA3_LPSPI5_SCK_I               NXP_S32_PINMUX(0, 0, 3, 0, 266, 2)
874 #define PTA14_LPSPI5_PCS1_O             NXP_S32_PINMUX(0, 0, 14, 7, 0, 0)
875 #define PTA14_LPSPI5_PCS1_I             NXP_S32_PINMUX(0, 0, 14, 0, 263, 2)
876 #define PTA15_LPSPI5_PCS0_O             NXP_S32_PINMUX(0, 0, 15, 6, 0, 0)
877 #define PTA15_LPSPI5_PCS0_I             NXP_S32_PINMUX(0, 0, 15, 0, 262, 3)
878 #define PTD2_LPSPI5_SOUT_O              NXP_S32_PINMUX(0, 0, 98, 7, 0, 0)
879 #define PTD2_LPSPI5_SOUT_I              NXP_S32_PINMUX(0, 0, 98, 0, 268, 2)
880 #define PTD4_LPSPI5_PCS0_O              NXP_S32_PINMUX(0, 0, 100, 7, 0, 0)
881 #define PTD4_LPSPI5_PCS0_I              NXP_S32_PINMUX(0, 0, 100, 0, 262, 2)
882 #define PTD13_LPSPI5_SIN_O              NXP_S32_PINMUX(0, 0, 109, 1, 0, 0)
883 #define PTD13_LPSPI5_SIN_I              NXP_S32_PINMUX(0, 0, 109, 0, 267, 1)
884 #define PTD14_LPSPI5_SCK_O              NXP_S32_PINMUX(0, 0, 110, 1, 0, 0)
885 #define PTD14_LPSPI5_SCK_I              NXP_S32_PINMUX(0, 0, 110, 0, 266, 1)
886 #define PTD17_LPSPI5_PCS0_O             NXP_S32_PINMUX(0, 0, 113, 1, 0, 0)
887 #define PTD17_LPSPI5_PCS0_I             NXP_S32_PINMUX(0, 0, 113, 0, 262, 1)
888 #define PTD26_LPSPI5_SCK_O              NXP_S32_PINMUX(0, 0, 122, 6, 0, 0)
889 #define PTD26_LPSPI5_SCK_I              NXP_S32_PINMUX(0, 0, 122, 0, 266, 3)
890 #define PTD27_LPSPI5_SOUT_O             NXP_S32_PINMUX(0, 0, 123, 6, 0, 0)
891 #define PTD27_LPSPI5_SOUT_I             NXP_S32_PINMUX(0, 0, 123, 0, 268, 3)
892 #define PTD28_LPSPI5_SIN_O              NXP_S32_PINMUX(0, 0, 124, 6, 0, 0)
893 #define PTD28_LPSPI5_SIN_I              NXP_S32_PINMUX(0, 0, 124, 0, 267, 3)
894 #define PTD29_LPSPI5_PCS2_O             NXP_S32_PINMUX(0, 0, 125, 6, 0, 0)
895 #define PTD29_LPSPI5_PCS2_I             NXP_S32_PINMUX(0, 0, 125, 0, 264, 1)
896 #define PTD30_LPSPI5_PCS3_O             NXP_S32_PINMUX(0, 0, 126, 6, 0, 0)
897 #define PTD30_LPSPI5_PCS3_I             NXP_S32_PINMUX(0, 0, 126, 0, 265, 1)
898 #define PTE8_LPSPI5_PCS1_O              NXP_S32_PINMUX(0, 0, 136, 3, 0, 0)
899 #define PTE8_LPSPI5_PCS1_I              NXP_S32_PINMUX(0, 0, 136, 0, 263, 1)
900 #define PTE9_LPSPI5_SOUT_O              NXP_S32_PINMUX(0, 0, 137, 1, 0, 0)
901 #define PTE9_LPSPI5_SOUT_I              NXP_S32_PINMUX(0, 0, 137, 0, 268, 1)
902 
903 /* LPSPI1 */
904 #define PTA2_LPSPI1_SIN                 NXP_S32_PINMUX(0, 0, 2, 0, 239, 2)
905 #define PTA3_LPSPI1_SCK_O               NXP_S32_PINMUX(0, 0, 3, 3, 0, 0)
906 #define PTA3_LPSPI1_SCK_I               NXP_S32_PINMUX(0, 0, 3, 0, 238, 1)
907 #define PTA6_LPSPI1_PCS1_O              NXP_S32_PINMUX(0, 0, 6, 3, 0, 0)
908 #define PTA6_LPSPI1_PCS1_I              NXP_S32_PINMUX(0, 0, 6, 0, 233, 1)
909 #define PTA11_LPSPI1_PCS0_O             NXP_S32_PINMUX(0, 0, 11, 6, 0, 0)
910 #define PTA11_LPSPI1_PCS0_I             NXP_S32_PINMUX(0, 0, 11, 0, 232, 2)
911 #define PTA12_LPSPI1_PCS5_O             NXP_S32_PINMUX(0, 0, 12, 1, 0, 0)
912 #define PTA12_LPSPI1_PCS5_I             NXP_S32_PINMUX(0, 0, 12, 0, 237, 1)
913 #define PTA13_LPSPI1_PCS4_O             NXP_S32_PINMUX(0, 0, 13, 1, 0, 0)
914 #define PTA13_LPSPI1_PCS4_I             NXP_S32_PINMUX(0, 0, 13, 0, 236, 1)
915 #define PTA14_LPSPI1_PCS3_O             NXP_S32_PINMUX(0, 0, 14, 3, 0, 0)
916 #define PTA14_LPSPI1_PCS3_I             NXP_S32_PINMUX(0, 0, 14, 0, 235, 2)
917 #define PTA16_LPSPI1_PCS2_O             NXP_S32_PINMUX(0, 0, 16, 3, 0, 0)
918 #define PTA16_LPSPI1_PCS2_I             NXP_S32_PINMUX(0, 0, 16, 0, 234, 2)
919 #define PTA18_LPSPI1_SOUT_O             NXP_S32_PINMUX(0, 0, 18, 4, 0, 0)
920 #define PTA18_LPSPI1_SOUT_I             NXP_S32_PINMUX(0, 0, 18, 0, 240, 4)
921 #define PTA19_LPSPI1_SCK_O              NXP_S32_PINMUX(0, 0, 19, 4, 0, 0)
922 #define PTA19_LPSPI1_SCK_I              NXP_S32_PINMUX(0, 0, 19, 0, 238, 3)
923 #define PTA20_LPSPI1_SIN_O              NXP_S32_PINMUX(0, 0, 20, 4, 0, 0)
924 #define PTA20_LPSPI1_SIN_I              NXP_S32_PINMUX(0, 0, 20, 0, 239, 3)
925 #define PTA21_LPSPI1_PCS0_O             NXP_S32_PINMUX(0, 0, 21, 4, 0, 0)
926 #define PTA21_LPSPI1_PCS0_I             NXP_S32_PINMUX(0, 0, 21, 0, 232, 3)
927 #define PTA28_LPSPI1_SCK_O              NXP_S32_PINMUX(0, 0, 28, 3, 0, 0)
928 #define PTA28_LPSPI1_SCK_I              NXP_S32_PINMUX(0, 0, 28, 0, 238, 4)
929 #define PTA29_LPSPI1_SIN_O              NXP_S32_PINMUX(0, 0, 29, 5, 0, 0)
930 #define PTA29_LPSPI1_SIN_I              NXP_S32_PINMUX(0, 0, 29, 0, 239, 4)
931 #define PTA30_LPSPI1_SOUT_O             NXP_S32_PINMUX(0, 0, 30, 3, 0, 0)
932 #define PTA30_LPSPI1_SOUT_I             NXP_S32_PINMUX(0, 0, 30, 0, 240, 5)
933 #define PTB14_LPSPI1_SCK_O              NXP_S32_PINMUX(0, 0, 46, 3, 0, 0)
934 #define PTB14_LPSPI1_SCK_I              NXP_S32_PINMUX(0, 0, 46, 0, 238, 2)
935 #define PTB15_LPSPI1_SIN_O              NXP_S32_PINMUX(0, 0, 47, 3, 0, 0)
936 #define PTB15_LPSPI1_SIN_I              NXP_S32_PINMUX(0, 0, 47, 0, 239, 1)
937 #define PTB16_LPSPI1_SOUT_O             NXP_S32_PINMUX(0, 0, 48, 3, 0, 0)
938 #define PTB16_LPSPI1_SOUT_I             NXP_S32_PINMUX(0, 0, 48, 0, 240, 2)
939 #define PTB17_LPSPI1_PCS3_O             NXP_S32_PINMUX(0, 0, 49, 3, 0, 0)
940 #define PTB17_LPSPI1_PCS3_I             NXP_S32_PINMUX(0, 0, 49, 0, 235, 1)
941 #define PTB18_LPSPI1_PCS1_O             NXP_S32_PINMUX(0, 0, 50, 4, 0, 0)
942 #define PTB18_LPSPI1_PCS1_I             NXP_S32_PINMUX(0, 0, 50, 0, 233, 2)
943 #define PTC6_LPSPI1_PCS1_O              NXP_S32_PINMUX(0, 0, 70, 3, 0, 0)
944 #define PTC6_LPSPI1_PCS1_I              NXP_S32_PINMUX(0, 0, 70, 0, 233, 4)
945 #define PTD2_LPSPI1_SOUT_O              NXP_S32_PINMUX(0, 0, 98, 3, 0, 0)
946 #define PTD2_LPSPI1_SOUT_I              NXP_S32_PINMUX(0, 0, 98, 0, 240, 1)
947 #define PTD3_LPSPI1_PCS0_O              NXP_S32_PINMUX(0, 0, 99, 3, 0, 0)
948 #define PTD3_LPSPI1_PCS0_I              NXP_S32_PINMUX(0, 0, 99, 0, 232, 1)
949 #define PTD4_LPSPI1_PCS1_O              NXP_S32_PINMUX(0, 0, 100, 3, 0, 0)
950 #define PTD4_LPSPI1_PCS1_I              NXP_S32_PINMUX(0, 0, 100, 0, 233, 6)
951 #define PTD20_LPSPI1_PCS2_O             NXP_S32_PINMUX(0, 0, 116, 5, 0, 0)
952 #define PTD20_LPSPI1_PCS2_I             NXP_S32_PINMUX(0, 0, 116, 0, 234, 1)
953 #define PTE4_LPSPI1_PCS1_O              NXP_S32_PINMUX(0, 0, 132, 2, 0, 0)
954 #define PTE4_LPSPI1_PCS1_I              NXP_S32_PINMUX(0, 0, 132, 0, 233, 5)
955 
956 /* CMP0 */
957 #define PTA4_CMP0_OUT                   NXP_S32_PINMUX(0, 0, 4, 4, 0, 0)
958 #define PTA11_CMP0_RRT                  NXP_S32_PINMUX(0, 0, 11, 5, 0, 0)
959 #define PTD14_CMP0_RRT                  NXP_S32_PINMUX(0, 0, 110, 6, 0, 0)
960 #define PTE3_CMP0_OUT                   NXP_S32_PINMUX(0, 0, 131, 7, 0, 0)
961 
962 /* JTAG */
963 #define PTA4_JTAG_TMSSWD_DIO_O          NXP_S32_PINMUX(0, 0, 4, 7, 0, 0)
964 #define PTA4_JTAG_TMSSWD_DIO_I          NXP_S32_PINMUX(0, 0, 4, 0, 186, 0)
965 #define PTC4_JTAG_TCKSWD_CLK            NXP_S32_PINMUX(0, 0, 68, 0, 184, 0)
966 #define PTC5_JTAG_TDI                   NXP_S32_PINMUX(0, 0, 69, 0, 185, 0)
967 
968 /* SYSTEM */
969 #define PTA12_CLKOUT_STANDBY            NXP_S32_PINMUX(0, 0, 12, 3, 0, 0)
970 #define PTB5_CLKOUT_RUN                 NXP_S32_PINMUX(0, 0, 37, 5, 0, 0)
971 #define PTD10_CLKOUT_RUN                NXP_S32_PINMUX(0, 0, 106, 6, 0, 0)
972 #define PTD14_CLKOUT_RUN                NXP_S32_PINMUX(0, 0, 110, 7, 0, 0)
973 #define PTE10_CLKOUT_STANDBY            NXP_S32_PINMUX(0, 0, 138, 5, 0, 0)
974 
975 /* LPSPI3 */
976 #define PTA6_LPSPI3_PCS1_O              NXP_S32_PINMUX(0, 0, 6, 6, 0, 0)
977 #define PTA6_LPSPI3_PCS1_I              NXP_S32_PINMUX(0, 0, 6, 0, 249, 5)
978 #define PTA9_LPSPI3_PCS0_O              NXP_S32_PINMUX(0, 0, 9, 6, 0, 0)
979 #define PTA9_LPSPI3_PCS0_I              NXP_S32_PINMUX(0, 0, 9, 0, 248, 3)
980 #define PTA17_LPSPI3_SOUT_O             NXP_S32_PINMUX(0, 0, 17, 6, 0, 0)
981 #define PTA17_LPSPI3_SOUT_I             NXP_S32_PINMUX(0, 0, 17, 0, 254, 2)
982 #define PTB12_LPSPI3_PCS3_O             NXP_S32_PINMUX(0, 0, 44, 1, 0, 0)
983 #define PTB12_LPSPI3_PCS3_I             NXP_S32_PINMUX(0, 0, 44, 0, 251, 1)
984 #define PTB13_LPSPI3_PCS2_O             NXP_S32_PINMUX(0, 0, 45, 1, 0, 0)
985 #define PTB13_LPSPI3_PCS2_I             NXP_S32_PINMUX(0, 0, 45, 0, 250, 1)
986 #define PTB17_LPSPI3_PCS0_O             NXP_S32_PINMUX(0, 0, 49, 6, 0, 0)
987 #define PTB17_LPSPI3_PCS0_I             NXP_S32_PINMUX(0, 0, 49, 0, 248, 2)
988 #define PTB22_LPSPI3_PCS1_O             NXP_S32_PINMUX(0, 0, 54, 3, 0, 0)
989 #define PTB22_LPSPI3_PCS1_I             NXP_S32_PINMUX(0, 0, 54, 0, 249, 4)
990 #define PTC2_LPSPI3_PCS2_O              NXP_S32_PINMUX(0, 0, 66, 3, 0, 0)
991 #define PTC2_LPSPI3_PCS2_I              NXP_S32_PINMUX(0, 0, 66, 0, 250, 4)
992 #define PTC16_LPSPI3_SIN_O              NXP_S32_PINMUX(0, 0, 80, 1, 0, 0)
993 #define PTC16_LPSPI3_SIN_I              NXP_S32_PINMUX(0, 0, 80, 0, 253, 3)
994 #define PTC17_LPSPI3_SCK_O              NXP_S32_PINMUX(0, 0, 81, 1, 0, 0)
995 #define PTC17_LPSPI3_SCK_I              NXP_S32_PINMUX(0, 0, 81, 0, 252, 3)
996 #define PTD0_LPSPI3_SOUT_O              NXP_S32_PINMUX(0, 0, 96, 3, 0, 0)
997 #define PTD0_LPSPI3_SOUT_I              NXP_S32_PINMUX(0, 0, 96, 0, 254, 1)
998 #define PTD1_LPSPI3_SCK_O               NXP_S32_PINMUX(0, 0, 97, 3, 0, 0)
999 #define PTD1_LPSPI3_SCK_I               NXP_S32_PINMUX(0, 0, 97, 0, 252, 1)
1000 #define PTD7_LPSPI3_PCS3_O              NXP_S32_PINMUX(0, 0, 103, 3, 0, 0)
1001 #define PTD7_LPSPI3_PCS3_I              NXP_S32_PINMUX(0, 0, 103, 0, 251, 5)
1002 #define PTD8_LPSPI3_SOUT_O              NXP_S32_PINMUX(0, 0, 104, 1, 0, 0)
1003 #define PTD8_LPSPI3_SOUT_I              NXP_S32_PINMUX(0, 0, 104, 0, 254, 3)
1004 #define PTD17_LPSPI3_PCS0_O             NXP_S32_PINMUX(0, 0, 113, 5, 0, 0)
1005 #define PTD17_LPSPI3_PCS0_I             NXP_S32_PINMUX(0, 0, 113, 0, 248, 1)
1006 #define PTD20_LPSPI3_SIN_O              NXP_S32_PINMUX(0, 0, 116, 6, 0, 0)
1007 #define PTD20_LPSPI3_SIN_I              NXP_S32_PINMUX(0, 0, 116, 0, 253, 2)
1008 #define PTE7_LPSPI3_SCK_O               NXP_S32_PINMUX(0, 0, 135, 6, 0, 0)
1009 #define PTE7_LPSPI3_SCK_I               NXP_S32_PINMUX(0, 0, 135, 0, 252, 2)
1010 #define PTE8_LPSPI3_PCS1_O              NXP_S32_PINMUX(0, 0, 136, 1, 0, 0)
1011 #define PTE8_LPSPI3_PCS1_I              NXP_S32_PINMUX(0, 0, 136, 0, 249, 1)
1012 #define PTE10_LPSPI3_SIN_O              NXP_S32_PINMUX(0, 0, 138, 2, 0, 0)
1013 #define PTE10_LPSPI3_SIN_I              NXP_S32_PINMUX(0, 0, 138, 0, 253, 1)
1014 
1015 /* CAN0 */
1016 #define PTA6_CAN0_RX                    NXP_S32_PINMUX(0, 0, 6, 0, 0, 2)
1017 #define PTA7_CAN0_TX                    NXP_S32_PINMUX(0, 0, 7, 4, 0, 0)
1018 #define PTA27_CAN0_TX                   NXP_S32_PINMUX(0, 0, 27, 5, 0, 0)
1019 #define PTA28_CAN0_RX                   NXP_S32_PINMUX(0, 0, 28, 0, 0, 4)
1020 #define PTB0_CAN0_RX                    NXP_S32_PINMUX(0, 0, 32, 0, 0, 3)
1021 #define PTB1_CAN0_TX                    NXP_S32_PINMUX(0, 0, 33, 5, 0, 0)
1022 #define PTC2_CAN0_RX                    NXP_S32_PINMUX(0, 0, 66, 0, 0, 1)
1023 #define PTC3_CAN0_TX                    NXP_S32_PINMUX(0, 0, 67, 3, 0, 0)
1024 
1025 /* LPUART3 */
1026 #define PTA6_LPUART3_RX                 NXP_S32_PINMUX(0, 0, 6, 0, 190, 2)
1027 #define PTA7_LPUART3_TX_O               NXP_S32_PINMUX(0, 0, 7, 1, 0, 0)
1028 #define PTA7_LPUART3_TX_I               NXP_S32_PINMUX(0, 0, 7, 0, 366, 1)
1029 #define PTD2_LPUART3_TX_O               NXP_S32_PINMUX(0, 0, 98, 6, 0, 0)
1030 #define PTD2_LPUART3_TX_I               NXP_S32_PINMUX(0, 0, 98, 0, 366, 2)
1031 #define PTD3_LPUART3_RX                 NXP_S32_PINMUX(0, 0, 99, 0, 190, 3)
1032 #define PTE15_LPUART3_RX                NXP_S32_PINMUX(0, 0, 143, 0, 190, 1)
1033 #define PTE16_LPUART3_TX_O              NXP_S32_PINMUX(0, 0, 144, 2, 0, 0)
1034 #define PTE16_LPUART3_TX_I              NXP_S32_PINMUX(0, 0, 144, 0, 366, 3)
1035 
1036 /* LPUART1 */
1037 #define PTA6_LPUART1_CTS                NXP_S32_PINMUX(0, 0, 6, 0, 361, 2)
1038 #define PTA7_LPUART1_RTS                NXP_S32_PINMUX(0, 0, 7, 5, 0, 0)
1039 #define PTA18_LPUART1_TX_O              NXP_S32_PINMUX(0, 0, 18, 3, 0, 0)
1040 #define PTA18_LPUART1_TX_I              NXP_S32_PINMUX(0, 0, 18, 0, 364, 4)
1041 #define PTA19_LPUART1_RX                NXP_S32_PINMUX(0, 0, 19, 0, 188, 5)
1042 #define PTB22_LPUART1_TX_O              NXP_S32_PINMUX(0, 0, 54, 5, 0, 0)
1043 #define PTB22_LPUART1_TX_I              NXP_S32_PINMUX(0, 0, 54, 0, 364, 5)
1044 #define PTB23_LPUART1_RX                NXP_S32_PINMUX(0, 0, 55, 0, 188, 4)
1045 #define PTC6_LPUART1_RX                 NXP_S32_PINMUX(0, 0, 70, 0, 188, 1)
1046 #define PTC7_LPUART1_TX_O               NXP_S32_PINMUX(0, 0, 71, 2, 0, 0)
1047 #define PTC7_LPUART1_TX_I               NXP_S32_PINMUX(0, 0, 71, 0, 364, 1)
1048 #define PTC8_LPUART1_RX                 NXP_S32_PINMUX(0, 0, 72, 0, 188, 2)
1049 #define PTC9_LPUART1_TX_O               NXP_S32_PINMUX(0, 0, 73, 2, 0, 0)
1050 #define PTC9_LPUART1_TX_I               NXP_S32_PINMUX(0, 0, 73, 0, 364, 2)
1051 #define PTD13_LPUART1_RX                NXP_S32_PINMUX(0, 0, 109, 0, 188, 3)
1052 #define PTD14_LPUART1_TX_O              NXP_S32_PINMUX(0, 0, 110, 3, 0, 0)
1053 #define PTD14_LPUART1_TX_I              NXP_S32_PINMUX(0, 0, 110, 0, 364, 3)
1054 #define PTE2_LPUART1_CTS                NXP_S32_PINMUX(0, 0, 130, 0, 361, 1)
1055 #define PTE6_LPUART1_RTS                NXP_S32_PINMUX(0, 0, 134, 3, 0, 0)
1056 #define PTE15_LPUART1_CTS               NXP_S32_PINMUX(0, 0, 143, 0, 361, 3)
1057 #define PTE16_LPUART1_RTS               NXP_S32_PINMUX(0, 0, 144, 5, 0, 0)
1058 
1059 /* LPSPI2 */
1060 #define PTA8_LPSPI2_SOUT_O              NXP_S32_PINMUX(0, 0, 8, 3, 0, 0)
1061 #define PTA8_LPSPI2_SOUT_I              NXP_S32_PINMUX(0, 0, 8, 0, 247, 1)
1062 #define PTA9_LPSPI2_PCS0_O              NXP_S32_PINMUX(0, 0, 9, 3, 0, 0)
1063 #define PTA9_LPSPI2_PCS0_I              NXP_S32_PINMUX(0, 0, 9, 0, 241, 1)
1064 #define PTA15_LPSPI2_PCS3_O             NXP_S32_PINMUX(0, 0, 15, 4, 0, 0)
1065 #define PTA15_LPSPI2_PCS3_I             NXP_S32_PINMUX(0, 0, 15, 0, 244, 1)
1066 #define PTA21_LPSPI2_PCS2_O             NXP_S32_PINMUX(0, 0, 21, 1, 0, 0)
1067 #define PTA21_LPSPI2_PCS2_I             NXP_S32_PINMUX(0, 0, 21, 0, 243, 1)
1068 #define PTB2_LPSPI2_SIN_O               NXP_S32_PINMUX(0, 0, 34, 3, 0, 0)
1069 #define PTB2_LPSPI2_SIN_I               NXP_S32_PINMUX(0, 0, 34, 0, 246, 2)
1070 #define PTB3_LPSPI2_SOUT_O              NXP_S32_PINMUX(0, 0, 35, 3, 0, 0)
1071 #define PTB3_LPSPI2_SOUT_I              NXP_S32_PINMUX(0, 0, 35, 0, 247, 2)
1072 #define PTB25_LPSPI2_PCS0_O             NXP_S32_PINMUX(0, 0, 57, 5, 0, 0)
1073 #define PTB25_LPSPI2_PCS0_I             NXP_S32_PINMUX(0, 0, 57, 0, 241, 4)
1074 #define PTB27_LPSPI2_SOUT_O             NXP_S32_PINMUX(0, 0, 59, 5, 0, 0)
1075 #define PTB27_LPSPI2_SOUT_I             NXP_S32_PINMUX(0, 0, 59, 0, 247, 3)
1076 #define PTB28_LPSPI2_SIN_O              NXP_S32_PINMUX(0, 0, 60, 5, 0, 0)
1077 #define PTB28_LPSPI2_SIN_I              NXP_S32_PINMUX(0, 0, 60, 0, 246, 3)
1078 #define PTB29_LPSPI2_SCK_O              NXP_S32_PINMUX(0, 0, 61, 5, 0, 0)
1079 #define PTB29_LPSPI2_SCK_I              NXP_S32_PINMUX(0, 0, 61, 0, 245, 3)
1080 #define PTC10_LPSPI2_PCS1_O             NXP_S32_PINMUX(0, 0, 74, 4, 0, 0)
1081 #define PTC10_LPSPI2_PCS1_I             NXP_S32_PINMUX(0, 0, 74, 0, 242, 3)
1082 #define PTC12_LPSPI2_PCS1_O             NXP_S32_PINMUX(0, 0, 76, 4, 0, 0)
1083 #define PTC12_LPSPI2_PCS1_I             NXP_S32_PINMUX(0, 0, 76, 0, 242, 4)
1084 #define PTC14_LPSPI2_PCS0_O             NXP_S32_PINMUX(0, 0, 78, 3, 0, 0)
1085 #define PTC14_LPSPI2_PCS0_I             NXP_S32_PINMUX(0, 0, 78, 0, 241, 2)
1086 #define PTC15_LPSPI2_SCK_O              NXP_S32_PINMUX(0, 0, 79, 3, 0, 0)
1087 #define PTC15_LPSPI2_SCK_I              NXP_S32_PINMUX(0, 0, 79, 0, 245, 2)
1088 #define PTC19_LPSPI2_PCS1_O             NXP_S32_PINMUX(0, 0, 83, 5, 0, 0)
1089 #define PTC19_LPSPI2_PCS1_I             NXP_S32_PINMUX(0, 0, 83, 0, 242, 2)
1090 #define PTE10_LPSPI2_PCS1_O             NXP_S32_PINMUX(0, 0, 138, 3, 0, 0)
1091 #define PTE10_LPSPI2_PCS1_I             NXP_S32_PINMUX(0, 0, 138, 0, 242, 1)
1092 #define PTE11_LPSPI2_PCS0_O             NXP_S32_PINMUX(0, 0, 139, 2, 0, 0)
1093 #define PTE11_LPSPI2_PCS0_I             NXP_S32_PINMUX(0, 0, 139, 0, 241, 3)
1094 #define PTE13_LPSPI2_PCS2_O             NXP_S32_PINMUX(0, 0, 141, 3, 0, 0)
1095 #define PTE13_LPSPI2_PCS0_O             NXP_S32_PINMUX(0, 0, 141, 5, 0, 0)
1096 #define PTE13_LPSPI2_PCS0_I             NXP_S32_PINMUX(0, 0, 141, 0, 241, 5)
1097 #define PTE13_LPSPI2_PCS2_I             NXP_S32_PINMUX(0, 0, 141, 0, 243, 2)
1098 #define PTE15_LPSPI2_SCK_O              NXP_S32_PINMUX(0, 0, 143, 3, 0, 0)
1099 #define PTE15_LPSPI2_SCK_I              NXP_S32_PINMUX(0, 0, 143, 0, 245, 1)
1100 #define PTE16_LPSPI2_SIN_O              NXP_S32_PINMUX(0, 0, 144, 3, 0, 0)
1101 #define PTE16_LPSPI2_SIN_I              NXP_S32_PINMUX(0, 0, 144, 0, 246, 1)
1102 
1103 /* EMIOS_2 */
1104 #define PTA8_EMIOS_2_CH7_H_O            NXP_S32_PINMUX(0, 0, 8, 6, 0, 0)
1105 #define PTA8_EMIOS_2_CH7_H_I            NXP_S32_PINMUX(0, 0, 8, 0, 119, 3)
1106 #define PTA14_EMIOS_2_CH18_Y_O          NXP_S32_PINMUX(0, 0, 14, 4, 0, 0)
1107 #define PTA14_EMIOS_2_CH18_Y_I          NXP_S32_PINMUX(0, 0, 14, 0, 130, 4)
1108 #define PTA18_EMIOS_2_CH0_X_O           NXP_S32_PINMUX(0, 0, 18, 6, 0, 0)
1109 #define PTA18_EMIOS_2_CH0_X_I           NXP_S32_PINMUX(0, 0, 18, 0, 112, 2)
1110 #define PTA19_EMIOS_2_CH1_H_O           NXP_S32_PINMUX(0, 0, 19, 6, 0, 0)
1111 #define PTA19_EMIOS_2_CH1_H_I           NXP_S32_PINMUX(0, 0, 19, 0, 113, 2)
1112 #define PTA20_EMIOS_2_CH2_H_O           NXP_S32_PINMUX(0, 0, 20, 6, 0, 0)
1113 #define PTA20_EMIOS_2_CH2_H_I           NXP_S32_PINMUX(0, 0, 20, 0, 114, 2)
1114 #define PTA21_EMIOS_2_CH3_H_O           NXP_S32_PINMUX(0, 0, 21, 6, 0, 0)
1115 #define PTA21_EMIOS_2_CH3_H_I           NXP_S32_PINMUX(0, 0, 21, 0, 115, 2)
1116 #define PTA25_EMIOS_2_CH8_X             NXP_S32_PINMUX(0, 0, 23, 0, 120, 2)
1117 #define PTA27_EMIOS_2_CH10_H_O          NXP_S32_PINMUX(0, 0, 27, 6, 0, 0)
1118 #define PTA27_EMIOS_2_CH10_H_I          NXP_S32_PINMUX(0, 0, 27, 0, 122, 2)
1119 #define PTA28_EMIOS_2_CH11_H_O          NXP_S32_PINMUX(0, 0, 28, 6, 0, 0)
1120 #define PTA28_EMIOS_2_CH11_H_I          NXP_S32_PINMUX(0, 0, 28, 0, 123, 2)
1121 #define PTA29_EMIOS_2_CH12_H_O          NXP_S32_PINMUX(0, 0, 29, 6, 0, 0)
1122 #define PTA29_EMIOS_2_CH12_H_I          NXP_S32_PINMUX(0, 0, 29, 0, 124, 1)
1123 #define PTA30_EMIOS_2_CH13_H_O          NXP_S32_PINMUX(0, 0, 30, 6, 0, 0)
1124 #define PTA30_EMIOS_2_CH13_H_I          NXP_S32_PINMUX(0, 0, 30, 0, 125, 2)
1125 #define PTB18_EMIOS_2_CH14_H_O          NXP_S32_PINMUX(0, 0, 50, 5, 0, 0)
1126 #define PTB18_EMIOS_2_CH14_H_I          NXP_S32_PINMUX(0, 0, 50, 0, 126, 2)
1127 #define PTB19_EMIOS_2_CH15_H_O          NXP_S32_PINMUX(0, 0, 51, 5, 0, 0)
1128 #define PTB19_EMIOS_2_CH15_H_I          NXP_S32_PINMUX(0, 0, 51, 0, 127, 3)
1129 #define PTB20_EMIOS_2_CH16_X_O          NXP_S32_PINMUX(0, 0, 52, 5, 0, 0)
1130 #define PTB20_EMIOS_2_CH16_X_I          NXP_S32_PINMUX(0, 0, 52, 0, 128, 2)
1131 #define PTB21_EMIOS_2_CH17_Y_O          NXP_S32_PINMUX(0, 0, 53, 5, 0, 0)
1132 #define PTB21_EMIOS_2_CH17_Y_I          NXP_S32_PINMUX(0, 0, 53, 0, 129, 2)
1133 #define PTB22_EMIOS_2_CH18_Y_O          NXP_S32_PINMUX(0, 0, 54, 4, 0, 0)
1134 #define PTB22_EMIOS_2_CH18_Y_I          NXP_S32_PINMUX(0, 0, 54, 0, 130, 2)
1135 #define PTB23_EMIOS_2_CH19_Y_O          NXP_S32_PINMUX(0, 0, 55, 4, 0, 0)
1136 #define PTB23_EMIOS_2_CH19_Y_I          NXP_S32_PINMUX(0, 0, 55, 0, 131, 2)
1137 #define PTB24_EMIOS_2_CH20_Y_O          NXP_S32_PINMUX(0, 0, 56, 4, 0, 0)
1138 #define PTB24_EMIOS_2_CH20_Y_I          NXP_S32_PINMUX(0, 0, 56, 0, 132, 2)
1139 #define PTB25_EMIOS_2_CH21_Y_O          NXP_S32_PINMUX(0, 0, 57, 4, 0, 0)
1140 #define PTB25_EMIOS_2_CH21_Y_I          NXP_S32_PINMUX(0, 0, 57, 0, 133, 2)
1141 #define PTB26_EMIOS_2_CH22_X_O          NXP_S32_PINMUX(0, 0, 58, 4, 0, 0)
1142 #define PTB26_EMIOS_2_CH22_X_I          NXP_S32_PINMUX(0, 0, 58, 0, 134, 2)
1143 #define PTB27_EMIOS_2_CH23_X_O          NXP_S32_PINMUX(0, 0, 59, 4, 0, 0)
1144 #define PTB27_EMIOS_2_CH23_X_I          NXP_S32_PINMUX(0, 0, 59, 0, 135, 2)
1145 #define PTB28_EMIOS_2_CH10_H_O          NXP_S32_PINMUX(0, 0, 60, 4, 0, 0)
1146 #define PTB28_EMIOS_2_CH10_H_I          NXP_S32_PINMUX(0, 0, 60, 0, 122, 3)
1147 #define PTB29_EMIOS_2_CH11_H_O          NXP_S32_PINMUX(0, 0, 61, 4, 0, 0)
1148 #define PTB29_EMIOS_2_CH11_H_I          NXP_S32_PINMUX(0, 0, 61, 0, 123, 3)
1149 #define PTC16_EMIOS_2_CH9_H_O           NXP_S32_PINMUX(0, 0, 80, 3, 0, 0)
1150 #define PTC16_EMIOS_2_CH9_H_I           NXP_S32_PINMUX(0, 0, 80, 0, 121, 4)
1151 #define PTC18_EMIOS_2_CH12_H_O          NXP_S32_PINMUX(0, 0, 82, 4, 0, 0)
1152 #define PTC18_EMIOS_2_CH12_H_I          NXP_S32_PINMUX(0, 0, 82, 0, 124, 3)
1153 #define PTC19_EMIOS_2_CH13_H_O          NXP_S32_PINMUX(0, 0, 83, 4, 0, 0)
1154 #define PTC19_EMIOS_2_CH13_H_I          NXP_S32_PINMUX(0, 0, 83, 0, 125, 3)
1155 #define PTC20_EMIOS_2_CH14_H_O          NXP_S32_PINMUX(0, 0, 84, 4, 0, 0)
1156 #define PTC20_EMIOS_2_CH14_H_I          NXP_S32_PINMUX(0, 0, 84, 0, 126, 3)
1157 #define PTC21_EMIOS_2_CH15_H_O          NXP_S32_PINMUX(0, 0, 85, 4, 0, 0)
1158 #define PTC21_EMIOS_2_CH15_H_I          NXP_S32_PINMUX(0, 0, 85, 0, 127, 5)
1159 #define PTC24_EMIOS_2_CH0_X_O           NXP_S32_PINMUX(0, 0, 88, 4, 0, 0)
1160 #define PTC24_EMIOS_2_CH0_X_I           NXP_S32_PINMUX(0, 0, 88, 0, 112, 5)
1161 #define PTC25_EMIOS_2_CH1_H_O           NXP_S32_PINMUX(0, 0, 89, 4, 0, 0)
1162 #define PTC25_EMIOS_2_CH1_H_I           NXP_S32_PINMUX(0, 0, 89, 0, 113, 3)
1163 #define PTC26_EMIOS_2_CH2_H_O           NXP_S32_PINMUX(0, 0, 90, 4, 0, 0)
1164 #define PTC26_EMIOS_2_CH2_H_I           NXP_S32_PINMUX(0, 0, 90, 0, 114, 3)
1165 #define PTC27_EMIOS_2_CH3_H_O           NXP_S32_PINMUX(0, 0, 91, 4, 0, 0)
1166 #define PTC27_EMIOS_2_CH3_H_I           NXP_S32_PINMUX(0, 0, 91, 0, 115, 3)
1167 #define PTC29_EMIOS_2_CH4_H_O           NXP_S32_PINMUX(0, 0, 93, 4, 0, 0)
1168 #define PTC29_EMIOS_2_CH4_H_I           NXP_S32_PINMUX(0, 0, 93, 0, 116, 2)
1169 #define PTC30_EMIOS_2_CH5_H_O           NXP_S32_PINMUX(0, 0, 94, 4, 0, 0)
1170 #define PTC30_EMIOS_2_CH5_H_I           NXP_S32_PINMUX(0, 0, 94, 0, 117, 3)
1171 #define PTC31_EMIOS_2_CH6_H_O           NXP_S32_PINMUX(0, 0, 95, 5, 0, 0)
1172 #define PTC31_EMIOS_2_CH6_H_I           NXP_S32_PINMUX(0, 0, 95, 0, 118, 2)
1173 #define PTD20_EMIOS_2_CH0_X_O           NXP_S32_PINMUX(0, 0, 116, 4, 0, 0)
1174 #define PTD20_EMIOS_2_CH0_X_I           NXP_S32_PINMUX(0, 0, 116, 0, 112, 3)
1175 #define PTD21_EMIOS_2_CH8_X_O           NXP_S32_PINMUX(0, 0, 117, 4, 0, 0)
1176 #define PTD21_EMIOS_2_CH8_X_I           NXP_S32_PINMUX(0, 0, 117, 0, 120, 3)
1177 #define PTD22_EMIOS_2_CH22_X_O          NXP_S32_PINMUX(0, 0, 118, 4, 0, 0)
1178 #define PTD22_EMIOS_2_CH22_X_I          NXP_S32_PINMUX(0, 0, 118, 0, 134, 3)
1179 #define PTD23_EMIOS_2_CH23_X_O          NXP_S32_PINMUX(0, 0, 119, 4, 0, 0)
1180 #define PTD23_EMIOS_2_CH23_X_I          NXP_S32_PINMUX(0, 0, 119, 0, 135, 3)
1181 #define PTD26_EMIOS_2_CH7_H_O           NXP_S32_PINMUX(0, 0, 122, 4, 0, 0)
1182 #define PTD26_EMIOS_2_CH7_H_I           NXP_S32_PINMUX(0, 0, 122, 0, 119, 1)
1183 #define PTD27_EMIOS_2_CH9_H_O           NXP_S32_PINMUX(0, 0, 123, 4, 0, 0)
1184 #define PTD27_EMIOS_2_CH9_H_I           NXP_S32_PINMUX(0, 0, 123, 0, 121, 3)
1185 #define PTD28_EMIOS_2_CH0_X_O           NXP_S32_PINMUX(0, 0, 124, 4, 0, 0)
1186 #define PTD28_EMIOS_2_CH0_X_I           NXP_S32_PINMUX(0, 0, 124, 0, 112, 4)
1187 #define PTD29_EMIOS_2_CH8_X_O           NXP_S32_PINMUX(0, 0, 125, 4, 0, 0)
1188 #define PTD29_EMIOS_2_CH8_X_I           NXP_S32_PINMUX(0, 0, 125, 0, 120, 4)
1189 #define PTD30_EMIOS_2_CH16_X_O          NXP_S32_PINMUX(0, 0, 126, 4, 0, 0)
1190 #define PTD30_EMIOS_2_CH16_X_I          NXP_S32_PINMUX(0, 0, 126, 0, 128, 3)
1191 #define PTD31_EMIOS_2_CH22_X_O          NXP_S32_PINMUX(0, 0, 127, 4, 0, 0)
1192 #define PTD31_EMIOS_2_CH22_X_I          NXP_S32_PINMUX(0, 0, 127, 0, 134, 4)
1193 #define PTE17_EMIOS_2_CH23_X_O          NXP_S32_PINMUX(0, 0, 145, 4, 0, 0)
1194 #define PTE17_EMIOS_2_CH23_X_I          NXP_S32_PINMUX(0, 0, 145, 0, 135, 4)
1195 #define PTE18_EMIOS_2_CH17_Y_O          NXP_S32_PINMUX(0, 0, 146, 4, 0, 0)
1196 #define PTE18_EMIOS_2_CH17_Y_I          NXP_S32_PINMUX(0, 0, 146, 0, 129, 4)
1197 #define PTE21_EMIOS_2_CH19_Y_O          NXP_S32_PINMUX(0, 0, 149, 4, 0, 0)
1198 #define PTE21_EMIOS_2_CH19_Y_I          NXP_S32_PINMUX(0, 0, 149, 0, 131, 4)
1199 #define PTE22_EMIOS_2_CH20_Y_O          NXP_S32_PINMUX(0, 0, 150, 4, 0, 0)
1200 #define PTE22_EMIOS_2_CH20_Y_I          NXP_S32_PINMUX(0, 0, 150, 0, 132, 4)
1201 #define PTE23_EMIOS_2_CH21_Y_O          NXP_S32_PINMUX(0, 0, 151, 4, 0, 0)
1202 #define PTE23_EMIOS_2_CH21_Y_I          NXP_S32_PINMUX(0, 0, 151, 0, 133, 4)
1203 #define PTE24_EMIOS_2_CH4_H_O           NXP_S32_PINMUX(0, 0, 152, 4, 0, 0)
1204 #define PTE24_EMIOS_2_CH4_H_I           NXP_S32_PINMUX(0, 0, 152, 0, 116, 3)
1205 #define PTE25_EMIOS_2_CH5_H_O           NXP_S32_PINMUX(0, 0, 153, 4, 0, 0)
1206 #define PTE25_EMIOS_2_CH5_H_I           NXP_S32_PINMUX(0, 0, 153, 0, 117, 2)
1207 #define PTE26_EMIOS_2_CH6_H_O           NXP_S32_PINMUX(0, 0, 154, 4, 0, 0)
1208 #define PTE26_EMIOS_2_CH6_H_I           NXP_S32_PINMUX(0, 0, 154, 0, 118, 3)
1209 
1210 /* LPUART2 */
1211 #define PTA8_LPUART2_RX                 NXP_S32_PINMUX(0, 0, 8, 0, 189, 3)
1212 #define PTA9_LPUART2_TX_O               NXP_S32_PINMUX(0, 0, 9, 2, 0, 0)
1213 #define PTA9_LPUART2_TX_I               NXP_S32_PINMUX(0, 0, 9, 0, 365, 1)
1214 #define PTA29_LPUART2_TX_O              NXP_S32_PINMUX(0, 0, 29, 4, 0, 0)
1215 #define PTA29_LPUART2_TX_I              NXP_S32_PINMUX(0, 0, 29, 0, 365, 5)
1216 #define PTA30_LPUART2_RX                NXP_S32_PINMUX(0, 0, 30, 0, 189, 4)
1217 #define PTC15_LPUART2_TX_O              NXP_S32_PINMUX(0, 0, 79, 5, 0, 0)
1218 #define PTC15_LPUART2_TX_I              NXP_S32_PINMUX(0, 0, 79, 0, 365, 2)
1219 #define PTC16_LPUART2_RX                NXP_S32_PINMUX(0, 0, 80, 0, 189, 5)
1220 #define PTD6_LPUART2_RX                 NXP_S32_PINMUX(0, 0, 102, 0, 189, 1)
1221 #define PTD7_LPUART2_TX_O               NXP_S32_PINMUX(0, 0, 103, 2, 0, 0)
1222 #define PTD7_LPUART2_TX_I               NXP_S32_PINMUX(0, 0, 103, 0, 365, 3)
1223 #define PTD11_LPUART2_CTS               NXP_S32_PINMUX(0, 0, 107, 0, 362, 1)
1224 #define PTD12_LPUART2_RTS               NXP_S32_PINMUX(0, 0, 108, 3, 0, 0)
1225 #define PTD15_LPUART2_CTS               NXP_S32_PINMUX(0, 0, 111, 0, 362, 2)
1226 #define PTD16_LPUART2_RTS               NXP_S32_PINMUX(0, 0, 112, 6, 0, 0)
1227 #define PTD17_LPUART2_RX                NXP_S32_PINMUX(0, 0, 113, 0, 189, 2)
1228 #define PTE3_LPUART2_RTS                NXP_S32_PINMUX(0, 0, 131, 5, 0, 0)
1229 #define PTE9_LPUART2_CTS                NXP_S32_PINMUX(0, 0, 137, 0, 362, 3)
1230 #define PTE12_LPUART2_TX_O              NXP_S32_PINMUX(0, 0, 140, 3, 0, 0)
1231 #define PTE12_LPUART2_TX_I              NXP_S32_PINMUX(0, 0, 140, 0, 365, 4)
1232 
1233 /* CMP2 */
1234 #define PTA9_CMP2_OUT                   NXP_S32_PINMUX(0, 0, 9, 7, 0, 0)
1235 #define PTC5_CMP2_RRT                   NXP_S32_PINMUX(0, 0, 69, 5, 0, 0)
1236 
1237 /* JTAGTRACENOETM */
1238 #define PTA10_JTAG_TDOTRACENOETM_SWO    NXP_S32_PINMUX(0, 0, 10, 7, 0, 0)
1239 
1240 /* CAN1 */
1241 #define PTA11_CAN1_TX                   NXP_S32_PINMUX(0, 0, 11, 1, 0, 0)
1242 #define PTA12_CAN1_RX                   NXP_S32_PINMUX(0, 0, 12, 0, 1, 2)
1243 #define PTB22_CAN1_TX                   NXP_S32_PINMUX(0, 0, 54, 1, 0, 0)
1244 #define PTB23_CAN1_RX                   NXP_S32_PINMUX(0, 0, 55, 0, 1, 4)
1245 #define PTC8_CAN1_TX                    NXP_S32_PINMUX(0, 0, 72, 3, 0, 0)
1246 #define PTC9_CAN1_RX                    NXP_S32_PINMUX(0, 0, 73, 0, 1, 1)
1247 
1248 /* CMP1 */
1249 #define PTA12_CMP1_OUT                  NXP_S32_PINMUX(0, 0, 12, 7, 0, 0)
1250 #define PTE15_CMP1_RRT                  NXP_S32_PINMUX(0, 0, 143, 5, 0, 0)
1251 
1252 /* LPUART11 */
1253 #define PTA12_LPUART11_RX               NXP_S32_PINMUX(0, 0, 12, 0, 198, 2)
1254 #define PTA13_LPUART11_TX_O             NXP_S32_PINMUX(0, 0, 13, 7, 0, 0)
1255 #define PTA13_LPUART11_TX_I             NXP_S32_PINMUX(0, 0, 13, 0, 374, 1)
1256 #define PTC10_LPUART11_TX_O             NXP_S32_PINMUX(0, 0, 74, 2, 0, 0)
1257 #define PTC10_LPUART11_TX_I             NXP_S32_PINMUX(0, 0, 74, 0, 374, 2)
1258 #define PTC11_LPUART11_RX               NXP_S32_PINMUX(0, 0, 75, 0, 198, 1)
1259 
1260 /* LPUART6 */
1261 #define PTA15_LPUART6_RX                NXP_S32_PINMUX(0, 0, 15, 0, 193, 2)
1262 #define PTA16_LPUART6_TX_O              NXP_S32_PINMUX(0, 0, 16, 5, 0, 0)
1263 #define PTA16_LPUART6_TX_I              NXP_S32_PINMUX(0, 0, 16, 0, 369, 1)
1264 #define PTB29_LPUART6_TX_O              NXP_S32_PINMUX(0, 0, 61, 1, 0, 0)
1265 #define PTB29_LPUART6_TX_I              NXP_S32_PINMUX(0, 0, 61, 0, 369, 3)
1266 #define PTC18_LPUART6_RX                NXP_S32_PINMUX(0, 0, 82, 0, 193, 4)
1267 #define PTD8_LPUART6_RX                 NXP_S32_PINMUX(0, 0, 104, 0, 193, 1)
1268 #define PTD9_LPUART6_TX_O               NXP_S32_PINMUX(0, 0, 105, 4, 0, 0)
1269 #define PTD9_LPUART6_TX_I               NXP_S32_PINMUX(0, 0, 105, 0, 369, 2)
1270 
1271 /* LPUART4 */
1272 #define PTA17_LPUART4_TX_O              NXP_S32_PINMUX(0, 0, 17, 4, 0, 0)
1273 #define PTA17_LPUART4_TX_I              NXP_S32_PINMUX(0, 0, 17, 0, 367, 1)
1274 #define PTB16_LPUART4_TX_O              NXP_S32_PINMUX(0, 0, 48, 4, 0, 0)
1275 #define PTB16_LPUART4_TX_I              NXP_S32_PINMUX(0, 0, 48, 0, 367, 2)
1276 #define PTB17_LPUART4_RX                NXP_S32_PINMUX(0, 0, 49, 0, 191, 3)
1277 #define PTE7_LPUART4_RX                 NXP_S32_PINMUX(0, 0, 135, 0, 191, 4)
1278 #define PTE10_LPUART4_RX                NXP_S32_PINMUX(0, 0, 138, 0, 191, 2)
1279 #define PTE11_LPUART4_TX_O              NXP_S32_PINMUX(0, 0, 139, 1, 0, 0)
1280 #define PTE11_LPUART4_TX_I              NXP_S32_PINMUX(0, 0, 139, 0, 367, 3)
1281 
1282 /* EMAC */
1283 #define PTA27_EMAC_PPS1_O               NXP_S32_PINMUX(0, 0, 27, 3, 0, 0)
1284 #define PTA27_EMAC_PPS1_I               NXP_S32_PINMUX(0, 0, 27, 0, 145, 3)
1285 #define PTA29_EMAC_PPS2_O               NXP_S32_PINMUX(0, 0, 29, 3, 0, 0)
1286 #define PTA29_EMAC_PPS2_I               NXP_S32_PINMUX(0, 0, 29, 0, 146, 3)
1287 #define PTB4_EMAC_MII_RMII_TXD1         NXP_S32_PINMUX(0, 0, 36, 1, 0, 0)
1288 #define PTB4_EMAC_MII_RMII_MDIO_O       NXP_S32_PINMUX(0, 0, 36, 5, 0, 0)
1289 #define PTB4_EMAC_MII_RMII_MDIO_I       NXP_S32_PINMUX(0, 0, 36, 0, 291, 1)
1290 #define PTB5_EMAC_MII_RMII_TXD0         NXP_S32_PINMUX(0, 0, 37, 1, 0, 0)
1291 #define PTB5_EMAC_MII_RMII_MDC          NXP_S32_PINMUX(0, 0, 37, 7, 0, 0)
1292 #define PTB22_EMAC_MII_CRS              NXP_S32_PINMUX(0, 0, 54, 0, 290, 1)
1293 #define PTB23_EMAC_MII_COL              NXP_S32_PINMUX(0, 0, 55, 0, 289, 1)
1294 #define PTB28_EMAC_PPS3_O               NXP_S32_PINMUX(0, 0, 60, 7, 0, 0)
1295 #define PTB28_EMAC_PPS3_I               NXP_S32_PINMUX(0, 0, 60, 0, 147, 2)
1296 #define PTC0_EMAC_MII_RMII_RXD0         NXP_S32_PINMUX(0, 0, 64, 0, 294, 2)
1297 #define PTC0_EMAC_MII_RMII_RXD1         NXP_S32_PINMUX(0, 0, 64, 0, 295, 1)
1298 #define PTC0_EMAC_MII_RMII_TX_CLK       NXP_S32_PINMUX(0, 0, 64, 0, 296, 4)
1299 #define PTC1_EMAC_MII_RMII_RXD0         NXP_S32_PINMUX(0, 0, 65, 0, 294, 1)
1300 #define PTC1_EMAC_MII_RMII_RXD1         NXP_S32_PINMUX(0, 0, 65, 0, 295, 2)
1301 #define PTC1_EMAC_MII_RX_CLK            NXP_S32_PINMUX(0, 0, 65, 0, 300, 3)
1302 #define PTC2_EMAC_MII_RMII_TXD1         NXP_S32_PINMUX(0, 0, 66, 1, 0, 0)
1303 #define PTC2_EMAC_MII_RMII_TXD0         NXP_S32_PINMUX(0, 0, 66, 5, 0, 0)
1304 #define PTC14_EMAC_MII_COL              NXP_S32_PINMUX(0, 0, 78, 0, 289, 2)
1305 #define PTC14_EMAC_MII_RMII_RX_ER       NXP_S32_PINMUX(0, 0, 78, 0, 293, 2)
1306 #define PTC14_EMAC_MII_RXD3             NXP_S32_PINMUX(0, 0, 78, 0, 302, 2)
1307 #define PTC15_EMAC_MII_CRS              NXP_S32_PINMUX(0, 0, 79, 0, 290, 2)
1308 #define PTC15_EMAC_MII_RMII_RX_DV       NXP_S32_PINMUX(0, 0, 79, 0, 292, 2)
1309 #define PTC15_EMAC_MII_RXD2             NXP_S32_PINMUX(0, 0, 79, 0, 301, 2)
1310 #define PTC16_EMAC_MII_RMII_RX_ER       NXP_S32_PINMUX(0, 0, 80, 0, 293, 1)
1311 #define PTC17_EMAC_MII_RMII_RX_DV       NXP_S32_PINMUX(0, 0, 81, 0, 292, 1)
1312 #define PTD5_EMAC_MII_TXD2              NXP_S32_PINMUX(0, 0, 101, 1, 0, 0)
1313 #define PTD5_EMAC_MII_TXD3              NXP_S32_PINMUX(0, 0, 101, 5, 0, 0)
1314 #define PTD5_EMAC_MII_RX_CLK            NXP_S32_PINMUX(0, 0, 101, 0, 300, 2)
1315 #define PTD6_EMAC_MII_TXD3              NXP_S32_PINMUX(0, 0, 102, 1, 0, 0)
1316 #define PTD6_EMAC_MII_TXD2              NXP_S32_PINMUX(0, 0, 102, 5, 0, 0)
1317 #define PTD6_EMAC_MII_RMII_TX_CLK       NXP_S32_PINMUX(0, 0, 102, 0, 296, 2)
1318 #define PTD7_EMAC_MII_RMII_TXD0         NXP_S32_PINMUX(0, 0, 103, 1, 0, 0)
1319 #define PTD7_EMAC_MII_RMII_TXD1         NXP_S32_PINMUX(0, 0, 103, 5, 0, 0)
1320 #define PTD8_EMAC_MII_RMII_RXD1         NXP_S32_PINMUX(0, 0, 104, 0, 295, 3)
1321 #define PTD8_EMAC_MII_RXD3              NXP_S32_PINMUX(0, 0, 104, 0, 302, 1)
1322 #define PTD9_EMAC_MII_RMII_RXD0         NXP_S32_PINMUX(0, 0, 105, 0, 294, 3)
1323 #define PTD9_EMAC_MII_RXD2              NXP_S32_PINMUX(0, 0, 105, 0, 301, 1)
1324 #define PTD10_EMAC_MII_TXD3             NXP_S32_PINMUX(0, 0, 106, 1, 0, 0)
1325 #define PTD10_EMAC_MII_RX_CLK           NXP_S32_PINMUX(0, 0, 106, 0, 300, 1)
1326 #define PTD11_EMAC_MII_TXD2             NXP_S32_PINMUX(0, 0, 107, 1, 0, 0)
1327 #define PTD11_EMAC_MII_RMII_TX_EN       NXP_S32_PINMUX(0, 0, 107, 3, 0, 0)
1328 #define PTD11_EMAC_MII_RMII_TX_CLK      NXP_S32_PINMUX(0, 0, 107, 0, 296, 1)
1329 #define PTD12_EMAC_MII_RMII_TX_EN       NXP_S32_PINMUX(0, 0, 108, 5, 0, 0)
1330 #define PTD12_EMAC_MII_RMII_TX_CLK      NXP_S32_PINMUX(0, 0, 108, 0, 296, 3)
1331 #define PTD13_EMAC_PPS1_O               NXP_S32_PINMUX(0, 0, 109, 5, 0, 0)
1332 #define PTD13_EMAC_PPS1_I               NXP_S32_PINMUX(0, 0, 109, 0, 145, 2)
1333 #define PTD14_EMAC_PPS0_O               NXP_S32_PINMUX(0, 0, 110, 5, 0, 0)
1334 #define PTD14_EMAC_PPS0_I               NXP_S32_PINMUX(0, 0, 110, 0, 144, 2)
1335 #define PTD15_EMAC_PPS2_O               NXP_S32_PINMUX(0, 0, 111, 5, 0, 0)
1336 #define PTD15_EMAC_PPS2_I               NXP_S32_PINMUX(0, 0, 111, 0, 146, 2)
1337 #define PTD16_EMAC_MII_RMII_MDIO_O      NXP_S32_PINMUX(0, 0, 112, 3, 0, 0)
1338 #define PTD16_EMAC_MII_RMII_MDIO_I      NXP_S32_PINMUX(0, 0, 112, 0, 291, 2)
1339 #define PTD17_EMAC_MII_RMII_MDC         NXP_S32_PINMUX(0, 0, 113, 3, 0, 0)
1340 #define PTD17_EMAC_PPS2_O               NXP_S32_PINMUX(0, 0, 113, 7, 0, 0)
1341 #define PTD17_EMAC_PPS2_I               NXP_S32_PINMUX(0, 0, 113, 0, 146, 1)
1342 #define PTE3_EMAC_PPS0_O                NXP_S32_PINMUX(0, 0, 131, 6, 0, 0)
1343 #define PTE3_EMAC_PPS0_I                NXP_S32_PINMUX(0, 0, 131, 0, 144, 1)
1344 #define PTE8_EMAC_MII_RMII_MDC          NXP_S32_PINMUX(0, 0, 136, 5, 0, 0)
1345 #define PTE9_EMAC_PPS3_O                NXP_S32_PINMUX(0, 0, 137, 5, 0, 0)
1346 #define PTE9_EMAC_MII_RMII_TX_EN        NXP_S32_PINMUX(0, 0, 137, 6, 0, 0)
1347 #define PTE9_EMAC_PPS3_I                NXP_S32_PINMUX(0, 0, 137, 0, 147, 1)
1348 #define PTE12_EMAC_PPS3_O               NXP_S32_PINMUX(0, 0, 140, 5, 0, 0)
1349 #define PTE12_EMAC_PPS3_I               NXP_S32_PINMUX(0, 0, 140, 0, 147, 3)
1350 #define PTE14_EMAC_PPS1_O               NXP_S32_PINMUX(0, 0, 142, 7, 0, 0)
1351 #define PTE14_EMAC_PPS1_I               NXP_S32_PINMUX(0, 0, 142, 0, 145, 1)
1352 
1353 /* LPI2C0 */
1354 #define PTB0_LPI2C0_SDAS_O              NXP_S32_PINMUX(0, 0, 32, 1, 0, 0)
1355 #define PTB0_LPI2C0_SDAS_I              NXP_S32_PINMUX(0, 0, 32, 0, 215, 1)
1356 #define PTB1_LPI2C0_SCLS_O              NXP_S32_PINMUX(0, 0, 33, 1, 0, 0)
1357 #define PTB1_LPI2C0_SCLS_I              NXP_S32_PINMUX(0, 0, 33, 0, 213, 1)
1358 #define PTB11_LPI2C0_HREQ               NXP_S32_PINMUX(0, 0, 43, 0, 211, 1)
1359 #define PTC7_LPI2C0_HREQ                NXP_S32_PINMUX(0, 0, 71, 0, 211, 2)
1360 #define PTC8_LPI2C0_SCL_O               NXP_S32_PINMUX(0, 0, 72, 1, 0, 0)
1361 #define PTC8_LPI2C0_SCL_I               NXP_S32_PINMUX(0, 0, 72, 0, 212, 1)
1362 #define PTC9_LPI2C0_SDA_O               NXP_S32_PINMUX(0, 0, 73, 1, 0, 0)
1363 #define PTC9_LPI2C0_SDA_I               NXP_S32_PINMUX(0, 0, 73, 0, 214, 1)
1364 #define PTD13_LPI2C0_SDA_O              NXP_S32_PINMUX(0, 0, 109, 4, 0, 0)
1365 #define PTD13_LPI2C0_SDA_I              NXP_S32_PINMUX(0, 0, 109, 0, 214, 2)
1366 #define PTD14_LPI2C0_SCL_O              NXP_S32_PINMUX(0, 0, 110, 4, 0, 0)
1367 #define PTD14_LPI2C0_SCL_I              NXP_S32_PINMUX(0, 0, 110, 0, 212, 2)
1368 
1369 /* LCU1 */
1370 #define PTB0_LCU1_OUT5                  NXP_S32_PINMUX(0, 0, 32, 5, 0, 0)
1371 #define PTB1_LCU1_OUT4                  NXP_S32_PINMUX(0, 0, 33, 7, 0, 0)
1372 #define PTB2_LCU1_OUT3                  NXP_S32_PINMUX(0, 0, 34, 5, 0, 0)
1373 #define PTB3_LCU1_OUT2                  NXP_S32_PINMUX(0, 0, 35, 6, 0, 0)
1374 #define PTB28_LCU1_OUT11                NXP_S32_PINMUX(0, 0, 60, 6, 0, 0)
1375 #define PTB29_LCU1_OUT10                NXP_S32_PINMUX(0, 0, 61, 6, 0, 0)
1376 #define PTC8_LCU1_OUT7                  NXP_S32_PINMUX(0, 0, 72, 5, 0, 0)
1377 #define PTC9_LCU1_OUT6                  NXP_S32_PINMUX(0, 0, 73, 5, 0, 0)
1378 #define PTC10_LCU1_OUT11                NXP_S32_PINMUX(0, 0, 74, 6, 0, 0)
1379 #define PTC11_LCU1_OUT10                NXP_S32_PINMUX(0, 0, 75, 7, 0, 0)
1380 #define PTC12_LCU1_OUT9                 NXP_S32_PINMUX(0, 0, 76, 6, 0, 0)
1381 #define PTC13_LCU1_OUT8                 NXP_S32_PINMUX(0, 0, 77, 6, 0, 0)
1382 #define PTC14_LCU1_OUT1                 NXP_S32_PINMUX(0, 0, 78, 6, 0, 0)
1383 #define PTC15_LCU1_OUT0                 NXP_S32_PINMUX(0, 0, 79, 6, 0, 0)
1384 #define PTC18_LCU1_OUT7                 NXP_S32_PINMUX(0, 0, 82, 6, 0, 0)
1385 #define PTC19_LCU1_OUT6                 NXP_S32_PINMUX(0, 0, 83, 6, 0, 0)
1386 #define PTC20_LCU1_OUT5                 NXP_S32_PINMUX(0, 0, 84, 6, 0, 0)
1387 #define PTC21_LCU1_OUT4                 NXP_S32_PINMUX(0, 0, 85, 6, 0, 0)
1388 #define PTC23_LCU1_OUT0                 NXP_S32_PINMUX(0, 0, 87, 6, 0, 0)
1389 #define PTC24_LCU1_OUT1                 NXP_S32_PINMUX(0, 0, 88, 6, 0, 0)
1390 #define PTC25_LCU1_OUT2                 NXP_S32_PINMUX(0, 0, 89, 6, 0, 0)
1391 #define PTC26_LCU1_OUT9                 NXP_S32_PINMUX(0, 0, 90, 6, 0, 0)
1392 #define PTC27_LCU1_OUT3                 NXP_S32_PINMUX(0, 0, 91, 6, 0, 0)
1393 #define PTC28_LCU1_OUT8                 NXP_S32_PINMUX(0, 0, 92, 6, 0, 0)
1394 
1395 /* HSE */
1396 #define PTB0_HSE_TAMPER_LOOP_OUT0       NXP_S32_PINMUX(0, 0, 32, 7, 0, 0)
1397 #define PTB1_HSE_TAMPER_EXTIN0          NXP_S32_PINMUX(0, 0, 33, 0, 343, 1)
1398 #define PTD23_HSE_TAMPER_LOOP_OUT0      NXP_S32_PINMUX(0, 0, 119, 5, 0, 0)
1399 #define PTD24_HSE_TAMPER_EXTIN0         NXP_S32_PINMUX(0, 0, 120, 0, 343, 2)
1400 
1401 /* ADC1 */
1402 #define PTB2_ADC1_MA0                   NXP_S32_PINMUX(0, 0, 34, 1, 0, 0)
1403 #define PTB23_ADC1_MA0                  NXP_S32_PINMUX(0, 0, 55, 1, 0, 0)
1404 #define PTB24_ADC1_MA1                  NXP_S32_PINMUX(0, 0, 56, 1, 0, 0)
1405 #define PTB28_ADC1_MA2                  NXP_S32_PINMUX(0, 0, 60, 1, 0, 0)
1406 #define PTC12_ADC1_MA2                  NXP_S32_PINMUX(0, 0, 76, 1, 0, 0)
1407 #define PTC13_ADC1_MA1                  NXP_S32_PINMUX(0, 0, 77, 4, 0, 0)
1408 #define PTC20_ADC1_MA2                  NXP_S32_PINMUX(0, 0, 84, 5, 0, 0)
1409 #define PTC21_ADC1_MA1                  NXP_S32_PINMUX(0, 0, 85, 5, 0, 0)
1410 #define PTC27_ADC1_MA0                  NXP_S32_PINMUX(0, 0, 91, 5, 0, 0)
1411 
1412 /* SAI0 */
1413 #define PTB2_SAI0_D0_O                  NXP_S32_PINMUX(0, 0, 34, 6, 0, 0)
1414 #define PTB2_SAI0_D0_I                  NXP_S32_PINMUX(0, 0, 34, 0, 316, 1)
1415 #define PTB3_SAI0_MCLK                  NXP_S32_PINMUX(0, 0, 35, 0, 320, 1)
1416 #define PTB29_SAI0_D1_O                 NXP_S32_PINMUX(0, 0, 61, 7, 0, 0)
1417 #define PTB29_SAI0_D1_I                 NXP_S32_PINMUX(0, 0, 61, 0, 317, 1)
1418 #define PTC12_SAI0_BCLK_O               NXP_S32_PINMUX(0, 0, 76, 7, 0, 0)
1419 #define PTC12_SAI0_BCLK_I               NXP_S32_PINMUX(0, 0, 76, 0, 315, 1)
1420 #define PTC13_SAI0_SYNC_O               NXP_S32_PINMUX(0, 0, 77, 7, 0, 0)
1421 #define PTC13_SAI0_SYNC_I               NXP_S32_PINMUX(0, 0, 77, 0, 321, 1)
1422 #define PTC18_SAI0_D2_O                 NXP_S32_PINMUX(0, 0, 82, 7, 0, 0)
1423 #define PTC18_SAI0_D2_I                 NXP_S32_PINMUX(0, 0, 82, 0, 318, 1)
1424 #define PTC19_SAI0_D3_O                 NXP_S32_PINMUX(0, 0, 83, 7, 0, 0)
1425 #define PTC19_SAI0_D3_I                 NXP_S32_PINMUX(0, 0, 83, 0, 319, 1)
1426 
1427 /* CAN4 */
1428 #define PTB2_CAN4_RX                    NXP_S32_PINMUX(0, 0, 34, 0, 4, 2)
1429 #define PTB3_CAN4_TX                    NXP_S32_PINMUX(0, 0, 35, 5, 0, 0)
1430 #define PTC30_CAN4_TX                   NXP_S32_PINMUX(0, 0, 94, 1, 0, 0)
1431 #define PTC31_CAN4_RX                   NXP_S32_PINMUX(0, 0, 95, 0, 4, 3)
1432 #define PTE3_CAN4_TX                    NXP_S32_PINMUX(0, 0, 131, 1, 0, 0)
1433 #define PTE14_CAN4_RX                   NXP_S32_PINMUX(0, 0, 142, 0, 4, 1)
1434 
1435 /* LPUART9 */
1436 #define PTB2_LPUART9_RX                 NXP_S32_PINMUX(0, 0, 34, 0, 196, 2)
1437 #define PTB3_LPUART9_TX_O               NXP_S32_PINMUX(0, 0, 35, 1, 0, 0)
1438 #define PTB3_LPUART9_TX_I               NXP_S32_PINMUX(0, 0, 35, 0, 372, 1)
1439 #define PTB9_LPUART9_RX                 NXP_S32_PINMUX(0, 0, 41, 0, 196, 1)
1440 #define PTB10_LPUART9_TX_O              NXP_S32_PINMUX(0, 0, 42, 5, 0, 0)
1441 #define PTB10_LPUART9_TX_I              NXP_S32_PINMUX(0, 0, 42, 0, 372, 2)
1442 
1443 /* ADC0 */
1444 #define PTB3_ADC0_MA0                   NXP_S32_PINMUX(0, 0, 35, 4, 0, 0)
1445 #define PTC6_ADC0_MA2                   NXP_S32_PINMUX(0, 0, 70, 7, 0, 0)
1446 #define PTC14_ADC0_MA1                  NXP_S32_PINMUX(0, 0, 78, 4, 0, 0)
1447 #define PTC15_ADC0_MA2                  NXP_S32_PINMUX(0, 0, 79, 4, 0, 0)
1448 #define PTE2_ADC0_MA0                   NXP_S32_PINMUX(0, 0, 130, 7, 0, 0)
1449 #define PTE6_ADC0_MA1                   NXP_S32_PINMUX(0, 0, 134, 7, 0, 0)
1450 
1451 /* LPUART8 */
1452 #define PTB12_LPUART8_RX                NXP_S32_PINMUX(0, 0, 44, 0, 195, 1)
1453 #define PTB13_LPUART8_TX_O              NXP_S32_PINMUX(0, 0, 45, 6, 0, 0)
1454 #define PTB13_LPUART8_TX_I              NXP_S32_PINMUX(0, 0, 45, 0, 371, 1)
1455 #define PTD15_LPUART8_RX                NXP_S32_PINMUX(0, 0, 111, 0, 195, 2)
1456 #define PTD16_LPUART8_TX_O              NXP_S32_PINMUX(0, 0, 112, 7, 0, 0)
1457 #define PTD16_LPUART8_TX_I              NXP_S32_PINMUX(0, 0, 112, 0, 371, 2)
1458 
1459 /* LPUART7 */
1460 #define PTB14_LPUART7_RX                NXP_S32_PINMUX(0, 0, 46, 0, 194, 1)
1461 #define PTB15_LPUART7_TX_O              NXP_S32_PINMUX(0, 0, 47, 6, 0, 0)
1462 #define PTB15_LPUART7_TX_I              NXP_S32_PINMUX(0, 0, 47, 0, 370, 1)
1463 #define PTC19_LPUART7_TX_O              NXP_S32_PINMUX(0, 0, 83, 1, 0, 0)
1464 #define PTC19_LPUART7_TX_I              NXP_S32_PINMUX(0, 0, 83, 0, 370, 2)
1465 #define PTC20_LPUART7_RX                NXP_S32_PINMUX(0, 0, 84, 0, 194, 4)
1466 #define PTE0_LPUART7_RX                 NXP_S32_PINMUX(0, 0, 128, 0, 194, 2)
1467 #define PTE1_LPUART7_TX_O               NXP_S32_PINMUX(0, 0, 129, 6, 0, 0)
1468 #define PTE1_LPUART7_TX_I               NXP_S32_PINMUX(0, 0, 129, 0, 370, 3)
1469 
1470 /* LPUART13 */
1471 #define PTB18_LPUART13_TX_O             NXP_S32_PINMUX(0, 0, 50, 1, 0, 0)
1472 #define PTB18_LPUART13_TX_I             NXP_S32_PINMUX(0, 0, 50, 0, 376, 1)
1473 #define PTB19_LPUART13_RX               NXP_S32_PINMUX(0, 0, 51, 0, 200, 1)
1474 #define PTC26_LPUART13_TX_O             NXP_S32_PINMUX(0, 0, 90, 1, 0, 0)
1475 #define PTC26_LPUART13_TX_I             NXP_S32_PINMUX(0, 0, 90, 0, 376, 2)
1476 #define PTC27_LPUART13_RX               NXP_S32_PINMUX(0, 0, 91, 0, 200, 2)
1477 
1478 /* LPUART14 */
1479 #define PTB20_LPUART14_TX_O             NXP_S32_PINMUX(0, 0, 52, 1, 0, 0)
1480 #define PTB20_LPUART14_TX_I             NXP_S32_PINMUX(0, 0, 52, 0, 377, 1)
1481 #define PTB21_LPUART14_RX               NXP_S32_PINMUX(0, 0, 53, 0, 201, 1)
1482 #define PTD26_LPUART14_TX_O             NXP_S32_PINMUX(0, 0, 122, 1, 0, 0)
1483 #define PTD26_LPUART14_TX_I             NXP_S32_PINMUX(0, 0, 122, 0, 377, 2)
1484 #define PTD27_LPUART14_RX               NXP_S32_PINMUX(0, 0, 123, 0, 201, 2)
1485 
1486 /* LPUART15 */
1487 #define PTB25_LPUART15_TX_O             NXP_S32_PINMUX(0, 0, 57, 1, 0, 0)
1488 #define PTB25_LPUART15_TX_I             NXP_S32_PINMUX(0, 0, 57, 0, 378, 1)
1489 #define PTB26_LPUART15_RX               NXP_S32_PINMUX(0, 0, 58, 0, 202, 1)
1490 #define PTD28_LPUART15_TX_O             NXP_S32_PINMUX(0, 0, 124, 1, 0, 0)
1491 #define PTD28_LPUART15_TX_I             NXP_S32_PINMUX(0, 0, 124, 0, 378, 2)
1492 #define PTD29_LPUART15_RX               NXP_S32_PINMUX(0, 0, 125, 0, 202, 2)
1493 
1494 /* LPUART5 */
1495 #define PTB27_LPUART5_TX_O              NXP_S32_PINMUX(0, 0, 59, 1, 0, 0)
1496 #define PTB27_LPUART5_TX_I              NXP_S32_PINMUX(0, 0, 59, 0, 368, 3)
1497 #define PTB28_LPUART5_RX                NXP_S32_PINMUX(0, 0, 60, 0, 192, 4)
1498 #define PTD0_LPUART5_RX                 NXP_S32_PINMUX(0, 0, 96, 0, 192, 2)
1499 #define PTD1_LPUART5_TX_O               NXP_S32_PINMUX(0, 0, 97, 1, 0, 0)
1500 #define PTD1_LPUART5_TX_I               NXP_S32_PINMUX(0, 0, 97, 0, 368, 1)
1501 #define PTE3_LPUART5_RX                 NXP_S32_PINMUX(0, 0, 131, 0, 192, 1)
1502 #define PTE14_LPUART5_TX_O              NXP_S32_PINMUX(0, 0, 142, 4, 0, 0)
1503 #define PTE14_LPUART5_TX_I              NXP_S32_PINMUX(0, 0, 142, 0, 368, 2)
1504 
1505 /* CAN3 */
1506 #define PTC0_CAN3_TX                    NXP_S32_PINMUX(0, 0, 64, 1, 0, 0)
1507 #define PTC1_CAN3_RX                    NXP_S32_PINMUX(0, 0, 65, 0, 3, 2)
1508 #define PTC28_CAN3_TX                   NXP_S32_PINMUX(0, 0, 92, 1, 0, 0)
1509 #define PTC29_CAN3_RX                   NXP_S32_PINMUX(0, 0, 93, 0, 3, 3)
1510 #define PTD15_CAN3_RX                   NXP_S32_PINMUX(0, 0, 111, 0, 3, 1)
1511 #define PTE9_CAN3_TX                    NXP_S32_PINMUX(0, 0, 137, 4, 0, 0)
1512 
1513 /* TRACE */
1514 #define PTC2_TRACE_ETM_CLKOUT           NXP_S32_PINMUX(0, 0, 66, 6, 0, 0)
1515 #define PTD7_TRACE_ETM_D0               NXP_S32_PINMUX(0, 0, 103, 6, 0, 0)
1516 #define PTD10_TRACE_ETM_D3              NXP_S32_PINMUX(0, 0, 106, 4, 0, 0)
1517 #define PTD11_TRACE_ETM_D2              NXP_S32_PINMUX(0, 0, 107, 4, 0, 0)
1518 #define PTD12_TRACE_ETM_D1              NXP_S32_PINMUX(0, 0, 108, 4, 0, 0)
1519 
1520 /* QUADSPI */
1521 #define PTC2_QUADSPI_IOFA3_O            NXP_S32_PINMUX(0, 0, 66, 7, 0, 0)
1522 #define PTC2_QUADSPI_IOFA3_I            NXP_S32_PINMUX(0, 0, 66, 0, 308, 1)
1523 #define PTC3_QUADSPI_PCSFA              NXP_S32_PINMUX(0, 0, 67, 6, 0, 0)
1524 #define PTD7_QUADSPI_IOFA1_O            NXP_S32_PINMUX(0, 0, 103, 7, 0, 0)
1525 #define PTD7_QUADSPI_IOFA1_I            NXP_S32_PINMUX(0, 0, 103, 0, 306, 1)
1526 #define PTD10_QUADSPI_SCKFA_O           NXP_S32_PINMUX(0, 0, 106, 7, 0, 0)
1527 #define PTD10_QUADSPI_SCKFA_I           NXP_S32_PINMUX(0, 0, 106, 0, 309, 1)
1528 #define PTD11_QUADSPI_IOFA0_O           NXP_S32_PINMUX(0, 0, 107, 7, 0, 0)
1529 #define PTD11_QUADSPI_IOFA0_I           NXP_S32_PINMUX(0, 0, 107, 0, 305, 1)
1530 #define PTD12_QUADSPI_IOFA2_O           NXP_S32_PINMUX(0, 0, 108, 7, 0, 0)
1531 #define PTD12_QUADSPI_IOFA2_I           NXP_S32_PINMUX(0, 0, 108, 0, 307, 1)
1532 
1533 /* LPI2C1 */
1534 #define PTC5_LPI2C1_HREQ                NXP_S32_PINMUX(0, 0, 69, 0, 216, 2)
1535 #define PTC6_LPI2C1_SDA_O               NXP_S32_PINMUX(0, 0, 70, 1, 0, 0)
1536 #define PTC6_LPI2C1_SDA_I               NXP_S32_PINMUX(0, 0, 70, 0, 219, 2)
1537 #define PTC7_LPI2C1_SCL_O               NXP_S32_PINMUX(0, 0, 71, 3, 0, 0)
1538 #define PTC7_LPI2C1_SCL_I               NXP_S32_PINMUX(0, 0, 71, 0, 217, 1)
1539 #define PTC15_LPI2C1_SCL_O              NXP_S32_PINMUX(0, 0, 79, 7, 0, 0)
1540 #define PTC15_LPI2C1_SCL_I              NXP_S32_PINMUX(0, 0, 79, 0, 217, 6)
1541 #define PTC16_LPI2C1_SDAS_O             NXP_S32_PINMUX(0, 0, 80, 4, 0, 0)
1542 #define PTC16_LPI2C1_SDA_O              NXP_S32_PINMUX(0, 0, 80, 7, 0, 0)
1543 #define PTC16_LPI2C1_SDA_I              NXP_S32_PINMUX(0, 0, 80, 0, 219, 5)
1544 #define PTC16_LPI2C1_SDAS_I             NXP_S32_PINMUX(0, 0, 80, 0, 220, 1)
1545 #define PTC17_LPI2C1_SCLS_O             NXP_S32_PINMUX(0, 0, 81, 4, 0, 0)
1546 #define PTC17_LPI2C1_SCLS_I             NXP_S32_PINMUX(0, 0, 81, 0, 218, 2)
1547 #define PTC28_LPI2C1_SCL_O              NXP_S32_PINMUX(0, 0, 92, 5, 0, 0)
1548 #define PTC28_LPI2C1_SCL_I              NXP_S32_PINMUX(0, 0, 92, 0, 217, 4)
1549 #define PTC29_LPI2C1_SDA_O              NXP_S32_PINMUX(0, 0, 93, 5, 0, 0)
1550 #define PTC29_LPI2C1_SDA_I              NXP_S32_PINMUX(0, 0, 93, 0, 219, 3)
1551 #define PTD8_LPI2C1_SDA_O               NXP_S32_PINMUX(0, 0, 104, 2, 0, 0)
1552 #define PTD8_LPI2C1_SDA_I               NXP_S32_PINMUX(0, 0, 104, 0, 219, 1)
1553 #define PTD9_LPI2C1_SCL_O               NXP_S32_PINMUX(0, 0, 105, 2, 0, 0)
1554 #define PTD9_LPI2C1_SCL_I               NXP_S32_PINMUX(0, 0, 105, 0, 217, 2)
1555 #define PTD12_LPI2C1_HREQ               NXP_S32_PINMUX(0, 0, 108, 0, 216, 1)
1556 
1557 /* CAN2 */
1558 #define PTC6_CAN2_RX                    NXP_S32_PINMUX(0, 0, 70, 0, 2, 6)
1559 #define PTC7_CAN2_TX                    NXP_S32_PINMUX(0, 0, 71, 7, 0, 0)
1560 #define PTC14_CAN2_RX                   NXP_S32_PINMUX(0, 0, 78, 0, 2, 2)
1561 #define PTC15_CAN2_TX                   NXP_S32_PINMUX(0, 0, 79, 1, 0, 0)
1562 #define PTC16_CAN2_RX                   NXP_S32_PINMUX(0, 0, 80, 0, 2, 1)
1563 #define PTC17_CAN2_TX                   NXP_S32_PINMUX(0, 0, 81, 3, 0, 0)
1564 #define PTE24_CAN2_TX                   NXP_S32_PINMUX(0, 0, 152, 3, 0, 0)
1565 #define PTE25_CAN2_RX                   NXP_S32_PINMUX(0, 0, 153, 0, 2, 3)
1566 
1567 /* CAN5 */
1568 #define PTC10_CAN5_TX                   NXP_S32_PINMUX(0, 0, 74, 3, 0, 0)
1569 #define PTC11_CAN5_RX                   NXP_S32_PINMUX(0, 0, 75, 0, 5, 2)
1570 #define PTC26_CAN5_RX                   NXP_S32_PINMUX(0, 0, 90, 0, 5, 5)
1571 #define PTC27_CAN5_TX                   NXP_S32_PINMUX(0, 0, 91, 1, 0, 0)
1572 #define PTD17_CAN5_RX                   NXP_S32_PINMUX(0, 0, 113, 0, 5, 1)
1573 #define PTE12_CAN5_TX                   NXP_S32_PINMUX(0, 0, 140, 2, 0, 0)
1574 
1575 /* LPUART10 */
1576 #define PTC12_LPUART10_RX               NXP_S32_PINMUX(0, 0, 76, 0, 197, 2)
1577 #define PTC13_LPUART10_TX_O             NXP_S32_PINMUX(0, 0, 77, 1, 0, 0)
1578 #define PTC13_LPUART10_TX_I             NXP_S32_PINMUX(0, 0, 77, 0, 373, 1)
1579 #define PTE2_LPUART10_RX                NXP_S32_PINMUX(0, 0, 130, 0, 197, 1)
1580 #define PTE6_LPUART10_TX_O              NXP_S32_PINMUX(0, 0, 134, 5, 0, 0)
1581 #define PTE6_LPUART10_TX_I              NXP_S32_PINMUX(0, 0, 134, 0, 373, 2)
1582 
1583 /* LPUART12 */
1584 #define PTC24_LPUART12_TX_O             NXP_S32_PINMUX(0, 0, 88, 1, 0, 0)
1585 #define PTC24_LPUART12_TX_I             NXP_S32_PINMUX(0, 0, 88, 0, 375, 1)
1586 #define PTC25_LPUART12_RX               NXP_S32_PINMUX(0, 0, 89, 0, 199, 2)
1587 #define PTE4_LPUART12_TX_O              NXP_S32_PINMUX(0, 0, 132, 5, 0, 0)
1588 #define PTE4_LPUART12_TX_I              NXP_S32_PINMUX(0, 0, 132, 0, 375, 2)
1589 #define PTE5_LPUART12_RX                NXP_S32_PINMUX(0, 0, 133, 0, 199, 1)
1590 
1591 /* SAI1 */
1592 #define PTD13_SAI1_D0_O                 NXP_S32_PINMUX(0, 0, 109, 6, 0, 0)
1593 #define PTD13_SAI1_D0_I                 NXP_S32_PINMUX(0, 0, 109, 0, 323, 1)
1594 #define PTD14_SAI1_MCLK                 NXP_S32_PINMUX(0, 0, 110, 0, 324, 1)
1595 #define PTD15_SAI1_SYNC_O               NXP_S32_PINMUX(0, 0, 111, 6, 0, 0)
1596 #define PTD15_SAI1_SYNC_I               NXP_S32_PINMUX(0, 0, 111, 0, 325, 1)
1597 #define PTE8_SAI1_BCLK_O                NXP_S32_PINMUX(0, 0, 136, 6, 0, 0)
1598 #define PTE8_SAI1_BCLK_I                NXP_S32_PINMUX(0, 0, 136, 0, 322, 1)
1599 
1600 /* TRGMUX INTERNAL */
1601 #define TRGMUX_INT_OUT37_EMIOS_0_CH6_G  NXP_S32_PINMUX(0, 0, 17, 0, 54, 3)
1602 #define TRGMUX_INT_OUT38_EMIOS_0_CH7_G  NXP_S32_PINMUX(0, 0, 135, 0, 55, 4)
1603 
1604 #endif /* HAL_NXP_DTS_NXP_S32_S32K344_172MQFP_PINCTRL_H_ */
1605