1 /* 2 * NOTE: Autogenerated file by gen_soc_headers.py 3 * for MCXA156VMP/signal_configuration.xml 4 * 5 * 6 */ 7 8 #ifndef _ZEPHYR_DTS_BINDING_MCXA156VMP_ 9 #define _ZEPHYR_DTS_BINDING_MCXA156VMP_ 10 11 #define A15X_MUX(port, pin, mux) \ 12 (((((port) - '0') & 0xF) << 28) | \ 13 (((pin) & 0x3F) << 22) | \ 14 (((mux) & 0xF) << 8)) 15 16 #define P0_0 A15X_MUX('0',0,0) /* PT0_0 */ 17 #define TMS_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ 18 #define SWDIO_P0_0 A15X_MUX('0',0,1) /* PT0_0 */ 19 #define LPUART0_RTS_B_P0_0 A15X_MUX('0',0,2) /* PT0_0 */ 20 #define LPSPI0_PCS0_P0_0 A15X_MUX('0',0,3) /* PT0_0 */ 21 #define CT_INP0_P0_0 A15X_MUX('0',0,4) /* PT0_0 */ 22 #define FLEXIO0_D0_P0_0 A15X_MUX('0',0,6) /* PT0_0 */ 23 #define P0_1 A15X_MUX('0',1,0) /* PT0_1 */ 24 #define TCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ 25 #define SWCLK_P0_1 A15X_MUX('0',1,1) /* PT0_1 */ 26 #define LPUART0_CTS_B_P0_1 A15X_MUX('0',1,2) /* PT0_1 */ 27 #define LPSPI0_SDI_P0_1 A15X_MUX('0',1,3) /* PT0_1 */ 28 #define CT_INP1_P0_1 A15X_MUX('0',1,4) /* PT0_1 */ 29 #define FLEXIO0_D1_P0_1 A15X_MUX('0',1,6) /* PT0_1 */ 30 #define P0_2 A15X_MUX('0',2,0) /* PT0_2 */ 31 #define SWO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ 32 #define TDO_P0_2 A15X_MUX('0',2,1) /* PT0_2 */ 33 #define LPUART0_RXD_P0_2 A15X_MUX('0',2,2) /* PT0_2 */ 34 #define LPSPI0_SCK_P0_2 A15X_MUX('0',2,3) /* PT0_2 */ 35 #define CT0_MAT0_P0_2 A15X_MUX('0',2,4) /* PT0_2 */ 36 #define UTICK_CAP0_P0_2 A15X_MUX('0',2,5) /* PT0_2 */ 37 #define FLEXIO0_D2_P0_2 A15X_MUX('0',2,6) /* PT0_2 */ 38 #define I3C0_PUR_P0_2 A15X_MUX('0',2,10) /* PT0_2 */ 39 #define P0_3 A15X_MUX('0',3,0) /* PT0_3 */ 40 #define CMP1_IN1_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ 41 #define ADC0_A14_P0_3 A15X_MUX('0',3,0) /* PT0_3 */ 42 #define TDI_P0_3 A15X_MUX('0',3,1) /* PT0_3 */ 43 #define LPUART0_TXD_P0_3 A15X_MUX('0',3,2) /* PT0_3 */ 44 #define LPSPI0_SDO_P0_3 A15X_MUX('0',3,3) /* PT0_3 */ 45 #define CT0_MAT1_P0_3 A15X_MUX('0',3,4) /* PT0_3 */ 46 #define UTICK_CAP1_P0_3 A15X_MUX('0',3,5) /* PT0_3 */ 47 #define FLEXIO0_D3_P0_3 A15X_MUX('0',3,6) /* PT0_3 */ 48 #define CMP0_OUT_P0_3 A15X_MUX('0',3,8) /* PT0_3 */ 49 #define ADC0_A15_P0_6 A15X_MUX('0',6,0) /* PT0_6 */ 50 #define P0_6 A15X_MUX('0',6,0) /* PT0_6 */ 51 #define ISPMODE_N_P0_6 A15X_MUX('0',6,1) /* PT0_6 */ 52 #define LPI2C0_HREQ_P0_6 A15X_MUX('0',6,2) /* PT0_6 */ 53 #define LPSPI0_PCS1_P0_6 A15X_MUX('0',6,3) /* PT0_6 */ 54 #define CT_INP2_P0_6 A15X_MUX('0',6,4) /* PT0_6 */ 55 #define FLEXIO0_D6_P0_6 A15X_MUX('0',6,6) /* PT0_6 */ 56 #define WUU0_IN31_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ 57 #define CMP1_OUT_P0_6 A15X_MUX('0',6,8) /* PT0_6 */ 58 #define CLKOUT_P0_6 A15X_MUX('0',6,12) /* PT0_6 */ 59 #define WUU0_IN2_P0_16 A15X_MUX('0',16,0) /* PT0_16 */ 60 #define P0_16 A15X_MUX('0',16,0) /* PT0_16 */ 61 #define LPI2C0_SDA_P0_16 A15X_MUX('0',16,2) /* PT0_16 */ 62 #define LPSPI0_PCS2_P0_16 A15X_MUX('0',16,3) /* PT0_16 */ 63 #define CT0_MAT0_P0_16 A15X_MUX('0',16,4) /* PT0_16 */ 64 #define UTICK_CAP2_P0_16 A15X_MUX('0',16,5) /* PT0_16 */ 65 #define FLEXIO0_D0_P0_16 A15X_MUX('0',16,6) /* PT0_16 */ 66 #define I3C0_SDA_P0_16 A15X_MUX('0',16,10) /* PT0_16 */ 67 #define P0_17 A15X_MUX('0',17,0) /* PT0_17 */ 68 #define LPI2C0_SCL_P0_17 A15X_MUX('0',17,2) /* PT0_17 */ 69 #define LPSPI0_PCS3_P0_17 A15X_MUX('0',17,3) /* PT0_17 */ 70 #define CT0_MAT1_P0_17 A15X_MUX('0',17,4) /* PT0_17 */ 71 #define UTICK_CAP3_P0_17 A15X_MUX('0',17,5) /* PT0_17 */ 72 #define FLEXIO0_D1_P0_17 A15X_MUX('0',17,6) /* PT0_17 */ 73 #define I3C0_SCL_P0_17 A15X_MUX('0',17,10) /* PT0_17 */ 74 #define P1_0 A15X_MUX('1',0,0) /* PT1_0 */ 75 #define CMP0_IN3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ 76 #define LPTMR0_ALT3_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ 77 #define ADC0_A16_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ 78 #define WUU0_IN6_P1_0 A15X_MUX('1',0,0) /* PT1_0 */ 79 #define TRIG_IN0_P1_0 A15X_MUX('1',0,1) /* PT1_0 */ 80 #define LPSPI0_SDO_P1_0 A15X_MUX('1',0,2) /* PT1_0 */ 81 #define LPI2C1_SDA_P1_0 A15X_MUX('1',0,3) /* PT1_0 */ 82 #define CT_INP4_P1_0 A15X_MUX('1',0,4) /* PT1_0 */ 83 #define CT0_MAT2_P1_0 A15X_MUX('1',0,5) /* PT1_0 */ 84 #define FLEXIO0_D8_P1_0 A15X_MUX('1',0,6) /* PT1_0 */ 85 #define CMP1_IN3_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ 86 #define ADC0_A17_P1_1 A15X_MUX('1',1,0) /* PT1_1 */ 87 #define P1_1 A15X_MUX('1',1,0) /* PT1_1 */ 88 #define TRIG_IN1_P1_1 A15X_MUX('1',1,1) /* PT1_1 */ 89 #define LPSPI0_SCK_P1_1 A15X_MUX('1',1,2) /* PT1_1 */ 90 #define LPI2C1_SCL_P1_1 A15X_MUX('1',1,3) /* PT1_1 */ 91 #define CT_INP5_P1_1 A15X_MUX('1',1,4) /* PT1_1 */ 92 #define CT0_MAT3_P1_1 A15X_MUX('1',1,5) /* PT1_1 */ 93 #define FLEXIO0_D9_P1_1 A15X_MUX('1',1,6) /* PT1_1 */ 94 #define P1_2 A15X_MUX('1',2,0) /* PT1_2 */ 95 #define ADC0_A18_P1_2 A15X_MUX('1',2,0) /* PT1_2 */ 96 #define TRIG_OUT0_P1_2 A15X_MUX('1',2,1) /* PT1_2 */ 97 #define LPSPI0_SDI_P1_2 A15X_MUX('1',2,2) /* PT1_2 */ 98 #define LPI2C1_SDAS_P1_2 A15X_MUX('1',2,3) /* PT1_2 */ 99 #define CT1_MAT0_P1_2 A15X_MUX('1',2,4) /* PT1_2 */ 100 #define CT_INP0_P1_2 A15X_MUX('1',2,5) /* PT1_2 */ 101 #define FLEXIO0_D10_P1_2 A15X_MUX('1',2,6) /* PT1_2 */ 102 #define CAN0_TXD_P1_2 A15X_MUX('1',2,11) /* PT1_2 */ 103 #define WUU0_IN7_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ 104 #define CMP0_IN1_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ 105 #define ADC0_A19_P1_3 A15X_MUX('1',3,0) /* PT1_3 */ 106 #define P1_3 A15X_MUX('1',3,0) /* PT1_3 */ 107 #define TRIG_OUT1_P1_3 A15X_MUX('1',3,1) /* PT1_3 */ 108 #define LPSPI0_PCS0_P1_3 A15X_MUX('1',3,2) /* PT1_3 */ 109 #define LPI2C1_SCLS_P1_3 A15X_MUX('1',3,3) /* PT1_3 */ 110 #define CT1_MAT1_P1_3 A15X_MUX('1',3,4) /* PT1_3 */ 111 #define CT_INP1_P1_3 A15X_MUX('1',3,5) /* PT1_3 */ 112 #define FLEXIO0_D11_P1_3 A15X_MUX('1',3,6) /* PT1_3 */ 113 #define CAN0_RXD_P1_3 A15X_MUX('1',3,11) /* PT1_3 */ 114 #define ADC0_A20_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ 115 #define P1_4 A15X_MUX('1',4,0) /* PT1_4 */ 116 #define CMP0_IN2_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ 117 #define WUU0_IN8_P1_4 A15X_MUX('1',4,0) /* PT1_4 */ 118 #define FREQME_CLK_IN0_P1_4 A15X_MUX('1',4,1) /* PT1_4 */ 119 #define LPSPI0_PCS3_P1_4 A15X_MUX('1',4,2) /* PT1_4 */ 120 #define LPUART2_RXD_P1_4 A15X_MUX('1',4,3) /* PT1_4 */ 121 #define CT1_MAT2_P1_4 A15X_MUX('1',4,4) /* PT1_4 */ 122 #define FLEXIO0_D12_P1_4 A15X_MUX('1',4,6) /* PT1_4 */ 123 #define CMP1_IN2_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ 124 #define P1_5 A15X_MUX('1',5,0) /* PT1_5 */ 125 #define ADC0_A21_P1_5 A15X_MUX('1',5,0) /* PT1_5 */ 126 #define FREQME_CLK_IN1_P1_5 A15X_MUX('1',5,1) /* PT1_5 */ 127 #define LPSPI0_PCS2_P1_5 A15X_MUX('1',5,2) /* PT1_5 */ 128 #define LPUART2_TXD_P1_5 A15X_MUX('1',5,3) /* PT1_5 */ 129 #define CT1_MAT3_P1_5 A15X_MUX('1',5,4) /* PT1_5 */ 130 #define FLEXIO0_D13_P1_5 A15X_MUX('1',5,6) /* PT1_5 */ 131 #define P1_6 A15X_MUX('1',6,0) /* PT1_6 */ 132 #define ADC0_A22_P1_6 A15X_MUX('1',6,0) /* PT1_6 */ 133 #define TRIG_IN2_P1_6 A15X_MUX('1',6,1) /* PT1_6 */ 134 #define LPSPI0_PCS1_P1_6 A15X_MUX('1',6,2) /* PT1_6 */ 135 #define LPUART2_RTS_B_P1_6 A15X_MUX('1',6,3) /* PT1_6 */ 136 #define CT_INP6_P1_6 A15X_MUX('1',6,4) /* PT1_6 */ 137 #define CT4_MAT0_P1_6 A15X_MUX('1',6,5) /* PT1_6 */ 138 #define FLEXIO0_D14_P1_6 A15X_MUX('1',6,6) /* PT1_6 */ 139 #define CAN0_TXD_P1_6 A15X_MUX('1',6,11) /* PT1_6 */ 140 #define WUU0_IN9_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ 141 #define P1_7 A15X_MUX('1',7,0) /* PT1_7 */ 142 #define ADC0_A23_P1_7 A15X_MUX('1',7,0) /* PT1_7 */ 143 #define TRIG_OUT2_P1_7 A15X_MUX('1',7,1) /* PT1_7 */ 144 #define LPUART2_CTS_B_P1_7 A15X_MUX('1',7,3) /* PT1_7 */ 145 #define CT_INP7_P1_7 A15X_MUX('1',7,4) /* PT1_7 */ 146 #define CT4_MAT1_P1_7 A15X_MUX('1',7,5) /* PT1_7 */ 147 #define FLEXIO0_D15_P1_7 A15X_MUX('1',7,6) /* PT1_7 */ 148 #define CAN0_RXD_P1_7 A15X_MUX('1',7,11) /* PT1_7 */ 149 #define P1_8 A15X_MUX('1',8,0) /* PT1_8 */ 150 #define WUU0_IN10_P1_8 A15X_MUX('1',8,0) /* PT1_8 */ 151 #define FREQME_CLK_IN0_P1_8 A15X_MUX('1',8,1) /* PT1_8 */ 152 #define LPUART1_RXD_P1_8 A15X_MUX('1',8,2) /* PT1_8 */ 153 #define LPI2C2_SDA_P1_8 A15X_MUX('1',8,3) /* PT1_8 */ 154 #define CT_INP8_P1_8 A15X_MUX('1',8,4) /* PT1_8 */ 155 #define CT0_MAT2_P1_8 A15X_MUX('1',8,5) /* PT1_8 */ 156 #define FLEXIO0_D16_P1_8 A15X_MUX('1',8,6) /* PT1_8 */ 157 #define I3C0_SDA_P1_8 A15X_MUX('1',8,10) /* PT1_8 */ 158 #define P1_9 A15X_MUX('1',9,0) /* PT1_9 */ 159 #define FREQME_CLK_IN1_P1_9 A15X_MUX('1',9,1) /* PT1_9 */ 160 #define LPUART1_TXD_P1_9 A15X_MUX('1',9,2) /* PT1_9 */ 161 #define LPI2C2_SCL_P1_9 A15X_MUX('1',9,3) /* PT1_9 */ 162 #define CT_INP9_P1_9 A15X_MUX('1',9,4) /* PT1_9 */ 163 #define CT0_MAT3_P1_9 A15X_MUX('1',9,5) /* PT1_9 */ 164 #define FLEXIO0_D17_P1_9 A15X_MUX('1',9,6) /* PT1_9 */ 165 #define I3C0_SCL_P1_9 A15X_MUX('1',9,10) /* PT1_9 */ 166 #define ADC1_A8_P1_10 A15X_MUX('1',10,0) /* PT1_10 */ 167 #define P1_10 A15X_MUX('1',10,0) /* PT1_10 */ 168 #define LPUART1_RTS_B_P1_10 A15X_MUX('1',10,2) /* PT1_10 */ 169 #define LPI2C2_SDAS_P1_10 A15X_MUX('1',10,3) /* PT1_10 */ 170 #define CT2_MAT0_P1_10 A15X_MUX('1',10,4) /* PT1_10 */ 171 #define FLEXIO0_D18_P1_10 A15X_MUX('1',10,6) /* PT1_10 */ 172 #define CAN0_TXD_P1_10 A15X_MUX('1',10,11) /* PT1_10 */ 173 #define P1_11 A15X_MUX('1',11,0) /* PT1_11 */ 174 #define WUU0_IN11_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ 175 #define ADC1_A9_P1_11 A15X_MUX('1',11,0) /* PT1_11 */ 176 #define TRIG_OUT2_P1_11 A15X_MUX('1',11,1) /* PT1_11 */ 177 #define LPUART1_CTS_B_P1_11 A15X_MUX('1',11,2) /* PT1_11 */ 178 #define LPI2C2_SCLS_P1_11 A15X_MUX('1',11,3) /* PT1_11 */ 179 #define CT2_MAT1_P1_11 A15X_MUX('1',11,4) /* PT1_11 */ 180 #define FLEXIO0_D19_P1_11 A15X_MUX('1',11,6) /* PT1_11 */ 181 #define I3C0_PUR_P1_11 A15X_MUX('1',11,10) /* PT1_11 */ 182 #define CAN0_RXD_P1_11 A15X_MUX('1',11,11) /* PT1_11 */ 183 #define P1_29 A15X_MUX('1',29,0) /* PT1_29 */ 184 #define RESET_B_P1_29 A15X_MUX('1',29,1) /* PT1_29 */ 185 #define SPC_LPREQ_P1_29 A15X_MUX('1',29,2) /* PT1_29 */ 186 #define P1_30 A15X_MUX('1',30,0) /* PT1_30 */ 187 #define XTAL48M_P1_30 A15X_MUX('1',30,0) /* PT1_30 */ 188 #define TRIG_OUT3_P1_30 A15X_MUX('1',30,1) /* PT1_30 */ 189 #define LPI2C0_SDA_P1_30 A15X_MUX('1',30,3) /* PT1_30 */ 190 #define CT_INP16_P1_30 A15X_MUX('1',30,4) /* PT1_30 */ 191 #define FLEXIO0_D30_P1_30 A15X_MUX('1',30,6) /* PT1_30 */ 192 #define I3C0_SDA_P1_30 A15X_MUX('1',30,10) /* PT1_30 */ 193 #define EXTAL48M_P1_31 A15X_MUX('1',31,0) /* PT1_31 */ 194 #define P1_31 A15X_MUX('1',31,0) /* PT1_31 */ 195 #define TRIG_IN4_P1_31 A15X_MUX('1',31,1) /* PT1_31 */ 196 #define LPI2C0_SCL_P1_31 A15X_MUX('1',31,3) /* PT1_31 */ 197 #define CT_INP17_P1_31 A15X_MUX('1',31,4) /* PT1_31 */ 198 #define FLEXIO0_D31_P1_31 A15X_MUX('1',31,6) /* PT1_31 */ 199 #define I3C0_SCL_P1_31 A15X_MUX('1',31,10) /* PT1_31 */ 200 #define P2_0 A15X_MUX('2',0,0) /* PT2_0 */ 201 #define ADC0_A0_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ 202 #define WUU0_IN18_P2_0 A15X_MUX('2',0,0) /* PT2_0 */ 203 #define TRIG_IN6_P2_0 A15X_MUX('2',0,1) /* PT2_0 */ 204 #define LPUART0_RXD_P2_0 A15X_MUX('2',0,2) /* PT2_0 */ 205 #define LPUART4_CTS_B_P2_0 A15X_MUX('2',0,3) /* PT2_0 */ 206 #define CT_INP16_P2_0 A15X_MUX('2',0,4) /* PT2_0 */ 207 #define CT2_MAT0_P2_0 A15X_MUX('2',0,5) /* PT2_0 */ 208 #define FLEXIO0_D8_P2_0 A15X_MUX('2',0,6) /* PT2_0 */ 209 #define P2_1 A15X_MUX('2',1,0) /* PT2_1 */ 210 #define ADC0_A1_P2_1 A15X_MUX('2',1,0) /* PT2_1 */ 211 #define TRIG_IN7_P2_1 A15X_MUX('2',1,1) /* PT2_1 */ 212 #define LPUART0_TXD_P2_1 A15X_MUX('2',1,2) /* PT2_1 */ 213 #define LPUART4_RTS_B_P2_1 A15X_MUX('2',1,3) /* PT2_1 */ 214 #define CT_INP17_P2_1 A15X_MUX('2',1,4) /* PT2_1 */ 215 #define CT2_MAT1_P2_1 A15X_MUX('2',1,5) /* PT2_1 */ 216 #define FLEXIO0_D9_P2_1 A15X_MUX('2',1,6) /* PT2_1 */ 217 #define P2_2 A15X_MUX('2',2,0) /* PT2_2 */ 218 #define CMP0_IN0_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ 219 #define DAC0_OUT_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ 220 #define ADC0_A4_P2_2 A15X_MUX('2',2,0) /* PT2_2 */ 221 #define TRIG_IN6_P2_2 A15X_MUX('2',2,1) /* PT2_2 */ 222 #define LPUART0_RTS_B_P2_2 A15X_MUX('2',2,2) /* PT2_2 */ 223 #define LPUART2_TXD_P2_2 A15X_MUX('2',2,3) /* PT2_2 */ 224 #define CT_INP12_P2_2 A15X_MUX('2',2,4) /* PT2_2 */ 225 #define CT2_MAT2_P2_2 A15X_MUX('2',2,5) /* PT2_2 */ 226 #define FLEXIO0_D10_P2_2 A15X_MUX('2',2,6) /* PT2_2 */ 227 #define P2_3 A15X_MUX('2',3,0) /* PT2_3 */ 228 #define WUU0_IN19_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ 229 #define CMP1_IN0_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ 230 #define ADC1_A4_P2_3 A15X_MUX('2',3,0) /* PT2_3 */ 231 #define TRIG_IN7_P2_3 A15X_MUX('2',3,1) /* PT2_3 */ 232 #define LPUART0_CTS_B_P2_3 A15X_MUX('2',3,2) /* PT2_3 */ 233 #define LPUART2_RXD_P2_3 A15X_MUX('2',3,3) /* PT2_3 */ 234 #define CT_INP13_P2_3 A15X_MUX('2',3,4) /* PT2_3 */ 235 #define CT2_MAT3_P2_3 A15X_MUX('2',3,5) /* PT2_3 */ 236 #define FLEXIO0_D11_P2_3 A15X_MUX('2',3,6) /* PT2_3 */ 237 #define ADC1_A0_P2_4 A15X_MUX('2',4,0) /* PT2_4 */ 238 #define P2_4 A15X_MUX('2',4,0) /* PT2_4 */ 239 #define LPUART2_CTS_B_P2_4 A15X_MUX('2',4,3) /* PT2_4 */ 240 #define CT_INP14_P2_4 A15X_MUX('2',4,4) /* PT2_4 */ 241 #define CT1_MAT0_P2_4 A15X_MUX('2',4,5) /* PT2_4 */ 242 #define FLEXIO0_D12_P2_4 A15X_MUX('2',4,6) /* PT2_4 */ 243 #define ADC1_A1_P2_5 A15X_MUX('2',5,0) /* PT2_5 */ 244 #define P2_5 A15X_MUX('2',5,0) /* PT2_5 */ 245 #define LPUART2_RTS_B_P2_5 A15X_MUX('2',5,3) /* PT2_5 */ 246 #define CT_INP15_P2_5 A15X_MUX('2',5,4) /* PT2_5 */ 247 #define CT1_MAT1_P2_5 A15X_MUX('2',5,5) /* PT2_5 */ 248 #define FLEXIO0_D13_P2_5 A15X_MUX('2',5,6) /* PT2_5 */ 249 #define P2_6 A15X_MUX('2',6,0) /* PT2_6 */ 250 #define ADC1_A3_P2_6 A15X_MUX('2',6,0) /* PT2_6 */ 251 #define TRIG_OUT4_P2_6 A15X_MUX('2',6,1) /* PT2_6 */ 252 #define LPSPI1_PCS1_P2_6 A15X_MUX('2',6,2) /* PT2_6 */ 253 #define LPUART4_RXD_P2_6 A15X_MUX('2',6,3) /* PT2_6 */ 254 #define CT_INP18_P2_6 A15X_MUX('2',6,4) /* PT2_6 */ 255 #define CT1_MAT2_P2_6 A15X_MUX('2',6,5) /* PT2_6 */ 256 #define FLEXIO0_D14_P2_6 A15X_MUX('2',6,6) /* PT2_6 */ 257 #define ADC0_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ 258 #define P2_7 A15X_MUX('2',7,0) /* PT2_7 */ 259 #define VREFI_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ 260 #define ADC1_A7_P2_7 A15X_MUX('2',7,0) /* PT2_7 */ 261 #define TRIG_IN5_P2_7 A15X_MUX('2',7,1) /* PT2_7 */ 262 #define LPUART4_TXD_P2_7 A15X_MUX('2',7,3) /* PT2_7 */ 263 #define CT_INP19_P2_7 A15X_MUX('2',7,4) /* PT2_7 */ 264 #define CT1_MAT3_P2_7 A15X_MUX('2',7,5) /* PT2_7 */ 265 #define FLEXIO0_D15_P2_7 A15X_MUX('2',7,6) /* PT2_7 */ 266 #define ADC0_A5_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ 267 #define OPAMP0_INP0_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ 268 #define P2_12 A15X_MUX('2',12,0) /* PT2_12 */ 269 #define WUU0_IN20_P2_12 A15X_MUX('2',12,0) /* PT2_12 */ 270 #define USB0_VBUS_DET_P2_12 A15X_MUX('2',12,1) /* PT2_12 */ 271 #define LPSPI1_SCK_P2_12 A15X_MUX('2',12,2) /* PT2_12 */ 272 #define LPUART1_RXD_P2_12 A15X_MUX('2',12,3) /* PT2_12 */ 273 #define CT4_MAT0_P2_12 A15X_MUX('2',12,4) /* PT2_12 */ 274 #define CT0_MAT0_P2_12 A15X_MUX('2',12,5) /* PT2_12 */ 275 #define FLEXIO0_D20_P2_12 A15X_MUX('2',12,6) /* PT2_12 */ 276 #define CAN0_RXD_P2_12 A15X_MUX('2',12,11) /* PT2_12 */ 277 #define OPAMP0_INN_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ 278 #define OPAMP0_INP1_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ 279 #define ADC1_A5_P2_13 A15X_MUX('2',13,0) /* PT2_13 */ 280 #define P2_13 A15X_MUX('2',13,0) /* PT2_13 */ 281 #define TRIG_IN8_P2_13 A15X_MUX('2',13,1) /* PT2_13 */ 282 #define LPSPI1_SDO_P2_13 A15X_MUX('2',13,2) /* PT2_13 */ 283 #define LPUART1_TXD_P2_13 A15X_MUX('2',13,3) /* PT2_13 */ 284 #define CT4_MAT1_P2_13 A15X_MUX('2',13,4) /* PT2_13 */ 285 #define CT0_MAT1_P2_13 A15X_MUX('2',13,5) /* PT2_13 */ 286 #define FLEXIO0_D21_P2_13 A15X_MUX('2',13,6) /* PT2_13 */ 287 #define CAN0_TXD_P2_13 A15X_MUX('2',13,11) /* PT2_13 */ 288 #define ADC0_A2_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ 289 #define P2_15 A15X_MUX('2',15,0) /* PT2_15 */ 290 #define OPAMP0_OUT_P2_15 A15X_MUX('2',15,0) /* PT2_15 */ 291 #define TRIG_OUT4_P2_15 A15X_MUX('2',15,1) /* PT2_15 */ 292 #define LPSPI1_SDI_P2_15 A15X_MUX('2',15,2) /* PT2_15 */ 293 #define LPUART1_RTS_B_P2_15 A15X_MUX('2',15,3) /* PT2_15 */ 294 #define CT4_MAT3_P2_15 A15X_MUX('2',15,4) /* PT2_15 */ 295 #define CT0_MAT2_P2_15 A15X_MUX('2',15,5) /* PT2_15 */ 296 #define FLEXIO0_D23_P2_15 A15X_MUX('2',15,6) /* PT2_15 */ 297 #define WUU0_IN22_P3_0 A15X_MUX('3',0,0) /* PT3_0 */ 298 #define P3_0 A15X_MUX('3',0,0) /* PT3_0 */ 299 #define TRIG_IN0_P3_0 A15X_MUX('3',0,1) /* PT3_0 */ 300 #define LPUART3_RXD_P3_0 A15X_MUX('3',0,3) /* PT3_0 */ 301 #define CT_INP16_P3_0 A15X_MUX('3',0,4) /* PT3_0 */ 302 #define PWM0_A0_P3_0 A15X_MUX('3',0,5) /* PT3_0 */ 303 #define FLEXIO0_D8_P3_0 A15X_MUX('3',0,6) /* PT3_0 */ 304 #define PWM1_X0_P3_0 A15X_MUX('3',0,7) /* PT3_0 */ 305 #define P3_1 A15X_MUX('3',1,0) /* PT3_1 */ 306 #define TRIG_IN1_P3_1 A15X_MUX('3',1,1) /* PT3_1 */ 307 #define LPUART3_TXD_P3_1 A15X_MUX('3',1,3) /* PT3_1 */ 308 #define CT_INP17_P3_1 A15X_MUX('3',1,4) /* PT3_1 */ 309 #define PWM0_B0_P3_1 A15X_MUX('3',1,5) /* PT3_1 */ 310 #define FLEXIO0_D9_P3_1 A15X_MUX('3',1,6) /* PT3_1 */ 311 #define PWM1_X1_P3_1 A15X_MUX('3',1,7) /* PT3_1 */ 312 #define FREQME_CLK_OUT0_P3_1 A15X_MUX('3',1,12) /* PT3_1 */ 313 #define P3_6 A15X_MUX('3',6,0) /* PT3_6 */ 314 #define CLKOUT_P3_6 A15X_MUX('3',6,1) /* PT3_6 */ 315 #define LPSPI1_PCS3_P3_6 A15X_MUX('3',6,2) /* PT3_6 */ 316 #define LPUART3_RTS_B_P3_6 A15X_MUX('3',6,3) /* PT3_6 */ 317 #define CT4_MAT2_P3_6 A15X_MUX('3',6,4) /* PT3_6 */ 318 #define PWM0_A0_P3_6 A15X_MUX('3',6,5) /* PT3_6 */ 319 #define FLEXIO0_D14_P3_6 A15X_MUX('3',6,6) /* PT3_6 */ 320 #define PWM1_A0_P3_6 A15X_MUX('3',6,7) /* PT3_6 */ 321 #define FREQME_CLK_OUT1_P3_6 A15X_MUX('3',6,12) /* PT3_6 */ 322 #define P3_7 A15X_MUX('3',7,0) /* PT3_7 */ 323 #define TRIG_IN2_P3_7 A15X_MUX('3',7,1) /* PT3_7 */ 324 #define LPSPI1_PCS2_P3_7 A15X_MUX('3',7,2) /* PT3_7 */ 325 #define LPUART3_CTS_B_P3_7 A15X_MUX('3',7,3) /* PT3_7 */ 326 #define CT4_MAT3_P3_7 A15X_MUX('3',7,4) /* PT3_7 */ 327 #define PWM0_B0_P3_7 A15X_MUX('3',7,5) /* PT3_7 */ 328 #define FLEXIO0_D15_P3_7 A15X_MUX('3',7,6) /* PT3_7 */ 329 #define PWM1_B0_P3_7 A15X_MUX('3',7,7) /* PT3_7 */ 330 #define P3_8 A15X_MUX('3',8,0) /* PT3_8 */ 331 #define WUU0_IN23_P3_8 A15X_MUX('3',8,0) /* PT3_8 */ 332 #define TRIG_IN3_P3_8 A15X_MUX('3',8,1) /* PT3_8 */ 333 #define LPSPI1_SDO_P3_8 A15X_MUX('3',8,2) /* PT3_8 */ 334 #define LPUART1_RXD_P3_8 A15X_MUX('3',8,3) /* PT3_8 */ 335 #define CT_INP4_P3_8 A15X_MUX('3',8,4) /* PT3_8 */ 336 #define PWM0_A1_P3_8 A15X_MUX('3',8,5) /* PT3_8 */ 337 #define FLEXIO0_D16_P3_8 A15X_MUX('3',8,6) /* PT3_8 */ 338 #define CLKOUT_P3_8 A15X_MUX('3',8,12) /* PT3_8 */ 339 #define P3_9 A15X_MUX('3',9,0) /* PT3_9 */ 340 #define TRIG_IN4_P3_9 A15X_MUX('3',9,1) /* PT3_9 */ 341 #define LPSPI1_SDI_P3_9 A15X_MUX('3',9,2) /* PT3_9 */ 342 #define LPUART1_TXD_P3_9 A15X_MUX('3',9,3) /* PT3_9 */ 343 #define CT_INP5_P3_9 A15X_MUX('3',9,4) /* PT3_9 */ 344 #define PWM0_B1_P3_9 A15X_MUX('3',9,5) /* PT3_9 */ 345 #define FLEXIO0_D17_P3_9 A15X_MUX('3',9,6) /* PT3_9 */ 346 #define P3_10 A15X_MUX('3',10,0) /* PT3_10 */ 347 #define TRIG_IN5_P3_10 A15X_MUX('3',10,1) /* PT3_10 */ 348 #define LPSPI1_SCK_P3_10 A15X_MUX('3',10,2) /* PT3_10 */ 349 #define LPUART1_RTS_B_P3_10 A15X_MUX('3',10,3) /* PT3_10 */ 350 #define CT1_MAT0_P3_10 A15X_MUX('3',10,4) /* PT3_10 */ 351 #define PWM0_A2_P3_10 A15X_MUX('3',10,5) /* PT3_10 */ 352 #define FLEXIO0_D18_P3_10 A15X_MUX('3',10,6) /* PT3_10 */ 353 #define P3_11 A15X_MUX('3',11,0) /* PT3_11 */ 354 #define WUU0_IN24_P3_11 A15X_MUX('3',11,0) /* PT3_11 */ 355 #define TRIG_IN6_P3_11 A15X_MUX('3',11,1) /* PT3_11 */ 356 #define LPSPI1_PCS0_P3_11 A15X_MUX('3',11,2) /* PT3_11 */ 357 #define LPUART1_CTS_B_P3_11 A15X_MUX('3',11,3) /* PT3_11 */ 358 #define CT1_MAT1_P3_11 A15X_MUX('3',11,4) /* PT3_11 */ 359 #define PWM0_B2_P3_11 A15X_MUX('3',11,5) /* PT3_11 */ 360 #define FLEXIO0_D19_P3_11 A15X_MUX('3',11,6) /* PT3_11 */ 361 #define P3_12 A15X_MUX('3',12,0) /* PT3_12 */ 362 #define LPUART2_RTS_B_P3_12 A15X_MUX('3',12,2) /* PT3_12 */ 363 #define LPUART3_TXD_P3_12 A15X_MUX('3',12,3) /* PT3_12 */ 364 #define CT1_MAT2_P3_12 A15X_MUX('3',12,4) /* PT3_12 */ 365 #define PWM0_X0_P3_12 A15X_MUX('3',12,5) /* PT3_12 */ 366 #define FLEXIO0_D20_P3_12 A15X_MUX('3',12,6) /* PT3_12 */ 367 #define PWM1_A2_P3_12 A15X_MUX('3',12,7) /* PT3_12 */ 368 #define P3_13 A15X_MUX('3',13,0) /* PT3_13 */ 369 #define LPUART2_CTS_B_P3_13 A15X_MUX('3',13,2) /* PT3_13 */ 370 #define LPUART3_RXD_P3_13 A15X_MUX('3',13,3) /* PT3_13 */ 371 #define CT1_MAT3_P3_13 A15X_MUX('3',13,4) /* PT3_13 */ 372 #define PWM0_X1_P3_13 A15X_MUX('3',13,5) /* PT3_13 */ 373 #define FLEXIO0_D21_P3_13 A15X_MUX('3',13,6) /* PT3_13 */ 374 #define PWM1_B2_P3_13 A15X_MUX('3',13,7) /* PT3_13 */ 375 #define WUU0_IN25_P3_14 A15X_MUX('3',14,0) /* PT3_14 */ 376 #define P3_14 A15X_MUX('3',14,0) /* PT3_14 */ 377 #define LPUART2_RXD_P3_14 A15X_MUX('3',14,2) /* PT3_14 */ 378 #define LPUART3_CTS_B_P3_14 A15X_MUX('3',14,3) /* PT3_14 */ 379 #define CT_INP6_P3_14 A15X_MUX('3',14,4) /* PT3_14 */ 380 #define PWM0_X2_P3_14 A15X_MUX('3',14,5) /* PT3_14 */ 381 #define FLEXIO0_D22_P3_14 A15X_MUX('3',14,6) /* PT3_14 */ 382 #define PWM1_A1_P3_14 A15X_MUX('3',14,7) /* PT3_14 */ 383 #define P3_15 A15X_MUX('3',15,0) /* PT3_15 */ 384 #define LPUART2_TXD_P3_15 A15X_MUX('3',15,2) /* PT3_15 */ 385 #define LPUART3_RTS_B_P3_15 A15X_MUX('3',15,3) /* PT3_15 */ 386 #define CT_INP7_P3_15 A15X_MUX('3',15,4) /* PT3_15 */ 387 #define FLEXIO0_D23_P3_15 A15X_MUX('3',15,6) /* PT3_15 */ 388 #define PWM1_B1_P3_15 A15X_MUX('3',15,7) /* PT3_15 */ 389 #define WUU0_IN30_P3_27 A15X_MUX('3',27,0) /* PT3_27 */ 390 #define P3_27 A15X_MUX('3',27,0) /* PT3_27 */ 391 #define TRIG_OUT7_P3_27 A15X_MUX('3',27,1) /* PT3_27 */ 392 #define LPI2C3_SCL_P3_27 A15X_MUX('3',27,2) /* PT3_27 */ 393 #define LPUART4_TXD_P3_27 A15X_MUX('3',27,3) /* PT3_27 */ 394 #define CT_INP13_P3_27 A15X_MUX('3',27,4) /* PT3_27 */ 395 #define CT3_MAT1_P3_27 A15X_MUX('3',27,5) /* PT3_27 */ 396 #define FLEXIO0_D27_P3_27 A15X_MUX('3',27,6) /* PT3_27 */ 397 #define WUU0_IN26_P3_28 A15X_MUX('3',28,0) /* PT3_28 */ 398 #define P3_28 A15X_MUX('3',28,0) /* PT3_28 */ 399 #define TRIG_IN11_P3_28 A15X_MUX('3',28,1) /* PT3_28 */ 400 #define LPI2C3_SDA_P3_28 A15X_MUX('3',28,2) /* PT3_28 */ 401 #define LPUART4_RXD_P3_28 A15X_MUX('3',28,3) /* PT3_28 */ 402 #define CT_INP12_P3_28 A15X_MUX('3',28,4) /* PT3_28 */ 403 #define CT3_MAT2_P3_28 A15X_MUX('3',28,5) /* PT3_28 */ 404 #define FLEXIO0_D28_P3_28 A15X_MUX('3',28,6) /* PT3_28 */ 405 #define WUU0_IN27_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ 406 #define P3_29 A15X_MUX('3',29,0) /* PT3_29 */ 407 #define ADC1_A22_P3_29 A15X_MUX('3',29,0) /* PT3_29 */ 408 #define ISPMODE_N_P3_29 A15X_MUX('3',29,1) /* PT3_29 */ 409 #define LPI2C3_HREQ_P3_29 A15X_MUX('3',29,2) /* PT3_29 */ 410 #define CT_INP3_P3_29 A15X_MUX('3',29,4) /* PT3_29 */ 411 #define CT3_MAT3_P3_29 A15X_MUX('3',29,5) /* PT3_29 */ 412 #define FLEXIO0_D29_P3_29 A15X_MUX('3',29,6) /* PT3_29 */ 413 #define ADC1_A21_P3_30 A15X_MUX('3',30,0) /* PT3_30 */ 414 #define P3_30 A15X_MUX('3',30,0) /* PT3_30 */ 415 #define TRIG_OUT6_P3_30 A15X_MUX('3',30,1) /* PT3_30 */ 416 #define LPI2C3_SCLS_P3_30 A15X_MUX('3',30,2) /* PT3_30 */ 417 #define LPUART4_RTS_B_P3_30 A15X_MUX('3',30,3) /* PT3_30 */ 418 #define CT0_MAT2_P3_30 A15X_MUX('3',30,4) /* PT3_30 */ 419 #define FLEXIO0_D30_P3_30 A15X_MUX('3',30,6) /* PT3_30 */ 420 #define P3_31 A15X_MUX('3',31,0) /* PT3_31 */ 421 #define LPTMR0_ALT2_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ 422 #define ADC1_A20_P3_31 A15X_MUX('3',31,0) /* PT3_31 */ 423 #define TRIG_IN10_P3_31 A15X_MUX('3',31,1) /* PT3_31 */ 424 #define LPI2C3_SDAS_P3_31 A15X_MUX('3',31,2) /* PT3_31 */ 425 #define LPUART4_CTS_B_P3_31 A15X_MUX('3',31,3) /* PT3_31 */ 426 #define CT0_MAT3_P3_31 A15X_MUX('3',31,4) /* PT3_31 */ 427 #define FLEXIO0_D31_P3_31 A15X_MUX('3',31,6) /* PT3_31 */ 428 #endif 429
