1 /* 2 * NOTE: File generated by lpc_cfg_utils.py 3 * from LPC55S69JBD64/signal_configuration.xml 4 * 5 * Copyright (c) 2022, NXP 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #ifndef _ZEPHYR_DTS_BINDING_LPC55S69JBD64_ 10 #define _ZEPHYR_DTS_BINDING_LPC55S69JBD64_ 11 12 #define IOCON_MUX(offset, type, mux) \ 13 (((offset & 0xFFF) << 20) | \ 14 (((type) & 0x3) << 18) | \ 15 (((mux) & 0xF) << 0)) 16 17 #define IOCON_TYPE_D 0x0 18 #define IOCON_TYPE_I 0x1 19 #define IOCON_TYPE_A 0x2 20 21 #define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ 22 #define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 23 #define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 24 #define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 25 #define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 26 #define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 27 #define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 28 #define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 29 #define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 30 #define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 31 #define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 32 #define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 33 #define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 34 #define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 35 #define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 36 #define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 37 #define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 38 #define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 39 #define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 40 #define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 41 #define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 42 #define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 43 #define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 44 #define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 45 #define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 46 #define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 47 #define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 48 #define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 49 #define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 50 #define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 51 #define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 52 #define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 53 #define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 54 #define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 55 #define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ 56 #define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 57 #define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 58 #define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 59 #define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 60 #define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 61 #define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 62 #define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 63 #define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 64 #define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 65 #define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 66 #define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ 67 #define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ 68 #define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ 69 #define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ 70 #define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ 71 #define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ 72 #define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ 73 #define SD1_CARD_INT_N_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 6) /* PIO0_0 */ 74 #define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ 75 #define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ 76 #define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ 77 #define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ 78 #define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 79 #define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 80 #define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 81 #define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 82 #define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 83 #define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 84 #define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 85 #define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 86 #define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 87 #define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 88 #define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 89 #define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 90 #define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 91 #define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 92 #define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 93 #define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 94 #define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 95 #define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 96 #define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 97 #define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 98 #define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 99 #define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 100 #define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 101 #define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 102 #define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 103 #define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 104 #define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 105 #define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 106 #define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 107 #define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 108 #define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 109 #define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 110 #define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 111 #define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 112 #define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 113 #define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 114 #define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 115 #define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 116 #define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 117 #define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 118 #define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 119 #define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 120 #define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 121 #define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 122 #define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 123 #define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 124 #define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 125 #define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 126 #define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 127 #define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 128 #define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 129 #define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 130 #define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 131 #define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ 132 #define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 133 #define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 134 #define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 135 #define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 136 #define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 137 #define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 138 #define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 139 #define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 140 #define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 141 #define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ 142 #define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ 143 #define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ 144 #define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ 145 #define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ 146 #define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ 147 #define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ 148 #define SD1_CLK_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 6) /* PIO0_1 */ 149 #define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ 150 #define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ 151 #define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ 152 #define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 153 #define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 154 #define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 155 #define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 156 #define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 157 #define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 158 #define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 159 #define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 160 #define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 161 #define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 162 #define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 163 #define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 164 #define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 165 #define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 166 #define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 167 #define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 168 #define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 169 #define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 170 #define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 171 #define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 172 #define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 173 #define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 174 #define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 175 #define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 176 #define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 177 #define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 178 #define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 179 #define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 180 #define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 181 #define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 182 #define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 183 #define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 184 #define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 185 #define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 186 #define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 187 #define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 188 #define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 189 #define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 190 #define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 191 #define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 192 #define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 193 #define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 194 #define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 195 #define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 196 #define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 197 #define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 198 #define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 199 #define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 200 #define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 201 #define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 202 #define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 203 #define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 204 #define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 205 #define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ 206 #define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 207 #define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 208 #define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 209 #define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 210 #define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 211 #define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 212 #define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 213 #define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 214 #define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 215 #define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ 216 #define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ 217 #define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ 218 #define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ 219 #define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ 220 #define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ 221 #define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ 222 #define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ 223 #define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ 224 #define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ 225 #define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ 226 #define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ 227 #define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 228 #define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 229 #define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 230 #define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 231 #define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 232 #define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 233 #define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 234 #define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 235 #define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 236 #define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 237 #define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 238 #define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 239 #define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 240 #define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 241 #define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 242 #define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 243 #define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 244 #define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 245 #define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 246 #define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 247 #define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 248 #define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 249 #define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 250 #define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 251 #define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 252 #define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 253 #define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 254 #define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 255 #define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 256 #define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 257 #define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 258 #define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 259 #define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 260 #define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ 261 #define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 262 #define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 263 #define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 264 #define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 265 #define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 266 #define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 267 #define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 268 #define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 269 #define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 270 #define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ 271 #define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ 272 #define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ 273 #define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ 274 #define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ 275 #define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ 276 #define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ 277 #define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ 278 #define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ 279 #define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ 280 #define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ 281 #define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 282 #define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 283 #define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 284 #define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 285 #define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 286 #define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 287 #define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 288 #define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 289 #define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 290 #define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 291 #define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 292 #define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 293 #define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 294 #define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 295 #define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 296 #define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 297 #define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 298 #define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 299 #define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 300 #define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 301 #define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 302 #define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 303 #define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 304 #define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 305 #define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 306 #define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 307 #define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 308 #define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 309 #define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 310 #define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 311 #define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 312 #define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 313 #define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 314 #define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 315 #define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 316 #define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 317 #define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 318 #define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 319 #define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 320 #define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 321 #define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 322 #define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 323 #define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 324 #define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 325 #define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 326 #define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 327 #define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 328 #define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 329 #define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 330 #define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 331 #define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 332 #define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 333 #define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 334 #define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ 335 #define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ 336 #define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 337 #define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 338 #define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 339 #define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 340 #define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 341 #define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 342 #define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 343 #define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 344 #define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 345 #define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ 346 #define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ 347 #define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ 348 #define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ 349 #define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ 350 #define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ 351 #define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ 352 #define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ 353 #define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ 354 #define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ 355 #define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ 356 #define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 357 #define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 358 #define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 359 #define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 360 #define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 361 #define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 362 #define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 363 #define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 364 #define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 365 #define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 366 #define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 367 #define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 368 #define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 369 #define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 370 #define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 371 #define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 372 #define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 373 #define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 374 #define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 375 #define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 376 #define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 377 #define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 378 #define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 379 #define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 380 #define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 381 #define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 382 #define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 383 #define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 384 #define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 385 #define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 386 #define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 387 #define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 388 #define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 389 #define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ 390 #define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ 391 #define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 392 #define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ 393 #define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 394 #define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 395 #define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 396 #define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 397 #define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 398 #define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 399 #define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 400 #define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 401 #define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ 402 #define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ 403 #define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ 404 #define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ 405 #define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ 406 #define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ 407 #define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ 408 #define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ 409 #define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ 410 #define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ 411 #define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 412 #define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 413 #define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 414 #define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 415 #define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 416 #define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 417 #define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 418 #define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 419 #define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 420 #define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 421 #define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 422 #define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 423 #define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 424 #define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 425 #define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 426 #define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 427 #define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 428 #define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 429 #define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 430 #define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 431 #define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ 432 #define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 433 #define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 434 #define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 435 #define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 436 #define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 437 #define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 438 #define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 439 #define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 440 #define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 441 #define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 442 #define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 443 #define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 444 #define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 445 #define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 446 #define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 447 #define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 448 #define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 449 #define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 450 #define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 451 #define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 452 #define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 453 #define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 454 #define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 455 #define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 456 #define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 457 #define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 458 #define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 459 #define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 460 #define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 461 #define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 462 #define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 463 #define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 464 #define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 465 #define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ 466 #define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 467 #define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 468 #define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 469 #define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 470 #define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 471 #define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 472 #define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 473 #define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 474 #define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 475 #define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ 476 #define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ 477 #define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ 478 #define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ 479 #define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ 480 #define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ 481 #define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ 482 #define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ 483 #define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ 484 #define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ 485 #define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 486 #define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 487 #define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 488 #define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 489 #define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 490 #define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 491 #define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 492 #define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 493 #define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 494 #define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 495 #define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 496 #define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 497 #define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 498 #define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 499 #define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 500 #define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 501 #define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 502 #define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 503 #define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 504 #define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 505 #define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 506 #define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 507 #define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 508 #define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 509 #define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 510 #define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 511 #define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 512 #define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 513 #define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 514 #define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 515 #define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 516 #define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 517 #define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 518 #define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 4) /* PIO0_7 */ 519 #define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 1) /* PIO0_7 */ 520 #define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 3) /* PIO0_7 */ 521 #define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 522 #define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 523 #define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 524 #define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 525 #define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 526 #define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 527 #define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 528 #define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 529 #define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 0) /* PIO0_7 */ 530 #define SD0_CLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 2) /* PIO0_7 */ 531 #define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ 532 #define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ 533 #define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_D, 10) /* PIO0_7 */ 534 #define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 535 #define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 536 #define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 537 #define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 538 #define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 539 #define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 540 #define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 541 #define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 542 #define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 543 #define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 544 #define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 545 #define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 546 #define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 547 #define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 548 #define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 549 #define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 550 #define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 551 #define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 552 #define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 553 #define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 554 #define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 555 #define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 556 #define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 557 #define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 558 #define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 559 #define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 560 #define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 561 #define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 562 #define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 563 #define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 564 #define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 565 #define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 566 #define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 567 #define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ 568 #define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ 569 #define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 570 #define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 571 #define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 572 #define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 573 #define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 574 #define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 575 #define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 576 #define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 577 #define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 578 #define SD0_CMD_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 2) /* PIO0_8 */ 579 #define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ 580 #define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ 581 #define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ 582 #define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ 583 #define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 584 #define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 585 #define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 586 #define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 587 #define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 588 #define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 589 #define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 590 #define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 591 #define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 592 #define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 593 #define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 594 #define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 595 #define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 596 #define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 597 #define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 598 #define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 599 #define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 600 #define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 601 #define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 602 #define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 603 #define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 604 #define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 605 #define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 606 #define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 607 #define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 608 #define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 609 #define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 610 #define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 611 #define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 612 #define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 613 #define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 614 #define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 615 #define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 616 #define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ 617 #define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ 618 #define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 619 #define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 620 #define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 621 #define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 622 #define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 623 #define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 624 #define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 625 #define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 626 #define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 627 #define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 628 #define SD0_POW_EN_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 2) /* PIO0_9 */ 629 #define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ 630 #define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ 631 #define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ 632 #define ADC0_CH1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 633 #define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 634 #define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 635 #define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 636 #define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 637 #define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 638 #define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 639 #define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 640 #define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 641 #define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 642 #define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 643 #define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 644 #define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 645 #define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 3) /* PIO0_10 */ 646 #define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 647 #define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 648 #define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 649 #define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 650 #define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 651 #define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 652 #define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 653 #define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 2) /* PIO0_10 */ 654 #define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 655 #define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 656 #define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 657 #define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 658 #define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 659 #define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 660 #define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 661 #define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 662 #define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 663 #define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 664 #define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 665 #define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 666 #define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 667 #define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 668 #define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 669 #define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 670 #define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 671 #define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 672 #define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 673 #define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 674 #define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 675 #define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 676 #define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 677 #define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 678 #define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 679 #define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 680 #define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 681 #define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 682 #define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 683 #define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 684 #define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 685 #define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 686 #define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 687 #define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 4) /* PIO0_10 */ 688 #define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 1) /* PIO0_10 */ 689 #define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 690 #define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 691 #define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 692 #define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 693 #define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 694 #define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 695 #define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 696 #define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 697 #define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 0) /* PIO0_10 */ 698 #define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 5) /* PIO0_10 */ 699 #define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ 700 #define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ 701 #define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 10) /* PIO0_10 */ 702 #define SWO_PIO0_10 IOCON_MUX(10, IOCON_TYPE_A, 6) /* PIO0_10 */ 703 #define ADC0_CH9_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 704 #define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 2) /* PIO0_11 */ 705 #define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 706 #define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 707 #define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 708 #define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 709 #define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 710 #define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 711 #define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 712 #define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 713 #define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 714 #define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 715 #define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 716 #define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 717 #define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 718 #define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 719 #define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 720 #define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 721 #define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 722 #define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 723 #define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 724 #define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 725 #define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 726 #define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 727 #define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 728 #define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 729 #define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 730 #define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 731 #define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 732 #define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 733 #define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 734 #define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 735 #define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 736 #define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 737 #define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 738 #define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 1) /* PIO0_11 */ 739 #define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 740 #define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 741 #define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 742 #define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 743 #define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 744 #define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 745 #define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 746 #define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 747 #define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 0) /* PIO0_11 */ 748 #define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ 749 #define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ 750 #define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 10) /* PIO0_11 */ 751 #define SWCLK_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 6) /* PIO0_11 */ 752 #define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_A, 3) /* PIO0_11 */ 753 #define ADC0_CH10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 754 #define DMA0_TRIG00_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 755 #define DMA0_TRIG010_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 756 #define DMA0_TRIG011_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 757 #define DMA0_TRIG012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 758 #define DMA0_TRIG013_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 759 #define DMA0_TRIG014_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 760 #define DMA0_TRIG015_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 761 #define DMA0_TRIG016_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 762 #define DMA0_TRIG017_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 763 #define DMA0_TRIG018_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 764 #define DMA0_TRIG019_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 765 #define DMA0_TRIG01_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 766 #define DMA0_TRIG020_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 767 #define DMA0_TRIG021_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 768 #define DMA0_TRIG022_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 769 #define DMA0_TRIG02_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 770 #define DMA0_TRIG03_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 771 #define DMA0_TRIG04_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 772 #define DMA0_TRIG05_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 773 #define DMA0_TRIG06_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 774 #define DMA0_TRIG07_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 775 #define DMA0_TRIG08_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 776 #define DMA0_TRIG09_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 777 #define DMA1_TRIG10_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 778 #define DMA1_TRIG11_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 779 #define DMA1_TRIG12_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 780 #define DMA1_TRIG13_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 781 #define DMA1_TRIG14_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 782 #define DMA1_TRIG15_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 783 #define DMA1_TRIG16_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 784 #define DMA1_TRIG17_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 785 #define DMA1_TRIG18_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 786 #define DMA1_TRIG19_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 787 #define FC3_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 1) /* PIO0_12 */ 788 #define FC6_TXD_SCL_MISO_WS_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 7) /* PIO0_12 */ 789 #define GPIO_PIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 790 #define PINT_PINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 791 #define PINT_PINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 792 #define PINT_PINT2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 793 #define PINT_PINT3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 794 #define PINT_PINT4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 795 #define PINT_PINT5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 796 #define PINT_PINT6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 797 #define PINT_PINT7_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 0) /* PIO0_12 */ 798 #define SCT0_IN0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ 799 #define SCT0_IN1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ 800 #define SCT0_IN2_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ 801 #define SCT0_IN3_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ 802 #define SCT0_IN4_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ 803 #define SCT0_IN5_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ 804 #define SCT0_IN6_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 4) /* PIO0_12 */ 805 #define SD0_POW_EN_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 5) /* PIO0_12 */ 806 #define SD1_BACKEND_PWR_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 2) /* PIO0_12 */ 807 #define SECGPIO_SECPIO012_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ 808 #define SECPINT_SECPINT0_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ 809 #define SECPINT_SECPINT1_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 10) /* PIO0_12 */ 810 #define SWDIO_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 6) /* PIO0_12 */ 811 #define SYSCON_FREQMEB_PIO0_12 IOCON_MUX(12, IOCON_TYPE_A, 3) /* PIO0_12 */ 812 #define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 813 #define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 814 #define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 815 #define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 816 #define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 817 #define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 818 #define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 819 #define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 820 #define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 821 #define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 822 #define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 823 #define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 824 #define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 825 #define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 826 #define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 827 #define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 828 #define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 829 #define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 830 #define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 831 #define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 832 #define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 833 #define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 834 #define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 835 #define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 836 #define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 837 #define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 838 #define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 839 #define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 840 #define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 841 #define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 842 #define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 843 #define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 844 #define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 845 #define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 846 #define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 847 #define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 848 #define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 849 #define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 850 #define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 851 #define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 852 #define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 853 #define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 854 #define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 855 #define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 856 #define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 857 #define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 858 #define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 859 #define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 860 #define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 861 #define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 862 #define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 863 #define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 864 #define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 865 #define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ 866 #define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ 867 #define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 868 #define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 869 #define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 870 #define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 871 #define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 872 #define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 873 #define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 874 #define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 875 #define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 876 #define PLU_INPUT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 9) /* PIO0_13 */ 877 #define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ 878 #define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ 879 #define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ 880 #define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ 881 #define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ 882 #define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ 883 #define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ 884 #define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ 885 #define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ 886 #define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ 887 #define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ 888 #define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 889 #define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 890 #define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 891 #define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 892 #define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 893 #define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 894 #define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 895 #define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 896 #define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 897 #define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 898 #define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 899 #define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 900 #define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 901 #define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 902 #define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 903 #define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 904 #define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 905 #define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 906 #define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 907 #define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 908 #define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 909 #define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 910 #define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 911 #define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 912 #define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 913 #define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 914 #define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 915 #define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 916 #define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 917 #define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 918 #define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 919 #define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 920 #define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 921 #define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 922 #define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 923 #define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 924 #define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 925 #define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 926 #define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 927 #define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 928 #define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 929 #define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 930 #define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 931 #define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 932 #define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 933 #define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 934 #define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 935 #define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 936 #define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 937 #define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 938 #define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 939 #define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 940 #define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 941 #define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ 942 #define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ 943 #define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 944 #define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 945 #define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 946 #define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 947 #define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 948 #define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 949 #define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 950 #define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 951 #define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 952 #define PLU_INPUT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 9) /* PIO0_14 */ 953 #define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ 954 #define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ 955 #define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ 956 #define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ 957 #define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ 958 #define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ 959 #define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ 960 #define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ 961 #define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ 962 #define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ 963 #define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ 964 #define ADC0_CH2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 965 #define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 966 #define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 967 #define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 968 #define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 969 #define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 970 #define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 971 #define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 972 #define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 973 #define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 974 #define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 975 #define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 976 #define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 977 #define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 978 #define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 979 #define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 980 #define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 981 #define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 982 #define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 983 #define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 984 #define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 3) /* PIO0_15 */ 985 #define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 986 #define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 987 #define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 988 #define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 989 #define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 990 #define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 991 #define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 992 #define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 993 #define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 994 #define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 995 #define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 996 #define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 997 #define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 998 #define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 999 #define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1000 #define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1001 #define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1002 #define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1003 #define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1004 #define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1005 #define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1006 #define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1007 #define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1008 #define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1009 #define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1010 #define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1011 #define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1012 #define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1013 #define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1014 #define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1015 #define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1016 #define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1017 #define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1018 #define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 1) /* PIO0_15 */ 1019 #define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1020 #define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1021 #define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1022 #define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1023 #define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1024 #define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1025 #define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1026 #define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1027 #define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 0) /* PIO0_15 */ 1028 #define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 4) /* PIO0_15 */ 1029 #define SD0_WR_PRT_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 5) /* PIO0_15 */ 1030 #define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ 1031 #define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ 1032 #define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 10) /* PIO0_15 */ 1033 #define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_A, 2) /* PIO0_15 */ 1034 #define ADC0_CH8_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1035 #define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 2) /* PIO0_16 */ 1036 #define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1037 #define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1038 #define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1039 #define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1040 #define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1041 #define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1042 #define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1043 #define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1044 #define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1045 #define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1046 #define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1047 #define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1048 #define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1049 #define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1050 #define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1051 #define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1052 #define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1053 #define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1054 #define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1055 #define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 3) /* PIO0_16 */ 1056 #define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1057 #define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1058 #define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1059 #define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1060 #define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1061 #define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1062 #define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1063 #define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1064 #define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1065 #define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1066 #define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1067 #define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1068 #define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1069 #define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1070 #define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1071 #define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1072 #define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1073 #define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1074 #define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1075 #define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1076 #define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1077 #define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1078 #define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1079 #define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1080 #define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1081 #define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1082 #define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1083 #define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1084 #define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1085 #define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1086 #define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1087 #define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1088 #define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1089 #define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 1) /* PIO0_16 */ 1090 #define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1091 #define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1092 #define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1093 #define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1094 #define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1095 #define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1096 #define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1097 #define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1098 #define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 0) /* PIO0_16 */ 1099 #define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ 1100 #define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ 1101 #define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_A, 10) /* PIO0_16 */ 1102 #define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1103 #define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1104 #define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1105 #define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1106 #define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1107 #define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1108 #define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1109 #define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1110 #define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1111 #define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1112 #define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1113 #define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1114 #define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1115 #define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1116 #define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1117 #define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1118 #define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1119 #define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1120 #define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1121 #define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1122 #define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1123 #define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1124 #define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1125 #define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1126 #define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1127 #define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1128 #define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1129 #define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1130 #define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1131 #define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1132 #define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1133 #define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1134 #define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1135 #define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 1) /* PIO0_17 */ 1136 #define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1137 #define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1138 #define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1139 #define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1140 #define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1141 #define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1142 #define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1143 #define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1144 #define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 0) /* PIO0_17 */ 1145 #define PLU_INPUT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 9) /* PIO0_17 */ 1146 #define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ 1147 #define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ 1148 #define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ 1149 #define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ 1150 #define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ 1151 #define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ 1152 #define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 3) /* PIO0_17 */ 1153 #define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 4) /* PIO0_17 */ 1154 #define SD0_CARD_DET_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 2) /* PIO0_17 */ 1155 #define SD0_CARD_INT_N_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 8) /* PIO0_17 */ 1156 #define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ 1157 #define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ 1158 #define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_D, 10) /* PIO0_17 */ 1159 #define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ 1160 #define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1161 #define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1162 #define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1163 #define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1164 #define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1165 #define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1166 #define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1167 #define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1168 #define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1169 #define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1170 #define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1171 #define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1172 #define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1173 #define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1174 #define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1175 #define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1176 #define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1177 #define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1178 #define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1179 #define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1180 #define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1181 #define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1182 #define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1183 #define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1184 #define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1185 #define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1186 #define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1187 #define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1188 #define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1189 #define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1190 #define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1191 #define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1192 #define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1193 #define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ 1194 #define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1195 #define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1196 #define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1197 #define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1198 #define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1199 #define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1200 #define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1201 #define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1202 #define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1203 #define PLU_INPUT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 9) /* PIO0_18 */ 1204 #define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 1205 #define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ 1206 #define SD0_WR_PRT_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 2) /* PIO0_18 */ 1207 #define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ 1208 #define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ 1209 #define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ 1210 #define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ 1211 #define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1212 #define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1213 #define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1214 #define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1215 #define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1216 #define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1217 #define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1218 #define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1219 #define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1220 #define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1221 #define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1222 #define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1223 #define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1224 #define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1225 #define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1226 #define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1227 #define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1228 #define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1229 #define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1230 #define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1231 #define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1232 #define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1233 #define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1234 #define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1235 #define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1236 #define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1237 #define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1238 #define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1239 #define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1240 #define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1241 #define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1242 #define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1243 #define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1244 #define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ 1245 #define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ 1246 #define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1247 #define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1248 #define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1249 #define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1250 #define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1251 #define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1252 #define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1253 #define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1254 #define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 1255 #define PLU_INPUT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ 1256 #define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ 1257 #define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ 1258 #define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ 1259 #define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ 1260 #define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ 1261 #define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1262 #define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1263 #define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1264 #define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1265 #define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1266 #define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1267 #define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1268 #define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1269 #define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ 1270 #define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1271 #define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1272 #define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1273 #define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1274 #define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1275 #define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1276 #define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1277 #define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1278 #define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1279 #define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1280 #define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1281 #define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 1282 #define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1283 #define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1284 #define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1285 #define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1286 #define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1287 #define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1288 #define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1289 #define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1290 #define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1291 #define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1292 #define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1293 #define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1294 #define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1295 #define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1296 #define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1297 #define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1298 #define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1299 #define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1300 #define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1301 #define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1302 #define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1303 #define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1304 #define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1305 #define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1306 #define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1307 #define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1308 #define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1309 #define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1310 #define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1311 #define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1312 #define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1313 #define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1314 #define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1315 #define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ 1316 #define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ 1317 #define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ 1318 #define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1319 #define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ 1320 #define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1321 #define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1322 #define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1323 #define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1324 #define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1325 #define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1326 #define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1327 #define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 1328 #define PLU_INPUT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 9) /* PIO0_20 */ 1329 #define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ 1330 #define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ 1331 #define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ 1332 #define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ 1333 #define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ 1334 #define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ 1335 #define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ 1336 #define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ 1337 #define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ 1338 #define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ 1339 #define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ 1340 #define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1341 #define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1342 #define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1343 #define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1344 #define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1345 #define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1346 #define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1347 #define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1348 #define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1349 #define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1350 #define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1351 #define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1352 #define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1353 #define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1354 #define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1355 #define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1356 #define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1357 #define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1358 #define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1359 #define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1360 #define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1361 #define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1362 #define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1363 #define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1364 #define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1365 #define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1366 #define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1367 #define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1368 #define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1369 #define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1370 #define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1371 #define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1372 #define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1373 #define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ 1374 #define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ 1375 #define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1376 #define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1377 #define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1378 #define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1379 #define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1380 #define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1381 #define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1382 #define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1383 #define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 1384 #define PLU_CLKIN_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ 1385 #define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ 1386 #define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ 1387 #define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ 1388 #define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ 1389 #define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ 1390 #define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ 1391 #define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ 1392 #define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ 1393 #define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ 1394 #define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ 1395 #define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ 1396 #define CTIMER0_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1397 #define CTIMER0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1398 #define CTIMER0_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1399 #define CTIMER0_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1400 #define CTIMER1_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1401 #define CTIMER1_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1402 #define CTIMER1_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1403 #define CTIMER1_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1404 #define CTIMER2_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1405 #define CTIMER2_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1406 #define CTIMER2_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1407 #define CTIMER2_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1408 #define CTIMER3_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1409 #define CTIMER3_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1410 #define CTIMER3_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1411 #define CTIMER3_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1412 #define CTIMER4_CAPTURE0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1413 #define CTIMER4_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1414 #define CTIMER4_CAPTURE2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1415 #define CTIMER4_CAPTURE3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 3) /* PIO0_22 */ 1416 #define DMA0_TRIG00_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1417 #define DMA0_TRIG010_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1418 #define DMA0_TRIG011_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1419 #define DMA0_TRIG012_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1420 #define DMA0_TRIG013_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1421 #define DMA0_TRIG014_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1422 #define DMA0_TRIG015_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1423 #define DMA0_TRIG016_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1424 #define DMA0_TRIG017_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1425 #define DMA0_TRIG018_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1426 #define DMA0_TRIG019_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1427 #define DMA0_TRIG01_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1428 #define DMA0_TRIG020_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1429 #define DMA0_TRIG021_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1430 #define DMA0_TRIG022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1431 #define DMA0_TRIG02_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1432 #define DMA0_TRIG03_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1433 #define DMA0_TRIG04_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1434 #define DMA0_TRIG05_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1435 #define DMA0_TRIG06_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1436 #define DMA0_TRIG07_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1437 #define DMA0_TRIG08_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1438 #define DMA0_TRIG09_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1439 #define DMA1_TRIG10_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1440 #define DMA1_TRIG11_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1441 #define DMA1_TRIG12_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1442 #define DMA1_TRIG13_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1443 #define DMA1_TRIG14_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1444 #define DMA1_TRIG15_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1445 #define DMA1_TRIG16_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1446 #define DMA1_TRIG17_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1447 #define DMA1_TRIG18_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1448 #define DMA1_TRIG19_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1449 #define FC6_TXD_SCL_MISO_WS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 1) /* PIO0_22 */ 1450 #define GPIO_PIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1451 #define PINT_PINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1452 #define PINT_PINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1453 #define PINT_PINT2_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1454 #define PINT_PINT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1455 #define PINT_PINT4_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1456 #define PINT_PINT5_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1457 #define PINT_PINT6_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1458 #define PINT_PINT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 0) /* PIO0_22 */ 1459 #define PLU_OUT7_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 9) /* PIO0_22 */ 1460 #define SCT0_OUT3_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 4) /* PIO0_22 */ 1461 #define SDIF_SD1_D0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 8) /* PIO0_22 */ 1462 #define SECGPIO_SECPIO022_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ 1463 #define SECPINT_SECPINT0_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ 1464 #define SECPINT_SECPINT1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 10) /* PIO0_22 */ 1465 #define USB0_VBUS_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 7) /* PIO0_22 */ 1466 #define UTICK0_CAPTURE1_PIO0_22 IOCON_MUX(22, IOCON_TYPE_D, 2) /* PIO0_22 */ 1467 #define ADC0_CH0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1468 #define CTIMER1_MATCH2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 2) /* PIO0_23 */ 1469 #define CTIMER3_MATCH3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 3) /* PIO0_23 */ 1470 #define DMA0_TRIG00_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1471 #define DMA0_TRIG010_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1472 #define DMA0_TRIG011_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1473 #define DMA0_TRIG012_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1474 #define DMA0_TRIG013_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1475 #define DMA0_TRIG014_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1476 #define DMA0_TRIG015_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1477 #define DMA0_TRIG016_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1478 #define DMA0_TRIG017_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1479 #define DMA0_TRIG018_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1480 #define DMA0_TRIG019_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1481 #define DMA0_TRIG01_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1482 #define DMA0_TRIG020_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1483 #define DMA0_TRIG021_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1484 #define DMA0_TRIG022_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1485 #define DMA0_TRIG02_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1486 #define DMA0_TRIG03_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1487 #define DMA0_TRIG04_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1488 #define DMA0_TRIG05_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1489 #define DMA0_TRIG06_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1490 #define DMA0_TRIG07_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1491 #define DMA0_TRIG08_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1492 #define DMA0_TRIG09_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1493 #define DMA1_TRIG10_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1494 #define DMA1_TRIG11_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1495 #define DMA1_TRIG12_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1496 #define DMA1_TRIG13_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1497 #define DMA1_TRIG14_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1498 #define DMA1_TRIG15_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1499 #define DMA1_TRIG16_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1500 #define DMA1_TRIG17_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1501 #define DMA1_TRIG18_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1502 #define DMA1_TRIG19_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1503 #define FC0_CTS_SDA_SSEL0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 5) /* PIO0_23 */ 1504 #define GPIO_PIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1505 #define MCLK_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 1) /* PIO0_23 */ 1506 #define PINT_PINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1507 #define PINT_PINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1508 #define PINT_PINT2_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1509 #define PINT_PINT3_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1510 #define PINT_PINT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1511 #define PINT_PINT5_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1512 #define PINT_PINT6_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1513 #define PINT_PINT7_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 0) /* PIO0_23 */ 1514 #define SCT0_OUT4_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 4) /* PIO0_23 */ 1515 #define SDIF_SD1_D1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 8) /* PIO0_23 */ 1516 #define SECGPIO_SECPIO023_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ 1517 #define SECPINT_SECPINT0_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ 1518 #define SECPINT_SECPINT1_PIO0_23 IOCON_MUX(23, IOCON_TYPE_A, 10) /* PIO0_23 */ 1519 #define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1520 #define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1521 #define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1522 #define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1523 #define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1524 #define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1525 #define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1526 #define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1527 #define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1528 #define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1529 #define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1530 #define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1531 #define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1532 #define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1533 #define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1534 #define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1535 #define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1536 #define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1537 #define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1538 #define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 3) /* PIO0_24 */ 1539 #define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1540 #define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1541 #define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1542 #define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1543 #define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1544 #define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1545 #define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1546 #define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1547 #define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1548 #define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1549 #define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1550 #define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1551 #define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1552 #define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1553 #define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1554 #define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1555 #define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1556 #define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1557 #define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1558 #define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1559 #define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1560 #define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1561 #define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1562 #define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1563 #define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1564 #define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1565 #define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1566 #define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1567 #define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1568 #define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1569 #define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1570 #define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1571 #define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1572 #define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 1) /* PIO0_24 */ 1573 #define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1574 #define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1575 #define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1576 #define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1577 #define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1578 #define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1579 #define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1580 #define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1581 #define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 0) /* PIO0_24 */ 1582 #define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ 1583 #define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ 1584 #define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ 1585 #define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ 1586 #define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ 1587 #define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ 1588 #define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 4) /* PIO0_24 */ 1589 #define SDIF_SD0_D0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 2) /* PIO0_24 */ 1590 #define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ 1591 #define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ 1592 #define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_D, 10) /* PIO0_24 */ 1593 #define CTIMER0_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1594 #define CTIMER0_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1595 #define CTIMER0_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1596 #define CTIMER0_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1597 #define CTIMER1_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1598 #define CTIMER1_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1599 #define CTIMER1_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1600 #define CTIMER1_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1601 #define CTIMER2_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1602 #define CTIMER2_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1603 #define CTIMER2_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1604 #define CTIMER2_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1605 #define CTIMER3_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1606 #define CTIMER3_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1607 #define CTIMER3_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1608 #define CTIMER3_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1609 #define CTIMER4_CAPTURE0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1610 #define CTIMER4_CAPTURE1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1611 #define CTIMER4_CAPTURE2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1612 #define CTIMER4_CAPTURE3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 3) /* PIO0_25 */ 1613 #define DMA0_TRIG00_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1614 #define DMA0_TRIG010_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1615 #define DMA0_TRIG011_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1616 #define DMA0_TRIG012_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1617 #define DMA0_TRIG013_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1618 #define DMA0_TRIG014_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1619 #define DMA0_TRIG015_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1620 #define DMA0_TRIG016_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1621 #define DMA0_TRIG017_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1622 #define DMA0_TRIG018_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1623 #define DMA0_TRIG019_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1624 #define DMA0_TRIG01_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1625 #define DMA0_TRIG020_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1626 #define DMA0_TRIG021_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1627 #define DMA0_TRIG022_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1628 #define DMA0_TRIG02_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1629 #define DMA0_TRIG03_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1630 #define DMA0_TRIG04_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1631 #define DMA0_TRIG05_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1632 #define DMA0_TRIG06_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1633 #define DMA0_TRIG07_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1634 #define DMA0_TRIG08_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1635 #define DMA0_TRIG09_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1636 #define DMA1_TRIG10_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1637 #define DMA1_TRIG11_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1638 #define DMA1_TRIG12_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1639 #define DMA1_TRIG13_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1640 #define DMA1_TRIG14_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1641 #define DMA1_TRIG15_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1642 #define DMA1_TRIG16_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1643 #define DMA1_TRIG17_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1644 #define DMA1_TRIG18_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1645 #define DMA1_TRIG19_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1646 #define FC0_TXD_SCL_MISO_WS_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 1) /* PIO0_25 */ 1647 #define GPIO_PIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1648 #define PINT_PINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1649 #define PINT_PINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1650 #define PINT_PINT2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1651 #define PINT_PINT3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1652 #define PINT_PINT4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1653 #define PINT_PINT5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1654 #define PINT_PINT6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1655 #define PINT_PINT7_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 0) /* PIO0_25 */ 1656 #define SCT0_IN0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ 1657 #define SCT0_IN1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ 1658 #define SCT0_IN2_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ 1659 #define SCT0_IN3_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ 1660 #define SCT0_IN4_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ 1661 #define SCT0_IN5_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ 1662 #define SCT0_IN6_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 4) /* PIO0_25 */ 1663 #define SDIF_SD0_D1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 2) /* PIO0_25 */ 1664 #define SECGPIO_SECPIO025_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ 1665 #define SECPINT_SECPINT0_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ 1666 #define SECPINT_SECPINT1_PIO0_25 IOCON_MUX(25, IOCON_TYPE_D, 10) /* PIO0_25 */ 1667 #define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ 1668 #define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1669 #define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1670 #define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1671 #define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1672 #define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1673 #define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1674 #define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1675 #define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1676 #define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1677 #define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1678 #define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1679 #define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1680 #define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1681 #define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1682 #define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1683 #define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1684 #define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1685 #define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1686 #define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1687 #define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 1688 #define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1689 #define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1690 #define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1691 #define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1692 #define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1693 #define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1694 #define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1695 #define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1696 #define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1697 #define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1698 #define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1699 #define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1700 #define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1701 #define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1702 #define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1703 #define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1704 #define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1705 #define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1706 #define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1707 #define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1708 #define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1709 #define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1710 #define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1711 #define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1712 #define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1713 #define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1714 #define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1715 #define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1716 #define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1717 #define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1718 #define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1719 #define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1720 #define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1721 #define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ 1722 #define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ 1723 #define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1724 #define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ 1725 #define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1726 #define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1727 #define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1728 #define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1729 #define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1730 #define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1731 #define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1732 #define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 1733 #define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ 1734 #define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ 1735 #define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ 1736 #define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ 1737 #define USB0_IDVALUE_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 7) /* PIO0_26 */ 1738 #define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ 1739 #define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1740 #define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1741 #define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1742 #define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1743 #define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1744 #define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1745 #define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1746 #define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1747 #define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1748 #define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1749 #define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1750 #define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1751 #define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1752 #define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1753 #define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1754 #define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1755 #define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1756 #define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1757 #define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1758 #define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1759 #define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1760 #define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1761 #define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1762 #define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1763 #define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1764 #define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1765 #define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1766 #define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1767 #define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1768 #define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1769 #define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1770 #define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1771 #define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1772 #define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ 1773 #define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ 1774 #define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1775 #define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1776 #define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1777 #define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1778 #define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1779 #define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1780 #define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1781 #define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1782 #define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 1783 #define PLU_OUT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 9) /* PIO0_27 */ 1784 #define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ 1785 #define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ 1786 #define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ 1787 #define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ 1788 #define CTIMER0_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1789 #define CTIMER0_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1790 #define CTIMER0_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1791 #define CTIMER0_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1792 #define CTIMER1_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1793 #define CTIMER1_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1794 #define CTIMER1_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1795 #define CTIMER1_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1796 #define CTIMER2_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1797 #define CTIMER2_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1798 #define CTIMER2_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1799 #define CTIMER2_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1800 #define CTIMER3_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1801 #define CTIMER3_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1802 #define CTIMER3_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1803 #define CTIMER3_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1804 #define CTIMER4_CAPTURE0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1805 #define CTIMER4_CAPTURE1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1806 #define CTIMER4_CAPTURE2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1807 #define CTIMER4_CAPTURE3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 3) /* PIO0_28 */ 1808 #define DMA0_TRIG00_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1809 #define DMA0_TRIG010_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1810 #define DMA0_TRIG011_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1811 #define DMA0_TRIG012_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1812 #define DMA0_TRIG013_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1813 #define DMA0_TRIG014_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1814 #define DMA0_TRIG015_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1815 #define DMA0_TRIG016_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1816 #define DMA0_TRIG017_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1817 #define DMA0_TRIG018_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1818 #define DMA0_TRIG019_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1819 #define DMA0_TRIG01_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1820 #define DMA0_TRIG020_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1821 #define DMA0_TRIG021_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1822 #define DMA0_TRIG022_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1823 #define DMA0_TRIG02_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1824 #define DMA0_TRIG03_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1825 #define DMA0_TRIG04_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1826 #define DMA0_TRIG05_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1827 #define DMA0_TRIG06_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1828 #define DMA0_TRIG07_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1829 #define DMA0_TRIG08_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1830 #define DMA0_TRIG09_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1831 #define DMA1_TRIG10_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1832 #define DMA1_TRIG11_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1833 #define DMA1_TRIG12_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1834 #define DMA1_TRIG13_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1835 #define DMA1_TRIG14_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1836 #define DMA1_TRIG15_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1837 #define DMA1_TRIG16_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1838 #define DMA1_TRIG17_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1839 #define DMA1_TRIG18_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1840 #define DMA1_TRIG19_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1841 #define FC0_SCK_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 1) /* PIO0_28 */ 1842 #define GPIO_PIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1843 #define PINT_PINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1844 #define PINT_PINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1845 #define PINT_PINT2_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1846 #define PINT_PINT3_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1847 #define PINT_PINT4_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1848 #define PINT_PINT5_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1849 #define PINT_PINT6_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1850 #define PINT_PINT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 0) /* PIO0_28 */ 1851 #define PLU_OUT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 9) /* PIO0_28 */ 1852 #define SCT0_OUT7_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 4) /* PIO0_28 */ 1853 #define SD1_CMD_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 2) /* PIO0_28 */ 1854 #define SECGPIO_SECPIO028_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ 1855 #define SECPINT_SECPINT0_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ 1856 #define SECPINT_SECPINT1_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 10) /* PIO0_28 */ 1857 #define USB0_OVERCURRENTN_PIO0_28 IOCON_MUX(28, IOCON_TYPE_D, 7) /* PIO0_28 */ 1858 #define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ 1859 #define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ 1860 #define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1861 #define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1862 #define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1863 #define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1864 #define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1865 #define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1866 #define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1867 #define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1868 #define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1869 #define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1870 #define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1871 #define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1872 #define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1873 #define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1874 #define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1875 #define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1876 #define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1877 #define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1878 #define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1879 #define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1880 #define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1881 #define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1882 #define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1883 #define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1884 #define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1885 #define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1886 #define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1887 #define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1888 #define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1889 #define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1890 #define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1891 #define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1892 #define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1893 #define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ 1894 #define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1895 #define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1896 #define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1897 #define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1898 #define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1899 #define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1900 #define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1901 #define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1902 #define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 1903 #define PLU_OUT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 9) /* PIO0_29 */ 1904 #define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ 1905 #define SDIF_SD1_D2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 2) /* PIO0_29 */ 1906 #define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ 1907 #define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ 1908 #define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ 1909 #define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ 1910 #define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1911 #define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1912 #define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1913 #define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1914 #define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1915 #define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1916 #define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1917 #define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1918 #define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1919 #define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1920 #define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1921 #define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1922 #define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1923 #define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1924 #define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1925 #define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1926 #define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1927 #define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1928 #define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1929 #define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1930 #define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1931 #define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1932 #define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1933 #define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1934 #define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1935 #define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1936 #define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1937 #define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1938 #define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1939 #define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1940 #define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1941 #define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1942 #define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1943 #define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ 1944 #define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1945 #define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1946 #define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1947 #define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1948 #define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1949 #define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1950 #define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1951 #define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1952 #define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 1953 #define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ 1954 #define SDIF_SD1_D3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 2) /* PIO0_30 */ 1955 #define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ 1956 #define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ 1957 #define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ 1958 #define ADC0_CH3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1959 #define CTIMER0_MATCH1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 3) /* PIO0_31 */ 1960 #define DMA0_TRIG00_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1961 #define DMA0_TRIG010_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1962 #define DMA0_TRIG011_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1963 #define DMA0_TRIG012_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1964 #define DMA0_TRIG013_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1965 #define DMA0_TRIG014_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1966 #define DMA0_TRIG015_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1967 #define DMA0_TRIG016_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1968 #define DMA0_TRIG017_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1969 #define DMA0_TRIG018_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1970 #define DMA0_TRIG019_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1971 #define DMA0_TRIG01_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1972 #define DMA0_TRIG020_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1973 #define DMA0_TRIG021_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1974 #define DMA0_TRIG022_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1975 #define DMA0_TRIG02_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1976 #define DMA0_TRIG03_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1977 #define DMA0_TRIG04_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1978 #define DMA0_TRIG05_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1979 #define DMA0_TRIG06_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1980 #define DMA0_TRIG07_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1981 #define DMA0_TRIG08_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1982 #define DMA0_TRIG09_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1983 #define DMA1_TRIG10_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1984 #define DMA1_TRIG11_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1985 #define DMA1_TRIG12_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1986 #define DMA1_TRIG13_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1987 #define DMA1_TRIG14_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1988 #define DMA1_TRIG15_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1989 #define DMA1_TRIG16_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1990 #define DMA1_TRIG17_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1991 #define DMA1_TRIG18_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1992 #define DMA1_TRIG19_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1993 #define FC0_CTS_SDA_SSEL0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 1) /* PIO0_31 */ 1994 #define GPIO_PIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1995 #define PINT_PINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1996 #define PINT_PINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1997 #define PINT_PINT2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1998 #define PINT_PINT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 1999 #define PINT_PINT4_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 2000 #define PINT_PINT5_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 2001 #define PINT_PINT6_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 2002 #define PINT_PINT7_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 0) /* PIO0_31 */ 2003 #define SCT0_OUT3_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 4) /* PIO0_31 */ 2004 #define SDIF_SD0_D2_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 2) /* PIO0_31 */ 2005 #define SECGPIO_SECPIO031_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ 2006 #define SECPINT_SECPINT0_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ 2007 #define SECPINT_SECPINT1_PIO0_31 IOCON_MUX(31, IOCON_TYPE_A, 10) /* PIO0_31 */ 2008 #define ADC0_CH11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2009 #define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2010 #define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2011 #define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2012 #define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2013 #define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2014 #define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2015 #define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2016 #define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2017 #define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2018 #define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2019 #define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2020 #define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2021 #define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2022 #define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2023 #define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2024 #define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2025 #define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2026 #define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2027 #define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2028 #define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 3) /* PIO1_0 */ 2029 #define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2030 #define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2031 #define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2032 #define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2033 #define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2034 #define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2035 #define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2036 #define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2037 #define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2038 #define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2039 #define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2040 #define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2041 #define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2042 #define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2043 #define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2044 #define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2045 #define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2046 #define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2047 #define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2048 #define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2049 #define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2050 #define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2051 #define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2052 #define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2053 #define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2054 #define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2055 #define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2056 #define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2057 #define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2058 #define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2059 #define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2060 #define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2061 #define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2062 #define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 1) /* PIO1_0 */ 2063 #define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2064 #define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2065 #define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2066 #define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2067 #define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2068 #define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2069 #define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2070 #define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2071 #define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 0) /* PIO1_0 */ 2072 #define PLU_OUT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 9) /* PIO1_0 */ 2073 #define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ 2074 #define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ 2075 #define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ 2076 #define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ 2077 #define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ 2078 #define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ 2079 #define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 4) /* PIO1_0 */ 2080 #define SDIF_SD0_D3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_A, 2) /* PIO1_0 */ 2081 #define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2082 #define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2083 #define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2084 #define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2085 #define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2086 #define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2087 #define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2088 #define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2089 #define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2090 #define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2091 #define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2092 #define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2093 #define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2094 #define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2095 #define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2096 #define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2097 #define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2098 #define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2099 #define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2100 #define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 2101 #define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2102 #define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2103 #define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2104 #define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2105 #define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2106 #define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2107 #define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2108 #define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2109 #define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2110 #define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2111 #define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2112 #define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2113 #define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2114 #define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2115 #define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2116 #define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2117 #define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2118 #define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2119 #define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2120 #define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2121 #define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2122 #define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2123 #define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2124 #define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2125 #define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2126 #define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2127 #define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2128 #define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2129 #define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2130 #define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2131 #define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2132 #define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2133 #define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2134 #define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ 2135 #define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2136 #define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ 2137 #define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2138 #define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2139 #define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2140 #define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2141 #define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2142 #define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2143 #define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2144 #define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 2145 #define PLU_OUT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 9) /* PIO1_1 */ 2146 #define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ 2147 #define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ 2148 #define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ 2149 #define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ 2150 #define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ 2151 #define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ 2152 #define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ 2153 #define USB1_OVERCURRENTN_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 7) /* PIO1_1 */ 2154 #define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ 2155 #define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2156 #define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2157 #define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2158 #define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2159 #define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2160 #define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2161 #define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2162 #define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2163 #define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2164 #define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2165 #define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2166 #define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2167 #define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2168 #define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2169 #define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2170 #define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2171 #define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2172 #define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2173 #define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2174 #define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2175 #define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2176 #define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2177 #define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2178 #define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2179 #define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2180 #define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2181 #define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2182 #define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2183 #define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2184 #define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2185 #define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2186 #define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2187 #define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2188 #define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2189 #define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ 2190 #define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2191 #define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2192 #define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2193 #define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2194 #define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2195 #define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2196 #define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2197 #define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 2198 #define PLU_OUT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 9) /* PIO1_2 */ 2199 #define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ 2200 #define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ 2201 #define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ 2202 #define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ 2203 #define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ 2204 #define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ 2205 #define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ 2206 #define USB1_PORTPWRN_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 7) /* PIO1_2 */ 2207 #define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2208 #define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2209 #define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2210 #define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2211 #define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2212 #define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2213 #define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2214 #define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2215 #define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2216 #define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2217 #define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2218 #define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2219 #define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2220 #define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2221 #define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2222 #define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2223 #define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2224 #define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2225 #define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2226 #define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2227 #define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2228 #define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2229 #define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2230 #define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2231 #define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2232 #define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2233 #define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2234 #define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2235 #define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2236 #define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2237 #define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2238 #define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2239 #define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2240 #define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2241 #define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ 2242 #define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2243 #define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2244 #define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2245 #define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2246 #define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2247 #define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2248 #define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2249 #define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 2250 #define PLU_OUT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 9) /* PIO1_3 */ 2251 #define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ 2252 #define USB0_PORTPWRN_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 7) /* PIO1_3 */ 2253 2254 #endif 2255
