1 /*
2  * Copyright 2021-2023 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 /**
7 *   @file       Clock_Ip_Pll.c
8 *   @version    1.0.0
9 *
10 *   @brief   CLOCK driver implementations.
11 *   @details CLOCK driver implementations.
12 *
13 *   @addtogroup CLOCK_DRIVER Clock Ip Driver
14 *   @{
15 */
16 
17 #ifdef __cplusplus
18 extern "C"{
19 #endif
20 
21 
22 /*==================================================================================================
23 *                                          INCLUDE FILES
24 * 1) system and project includes
25 * 2) needed interfaces from external units
26 * 3) internal and external interfaces from this unit
27 ==================================================================================================*/
28 
29 #include "Clock_Ip_Private.h"
30 
31 /*==================================================================================================
32                                SOURCE FILE VERSION INFORMATION
33 ==================================================================================================*/
34 #define CLOCK_IP_PLL_VENDOR_ID_C                      43
35 #define CLOCK_IP_PLL_AR_RELEASE_MAJOR_VERSION_C       4
36 #define CLOCK_IP_PLL_AR_RELEASE_MINOR_VERSION_C       7
37 #define CLOCK_IP_PLL_AR_RELEASE_REVISION_VERSION_C    0
38 #define CLOCK_IP_PLL_SW_MAJOR_VERSION_C               1
39 #define CLOCK_IP_PLL_SW_MINOR_VERSION_C               0
40 #define CLOCK_IP_PLL_SW_PATCH_VERSION_C               0
41 
42 /*==================================================================================================
43 *                                     FILE VERSION CHECKS
44 ==================================================================================================*/
45 /* Check if Clock_Ip_Pll.c file and Clock_Ip_Private.h file are of the same vendor */
46 #if (CLOCK_IP_PLL_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID)
47     #error "Clock_Ip_Pll.c and Clock_Ip_Private.h have different vendor ids"
48 #endif
49 
50 /* Check if Clock_Ip_Pll.c file and Clock_Ip_Private.h file are of the same Autosar version */
51 #if ((CLOCK_IP_PLL_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \
52      (CLOCK_IP_PLL_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \
53      (CLOCK_IP_PLL_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \
54     )
55     #error "AutoSar Version Numbers of Clock_Ip_Pll.c and Clock_Ip_Private.h are different"
56 #endif
57 
58 /* Check if Clock_Ip_Pll.c file and Clock_Ip_Private.h file are of the same Software version */
59 #if ((CLOCK_IP_PLL_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \
60      (CLOCK_IP_PLL_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \
61      (CLOCK_IP_PLL_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \
62     )
63     #error "Software Version Numbers of Clock_Ip_Pll.c and Clock_Ip_Private.h are different"
64 #endif
65 
66 /*==================================================================================================
67 *                           LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
68 ==================================================================================================*/
69 
70 /*==================================================================================================
71 *                                          LOCAL MACROS
72 ==================================================================================================*/
73 
74 /*==================================================================================================
75 *                                         LOCAL CONSTANTS
76 ==================================================================================================*/
77 
78 /*==================================================================================================
79 *                                         LOCAL VARIABLES
80 ==================================================================================================*/
81 
82 /*==================================================================================================
83 *                                        GLOBAL CONSTANTS
84 ==================================================================================================*/
85 
86 /*==================================================================================================
87 *                                        GLOBAL VARIABLES
88 ==================================================================================================*/
89 
90 /*==================================================================================================
91 *                                    GLOBAL FUNCTION PROTOTYPES
92 ==================================================================================================*/
93 /* Clock start section code */
94 #define MCU_START_SEC_CODE
95 
96 #include "Mcu_MemMap.h"
97 
98 /*==================================================================================================
99 *                                    LOCAL FUNCTION PROTOTYPES
100 ==================================================================================================*/
101 
102 
103 static void Clock_Ip_CallbackPllEmpty(Clock_Ip_PllConfigType const* Config);
104 static Clock_Ip_PllStatusReturnType Clock_Ip_CallbackPllEmptyComplete(Clock_Ip_NameType PllName);
105 static void Clock_Ip_CallbackPllEmptyDisable(Clock_Ip_NameType PllName);
106 
107 #ifdef CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE
108 static void Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* Config);
109 static void Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* Config);
110 static Clock_Ip_PllStatusReturnType Clock_Ip_CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_NameType PllName);
111 static void Clock_Ip_EnablePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* Config);
112 #endif
113 #ifdef CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN
114 static void Clock_Ip_ResetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* Config);
115 static void Clock_Ip_SetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* Config);
116 static Clock_Ip_PllStatusReturnType Clock_Ip_CompletePlldigRdivMfiMfnSdmen(Clock_Ip_NameType PllName);
117 static void Clock_Ip_EnablePlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* Config);
118 #endif
119 #ifdef CLOCK_IP_LFASTPLL_ENABLE
120 static void Clock_Ip_ResetLfastPLL(Clock_Ip_PllConfigType const* Config);
121 static void Clock_Ip_SetLfastPLL(Clock_Ip_PllConfigType const* Config);
122 static Clock_Ip_PllStatusReturnType Clock_Ip_CompleteLfastPLL(Clock_Ip_NameType PllName);
123 static void Clock_Ip_EnableLfastPLL(Clock_Ip_PllConfigType const* Config);
124 #endif
125 
126 
127 /* Clock stop section code */
128 #define MCU_STOP_SEC_CODE
129 
130 #include "Mcu_MemMap.h"
131 
132 /*==================================================================================================
133 *                                         LOCAL FUNCTIONS
134 ==================================================================================================*/
135 
136 #define MCU_START_SEC_CODE
137 /* Clock start section code */
138 
139 #include "Mcu_MemMap.h"
140 
141 
Clock_Ip_CallbackPllEmpty(Clock_Ip_PllConfigType const * Config)142 static void Clock_Ip_CallbackPllEmpty(Clock_Ip_PllConfigType const* Config)
143 {
144     (void)Config;
145     /* No implementation */
146 }
Clock_Ip_CallbackPllEmptyComplete(Clock_Ip_NameType PllName)147 static Clock_Ip_PllStatusReturnType Clock_Ip_CallbackPllEmptyComplete(Clock_Ip_NameType PllName)
148 {
149     (void)PllName;
150     /* No implementation */
151     return STATUS_PLL_LOCKED;
152 }
Clock_Ip_CallbackPllEmptyDisable(Clock_Ip_NameType PllName)153 static void Clock_Ip_CallbackPllEmptyDisable(Clock_Ip_NameType PllName)
154 {
155     (void)PllName;
156     /* No implementation */
157 }
158 
159 
160 /* Pll with frequency modulation */
161 #ifdef CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE
162 #ifndef CLOCK_IP_FIRC_PLL_REFERENCE
163     #define CLOCK_IP_FIRC_PLL_REFERENCE 0U
164 #endif
165 #ifndef CLOCK_IP_FXOSC_PLL_REFERENCE
166     #define CLOCK_IP_FXOSC_PLL_REFERENCE 1U
167 #endif
Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const * Config)168 static void Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* Config)
169 {
170     uint32 Instance;
171     uint8 DividerIndex;
172 
173     if (NULL_PTR != Config)
174     {
175         Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
176 
177         /* Disable output dividers */
178         for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++)
179         {
180             Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLLDIG_PLLODIV_DE_MASK;
181         }
182 
183         /* Power down PLL */
184         Clock_Ip_apxPll[Instance].PllInstance->PLLCR |= PLLDIG_PLLCR_PLLPD_MASK;
185     }
186     else
187     {
188         (void)Instance;
189         (void)DividerIndex;
190     }
191 }
Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const * Config)192 static void Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* Config)
193 {
194     uint32 Instance;
195     uint32 Value;
196 
197     if (NULL_PTR != Config)
198     {
199         Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
200 
201         if (Config->Enable != 0U)
202         {
203             /* Name of the input reference clock */
204             switch (Config->InputReference)
205             {
206                 case FIRC_CLK:
207                     /* Select input reference. */
208                     Clock_Ip_apxPll[Instance].PllInstance->PLLCLKMUX = PLLDIG_PLLCLKMUX_REFCLKSEL(CLOCK_IP_FIRC_PLL_REFERENCE);
209                     break;
210                 case FXOSC_CLK:
211                     /* Select input reference. */
212                     Clock_Ip_apxPll[Instance].PllInstance->PLLCLKMUX = PLLDIG_PLLCLKMUX_REFCLKSEL(CLOCK_IP_FXOSC_PLL_REFERENCE);
213                     break;
214                 default:
215                     /* Command is not implemented on this platform */
216                     break;
217             }
218 
219             /* Configure PLL: predivider and multiplier */
220             Value = Clock_Ip_apxPll[Instance].PllInstance->PLLDV;
221             Value &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK);
222             Value |= (uint32) (PLLDIG_PLLDV_RDIV(Config->Predivider)   |
223                                 PLLDIG_PLLDV_MFI(Config->MulFactorDiv));
224             Clock_Ip_apxPll[Instance].PllInstance->PLLDV = Value;
225             /* Set numerator fractional loop divider and sigma delta modulation */
226             Value = Clock_Ip_apxPll[Instance].PllInstance->PLLFD;
227             Value &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK);
228             Value |=  PLLDIG_PLLFD_MFN(Config->NumeratorFracLoopDiv);
229             Value |= PLLDIG_PLLFD_SDMEN(Config->SigmaDelta);
230             Clock_Ip_apxPll[Instance].PllInstance->PLLFD = Value;
231             /* Configure modulation */
232             Value = (uint32) (PLLDIG_PLLFM_SSCGBYP(Config->FrequencyModulationBypass)               |
233                               PLLDIG_PLLFM_SPREADCTL(Config->ModulationType)                        |
234                               PLLDIG_PLLFM_STEPNO(Config->IncrementStep)                            |
235                               PLLDIG_PLLFM_STEPSIZE(Config->ModulationPeriod));
236             Clock_Ip_apxPll[Instance].PllInstance->PLLFM = Value;
237         }
238     }
239     else
240     {
241         (void)Instance;
242         (void)Value;
243     }
244 }
245 
Clock_Ip_CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_NameType PllName)246 static Clock_Ip_PllStatusReturnType Clock_Ip_CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_NameType PllName)
247 {
248     Clock_Ip_PllStatusReturnType PllStatus = STATUS_PLL_LOCKED;
249 
250     boolean TimeoutOccurred = FALSE;
251     uint32 StartTime;
252     uint32 ElapsedTime;
253     uint32 TimeoutTicks;
254     uint32 PllLockStatus;
255     uint32 Instance = Clock_Ip_au8ClockFeatures[PllName][CLOCK_IP_MODULE_INSTANCE];
256 
257     if (0U == (Clock_Ip_apxPll[Instance].PllInstance->PLLCR & PLLDIG_PLLCR_PLLPD_MASK))
258     {
259         Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_IP_TIMEOUT_VALUE_US);
260         /* Wait until this pll is locked */
261         do
262         {
263             PllLockStatus = ((Clock_Ip_apxPll[Instance].PllInstance->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT);
264             TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
265         }
266         while ((0U == PllLockStatus) && (FALSE == TimeoutOccurred));
267 
268         if (TRUE == TimeoutOccurred)
269         {
270             PllStatus = STATUS_PLL_UNLOCKED;
271             /* Report timeout error */
272             Clock_Ip_ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, PllName);
273         }
274     }
275     else
276     {
277         PllStatus = STATUS_PLL_NOT_ENABLED;
278     }
279 
280     return PllStatus;
281 }
Clock_Ip_EnablePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const * Config)282 static void Clock_Ip_EnablePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize(Clock_Ip_PllConfigType const* Config)
283 {
284     uint32 Instance;
285 
286     if (NULL_PTR != Config)
287     {
288         Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
289 
290         /* Configure PLL. */
291         if (1U == Config->Enable)
292         {
293             /* Send command to enable PLL device. */
294             Clock_Ip_apxPll[Instance].PllInstance->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK;
295         }
296     }
297     else
298     {
299         (void)Instance;
300     }
301 }
302 #endif
303 
304 /* Pll without frequency modulation */
305 #ifdef CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN
306 #ifndef CLOCK_IP_FIRC_PLL_REFERENCE
307     #define CLOCK_IP_FIRC_PLL_REFERENCE 0U
308 #endif
309 #ifndef CLOCK_IP_FXOSC_PLL_REFERENCE
310     #define CLOCK_IP_FXOSC_PLL_REFERENCE 1U
311 #endif
Clock_Ip_ResetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const * Config)312 static void Clock_Ip_ResetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* Config)
313 {
314     uint32 Instance;
315     uint8 DividerIndex;
316 
317     if (NULL_PTR != Config)
318     {
319         Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
320 
321         /* Disable output dividers */
322         for (DividerIndex = 0U; DividerIndex < Clock_Ip_apxPll[Instance].DivsNo; DividerIndex++)
323         {
324             Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLLDIG_PLLODIV_DE_MASK;
325         }
326 
327         /* Power down PLL */
328         Clock_Ip_apxPll[Instance].PllInstance->PLLCR |= PLLDIG_PLLCR_PLLPD_MASK;
329     }
330     else
331     {
332         (void)Instance;
333         (void)DividerIndex;
334     }
335 }
Clock_Ip_SetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const * Config)336 static void Clock_Ip_SetPlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* Config)
337 {
338     uint32 Instance;
339     uint32 Value;
340 
341     if (NULL_PTR != Config)
342     {
343         Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
344 
345         if (Config->Enable != 0U)
346         {
347             /* Name of the input reference clock */
348             switch (Config->InputReference)
349             {
350                 case FIRC_CLK:
351                     /* Select input reference. */
352                     Clock_Ip_apxPll[Instance].PllInstance->PLLCLKMUX = PLLDIG_PLLCLKMUX_REFCLKSEL(CLOCK_IP_FIRC_PLL_REFERENCE);
353                     break;
354                 case FXOSC_CLK:
355                     /* Select input reference. */
356                     Clock_Ip_apxPll[Instance].PllInstance->PLLCLKMUX = PLLDIG_PLLCLKMUX_REFCLKSEL(CLOCK_IP_FXOSC_PLL_REFERENCE);
357                     break;
358                 default:
359                     /* Command is not implemented on this platform */
360                     break;
361             }
362 
363             /* Configure PLL: predivider and multiplier */
364             Value = Clock_Ip_apxPll[Instance].PllInstance->PLLDV;
365             Value &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK);
366             Value |= (uint32) (PLLDIG_PLLDV_RDIV(Config->Predivider)   |
367                                 PLLDIG_PLLDV_MFI(Config->MulFactorDiv));
368             Clock_Ip_apxPll[Instance].PllInstance->PLLDV = Value;
369             /* Set numerator fractional loop divider and sigma delta modulation */
370             Value = Clock_Ip_apxPll[Instance].PllInstance->PLLFD;
371             Value &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK);
372             Value |=  PLLDIG_PLLFD_MFN(Config->NumeratorFracLoopDiv);
373             Value |= PLLDIG_PLLFD_SDMEN(Config->SigmaDelta);
374             Clock_Ip_apxPll[Instance].PllInstance->PLLFD = Value;
375         }
376     }
377     else
378     {
379         (void)Instance;
380         (void)Value;
381     }
382 }
Clock_Ip_CompletePlldigRdivMfiMfnSdmen(Clock_Ip_NameType PllName)383 static Clock_Ip_PllStatusReturnType Clock_Ip_CompletePlldigRdivMfiMfnSdmen(Clock_Ip_NameType PllName)
384 {
385     Clock_Ip_PllStatusReturnType PllStatus = STATUS_PLL_LOCKED;
386     boolean TimeoutOccurred = FALSE;
387     uint32 StartTime;
388     uint32 ElapsedTime;
389     uint32 TimeoutTicks;
390     uint32 PllLockStatus;
391     uint32 Instance = Clock_Ip_au8ClockFeatures[PllName][CLOCK_IP_MODULE_INSTANCE];
392 
393     if (0U == (Clock_Ip_apxPll[Instance].PllInstance->PLLCR & PLLDIG_PLLCR_PLLPD_MASK))
394     {
395         Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_IP_TIMEOUT_VALUE_US);
396         /* Wait until this pll is locked */
397         do
398         {
399             PllLockStatus = ((Clock_Ip_apxPll[Instance].PllInstance->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT);
400             TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
401         }
402         while ((0U == PllLockStatus) && (FALSE == TimeoutOccurred));
403 
404         if (TRUE == TimeoutOccurred)
405         {
406             PllStatus = STATUS_PLL_UNLOCKED;
407             /* Report timeout error */
408             Clock_Ip_ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, PllName);
409         }
410     }
411     else
412     {
413         PllStatus = STATUS_PLL_NOT_ENABLED;
414     }
415     return PllStatus;
416 }
Clock_Ip_EnablePlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const * Config)417 static void Clock_Ip_EnablePlldigRdivMfiMfnSdmen(Clock_Ip_PllConfigType const* Config)
418 {
419     uint32 Instance;
420 
421     if (NULL_PTR != Config)
422     {
423         Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
424 
425         /* Configure PLL. */
426         if (1U == Config->Enable)
427         {
428             /* Send command to enable PLL device. */
429             Clock_Ip_apxPll[Instance].PllInstance->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK;
430         }
431     }
432     else
433     {
434         (void)Instance;
435     }
436 }
437 #endif
438 
439 /*==================================================================================================
440 *                                        GLOBAL FUNCTIONS
441 ==================================================================================================*/
442 
443 
444 
445 
446 #ifdef CLOCK_IP_LFASTPLL_ENABLE
447 #ifdef ERR_IPV_LFAST_PLL_051380
448 #define CLOCK_IP_LFASTPLL_PLLCR_RESERVED_RWBIT_MASK    (0xE0000000U)
449 #endif
Clock_Ip_ResetLfastPLL(Clock_Ip_PllConfigType const * Config)450 static void Clock_Ip_ResetLfastPLL(Clock_Ip_PllConfigType const* Config)
451 {
452     uint32 Instance;
453 #ifdef ERR_IPV_LFAST_PLL_051380
454     uint32 RegValue;
455 #endif
456     if (NULL_PTR != Config)
457     {
458         Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
459 
460     #ifndef ERR_IPV_LFAST_PLL_051380
461         /* Power down PLL */
462         Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR |= LFAST_PLLCR_SWPOFF(1);
463         /* Accept write register LFAST */
464         Clock_Ip_apxLfastPll[Instance].PllInstance->MCR &= (~((uint32)LFAST_MCR_DRFEN_MASK));
465         /* Clear FBDIV bit field */
466         Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= (~((uint32)LFAST_PLLCR_FBDIV_MASK));
467         /* Clear PREDIV bit field */
468         Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= (~((uint32)LFAST_PLLCR_PREDIV_MASK));
469         /* Clear FDIVEN bit field */
470         Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= (~((uint32)LFAST_PLLCR_FDIVEN_MASK));
471     #else
472         RegValue = Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR;
473         RegValue &= ~(CLOCK_IP_LFASTPLL_PLLCR_RESERVED_RWBIT_MASK);
474         RegValue |= 0xC0000000U;
475 
476         RegValue &= (~((uint32)LFAST_PLLCR_FBDIV_MASK));
477         RegValue |= LFAST_PLLCR_FBDIV((uint8)(Config->MulFactorDiv));
478 
479         RegValue &= (~((uint32)LFAST_PLLCR_PREDIV_MASK));
480         RegValue |= LFAST_PLLCR_PREDIV((uint8)(Config->Predivider - 1U));
481 
482         RegValue &= (~((uint32)LFAST_PLLCR_FDIVEN_MASK));
483 
484         RegValue &= (~((uint32)LFAST_PLLCR_LPCFG_MASK));
485         if (Config->MulFactorDiv <= 21U)
486         {
487             RegValue |= LFAST_PLLCR_LPCFG(3U);
488         }
489         else if (Config->MulFactorDiv >= 28U)
490         {
491             RegValue |= LFAST_PLLCR_LPCFG(1U);
492         }
493         else
494         {
495             /* Do nothing */
496         }
497 
498         /* Accept write register LFAST */
499         Clock_Ip_apxLfastPll[Instance].PllInstance->MCR &= (~((uint32)LFAST_MCR_DRFEN_MASK));
500 
501         /* 1. Discharge the charge pump by switching the PLL to the closed loop mode */
502         Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR = RegValue;
503 
504         /* 2. Turn off the PLL */
505         Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR |= LFAST_PLLCR_SWPOFF(1);
506 
507     #endif /* ERR_IPV_LFAST_PLL_051380 */
508     }
509     else
510     {
511         (void)Instance;
512     }
513 }
Clock_Ip_SetLfastPLL(Clock_Ip_PllConfigType const * Config)514 static void Clock_Ip_SetLfastPLL(Clock_Ip_PllConfigType const* Config)
515 {
516     uint32 Instance;
517 #ifdef ERR_IPV_LFAST_PLL_051380
518     uint32 RegValue;
519     boolean TimeoutOccurred = FALSE;
520     uint32 StartTime;
521     uint32 ElapsedTime;
522     uint32 TimeoutTicks;
523 #endif
524 
525     if (NULL_PTR != Config)
526     {
527         Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
528 
529         /* Configure LFAST PLL. */
530         if (1U == Config->Enable)
531         {
532             /* Accept write register LFAST */
533             Clock_Ip_apxLfastPll[Instance].PllInstance->MCR &= (~((uint32)LFAST_MCR_DRFEN_MASK));
534         #ifndef ERR_IPV_LFAST_PLL_051380
535             Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= (~((uint32)LFAST_PLLCR_FBDIV_MASK));
536             Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR |= LFAST_PLLCR_FBDIV((uint8)(Config->MulFactorDiv));
537 
538             Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= (~((uint32)LFAST_PLLCR_PREDIV_MASK));
539             Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR |= LFAST_PLLCR_PREDIV((uint8)(Config->Predivider - 1U));
540 
541             Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= (~((uint32)LFAST_PLLCR_FDIVEN_MASK));
542             Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR |= LFAST_PLLCR_FDIVEN(Config->SigmaDelta);
543         #else
544             /* 3. Turn on the PLL  */
545             Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR |= LFAST_PLLCR_SWPON(1);
546 
547             /* 4. Wait for 10us */
548             Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, 10U);
549             do
550             {
551                 TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
552             }
553             while (FALSE == TimeoutOccurred);
554 
555             /* 5. Enable VCO control voltage pumping */
556             RegValue = Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR;
557             RegValue &= ~(CLOCK_IP_LFASTPLL_PLLCR_RESERVED_RWBIT_MASK);
558             RegValue |= 0xE0000000U;
559             Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR = RegValue;
560 
561             /* 6. Wait for 10us */
562             Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, 10U);
563             do
564             {
565                 TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
566             }
567             while (FALSE == TimeoutOccurred);
568         #endif
569         }
570         else
571         {
572             (void)Instance;
573         }
574     }
575     else
576     {
577         (void)Instance;
578     }
579 }
Clock_Ip_CompleteLfastPLL(Clock_Ip_NameType PllName)580 static Clock_Ip_PllStatusReturnType Clock_Ip_CompleteLfastPLL(Clock_Ip_NameType PllName)
581 {
582     Clock_Ip_PllStatusReturnType PllStatus = STATUS_PLL_LOCKED;
583     boolean TimeoutOccurred = FALSE;
584     uint32 StartTime;
585     uint32 ElapsedTime;
586     uint32 TimeoutTicks;
587     uint32 PllLockStatus;
588     uint32 PllEnableStatus;
589     uint32 Instance = Clock_Ip_au8ClockFeatures[PllName][CLOCK_IP_MODULE_INSTANCE];
590     if (1U == ((Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR & LFAST_PLLCR_SWPON_MASK) >> LFAST_PLLCR_SWPON_SHIFT))
591     {
592         Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_IP_TIMEOUT_VALUE_US);
593         /* Wait until this pll is enable */
594         do
595         {
596             PllEnableStatus = ((Clock_Ip_apxLfastPll[Instance].PllInstance->PLLLSR & LFAST_PLLLSR_PLLDIS_MASK) >> LFAST_PLLLSR_PLLDIS_SHIFT);
597             TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
598         }
599         while ((0U != PllEnableStatus) && (FALSE == TimeoutOccurred));
600 
601         if (TRUE == TimeoutOccurred)
602         {
603             PllStatus = STATUS_PLL_NOT_ENABLED;
604             /* Report timeout error */
605             Clock_Ip_ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, PllName);
606         }
607         else
608         {
609             Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_IP_TIMEOUT_VALUE_US);
610             /* Wait until this pll is locked */
611             do
612             {
613                 PllLockStatus = ((Clock_Ip_apxLfastPll[Instance].PllInstance->PLLLSR & LFAST_PLLLSR_PLDCR_MASK) >> LFAST_PLLLSR_PLDCR_SHIFT);
614                 TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
615             }
616             while ((1U != PllLockStatus) && (FALSE == TimeoutOccurred));
617 
618             if (TRUE == TimeoutOccurred)
619             {
620                 PllStatus = STATUS_PLL_UNLOCKED;
621                 /* Report timeout error */
622                 Clock_Ip_ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, PllName);
623             }
624         }
625     }
626     else
627     {
628         PllStatus = STATUS_PLL_NOT_ENABLED;
629     }
630 
631     return PllStatus;
632 }
Clock_Ip_EnableLfastPLL(Clock_Ip_PllConfigType const * Config)633 static void Clock_Ip_EnableLfastPLL(Clock_Ip_PllConfigType const* Config)
634 {
635     uint32 Instance;
636 
637     if (NULL_PTR != Config)
638     {
639         Instance = Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_MODULE_INSTANCE];
640 
641         /* Configure LFAST PLL. */
642         if (1U == Config->Enable)
643         {
644         #ifndef ERR_IPV_LFAST_PLL_051380
645             /* Enable LFAST PLL */
646             Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR |= LFAST_PLLCR_SWPON(1);
647         #else
648             /* 7. Switch to the functional mode */
649             Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= ~(CLOCK_IP_LFASTPLL_PLLCR_RESERVED_RWBIT_MASK);
650 
651             /* 8. Set PLLCR[LPCFG] = 00b */
652             Clock_Ip_apxLfastPll[Instance].PllInstance->PLLCR &= ~(LFAST_PLLCR_LPCFG_MASK);
653         #endif /* ERR_IPV_LFAST_PLL_051380 */
654         }
655         else
656         {
657             (void)Instance;
658         }
659     }
660     else
661     {
662         (void)Instance;
663     }
664 }
665 #endif
666 
667 
668 
669 
670 /* Clock stop section code */
671 #define MCU_STOP_SEC_CODE
672 
673 #include "Mcu_MemMap.h"
674 
675 /*==================================================================================================
676 *                                        GLOBAL CONSTANTS
677 ==================================================================================================*/
678 /* Clock start constant section data */
679 #define MCU_START_SEC_CONST_UNSPECIFIED
680 
681 #include "Mcu_MemMap.h"
682 const Clock_Ip_PllCallbackType Clock_Ip_axPllCallbacks[CLOCK_IP_PLL_CALLBACKS_COUNT] =
683 {
684     {
685         Clock_Ip_CallbackPllEmpty,            /* Reset */
686         Clock_Ip_CallbackPllEmpty,            /* Set */
687         Clock_Ip_CallbackPllEmptyComplete,    /* Complete */
688         Clock_Ip_CallbackPllEmpty,            /* Enable */
689         Clock_Ip_CallbackPllEmptyDisable,     /* Disable */
690     },
691     /* Pll with frequency modulation */
692 #ifdef CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN_SSCGBYP_SPREADCTL_STEPNO_STEPSIZE
693     {
694         Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize,              /* Reset */
695         Clock_Ip_SetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize,                /* Set */
696         Clock_Ip_CompletePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize,           /* Complete */
697         Clock_Ip_EnablePlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize,             /* Enable */
698         Clock_Ip_CallbackPllEmptyDisable,                                               /* Disable */
699     },
700 #endif
701     /* Pll without frequency modulation */
702 #ifdef CLOCK_IP_PLLDIG_RDIV_MFI_MFN_SDMEN
703     {
704         Clock_Ip_ResetPlldigRdivMfiMfnSdmen,          /* Reset */
705         Clock_Ip_SetPlldigRdivMfiMfnSdmen,            /* Set */
706         Clock_Ip_CompletePlldigRdivMfiMfnSdmen,       /* Complete */
707         Clock_Ip_EnablePlldigRdivMfiMfnSdmen,         /* Enable */
708         Clock_Ip_CallbackPllEmptyDisable,            /* Disable */
709     },
710 #endif
711 #ifdef CLOCK_IP_LFASTPLL_ENABLE
712     {
713         Clock_Ip_ResetLfastPLL,                                      /* Reset */
714         Clock_Ip_SetLfastPLL,                                        /* Set */
715         Clock_Ip_CompleteLfastPLL,                                   /* Complete */
716         Clock_Ip_EnableLfastPLL,                                     /* Enable */
717         Clock_Ip_CallbackPllEmptyDisable,                            /* Disable */
718     },
719 #endif
720 };
721 
722 
723 /* Clock stop constant section data */
724 #define MCU_STOP_SEC_CONST_UNSPECIFIED
725 
726 #include "Mcu_MemMap.h"
727 
728 #ifdef __cplusplus
729 }
730 #endif
731 
732 /** @} */
733 
734