1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_EIM.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_EIM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_EIM_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_EIM_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- EIM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** EIM - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ 74 __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ 75 uint8_t RESERVED_0[248]; 76 __IO uint32_t EICHD0_WORD0; /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100, not available in all instances (available on 3 out of 8) */ 77 __IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104, not available in all instances (available on 7 out of 8) */ 78 __IO uint32_t EICHD0_WORD2; /**< Error Injection Channel Descriptor 0, Word2, offset: 0x108, not available in all instances (available on 7 out of 8) */ 79 __IO uint32_t EICHD0_WORD3; /**< Error Injection Channel Descriptor 0, Word3, offset: 0x10C, not available in all instances (available on 1 out of 8) */ 80 uint8_t RESERVED_1[48]; 81 __IO uint32_t EICHD1_WORD0; /**< Error Injection Channel Descriptor 1, Word0, offset: 0x140, not available in all instances (available on 2 out of 8) */ 82 __IO uint32_t EICHD1_WORD1; /**< Error Injection Channel Descriptor 1, Word1, offset: 0x144, not available in all instances (available on 6 out of 8) */ 83 __IO uint32_t EICHD1_WORD2; /**< Error Injection Channel Descriptor 1, Word2, offset: 0x148, not available in all instances (available on 5 out of 8) */ 84 __IO uint32_t EICHD1_WORD3; /**< Error Injection Channel Descriptor 1, Word3, offset: 0x14C, not available in all instances (available on 1 out of 8) */ 85 __IO uint32_t EICHD1_WORD4; /**< Error Injection Channel Descriptor 1, Word4, offset: 0x150, not available in all instances (available on 1 out of 8) */ 86 __IO uint32_t EICHD1_WORD5; /**< Error Injection Channel Descriptor 1, Word5, offset: 0x154, not available in all instances (available on 1 out of 8) */ 87 __IO uint32_t EICHD1_WORD6; /**< Error Injection Channel Descriptor 1, Word6, offset: 0x158, not available in all instances (available on 1 out of 8) */ 88 __IO uint32_t EICHD1_WORD7; /**< Error Injection Channel Descriptor 1, Word7, offset: 0x15C, not available in all instances (available on 1 out of 8) */ 89 __IO uint32_t EICHD1_WORD8; /**< Error Injection Channel Descriptor 1, Word8, offset: 0x160, not available in all instances (available on 1 out of 8) */ 90 uint8_t RESERVED_2[28]; 91 __IO uint32_t EICHD2_WORD0; /**< Error Injection Channel Descriptor 2, Word0, offset: 0x180, not available in all instances (available on 3 out of 8) */ 92 __IO uint32_t EICHD2_WORD1; /**< Error Injection Channel Descriptor 2, Word1, offset: 0x184, not available in all instances (available on 6 out of 8) */ 93 __IO uint32_t EICHD2_WORD2; /**< Error Injection Channel Descriptor 2, Word2, offset: 0x188, not available in all instances (available on 3 out of 8) */ 94 uint8_t RESERVED_3[52]; 95 __IO uint32_t EICHD3_WORD0; /**< Error Injection Channel Descriptor 3, Word0, offset: 0x1C0, not available in all instances (available on 3 out of 8) */ 96 __IO uint32_t EICHD3_WORD1; /**< Error Injection Channel Descriptor 3, Word1, offset: 0x1C4, not available in all instances (available on 6 out of 8) */ 97 __IO uint32_t EICHD3_WORD2; /**< Error Injection Channel Descriptor 3, Word2, offset: 0x1C8, not available in all instances (available on 3 out of 8) */ 98 uint8_t RESERVED_4[52]; 99 __IO uint32_t EICHD4_WORD0; /**< Error Injection Channel Descriptor 4, Word0, offset: 0x200, not available in all instances (available on 1 out of 8) */ 100 __IO uint32_t EICHD4_WORD1; /**< Error Injection Channel Descriptor 4, Word1, offset: 0x204, not available in all instances (available on 3 out of 8) */ 101 __IO uint32_t EICHD4_WORD2; /**< Error Injection Channel Descriptor 4, Word2, offset: 0x208, not available in all instances (available on 1 out of 8) */ 102 uint8_t RESERVED_5[52]; 103 __IO uint32_t EICHD5_WORD0; /**< Error Injection Channel Descriptor 5, Word0, offset: 0x240, not available in all instances (available on 1 out of 8) */ 104 __IO uint32_t EICHD5_WORD1; /**< Error Injection Channel Descriptor 5, Word1, offset: 0x244, not available in all instances (available on 1 out of 8) */ 105 __IO uint32_t EICHD5_WORD2; /**< Error Injection Channel Descriptor 5, Word2, offset: 0x248, not available in all instances (available on 1 out of 8) */ 106 uint8_t RESERVED_6[52]; 107 __IO uint32_t EICHD6_WORD0; /**< Error Injection Channel Descriptor 6, Word0, offset: 0x280, not available in all instances (available on 1 out of 8) */ 108 __IO uint32_t EICHD6_WORD1; /**< Error Injection Channel Descriptor 6, Word1, offset: 0x284, not available in all instances (available on 1 out of 8) */ 109 __IO uint32_t EICHD6_WORD2; /**< Error Injection Channel Descriptor 6, Word2, offset: 0x288, not available in all instances (available on 1 out of 8) */ 110 uint8_t RESERVED_7[52]; 111 __IO uint32_t EICHD7_WORD0; /**< Error Injection Channel Descriptor 7, Word0, offset: 0x2C0, not available in all instances (available on 4 out of 8) */ 112 __IO uint32_t EICHD7_WORD1; /**< Error Injection Channel Descriptor 7, Word1, offset: 0x2C4, not available in all instances (available on 4 out of 8) */ 113 __IO uint32_t EICHD7_WORD2; /**< Error Injection Channel Descriptor 7, Word2, offset: 0x2C8, not available in all instances (available on 4 out of 8) */ 114 uint8_t RESERVED_8[52]; 115 __IO uint32_t EICHD8_WORD0; /**< Error Injection Channel Descriptor 8, Word0, offset: 0x300, not available in all instances (available on 3 out of 8) */ 116 __IO uint32_t EICHD8_WORD1; /**< Error Injection Channel Descriptor 8, Word1, offset: 0x304, not available in all instances (available on 4 out of 8) */ 117 __IO uint32_t EICHD8_WORD2; /**< Error Injection Channel Descriptor 8, Word2, offset: 0x308, not available in all instances (available on 4 out of 8) */ 118 __IO uint32_t EICHD8_WORD3; /**< Error Injection Channel Descriptor 8, Word3, offset: 0x30C, not available in all instances (available on 4 out of 8) */ 119 __IO uint32_t EICHD8_WORD4; /**< Error Injection Channel Descriptor 8, Word4, offset: 0x310, not available in all instances (available on 4 out of 8) */ 120 __IO uint32_t EICHD8_WORD5; /**< Error Injection Channel Descriptor 8, Word5, offset: 0x314, not available in all instances (available on 1 out of 8) */ 121 __IO uint32_t EICHD8_WORD6; /**< Error Injection Channel Descriptor 8, Word6, offset: 0x318, not available in all instances (available on 1 out of 8) */ 122 __IO uint32_t EICHD8_WORD7; /**< Error Injection Channel Descriptor 8, Word7, offset: 0x31C, not available in all instances (available on 1 out of 8) */ 123 __IO uint32_t EICHD8_WORD8; /**< Error Injection Channel Descriptor 8, Word8, offset: 0x320, not available in all instances (available on 1 out of 8) */ 124 uint8_t RESERVED_9[28]; 125 __IO uint32_t EICHD9_WORD0; /**< Error Injection Channel Descriptor 9, Word0, offset: 0x340, not available in all instances (available on 3 out of 8) */ 126 __IO uint32_t EICHD9_WORD1; /**< Error Injection Channel Descriptor 9, Word1, offset: 0x344, not available in all instances (available on 4 out of 8) */ 127 __IO uint32_t EICHD9_WORD2; /**< Error Injection Channel Descriptor 9, Word2, offset: 0x348, not available in all instances (available on 4 out of 8) */ 128 __IO uint32_t EICHD9_WORD3; /**< Error Injection Channel Descriptor 9, Word3, offset: 0x34C, not available in all instances (available on 1 out of 8) */ 129 __IO uint32_t EICHD9_WORD4; /**< Error Injection Channel Descriptor 9, Word4, offset: 0x350, not available in all instances (available on 1 out of 8) */ 130 __IO uint32_t EICHD9_WORD5; /**< Error Injection Channel Descriptor 9, Word5, offset: 0x354, not available in all instances (available on 1 out of 8) */ 131 __IO uint32_t EICHD9_WORD6; /**< Error Injection Channel Descriptor 9, Word6, offset: 0x358, not available in all instances (available on 1 out of 8) */ 132 __IO uint32_t EICHD9_WORD7; /**< Error Injection Channel Descriptor 9, Word7, offset: 0x35C, not available in all instances (available on 1 out of 8) */ 133 __IO uint32_t EICHD9_WORD8; /**< Error Injection Channel Descriptor 9, Word8, offset: 0x360, not available in all instances (available on 1 out of 8) */ 134 uint8_t RESERVED_10[28]; 135 __IO uint32_t EICHD10_WORD0; /**< Error Injection Channel Descriptor 10, Word0, offset: 0x380, not available in all instances (available on 3 out of 8) */ 136 __IO uint32_t EICHD10_WORD1; /**< Error Injection Channel Descriptor 10, Word1, offset: 0x384, not available in all instances (available on 4 out of 8) */ 137 __IO uint32_t EICHD10_WORD2; /**< Error Injection Channel Descriptor 10, Word2, offset: 0x388, not available in all instances (available on 4 out of 8) */ 138 __IO uint32_t EICHD10_WORD3; /**< Error Injection Channel Descriptor 10, Word3, offset: 0x38C, not available in all instances (available on 4 out of 8) */ 139 __IO uint32_t EICHD10_WORD4; /**< Error Injection Channel Descriptor 10, Word4, offset: 0x390, not available in all instances (available on 3 out of 8) */ 140 uint8_t RESERVED_11[44]; 141 __IO uint32_t EICHD11_WORD0; /**< Error Injection Channel Descriptor 11, Word0, offset: 0x3C0, not available in all instances (available on 3 out of 8) */ 142 __IO uint32_t EICHD11_WORD1; /**< Error Injection Channel Descriptor 11, Word1, offset: 0x3C4, not available in all instances (available on 4 out of 8) */ 143 __IO uint32_t EICHD11_WORD2; /**< Error Injection Channel Descriptor 11, Word2, offset: 0x3C8, not available in all instances (available on 3 out of 8) */ 144 uint8_t RESERVED_12[52]; 145 __IO uint32_t EICHD12_WORD0; /**< Error Injection Channel Descriptor 12, Word0, offset: 0x400, not available in all instances (available on 3 out of 8) */ 146 __IO uint32_t EICHD12_WORD1; /**< Error Injection Channel Descriptor 12, Word1, offset: 0x404, not available in all instances (available on 4 out of 8) */ 147 __IO uint32_t EICHD12_WORD2; /**< Error Injection Channel Descriptor 12, Word2, offset: 0x408, not available in all instances (available on 3 out of 8) */ 148 uint8_t RESERVED_13[52]; 149 __IO uint32_t EICHD13_WORD0; /**< Error Injection Channel Descriptor 13, Word0, offset: 0x440, not available in all instances (available on 3 out of 8) */ 150 __IO uint32_t EICHD13_WORD1; /**< Error Injection Channel Descriptor 13, Word1, offset: 0x444, not available in all instances (available on 3 out of 8) */ 151 __IO uint32_t EICHD13_WORD2; /**< Error Injection Channel Descriptor 13, Word2, offset: 0x448, not available in all instances (available on 3 out of 8) */ 152 uint8_t RESERVED_14[52]; 153 __IO uint32_t EICHD14_WORD0; /**< Error Injection Channel Descriptor 14, Word0, offset: 0x480, not available in all instances (available on 3 out of 8) */ 154 __IO uint32_t EICHD14_WORD1; /**< Error Injection Channel Descriptor 14, Word1, offset: 0x484, not available in all instances (available on 3 out of 8) */ 155 __IO uint32_t EICHD14_WORD2; /**< Error Injection Channel Descriptor 14, Word2, offset: 0x488, not available in all instances (available on 3 out of 8) */ 156 uint8_t RESERVED_15[52]; 157 __IO uint32_t EICHD15_WORD0; /**< Error Injection Channel Descriptor 15, Word0, offset: 0x4C0, not available in all instances (available on 3 out of 8) */ 158 __IO uint32_t EICHD15_WORD1; /**< Error Injection Channel Descriptor 15, Word1, offset: 0x4C4, not available in all instances (available on 3 out of 8) */ 159 __IO uint32_t EICHD15_WORD2; /**< Error Injection Channel Descriptor 15, Word2, offset: 0x4C8, not available in all instances (available on 3 out of 8) */ 160 uint8_t RESERVED_16[52]; 161 __IO uint32_t EICHD16_WORD0; /**< Error Injection Channel Descriptor 16, Word0, offset: 0x500, not available in all instances (available on 3 out of 8) */ 162 __IO uint32_t EICHD16_WORD1; /**< Error Injection Channel Descriptor 16, Word1, offset: 0x504, not available in all instances (available on 4 out of 8) */ 163 __IO uint32_t EICHD16_WORD2; /**< Error Injection Channel Descriptor 16, Word2, offset: 0x508, not available in all instances (available on 3 out of 8) */ 164 uint8_t RESERVED_17[52]; 165 __IO uint32_t EICHD17_WORD0; /**< Error Injection Channel Descriptor 17, Word0, offset: 0x540, not available in all instances (available on 2 out of 8) */ 166 __IO uint32_t EICHD17_WORD1; /**< Error Injection Channel Descriptor 17, Word1, offset: 0x544, not available in all instances (available on 3 out of 8) */ 167 __IO uint32_t EICHD17_WORD2; /**< Error Injection Channel Descriptor 17, Word2, offset: 0x548, not available in all instances (available on 2 out of 8) */ 168 uint8_t RESERVED_18[56]; 169 __IO uint32_t EICHD18_WORD1; /**< Error Injection Channel Descriptor 18, Word1, offset: 0x584, not available in all instances (available on 4 out of 8) */ 170 __IO uint32_t EICHD18_WORD2; /**< Error Injection Channel Descriptor 18, Word2, offset: 0x588, not available in all instances (available on 3 out of 8) */ 171 uint8_t RESERVED_19[52]; 172 __IO uint32_t EICHD19_WORD0; /**< Error Injection Channel Descriptor 19, Word0, offset: 0x5C0, not available in all instances (available on 1 out of 8) */ 173 __IO uint32_t EICHD19_WORD1; /**< Error Injection Channel Descriptor 19, Word1, offset: 0x5C4, not available in all instances (available on 4 out of 8) */ 174 __IO uint32_t EICHD19_WORD2; /**< Error Injection Channel Descriptor 19, Word2, offset: 0x5C8, not available in all instances (available on 4 out of 8) */ 175 uint8_t RESERVED_20[52]; 176 __IO uint32_t EICHD20_WORD0; /**< Error Injection Channel Descriptor 20, Word0, offset: 0x600, not available in all instances (available on 1 out of 8) */ 177 __IO uint32_t EICHD20_WORD1; /**< Error Injection Channel Descriptor 20, Word1, offset: 0x604, not available in all instances (available on 3 out of 8) */ 178 __IO uint32_t EICHD20_WORD2; /**< Error Injection Channel Descriptor 20, Word2, offset: 0x608, not available in all instances (available on 3 out of 8) */ 179 uint8_t RESERVED_21[52]; 180 __IO uint32_t EICHD21_WORD0; /**< Error Injection Channel Descriptor 21, Word0, offset: 0x640, not available in all instances (available on 1 out of 8) */ 181 __IO uint32_t EICHD21_WORD1; /**< Error Injection Channel Descriptor 21, Word1, offset: 0x644, not available in all instances (available on 3 out of 8) */ 182 __IO uint32_t EICHD21_WORD2; /**< Error Injection Channel Descriptor 21, Word2, offset: 0x648, not available in all instances (available on 3 out of 8) */ 183 uint8_t RESERVED_22[52]; 184 __IO uint32_t EICHD22_WORD0; /**< Error Injection Channel Descriptor 22, Word0, offset: 0x680, not available in all instances (available on 1 out of 8) */ 185 __IO uint32_t EICHD22_WORD1; /**< Error Injection Channel Descriptor 22, Word1, offset: 0x684, not available in all instances (available on 3 out of 8) */ 186 __IO uint32_t EICHD22_WORD2; /**< Error Injection Channel Descriptor 22, Word2, offset: 0x688, not available in all instances (available on 1 out of 8) */ 187 uint8_t RESERVED_23[56]; 188 __IO uint32_t EICHD23_WORD1; /**< Error Injection Channel Descriptor 23, Word1, offset: 0x6C4, not available in all instances (available on 3 out of 8) */ 189 uint8_t RESERVED_24[60]; 190 __IO uint32_t EICHD24_WORD1; /**< Error Injection Channel Descriptor 24, Word1, offset: 0x704, not available in all instances (available on 4 out of 8) */ 191 uint8_t RESERVED_25[60]; 192 __IO uint32_t EICHD25_WORD1; /**< Error Injection Channel Descriptor 25, Word1, offset: 0x744, not available in all instances (available on 1 out of 8) */ 193 uint8_t RESERVED_26[56]; 194 __IO uint32_t EICHD26_WORD0; /**< Error Injection Channel Descriptor 26, Word0, offset: 0x780, not available in all instances (available on 2 out of 8) */ 195 __IO uint32_t EICHD26_WORD1; /**< Error Injection Channel Descriptor 26, Word1, offset: 0x784, not available in all instances (available on 3 out of 8) */ 196 __IO uint32_t EICHD26_WORD2; /**< Error Injection Channel Descriptor 26, Word2, offset: 0x788, not available in all instances (available on 2 out of 8) */ 197 uint8_t RESERVED_27[52]; 198 __IO uint32_t EICHD27_WORD0; /**< Error Injection Channel Descriptor 27, Word0, offset: 0x7C0, not available in all instances (available on 1 out of 8) */ 199 __IO uint32_t EICHD27_WORD1; /**< Error Injection Channel Descriptor 27, Word1, offset: 0x7C4, not available in all instances (available on 3 out of 8) */ 200 __IO uint32_t EICHD27_WORD2; /**< Error Injection Channel Descriptor 27, Word2, offset: 0x7C8, not available in all instances (available on 1 out of 8) */ 201 uint8_t RESERVED_28[52]; 202 __IO uint32_t EICHD28_WORD0; /**< Error Injection Channel Descriptor 28, Word0, offset: 0x800, not available in all instances (available on 1 out of 8) */ 203 __IO uint32_t EICHD28_WORD1; /**< Error Injection Channel Descriptor 28, Word1, offset: 0x804, not available in all instances (available on 1 out of 8) */ 204 __IO uint32_t EICHD28_WORD2; /**< Error Injection Channel Descriptor 28, Word2, offset: 0x808, not available in all instances (available on 1 out of 8) */ 205 uint8_t RESERVED_29[52]; 206 __IO uint32_t EICHD29_WORD0; /**< Error Injection Channel Descriptor 29, Word0, offset: 0x840, not available in all instances (available on 1 out of 8) */ 207 __IO uint32_t EICHD29_WORD1; /**< Error Injection Channel Descriptor 29, Word1, offset: 0x844, not available in all instances (available on 3 out of 8) */ 208 __IO uint32_t EICHD29_WORD2; /**< Error Injection Channel Descriptor 29, Word2, offset: 0x848, not available in all instances (available on 1 out of 8) */ 209 uint8_t RESERVED_30[52]; 210 __IO uint32_t EICHD30_WORD0; /**< Error Injection Channel Descriptor 30, Word0, offset: 0x880, not available in all instances (available on 1 out of 8) */ 211 __IO uint32_t EICHD30_WORD1; /**< Error Injection Channel Descriptor 30, Word1, offset: 0x884, not available in all instances (available on 3 out of 8) */ 212 __IO uint32_t EICHD30_WORD2; /**< Error Injection Channel Descriptor 30, Word2, offset: 0x888, not available in all instances (available on 3 out of 8) */ 213 uint8_t RESERVED_31[56]; 214 __IO uint32_t EICHD31_WORD1; /**< Error Injection Channel Descriptor 31, Word1, offset: 0x8C4, not available in all instances (available on 3 out of 8) */ 215 __IO uint32_t EICHD31_WORD2; /**< Error Injection Channel Descriptor 31, Word2, offset: 0x8C8, not available in all instances (available on 2 out of 8) */ 216 } EIM_Type, *EIM_MemMapPtr; 217 218 /** Number of instances of the EIM module. */ 219 #define EIM_INSTANCE_COUNT (8u) 220 221 /* EIM - Peripheral instance base addresses */ 222 /** Peripheral CE_EIM_0 base address */ 223 #define IP_CE_EIM_0_BASE (0x44814000u) 224 /** Peripheral CE_EIM_0 base pointer */ 225 #define IP_CE_EIM_0 ((EIM_Type *)IP_CE_EIM_0_BASE) 226 /** Peripheral CE_EIM_1 base address */ 227 #define IP_CE_EIM_1_BASE (0x4481C000u) 228 /** Peripheral CE_EIM_1 base pointer */ 229 #define IP_CE_EIM_1 ((EIM_Type *)IP_CE_EIM_1_BASE) 230 /** Peripheral EIM_1 base address */ 231 #define IP_EIM_1_BASE (0x40880000u) 232 /** Peripheral EIM_1 base pointer */ 233 #define IP_EIM_1 ((EIM_Type *)IP_EIM_1_BASE) 234 /** Peripheral EIM_2 base address */ 235 #define IP_EIM_2_BASE (0x41080000u) 236 /** Peripheral EIM_2 base pointer */ 237 #define IP_EIM_2 ((EIM_Type *)IP_EIM_2_BASE) 238 /** Peripheral EIM_3 base address */ 239 #define IP_EIM_3_BASE (0x41880000u) 240 /** Peripheral EIM_3 base pointer */ 241 #define IP_EIM_3 ((EIM_Type *)IP_EIM_3_BASE) 242 /** Peripheral RTU0__EIM base address */ 243 #define IP_RTU0__EIM_BASE (0x76180000u) 244 /** Peripheral RTU0__EIM base pointer */ 245 #define IP_RTU0__EIM ((EIM_Type *)IP_RTU0__EIM_BASE) 246 /** Peripheral RTU1__EIM base address */ 247 #define IP_RTU1__EIM_BASE (0x76980000u) 248 /** Peripheral RTU1__EIM base pointer */ 249 #define IP_RTU1__EIM ((EIM_Type *)IP_RTU1__EIM_BASE) 250 /** Peripheral SMU__EIM base address */ 251 #define IP_SMU__EIM_BASE (0x45014000u) 252 /** Peripheral SMU__EIM base pointer */ 253 #define IP_SMU__EIM ((EIM_Type *)IP_SMU__EIM_BASE) 254 /** Array initializer of EIM peripheral base addresses */ 255 #define IP_EIM_BASE_ADDRS { IP_CE_EIM_0_BASE, IP_CE_EIM_1_BASE, IP_EIM_1_BASE, IP_EIM_2_BASE, IP_EIM_3_BASE, IP_RTU0__EIM_BASE, IP_RTU1__EIM_BASE, IP_SMU__EIM_BASE } 256 /** Array initializer of EIM peripheral base pointers */ 257 #define IP_EIM_BASE_PTRS { IP_CE_EIM_0, IP_CE_EIM_1, IP_EIM_1, IP_EIM_2, IP_EIM_3, IP_RTU0__EIM, IP_RTU1__EIM, IP_SMU__EIM } 258 259 /* ---------------------------------------------------------------------------- 260 -- EIM Register Masks 261 ---------------------------------------------------------------------------- */ 262 263 /*! 264 * @addtogroup EIM_Register_Masks EIM Register Masks 265 * @{ 266 */ 267 268 /*! @name EIMCR - Error Injection Module Configuration Register */ 269 /*! @{ */ 270 271 #define EIM_EIMCR_GEIEN_MASK (0x1U) 272 #define EIM_EIMCR_GEIEN_SHIFT (0U) 273 #define EIM_EIMCR_GEIEN_WIDTH (1U) 274 #define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EIMCR_GEIEN_SHIFT)) & EIM_EIMCR_GEIEN_MASK) 275 /*! @} */ 276 277 /*! @name EICHEN - Error Injection Channel Enable register */ 278 /*! @{ */ 279 280 #define EIM_EICHEN_EICH31EN_MASK (0x1U) 281 #define EIM_EICHEN_EICH31EN_SHIFT (0U) 282 #define EIM_EICHEN_EICH31EN_WIDTH (1U) 283 #define EIM_EICHEN_EICH31EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH31EN_SHIFT)) & EIM_EICHEN_EICH31EN_MASK) 284 285 #define EIM_EICHEN_EICH30EN_MASK (0x2U) 286 #define EIM_EICHEN_EICH30EN_SHIFT (1U) 287 #define EIM_EICHEN_EICH30EN_WIDTH (1U) 288 #define EIM_EICHEN_EICH30EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH30EN_SHIFT)) & EIM_EICHEN_EICH30EN_MASK) 289 290 #define EIM_EICHEN_EICH29EN_MASK (0x4U) 291 #define EIM_EICHEN_EICH29EN_SHIFT (2U) 292 #define EIM_EICHEN_EICH29EN_WIDTH (1U) 293 #define EIM_EICHEN_EICH29EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH29EN_SHIFT)) & EIM_EICHEN_EICH29EN_MASK) 294 295 #define EIM_EICHEN_EICH28EN_MASK (0x8U) 296 #define EIM_EICHEN_EICH28EN_SHIFT (3U) 297 #define EIM_EICHEN_EICH28EN_WIDTH (1U) 298 #define EIM_EICHEN_EICH28EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH28EN_SHIFT)) & EIM_EICHEN_EICH28EN_MASK) 299 300 #define EIM_EICHEN_EICH27EN_MASK (0x10U) 301 #define EIM_EICHEN_EICH27EN_SHIFT (4U) 302 #define EIM_EICHEN_EICH27EN_WIDTH (1U) 303 #define EIM_EICHEN_EICH27EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH27EN_SHIFT)) & EIM_EICHEN_EICH27EN_MASK) 304 305 #define EIM_EICHEN_EICH26EN_MASK (0x20U) 306 #define EIM_EICHEN_EICH26EN_SHIFT (5U) 307 #define EIM_EICHEN_EICH26EN_WIDTH (1U) 308 #define EIM_EICHEN_EICH26EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH26EN_SHIFT)) & EIM_EICHEN_EICH26EN_MASK) 309 310 #define EIM_EICHEN_EICH25EN_MASK (0x40U) 311 #define EIM_EICHEN_EICH25EN_SHIFT (6U) 312 #define EIM_EICHEN_EICH25EN_WIDTH (1U) 313 #define EIM_EICHEN_EICH25EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH25EN_SHIFT)) & EIM_EICHEN_EICH25EN_MASK) 314 315 #define EIM_EICHEN_EICH24EN_MASK (0x80U) 316 #define EIM_EICHEN_EICH24EN_SHIFT (7U) 317 #define EIM_EICHEN_EICH24EN_WIDTH (1U) 318 #define EIM_EICHEN_EICH24EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH24EN_SHIFT)) & EIM_EICHEN_EICH24EN_MASK) 319 320 #define EIM_EICHEN_EICH23EN_MASK (0x100U) 321 #define EIM_EICHEN_EICH23EN_SHIFT (8U) 322 #define EIM_EICHEN_EICH23EN_WIDTH (1U) 323 #define EIM_EICHEN_EICH23EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH23EN_SHIFT)) & EIM_EICHEN_EICH23EN_MASK) 324 325 #define EIM_EICHEN_EICH22EN_MASK (0x200U) 326 #define EIM_EICHEN_EICH22EN_SHIFT (9U) 327 #define EIM_EICHEN_EICH22EN_WIDTH (1U) 328 #define EIM_EICHEN_EICH22EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH22EN_SHIFT)) & EIM_EICHEN_EICH22EN_MASK) 329 330 #define EIM_EICHEN_EICH21EN_MASK (0x400U) 331 #define EIM_EICHEN_EICH21EN_SHIFT (10U) 332 #define EIM_EICHEN_EICH21EN_WIDTH (1U) 333 #define EIM_EICHEN_EICH21EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH21EN_SHIFT)) & EIM_EICHEN_EICH21EN_MASK) 334 335 #define EIM_EICHEN_EICH20EN_MASK (0x800U) 336 #define EIM_EICHEN_EICH20EN_SHIFT (11U) 337 #define EIM_EICHEN_EICH20EN_WIDTH (1U) 338 #define EIM_EICHEN_EICH20EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH20EN_SHIFT)) & EIM_EICHEN_EICH20EN_MASK) 339 340 #define EIM_EICHEN_EICH19EN_MASK (0x1000U) 341 #define EIM_EICHEN_EICH19EN_SHIFT (12U) 342 #define EIM_EICHEN_EICH19EN_WIDTH (1U) 343 #define EIM_EICHEN_EICH19EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH19EN_SHIFT)) & EIM_EICHEN_EICH19EN_MASK) 344 345 #define EIM_EICHEN_EICH18EN_MASK (0x2000U) 346 #define EIM_EICHEN_EICH18EN_SHIFT (13U) 347 #define EIM_EICHEN_EICH18EN_WIDTH (1U) 348 #define EIM_EICHEN_EICH18EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH18EN_SHIFT)) & EIM_EICHEN_EICH18EN_MASK) 349 350 #define EIM_EICHEN_EICH17EN_MASK (0x4000U) 351 #define EIM_EICHEN_EICH17EN_SHIFT (14U) 352 #define EIM_EICHEN_EICH17EN_WIDTH (1U) 353 #define EIM_EICHEN_EICH17EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH17EN_SHIFT)) & EIM_EICHEN_EICH17EN_MASK) 354 355 #define EIM_EICHEN_EICH16EN_MASK (0x8000U) 356 #define EIM_EICHEN_EICH16EN_SHIFT (15U) 357 #define EIM_EICHEN_EICH16EN_WIDTH (1U) 358 #define EIM_EICHEN_EICH16EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH16EN_SHIFT)) & EIM_EICHEN_EICH16EN_MASK) 359 360 #define EIM_EICHEN_EICH15EN_MASK (0x10000U) 361 #define EIM_EICHEN_EICH15EN_SHIFT (16U) 362 #define EIM_EICHEN_EICH15EN_WIDTH (1U) 363 #define EIM_EICHEN_EICH15EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH15EN_SHIFT)) & EIM_EICHEN_EICH15EN_MASK) 364 365 #define EIM_EICHEN_EICH14EN_MASK (0x20000U) 366 #define EIM_EICHEN_EICH14EN_SHIFT (17U) 367 #define EIM_EICHEN_EICH14EN_WIDTH (1U) 368 #define EIM_EICHEN_EICH14EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH14EN_SHIFT)) & EIM_EICHEN_EICH14EN_MASK) 369 370 #define EIM_EICHEN_EICH13EN_MASK (0x40000U) 371 #define EIM_EICHEN_EICH13EN_SHIFT (18U) 372 #define EIM_EICHEN_EICH13EN_WIDTH (1U) 373 #define EIM_EICHEN_EICH13EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH13EN_SHIFT)) & EIM_EICHEN_EICH13EN_MASK) 374 375 #define EIM_EICHEN_EICH12EN_MASK (0x80000U) 376 #define EIM_EICHEN_EICH12EN_SHIFT (19U) 377 #define EIM_EICHEN_EICH12EN_WIDTH (1U) 378 #define EIM_EICHEN_EICH12EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH12EN_SHIFT)) & EIM_EICHEN_EICH12EN_MASK) 379 380 #define EIM_EICHEN_EICH11EN_MASK (0x100000U) 381 #define EIM_EICHEN_EICH11EN_SHIFT (20U) 382 #define EIM_EICHEN_EICH11EN_WIDTH (1U) 383 #define EIM_EICHEN_EICH11EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH11EN_SHIFT)) & EIM_EICHEN_EICH11EN_MASK) 384 385 #define EIM_EICHEN_EICH10EN_MASK (0x200000U) 386 #define EIM_EICHEN_EICH10EN_SHIFT (21U) 387 #define EIM_EICHEN_EICH10EN_WIDTH (1U) 388 #define EIM_EICHEN_EICH10EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH10EN_SHIFT)) & EIM_EICHEN_EICH10EN_MASK) 389 390 #define EIM_EICHEN_EICH9EN_MASK (0x400000U) 391 #define EIM_EICHEN_EICH9EN_SHIFT (22U) 392 #define EIM_EICHEN_EICH9EN_WIDTH (1U) 393 #define EIM_EICHEN_EICH9EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH9EN_SHIFT)) & EIM_EICHEN_EICH9EN_MASK) 394 395 #define EIM_EICHEN_EICH8EN_MASK (0x800000U) 396 #define EIM_EICHEN_EICH8EN_SHIFT (23U) 397 #define EIM_EICHEN_EICH8EN_WIDTH (1U) 398 #define EIM_EICHEN_EICH8EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH8EN_SHIFT)) & EIM_EICHEN_EICH8EN_MASK) 399 400 #define EIM_EICHEN_EICH7EN_MASK (0x1000000U) 401 #define EIM_EICHEN_EICH7EN_SHIFT (24U) 402 #define EIM_EICHEN_EICH7EN_WIDTH (1U) 403 #define EIM_EICHEN_EICH7EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH7EN_SHIFT)) & EIM_EICHEN_EICH7EN_MASK) 404 405 #define EIM_EICHEN_EICH6EN_MASK (0x2000000U) 406 #define EIM_EICHEN_EICH6EN_SHIFT (25U) 407 #define EIM_EICHEN_EICH6EN_WIDTH (1U) 408 #define EIM_EICHEN_EICH6EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH6EN_SHIFT)) & EIM_EICHEN_EICH6EN_MASK) 409 410 #define EIM_EICHEN_EICH5EN_MASK (0x4000000U) 411 #define EIM_EICHEN_EICH5EN_SHIFT (26U) 412 #define EIM_EICHEN_EICH5EN_WIDTH (1U) 413 #define EIM_EICHEN_EICH5EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH5EN_SHIFT)) & EIM_EICHEN_EICH5EN_MASK) 414 415 #define EIM_EICHEN_EICH4EN_MASK (0x8000000U) 416 #define EIM_EICHEN_EICH4EN_SHIFT (27U) 417 #define EIM_EICHEN_EICH4EN_WIDTH (1U) 418 #define EIM_EICHEN_EICH4EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH4EN_SHIFT)) & EIM_EICHEN_EICH4EN_MASK) 419 420 #define EIM_EICHEN_EICH3EN_MASK (0x10000000U) 421 #define EIM_EICHEN_EICH3EN_SHIFT (28U) 422 #define EIM_EICHEN_EICH3EN_WIDTH (1U) 423 #define EIM_EICHEN_EICH3EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH3EN_SHIFT)) & EIM_EICHEN_EICH3EN_MASK) 424 425 #define EIM_EICHEN_EICH2EN_MASK (0x20000000U) 426 #define EIM_EICHEN_EICH2EN_SHIFT (29U) 427 #define EIM_EICHEN_EICH2EN_WIDTH (1U) 428 #define EIM_EICHEN_EICH2EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH2EN_SHIFT)) & EIM_EICHEN_EICH2EN_MASK) 429 430 #define EIM_EICHEN_EICH1EN_MASK (0x40000000U) 431 #define EIM_EICHEN_EICH1EN_SHIFT (30U) 432 #define EIM_EICHEN_EICH1EN_WIDTH (1U) 433 #define EIM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH1EN_SHIFT)) & EIM_EICHEN_EICH1EN_MASK) 434 435 #define EIM_EICHEN_EICH0EN_MASK (0x80000000U) 436 #define EIM_EICHEN_EICH0EN_SHIFT (31U) 437 #define EIM_EICHEN_EICH0EN_WIDTH (1U) 438 #define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH0EN_SHIFT)) & EIM_EICHEN_EICH0EN_MASK) 439 /*! @} */ 440 441 /*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */ 442 /*! @{ */ 443 444 #define EIM_EICHD0_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 445 #define EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT (24U) 446 #define EIM_EICHD0_WORD0_CHKBIT_MASK_WIDTH (8U) 447 #define EIM_EICHD0_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) 448 /*! @} */ 449 450 /*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */ 451 /*! @{ */ 452 453 #define EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (12, 16, 19, 32), largest definition used */ 454 #define EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U) 455 #define EIM_EICHD0_WORD1_B0_3DATA_MASK_WIDTH (32U) 456 #define EIM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (12, 16, 19, 32), largest definition used */ 457 /*! @} */ 458 459 /*! @name EICHD0_WORD2 - Error Injection Channel Descriptor 0, Word2 */ 460 /*! @{ */ 461 462 #define EIM_EICHD0_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 463 #define EIM_EICHD0_WORD2_B4_7DATA_MASK_SHIFT (0U) 464 #define EIM_EICHD0_WORD2_B4_7DATA_MASK_WIDTH (32U) 465 #define EIM_EICHD0_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD0_WORD2_B4_7DATA_MASK_MASK) 466 /*! @} */ 467 468 /*! @name EICHD0_WORD3 - Error Injection Channel Descriptor 0, Word3 */ 469 /*! @{ */ 470 471 #define EIM_EICHD0_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) 472 #define EIM_EICHD0_WORD3_B8_11DATA_MASK_SHIFT (0U) 473 #define EIM_EICHD0_WORD3_B8_11DATA_MASK_WIDTH (32U) 474 #define EIM_EICHD0_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD0_WORD3_B8_11DATA_MASK_MASK) 475 /*! @} */ 476 477 /*! @name EICHD1_WORD0 - Error Injection Channel Descriptor 1, Word0 */ 478 /*! @{ */ 479 480 #define EIM_EICHD1_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 481 #define EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT (24U) 482 #define EIM_EICHD1_WORD0_CHKBIT_MASK_WIDTH (8U) 483 #define EIM_EICHD1_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) 484 /*! @} */ 485 486 /*! @name EICHD1_WORD1 - Error Injection Channel Descriptor 1, Word1 */ 487 /*! @{ */ 488 489 #define EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (1, 22, 32), largest definition used */ 490 #define EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT (0U) 491 #define EIM_EICHD1_WORD1_B0_3DATA_MASK_WIDTH (32U) 492 #define EIM_EICHD1_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (1, 22, 32), largest definition used */ 493 /*! @} */ 494 495 /*! @name EICHD1_WORD2 - Error Injection Channel Descriptor 1, Word2 */ 496 /*! @{ */ 497 498 #define EIM_EICHD1_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 499 #define EIM_EICHD1_WORD2_B4_7DATA_MASK_SHIFT (0U) 500 #define EIM_EICHD1_WORD2_B4_7DATA_MASK_WIDTH (32U) 501 #define EIM_EICHD1_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD1_WORD2_B4_7DATA_MASK_MASK) 502 /*! @} */ 503 504 /*! @name EICHD1_WORD3 - Error Injection Channel Descriptor 1, Word3 */ 505 /*! @{ */ 506 507 #define EIM_EICHD1_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) 508 #define EIM_EICHD1_WORD3_B8_11DATA_MASK_SHIFT (0U) 509 #define EIM_EICHD1_WORD3_B8_11DATA_MASK_WIDTH (32U) 510 #define EIM_EICHD1_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD1_WORD3_B8_11DATA_MASK_MASK) 511 /*! @} */ 512 513 /*! @name EICHD1_WORD4 - Error Injection Channel Descriptor 1, Word4 */ 514 /*! @{ */ 515 516 #define EIM_EICHD1_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) 517 #define EIM_EICHD1_WORD4_B12_15DATA_MASK_SHIFT (0U) 518 #define EIM_EICHD1_WORD4_B12_15DATA_MASK_WIDTH (32U) 519 #define EIM_EICHD1_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD1_WORD4_B12_15DATA_MASK_MASK) 520 /*! @} */ 521 522 /*! @name EICHD1_WORD5 - Error Injection Channel Descriptor 1, Word5 */ 523 /*! @{ */ 524 525 #define EIM_EICHD1_WORD5_B16_19DATA_MASK_MASK (0xFFFFFFFFU) 526 #define EIM_EICHD1_WORD5_B16_19DATA_MASK_SHIFT (0U) 527 #define EIM_EICHD1_WORD5_B16_19DATA_MASK_WIDTH (32U) 528 #define EIM_EICHD1_WORD5_B16_19DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD5_B16_19DATA_MASK_SHIFT)) & EIM_EICHD1_WORD5_B16_19DATA_MASK_MASK) 529 /*! @} */ 530 531 /*! @name EICHD1_WORD6 - Error Injection Channel Descriptor 1, Word6 */ 532 /*! @{ */ 533 534 #define EIM_EICHD1_WORD6_B20_23DATA_MASK_MASK (0xFFFFFFFFU) 535 #define EIM_EICHD1_WORD6_B20_23DATA_MASK_SHIFT (0U) 536 #define EIM_EICHD1_WORD6_B20_23DATA_MASK_WIDTH (32U) 537 #define EIM_EICHD1_WORD6_B20_23DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD6_B20_23DATA_MASK_SHIFT)) & EIM_EICHD1_WORD6_B20_23DATA_MASK_MASK) 538 /*! @} */ 539 540 /*! @name EICHD1_WORD7 - Error Injection Channel Descriptor 1, Word7 */ 541 /*! @{ */ 542 543 #define EIM_EICHD1_WORD7_B24_27DATA_MASK_MASK (0xFFFFFFFFU) 544 #define EIM_EICHD1_WORD7_B24_27DATA_MASK_SHIFT (0U) 545 #define EIM_EICHD1_WORD7_B24_27DATA_MASK_WIDTH (32U) 546 #define EIM_EICHD1_WORD7_B24_27DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD7_B24_27DATA_MASK_SHIFT)) & EIM_EICHD1_WORD7_B24_27DATA_MASK_MASK) 547 /*! @} */ 548 549 /*! @name EICHD1_WORD8 - Error Injection Channel Descriptor 1, Word8 */ 550 /*! @{ */ 551 552 #define EIM_EICHD1_WORD8_B28_31DATA_MASK_MASK (0xFFFFFFFFU) 553 #define EIM_EICHD1_WORD8_B28_31DATA_MASK_SHIFT (0U) 554 #define EIM_EICHD1_WORD8_B28_31DATA_MASK_WIDTH (32U) 555 #define EIM_EICHD1_WORD8_B28_31DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD8_B28_31DATA_MASK_SHIFT)) & EIM_EICHD1_WORD8_B28_31DATA_MASK_MASK) 556 /*! @} */ 557 558 /*! @name EICHD2_WORD0 - Error Injection Channel Descriptor 2, Word0 */ 559 /*! @{ */ 560 561 #define EIM_EICHD2_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 562 #define EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT (24U) 563 #define EIM_EICHD2_WORD0_CHKBIT_MASK_WIDTH (8U) 564 #define EIM_EICHD2_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) 565 /*! @} */ 566 567 /*! @name EICHD2_WORD1 - Error Injection Channel Descriptor 2, Word1 */ 568 /*! @{ */ 569 570 #define EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (1, 16, 32), largest definition used */ 571 #define EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT (0U) 572 #define EIM_EICHD2_WORD1_B0_3DATA_MASK_WIDTH (32U) 573 #define EIM_EICHD2_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (1, 16, 32), largest definition used */ 574 /*! @} */ 575 576 /*! @name EICHD2_WORD2 - Error Injection Channel Descriptor 2, Word2 */ 577 /*! @{ */ 578 579 #define EIM_EICHD2_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 580 #define EIM_EICHD2_WORD2_B4_7DATA_MASK_SHIFT (0U) 581 #define EIM_EICHD2_WORD2_B4_7DATA_MASK_WIDTH (32U) 582 #define EIM_EICHD2_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD2_WORD2_B4_7DATA_MASK_MASK) 583 /*! @} */ 584 585 /*! @name EICHD3_WORD0 - Error Injection Channel Descriptor 3, Word0 */ 586 /*! @{ */ 587 588 #define EIM_EICHD3_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 589 #define EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT (24U) 590 #define EIM_EICHD3_WORD0_CHKBIT_MASK_WIDTH (8U) 591 #define EIM_EICHD3_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) 592 /*! @} */ 593 594 /*! @name EICHD3_WORD1 - Error Injection Channel Descriptor 3, Word1 */ 595 /*! @{ */ 596 597 #define EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (5, 26, 32), largest definition used */ 598 #define EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT (0U) 599 #define EIM_EICHD3_WORD1_B0_3DATA_MASK_WIDTH (32U) 600 #define EIM_EICHD3_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (5, 26, 32), largest definition used */ 601 /*! @} */ 602 603 /*! @name EICHD3_WORD2 - Error Injection Channel Descriptor 3, Word2 */ 604 /*! @{ */ 605 606 #define EIM_EICHD3_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 607 #define EIM_EICHD3_WORD2_B4_7DATA_MASK_SHIFT (0U) 608 #define EIM_EICHD3_WORD2_B4_7DATA_MASK_WIDTH (32U) 609 #define EIM_EICHD3_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD3_WORD2_B4_7DATA_MASK_MASK) 610 /*! @} */ 611 612 /*! @name EICHD4_WORD0 - Error Injection Channel Descriptor 4, Word0 */ 613 /*! @{ */ 614 615 #define EIM_EICHD4_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 616 #define EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT (24U) 617 #define EIM_EICHD4_WORD0_CHKBIT_MASK_WIDTH (8U) 618 #define EIM_EICHD4_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) 619 /*! @} */ 620 621 /*! @name EICHD4_WORD1 - Error Injection Channel Descriptor 4, Word1 */ 622 /*! @{ */ 623 624 #define EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (23, 32), largest definition used */ 625 #define EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT (0U) 626 #define EIM_EICHD4_WORD1_B0_3DATA_MASK_WIDTH (32U) 627 #define EIM_EICHD4_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (23, 32), largest definition used */ 628 /*! @} */ 629 630 /*! @name EICHD4_WORD2 - Error Injection Channel Descriptor 4, Word2 */ 631 /*! @{ */ 632 633 #define EIM_EICHD4_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 634 #define EIM_EICHD4_WORD2_B4_7DATA_MASK_SHIFT (0U) 635 #define EIM_EICHD4_WORD2_B4_7DATA_MASK_WIDTH (32U) 636 #define EIM_EICHD4_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD4_WORD2_B4_7DATA_MASK_MASK) 637 /*! @} */ 638 639 /*! @name EICHD5_WORD0 - Error Injection Channel Descriptor 5, Word0 */ 640 /*! @{ */ 641 642 #define EIM_EICHD5_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 643 #define EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT (24U) 644 #define EIM_EICHD5_WORD0_CHKBIT_MASK_WIDTH (8U) 645 #define EIM_EICHD5_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) 646 /*! @} */ 647 648 /*! @name EICHD5_WORD1 - Error Injection Channel Descriptor 5, Word1 */ 649 /*! @{ */ 650 651 #define EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 652 #define EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT (0U) 653 #define EIM_EICHD5_WORD1_B0_3DATA_MASK_WIDTH (32U) 654 #define EIM_EICHD5_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) 655 /*! @} */ 656 657 /*! @name EICHD5_WORD2 - Error Injection Channel Descriptor 5, Word2 */ 658 /*! @{ */ 659 660 #define EIM_EICHD5_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 661 #define EIM_EICHD5_WORD2_B4_7DATA_MASK_SHIFT (0U) 662 #define EIM_EICHD5_WORD2_B4_7DATA_MASK_WIDTH (32U) 663 #define EIM_EICHD5_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD5_WORD2_B4_7DATA_MASK_MASK) 664 /*! @} */ 665 666 /*! @name EICHD6_WORD0 - Error Injection Channel Descriptor 6, Word0 */ 667 /*! @{ */ 668 669 #define EIM_EICHD6_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 670 #define EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT (24U) 671 #define EIM_EICHD6_WORD0_CHKBIT_MASK_WIDTH (8U) 672 #define EIM_EICHD6_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) 673 /*! @} */ 674 675 /*! @name EICHD6_WORD1 - Error Injection Channel Descriptor 6, Word1 */ 676 /*! @{ */ 677 678 #define EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 679 #define EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT (0U) 680 #define EIM_EICHD6_WORD1_B0_3DATA_MASK_WIDTH (32U) 681 #define EIM_EICHD6_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) 682 /*! @} */ 683 684 /*! @name EICHD6_WORD2 - Error Injection Channel Descriptor 6, Word2 */ 685 /*! @{ */ 686 687 #define EIM_EICHD6_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 688 #define EIM_EICHD6_WORD2_B4_7DATA_MASK_SHIFT (0U) 689 #define EIM_EICHD6_WORD2_B4_7DATA_MASK_WIDTH (32U) 690 #define EIM_EICHD6_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD6_WORD2_B4_7DATA_MASK_MASK) 691 /*! @} */ 692 693 /*! @name EICHD7_WORD0 - Error Injection Channel Descriptor 7, Word0 */ 694 /*! @{ */ 695 696 #define EIM_EICHD7_WORD0_CHKBIT_MASK_MASK (0xFFFC0000U) /* Merged from fields with different position or width, of widths (8, 14), largest definition used */ 697 #define EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT (18U) 698 #define EIM_EICHD7_WORD0_CHKBIT_MASK_WIDTH (14U) 699 #define EIM_EICHD7_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) /* Merged from fields with different position or width, of widths (8, 14), largest definition used */ 700 /*! @} */ 701 702 /*! @name EICHD7_WORD1 - Error Injection Channel Descriptor 7, Word1 */ 703 /*! @{ */ 704 705 #define EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 706 #define EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT (0U) 707 #define EIM_EICHD7_WORD1_B0_3DATA_MASK_WIDTH (32U) 708 #define EIM_EICHD7_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) 709 /*! @} */ 710 711 /*! @name EICHD7_WORD2 - Error Injection Channel Descriptor 7, Word2 */ 712 /*! @{ */ 713 714 #define EIM_EICHD7_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 715 #define EIM_EICHD7_WORD2_B4_7DATA_MASK_SHIFT (0U) 716 #define EIM_EICHD7_WORD2_B4_7DATA_MASK_WIDTH (32U) 717 #define EIM_EICHD7_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD7_WORD2_B4_7DATA_MASK_MASK) 718 /*! @} */ 719 720 /*! @name EICHD8_WORD0 - Error Injection Channel Descriptor 8, Word0 */ 721 /*! @{ */ 722 723 #define EIM_EICHD8_WORD0_CHKBIT_MASK_MASK (0xFFFFFFFFU) 724 #define EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT (0U) 725 #define EIM_EICHD8_WORD0_CHKBIT_MASK_WIDTH (32U) 726 #define EIM_EICHD8_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) 727 /*! @} */ 728 729 /*! @name EICHD8_WORD1 - Error Injection Channel Descriptor 8, Word1 */ 730 /*! @{ */ 731 732 #define EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 733 #define EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT (0U) 734 #define EIM_EICHD8_WORD1_B0_3DATA_MASK_WIDTH (32U) 735 #define EIM_EICHD8_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) 736 /*! @} */ 737 738 /*! @name EICHD8_WORD2 - Error Injection Channel Descriptor 8, Word2 */ 739 /*! @{ */ 740 741 #define EIM_EICHD8_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 742 #define EIM_EICHD8_WORD2_B4_7DATA_MASK_SHIFT (0U) 743 #define EIM_EICHD8_WORD2_B4_7DATA_MASK_WIDTH (32U) 744 #define EIM_EICHD8_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD8_WORD2_B4_7DATA_MASK_MASK) 745 /*! @} */ 746 747 /*! @name EICHD8_WORD3 - Error Injection Channel Descriptor 8, Word3 */ 748 /*! @{ */ 749 750 #define EIM_EICHD8_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) 751 #define EIM_EICHD8_WORD3_B8_11DATA_MASK_SHIFT (0U) 752 #define EIM_EICHD8_WORD3_B8_11DATA_MASK_WIDTH (32U) 753 #define EIM_EICHD8_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD8_WORD3_B8_11DATA_MASK_MASK) 754 /*! @} */ 755 756 /*! @name EICHD8_WORD4 - Error Injection Channel Descriptor 8, Word4 */ 757 /*! @{ */ 758 759 #define EIM_EICHD8_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) 760 #define EIM_EICHD8_WORD4_B12_15DATA_MASK_SHIFT (0U) 761 #define EIM_EICHD8_WORD4_B12_15DATA_MASK_WIDTH (32U) 762 #define EIM_EICHD8_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD8_WORD4_B12_15DATA_MASK_MASK) 763 /*! @} */ 764 765 /*! @name EICHD8_WORD5 - Error Injection Channel Descriptor 8, Word5 */ 766 /*! @{ */ 767 768 #define EIM_EICHD8_WORD5_B16_19DATA_MASK_MASK (0xFFFFFFFFU) 769 #define EIM_EICHD8_WORD5_B16_19DATA_MASK_SHIFT (0U) 770 #define EIM_EICHD8_WORD5_B16_19DATA_MASK_WIDTH (32U) 771 #define EIM_EICHD8_WORD5_B16_19DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD5_B16_19DATA_MASK_SHIFT)) & EIM_EICHD8_WORD5_B16_19DATA_MASK_MASK) 772 /*! @} */ 773 774 /*! @name EICHD8_WORD6 - Error Injection Channel Descriptor 8, Word6 */ 775 /*! @{ */ 776 777 #define EIM_EICHD8_WORD6_B20_23DATA_MASK_MASK (0xFFFFFFFFU) 778 #define EIM_EICHD8_WORD6_B20_23DATA_MASK_SHIFT (0U) 779 #define EIM_EICHD8_WORD6_B20_23DATA_MASK_WIDTH (32U) 780 #define EIM_EICHD8_WORD6_B20_23DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD6_B20_23DATA_MASK_SHIFT)) & EIM_EICHD8_WORD6_B20_23DATA_MASK_MASK) 781 /*! @} */ 782 783 /*! @name EICHD8_WORD7 - Error Injection Channel Descriptor 8, Word7 */ 784 /*! @{ */ 785 786 #define EIM_EICHD8_WORD7_B24_27DATA_MASK_MASK (0xFFFFFFFFU) 787 #define EIM_EICHD8_WORD7_B24_27DATA_MASK_SHIFT (0U) 788 #define EIM_EICHD8_WORD7_B24_27DATA_MASK_WIDTH (32U) 789 #define EIM_EICHD8_WORD7_B24_27DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD7_B24_27DATA_MASK_SHIFT)) & EIM_EICHD8_WORD7_B24_27DATA_MASK_MASK) 790 /*! @} */ 791 792 /*! @name EICHD8_WORD8 - Error Injection Channel Descriptor 8, Word8 */ 793 /*! @{ */ 794 795 #define EIM_EICHD8_WORD8_B28_31DATA_MASK_MASK (0xFFFFFFFFU) 796 #define EIM_EICHD8_WORD8_B28_31DATA_MASK_SHIFT (0U) 797 #define EIM_EICHD8_WORD8_B28_31DATA_MASK_WIDTH (32U) 798 #define EIM_EICHD8_WORD8_B28_31DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD8_B28_31DATA_MASK_SHIFT)) & EIM_EICHD8_WORD8_B28_31DATA_MASK_MASK) 799 /*! @} */ 800 801 /*! @name EICHD9_WORD0 - Error Injection Channel Descriptor 9, Word0 */ 802 /*! @{ */ 803 804 #define EIM_EICHD9_WORD0_CHKBIT_MASK_MASK (0xFFFC0000U) 805 #define EIM_EICHD9_WORD0_CHKBIT_MASK_SHIFT (18U) 806 #define EIM_EICHD9_WORD0_CHKBIT_MASK_WIDTH (14U) 807 #define EIM_EICHD9_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD9_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD9_WORD0_CHKBIT_MASK_MASK) 808 /*! @} */ 809 810 /*! @name EICHD9_WORD1 - Error Injection Channel Descriptor 9, Word1 */ 811 /*! @{ */ 812 813 #define EIM_EICHD9_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 814 #define EIM_EICHD9_WORD1_B0_3DATA_MASK_SHIFT (0U) 815 #define EIM_EICHD9_WORD1_B0_3DATA_MASK_WIDTH (32U) 816 #define EIM_EICHD9_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD9_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD9_WORD1_B0_3DATA_MASK_MASK) 817 /*! @} */ 818 819 /*! @name EICHD9_WORD2 - Error Injection Channel Descriptor 9, Word2 */ 820 /*! @{ */ 821 822 #define EIM_EICHD9_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 823 #define EIM_EICHD9_WORD2_B4_7DATA_MASK_SHIFT (0U) 824 #define EIM_EICHD9_WORD2_B4_7DATA_MASK_WIDTH (32U) 825 #define EIM_EICHD9_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD9_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD9_WORD2_B4_7DATA_MASK_MASK) 826 /*! @} */ 827 828 /*! @name EICHD9_WORD3 - Error Injection Channel Descriptor 9, Word3 */ 829 /*! @{ */ 830 831 #define EIM_EICHD9_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) 832 #define EIM_EICHD9_WORD3_B8_11DATA_MASK_SHIFT (0U) 833 #define EIM_EICHD9_WORD3_B8_11DATA_MASK_WIDTH (32U) 834 #define EIM_EICHD9_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD9_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD9_WORD3_B8_11DATA_MASK_MASK) 835 /*! @} */ 836 837 /*! @name EICHD9_WORD4 - Error Injection Channel Descriptor 9, Word4 */ 838 /*! @{ */ 839 840 #define EIM_EICHD9_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) 841 #define EIM_EICHD9_WORD4_B12_15DATA_MASK_SHIFT (0U) 842 #define EIM_EICHD9_WORD4_B12_15DATA_MASK_WIDTH (32U) 843 #define EIM_EICHD9_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD9_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD9_WORD4_B12_15DATA_MASK_MASK) 844 /*! @} */ 845 846 /*! @name EICHD9_WORD5 - Error Injection Channel Descriptor 9, Word5 */ 847 /*! @{ */ 848 849 #define EIM_EICHD9_WORD5_B16_19DATA_MASK_MASK (0xFFFFFFFFU) 850 #define EIM_EICHD9_WORD5_B16_19DATA_MASK_SHIFT (0U) 851 #define EIM_EICHD9_WORD5_B16_19DATA_MASK_WIDTH (32U) 852 #define EIM_EICHD9_WORD5_B16_19DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD9_WORD5_B16_19DATA_MASK_SHIFT)) & EIM_EICHD9_WORD5_B16_19DATA_MASK_MASK) 853 /*! @} */ 854 855 /*! @name EICHD9_WORD6 - Error Injection Channel Descriptor 9, Word6 */ 856 /*! @{ */ 857 858 #define EIM_EICHD9_WORD6_B20_23DATA_MASK_MASK (0xFFFFFFFFU) 859 #define EIM_EICHD9_WORD6_B20_23DATA_MASK_SHIFT (0U) 860 #define EIM_EICHD9_WORD6_B20_23DATA_MASK_WIDTH (32U) 861 #define EIM_EICHD9_WORD6_B20_23DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD9_WORD6_B20_23DATA_MASK_SHIFT)) & EIM_EICHD9_WORD6_B20_23DATA_MASK_MASK) 862 /*! @} */ 863 864 /*! @name EICHD9_WORD7 - Error Injection Channel Descriptor 9, Word7 */ 865 /*! @{ */ 866 867 #define EIM_EICHD9_WORD7_B24_27DATA_MASK_MASK (0xFFFFFFFFU) 868 #define EIM_EICHD9_WORD7_B24_27DATA_MASK_SHIFT (0U) 869 #define EIM_EICHD9_WORD7_B24_27DATA_MASK_WIDTH (32U) 870 #define EIM_EICHD9_WORD7_B24_27DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD9_WORD7_B24_27DATA_MASK_SHIFT)) & EIM_EICHD9_WORD7_B24_27DATA_MASK_MASK) 871 /*! @} */ 872 873 /*! @name EICHD9_WORD8 - Error Injection Channel Descriptor 9, Word8 */ 874 /*! @{ */ 875 876 #define EIM_EICHD9_WORD8_B28_31DATA_MASK_MASK (0xFFFFFFFFU) 877 #define EIM_EICHD9_WORD8_B28_31DATA_MASK_SHIFT (0U) 878 #define EIM_EICHD9_WORD8_B28_31DATA_MASK_WIDTH (32U) 879 #define EIM_EICHD9_WORD8_B28_31DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD9_WORD8_B28_31DATA_MASK_SHIFT)) & EIM_EICHD9_WORD8_B28_31DATA_MASK_MASK) 880 /*! @} */ 881 882 /*! @name EICHD10_WORD0 - Error Injection Channel Descriptor 10, Word0 */ 883 /*! @{ */ 884 885 #define EIM_EICHD10_WORD0_CHKBIT_MASK_MASK (0xFFFFFFFFU) 886 #define EIM_EICHD10_WORD0_CHKBIT_MASK_SHIFT (0U) 887 #define EIM_EICHD10_WORD0_CHKBIT_MASK_WIDTH (32U) 888 #define EIM_EICHD10_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD10_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD10_WORD0_CHKBIT_MASK_MASK) 889 /*! @} */ 890 891 /*! @name EICHD10_WORD1 - Error Injection Channel Descriptor 10, Word1 */ 892 /*! @{ */ 893 894 #define EIM_EICHD10_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (8, 32), largest definition used */ 895 #define EIM_EICHD10_WORD1_B0_3DATA_MASK_SHIFT (0U) 896 #define EIM_EICHD10_WORD1_B0_3DATA_MASK_WIDTH (32U) 897 #define EIM_EICHD10_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD10_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD10_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (8, 32), largest definition used */ 898 /*! @} */ 899 900 /*! @name EICHD10_WORD2 - Error Injection Channel Descriptor 10, Word2 */ 901 /*! @{ */ 902 903 #define EIM_EICHD10_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 904 #define EIM_EICHD10_WORD2_B4_7DATA_MASK_SHIFT (0U) 905 #define EIM_EICHD10_WORD2_B4_7DATA_MASK_WIDTH (32U) 906 #define EIM_EICHD10_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD10_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD10_WORD2_B4_7DATA_MASK_MASK) 907 /*! @} */ 908 909 /*! @name EICHD10_WORD3 - Error Injection Channel Descriptor 10, Word3 */ 910 /*! @{ */ 911 912 #define EIM_EICHD10_WORD3_B8_11DATA_MASK_MASK (0xFFFFFFFFU) 913 #define EIM_EICHD10_WORD3_B8_11DATA_MASK_SHIFT (0U) 914 #define EIM_EICHD10_WORD3_B8_11DATA_MASK_WIDTH (32U) 915 #define EIM_EICHD10_WORD3_B8_11DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD10_WORD3_B8_11DATA_MASK_SHIFT)) & EIM_EICHD10_WORD3_B8_11DATA_MASK_MASK) 916 /*! @} */ 917 918 /*! @name EICHD10_WORD4 - Error Injection Channel Descriptor 10, Word4 */ 919 /*! @{ */ 920 921 #define EIM_EICHD10_WORD4_B12_15DATA_MASK_MASK (0xFFFFFFFFU) 922 #define EIM_EICHD10_WORD4_B12_15DATA_MASK_SHIFT (0U) 923 #define EIM_EICHD10_WORD4_B12_15DATA_MASK_WIDTH (32U) 924 #define EIM_EICHD10_WORD4_B12_15DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD10_WORD4_B12_15DATA_MASK_SHIFT)) & EIM_EICHD10_WORD4_B12_15DATA_MASK_MASK) 925 /*! @} */ 926 927 /*! @name EICHD11_WORD0 - Error Injection Channel Descriptor 11, Word0 */ 928 /*! @{ */ 929 930 #define EIM_EICHD11_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 931 #define EIM_EICHD11_WORD0_CHKBIT_MASK_SHIFT (24U) 932 #define EIM_EICHD11_WORD0_CHKBIT_MASK_WIDTH (8U) 933 #define EIM_EICHD11_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD11_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD11_WORD0_CHKBIT_MASK_MASK) 934 /*! @} */ 935 936 /*! @name EICHD11_WORD1 - Error Injection Channel Descriptor 11, Word1 */ 937 /*! @{ */ 938 939 #define EIM_EICHD11_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (24, 32), largest definition used */ 940 #define EIM_EICHD11_WORD1_B0_3DATA_MASK_SHIFT (0U) 941 #define EIM_EICHD11_WORD1_B0_3DATA_MASK_WIDTH (32U) 942 #define EIM_EICHD11_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD11_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD11_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (24, 32), largest definition used */ 943 /*! @} */ 944 945 /*! @name EICHD11_WORD2 - Error Injection Channel Descriptor 11, Word2 */ 946 /*! @{ */ 947 948 #define EIM_EICHD11_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 949 #define EIM_EICHD11_WORD2_B4_7DATA_MASK_SHIFT (0U) 950 #define EIM_EICHD11_WORD2_B4_7DATA_MASK_WIDTH (32U) 951 #define EIM_EICHD11_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD11_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD11_WORD2_B4_7DATA_MASK_MASK) 952 /*! @} */ 953 954 /*! @name EICHD12_WORD0 - Error Injection Channel Descriptor 12, Word0 */ 955 /*! @{ */ 956 957 #define EIM_EICHD12_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 958 #define EIM_EICHD12_WORD0_CHKBIT_MASK_SHIFT (24U) 959 #define EIM_EICHD12_WORD0_CHKBIT_MASK_WIDTH (8U) 960 #define EIM_EICHD12_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD12_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD12_WORD0_CHKBIT_MASK_MASK) 961 /*! @} */ 962 963 /*! @name EICHD12_WORD1 - Error Injection Channel Descriptor 12, Word1 */ 964 /*! @{ */ 965 966 #define EIM_EICHD12_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (24, 32), largest definition used */ 967 #define EIM_EICHD12_WORD1_B0_3DATA_MASK_SHIFT (0U) 968 #define EIM_EICHD12_WORD1_B0_3DATA_MASK_WIDTH (32U) 969 #define EIM_EICHD12_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD12_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD12_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (24, 32), largest definition used */ 970 /*! @} */ 971 972 /*! @name EICHD12_WORD2 - Error Injection Channel Descriptor 12, Word2 */ 973 /*! @{ */ 974 975 #define EIM_EICHD12_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 976 #define EIM_EICHD12_WORD2_B4_7DATA_MASK_SHIFT (0U) 977 #define EIM_EICHD12_WORD2_B4_7DATA_MASK_WIDTH (32U) 978 #define EIM_EICHD12_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD12_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD12_WORD2_B4_7DATA_MASK_MASK) 979 /*! @} */ 980 981 /*! @name EICHD13_WORD0 - Error Injection Channel Descriptor 13, Word0 */ 982 /*! @{ */ 983 984 #define EIM_EICHD13_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 985 #define EIM_EICHD13_WORD0_CHKBIT_MASK_SHIFT (24U) 986 #define EIM_EICHD13_WORD0_CHKBIT_MASK_WIDTH (8U) 987 #define EIM_EICHD13_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD13_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD13_WORD0_CHKBIT_MASK_MASK) 988 /*! @} */ 989 990 /*! @name EICHD13_WORD1 - Error Injection Channel Descriptor 13, Word1 */ 991 /*! @{ */ 992 993 #define EIM_EICHD13_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 994 #define EIM_EICHD13_WORD1_B0_3DATA_MASK_SHIFT (0U) 995 #define EIM_EICHD13_WORD1_B0_3DATA_MASK_WIDTH (32U) 996 #define EIM_EICHD13_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD13_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD13_WORD1_B0_3DATA_MASK_MASK) 997 /*! @} */ 998 999 /*! @name EICHD13_WORD2 - Error Injection Channel Descriptor 13, Word2 */ 1000 /*! @{ */ 1001 1002 #define EIM_EICHD13_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1003 #define EIM_EICHD13_WORD2_B4_7DATA_MASK_SHIFT (0U) 1004 #define EIM_EICHD13_WORD2_B4_7DATA_MASK_WIDTH (32U) 1005 #define EIM_EICHD13_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD13_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD13_WORD2_B4_7DATA_MASK_MASK) 1006 /*! @} */ 1007 1008 /*! @name EICHD14_WORD0 - Error Injection Channel Descriptor 14, Word0 */ 1009 /*! @{ */ 1010 1011 #define EIM_EICHD14_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 1012 #define EIM_EICHD14_WORD0_CHKBIT_MASK_SHIFT (24U) 1013 #define EIM_EICHD14_WORD0_CHKBIT_MASK_WIDTH (8U) 1014 #define EIM_EICHD14_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD14_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD14_WORD0_CHKBIT_MASK_MASK) 1015 /*! @} */ 1016 1017 /*! @name EICHD14_WORD1 - Error Injection Channel Descriptor 14, Word1 */ 1018 /*! @{ */ 1019 1020 #define EIM_EICHD14_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 1021 #define EIM_EICHD14_WORD1_B0_3DATA_MASK_SHIFT (0U) 1022 #define EIM_EICHD14_WORD1_B0_3DATA_MASK_WIDTH (32U) 1023 #define EIM_EICHD14_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD14_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD14_WORD1_B0_3DATA_MASK_MASK) 1024 /*! @} */ 1025 1026 /*! @name EICHD14_WORD2 - Error Injection Channel Descriptor 14, Word2 */ 1027 /*! @{ */ 1028 1029 #define EIM_EICHD14_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1030 #define EIM_EICHD14_WORD2_B4_7DATA_MASK_SHIFT (0U) 1031 #define EIM_EICHD14_WORD2_B4_7DATA_MASK_WIDTH (32U) 1032 #define EIM_EICHD14_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD14_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD14_WORD2_B4_7DATA_MASK_MASK) 1033 /*! @} */ 1034 1035 /*! @name EICHD15_WORD0 - Error Injection Channel Descriptor 15, Word0 */ 1036 /*! @{ */ 1037 1038 #define EIM_EICHD15_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 1039 #define EIM_EICHD15_WORD0_CHKBIT_MASK_SHIFT (24U) 1040 #define EIM_EICHD15_WORD0_CHKBIT_MASK_WIDTH (8U) 1041 #define EIM_EICHD15_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD15_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD15_WORD0_CHKBIT_MASK_MASK) 1042 /*! @} */ 1043 1044 /*! @name EICHD15_WORD1 - Error Injection Channel Descriptor 15, Word1 */ 1045 /*! @{ */ 1046 1047 #define EIM_EICHD15_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 1048 #define EIM_EICHD15_WORD1_B0_3DATA_MASK_SHIFT (0U) 1049 #define EIM_EICHD15_WORD1_B0_3DATA_MASK_WIDTH (32U) 1050 #define EIM_EICHD15_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD15_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD15_WORD1_B0_3DATA_MASK_MASK) 1051 /*! @} */ 1052 1053 /*! @name EICHD15_WORD2 - Error Injection Channel Descriptor 15, Word2 */ 1054 /*! @{ */ 1055 1056 #define EIM_EICHD15_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1057 #define EIM_EICHD15_WORD2_B4_7DATA_MASK_SHIFT (0U) 1058 #define EIM_EICHD15_WORD2_B4_7DATA_MASK_WIDTH (32U) 1059 #define EIM_EICHD15_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD15_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD15_WORD2_B4_7DATA_MASK_MASK) 1060 /*! @} */ 1061 1062 /*! @name EICHD16_WORD0 - Error Injection Channel Descriptor 16, Word0 */ 1063 /*! @{ */ 1064 1065 #define EIM_EICHD16_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 1066 #define EIM_EICHD16_WORD0_CHKBIT_MASK_SHIFT (24U) 1067 #define EIM_EICHD16_WORD0_CHKBIT_MASK_WIDTH (8U) 1068 #define EIM_EICHD16_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD16_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD16_WORD0_CHKBIT_MASK_MASK) 1069 /*! @} */ 1070 1071 /*! @name EICHD16_WORD1 - Error Injection Channel Descriptor 16, Word1 */ 1072 /*! @{ */ 1073 1074 #define EIM_EICHD16_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (20, 32), largest definition used */ 1075 #define EIM_EICHD16_WORD1_B0_3DATA_MASK_SHIFT (0U) 1076 #define EIM_EICHD16_WORD1_B0_3DATA_MASK_WIDTH (32U) 1077 #define EIM_EICHD16_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD16_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD16_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (20, 32), largest definition used */ 1078 /*! @} */ 1079 1080 /*! @name EICHD16_WORD2 - Error Injection Channel Descriptor 16, Word2 */ 1081 /*! @{ */ 1082 1083 #define EIM_EICHD16_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1084 #define EIM_EICHD16_WORD2_B4_7DATA_MASK_SHIFT (0U) 1085 #define EIM_EICHD16_WORD2_B4_7DATA_MASK_WIDTH (32U) 1086 #define EIM_EICHD16_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD16_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD16_WORD2_B4_7DATA_MASK_MASK) 1087 /*! @} */ 1088 1089 /*! @name EICHD17_WORD0 - Error Injection Channel Descriptor 17, Word0 */ 1090 /*! @{ */ 1091 1092 #define EIM_EICHD17_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 1093 #define EIM_EICHD17_WORD0_CHKBIT_MASK_SHIFT (24U) 1094 #define EIM_EICHD17_WORD0_CHKBIT_MASK_WIDTH (8U) 1095 #define EIM_EICHD17_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD17_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD17_WORD0_CHKBIT_MASK_MASK) 1096 /*! @} */ 1097 1098 /*! @name EICHD17_WORD1 - Error Injection Channel Descriptor 17, Word1 */ 1099 /*! @{ */ 1100 1101 #define EIM_EICHD17_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (11, 32), largest definition used */ 1102 #define EIM_EICHD17_WORD1_B0_3DATA_MASK_SHIFT (0U) 1103 #define EIM_EICHD17_WORD1_B0_3DATA_MASK_WIDTH (32U) 1104 #define EIM_EICHD17_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD17_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD17_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (11, 32), largest definition used */ 1105 /*! @} */ 1106 1107 /*! @name EICHD17_WORD2 - Error Injection Channel Descriptor 17, Word2 */ 1108 /*! @{ */ 1109 1110 #define EIM_EICHD17_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1111 #define EIM_EICHD17_WORD2_B4_7DATA_MASK_SHIFT (0U) 1112 #define EIM_EICHD17_WORD2_B4_7DATA_MASK_WIDTH (32U) 1113 #define EIM_EICHD17_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD17_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD17_WORD2_B4_7DATA_MASK_MASK) 1114 /*! @} */ 1115 1116 /*! @name EICHD18_WORD1 - Error Injection Channel Descriptor 18, Word1 */ 1117 /*! @{ */ 1118 1119 #define EIM_EICHD18_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFU) /* Merged from fields with different position or width, of widths (11, 28), largest definition used */ 1120 #define EIM_EICHD18_WORD1_B0_3DATA_MASK_SHIFT (0U) 1121 #define EIM_EICHD18_WORD1_B0_3DATA_MASK_WIDTH (28U) 1122 #define EIM_EICHD18_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD18_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD18_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (11, 28), largest definition used */ 1123 /*! @} */ 1124 1125 /*! @name EICHD18_WORD2 - Error Injection Channel Descriptor 18, Word2 */ 1126 /*! @{ */ 1127 1128 #define EIM_EICHD18_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1129 #define EIM_EICHD18_WORD2_B4_7DATA_MASK_SHIFT (0U) 1130 #define EIM_EICHD18_WORD2_B4_7DATA_MASK_WIDTH (32U) 1131 #define EIM_EICHD18_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD18_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD18_WORD2_B4_7DATA_MASK_MASK) 1132 /*! @} */ 1133 1134 /*! @name EICHD19_WORD0 - Error Injection Channel Descriptor 19, Word0 */ 1135 /*! @{ */ 1136 1137 #define EIM_EICHD19_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 1138 #define EIM_EICHD19_WORD0_CHKBIT_MASK_SHIFT (24U) 1139 #define EIM_EICHD19_WORD0_CHKBIT_MASK_WIDTH (8U) 1140 #define EIM_EICHD19_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD19_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD19_WORD0_CHKBIT_MASK_MASK) 1141 /*! @} */ 1142 1143 /*! @name EICHD19_WORD1 - Error Injection Channel Descriptor 19, Word1 */ 1144 /*! @{ */ 1145 1146 #define EIM_EICHD19_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (28, 32), largest definition used */ 1147 #define EIM_EICHD19_WORD1_B0_3DATA_MASK_SHIFT (0U) 1148 #define EIM_EICHD19_WORD1_B0_3DATA_MASK_WIDTH (32U) 1149 #define EIM_EICHD19_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD19_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD19_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (28, 32), largest definition used */ 1150 /*! @} */ 1151 1152 /*! @name EICHD19_WORD2 - Error Injection Channel Descriptor 19, Word2 */ 1153 /*! @{ */ 1154 1155 #define EIM_EICHD19_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1156 #define EIM_EICHD19_WORD2_B4_7DATA_MASK_SHIFT (0U) 1157 #define EIM_EICHD19_WORD2_B4_7DATA_MASK_WIDTH (32U) 1158 #define EIM_EICHD19_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD19_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD19_WORD2_B4_7DATA_MASK_MASK) 1159 /*! @} */ 1160 1161 /*! @name EICHD20_WORD0 - Error Injection Channel Descriptor 20, Word0 */ 1162 /*! @{ */ 1163 1164 #define EIM_EICHD20_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 1165 #define EIM_EICHD20_WORD0_CHKBIT_MASK_SHIFT (24U) 1166 #define EIM_EICHD20_WORD0_CHKBIT_MASK_WIDTH (8U) 1167 #define EIM_EICHD20_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD20_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD20_WORD0_CHKBIT_MASK_MASK) 1168 /*! @} */ 1169 1170 /*! @name EICHD20_WORD1 - Error Injection Channel Descriptor 20, Word1 */ 1171 /*! @{ */ 1172 1173 #define EIM_EICHD20_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (28, 32), largest definition used */ 1174 #define EIM_EICHD20_WORD1_B0_3DATA_MASK_SHIFT (0U) 1175 #define EIM_EICHD20_WORD1_B0_3DATA_MASK_WIDTH (32U) 1176 #define EIM_EICHD20_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD20_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD20_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (28, 32), largest definition used */ 1177 /*! @} */ 1178 1179 /*! @name EICHD20_WORD2 - Error Injection Channel Descriptor 20, Word2 */ 1180 /*! @{ */ 1181 1182 #define EIM_EICHD20_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1183 #define EIM_EICHD20_WORD2_B4_7DATA_MASK_SHIFT (0U) 1184 #define EIM_EICHD20_WORD2_B4_7DATA_MASK_WIDTH (32U) 1185 #define EIM_EICHD20_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD20_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD20_WORD2_B4_7DATA_MASK_MASK) 1186 /*! @} */ 1187 1188 /*! @name EICHD21_WORD0 - Error Injection Channel Descriptor 21, Word0 */ 1189 /*! @{ */ 1190 1191 #define EIM_EICHD21_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 1192 #define EIM_EICHD21_WORD0_CHKBIT_MASK_SHIFT (24U) 1193 #define EIM_EICHD21_WORD0_CHKBIT_MASK_WIDTH (8U) 1194 #define EIM_EICHD21_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD21_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD21_WORD0_CHKBIT_MASK_MASK) 1195 /*! @} */ 1196 1197 /*! @name EICHD21_WORD1 - Error Injection Channel Descriptor 21, Word1 */ 1198 /*! @{ */ 1199 1200 #define EIM_EICHD21_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (28, 32), largest definition used */ 1201 #define EIM_EICHD21_WORD1_B0_3DATA_MASK_SHIFT (0U) 1202 #define EIM_EICHD21_WORD1_B0_3DATA_MASK_WIDTH (32U) 1203 #define EIM_EICHD21_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD21_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD21_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (28, 32), largest definition used */ 1204 /*! @} */ 1205 1206 /*! @name EICHD21_WORD2 - Error Injection Channel Descriptor 21, Word2 */ 1207 /*! @{ */ 1208 1209 #define EIM_EICHD21_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1210 #define EIM_EICHD21_WORD2_B4_7DATA_MASK_SHIFT (0U) 1211 #define EIM_EICHD21_WORD2_B4_7DATA_MASK_WIDTH (32U) 1212 #define EIM_EICHD21_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD21_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD21_WORD2_B4_7DATA_MASK_MASK) 1213 /*! @} */ 1214 1215 /*! @name EICHD22_WORD0 - Error Injection Channel Descriptor 22, Word0 */ 1216 /*! @{ */ 1217 1218 #define EIM_EICHD22_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 1219 #define EIM_EICHD22_WORD0_CHKBIT_MASK_SHIFT (24U) 1220 #define EIM_EICHD22_WORD0_CHKBIT_MASK_WIDTH (8U) 1221 #define EIM_EICHD22_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD22_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD22_WORD0_CHKBIT_MASK_MASK) 1222 /*! @} */ 1223 1224 /*! @name EICHD22_WORD1 - Error Injection Channel Descriptor 22, Word1 */ 1225 /*! @{ */ 1226 1227 #define EIM_EICHD22_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (20, 32), largest definition used */ 1228 #define EIM_EICHD22_WORD1_B0_3DATA_MASK_SHIFT (0U) 1229 #define EIM_EICHD22_WORD1_B0_3DATA_MASK_WIDTH (32U) 1230 #define EIM_EICHD22_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD22_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD22_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (20, 32), largest definition used */ 1231 /*! @} */ 1232 1233 /*! @name EICHD22_WORD2 - Error Injection Channel Descriptor 22, Word2 */ 1234 /*! @{ */ 1235 1236 #define EIM_EICHD22_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1237 #define EIM_EICHD22_WORD2_B4_7DATA_MASK_SHIFT (0U) 1238 #define EIM_EICHD22_WORD2_B4_7DATA_MASK_WIDTH (32U) 1239 #define EIM_EICHD22_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD22_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD22_WORD2_B4_7DATA_MASK_MASK) 1240 /*! @} */ 1241 1242 /*! @name EICHD23_WORD1 - Error Injection Channel Descriptor 23, Word1 */ 1243 /*! @{ */ 1244 1245 #define EIM_EICHD23_WORD1_B0_3DATA_MASK_MASK (0x7FFU) /* Merged from fields with different position or width, of widths (1, 11), largest definition used */ 1246 #define EIM_EICHD23_WORD1_B0_3DATA_MASK_SHIFT (0U) 1247 #define EIM_EICHD23_WORD1_B0_3DATA_MASK_WIDTH (11U) 1248 #define EIM_EICHD23_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD23_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD23_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (1, 11), largest definition used */ 1249 /*! @} */ 1250 1251 /*! @name EICHD24_WORD1 - Error Injection Channel Descriptor 24, Word1 */ 1252 /*! @{ */ 1253 1254 #define EIM_EICHD24_WORD1_B0_3DATA_MASK_MASK (0x3FFFFFFFU) /* Merged from fields with different position or width, of widths (1, 30), largest definition used */ 1255 #define EIM_EICHD24_WORD1_B0_3DATA_MASK_SHIFT (0U) 1256 #define EIM_EICHD24_WORD1_B0_3DATA_MASK_WIDTH (30U) 1257 #define EIM_EICHD24_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD24_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD24_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (1, 30), largest definition used */ 1258 /*! @} */ 1259 1260 /*! @name EICHD25_WORD1 - Error Injection Channel Descriptor 25, Word1 */ 1261 /*! @{ */ 1262 1263 #define EIM_EICHD25_WORD1_B0_3DATA_MASK_MASK (0x3U) 1264 #define EIM_EICHD25_WORD1_B0_3DATA_MASK_SHIFT (0U) 1265 #define EIM_EICHD25_WORD1_B0_3DATA_MASK_WIDTH (2U) 1266 #define EIM_EICHD25_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD25_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD25_WORD1_B0_3DATA_MASK_MASK) 1267 /*! @} */ 1268 1269 /*! @name EICHD26_WORD0 - Error Injection Channel Descriptor 26, Word0 */ 1270 /*! @{ */ 1271 1272 #define EIM_EICHD26_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 1273 #define EIM_EICHD26_WORD0_CHKBIT_MASK_SHIFT (24U) 1274 #define EIM_EICHD26_WORD0_CHKBIT_MASK_WIDTH (8U) 1275 #define EIM_EICHD26_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD26_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD26_WORD0_CHKBIT_MASK_MASK) 1276 /*! @} */ 1277 1278 /*! @name EICHD26_WORD1 - Error Injection Channel Descriptor 26, Word1 */ 1279 /*! @{ */ 1280 1281 #define EIM_EICHD26_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (26, 32), largest definition used */ 1282 #define EIM_EICHD26_WORD1_B0_3DATA_MASK_SHIFT (0U) 1283 #define EIM_EICHD26_WORD1_B0_3DATA_MASK_WIDTH (32U) 1284 #define EIM_EICHD26_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD26_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD26_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (26, 32), largest definition used */ 1285 /*! @} */ 1286 1287 /*! @name EICHD26_WORD2 - Error Injection Channel Descriptor 26, Word2 */ 1288 /*! @{ */ 1289 1290 #define EIM_EICHD26_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1291 #define EIM_EICHD26_WORD2_B4_7DATA_MASK_SHIFT (0U) 1292 #define EIM_EICHD26_WORD2_B4_7DATA_MASK_WIDTH (32U) 1293 #define EIM_EICHD26_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD26_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD26_WORD2_B4_7DATA_MASK_MASK) 1294 /*! @} */ 1295 1296 /*! @name EICHD27_WORD0 - Error Injection Channel Descriptor 27, Word0 */ 1297 /*! @{ */ 1298 1299 #define EIM_EICHD27_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 1300 #define EIM_EICHD27_WORD0_CHKBIT_MASK_SHIFT (24U) 1301 #define EIM_EICHD27_WORD0_CHKBIT_MASK_WIDTH (8U) 1302 #define EIM_EICHD27_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD27_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD27_WORD0_CHKBIT_MASK_MASK) 1303 /*! @} */ 1304 1305 /*! @name EICHD27_WORD1 - Error Injection Channel Descriptor 27, Word1 */ 1306 /*! @{ */ 1307 1308 #define EIM_EICHD27_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (10, 32), largest definition used */ 1309 #define EIM_EICHD27_WORD1_B0_3DATA_MASK_SHIFT (0U) 1310 #define EIM_EICHD27_WORD1_B0_3DATA_MASK_WIDTH (32U) 1311 #define EIM_EICHD27_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD27_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD27_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (10, 32), largest definition used */ 1312 /*! @} */ 1313 1314 /*! @name EICHD27_WORD2 - Error Injection Channel Descriptor 27, Word2 */ 1315 /*! @{ */ 1316 1317 #define EIM_EICHD27_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1318 #define EIM_EICHD27_WORD2_B4_7DATA_MASK_SHIFT (0U) 1319 #define EIM_EICHD27_WORD2_B4_7DATA_MASK_WIDTH (32U) 1320 #define EIM_EICHD27_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD27_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD27_WORD2_B4_7DATA_MASK_MASK) 1321 /*! @} */ 1322 1323 /*! @name EICHD28_WORD0 - Error Injection Channel Descriptor 28, Word0 */ 1324 /*! @{ */ 1325 1326 #define EIM_EICHD28_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 1327 #define EIM_EICHD28_WORD0_CHKBIT_MASK_SHIFT (24U) 1328 #define EIM_EICHD28_WORD0_CHKBIT_MASK_WIDTH (8U) 1329 #define EIM_EICHD28_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD28_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD28_WORD0_CHKBIT_MASK_MASK) 1330 /*! @} */ 1331 1332 /*! @name EICHD28_WORD1 - Error Injection Channel Descriptor 28, Word1 */ 1333 /*! @{ */ 1334 1335 #define EIM_EICHD28_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) 1336 #define EIM_EICHD28_WORD1_B0_3DATA_MASK_SHIFT (0U) 1337 #define EIM_EICHD28_WORD1_B0_3DATA_MASK_WIDTH (32U) 1338 #define EIM_EICHD28_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD28_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD28_WORD1_B0_3DATA_MASK_MASK) 1339 /*! @} */ 1340 1341 /*! @name EICHD28_WORD2 - Error Injection Channel Descriptor 28, Word2 */ 1342 /*! @{ */ 1343 1344 #define EIM_EICHD28_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1345 #define EIM_EICHD28_WORD2_B4_7DATA_MASK_SHIFT (0U) 1346 #define EIM_EICHD28_WORD2_B4_7DATA_MASK_WIDTH (32U) 1347 #define EIM_EICHD28_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD28_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD28_WORD2_B4_7DATA_MASK_MASK) 1348 /*! @} */ 1349 1350 /*! @name EICHD29_WORD0 - Error Injection Channel Descriptor 29, Word0 */ 1351 /*! @{ */ 1352 1353 #define EIM_EICHD29_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 1354 #define EIM_EICHD29_WORD0_CHKBIT_MASK_SHIFT (24U) 1355 #define EIM_EICHD29_WORD0_CHKBIT_MASK_WIDTH (8U) 1356 #define EIM_EICHD29_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD29_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD29_WORD0_CHKBIT_MASK_MASK) 1357 /*! @} */ 1358 1359 /*! @name EICHD29_WORD1 - Error Injection Channel Descriptor 29, Word1 */ 1360 /*! @{ */ 1361 1362 #define EIM_EICHD29_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (12, 32), largest definition used */ 1363 #define EIM_EICHD29_WORD1_B0_3DATA_MASK_SHIFT (0U) 1364 #define EIM_EICHD29_WORD1_B0_3DATA_MASK_WIDTH (32U) 1365 #define EIM_EICHD29_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD29_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD29_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (12, 32), largest definition used */ 1366 /*! @} */ 1367 1368 /*! @name EICHD29_WORD2 - Error Injection Channel Descriptor 29, Word2 */ 1369 /*! @{ */ 1370 1371 #define EIM_EICHD29_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1372 #define EIM_EICHD29_WORD2_B4_7DATA_MASK_SHIFT (0U) 1373 #define EIM_EICHD29_WORD2_B4_7DATA_MASK_WIDTH (32U) 1374 #define EIM_EICHD29_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD29_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD29_WORD2_B4_7DATA_MASK_MASK) 1375 /*! @} */ 1376 1377 /*! @name EICHD30_WORD0 - Error Injection Channel Descriptor 30, Word0 */ 1378 /*! @{ */ 1379 1380 #define EIM_EICHD30_WORD0_CHKBIT_MASK_MASK (0xFF000000U) 1381 #define EIM_EICHD30_WORD0_CHKBIT_MASK_SHIFT (24U) 1382 #define EIM_EICHD30_WORD0_CHKBIT_MASK_WIDTH (8U) 1383 #define EIM_EICHD30_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD30_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD30_WORD0_CHKBIT_MASK_MASK) 1384 /*! @} */ 1385 1386 /*! @name EICHD30_WORD1 - Error Injection Channel Descriptor 30, Word1 */ 1387 /*! @{ */ 1388 1389 #define EIM_EICHD30_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (22, 32), largest definition used */ 1390 #define EIM_EICHD30_WORD1_B0_3DATA_MASK_SHIFT (0U) 1391 #define EIM_EICHD30_WORD1_B0_3DATA_MASK_WIDTH (32U) 1392 #define EIM_EICHD30_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD30_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD30_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (22, 32), largest definition used */ 1393 /*! @} */ 1394 1395 /*! @name EICHD30_WORD2 - Error Injection Channel Descriptor 30, Word2 */ 1396 /*! @{ */ 1397 1398 #define EIM_EICHD30_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1399 #define EIM_EICHD30_WORD2_B4_7DATA_MASK_SHIFT (0U) 1400 #define EIM_EICHD30_WORD2_B4_7DATA_MASK_WIDTH (32U) 1401 #define EIM_EICHD30_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD30_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD30_WORD2_B4_7DATA_MASK_MASK) 1402 /*! @} */ 1403 1404 /*! @name EICHD31_WORD1 - Error Injection Channel Descriptor 31, Word1 */ 1405 /*! @{ */ 1406 1407 #define EIM_EICHD31_WORD1_B0_3DATA_MASK_MASK (0x3FFFFFU) /* Merged from fields with different position or width, of widths (13, 22), largest definition used */ 1408 #define EIM_EICHD31_WORD1_B0_3DATA_MASK_SHIFT (0U) 1409 #define EIM_EICHD31_WORD1_B0_3DATA_MASK_WIDTH (22U) 1410 #define EIM_EICHD31_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD31_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD31_WORD1_B0_3DATA_MASK_MASK) /* Merged from fields with different position or width, of widths (13, 22), largest definition used */ 1411 /*! @} */ 1412 1413 /*! @name EICHD31_WORD2 - Error Injection Channel Descriptor 31, Word2 */ 1414 /*! @{ */ 1415 1416 #define EIM_EICHD31_WORD2_B4_7DATA_MASK_MASK (0xFFFFFFFFU) 1417 #define EIM_EICHD31_WORD2_B4_7DATA_MASK_SHIFT (0U) 1418 #define EIM_EICHD31_WORD2_B4_7DATA_MASK_WIDTH (32U) 1419 #define EIM_EICHD31_WORD2_B4_7DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD31_WORD2_B4_7DATA_MASK_SHIFT)) & EIM_EICHD31_WORD2_B4_7DATA_MASK_MASK) 1420 /*! @} */ 1421 1422 /*! 1423 * @} 1424 */ /* end of group EIM_Register_Masks */ 1425 1426 /*! 1427 * @} 1428 */ /* end of group EIM_Peripheral_Access_Layer */ 1429 1430 #endif /* #if !defined(S32Z2_EIM_H_) */ 1431
