1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_CMU_FC.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_CMU_FC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_CMU_FC_H_) /* Check if memory map has not been already included */ 58 #define S32K344_CMU_FC_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CMU_FC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CMU_FC_Peripheral_Access_Layer CMU_FC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CMU_FC - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t GCR; /**< Global Configuration Register, offset: 0x0 */ 74 __IO uint32_t RCCR; /**< Reference Count Configuration Register, offset: 0x4 */ 75 __IO uint32_t HTCR; /**< High Threshold Configuration Register, offset: 0x8 */ 76 __IO uint32_t LTCR; /**< Low Threshold Configuration Register, offset: 0xC */ 77 __IO uint32_t SR; /**< Status Register, offset: 0x10 */ 78 __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x14 */ 79 } CMU_FC_Type, *CMU_FC_MemMapPtr; 80 81 /** Number of instances of the CMU_FC module. */ 82 #define CMU_FC_INSTANCE_COUNT (4u) 83 84 /* CMU_FC - Peripheral instance base addresses */ 85 /** Peripheral CMU_0 base address */ 86 #define IP_CMU_0_BASE (0x402BC000u) 87 /** Peripheral CMU_0 base pointer */ 88 #define IP_CMU_0 ((CMU_FC_Type *)IP_CMU_0_BASE) 89 /** Peripheral CMU_3 base address */ 90 #define IP_CMU_3_BASE (0x402BC060u) 91 /** Peripheral CMU_3 base pointer */ 92 #define IP_CMU_3 ((CMU_FC_Type *)IP_CMU_3_BASE) 93 /** Peripheral CMU_4 base address */ 94 #define IP_CMU_4_BASE (0x402BC080u) 95 /** Peripheral CMU_4 base pointer */ 96 #define IP_CMU_4 ((CMU_FC_Type *)IP_CMU_4_BASE) 97 /** Peripheral CMU_5 base address */ 98 #define IP_CMU_5_BASE (0x402BC0A0u) 99 /** Peripheral CMU_5 base pointer */ 100 #define IP_CMU_5 ((CMU_FC_Type *)IP_CMU_5_BASE) 101 /** Array initializer of CMU_FC peripheral base addresses */ 102 #define IP_CMU_FC_BASE_ADDRS { IP_CMU_0_BASE, IP_CMU_3_BASE, IP_CMU_4_BASE, IP_CMU_5_BASE } 103 /** Array initializer of CMU_FC peripheral base pointers */ 104 #define IP_CMU_FC_BASE_PTRS { IP_CMU_0, IP_CMU_3, IP_CMU_4, IP_CMU_5 } 105 106 /* ---------------------------------------------------------------------------- 107 -- CMU_FC Register Masks 108 ---------------------------------------------------------------------------- */ 109 110 /*! 111 * @addtogroup CMU_FC_Register_Masks CMU_FC Register Masks 112 * @{ 113 */ 114 115 /*! @name GCR - Global Configuration Register */ 116 /*! @{ */ 117 118 #define CMU_FC_GCR_FCE_MASK (0x1U) 119 #define CMU_FC_GCR_FCE_SHIFT (0U) 120 #define CMU_FC_GCR_FCE_WIDTH (1U) 121 #define CMU_FC_GCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_GCR_FCE_SHIFT)) & CMU_FC_GCR_FCE_MASK) 122 /*! @} */ 123 124 /*! @name RCCR - Reference Count Configuration Register */ 125 /*! @{ */ 126 127 #define CMU_FC_RCCR_REF_CNT_MASK (0xFFFFU) 128 #define CMU_FC_RCCR_REF_CNT_SHIFT (0U) 129 #define CMU_FC_RCCR_REF_CNT_WIDTH (16U) 130 #define CMU_FC_RCCR_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_RCCR_REF_CNT_SHIFT)) & CMU_FC_RCCR_REF_CNT_MASK) 131 /*! @} */ 132 133 /*! @name HTCR - High Threshold Configuration Register */ 134 /*! @{ */ 135 136 #define CMU_FC_HTCR_HFREF_MASK (0xFFFFFFU) 137 #define CMU_FC_HTCR_HFREF_SHIFT (0U) 138 #define CMU_FC_HTCR_HFREF_WIDTH (24U) 139 #define CMU_FC_HTCR_HFREF(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_HTCR_HFREF_SHIFT)) & CMU_FC_HTCR_HFREF_MASK) 140 /*! @} */ 141 142 /*! @name LTCR - Low Threshold Configuration Register */ 143 /*! @{ */ 144 145 #define CMU_FC_LTCR_LFREF_MASK (0xFFFFFFU) 146 #define CMU_FC_LTCR_LFREF_SHIFT (0U) 147 #define CMU_FC_LTCR_LFREF_WIDTH (24U) 148 #define CMU_FC_LTCR_LFREF(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_LTCR_LFREF_SHIFT)) & CMU_FC_LTCR_LFREF_MASK) 149 /*! @} */ 150 151 /*! @name SR - Status Register */ 152 /*! @{ */ 153 154 #define CMU_FC_SR_FLL_MASK (0x1U) 155 #define CMU_FC_SR_FLL_SHIFT (0U) 156 #define CMU_FC_SR_FLL_WIDTH (1U) 157 #define CMU_FC_SR_FLL(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_SR_FLL_SHIFT)) & CMU_FC_SR_FLL_MASK) 158 159 #define CMU_FC_SR_FHH_MASK (0x2U) 160 #define CMU_FC_SR_FHH_SHIFT (1U) 161 #define CMU_FC_SR_FHH_WIDTH (1U) 162 #define CMU_FC_SR_FHH(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_SR_FHH_SHIFT)) & CMU_FC_SR_FHH_MASK) 163 164 #define CMU_FC_SR_RS_MASK (0x10U) 165 #define CMU_FC_SR_RS_SHIFT (4U) 166 #define CMU_FC_SR_RS_WIDTH (1U) 167 #define CMU_FC_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_SR_RS_SHIFT)) & CMU_FC_SR_RS_MASK) 168 /*! @} */ 169 170 /*! @name IER - Interrupt Enable Register */ 171 /*! @{ */ 172 173 #define CMU_FC_IER_FLLIE_MASK (0x1U) 174 #define CMU_FC_IER_FLLIE_SHIFT (0U) 175 #define CMU_FC_IER_FLLIE_WIDTH (1U) 176 #define CMU_FC_IER_FLLIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_IER_FLLIE_SHIFT)) & CMU_FC_IER_FLLIE_MASK) 177 178 #define CMU_FC_IER_FHHIE_MASK (0x2U) 179 #define CMU_FC_IER_FHHIE_SHIFT (1U) 180 #define CMU_FC_IER_FHHIE_WIDTH (1U) 181 #define CMU_FC_IER_FHHIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_IER_FHHIE_SHIFT)) & CMU_FC_IER_FHHIE_MASK) 182 183 #define CMU_FC_IER_FLLAIE_MASK (0x4U) 184 #define CMU_FC_IER_FLLAIE_SHIFT (2U) 185 #define CMU_FC_IER_FLLAIE_WIDTH (1U) 186 #define CMU_FC_IER_FLLAIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_IER_FLLAIE_SHIFT)) & CMU_FC_IER_FLLAIE_MASK) 187 188 #define CMU_FC_IER_FHHAIE_MASK (0x8U) 189 #define CMU_FC_IER_FHHAIE_SHIFT (3U) 190 #define CMU_FC_IER_FHHAIE_WIDTH (1U) 191 #define CMU_FC_IER_FHHAIE(x) (((uint32_t)(((uint32_t)(x)) << CMU_FC_IER_FHHAIE_SHIFT)) & CMU_FC_IER_FHHAIE_MASK) 192 /*! @} */ 193 194 /*! 195 * @} 196 */ /* end of group CMU_FC_Register_Masks */ 197 198 /*! 199 * @} 200 */ /* end of group CMU_FC_Peripheral_Access_Layer */ 201 202 #endif /* #if !defined(S32K344_CMU_FC_H_) */ 203
