1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2022 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32K146_RTC.h
10  * @version 1.1
11  * @date 2022-01-31
12  * @brief Peripheral Access Layer for S32K146_RTC
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32K146_RTC_H_)  /* Check if memory map has not been already included */
58 #define S32K146_RTC_H_
59 
60 #include "S32K146_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- RTC Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
68  * @{
69  */
70 
71 /** RTC - Register Layout Typedef */
72 typedef struct {
73   __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
74   __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
75   __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
76   __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
77   __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
78   __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
79   __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
80   __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
81 } RTC_Type, *RTC_MemMapPtr;
82 
83 /** Number of instances of the RTC module. */
84 #define RTC_INSTANCE_COUNT                       (1u)
85 
86 /* RTC - Peripheral instance base addresses */
87 /** Peripheral RTC base address */
88 #define IP_RTC_BASE                              (0x4003D000u)
89 /** Peripheral RTC base pointer */
90 #define IP_RTC                                   ((RTC_Type *)IP_RTC_BASE)
91 /** Array initializer of RTC peripheral base addresses */
92 #define IP_RTC_BASE_ADDRS                        { IP_RTC_BASE }
93 /** Array initializer of RTC peripheral base pointers */
94 #define IP_RTC_BASE_PTRS                         { IP_RTC }
95 
96 /* ----------------------------------------------------------------------------
97    -- RTC Register Masks
98    ---------------------------------------------------------------------------- */
99 
100 /*!
101  * @addtogroup RTC_Register_Masks RTC Register Masks
102  * @{
103  */
104 
105 /*! @name TSR - RTC Time Seconds Register */
106 /*! @{ */
107 
108 #define RTC_TSR_TSR_MASK                         (0xFFFFFFFFU)
109 #define RTC_TSR_TSR_SHIFT                        (0U)
110 #define RTC_TSR_TSR_WIDTH                        (32U)
111 #define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
112 /*! @} */
113 
114 /*! @name TPR - RTC Time Prescaler Register */
115 /*! @{ */
116 
117 #define RTC_TPR_TPR_MASK                         (0xFFFFU)
118 #define RTC_TPR_TPR_SHIFT                        (0U)
119 #define RTC_TPR_TPR_WIDTH                        (16U)
120 #define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
121 /*! @} */
122 
123 /*! @name TAR - RTC Time Alarm Register */
124 /*! @{ */
125 
126 #define RTC_TAR_TAR_MASK                         (0xFFFFFFFFU)
127 #define RTC_TAR_TAR_SHIFT                        (0U)
128 #define RTC_TAR_TAR_WIDTH                        (32U)
129 #define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
130 /*! @} */
131 
132 /*! @name TCR - RTC Time Compensation Register */
133 /*! @{ */
134 
135 #define RTC_TCR_TCR_MASK                         (0xFFU)
136 #define RTC_TCR_TCR_SHIFT                        (0U)
137 #define RTC_TCR_TCR_WIDTH                        (8U)
138 #define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
139 
140 #define RTC_TCR_CIR_MASK                         (0xFF00U)
141 #define RTC_TCR_CIR_SHIFT                        (8U)
142 #define RTC_TCR_CIR_WIDTH                        (8U)
143 #define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
144 
145 #define RTC_TCR_TCV_MASK                         (0xFF0000U)
146 #define RTC_TCR_TCV_SHIFT                        (16U)
147 #define RTC_TCR_TCV_WIDTH                        (8U)
148 #define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
149 
150 #define RTC_TCR_CIC_MASK                         (0xFF000000U)
151 #define RTC_TCR_CIC_SHIFT                        (24U)
152 #define RTC_TCR_CIC_WIDTH                        (8U)
153 #define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
154 /*! @} */
155 
156 /*! @name CR - RTC Control Register */
157 /*! @{ */
158 
159 #define RTC_CR_SWR_MASK                          (0x1U)
160 #define RTC_CR_SWR_SHIFT                         (0U)
161 #define RTC_CR_SWR_WIDTH                         (1U)
162 #define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
163 
164 #define RTC_CR_SUP_MASK                          (0x4U)
165 #define RTC_CR_SUP_SHIFT                         (2U)
166 #define RTC_CR_SUP_WIDTH                         (1U)
167 #define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
168 
169 #define RTC_CR_UM_MASK                           (0x8U)
170 #define RTC_CR_UM_SHIFT                          (3U)
171 #define RTC_CR_UM_WIDTH                          (1U)
172 #define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
173 
174 #define RTC_CR_CPS_MASK                          (0x20U)
175 #define RTC_CR_CPS_SHIFT                         (5U)
176 #define RTC_CR_CPS_WIDTH                         (1U)
177 #define RTC_CR_CPS(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPS_SHIFT)) & RTC_CR_CPS_MASK)
178 
179 #define RTC_CR_LPOS_MASK                         (0x80U)
180 #define RTC_CR_LPOS_SHIFT                        (7U)
181 #define RTC_CR_LPOS_WIDTH                        (1U)
182 #define RTC_CR_LPOS(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_LPOS_SHIFT)) & RTC_CR_LPOS_MASK)
183 
184 #define RTC_CR_CLKO_MASK                         (0x200U)
185 #define RTC_CR_CLKO_SHIFT                        (9U)
186 #define RTC_CR_CLKO_WIDTH                        (1U)
187 #define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
188 
189 #define RTC_CR_CPE_MASK                          (0x1000000U)
190 #define RTC_CR_CPE_SHIFT                         (24U)
191 #define RTC_CR_CPE_WIDTH                         (1U)
192 #define RTC_CR_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_CPE_SHIFT)) & RTC_CR_CPE_MASK)
193 /*! @} */
194 
195 /*! @name SR - RTC Status Register */
196 /*! @{ */
197 
198 #define RTC_SR_TIF_MASK                          (0x1U)
199 #define RTC_SR_TIF_SHIFT                         (0U)
200 #define RTC_SR_TIF_WIDTH                         (1U)
201 #define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
202 
203 #define RTC_SR_TOF_MASK                          (0x2U)
204 #define RTC_SR_TOF_SHIFT                         (1U)
205 #define RTC_SR_TOF_WIDTH                         (1U)
206 #define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
207 
208 #define RTC_SR_TAF_MASK                          (0x4U)
209 #define RTC_SR_TAF_SHIFT                         (2U)
210 #define RTC_SR_TAF_WIDTH                         (1U)
211 #define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
212 
213 #define RTC_SR_TCE_MASK                          (0x10U)
214 #define RTC_SR_TCE_SHIFT                         (4U)
215 #define RTC_SR_TCE_WIDTH                         (1U)
216 #define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
217 /*! @} */
218 
219 /*! @name LR - RTC Lock Register */
220 /*! @{ */
221 
222 #define RTC_LR_TCL_MASK                          (0x8U)
223 #define RTC_LR_TCL_SHIFT                         (3U)
224 #define RTC_LR_TCL_WIDTH                         (1U)
225 #define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
226 
227 #define RTC_LR_CRL_MASK                          (0x10U)
228 #define RTC_LR_CRL_SHIFT                         (4U)
229 #define RTC_LR_CRL_WIDTH                         (1U)
230 #define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
231 
232 #define RTC_LR_SRL_MASK                          (0x20U)
233 #define RTC_LR_SRL_SHIFT                         (5U)
234 #define RTC_LR_SRL_WIDTH                         (1U)
235 #define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
236 
237 #define RTC_LR_LRL_MASK                          (0x40U)
238 #define RTC_LR_LRL_SHIFT                         (6U)
239 #define RTC_LR_LRL_WIDTH                         (1U)
240 #define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
241 /*! @} */
242 
243 /*! @name IER - RTC Interrupt Enable Register */
244 /*! @{ */
245 
246 #define RTC_IER_TIIE_MASK                        (0x1U)
247 #define RTC_IER_TIIE_SHIFT                       (0U)
248 #define RTC_IER_TIIE_WIDTH                       (1U)
249 #define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
250 
251 #define RTC_IER_TOIE_MASK                        (0x2U)
252 #define RTC_IER_TOIE_SHIFT                       (1U)
253 #define RTC_IER_TOIE_WIDTH                       (1U)
254 #define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
255 
256 #define RTC_IER_TAIE_MASK                        (0x4U)
257 #define RTC_IER_TAIE_SHIFT                       (2U)
258 #define RTC_IER_TAIE_WIDTH                       (1U)
259 #define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
260 
261 #define RTC_IER_TSIE_MASK                        (0x10U)
262 #define RTC_IER_TSIE_SHIFT                       (4U)
263 #define RTC_IER_TSIE_WIDTH                       (1U)
264 #define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
265 
266 #define RTC_IER_TSIC_MASK                        (0x70000U)
267 #define RTC_IER_TSIC_SHIFT                       (16U)
268 #define RTC_IER_TSIC_WIDTH                       (3U)
269 #define RTC_IER_TSIC(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIC_SHIFT)) & RTC_IER_TSIC_MASK)
270 /*! @} */
271 
272 /*!
273  * @}
274  */ /* end of group RTC_Register_Masks */
275 
276 /*!
277  * @}
278  */ /* end of group RTC_Peripheral_Access_Layer */
279 
280 #endif  /* #if !defined(S32K146_RTC_H_) */
281