1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K146_ERM.h 10 * @version 1.1 11 * @date 2022-01-31 12 * @brief Peripheral Access Layer for S32K146_ERM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K146_ERM_H_) /* Check if memory map has not been already included */ 58 #define S32K146_ERM_H_ 59 60 #include "S32K146_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ERM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ERM - Size of Registers Arrays */ 72 #define ERM_EARn_COUNT 2u 73 74 /** ERM - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t CR0; /**< ERM Configuration Register 0, offset: 0x0 */ 77 uint8_t RESERVED_0[12]; 78 __IO uint32_t SR0; /**< ERM Status Register 0, offset: 0x10 */ 79 uint8_t RESERVED_1[236]; 80 struct { /* offset: 0x100, array step: 0x10 */ 81 __I uint32_t EAR; /**< ERM Memory n Error Address Register, array offset: 0x100, array step: 0x10 */ 82 uint8_t RESERVED_0[12]; 83 } EARn[ERM_EARn_COUNT]; 84 } ERM_Type, *ERM_MemMapPtr; 85 86 /** Number of instances of the ERM module. */ 87 #define ERM_INSTANCE_COUNT (1u) 88 89 /* ERM - Peripheral instance base addresses */ 90 /** Peripheral ERM base address */ 91 #define IP_ERM_BASE (0x40018000u) 92 /** Peripheral ERM base pointer */ 93 #define IP_ERM ((ERM_Type *)IP_ERM_BASE) 94 /** Array initializer of ERM peripheral base addresses */ 95 #define IP_ERM_BASE_ADDRS { IP_ERM_BASE } 96 /** Array initializer of ERM peripheral base pointers */ 97 #define IP_ERM_BASE_PTRS { IP_ERM } 98 99 /* ---------------------------------------------------------------------------- 100 -- ERM Register Masks 101 ---------------------------------------------------------------------------- */ 102 103 /*! 104 * @addtogroup ERM_Register_Masks ERM Register Masks 105 * @{ 106 */ 107 108 /*! @name CR0 - ERM Configuration Register 0 */ 109 /*! @{ */ 110 111 #define ERM_CR0_ENCIE1_MASK (0x4000000U) 112 #define ERM_CR0_ENCIE1_SHIFT (26U) 113 #define ERM_CR0_ENCIE1_WIDTH (1U) 114 #define ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE1_SHIFT)) & ERM_CR0_ENCIE1_MASK) 115 116 #define ERM_CR0_ESCIE1_MASK (0x8000000U) 117 #define ERM_CR0_ESCIE1_SHIFT (27U) 118 #define ERM_CR0_ESCIE1_WIDTH (1U) 119 #define ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE1_SHIFT)) & ERM_CR0_ESCIE1_MASK) 120 121 #define ERM_CR0_ENCIE0_MASK (0x40000000U) 122 #define ERM_CR0_ENCIE0_SHIFT (30U) 123 #define ERM_CR0_ENCIE0_WIDTH (1U) 124 #define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE0_SHIFT)) & ERM_CR0_ENCIE0_MASK) 125 126 #define ERM_CR0_ESCIE0_MASK (0x80000000U) 127 #define ERM_CR0_ESCIE0_SHIFT (31U) 128 #define ERM_CR0_ESCIE0_WIDTH (1U) 129 #define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE0_SHIFT)) & ERM_CR0_ESCIE0_MASK) 130 /*! @} */ 131 132 /*! @name SR0 - ERM Status Register 0 */ 133 /*! @{ */ 134 135 #define ERM_SR0_NCE1_MASK (0x4000000U) 136 #define ERM_SR0_NCE1_SHIFT (26U) 137 #define ERM_SR0_NCE1_WIDTH (1U) 138 #define ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE1_SHIFT)) & ERM_SR0_NCE1_MASK) 139 140 #define ERM_SR0_SBC1_MASK (0x8000000U) 141 #define ERM_SR0_SBC1_SHIFT (27U) 142 #define ERM_SR0_SBC1_WIDTH (1U) 143 #define ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC1_SHIFT)) & ERM_SR0_SBC1_MASK) 144 145 #define ERM_SR0_NCE0_MASK (0x40000000U) 146 #define ERM_SR0_NCE0_SHIFT (30U) 147 #define ERM_SR0_NCE0_WIDTH (1U) 148 #define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE0_SHIFT)) & ERM_SR0_NCE0_MASK) 149 150 #define ERM_SR0_SBC0_MASK (0x80000000U) 151 #define ERM_SR0_SBC0_SHIFT (31U) 152 #define ERM_SR0_SBC0_WIDTH (1U) 153 #define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC0_SHIFT)) & ERM_SR0_SBC0_MASK) 154 /*! @} */ 155 156 /*! @name EAR - ERM Memory n Error Address Register */ 157 /*! @{ */ 158 159 #define ERM_EAR_EAR_MASK (0xFFFFFFFFU) 160 #define ERM_EAR_EAR_SHIFT (0U) 161 #define ERM_EAR_EAR_WIDTH (32U) 162 #define ERM_EAR_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR_EAR_SHIFT)) & ERM_EAR_EAR_MASK) 163 /*! @} */ 164 165 /*! 166 * @} 167 */ /* end of group ERM_Register_Masks */ 168 169 /*! 170 * @} 171 */ /* end of group ERM_Peripheral_Access_Layer */ 172 173 #endif /* #if !defined(S32K146_ERM_H_) */ 174
