1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K144W_TRGMUX.h 10 * @version 1.4 11 * @date 2022-02-09 12 * @brief Peripheral Access Layer for S32K144W_TRGMUX 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K144W_TRGMUX_H_) /* Check if memory map has not been already included */ 58 #define S32K144W_TRGMUX_H_ 59 60 #include "S32K144W_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- TRGMUX Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup TRGMUX_Peripheral_Access_Layer TRGMUX Peripheral Access Layer 68 * @{ 69 */ 70 71 /** TRGMUX - Size of Registers Arrays */ 72 #define TRGMUX_TRGMUXn_COUNT 26u 73 74 /** TRGMUX - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t TRGMUXn[TRGMUX_TRGMUXn_COUNT]; /**< TRGMUX DMAMUX0 Register..TRGMUX LPTMR0 Register, array offset: 0x0, array step: 0x4 */ 77 } TRGMUX_Type, *TRGMUX_MemMapPtr; 78 79 /** Number of instances of the TRGMUX module. */ 80 #define TRGMUX_INSTANCE_COUNT (1u) 81 82 /* TRGMUX - Peripheral instance base addresses */ 83 /** Peripheral TRGMUX base address */ 84 #define IP_TRGMUX_BASE (0x40063000u) 85 /** Peripheral TRGMUX base pointer */ 86 #define IP_TRGMUX ((TRGMUX_Type *)IP_TRGMUX_BASE) 87 /** Array initializer of TRGMUX peripheral base addresses */ 88 #define IP_TRGMUX_BASE_ADDRS { IP_TRGMUX_BASE } 89 /** Array initializer of TRGMUX peripheral base pointers */ 90 #define IP_TRGMUX_BASE_PTRS { IP_TRGMUX } 91 92 /* ---------------------------------------------------------------------------- 93 -- TRGMUX Register Masks 94 ---------------------------------------------------------------------------- */ 95 96 /*! 97 * @addtogroup TRGMUX_Register_Masks TRGMUX Register Masks 98 * @{ 99 */ 100 101 /*! @name TRGMUXn - TRGMUX DMAMUX0 Register..TRGMUX LPTMR0 Register */ 102 /*! @{ */ 103 104 #define TRGMUX_TRGMUXn_SEL0_MASK (0x3FU) 105 #define TRGMUX_TRGMUXn_SEL0_SHIFT (0U) 106 #define TRGMUX_TRGMUXn_SEL0_WIDTH (6U) 107 #define TRGMUX_TRGMUXn_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGMUXn_SEL0_SHIFT)) & TRGMUX_TRGMUXn_SEL0_MASK) 108 109 #define TRGMUX_TRGMUXn_SEL1_MASK (0x3F00U) 110 #define TRGMUX_TRGMUXn_SEL1_SHIFT (8U) 111 #define TRGMUX_TRGMUXn_SEL1_WIDTH (6U) 112 #define TRGMUX_TRGMUXn_SEL1(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGMUXn_SEL1_SHIFT)) & TRGMUX_TRGMUXn_SEL1_MASK) 113 114 #define TRGMUX_TRGMUXn_SEL2_MASK (0x3F0000U) 115 #define TRGMUX_TRGMUXn_SEL2_SHIFT (16U) 116 #define TRGMUX_TRGMUXn_SEL2_WIDTH (6U) 117 #define TRGMUX_TRGMUXn_SEL2(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGMUXn_SEL2_SHIFT)) & TRGMUX_TRGMUXn_SEL2_MASK) 118 119 #define TRGMUX_TRGMUXn_SEL3_MASK (0x3F000000U) 120 #define TRGMUX_TRGMUXn_SEL3_SHIFT (24U) 121 #define TRGMUX_TRGMUXn_SEL3_WIDTH (6U) 122 #define TRGMUX_TRGMUXn_SEL3(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGMUXn_SEL3_SHIFT)) & TRGMUX_TRGMUXn_SEL3_MASK) 123 124 #define TRGMUX_TRGMUXn_LK_MASK (0x80000000U) 125 #define TRGMUX_TRGMUXn_LK_SHIFT (31U) 126 #define TRGMUX_TRGMUXn_LK_WIDTH (1U) 127 #define TRGMUX_TRGMUXn_LK(x) (((uint32_t)(((uint32_t)(x)) << TRGMUX_TRGMUXn_LK_SHIFT)) & TRGMUX_TRGMUXn_LK_MASK) 128 /*! @} */ 129 130 /*! 131 * @} 132 */ /* end of group TRGMUX_Register_Masks */ 133 #define TRGMUX_DMAMUX0_INDEX 0 134 #define TRGMUX_EXTOUT0_INDEX 1 135 #define TRGMUX_EXTOUT1_INDEX 2 136 #define TRGMUX_ADC0_INDEX 3 137 #define TRGMUX_ADC1_INDEX 4 138 #define TRGMUX_CMP0_INDEX 7 139 #define TRGMUX_FTM0_INDEX 10 140 #define TRGMUX_FTM1_INDEX 11 141 #define TRGMUX_FTM2_INDEX 12 142 #define TRGMUX_FTM3_INDEX 13 143 #define TRGMUX_PDB0_INDEX 14 144 #define TRGMUX_PDB1_INDEX 15 145 #define TRGMUX_FLEXIO_INDEX 17 146 #define TRGMUX_LPIT0_INDEX 18 147 #define TRGMUX_LPUART0_INDEX 19 148 #define TRGMUX_LPUART1_INDEX 20 149 #define TRGMUX_LPI2C0_INDEX 21 150 #define TRGMUX_LPSPI0_INDEX 23 151 #define TRGMUX_LPSPI1_INDEX 24 152 #define TRGMUX_LPTMR0_INDEX 25 153 154 155 /*! 156 * @} 157 */ /* end of group TRGMUX_Peripheral_Access_Layer */ 158 159 #endif /* #if !defined(S32K144W_TRGMUX_H_) */ 160
