1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K144W_MSCM.h 10 * @version 1.4 11 * @date 2022-02-09 12 * @brief Peripheral Access Layer for S32K144W_MSCM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K144W_MSCM_H_) /* Check if memory map has not been already included */ 58 #define S32K144W_MSCM_H_ 59 60 #include "S32K144W_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MSCM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MSCM_Peripheral_Access_Layer MSCM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MSCM - Size of Registers Arrays */ 72 #define MSCM_OCMDR_COUNT 3u 73 74 /** MSCM - Register Layout Typedef */ 75 typedef struct { 76 __I uint32_t CPxTYPE; /**< Processor X Type Register, offset: 0x0 */ 77 __I uint32_t CPxNUM; /**< Processor X Number Register, offset: 0x4 */ 78 __I uint32_t CPxMASTER; /**< Processor X Master Register, offset: 0x8 */ 79 __I uint32_t CPxCOUNT; /**< Processor X Count Register, offset: 0xC */ 80 __I uint32_t CPxCFG0; /**< Processor X Configuration Register 0, offset: 0x10 */ 81 __I uint32_t CPxCFG1; /**< Processor X Configuration Register 1, offset: 0x14 */ 82 __I uint32_t CPxCFG2; /**< Processor X Configuration Register 2, offset: 0x18 */ 83 __I uint32_t CPxCFG3; /**< Processor X Configuration Register 3, offset: 0x1C */ 84 __I uint32_t CP0TYPE; /**< Processor 0 Type Register, offset: 0x20 */ 85 __I uint32_t CP0NUM; /**< Processor 0 Number Register, offset: 0x24 */ 86 __I uint32_t CP0MASTER; /**< Processor 0 Master Register, offset: 0x28 */ 87 __I uint32_t CP0COUNT; /**< Processor 0 Count Register, offset: 0x2C */ 88 __I uint32_t CP0CFG0; /**< Processor 0 Configuration Register 0, offset: 0x30 */ 89 __I uint32_t CP0CFG1; /**< Processor 0 Configuration Register 1, offset: 0x34 */ 90 __I uint32_t CP0CFG2; /**< Processor 0 Configuration Register 2, offset: 0x38 */ 91 __I uint32_t CP0CFG3; /**< Processor 0 Configuration Register 3, offset: 0x3C */ 92 uint8_t RESERVED_0[960]; 93 __IO uint32_t OCMDR[MSCM_OCMDR_COUNT]; /**< On-Chip Memory Descriptor Register, array offset: 0x400, array step: 0x4 */ 94 } MSCM_Type, *MSCM_MemMapPtr; 95 96 /** Number of instances of the MSCM module. */ 97 #define MSCM_INSTANCE_COUNT (1u) 98 99 /* MSCM - Peripheral instance base addresses */ 100 /** Peripheral MSCM base address */ 101 #define IP_MSCM_BASE (0x40001000u) 102 /** Peripheral MSCM base pointer */ 103 #define IP_MSCM ((MSCM_Type *)IP_MSCM_BASE) 104 /** Array initializer of MSCM peripheral base addresses */ 105 #define IP_MSCM_BASE_ADDRS { IP_MSCM_BASE } 106 /** Array initializer of MSCM peripheral base pointers */ 107 #define IP_MSCM_BASE_PTRS { IP_MSCM } 108 109 /* ---------------------------------------------------------------------------- 110 -- MSCM Register Masks 111 ---------------------------------------------------------------------------- */ 112 113 /*! 114 * @addtogroup MSCM_Register_Masks MSCM Register Masks 115 * @{ 116 */ 117 118 /*! @name CPxTYPE - Processor X Type Register */ 119 /*! @{ */ 120 121 #define MSCM_CPxTYPE_RYPZ_MASK (0xFFU) 122 #define MSCM_CPxTYPE_RYPZ_SHIFT (0U) 123 #define MSCM_CPxTYPE_RYPZ_WIDTH (8U) 124 #define MSCM_CPxTYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxTYPE_RYPZ_SHIFT)) & MSCM_CPxTYPE_RYPZ_MASK) 125 126 #define MSCM_CPxTYPE_PERSONALITY_MASK (0xFFFFFF00U) 127 #define MSCM_CPxTYPE_PERSONALITY_SHIFT (8U) 128 #define MSCM_CPxTYPE_PERSONALITY_WIDTH (24U) 129 #define MSCM_CPxTYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxTYPE_PERSONALITY_SHIFT)) & MSCM_CPxTYPE_PERSONALITY_MASK) 130 /*! @} */ 131 132 /*! @name CPxNUM - Processor X Number Register */ 133 /*! @{ */ 134 135 #define MSCM_CPxNUM_CPN_MASK (0x1U) 136 #define MSCM_CPxNUM_CPN_SHIFT (0U) 137 #define MSCM_CPxNUM_CPN_WIDTH (1U) 138 #define MSCM_CPxNUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxNUM_CPN_SHIFT)) & MSCM_CPxNUM_CPN_MASK) 139 /*! @} */ 140 141 /*! @name CPxMASTER - Processor X Master Register */ 142 /*! @{ */ 143 144 #define MSCM_CPxMASTER_PPMN_MASK (0x3FU) 145 #define MSCM_CPxMASTER_PPMN_SHIFT (0U) 146 #define MSCM_CPxMASTER_PPMN_WIDTH (6U) 147 #define MSCM_CPxMASTER_PPMN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxMASTER_PPMN_SHIFT)) & MSCM_CPxMASTER_PPMN_MASK) 148 /*! @} */ 149 150 /*! @name CPxCOUNT - Processor X Count Register */ 151 /*! @{ */ 152 153 #define MSCM_CPxCOUNT_PCNT_MASK (0x3U) 154 #define MSCM_CPxCOUNT_PCNT_SHIFT (0U) 155 #define MSCM_CPxCOUNT_PCNT_WIDTH (2U) 156 #define MSCM_CPxCOUNT_PCNT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCOUNT_PCNT_SHIFT)) & MSCM_CPxCOUNT_PCNT_MASK) 157 /*! @} */ 158 159 /*! @name CPxCFG0 - Processor X Configuration Register 0 */ 160 /*! @{ */ 161 162 #define MSCM_CPxCFG0_DCWY_MASK (0xFFU) 163 #define MSCM_CPxCFG0_DCWY_SHIFT (0U) 164 #define MSCM_CPxCFG0_DCWY_WIDTH (8U) 165 #define MSCM_CPxCFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG0_DCWY_SHIFT)) & MSCM_CPxCFG0_DCWY_MASK) 166 167 #define MSCM_CPxCFG0_DCSZ_MASK (0xFF00U) 168 #define MSCM_CPxCFG0_DCSZ_SHIFT (8U) 169 #define MSCM_CPxCFG0_DCSZ_WIDTH (8U) 170 #define MSCM_CPxCFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG0_DCSZ_SHIFT)) & MSCM_CPxCFG0_DCSZ_MASK) 171 172 #define MSCM_CPxCFG0_ICWY_MASK (0xFF0000U) 173 #define MSCM_CPxCFG0_ICWY_SHIFT (16U) 174 #define MSCM_CPxCFG0_ICWY_WIDTH (8U) 175 #define MSCM_CPxCFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG0_ICWY_SHIFT)) & MSCM_CPxCFG0_ICWY_MASK) 176 177 #define MSCM_CPxCFG0_ICSZ_MASK (0xFF000000U) 178 #define MSCM_CPxCFG0_ICSZ_SHIFT (24U) 179 #define MSCM_CPxCFG0_ICSZ_WIDTH (8U) 180 #define MSCM_CPxCFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG0_ICSZ_SHIFT)) & MSCM_CPxCFG0_ICSZ_MASK) 181 /*! @} */ 182 183 /*! @name CPxCFG1 - Processor X Configuration Register 1 */ 184 /*! @{ */ 185 186 #define MSCM_CPxCFG1_L2WY_MASK (0xFF0000U) 187 #define MSCM_CPxCFG1_L2WY_SHIFT (16U) 188 #define MSCM_CPxCFG1_L2WY_WIDTH (8U) 189 #define MSCM_CPxCFG1_L2WY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG1_L2WY_SHIFT)) & MSCM_CPxCFG1_L2WY_MASK) 190 191 #define MSCM_CPxCFG1_L2SZ_MASK (0xFF000000U) 192 #define MSCM_CPxCFG1_L2SZ_SHIFT (24U) 193 #define MSCM_CPxCFG1_L2SZ_WIDTH (8U) 194 #define MSCM_CPxCFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG1_L2SZ_SHIFT)) & MSCM_CPxCFG1_L2SZ_MASK) 195 /*! @} */ 196 197 /*! @name CPxCFG2 - Processor X Configuration Register 2 */ 198 /*! @{ */ 199 200 #define MSCM_CPxCFG2_TMUSZ_MASK (0xFF00U) 201 #define MSCM_CPxCFG2_TMUSZ_SHIFT (8U) 202 #define MSCM_CPxCFG2_TMUSZ_WIDTH (8U) 203 #define MSCM_CPxCFG2_TMUSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG2_TMUSZ_SHIFT)) & MSCM_CPxCFG2_TMUSZ_MASK) 204 205 #define MSCM_CPxCFG2_TMLSZ_MASK (0xFF000000U) 206 #define MSCM_CPxCFG2_TMLSZ_SHIFT (24U) 207 #define MSCM_CPxCFG2_TMLSZ_WIDTH (8U) 208 #define MSCM_CPxCFG2_TMLSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG2_TMLSZ_SHIFT)) & MSCM_CPxCFG2_TMLSZ_MASK) 209 /*! @} */ 210 211 /*! @name CPxCFG3 - Processor X Configuration Register 3 */ 212 /*! @{ */ 213 214 #define MSCM_CPxCFG3_FPU_MASK (0x1U) 215 #define MSCM_CPxCFG3_FPU_SHIFT (0U) 216 #define MSCM_CPxCFG3_FPU_WIDTH (1U) 217 #define MSCM_CPxCFG3_FPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_FPU_SHIFT)) & MSCM_CPxCFG3_FPU_MASK) 218 219 #define MSCM_CPxCFG3_SIMD_MASK (0x2U) 220 #define MSCM_CPxCFG3_SIMD_SHIFT (1U) 221 #define MSCM_CPxCFG3_SIMD_WIDTH (1U) 222 #define MSCM_CPxCFG3_SIMD(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_SIMD_SHIFT)) & MSCM_CPxCFG3_SIMD_MASK) 223 224 #define MSCM_CPxCFG3_JAZ_MASK (0x4U) 225 #define MSCM_CPxCFG3_JAZ_SHIFT (2U) 226 #define MSCM_CPxCFG3_JAZ_WIDTH (1U) 227 #define MSCM_CPxCFG3_JAZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_JAZ_SHIFT)) & MSCM_CPxCFG3_JAZ_MASK) 228 229 #define MSCM_CPxCFG3_MMU_MASK (0x8U) 230 #define MSCM_CPxCFG3_MMU_SHIFT (3U) 231 #define MSCM_CPxCFG3_MMU_WIDTH (1U) 232 #define MSCM_CPxCFG3_MMU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_MMU_SHIFT)) & MSCM_CPxCFG3_MMU_MASK) 233 234 #define MSCM_CPxCFG3_TZ_MASK (0x10U) 235 #define MSCM_CPxCFG3_TZ_SHIFT (4U) 236 #define MSCM_CPxCFG3_TZ_WIDTH (1U) 237 #define MSCM_CPxCFG3_TZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_TZ_SHIFT)) & MSCM_CPxCFG3_TZ_MASK) 238 239 #define MSCM_CPxCFG3_CMP_MASK (0x20U) 240 #define MSCM_CPxCFG3_CMP_SHIFT (5U) 241 #define MSCM_CPxCFG3_CMP_WIDTH (1U) 242 #define MSCM_CPxCFG3_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_CMP_SHIFT)) & MSCM_CPxCFG3_CMP_MASK) 243 244 #define MSCM_CPxCFG3_BB_MASK (0x40U) 245 #define MSCM_CPxCFG3_BB_SHIFT (6U) 246 #define MSCM_CPxCFG3_BB_WIDTH (1U) 247 #define MSCM_CPxCFG3_BB(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_BB_SHIFT)) & MSCM_CPxCFG3_BB_MASK) 248 249 #define MSCM_CPxCFG3_SBP_MASK (0x300U) 250 #define MSCM_CPxCFG3_SBP_SHIFT (8U) 251 #define MSCM_CPxCFG3_SBP_WIDTH (2U) 252 #define MSCM_CPxCFG3_SBP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CPxCFG3_SBP_SHIFT)) & MSCM_CPxCFG3_SBP_MASK) 253 /*! @} */ 254 255 /*! @name CP0TYPE - Processor 0 Type Register */ 256 /*! @{ */ 257 258 #define MSCM_CP0TYPE_RYPZ_MASK (0xFFU) 259 #define MSCM_CP0TYPE_RYPZ_SHIFT (0U) 260 #define MSCM_CP0TYPE_RYPZ_WIDTH (8U) 261 #define MSCM_CP0TYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0TYPE_RYPZ_SHIFT)) & MSCM_CP0TYPE_RYPZ_MASK) 262 263 #define MSCM_CP0TYPE_PERSONALITY_MASK (0xFFFFFF00U) 264 #define MSCM_CP0TYPE_PERSONALITY_SHIFT (8U) 265 #define MSCM_CP0TYPE_PERSONALITY_WIDTH (24U) 266 #define MSCM_CP0TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0TYPE_PERSONALITY_SHIFT)) & MSCM_CP0TYPE_PERSONALITY_MASK) 267 /*! @} */ 268 269 /*! @name CP0NUM - Processor 0 Number Register */ 270 /*! @{ */ 271 272 #define MSCM_CP0NUM_CPN_MASK (0x1U) 273 #define MSCM_CP0NUM_CPN_SHIFT (0U) 274 #define MSCM_CP0NUM_CPN_WIDTH (1U) 275 #define MSCM_CP0NUM_CPN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0NUM_CPN_SHIFT)) & MSCM_CP0NUM_CPN_MASK) 276 /*! @} */ 277 278 /*! @name CP0MASTER - Processor 0 Master Register */ 279 /*! @{ */ 280 281 #define MSCM_CP0MASTER_PPMN_MASK (0x3FU) 282 #define MSCM_CP0MASTER_PPMN_SHIFT (0U) 283 #define MSCM_CP0MASTER_PPMN_WIDTH (6U) 284 #define MSCM_CP0MASTER_PPMN(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0MASTER_PPMN_SHIFT)) & MSCM_CP0MASTER_PPMN_MASK) 285 /*! @} */ 286 287 /*! @name CP0COUNT - Processor 0 Count Register */ 288 /*! @{ */ 289 290 #define MSCM_CP0COUNT_PCNT_MASK (0x3U) 291 #define MSCM_CP0COUNT_PCNT_SHIFT (0U) 292 #define MSCM_CP0COUNT_PCNT_WIDTH (2U) 293 #define MSCM_CP0COUNT_PCNT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0COUNT_PCNT_SHIFT)) & MSCM_CP0COUNT_PCNT_MASK) 294 /*! @} */ 295 296 /*! @name CP0CFG0 - Processor 0 Configuration Register 0 */ 297 /*! @{ */ 298 299 #define MSCM_CP0CFG0_DCWY_MASK (0xFFU) 300 #define MSCM_CP0CFG0_DCWY_SHIFT (0U) 301 #define MSCM_CP0CFG0_DCWY_WIDTH (8U) 302 #define MSCM_CP0CFG0_DCWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_DCWY_SHIFT)) & MSCM_CP0CFG0_DCWY_MASK) 303 304 #define MSCM_CP0CFG0_DCSZ_MASK (0xFF00U) 305 #define MSCM_CP0CFG0_DCSZ_SHIFT (8U) 306 #define MSCM_CP0CFG0_DCSZ_WIDTH (8U) 307 #define MSCM_CP0CFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_DCSZ_SHIFT)) & MSCM_CP0CFG0_DCSZ_MASK) 308 309 #define MSCM_CP0CFG0_ICWY_MASK (0xFF0000U) 310 #define MSCM_CP0CFG0_ICWY_SHIFT (16U) 311 #define MSCM_CP0CFG0_ICWY_WIDTH (8U) 312 #define MSCM_CP0CFG0_ICWY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_ICWY_SHIFT)) & MSCM_CP0CFG0_ICWY_MASK) 313 314 #define MSCM_CP0CFG0_ICSZ_MASK (0xFF000000U) 315 #define MSCM_CP0CFG0_ICSZ_SHIFT (24U) 316 #define MSCM_CP0CFG0_ICSZ_WIDTH (8U) 317 #define MSCM_CP0CFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG0_ICSZ_SHIFT)) & MSCM_CP0CFG0_ICSZ_MASK) 318 /*! @} */ 319 320 /*! @name CP0CFG1 - Processor 0 Configuration Register 1 */ 321 /*! @{ */ 322 323 #define MSCM_CP0CFG1_L2WY_MASK (0xFF0000U) 324 #define MSCM_CP0CFG1_L2WY_SHIFT (16U) 325 #define MSCM_CP0CFG1_L2WY_WIDTH (8U) 326 #define MSCM_CP0CFG1_L2WY(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG1_L2WY_SHIFT)) & MSCM_CP0CFG1_L2WY_MASK) 327 328 #define MSCM_CP0CFG1_L2SZ_MASK (0xFF000000U) 329 #define MSCM_CP0CFG1_L2SZ_SHIFT (24U) 330 #define MSCM_CP0CFG1_L2SZ_WIDTH (8U) 331 #define MSCM_CP0CFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG1_L2SZ_SHIFT)) & MSCM_CP0CFG1_L2SZ_MASK) 332 /*! @} */ 333 334 /*! @name CP0CFG2 - Processor 0 Configuration Register 2 */ 335 /*! @{ */ 336 337 #define MSCM_CP0CFG2_TMUSZ_MASK (0xFF00U) 338 #define MSCM_CP0CFG2_TMUSZ_SHIFT (8U) 339 #define MSCM_CP0CFG2_TMUSZ_WIDTH (8U) 340 #define MSCM_CP0CFG2_TMUSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG2_TMUSZ_SHIFT)) & MSCM_CP0CFG2_TMUSZ_MASK) 341 342 #define MSCM_CP0CFG2_TMLSZ_MASK (0xFF000000U) 343 #define MSCM_CP0CFG2_TMLSZ_SHIFT (24U) 344 #define MSCM_CP0CFG2_TMLSZ_WIDTH (8U) 345 #define MSCM_CP0CFG2_TMLSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG2_TMLSZ_SHIFT)) & MSCM_CP0CFG2_TMLSZ_MASK) 346 /*! @} */ 347 348 /*! @name CP0CFG3 - Processor 0 Configuration Register 3 */ 349 /*! @{ */ 350 351 #define MSCM_CP0CFG3_FPU_MASK (0x1U) 352 #define MSCM_CP0CFG3_FPU_SHIFT (0U) 353 #define MSCM_CP0CFG3_FPU_WIDTH (1U) 354 #define MSCM_CP0CFG3_FPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_FPU_SHIFT)) & MSCM_CP0CFG3_FPU_MASK) 355 356 #define MSCM_CP0CFG3_SIMD_MASK (0x2U) 357 #define MSCM_CP0CFG3_SIMD_SHIFT (1U) 358 #define MSCM_CP0CFG3_SIMD_WIDTH (1U) 359 #define MSCM_CP0CFG3_SIMD(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SIMD_SHIFT)) & MSCM_CP0CFG3_SIMD_MASK) 360 361 #define MSCM_CP0CFG3_JAZ_MASK (0x4U) 362 #define MSCM_CP0CFG3_JAZ_SHIFT (2U) 363 #define MSCM_CP0CFG3_JAZ_WIDTH (1U) 364 #define MSCM_CP0CFG3_JAZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_JAZ_SHIFT)) & MSCM_CP0CFG3_JAZ_MASK) 365 366 #define MSCM_CP0CFG3_MMU_MASK (0x8U) 367 #define MSCM_CP0CFG3_MMU_SHIFT (3U) 368 #define MSCM_CP0CFG3_MMU_WIDTH (1U) 369 #define MSCM_CP0CFG3_MMU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_MMU_SHIFT)) & MSCM_CP0CFG3_MMU_MASK) 370 371 #define MSCM_CP0CFG3_TZ_MASK (0x10U) 372 #define MSCM_CP0CFG3_TZ_SHIFT (4U) 373 #define MSCM_CP0CFG3_TZ_WIDTH (1U) 374 #define MSCM_CP0CFG3_TZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_TZ_SHIFT)) & MSCM_CP0CFG3_TZ_MASK) 375 376 #define MSCM_CP0CFG3_CMP_MASK (0x20U) 377 #define MSCM_CP0CFG3_CMP_SHIFT (5U) 378 #define MSCM_CP0CFG3_CMP_WIDTH (1U) 379 #define MSCM_CP0CFG3_CMP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_CMP_SHIFT)) & MSCM_CP0CFG3_CMP_MASK) 380 381 #define MSCM_CP0CFG3_BB_MASK (0x40U) 382 #define MSCM_CP0CFG3_BB_SHIFT (6U) 383 #define MSCM_CP0CFG3_BB_WIDTH (1U) 384 #define MSCM_CP0CFG3_BB(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_BB_SHIFT)) & MSCM_CP0CFG3_BB_MASK) 385 386 #define MSCM_CP0CFG3_SBP_MASK (0x300U) 387 #define MSCM_CP0CFG3_SBP_SHIFT (8U) 388 #define MSCM_CP0CFG3_SBP_WIDTH (2U) 389 #define MSCM_CP0CFG3_SBP(x) (((uint32_t)(((uint32_t)(x)) << MSCM_CP0CFG3_SBP_SHIFT)) & MSCM_CP0CFG3_SBP_MASK) 390 /*! @} */ 391 392 /*! @name OCMDR - On-Chip Memory Descriptor Register */ 393 /*! @{ */ 394 395 #define MSCM_OCMDR_OCM1_MASK (0x30U) 396 #define MSCM_OCMDR_OCM1_SHIFT (4U) 397 #define MSCM_OCMDR_OCM1_WIDTH (2U) 398 #define MSCM_OCMDR_OCM1(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCM1_SHIFT)) & MSCM_OCMDR_OCM1_MASK) 399 400 #define MSCM_OCMDR_OCMPU_MASK (0x1000U) 401 #define MSCM_OCMDR_OCMPU_SHIFT (12U) 402 #define MSCM_OCMDR_OCMPU_WIDTH (1U) 403 #define MSCM_OCMDR_OCMPU(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMPU_SHIFT)) & MSCM_OCMDR_OCMPU_MASK) 404 405 #define MSCM_OCMDR_OCMT_MASK (0xE000U) 406 #define MSCM_OCMDR_OCMT_SHIFT (13U) 407 #define MSCM_OCMDR_OCMT_WIDTH (3U) 408 #define MSCM_OCMDR_OCMT(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMT_SHIFT)) & MSCM_OCMDR_OCMT_MASK) 409 410 #define MSCM_OCMDR_RO_MASK (0x10000U) 411 #define MSCM_OCMDR_RO_SHIFT (16U) 412 #define MSCM_OCMDR_RO_WIDTH (1U) 413 #define MSCM_OCMDR_RO(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_RO_SHIFT)) & MSCM_OCMDR_RO_MASK) 414 415 #define MSCM_OCMDR_OCMW_MASK (0xE0000U) 416 #define MSCM_OCMDR_OCMW_SHIFT (17U) 417 #define MSCM_OCMDR_OCMW_WIDTH (3U) 418 #define MSCM_OCMDR_OCMW(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMW_SHIFT)) & MSCM_OCMDR_OCMW_MASK) 419 420 #define MSCM_OCMDR_OCMSZ_MASK (0xF000000U) 421 #define MSCM_OCMDR_OCMSZ_SHIFT (24U) 422 #define MSCM_OCMDR_OCMSZ_WIDTH (4U) 423 #define MSCM_OCMDR_OCMSZ(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMSZ_SHIFT)) & MSCM_OCMDR_OCMSZ_MASK) 424 425 #define MSCM_OCMDR_OCMSZH_MASK (0x10000000U) 426 #define MSCM_OCMDR_OCMSZH_SHIFT (28U) 427 #define MSCM_OCMDR_OCMSZH_WIDTH (1U) 428 #define MSCM_OCMDR_OCMSZH(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_OCMSZH_SHIFT)) & MSCM_OCMDR_OCMSZH_MASK) 429 430 #define MSCM_OCMDR_V_MASK (0x80000000U) 431 #define MSCM_OCMDR_V_SHIFT (31U) 432 #define MSCM_OCMDR_V_WIDTH (1U) 433 #define MSCM_OCMDR_V(x) (((uint32_t)(((uint32_t)(x)) << MSCM_OCMDR_V_SHIFT)) & MSCM_OCMDR_V_MASK) 434 /*! @} */ 435 436 /*! 437 * @} 438 */ /* end of group MSCM_Register_Masks */ 439 440 /*! 441 * @} 442 */ /* end of group MSCM_Peripheral_Access_Layer */ 443 444 #endif /* #if !defined(S32K144W_MSCM_H_) */ 445
