1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K142W_SYSTICK.h 10 * @version 1.0 11 * @date 2021-02-18 12 * @brief Peripheral Access Layer for S32K142W_SYSTICK 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K142W_SYSTICK_H_) /* Check if memory map has not been already included */ 58 #define S32K142W_SYSTICK_H_ 59 60 #include "S32K142W_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- S32_SysTick Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup S32_SysTick_Peripheral_Access_Layer S32_SysTick Peripheral Access Layer 68 * @{ 69 */ 70 71 72 /** S32_SysTick - Size of Registers Arrays */ 73 74 /** S32_SysTick - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t CSRr; /**< SysTick Control and Status Register, offset: 0x0 */ 77 __IO uint32_t RVR; /**< SysTick Reload Value Register, offset: 0x4 */ 78 __IO uint32_t CVR; /**< SysTick Current Value Register, offset: 0x8 */ 79 __I uint32_t CALIB; /**< SysTick Calibration Value Register, offset: 0xC */ 80 } S32_SysTick_Type, *S32_SysTick_MemMapPtr; 81 82 /** Number of instances of the S32_SysTick module. */ 83 #define S32_SysTick_INSTANCE_COUNT (1u) 84 85 86 /* S32_SysTick - Peripheral instance base addresses */ 87 /** Peripheral S32_SysTick base address */ 88 #define S32_SysTick_BASE (0xE000E010u) 89 /** Peripheral S32_SysTick base pointer */ 90 #define S32_SysTick ((S32_SysTick_Type *)S32_SysTick_BASE) 91 /** Array initializer of S32_SysTick peripheral base addresses */ 92 #define S32_SysTick_BASE_ADDRS { S32_SysTick_BASE } 93 /** Array initializer of S32_SysTick peripheral base pointers */ 94 #define S32_SysTick_BASE_PTRS { S32_SysTick } 95 /** Number of interrupt vector arrays for the S32_SysTick module. */ 96 #define S32_SysTick_IRQS_ARR_COUNT (1u) 97 /** Number of interrupt channels for the S32_SysTick module. */ 98 #define S32_SysTick_IRQS_CH_COUNT (1u) 99 /** Interrupt vectors for the S32_SysTick peripheral type */ 100 #define S32_SysTick_IRQS { SysTick_IRQn } 101 102 /* ---------------------------------------------------------------------------- 103 -- S32_SysTick Register Masks 104 ---------------------------------------------------------------------------- */ 105 106 /*! 107 * @addtogroup S32_SysTick_Register_Masks S32_SysTick Register Masks 108 * @{ 109 */ 110 111 /* CSR Bit Fields */ 112 #define S32_SysTick_CSR_ENABLE_MASK 0x1u 113 #define S32_SysTick_CSR_ENABLE_SHIFT 0u 114 #define S32_SysTick_CSR_ENABLE_WIDTH 1u 115 #define S32_SysTick_CSR_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_ENABLE_SHIFT))&S32_SysTick_CSR_ENABLE_MASK) 116 #define S32_SysTick_CSR_TICKINT_MASK 0x2u 117 #define S32_SysTick_CSR_TICKINT_SHIFT 1u 118 #define S32_SysTick_CSR_TICKINT_WIDTH 1u 119 #define S32_SysTick_CSR_TICKINT(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_TICKINT_SHIFT))&S32_SysTick_CSR_TICKINT_MASK) 120 #define S32_SysTick_CSR_CLKSOURCE_MASK 0x4u 121 #define S32_SysTick_CSR_CLKSOURCE_SHIFT 2u 122 #define S32_SysTick_CSR_CLKSOURCE_WIDTH 1u 123 #define S32_SysTick_CSR_CLKSOURCE(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_CLKSOURCE_SHIFT))&S32_SysTick_CSR_CLKSOURCE_MASK) 124 #define S32_SysTick_CSR_COUNTFLAG_MASK 0x10000u 125 #define S32_SysTick_CSR_COUNTFLAG_SHIFT 16u 126 #define S32_SysTick_CSR_COUNTFLAG_WIDTH 1u 127 #define S32_SysTick_CSR_COUNTFLAG(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_COUNTFLAG_SHIFT))&S32_SysTick_CSR_COUNTFLAG_MASK) 128 /* RVR Bit Fields */ 129 #define S32_SysTick_RVR_RELOAD_MASK 0xFFFFFFu 130 #define S32_SysTick_RVR_RELOAD_SHIFT 0u 131 #define S32_SysTick_RVR_RELOAD_WIDTH 24u 132 #define S32_SysTick_RVR_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_RVR_RELOAD_SHIFT))&S32_SysTick_RVR_RELOAD_MASK) 133 /* CVR Bit Fields */ 134 #define S32_SysTick_CVR_CURRENT_MASK 0xFFFFFFu 135 #define S32_SysTick_CVR_CURRENT_SHIFT 0u 136 #define S32_SysTick_CVR_CURRENT_WIDTH 24u 137 #define S32_SysTick_CVR_CURRENT(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CVR_CURRENT_SHIFT))&S32_SysTick_CVR_CURRENT_MASK) 138 /* CALIB Bit Fields */ 139 #define S32_SysTick_CALIB_TENMS_MASK 0xFFFFFFu 140 #define S32_SysTick_CALIB_TENMS_SHIFT 0u 141 #define S32_SysTick_CALIB_TENMS_WIDTH 24u 142 #define S32_SysTick_CALIB_TENMS(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CALIB_TENMS_SHIFT))&S32_SysTick_CALIB_TENMS_MASK) 143 #define S32_SysTick_CALIB_SKEW_MASK 0x40000000u 144 #define S32_SysTick_CALIB_SKEW_SHIFT 30u 145 #define S32_SysTick_CALIB_SKEW_WIDTH 1u 146 #define S32_SysTick_CALIB_SKEW(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CALIB_SKEW_SHIFT))&S32_SysTick_CALIB_SKEW_MASK) 147 #define S32_SysTick_CALIB_NOREF_MASK 0x80000000u 148 #define S32_SysTick_CALIB_NOREF_SHIFT 31u 149 #define S32_SysTick_CALIB_NOREF_WIDTH 1u 150 #define S32_SysTick_CALIB_NOREF(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CALIB_NOREF_SHIFT))&S32_SysTick_CALIB_NOREF_MASK) 151 152 /*! 153 * @} 154 */ /* end of group S32_SysTick_Register_Masks */ 155 156 157 /*! 158 * @} 159 */ /* end of group S32_SysTick_Peripheral_Access_Layer */ 160 161 #endif /* #if !defined(S32K142W_SYSTICK_H_) */ 162
