1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K142W_MCM.h 10 * @version 1.2 11 * @date 2022-02-10 12 * @brief Peripheral Access Layer for S32K142W_MCM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K142W_MCM_H_) /* Check if memory map has not been already included */ 58 #define S32K142W_MCM_H_ 59 60 #include "S32K142W_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MCM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MCM - Size of Registers Arrays */ 72 #define MCM_LMDR_COUNT 2u 73 74 /** MCM - Register Layout Typedef */ 75 typedef struct { 76 uint8_t RESERVED_0[8]; 77 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 78 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ 79 __IO uint32_t CPCR; /**< Core Platform Control Register, offset: 0xC */ 80 __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */ 81 uint8_t RESERVED_1[28]; 82 __IO uint32_t PID; /**< Process ID Register, offset: 0x30 */ 83 uint8_t RESERVED_2[12]; 84 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ 85 uint8_t RESERVED_3[956]; 86 __IO uint32_t LMDR[MCM_LMDR_COUNT]; /**< Local Memory Descriptor Register, array offset: 0x400, array step: 0x4 */ 87 __IO uint32_t LMDR2; /**< Local Memory Descriptor Register2, offset: 0x408 */ 88 uint8_t RESERVED_4[116]; 89 __IO uint32_t LMPECR; /**< LMEM Parity and ECC Control Register, offset: 0x480 */ 90 uint8_t RESERVED_5[4]; 91 __IO uint32_t LMPEIR; /**< LMEM Parity and ECC Interrupt Register, offset: 0x488 */ 92 uint8_t RESERVED_6[4]; 93 __I uint32_t LMFAR; /**< LMEM Fault Address Register, offset: 0x490 */ 94 __I uint32_t LMFATR; /**< LMEM Fault Attribute Register, offset: 0x494 */ 95 uint8_t RESERVED_7[8]; 96 __I uint32_t LMFDHR; /**< LMEM Fault Data High Register, offset: 0x4A0 */ 97 __I uint32_t LMFDLR; /**< LMEM Fault Data Low Register, offset: 0x4A4 */ 98 } MCM_Type, *MCM_MemMapPtr; 99 100 /** Number of instances of the MCM module. */ 101 #define MCM_INSTANCE_COUNT (1u) 102 103 /* MCM - Peripheral instance base addresses */ 104 /** Peripheral MCM base address */ 105 #define IP_MCM_BASE (0xE0080000u) 106 /** Peripheral MCM base pointer */ 107 #define IP_MCM ((MCM_Type *)IP_MCM_BASE) 108 /** Array initializer of MCM peripheral base addresses */ 109 #define IP_MCM_BASE_ADDRS { IP_MCM_BASE } 110 /** Array initializer of MCM peripheral base pointers */ 111 #define IP_MCM_BASE_PTRS { IP_MCM } 112 113 /* ---------------------------------------------------------------------------- 114 -- MCM Register Masks 115 ---------------------------------------------------------------------------- */ 116 117 /*! 118 * @addtogroup MCM_Register_Masks MCM Register Masks 119 * @{ 120 */ 121 122 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ 123 /*! @{ */ 124 125 #define MCM_PLASC_ASC_MASK (0xFFU) 126 #define MCM_PLASC_ASC_SHIFT (0U) 127 #define MCM_PLASC_ASC_WIDTH (8U) 128 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) 129 /*! @} */ 130 131 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ 132 /*! @{ */ 133 134 #define MCM_PLAMC_AMC_MASK (0xFFU) 135 #define MCM_PLAMC_AMC_SHIFT (0U) 136 #define MCM_PLAMC_AMC_WIDTH (8U) 137 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) 138 /*! @} */ 139 140 /*! @name CPCR - Core Platform Control Register */ 141 /*! @{ */ 142 143 #define MCM_CPCR_HLT_FSM_ST_MASK (0x3U) 144 #define MCM_CPCR_HLT_FSM_ST_SHIFT (0U) 145 #define MCM_CPCR_HLT_FSM_ST_WIDTH (2U) 146 #define MCM_CPCR_HLT_FSM_ST(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_HLT_FSM_ST_SHIFT)) & MCM_CPCR_HLT_FSM_ST_MASK) 147 148 #define MCM_CPCR_AXBS_HLT_REQ_MASK (0x4U) 149 #define MCM_CPCR_AXBS_HLT_REQ_SHIFT (2U) 150 #define MCM_CPCR_AXBS_HLT_REQ_WIDTH (1U) 151 #define MCM_CPCR_AXBS_HLT_REQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_AXBS_HLT_REQ_SHIFT)) & MCM_CPCR_AXBS_HLT_REQ_MASK) 152 153 #define MCM_CPCR_AXBS_HLTD_MASK (0x8U) 154 #define MCM_CPCR_AXBS_HLTD_SHIFT (3U) 155 #define MCM_CPCR_AXBS_HLTD_WIDTH (1U) 156 #define MCM_CPCR_AXBS_HLTD(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_AXBS_HLTD_SHIFT)) & MCM_CPCR_AXBS_HLTD_MASK) 157 158 #define MCM_CPCR_FMC_PF_IDLE_MASK (0x10U) 159 #define MCM_CPCR_FMC_PF_IDLE_SHIFT (4U) 160 #define MCM_CPCR_FMC_PF_IDLE_WIDTH (1U) 161 #define MCM_CPCR_FMC_PF_IDLE(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_FMC_PF_IDLE_SHIFT)) & MCM_CPCR_FMC_PF_IDLE_MASK) 162 163 #define MCM_CPCR_PBRIDGE_IDLE_MASK (0x40U) 164 #define MCM_CPCR_PBRIDGE_IDLE_SHIFT (6U) 165 #define MCM_CPCR_PBRIDGE_IDLE_WIDTH (1U) 166 #define MCM_CPCR_PBRIDGE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_PBRIDGE_IDLE_SHIFT)) & MCM_CPCR_PBRIDGE_IDLE_MASK) 167 168 #define MCM_CPCR_CBRR_MASK (0x200U) 169 #define MCM_CPCR_CBRR_SHIFT (9U) 170 #define MCM_CPCR_CBRR_WIDTH (1U) 171 #define MCM_CPCR_CBRR(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_CBRR_SHIFT)) & MCM_CPCR_CBRR_MASK) 172 173 #define MCM_CPCR_SRAMUAP_MASK (0x3000000U) 174 #define MCM_CPCR_SRAMUAP_SHIFT (24U) 175 #define MCM_CPCR_SRAMUAP_WIDTH (2U) 176 #define MCM_CPCR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_SRAMUAP_SHIFT)) & MCM_CPCR_SRAMUAP_MASK) 177 178 #define MCM_CPCR_SRAMUWP_MASK (0x4000000U) 179 #define MCM_CPCR_SRAMUWP_SHIFT (26U) 180 #define MCM_CPCR_SRAMUWP_WIDTH (1U) 181 #define MCM_CPCR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_SRAMUWP_SHIFT)) & MCM_CPCR_SRAMUWP_MASK) 182 183 #define MCM_CPCR_SRAMLAP_MASK (0x30000000U) 184 #define MCM_CPCR_SRAMLAP_SHIFT (28U) 185 #define MCM_CPCR_SRAMLAP_WIDTH (2U) 186 #define MCM_CPCR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_SRAMLAP_SHIFT)) & MCM_CPCR_SRAMLAP_MASK) 187 188 #define MCM_CPCR_SRAMLWP_MASK (0x40000000U) 189 #define MCM_CPCR_SRAMLWP_SHIFT (30U) 190 #define MCM_CPCR_SRAMLWP_WIDTH (1U) 191 #define MCM_CPCR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPCR_SRAMLWP_SHIFT)) & MCM_CPCR_SRAMLWP_MASK) 192 /*! @} */ 193 194 /*! @name ISCR - Interrupt Status and Control Register */ 195 /*! @{ */ 196 197 #define MCM_ISCR_FIOC_MASK (0x100U) 198 #define MCM_ISCR_FIOC_SHIFT (8U) 199 #define MCM_ISCR_FIOC_WIDTH (1U) 200 #define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK) 201 202 #define MCM_ISCR_FDZC_MASK (0x200U) 203 #define MCM_ISCR_FDZC_SHIFT (9U) 204 #define MCM_ISCR_FDZC_WIDTH (1U) 205 #define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK) 206 207 #define MCM_ISCR_FOFC_MASK (0x400U) 208 #define MCM_ISCR_FOFC_SHIFT (10U) 209 #define MCM_ISCR_FOFC_WIDTH (1U) 210 #define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK) 211 212 #define MCM_ISCR_FUFC_MASK (0x800U) 213 #define MCM_ISCR_FUFC_SHIFT (11U) 214 #define MCM_ISCR_FUFC_WIDTH (1U) 215 #define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK) 216 217 #define MCM_ISCR_FIXC_MASK (0x1000U) 218 #define MCM_ISCR_FIXC_SHIFT (12U) 219 #define MCM_ISCR_FIXC_WIDTH (1U) 220 #define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK) 221 222 #define MCM_ISCR_FIDC_MASK (0x8000U) 223 #define MCM_ISCR_FIDC_SHIFT (15U) 224 #define MCM_ISCR_FIDC_WIDTH (1U) 225 #define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK) 226 227 #define MCM_ISCR_FIOCE_MASK (0x1000000U) 228 #define MCM_ISCR_FIOCE_SHIFT (24U) 229 #define MCM_ISCR_FIOCE_WIDTH (1U) 230 #define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK) 231 232 #define MCM_ISCR_FDZCE_MASK (0x2000000U) 233 #define MCM_ISCR_FDZCE_SHIFT (25U) 234 #define MCM_ISCR_FDZCE_WIDTH (1U) 235 #define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK) 236 237 #define MCM_ISCR_FOFCE_MASK (0x4000000U) 238 #define MCM_ISCR_FOFCE_SHIFT (26U) 239 #define MCM_ISCR_FOFCE_WIDTH (1U) 240 #define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK) 241 242 #define MCM_ISCR_FUFCE_MASK (0x8000000U) 243 #define MCM_ISCR_FUFCE_SHIFT (27U) 244 #define MCM_ISCR_FUFCE_WIDTH (1U) 245 #define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK) 246 247 #define MCM_ISCR_FIXCE_MASK (0x10000000U) 248 #define MCM_ISCR_FIXCE_SHIFT (28U) 249 #define MCM_ISCR_FIXCE_WIDTH (1U) 250 #define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK) 251 252 #define MCM_ISCR_FIDCE_MASK (0x80000000U) 253 #define MCM_ISCR_FIDCE_SHIFT (31U) 254 #define MCM_ISCR_FIDCE_WIDTH (1U) 255 #define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK) 256 /*! @} */ 257 258 /*! @name PID - Process ID Register */ 259 /*! @{ */ 260 261 #define MCM_PID_PID_MASK (0xFFU) 262 #define MCM_PID_PID_SHIFT (0U) 263 #define MCM_PID_PID_WIDTH (8U) 264 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK) 265 /*! @} */ 266 267 /*! @name CPO - Compute Operation Control Register */ 268 /*! @{ */ 269 270 #define MCM_CPO_CPOREQ_MASK (0x1U) 271 #define MCM_CPO_CPOREQ_SHIFT (0U) 272 #define MCM_CPO_CPOREQ_WIDTH (1U) 273 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) 274 275 #define MCM_CPO_CPOACK_MASK (0x2U) 276 #define MCM_CPO_CPOACK_SHIFT (1U) 277 #define MCM_CPO_CPOACK_WIDTH (1U) 278 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) 279 280 #define MCM_CPO_CPOWOI_MASK (0x4U) 281 #define MCM_CPO_CPOWOI_SHIFT (2U) 282 #define MCM_CPO_CPOWOI_WIDTH (1U) 283 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) 284 /*! @} */ 285 286 /*! @name LMDR - Local Memory Descriptor Register */ 287 /*! @{ */ 288 289 #define MCM_LMDR_CF0_MASK (0xFU) 290 #define MCM_LMDR_CF0_SHIFT (0U) 291 #define MCM_LMDR_CF0_WIDTH (4U) 292 #define MCM_LMDR_CF0(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_CF0_SHIFT)) & MCM_LMDR_CF0_MASK) 293 294 #define MCM_LMDR_MT_MASK (0xE000U) 295 #define MCM_LMDR_MT_SHIFT (13U) 296 #define MCM_LMDR_MT_WIDTH (3U) 297 #define MCM_LMDR_MT(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_MT_SHIFT)) & MCM_LMDR_MT_MASK) 298 299 #define MCM_LMDR_LOCK_MASK (0x10000U) 300 #define MCM_LMDR_LOCK_SHIFT (16U) 301 #define MCM_LMDR_LOCK_WIDTH (1U) 302 #define MCM_LMDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_LOCK_SHIFT)) & MCM_LMDR_LOCK_MASK) 303 304 #define MCM_LMDR_DPW_MASK (0xE0000U) 305 #define MCM_LMDR_DPW_SHIFT (17U) 306 #define MCM_LMDR_DPW_WIDTH (3U) 307 #define MCM_LMDR_DPW(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_DPW_SHIFT)) & MCM_LMDR_DPW_MASK) 308 309 #define MCM_LMDR_WY_MASK (0xF00000U) 310 #define MCM_LMDR_WY_SHIFT (20U) 311 #define MCM_LMDR_WY_WIDTH (4U) 312 #define MCM_LMDR_WY(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_WY_SHIFT)) & MCM_LMDR_WY_MASK) 313 314 #define MCM_LMDR_LMSZ_MASK (0xF000000U) 315 #define MCM_LMDR_LMSZ_SHIFT (24U) 316 #define MCM_LMDR_LMSZ_WIDTH (4U) 317 #define MCM_LMDR_LMSZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_LMSZ_SHIFT)) & MCM_LMDR_LMSZ_MASK) 318 319 #define MCM_LMDR_LMSZH_MASK (0x10000000U) 320 #define MCM_LMDR_LMSZH_SHIFT (28U) 321 #define MCM_LMDR_LMSZH_WIDTH (1U) 322 #define MCM_LMDR_LMSZH(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_LMSZH_SHIFT)) & MCM_LMDR_LMSZH_MASK) 323 324 #define MCM_LMDR_V_MASK (0x80000000U) 325 #define MCM_LMDR_V_SHIFT (31U) 326 #define MCM_LMDR_V_WIDTH (1U) 327 #define MCM_LMDR_V(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR_V_SHIFT)) & MCM_LMDR_V_MASK) 328 /*! @} */ 329 330 /*! @name LMDR2 - Local Memory Descriptor Register2 */ 331 /*! @{ */ 332 333 #define MCM_LMDR2_CF1_MASK (0xF0U) 334 #define MCM_LMDR2_CF1_SHIFT (4U) 335 #define MCM_LMDR2_CF1_WIDTH (4U) 336 #define MCM_LMDR2_CF1(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_CF1_SHIFT)) & MCM_LMDR2_CF1_MASK) 337 338 #define MCM_LMDR2_MT_MASK (0xE000U) 339 #define MCM_LMDR2_MT_SHIFT (13U) 340 #define MCM_LMDR2_MT_WIDTH (3U) 341 #define MCM_LMDR2_MT(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_MT_SHIFT)) & MCM_LMDR2_MT_MASK) 342 343 #define MCM_LMDR2_LOCK_MASK (0x10000U) 344 #define MCM_LMDR2_LOCK_SHIFT (16U) 345 #define MCM_LMDR2_LOCK_WIDTH (1U) 346 #define MCM_LMDR2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_LOCK_SHIFT)) & MCM_LMDR2_LOCK_MASK) 347 348 #define MCM_LMDR2_DPW_MASK (0xE0000U) 349 #define MCM_LMDR2_DPW_SHIFT (17U) 350 #define MCM_LMDR2_DPW_WIDTH (3U) 351 #define MCM_LMDR2_DPW(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_DPW_SHIFT)) & MCM_LMDR2_DPW_MASK) 352 353 #define MCM_LMDR2_WY_MASK (0xF00000U) 354 #define MCM_LMDR2_WY_SHIFT (20U) 355 #define MCM_LMDR2_WY_WIDTH (4U) 356 #define MCM_LMDR2_WY(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_WY_SHIFT)) & MCM_LMDR2_WY_MASK) 357 358 #define MCM_LMDR2_LMSZ_MASK (0xF000000U) 359 #define MCM_LMDR2_LMSZ_SHIFT (24U) 360 #define MCM_LMDR2_LMSZ_WIDTH (4U) 361 #define MCM_LMDR2_LMSZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_LMSZ_SHIFT)) & MCM_LMDR2_LMSZ_MASK) 362 363 #define MCM_LMDR2_LMSZH_MASK (0x10000000U) 364 #define MCM_LMDR2_LMSZH_SHIFT (28U) 365 #define MCM_LMDR2_LMSZH_WIDTH (1U) 366 #define MCM_LMDR2_LMSZH(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_LMSZH_SHIFT)) & MCM_LMDR2_LMSZH_MASK) 367 368 #define MCM_LMDR2_V_MASK (0x80000000U) 369 #define MCM_LMDR2_V_SHIFT (31U) 370 #define MCM_LMDR2_V_WIDTH (1U) 371 #define MCM_LMDR2_V(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMDR2_V_SHIFT)) & MCM_LMDR2_V_MASK) 372 /*! @} */ 373 374 /*! @name LMPECR - LMEM Parity and ECC Control Register */ 375 /*! @{ */ 376 377 #define MCM_LMPECR_ERNCR_MASK (0x1U) 378 #define MCM_LMPECR_ERNCR_SHIFT (0U) 379 #define MCM_LMPECR_ERNCR_WIDTH (1U) 380 #define MCM_LMPECR_ERNCR(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ERNCR_SHIFT)) & MCM_LMPECR_ERNCR_MASK) 381 382 #define MCM_LMPECR_ER1BR_MASK (0x100U) 383 #define MCM_LMPECR_ER1BR_SHIFT (8U) 384 #define MCM_LMPECR_ER1BR_WIDTH (1U) 385 #define MCM_LMPECR_ER1BR(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ER1BR_SHIFT)) & MCM_LMPECR_ER1BR_MASK) 386 387 #define MCM_LMPECR_ECPR_MASK (0x100000U) 388 #define MCM_LMPECR_ECPR_SHIFT (20U) 389 #define MCM_LMPECR_ECPR_WIDTH (1U) 390 #define MCM_LMPECR_ECPR(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPECR_ECPR_SHIFT)) & MCM_LMPECR_ECPR_MASK) 391 /*! @} */ 392 393 /*! @name LMPEIR - LMEM Parity and ECC Interrupt Register */ 394 /*! @{ */ 395 396 #define MCM_LMPEIR_ENC_MASK (0xFFU) 397 #define MCM_LMPEIR_ENC_SHIFT (0U) 398 #define MCM_LMPEIR_ENC_WIDTH (8U) 399 #define MCM_LMPEIR_ENC(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_ENC_SHIFT)) & MCM_LMPEIR_ENC_MASK) 400 401 #define MCM_LMPEIR_E1B_MASK (0xFF00U) 402 #define MCM_LMPEIR_E1B_SHIFT (8U) 403 #define MCM_LMPEIR_E1B_WIDTH (8U) 404 #define MCM_LMPEIR_E1B(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_E1B_SHIFT)) & MCM_LMPEIR_E1B_MASK) 405 406 #define MCM_LMPEIR_PE_MASK (0xFF0000U) 407 #define MCM_LMPEIR_PE_SHIFT (16U) 408 #define MCM_LMPEIR_PE_WIDTH (8U) 409 #define MCM_LMPEIR_PE(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PE_SHIFT)) & MCM_LMPEIR_PE_MASK) 410 411 #define MCM_LMPEIR_PEELOC_MASK (0x1F000000U) 412 #define MCM_LMPEIR_PEELOC_SHIFT (24U) 413 #define MCM_LMPEIR_PEELOC_WIDTH (5U) 414 #define MCM_LMPEIR_PEELOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_PEELOC_SHIFT)) & MCM_LMPEIR_PEELOC_MASK) 415 416 #define MCM_LMPEIR_V_MASK (0x80000000U) 417 #define MCM_LMPEIR_V_SHIFT (31U) 418 #define MCM_LMPEIR_V_WIDTH (1U) 419 #define MCM_LMPEIR_V(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMPEIR_V_SHIFT)) & MCM_LMPEIR_V_MASK) 420 /*! @} */ 421 422 /*! @name LMFAR - LMEM Fault Address Register */ 423 /*! @{ */ 424 425 #define MCM_LMFAR_EFADD_MASK (0xFFFFFFFFU) 426 #define MCM_LMFAR_EFADD_SHIFT (0U) 427 #define MCM_LMFAR_EFADD_WIDTH (32U) 428 #define MCM_LMFAR_EFADD(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFAR_EFADD_SHIFT)) & MCM_LMFAR_EFADD_MASK) 429 /*! @} */ 430 431 /*! @name LMFATR - LMEM Fault Attribute Register */ 432 /*! @{ */ 433 434 #define MCM_LMFATR_PEFPRT_MASK (0xFU) 435 #define MCM_LMFATR_PEFPRT_SHIFT (0U) 436 #define MCM_LMFATR_PEFPRT_WIDTH (4U) 437 #define MCM_LMFATR_PEFPRT(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFPRT_SHIFT)) & MCM_LMFATR_PEFPRT_MASK) 438 439 #define MCM_LMFATR_PEFSIZE_MASK (0x70U) 440 #define MCM_LMFATR_PEFSIZE_SHIFT (4U) 441 #define MCM_LMFATR_PEFSIZE_WIDTH (3U) 442 #define MCM_LMFATR_PEFSIZE(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFSIZE_SHIFT)) & MCM_LMFATR_PEFSIZE_MASK) 443 444 #define MCM_LMFATR_PEFW_MASK (0x80U) 445 #define MCM_LMFATR_PEFW_SHIFT (7U) 446 #define MCM_LMFATR_PEFW_WIDTH (1U) 447 #define MCM_LMFATR_PEFW(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFW_SHIFT)) & MCM_LMFATR_PEFW_MASK) 448 449 #define MCM_LMFATR_PEFMST_MASK (0xFF00U) 450 #define MCM_LMFATR_PEFMST_SHIFT (8U) 451 #define MCM_LMFATR_PEFMST_WIDTH (8U) 452 #define MCM_LMFATR_PEFMST(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_PEFMST_SHIFT)) & MCM_LMFATR_PEFMST_MASK) 453 454 #define MCM_LMFATR_OVR_MASK (0x80000000U) 455 #define MCM_LMFATR_OVR_SHIFT (31U) 456 #define MCM_LMFATR_OVR_WIDTH (1U) 457 #define MCM_LMFATR_OVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFATR_OVR_SHIFT)) & MCM_LMFATR_OVR_MASK) 458 /*! @} */ 459 460 /*! @name LMFDHR - LMEM Fault Data High Register */ 461 /*! @{ */ 462 463 #define MCM_LMFDHR_PEFDH_MASK (0xFFFFFFFFU) 464 #define MCM_LMFDHR_PEFDH_SHIFT (0U) 465 #define MCM_LMFDHR_PEFDH_WIDTH (32U) 466 #define MCM_LMFDHR_PEFDH(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFDHR_PEFDH_SHIFT)) & MCM_LMFDHR_PEFDH_MASK) 467 /*! @} */ 468 469 /*! @name LMFDLR - LMEM Fault Data Low Register */ 470 /*! @{ */ 471 472 #define MCM_LMFDLR_PEFDL_MASK (0xFFFFFFFFU) 473 #define MCM_LMFDLR_PEFDL_SHIFT (0U) 474 #define MCM_LMFDLR_PEFDL_WIDTH (32U) 475 #define MCM_LMFDLR_PEFDL(x) (((uint32_t)(((uint32_t)(x)) << MCM_LMFDLR_PEFDL_SHIFT)) & MCM_LMFDLR_PEFDL_MASK) 476 /*! @} */ 477 478 /*! 479 * @} 480 */ /* end of group MCM_Register_Masks */ 481 482 /*! 483 * @} 484 */ /* end of group MCM_Peripheral_Access_Layer */ 485 486 #endif /* #if !defined(S32K142W_MCM_H_) */ 487
