1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K118.h 10 * @version 1.1 11 * @date 2022-01-24 12 * @brief Peripheral Access Layer for S32K118 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 57 /* ---------------------------------------------------------------------------- 58 -- MCU activation 59 ---------------------------------------------------------------------------- */ 60 61 /* Prevention from multiple including the same memory map */ 62 #if !defined(S32K118_COMMON_H_) /* Check if memory map has not been already included */ 63 #define S32K118_COMMON_H_ 64 #define MCU_S32K118 65 66 /* Check if another memory map has not been also included */ 67 #if (defined(MCU_ACTIVE)) 68 #error S32K118 memory map: There is already included another memory map. Only one memory map can be included. 69 #endif /* (defined(MCU_ACTIVE)) */ 70 #define MCU_ACTIVE 71 72 #include "BasicTypes.h" 73 74 /** Memory map major version (memory maps with equal major version number are 75 * compatible) */ 76 #define MCU_MEM_MAP_VERSION 0x0100U 77 /** Memory map minor version */ 78 #define MCU_MEM_MAP_VERSION_MINOR 0x0001U 79 80 /* ---------------------------------------------------------------------------- 81 -- Generic macros 82 ---------------------------------------------------------------------------- */ 83 84 /* IO definitions (access restrictions to peripheral registers) */ 85 /** 86 * IO Type Qualifiers are used 87 * \li to specify the access to peripheral variables. 88 * \li for automatic generation of peripheral register debug information. 89 */ 90 #ifndef __IO 91 #ifdef __cplusplus 92 #define __I volatile /*!< Defines 'read only' permissions */ 93 #else 94 #define __I volatile const /*!< Defines 'read only' permissions */ 95 #endif 96 #define __O volatile /*!< Defines 'write only' permissions */ 97 #define __IO volatile /*!< Defines 'read / write' permissions */ 98 #endif 99 100 101 /** 102 * @brief 32 bits memory read macro. 103 */ 104 #if !defined(REG_READ32) 105 #define REG_READ32(address) (*(volatile uint32_t*)(address)) 106 #endif 107 108 /** 109 * @brief 32 bits memory write macro. 110 */ 111 #if !defined(REG_WRITE32) 112 #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value)) 113 #endif 114 115 /** 116 * @brief 32 bits bits setting macro. 117 */ 118 #if !defined(REG_BIT_SET32) 119 #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask)) 120 #endif 121 122 /** 123 * @brief 32 bits bits clearing macro. 124 */ 125 #if !defined(REG_BIT_CLEAR32) 126 #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask)))) 127 #endif 128 129 /** 130 * @brief 32 bit clear bits and set with new value 131 * @note It is user's responsability to make sure that value has only "mask" bits set - (value&~mask)==0 132 */ 133 #if !defined(REG_RMW32) 134 #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value))))) 135 #endif 136 137 138 /* ---------------------------------------------------------------------------- 139 -- Interrupt vector numbers 140 ---------------------------------------------------------------------------- */ 141 142 /*! 143 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 144 * @{ 145 */ 146 147 /** Interrupt Number Definitions */ 148 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ 149 150 typedef enum { 151 /* Auxiliary constants */ 152 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 153 154 /* Core interrupts */ 155 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 156 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ 157 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ 158 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ 159 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ 160 161 /* Device specific interrupts */ 162 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */ 163 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ 164 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ 165 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */ 166 DMA_Error_IRQn = 4, /**< DMA error interrupt channels 0-3 */ 167 ERM_IRQn = 5, /**< ERM single bit error correction, ERM double bit error correction */ 168 RTC_IRQn = 6, /**< RTC alarm interrupt */ 169 RTC_Seconds_IRQn = 7, /**< RTC seconds interrupt */ 170 LPTMR0_IRQn = 8, /**< LPTIMER interrupt request */ 171 PORT_IRQn = 9, /**< PORTA Interrupt,PORTB Interrupt,PORTC Interrupt,PORTD Interrupt,PORTE Interrupt */ 172 CAN0_ORed_IRQn = 10, /**< CAN0 OR'ed Bus in Off State,Interrupt indicating Transmit Error Counter transition from less than 96 to greater and equal to 96,Interrupt indicating Receive Error Counter transition from less than to greater and equal to 96,Interrupt indicating that errors were detected on the CAN bus, Interrupt indicating that errors were detected on the CAN bus for FD messages in the Fast Bit Rate region,Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode */ 173 CAN0_ORed_0_31_MB_IRQn = 11, /**< CAN0 OR'ed Message buffer (0-15),CAN0 OR'ed Message buffer (16-31) */ 174 FTM0_Ch0_Ch7_IRQn = 12, /**< FTM0 Channel 0 and 7 interrupt */ 175 FTM0_Fault_IRQn = 13, /**< FTM0 Fault interrupt */ 176 FTM0_Ovf_Reload_IRQn = 14, /**< FTM0 Counter overflow and Reload interrupt */ 177 FTM1_Ch0_Ch7_IRQn = 15, /**< FTM1 Channel 0 and 7 interrupt */ 178 FTM1_Fault_IRQn = 16, /**< FTM1 Fault interrupt */ 179 FTM1_Ovf_Reload_IRQn = 17, /**< FTM1 Counter overflow and Reload interrupt */ 180 FTFC_IRQn = 18, /**< FTFC Command complete,Read collision,Double bit */ 181 PDB0_IRQn = 19, /**< PDB0 interrupt */ 182 LPIT_IRQn = 20, /**< LPIT interrupt */ 183 PMC_SCG_CMU_IRQn = 21, /**< PMC Low voltage detect interrupt, SCG bus interrupt request,CMU loss of range interrupt */ 184 WDOG_IRQn = 22, /**< Interrupt request out before WDOG reset out */ 185 RCM_IRQn = 23, /**< RCM Asynchronous Interrupt */ 186 LPI2C0_Master_Slave_IRQn = 24, /**< LPI2C0 Master and Slave Interrupt */ 187 FLEXIO_IRQn = 25, /**< FLEXIO interrupt */ 188 LPSPI0_IRQn = 26, /**< LPSPI0 Interrupt */ 189 LPSPI1_IRQn = 27, /**< LPSPI1 Interrupt */ 190 ADC0_IRQn = 28, /**< ADC0 interrupt request */ 191 CMP0_IRQn = 29, /**< CMP0 interrupt request */ 192 LPUART1_RxTx_IRQn = 30, /**< LPUART1 Transmit / Receive Interrupt / Error / Overrun */ 193 LPUART0_RxTx_IRQn = 31 /**< LPUART0 Transmit / Receive Interrupt / Error / Overrun */ 194 } IRQn_Type; 195 196 /*! 197 * @} 198 */ /* end of group Interrupt_vector_numbers */ 199 200 201 /* ---------------------------------------------------------------------------- 202 -- Cortex M0 Core Configuration 203 ---------------------------------------------------------------------------- */ 204 205 /*! 206 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 207 * @{ 208 */ 209 210 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ 211 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 212 #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ 213 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ 214 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 215 216 217 /*! 218 * @} 219 */ /* end of group Cortex_Core_Configuration */ 220 221 222 /* ---------------------------------------------------------------------------- 223 -- SDK Compatibility 224 ---------------------------------------------------------------------------- */ 225 226 /*! 227 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 228 * @{ 229 */ 230 231 /* No SDK compatibility issues. */ 232 233 /*! 234 * @} 235 */ /* end of group SDK_Compatibility_Symbols */ 236 237 238 #endif /* #if !defined(S32K118_COMMON_H_) */ 239 240
