1 /*
2 * Copyright 2021-2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef FSL_TRDC_H_
9 #define FSL_TRDC_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup trdc
15 * @{
16 */
17
18 /******************************************************************************
19 * Definitions
20 *****************************************************************************/
21 #define FSL_TRDC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
22
23 /* Hardware configuration definitions */
24 /*!
25 * @brief TRDC hardware configuration.
26 */
27 typedef struct _trdc_hardware_config
28 {
29 uint8_t masterNumber; /*!< Number of bus masters. */
30 uint8_t domainNumber; /*!< Number of domains. */
31 uint8_t mbcNumber; /*!< Number of MBCs. */
32 uint8_t mrcNumber; /*!< Number of MRCs. */
33 } trdc_hardware_config_t;
34
35 /*!
36 * @brief Hardware configuration of the two slave memories within each MBC(memory block checker).
37 */
38 typedef struct _trdc_slave_memory_hardware_config
39 {
40 uint32_t blockNum; /*!< Number of blocks. */
41 uint32_t blockSize; /*!< Block size. */
42 } trdc_slave_memory_hardware_config_t;
43
44 /* Master domain assignment definitions */
45 /*!
46 * @brief TRDC domain ID select method, the register bit TRDC_MDA_W0_0_DFMT0[DIDS], used for
47 * domain hit evaluation.
48 */
49 typedef enum _trdc_did_sel
50 {
51 kTRDC_DidMda, /*!< Use MDAn[2:0] as DID. */
52 kTRDC_DidInput, /*!< Use the input DID (DID_in) as DID. */
53 kTRDC_DidMdaAndInput, /*!< Use MDAn[2] concatenated with DID_in[1:0] as DID. */
54 kTRDC_DidReserved /*!< Reserved. */
55 } trdc_did_sel_t;
56
57 /*!
58 * @brief TRDC secure attribute, the register bit TRDC_MDA_W0_0_DFMT0[SA], used for
59 * bus master domain assignment.
60 */
61 typedef enum _trdc_secure_attr
62 {
63 kTRDC_ForceSecure, /*!< Force the bus attribute for this master to secure. */
64 kTRDC_ForceNonSecure, /*!< Force the bus attribute for this master to non-secure. */
65 kTRDC_MasterSecure, /*!< Use the bus master's secure/nonsecure attribute directly. */
66 kTRDC_MasterSecure1, /*!< Use the bus master's secure/nonsecure attribute directly. */
67 } trdc_secure_attr_t;
68
69 #if defined(FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT) && (FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT > 1)
70 /*!
71 * @brief The configuration of domain hit evaluation of PID.
72 */
73 typedef enum _trdc_pid_domain_hit_config
74 {
75 kTRDC_pidDomainHitNone0, /*!< No PID is included in the domain hit evaluation. */
76 kTRDC_pidDomainHitNone1, /*!< No PID is included in the domain hit evaluation. */
77 kTRDC_pidDomainHitInclusive, /*!< Domain hit when all the bits in PID is masked by the pidMask. */
78 kTRDC_pidDomainHitExclusive, /*!< Domain hit when not all the bits in PID is masked by the pidMask. */
79 } trdc_pid_domain_hit_config_t;
80 #endif
81
82 /*!
83 * @brief Domain assignment for the processor bus master.
84 */
85 typedef struct _trdc_processor_domain_assignment
86 {
87 uint32_t domainId : 4U; /*!< Domain ID. */
88 uint32_t domainIdSelect : 2U; /*!< Domain ID select method, see @ref trdc_did_sel_t. */
89 #if defined(FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT) && (FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT > 1)
90 uint32_t pidDomainHitConfig : 2U; /*!< The configuration of the domain hit evaluation for PID, see @ref
91 trdc_pid_domain_hit_config_t. */
92 uint32_t pidMask : 6U; /*!< The mask combined with PID, so multiple PID can be included as part of the domain hit
93 determination. Set to 0 to disable. */
94 #else
95 uint32_t : 8U; /*!< Reserved. */
96 #endif
97 uint32_t secureAttr : 2U; /*!< Secure attribute, see @ref trdc_secure_attr_t. */
98 #if defined(FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT) && (FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT > 1)
99 uint32_t pid : 6U; /*!< The process identifier, combined with pidMask to form the domain hit determination. */
100 uint32_t : 8U; /*!< Reserved. */
101 #else
102 uint32_t : 14U; /*!< Reserved. */
103 #endif
104 uint32_t lock : 1U; /*!< Lock the register. */
105 uint32_t : 1U; /*!< Reserved. */
106 } trdc_processor_domain_assignment_t;
107
108 /*!
109 * @brief TRDC privileged attribute, the register bit TRDC_MDA_W0_x_DFMT1[PA], used for non-processor
110 * bus master domain assignment.
111 */
112 typedef enum _trdc_privilege_attr
113 {
114 kTRDC_ForceUser, /*!< Force the bus attribute for this master to user. */
115 kTRDC_ForcePrivilege, /*!< Force the bus attribute for this master to privileged. */
116 kTRDC_MasterPrivilege, /*!< Use the bus master's attribute directly. */
117 kTRDC_MasterPrivilege1, /*!< Use the bus master's attribute directly. */
118 } trdc_privilege_attr_t;
119
120 /*!
121 * @brief Domain assignment for the non-processor bus master.
122 */
123 typedef struct _trdc_non_processor_domain_assignment
124 {
125 uint32_t domainId : 4U; /*!< Domain ID. */
126 uint32_t privilegeAttr : 2U; /*!< Privileged attribute, see @ref trdc_privilege_attr_t. */
127 uint32_t secureAttr : 2U; /*!< Secure attribute, see @ref trdc_secure_attr_t. */
128 uint32_t bypassDomainId : 1U; /*!< Bypass domain ID. */
129 uint32_t : 21U; /*!< Reserved. */
130 uint32_t lock : 1U; /*!< Lock the register. */
131 uint32_t : 1U; /*!< Reserved. */
132 } trdc_non_processor_domain_assignment_t;
133
134 #if defined(FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT) && (FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT > 1)
135 /*!
136 * @brief PID lock configuration.
137 */
138 typedef enum _trdc_pid_lock
139 {
140 kTRDC_PidUnlocked0, /*!< The PID value can be updated by any secure priviledged write. */
141 kTRDC_PidUnlocked1, /*!< The PID value can be updated by any secure priviledged write. */
142 kTRDC_PidUnlocked2, /*!< The PID value can be updated by any secure priviledged write from the bus master that first
143 configured this register. */
144 kTRDC_PidLocked, /*!< The PID value is locked until next reset. */
145 } trdc_pid_lock_t;
146
147 /*!
148 * @brief Process identifier(PID) configuration for processor cores.
149 */
150 typedef struct _trdc_pid_config
151 {
152 uint32_t pid : 6U; /*!< The process identifier of the executing task. The highest bit can be used to define
153 secure/nonsecure attribute of the task. */
154 uint32_t : 23U; /*!< Reserved. */
155 uint32_t lock : 2U; /*!< How to lock the register, see @ref trdc_pid_lock_t. */
156 uint32_t : 1U; /*!< Reserved. */
157 } trdc_pid_config_t;
158 #endif
159
160 /* TZ-M congiguration definitions */
161 /*!
162 * @brief IDAU(Implementation-Defined Attribution Unit) configuration for TZ-M function control.
163 */
164 typedef struct _trdc_idau_config
165 {
166 uint32_t : 8U; /*!< Reserved. */
167 uint32_t lockSecureVTOR : 1U; /*!< Disable writes to secure VTOR(Vector Table Offset Register). */
168 uint32_t lockNonsecureVTOR : 1U; /*!< Disable writes to non-secure VTOR, Application interrupt and Reset Control
169 Registers. */
170 uint32_t lockSecureMPU : 1U; /*!< Disable writes to secure MPU(Memory Protection Unit) from software or from a debug
171 agent connected to the processor in Secure state. */
172 uint32_t lockNonsecureMPU : 1U; /*!< Disable writes to non-secure MPU(Memory Protection Unit) from software or from
173 a debug agent connected to the processor. */
174 uint32_t lockSAU : 1U; /*!< Disable writes to SAU(Security Attribution Unit) registers. */
175 uint32_t : 19U; /*!< Reserved. */
176 } trdc_idau_config_t;
177
178 /* FLW(Flash Logical Window) configuration definitions */
179 /*!
180 * @brief FLW(Flash Logical Window) configuration.
181 */
182 typedef struct _trdc_flw_config
183 {
184 uint16_t blockCount; /*!< Block count of the Flash Logic Window in 32KByte blocks. */
185 uint32_t arrayBaseAddr; /*!< Flash array base address of the Flash Logical Window. */
186 bool lock; /*!< Disable writes to FLW registers. */
187 bool enable; /*!< Enable FLW function. */
188 } trdc_flw_config_t;
189
190 /* Domain error check and clear definitions */
191 /*!
192 * @brief TRDC controller definition for domain error check. Each TRDC instance may have different
193 * MRC or MBC count, call TRDC_GetHardwareConfig to get the actual count.
194 */
195 typedef enum _trdc_controller
196 {
197 kTRDC_MemBlockController0 = 0U, /*!< Memory block checker 0. */
198 kTRDC_MemBlockController1 = 1U, /*!< Memory block checker 1. */
199 kTRDC_MemBlockController2 = 2U, /*!< Memory block checker 2. */
200 kTRDC_MemBlockController3 = 3U, /*!< Memory block checker 3. */
201 kTRDC_MemRegionChecker0 = 4U, /*!< Memory region checker 0. */
202 kTRDC_MemRegionChecker1 = 5U, /*!< Memory region checker 1. */
203 kTRDC_MemRegionChecker2 = 6U, /*!< Memory region checker 2. */
204 kTRDC_MemRegionChecker3 = 7U, /*!< Memory region checker 3. */
205 kTRDC_MemRegionChecker4 = 8U, /*!< Memory region checker 4. */
206 kTRDC_MemRegionChecker5 = 9U, /*!< Memory region checker 5. */
207 kTRDC_MemRegionChecker6 = 10U, /*!< Memory region checker 6. */
208 } trdc_controller_t;
209
210 /*!
211 * @brief TRDC domain error state definition TRDC_MBCn_DERR_W1[EST] or TRDC_MRCn_DERR_W1[EST].
212 */
213 typedef enum _trdc_error_state
214 {
215 kTRDC_ErrorStateNone = 0x00U, /*!< No access violation detected. */
216 kTRDC_ErrorStateNone1 = 0x01U, /*!< No access violation detected. */
217 kTRDC_ErrorStateSingle = 0x02U, /*!< Single access violation detected. */
218 kTRDC_ErrorStateMulti = 0x03U /*!< Multiple access violation detected. */
219 } trdc_error_state_t;
220
221 /*!
222 * @brief TRDC domain error attribute definition TRDC_MBCn_DERR_W1[EATR] or TRDC_MRCn_DERR_W1[EATR].
223 */
224 typedef enum _trdc_error_attr
225 {
226 kTRDC_ErrorSecureUserInst = 0x00U, /*!< Secure user mode, instruction fetch access. */
227 kTRDC_ErrorSecureUserData = 0x01U, /*!< Secure user mode, data access. */
228 kTRDC_ErrorSecurePrivilegeInst = 0x02U, /*!< Secure privileged mode, instruction fetch access. */
229 kTRDC_ErrorSecurePrivilegeData = 0x03U, /*!< Secure privileged mode, data access. */
230 kTRDC_ErrorNonSecureUserInst = 0x04U, /*!< NonSecure user mode, instruction fetch access. */
231 kTRDC_ErrorNonSecureUserData = 0x05U, /*!< NonSecure user mode, data access. */
232 kTRDC_ErrorNonSecurePrivilegeInst = 0x06U, /*!< NonSecure privileged mode, instruction fetch access. */
233 kTRDC_ErrorNonSecurePrivilegeData = 0x07U /*!< NonSecure privileged mode, data access. */
234 } trdc_error_attr_t;
235
236 /*!
237 * @brief TRDC domain error access type definition TRDC_DERR_W1_n[ERW].
238 */
239 typedef enum _trdc_error_type
240 {
241 kTRDC_ErrorTypeRead = 0x00U, /*!< Error occurs on read reference. */
242 kTRDC_ErrorTypeWrite = 0x01U /*!< Error occurs on write reference. */
243 } trdc_error_type_t;
244
245 /*!
246 * @brief TRDC domain error definition.
247 */
248 typedef struct _trdc_domain_error
249 {
250 trdc_controller_t controller; /*!< Which controller captured access violation. */
251 uint32_t address; /*!< Access address that generated access violation. */
252 trdc_error_state_t errorState; /*!< Error state. */
253 trdc_error_attr_t errorAttr; /*!< Error attribute. */
254 trdc_error_type_t errorType; /*!< Error type. */
255 uint8_t errorPort; /*!< Error port. */
256 uint8_t domainId; /*!< Domain ID. */
257 uint8_t slaveMemoryIdx; /*!< The slave memory index. Only apply when violation in MBC. */
258 } trdc_domain_error_t;
259
260 /* Common definitions for MBC/MRC configuration */
261 /*!
262 * @brief Memory access control configuration for MBC/MRC.
263 */
264 typedef struct _trdc_memory_access_control_config
265 {
266 uint32_t nonsecureUsrX : 1U; /*!< Allow nonsecure user execute access. */
267 uint32_t nonsecureUsrW : 1U; /*!< Allow nonsecure user write access. */
268 uint32_t nonsecureUsrR : 1U; /*!< Allow nonsecure user read access. */
269 uint32_t : 1U; /*!< Reserved. */
270 uint32_t nonsecurePrivX : 1U; /*!< Allow nonsecure privilege execute access. */
271 uint32_t nonsecurePrivW : 1U; /*!< Allow nonsecure privilege write access. */
272 uint32_t nonsecurePrivR : 1U; /*!< Allow nonsecure privilege read access. */
273 uint32_t : 1U; /*!< Reserved. */
274 uint32_t secureUsrX : 1U; /*!< Allow secure user execute access. */
275 uint32_t secureUsrW : 1U; /*!< Allow secure user write access. */
276 uint32_t secureUsrR : 1U; /*!< Allow secure user read access. */
277 uint32_t : 1U; /*!< Reserved. */
278 uint32_t securePrivX : 1U; /*!< Allownsecure privilege execute access. */
279 uint32_t securePrivW : 1U; /*!< Allownsecure privilege write access. */
280 uint32_t securePrivR : 1U; /*!< Allownsecure privilege read access. */
281 uint32_t : 16U; /*!< Reserved. */
282 uint32_t lock : 1U; /*!< Lock the configuration until next reset, only apply to access control register 0. */
283 } trdc_memory_access_control_config_t;
284
285 /*! @brief The region descriptor enumeration, used to form a mask to set/clear the NSE bits for one or several regions.
286 */
287 enum _trdc_region_descriptor
288 {
289 kTRDC_RegionDescriptor0 = (1U << 0U), /*!< Region descriptor 0. */
290 kTRDC_RegionDescriptor1 = (1U << 1U), /*!< Region descriptor 1. */
291 kTRDC_RegionDescriptor2 = (1U << 2U), /*!< Region descriptor 2. */
292 kTRDC_RegionDescriptor3 = (1U << 3U), /*!< Region descriptor 3. */
293 kTRDC_RegionDescriptor4 = (1U << 4U), /*!< Region descriptor 4. */
294 kTRDC_RegionDescriptor5 = (1U << 5U), /*!< Region descriptor 5. */
295 kTRDC_RegionDescriptor6 = (1U << 6U), /*!< Region descriptor 6. */
296 kTRDC_RegionDescriptor7 = (1U << 7U), /*!< Region descriptor 7. */
297 kTRDC_RegionDescriptor8 = (1U << 8U), /*!< Region descriptor 8. */
298 kTRDC_RegionDescriptor9 = (1U << 9U), /*!< Region descriptor 9. */
299 kTRDC_RegionDescriptor10 = (1U << 10U), /*!< Region descriptor 10. */
300 kTRDC_RegionDescriptor11 = (1U << 11U), /*!< Region descriptor 11. */
301 kTRDC_RegionDescriptor12 = (1U << 12U), /*!< Region descriptor 12. */
302 kTRDC_RegionDescriptor13 = (1U << 13U), /*!< Region descriptor 13. */
303 kTRDC_RegionDescriptor14 = (1U << 14U), /*!< Region descriptor 14. */
304 kTRDC_RegionDescriptor15 = (1U << 15U), /*!< Region descriptor 15. */
305 };
306
307 /* MRC configuration definitions */
308 /*! @brief The MRC domain enumeration, used to form a mask to enable/disable the update or clear all NSE bits of one or
309 * several domains. */
310 enum _trdc_MRC_domain
311 {
312 kTRDC_MrcDomain0 = (1U << 0U), /*!< Domain 0. */
313 kTRDC_MrcDomain1 = (1U << 1U), /*!< Domain 1. */
314 kTRDC_MrcDomain2 = (1U << 2U), /*!< Domain 2. */
315 kTRDC_MrcDomain3 = (1U << 3U), /*!< Domain 3. */
316 kTRDC_MrcDomain4 = (1U << 4U), /*!< Domain 4. */
317 kTRDC_MrcDomain5 = (1U << 5U), /*!< Domain 5. */
318 kTRDC_MrcDomain6 = (1U << 6U), /*!< Domain 6. */
319 kTRDC_MrcDomain7 = (1U << 7U), /*!< Domain 7. */
320 kTRDC_MrcDomain8 = (1U << 8U), /*!< Domain 8. */
321 kTRDC_MrcDomain9 = (1U << 9U), /*!< Domain 9. */
322 kTRDC_MrcDomain10 = (1U << 10U), /*!< Domain 10. */
323 kTRDC_MrcDomain11 = (1U << 11U), /*!< Domain 11. */
324 kTRDC_MrcDomain12 = (1U << 12U), /*!< Domain 12. */
325 kTRDC_MrcDomain13 = (1U << 13U), /*!< Domain 13. */
326 kTRDC_MrcDomain14 = (1U << 14U), /*!< Domain 14. */
327 kTRDC_MrcDomain15 = (1U << 15U), /*!< Domain 15. */
328 };
329
330 /*!
331 * @brief The configuration of each region descriptor per domain per MRC instance.
332 */
333 typedef struct _trdc_mrc_region_descriptor_config
334 {
335 uint8_t memoryAccessControlSelect; /*!< Select one of the 8 access control policies for this region, for
336 access cotrol policies see @ref trdc_memory_access_control_config_t. */
337 uint32_t startAddr; /*!< Physical start address. */
338 bool valid; /*!< Lock the register. */
339 bool nseEnable; /*!< Enable non-secure accesses and disable secure accesses. */
340 uint32_t endAddr; /*!< Physical start address. */
341 uint8_t mrcIdx; /*!< The index of the MRC for this configuration to take effect. */
342 uint8_t domainIdx; /*!< The index of the domain for this configuration to take effect. */
343 uint8_t regionIdx; /*!< The index of the region for this configuration to take effect. */
344 } trdc_mrc_region_descriptor_config_t;
345
346 /* MBC configuration definitions */
347 /*!
348 * @brief The configuration of MBC NSE update.
349 */
350 #if defined(FSL_FEATURE_TRDC_DOMAIN_COUNT) && (FSL_FEATURE_TRDC_DOMAIN_COUNT > 0x8U)
351 typedef struct _trdc_mbc_nse_update_config
352 {
353 uint32_t autoIncrement : 1U; /*!< Whether to increment the word index after current word is updated using this
354 configuration. */
355 uint32_t : 1U; /*!< Reserved. */
356 uint32_t wordIdx : 4U; /*!< MBC configuration word index to be updated. */
357 uint32_t : 2U; /*!< Reserved. */
358 uint32_t memorySelect : 4U; /*!< Bit mask of the selected memory to be updated. @ref _trdc_MBC_memory. */
359 uint32_t : 4U; /*!< Reserved. */
360 uint32_t domianSelect : 16U; /*!< Bit mask of the selected domain to be updated. @ref _trdc_MBC_domain. */
361 } trdc_mbc_nse_update_config_t;
362 #else
363 typedef struct _trdc_mbc_nse_update_config
364 {
365 uint32_t : 2U; /*!< Reserved. */
366 uint32_t wordIdx : 4U; /*!< MBC configuration word index to be updated. */
367 uint32_t : 2U; /*!< Reserved. */
368 uint32_t memorySelect : 4U; /*!< Bit mask of the selected memory to be updated. @ref _trdc_MBC_memory. */
369 uint32_t : 4U; /*!< Reserved. */
370 uint32_t domianSelect : 8U; /*!< Bit mask of the selected domain to be updated. @ref _trdc_MBC_domain. */
371 uint32_t : 7U; /*!< Reserved. */
372 uint32_t autoIncrement : 1U; /*!< Whether to increment the word index after current word is updated using this
373 configuration. */
374 } trdc_mbc_nse_update_config_t;
375 #endif
376
377 /*! @brief The MBC domain enumeration, used to form a mask to enable/disable the update or clear NSE bits of one or
378 * several domains. */
379 enum _trdc_MBC_domain
380 {
381 kTRDC_MbcDomain0 = (1U << 0U), /*!< Domain 0. */
382 kTRDC_MbcDomain1 = (1U << 1U), /*!< Domain 1. */
383 kTRDC_MbcDomain2 = (1U << 2U), /*!< Domain 2. */
384 kTRDC_MbcDomain3 = (1U << 3U), /*!< Domain 3. */
385 kTRDC_MbcDomain4 = (1U << 4U), /*!< Domain 4. */
386 kTRDC_MbcDomain5 = (1U << 5U), /*!< Domain 5. */
387 kTRDC_MbcDomain6 = (1U << 6U), /*!< Domain 6. */
388 kTRDC_MbcDomain7 = (1U << 7U), /*!< Domain 7. */
389 };
390
391 /*! @brief The MBC slave memory enumeration, used to form a mask to enable/disable the update or clear NSE bits of one
392 * or several memory block. */
393 enum _trdc_MBC_memory
394 {
395 kTRDC_MbcSlaveMemory0 = (1U << 0U), /*!< Memory 0. */
396 kTRDC_MbcSlaveMemory1 = (1U << 1U), /*!< Memory 1. */
397 kTRDC_MbcSlaveMemory2 = (1U << 2U), /*!< Memory 2. */
398 kTRDC_MbcSlaveMemory3 = (1U << 3U), /*!< Memory 3. */
399 };
400
401 /*! @brief The MBC bit enumeration, used to form a mask to set/clear configured words' NSE. */
402 enum _trdc_MBC_bit
403 {
404 kTRDC_MbcBit0 = (1U << 0U), /*!< Bit 0. */
405 kTRDC_MbcBit1 = (1U << 1U), /*!< Bit 1. */
406 kTRDC_MbcBit2 = (1U << 2U), /*!< Bit 2. */
407 kTRDC_MbcBit3 = (1U << 3U), /*!< Bit 3. */
408 kTRDC_MbcBit4 = (1U << 4U), /*!< Bit 4. */
409 kTRDC_MbcBit5 = (1U << 5U), /*!< Bit 5. */
410 kTRDC_MbcBit6 = (1U << 6U), /*!< Bit 6. */
411 kTRDC_MbcBit7 = (1U << 7U), /*!< Bit 7. */
412 kTRDC_MbcBit8 = (1U << 8U), /*!< Bit 8. */
413 kTRDC_MbcBit9 = (1U << 9U), /*!< Bit 9. */
414 kTRDC_MbcBit10 = (1U << 10U), /*!< Bit 10. */
415 kTRDC_MbcBit11 = (1U << 11U), /*!< Bit 11. */
416 kTRDC_MbcBit12 = (1U << 12U), /*!< Bit 12. */
417 kTRDC_MbcBit13 = (1U << 13U), /*!< Bit 13. */
418 kTRDC_MbcBit14 = (1U << 14U), /*!< Bit 14. */
419 kTRDC_MbcBit15 = (1U << 15U), /*!< Bit 15. */
420 kTRDC_MbcBit16 = (1U << 16U), /*!< Bit 16. */
421 kTRDC_MbcBit17 = (1U << 17U), /*!< Bit 17. */
422 kTRDC_MbcBit18 = (1U << 18U), /*!< Bit 18. */
423 kTRDC_MbcBit19 = (1U << 19U), /*!< Bit 19. */
424 kTRDC_MbcBit20 = (1U << 20U), /*!< Bit 20. */
425 kTRDC_MbcBit21 = (1U << 21U), /*!< Bit 21. */
426 kTRDC_MbcBit22 = (1U << 22U), /*!< Bit 22. */
427 kTRDC_MbcBit23 = (1U << 23U), /*!< Bit 23. */
428 kTRDC_MbcBit24 = (1U << 24U), /*!< Bit 24. */
429 kTRDC_MbcBit25 = (1U << 25U), /*!< Bit 25. */
430 kTRDC_MbcBit26 = (1U << 26U), /*!< Bit 26. */
431 kTRDC_MbcBit27 = (1U << 27U), /*!< Bit 27. */
432 kTRDC_MbcBit28 = (1U << 28U), /*!< Bit 28. */
433 kTRDC_MbcBit29 = (1U << 29U), /*!< Bit 29. */
434 kTRDC_MbcBit30 = (1U << 30U), /*!< Bit 30. */
435 kTRDC_MbcBit31 = (1U << 31U), /*!< Bit 31. */
436 };
437
438 /*!
439 * @brief The configuration of each memory block per domain per MBC instance.
440 */
441 typedef struct _trdc_mbc_memory_block_config
442 {
443 uint32_t memoryAccessControlSelect : 3U; /*!< Select one of the 8 access control policies for this memory block, for
444 access cotrol policies see @ref trdc_memory_access_control_config_t. */
445 uint32_t nseEnable : 1U; /*!< Enable non-secure accesses and disable secure accesses. */
446 uint32_t mbcIdx : 4U; /*!< The index of the MBC for this configuration to take effect. */
447 uint32_t domainIdx : 8U; /*!< The index of the domain for this configuration to take effect. */
448 uint32_t slaveMemoryIdx : 8U; /*!< The index of the slave memory for this configuration to take effect. */
449 uint32_t memoryBlockIdx : 8U; /*!< The index of the memory block for this configuration to take effect. */
450 } trdc_mbc_memory_block_config_t;
451
452 /*******************************************************************************
453 * API
454 ******************************************************************************/
455
456 #if defined(__cplusplus)
457 extern "C" {
458 #endif
459
460 /*!
461 * @name Initialization and deinitialization
462 * @{
463 */
464 /*!
465 * @brief Initializes the TRDC module.
466 *
467 * This function enables the TRDC clock.
468 *
469 * @param base TRDC peripheral base address.
470 */
471 void TRDC_Init(TRDC_Type *base);
472
473 /*!
474 * @brief De-initializes the TRDC module.
475 *
476 * This function disables the TRDC clock.
477 *
478 * @param base TRDC peripheral base address.
479 */
480 void TRDC_Deinit(TRDC_Type *base);
481 /*! @} */
482
483 /*!
484 * @name Hardware configuration
485 * @{
486 */
487 /*!
488 * @brief Gets the domain ID of the current bus master.
489 *
490 * @param base TRDC peripheral base address.
491 * @return Domain ID of current bus master.
492 */
TRDC_GetCurrentMasterDomainId(TRDC_Type * base)493 static inline uint8_t TRDC_GetCurrentMasterDomainId(TRDC_Type *base)
494 {
495 return (uint8_t)((base->TRDC_HWCFG1 & TRDC_TRDC_HWCFG1_DID_MASK) >> TRDC_TRDC_HWCFG1_DID_SHIFT);
496 }
497
498 /*!
499 * @brief Gets the TRDC hardware configuration.
500 *
501 * This function gets the TRDC hardware configurations, including number of bus
502 * masters, number of domains, number of MRCs and number of PACs.
503 *
504 * @param base TRDC peripheral base address.
505 * @param config Pointer to the structure to get the configuration.
506 */
507 void TRDC_GetHardwareConfig(TRDC_Type *base, trdc_hardware_config_t *config);
508 /*! @} */
509
510 /*!
511 * @name Master domain assignment
512 * @{
513 */
514 /*!
515 * @brief Sets the TRDC DAC(Domain Assignment Controllers) global valid.
516 *
517 * Once enabled, it will remain enabled until next reset.
518 *
519 * @param base TRDC peripheral base address.
520 */
TRDC_SetDacGlobalValid(TRDC_Type * base)521 static inline void TRDC_SetDacGlobalValid(TRDC_Type *base)
522 {
523 base->TRDC_CR |= TRDC_TRDC_CR_GVLDM_MASK;
524 }
525
526 #if defined(FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT) && (FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT > 1)
527 /*!
528 * @brief Locks the bus master domain assignment register.
529 *
530 * This function locks the master domain assignment. After it is locked, the register can't be changed
531 * until next reset.
532 *
533 * @param base TRDC peripheral base address.
534 * @param master Which master to configure, refer to trdcx_master_t in processor header file, x is trdc instance.
535 * @param regNum Which register to configure, processor master can have more than one register for the MDAC
536 * configuration.
537 * @param assignIndex Which assignment register to lock.
538 */
TRDC_LockMasterDomainAssignment(TRDC_Type * base,uint8_t master,uint8_t regNum)539 static inline void TRDC_LockMasterDomainAssignment(TRDC_Type *base, uint8_t master, uint8_t regNum)
540 #else
541 /*!
542 * @brief Locks the bus master domain assignment register.
543 *
544 * This function locks the master domain assignment. After it is locked, the register can't be changed
545 * until next reset.
546 *
547 * @param base TRDC peripheral base address.
548 * @param master Which master to configure.
549 * @param assignIndex Which assignment register to lock.
550 */
551 static inline void TRDC_LockMasterDomainAssignment(TRDC_Type *base, uint8_t master)
552 #endif
553 {
554 /* Make sure in the master range. */
555 assert((uint32_t)master < ((base->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT));
556 #if defined(FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT) && (FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT > 1)
557 if (0U == (base->DACFG[master] & TRDC_DACFG_NCM_MASK))
558 {
559 base->MDA_DFMT0[master].MDA_W_DFMT0[regNum] |= TRDC_MDA_W_DFMT0_LK1_MASK;
560 }
561 else
562 {
563 base->MDA_DFMT1[master].MDA_W_DFMT1[0] |= TRDC_MDA_W_DFMT1_LK1_MASK;
564 }
565 #else
566 /* Non-processor master */
567 if ((uint8_t)master != 0U)
568 {
569 base->MDA_W0_DFMT1[(uint8_t)(master - 1U)].MDA_W0_x_DFMT1 |= TRDC_MDA_W0_x_DFMT1_LK1_MASK;
570 }
571 /* Processor master */
572 else
573 {
574 base->MDA_W0_0_DFMT0 |= TRDC_MDA_W0_0_DFMT0_LK1_MASK;
575 }
576 #endif
577 }
578
579 #if defined(FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT) && (FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT > 1)
580 /*!
581 * @brief Sets the master domain assignment as valid or invalid.
582 *
583 * This function sets the master domain assignment as valid or invalid.
584 *
585 * @param base TRDC peripheral base address.
586 * @param master Which master to configure.
587 * @param regNum Which register to configure, processor master can have more than one register for the MDAC
588 * configuration.
589 * @param assignIndex Index for the domain assignment register.
590 * @param valid True to set valid, false to set invalid.
591 */
TRDC_SetMasterDomainAssignmentValid(TRDC_Type * base,uint8_t master,uint8_t regNum,bool valid)592 static inline void TRDC_SetMasterDomainAssignmentValid(TRDC_Type *base, uint8_t master, uint8_t regNum, bool valid)
593 #else
594 /*!
595 * @brief Sets the master domain assignment as valid or invalid.
596 *
597 * This function sets the master domain assignment as valid or invalid.
598 *
599 * @param base TRDC peripheral base address.
600 * @param master Which master to configure.
601 * @param assignIndex Index for the domain assignment register.
602 * @param valid True to set valid, false to set invalid.
603 */
604 static inline void TRDC_SetMasterDomainAssignmentValid(TRDC_Type *base, uint8_t master, bool valid)
605 #endif
606 {
607 /* Make sure in the master range. */
608 assert((uint32_t)master < ((base->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT));
609 #if defined(FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT) && (FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT > 1)
610 if (valid)
611 {
612 if (0U == (base->DACFG[master] & TRDC_DACFG_NCM_MASK))
613 {
614 base->MDA_DFMT0[master].MDA_W_DFMT0[regNum] |= TRDC_MDA_W_DFMT0_VLD_MASK;
615 }
616 else
617 {
618 base->MDA_DFMT1[master].MDA_W_DFMT1[0] |= TRDC_MDA_W_DFMT1_VLD_MASK;
619 }
620 }
621 else
622 {
623 if (0U == (base->DACFG[master] & TRDC_DACFG_NCM_MASK))
624 {
625 base->MDA_DFMT0[master].MDA_W_DFMT0[regNum] &= ~TRDC_MDA_W_DFMT0_VLD_MASK;
626 }
627 else
628 {
629 base->MDA_DFMT1[master].MDA_W_DFMT1[0] &= ~TRDC_MDA_W_DFMT1_VLD_MASK;
630 }
631 }
632 #else
633 /* Non-processor master */
634 if ((uint8_t)master != 0U)
635 {
636 if (valid)
637 {
638 base->MDA_W0_DFMT1[(uint8_t)(master - 1U)].MDA_W0_x_DFMT1 |= TRDC_MDA_W0_x_DFMT1_VLD_MASK;
639 }
640 else
641 {
642 base->MDA_W0_DFMT1[(uint8_t)(master - 1U)].MDA_W0_x_DFMT1 &= ~TRDC_MDA_W0_x_DFMT1_VLD_MASK;
643 }
644 }
645 /* Processor master */
646 else
647 {
648 if (valid)
649 {
650 base->MDA_W0_0_DFMT0 |= TRDC_MDA_W0_0_DFMT0_VLD_MASK;
651 }
652 else
653 {
654 base->MDA_W0_0_DFMT0 &= ~TRDC_MDA_W0_0_DFMT0_VLD_MASK;
655 }
656 }
657 #endif
658 }
659
660 /*!
661 * @brief Gets the default master domain assignment for the processor bus master.
662 *
663 * This function gets the default master domain assignment for the processor bus master.
664 * It should only be used for the processor bus masters, such as CORE0. This function
665 * sets the assignment as follows:
666 *
667 * @code
668 * assignment->domainId = 0U;
669 * assignment->domainIdSelect = kTRDC_DidMda;
670 * assignment->lock = 0U;
671 * @endcode
672 *
673 * @param domainAssignment Pointer to the assignment structure.
674 */
675 void TRDC_GetDefaultProcessorDomainAssignment(trdc_processor_domain_assignment_t *domainAssignment);
676
677 /*!
678 * @brief Gets the default master domain assignment for non-processor bus master.
679 *
680 * This function gets the default master domain assignment for non-processor bus master.
681 * It should only be used for the non-processor bus masters, such as DMA. This function
682 * sets the assignment as follows:
683 *
684 * @code
685 * assignment->domainId = 0U;
686 * assignment->privilegeAttr = kTRDC_ForceUser;
687 * assignment->secureAttr = kTRDC_ForceSecure;
688 * assignment->bypassDomainId = 0U;
689 * assignment->lock = 0U;
690 * @endcode
691 *
692 * @param domainAssignment Pointer to the assignment structure.
693 */
694 void TRDC_GetDefaultNonProcessorDomainAssignment(trdc_non_processor_domain_assignment_t *domainAssignment);
695
696 #if defined(FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT) && (FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT > 1)
697 /*!
698 * brief Sets the current Process identifier(PID) for processor core.
699 *
700 * Each processor has a corresponding process identifier (PID) which can be used to group tasks into different domains.
701 * Secure privileged software saves and restores the PID as part of any context switch.
702 *
703 * param base TRDC peripheral base address.
704 * param master Which processor master to configure, refer to trdc_master_t in processor header file.
705 * param pidConfig Pointer to the configuration structure.
706 */
707 void TRDC_SetPid(TRDC_Type *base, uint8_t master, const trdc_pid_config_t *pidConfig);
708
709 /*!
710 * @brief Gets the bit map of the bus master(s) that is(are) sourcing a PID register.
711 *
712 * This function sets the non-processor master domain assignment as valid.
713 *
714 * @param base TRDC peripheral base address.
715 * @return the bit map of the master(s). Bit 1 sets indicates bus master 1.
716 */
TRDC_GetActiveMasterPidMap(TRDC_Type * base)717 static inline uint64_t TRDC_GetActiveMasterPidMap(TRDC_Type *base)
718 {
719 return ((uint64_t)base->TRDC_HWCFG3 << 32U) | (uint64_t)base->TRDC_HWCFG2;
720 }
721
722 /*!
723 * @brief Sets the processor bus master domain assignment.
724 *
725 * This function sets the processor master domain assignment as valid.
726 * One bus master might have multiple domain assignment registers. The parameter
727 * \p assignIndex specifies which assignment register to set.
728 *
729 * Example: Set domain assignment for core 0.
730 *
731 * @code
732 * trdc_processor_domain_assignment_t processorAssignment;
733 *
734 * TRDC_GetDefaultProcessorDomainAssignment(&processorAssignment);
735 *
736 * processorAssignment.domainId = 0;
737 * processorAssignment.xxx = xxx;
738 * TRDC_SetMasterDomainAssignment(TRDC, &processorAssignment);
739 * @endcode
740 *
741 * @param base TRDC peripheral base address.
742 * @param master Which master to configure, refer to trdc_master_t in processor header file.
743 * @param regNum Which register to configure, processor master can have more than one register for the MDAC
744 * configuration.
745 * @param domainAssignment Pointer to the assignment structure.
746 */
747 void TRDC_SetProcessorDomainAssignment(TRDC_Type *base,
748 uint8_t master,
749 uint8_t regNum,
750 const trdc_processor_domain_assignment_t *domainAssignment);
751 #else
752 /*!
753 * @brief Sets the processor bus master domain assignment.
754 *
755 * This function sets the processor master domain assignment as valid.
756 * One bus master might have multiple domain assignment registers. The parameter
757 * \p assignIndex specifies which assignment register to set.
758 *
759 * Example: Set domain assignment for core 0.
760 *
761 * @code
762 * trdc_processor_domain_assignment_t processorAssignment;
763 *
764 * TRDC_GetDefaultProcessorDomainAssignment(&processorAssignment);
765 *
766 * processorAssignment.domainId = 0;
767 * processorAssignment.xxx = xxx;
768 * TRDC_SetMasterDomainAssignment(TRDC, &processorAssignment);
769 * @endcode
770 *
771 * @param base TRDC peripheral base address.
772 * @param domainAssignment Pointer to the assignment structure.
773 */
774 void TRDC_SetProcessorDomainAssignment(TRDC_Type *base, const trdc_processor_domain_assignment_t *domainAssignment);
775 #endif
776
777 #if defined(FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT) && (FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT > 1)
778 /*!
779 * @brief Enables the processor bus master domain assignment.
780 *
781 * @param base TRDC peripheral base address.
782 * @param master Which master to configure, refer to trdcx_master_t in processor header file, x is trdc instance.
783 * @param regNum Which register to configure, processor master can have more than one register.
784 * @param enable True to enable, false to disable.
785 */
TRDC_EnableProcessorDomainAssignment(TRDC_Type * base,uint8_t master,uint8_t regNum,bool enable)786 static inline void TRDC_EnableProcessorDomainAssignment(TRDC_Type *base, uint8_t master, uint8_t regNum, bool enable)
787 #else
788 /*!
789 * @brief Enables the processor bus master domain assignment.
790 *
791 * @param base TRDC peripheral base address.
792 * @param enable True to enable, false to disable.
793 */
794 static inline void TRDC_EnableProcessorDomainAssignment(TRDC_Type *base, bool enable)
795 #endif
796 {
797 #if defined(FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT) && (FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT > 1)
798 /* Make sure the master number does not exceed the max master count. */
799 assert(master < ((base->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT));
800 /* Make sure the master is a processor master. */
801 assert(0U == (base->DACFG[master] & TRDC_DACFG_NCM_MASK));
802 if (enable)
803 {
804 base->MDA_DFMT0[master].MDA_W_DFMT0[regNum] |= TRDC_MDA_W_DFMT0_VLD_MASK;
805 }
806 else
807 {
808 base->MDA_DFMT0[master].MDA_W_DFMT0[regNum] &= ~TRDC_MDA_W_DFMT0_VLD_MASK;
809 }
810 #else
811 if (enable)
812 {
813 base->MDA_W0_0_DFMT0 |= TRDC_MDA_W0_0_DFMT0_VLD_MASK;
814 }
815 else
816 {
817 base->MDA_W0_0_DFMT0 &= ~TRDC_MDA_W0_0_DFMT0_VLD_MASK;
818 }
819 #endif
820 }
821
822 /*!
823 * @brief Sets the non-processor bus master domain assignment.
824 *
825 * This function sets the non-processor master domain assignment as valid.
826 * One bus master might have multiple domain assignment registers. The parameter
827 * \p assignIndex specifies which assignment register to set.
828 *
829 * Example: Set domain assignment for DMA0.
830 * @code
831 * trdc_non_processor_domain_assignment_t nonProcessorAssignment;
832 *
833 * TRDC_GetDefaultNonProcessorDomainAssignment(&nonProcessorAssignment);
834 * nonProcessorAssignment.domainId = 1;
835 * nonProcessorAssignment.xxx = xxx;
836 *
837 * TRDC_SetMasterDomainAssignment(TRDC, kTrdcMasterDma0, 0U, &nonProcessorAssignment);
838 * @endcode
839 *
840 * @param base TRDC peripheral base address.
841 * @param master Which master to configure, refer to trdc_master_t in processor header file.
842 * @param domainAssignment Pointer to the assignment structure.
843 */
844 void TRDC_SetNonProcessorDomainAssignment(TRDC_Type *base,
845 uint8_t master,
846 const trdc_non_processor_domain_assignment_t *domainAssignment);
847
848 /*! @} */
849
850 /*!
851 * @name TZ-M congiguration
852 * @{
853 */
854 /*!
855 * @brief Gets the default IDAU(Implementation-Defined Attribution Unit) configuration.
856 *
857 * @code
858 * config->lockSecureVTOR = false;
859 * config->lockNonsecureVTOR = false;
860 * config->lockSecureMPU = false;
861 * config->lockNonsecureMPU = false;
862 * config->lockSAU = false;
863 * @endcode
864 *
865 * @param domainAssignment Pointer to the configuration structure.
866 */
867 void TRDC_GetDefaultIDAUConfig(trdc_idau_config_t *idauConfiguration);
868
869 /*!
870 * @brief Sets the IDAU(Implementation-Defined Attribution Unit) control configuration.
871 *
872 * Example: Lock the secure and non-secure MPU registers.
873 *
874 * @code
875 * trdc_idau_config_t idauConfiguration;
876 *
877 * TRDC_GetDefaultIDAUConfig(&idauConfiguration);
878 *
879 * idauConfiguration.lockSecureMPU = true;
880 * idauConfiguration.lockNonsecureMPU = true;
881 * TRDC_SetIDAU(TRDC, &idauConfiguration);
882 * @endcode
883 *
884 * @param base TRDC peripheral base address.
885 * @param domainAssignment Pointer to the configuration structure.
886 */
887 void TRDC_SetIDAU(TRDC_Type *base, const trdc_idau_config_t *idauConfiguration);
888 /*! @} */
889
890 /*!
891 * @name FLW(Flash Logical Window) configuration
892 * @{
893 */
894 /*!
895 * @brief Enables/disables the FLW(flash logical window) function.
896 *
897 * @param base TRDC peripheral base address.
898 * @param enable True to enable, false to disable.
899 */
TRDC_EnableFlashLogicalWindow(TRDC_Type * base,bool enable)900 static inline void TRDC_EnableFlashLogicalWindow(TRDC_Type *base, bool enable)
901 {
902 if (enable)
903 {
904 base->TRDC_FLW_CTL |= TRDC_TRDC_FLW_CTL_V_MASK;
905 }
906 else
907 {
908 base->TRDC_FLW_CTL &= ~TRDC_TRDC_FLW_CTL_V_MASK;
909 }
910 }
911
912 /*!
913 * @brief Locks FLW registers. Once locked the registers can noy be updated until next reset.
914 *
915 * @param base TRDC peripheral base address.
916 */
TRDC_LockFlashLogicalWindow(TRDC_Type * base)917 static inline void TRDC_LockFlashLogicalWindow(TRDC_Type *base)
918 {
919 base->TRDC_FLW_CTL |= TRDC_TRDC_FLW_CTL_LK_MASK;
920 }
921
922 /*!
923 * @brief Gets the FLW physical base address.
924 *
925 * @param base TRDC peripheral base address.
926 * @return Physical address of the FLW function.
927 */
TRDC_GetFlashLogicalWindowPbase(TRDC_Type * base)928 static inline uint32_t TRDC_GetFlashLogicalWindowPbase(TRDC_Type *base)
929 {
930 return base->TRDC_FLW_PBASE;
931 }
932
933 /*!
934 * @brief Sets the FLW size.
935 *
936 * @param base TRDC peripheral base address.
937 * @param size Size of the FLW in unit of 32k bytes.
938 */
TRDC_GetSetFlashLogicalWindowSize(TRDC_Type * base,uint16_t size)939 static inline void TRDC_GetSetFlashLogicalWindowSize(TRDC_Type *base, uint16_t size)
940 {
941 base->TRDC_FLW_BCNT = size;
942 }
943
944 /*!
945 * @brief Gets the default FLW(Flsh Logical Window) configuration.
946 *
947 * @code
948 * config->blockCount = false;
949 * config->arrayBaseAddr = false;
950 * config->lock = false;
951 * config->enable = false;
952 * @endcode
953 *
954 * @param flwConfiguration Pointer to the configuration structure.
955 */
956 void TRDC_GetDefaultFlashLogicalWindowConfig(trdc_flw_config_t *flwConfiguration);
957
958 /*!
959 * @brief Sets the FLW function's configuration.
960 *
961 * @code
962 * trdc_flw_config_t flwConfiguration;
963 *
964 * TRDC_GetDefaultIDAUConfig(&flwConfiguration);
965 *
966 * flwConfiguration.blockCount = 32U;
967 * flwConfiguration.arrayBaseAddr = 0xXXXXXXXX;
968 * TRDC_SetIDAU(TRDC, &flwConfiguration);
969 * @endcode
970 *
971 * @param base TRDC peripheral base address.
972 * @param flwConfiguration Pointer to the configuration structure.
973 */
974 void TRDC_SetFlashLogicalWindow(TRDC_Type *base, const trdc_flw_config_t *flwConfiguration);
975 /*! @} */
976
977 /*!
978 * @name Domain error check and clear
979 * @{
980 */
981 /*!
982 * @brief Gets and clears the first domain error of the current domain.
983 *
984 * This function gets the first access violation information for the current domain
985 * and clears the pending flag. There might be multiple access violations pending
986 * for the current domain. This function only processes the first error.
987 *
988 * @param base TRDC peripheral base address.
989 * @param error Pointer to the error information.
990 * @return If the access violation is captured, this function returns the kStatus_Success.
991 * The error information can be obtained from the parameter error. If no
992 * access violation is captured, this function returns the kStatus_NoData.
993 */
994 status_t TRDC_GetAndClearFirstDomainError(TRDC_Type *base, trdc_domain_error_t *error);
995
996 /*!
997 * @brief Gets and clears the first domain error of the specific domain.
998 *
999 * This function gets the first access violation information for the specific domain
1000 * and clears the pending flag. There might be multiple access violations pending
1001 * for the current domain. This function only processes the first error.
1002 *
1003 * @param base TRDC peripheral base address.
1004 * @param error Pointer to the error information.
1005 * @param domainId The error of which domain to get and clear.
1006 * @return If the access violation is captured, this function returns the kStatus_Success.
1007 * The error information can be obtained from the parameter error. If no
1008 * access violation is captured, this function returns the kStatus_NoData.
1009 */
1010 status_t TRDC_GetAndClearFirstSpecificDomainError(TRDC_Type *base, trdc_domain_error_t *error, uint8_t domainId);
1011 /*! @} */
1012
1013 /*!
1014 * @name MRC configuration
1015 * @{
1016 */
1017 /*!
1018 * @brief Sets the TRDC MRC(Memory Region Checkers) global valid.
1019 *
1020 * Once enabled, it will remain enabled until next reset.
1021 *
1022 * @param base TRDC peripheral base address.
1023 */
TRDC_SetMrcGlobalValid(TRDC_Type * base)1024 static inline void TRDC_SetMrcGlobalValid(TRDC_Type *base)
1025 {
1026 base->TRDC_CR |= TRDC_TRDC_CR_GVLDR_MASK;
1027 }
1028
1029 /*!
1030 * @brief Gets the TRDC MRC(Memory Region Checkers) region number valid.
1031 *
1032 * @param base TRDC peripheral base address.
1033 * @return the region number of the given MRC instance
1034 */
TRDC_GetMrcRegionNumber(TRDC_Type * base,uint8_t mrcIdx)1035 static inline uint8_t TRDC_GetMrcRegionNumber(TRDC_Type *base, uint8_t mrcIdx)
1036 {
1037 return (uint8_t)((base->MRC_INDEX[mrcIdx].MRC_GLBCFG & TRDC_MRC_GLBCFG_NRGNS_MASK) >> TRDC_MRC_GLBCFG_NRGNS_SHIFT);
1038 }
1039
1040 /*!
1041 * @brief Sets the memory access configuration for one of the access control register of one MRC.
1042 *
1043 * Example: Enable the secure operations and lock the configuration for MRC0 region 1.
1044 *
1045 * @code
1046 * trdc_memory_access_control_config_t config;
1047 *
1048 * config.securePrivX = true;
1049 * config.securePrivW = true;
1050 * config.securePrivR = true;
1051 * config.lock = true;
1052 * TRDC_SetMrcMemoryAccess(TRDC, &config, 0, 1);
1053 * @endcode
1054 *
1055 * @param base TRDC peripheral base address.
1056 * @param config Pointer to the configuration structure.
1057 * @param mrcIdx MRC index.
1058 * @param regIdx Register number.
1059 */
1060 void TRDC_MrcSetMemoryAccessConfig(TRDC_Type *base,
1061 const trdc_memory_access_control_config_t *config,
1062 uint8_t mrcIdx,
1063 uint8_t regIdx);
1064
1065 /*!
1066 * @brief Enables the update of the selected domians.
1067 *
1068 * After the domians' update are enabled, their regions' NSE bits can be set or clear.
1069 *
1070 * @param base TRDC peripheral base address.
1071 * @param mrcIdx MRC index.
1072 * @param domianMask Bit mask of the domains to be enabled.
1073 * @param enable True to enable, false to disable.
1074 */
1075 void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domianMask, bool enable);
1076
1077 /*!
1078 * @brief Sets the NSE bits of the selected regions for domains.
1079 *
1080 * This function sets the NSE bits for the selected regions for the domains whose update are enabled.
1081 *
1082 * @param base TRDC peripheral base address.
1083 * @param mrcIdx MRC index.
1084 * @param regionMask Bit mask of the regions whose NSE bits to set.
1085 */
1086 void TRDC_MrcRegionNseSet(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask);
1087
1088 /*!
1089 * @brief Clears the NSE bits of the selected regions for domains.
1090 *
1091 * This function clears the NSE bits for the selected regions for the domains whose update are enabled.
1092 *
1093 * @param base TRDC peripheral base address.
1094 * @param mrcIdx MRC index.
1095 * @param regionMask Bit mask of the regions whose NSE bits to clear.
1096 */
1097 void TRDC_MrcRegionNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask);
1098
1099 /*!
1100 * @brief Clears the NSE bits for all the regions of the selected domains.
1101 *
1102 * This function clears the NSE bits for all regions of selected domains whose update are enabled.
1103 *
1104 * @param base TRDC peripheral base address.
1105 * @param mrcIdx MRC index.
1106 * @param domainMask Bit mask of the domians whose NSE bits to clear.
1107 */
1108 void TRDC_MrcDomainNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask);
1109
1110 /*!
1111 * @brief Sets the configuration for one of the region descriptor per domain per MRC instnce.
1112 *
1113 * This function sets the configuration for one of the region descriptor, including the start
1114 * and end address of the region, memory access control policy and valid.
1115 *
1116 * @param base TRDC peripheral base address.
1117 * @param config Pointer to region descriptor configuration structure.
1118 */
1119 void TRDC_MrcSetRegionDescriptorConfig(TRDC_Type *base, const trdc_mrc_region_descriptor_config_t *config);
1120 /*! @} */
1121
1122 /*!
1123 * @name MBC configuration
1124 * @{
1125 */
1126 /*!
1127 * @brief Sets the TRDC MBC(Memory Block Checkers) global valid.
1128 *
1129 * Once enabled, it will remain enabled until next reset.
1130 *
1131 * @param base TRDC peripheral base address.
1132 */
TRDC_SetMbcGlobalValid(TRDC_Type * base)1133 static inline void TRDC_SetMbcGlobalValid(TRDC_Type *base)
1134 {
1135 base->TRDC_CR |= TRDC_TRDC_CR_GVLDB_MASK;
1136 }
1137
1138 /*!
1139 * @brief Gets the hardware configuration of the one of two slave memories within each MBC(memory block checker).
1140 *
1141 * @param base TRDC peripheral base address.
1142 * @param config Pointer to the structure to get the configuration.
1143 * @param mbcIdx MBC number.
1144 * @param slvIdx Slave number.
1145 */
1146 void TRDC_GetMbcHardwareConfig(TRDC_Type *base,
1147 trdc_slave_memory_hardware_config_t *config,
1148 uint8_t mbcIdx,
1149 uint8_t slvIdx);
1150
1151 /*!
1152 * @brief Sets the NSR update configuration for one of the MBC instance.
1153 *
1154 * After set the NSE configuration, the configured memory area can be updateby NSE set/clear.
1155 *
1156 * @param base TRDC peripheral base address.
1157 * @param config Pointer to NSE update configuration structure.
1158 * @param mbcIdx MBC index.
1159 */
1160 void TRDC_MbcSetNseUpdateConfig(TRDC_Type *base, const trdc_mbc_nse_update_config_t *config, uint8_t mbcIdx);
1161
1162 /*!
1163 * @brief Sets the NSE bits of the selected configuration words according to NSE update configuration.
1164 *
1165 * This function sets the NSE bits of the word for the configured regio, memory.
1166 *
1167 * @param base TRDC peripheral base address.
1168 * @param mbcIdx MBC index.
1169 * @param bitMask Mask of the bits whose NSE bits to set.
1170 */
1171 void TRDC_MbcWordNseSet(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask);
1172
1173 /*!
1174 * @brief Clears the NSE bits of the selected configuration words according to NSE update configuration.
1175 *
1176 * This function sets the NSE bits of the word for the configured regio, memory.
1177 *
1178 * @param base TRDC peripheral base address.
1179 * @param mbcIdx MBC index.
1180 * @param bitMask Mask of the bits whose NSE bits to clear.
1181 */
1182 void TRDC_MbcWordNseClear(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask);
1183
1184 /*!
1185 * @brief Clears all configuration words' NSE bits of the selected domain and memory.
1186 *
1187 * @param base TRDC peripheral base address.
1188 * @param mbcIdx MBC index.
1189 * @param domainMask Mask of the domains whose NSE bits to clear, 0b110 means clear domain 1&2.
1190 * @param slaveMask Mask of the slaves whose NSE bits to clear, 0x11 means clear all slave 0&1's NSE bits.
1191 */
1192 void TRDC_MbcNseClearAll(TRDC_Type *base, uint8_t mbcIdx, uint16_t domainMask, uint8_t slave);
1193
1194 /*!
1195 * @brief Sets the memory access configuration for one of the region descriptor of one MBC.
1196 *
1197 * Example: Enable the secure operations and lock the configuration for MRC0 region 1.
1198 *
1199 * @code
1200 * trdc_memory_access_control_config_t config;
1201 *
1202 * config.securePrivX = true;
1203 * config.securePrivW = true;
1204 * config.securePrivR = true;
1205 * config.lock = true;
1206 * TRDC_SetMbcMemoryAccess(TRDC, &config, 0, 1);
1207 * @endcode
1208 *
1209 * @param base TRDC peripheral base address.
1210 * @param config Pointer to the configuration structure.
1211 * @param mbcIdx MBC index.
1212 * @param rgdIdx Region descriptor number.
1213 */
1214 void TRDC_MbcSetMemoryAccessConfig(TRDC_Type *base,
1215 const trdc_memory_access_control_config_t *config,
1216 uint8_t mbcIdx,
1217 uint8_t rgdIdx);
1218
1219 /*!
1220 * @brief Sets the configuration for one of the memory block per domain per MBC instnce.
1221 *
1222 * This function sets the configuration for one of the memory block, including the memory access
1223 * control policy and nse enable.
1224 *
1225 * @param base TRDC peripheral base address.
1226 * @param config Pointer to memory block configuration structure.
1227 */
1228 void TRDC_MbcSetMemoryBlockConfig(TRDC_Type *base, const trdc_mbc_memory_block_config_t *config);
1229 /*! @} */
1230
1231 #if defined(__cplusplus)
1232 }
1233 #endif
1234
1235 /*!
1236 * @}
1237 */
1238
1239 #endif /* FSL_TRDC_H_ */
1240
