1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_mmdvsq.h"
10
11 /* Component ID definition, used by tools. */
12 #ifndef FSL_COMPONENT_ID
13 #define FSL_COMPONENT_ID "platform.drivers.mmdvsq"
14 #endif
15
16 /*******************************************************************************
17 * Code
18 ******************************************************************************/
19
20 /*!
21 * brief Performs the MMDVSQ division operation and returns the remainder.
22 *
23 * param base MMDVSQ peripheral address
24 * param dividend Dividend value
25 * param divisor Divisor value
26 * param isUnsigned Mode of unsigned divide
27 * - true unsigned divide
28 * - false signed divide
29 *
30 */
MMDVSQ_GetDivideRemainder(MMDVSQ_Type * base,int32_t dividend,int32_t divisor,bool isUnsigned)31 int32_t MMDVSQ_GetDivideRemainder(MMDVSQ_Type *base, int32_t dividend, int32_t divisor, bool isUnsigned)
32 {
33 uint32_t temp = 0;
34
35 temp = base->CSR;
36 temp &= ~(MMDVSQ_CSR_USGN_MASK | MMDVSQ_CSR_REM_MASK);
37 /* Prepare setting for calculation */
38 temp |= MMDVSQ_CSR_USGN(isUnsigned) | MMDVSQ_CSR_REM(true);
39 /* Write setting to CSR register */
40 base->CSR = temp;
41 /* Write dividend to DEND register */
42 base->DEND = (uint32_t)dividend;
43 /* Write divisor to DSOR register and start calculation if Fast-Start is enabled */
44 base->DSOR = (uint32_t)divisor;
45 /* Start calculation by writing 1 to SRT bit in case Fast-Start is disabled */
46 base->CSR |= MMDVSQ_CSR_SRT_MASK;
47 /* Return remainder, if divide-by-zero is enabled and occurred, reading from
48 * RES result is error terminated */
49 return (int32_t)base->RES;
50 }
51
52 /*!
53 * brief Performs the MMDVSQ division operation and returns the quotient.
54 *
55 * param base MMDVSQ peripheral address
56 * param dividend Dividend value
57 * param divisor Divisor value
58 * param isUnsigned Mode of unsigned divide
59 * - true unsigned divide
60 * - false signed divide
61 *
62 */
MMDVSQ_GetDivideQuotient(MMDVSQ_Type * base,int32_t dividend,int32_t divisor,bool isUnsigned)63 int32_t MMDVSQ_GetDivideQuotient(MMDVSQ_Type *base, int32_t dividend, int32_t divisor, bool isUnsigned)
64 {
65 uint32_t temp = 0;
66
67 temp = base->CSR;
68 temp &= ~(MMDVSQ_CSR_USGN_MASK | MMDVSQ_CSR_REM_MASK);
69 /* Prepare setting for calculation */
70 temp |= MMDVSQ_CSR_USGN(isUnsigned) | MMDVSQ_CSR_REM(false);
71 /* Write setting mode to CSR register */
72 base->CSR = temp;
73 /* Write dividend to DEND register */
74 base->DEND = (uint32_t)dividend;
75 /* Write divisor to DSOR register and start calculation when Fast-Start is enabled */
76 base->DSOR = (uint32_t)divisor;
77 /* Start calculation by writing 1 to SRT bit in case Fast-Start is disabled */
78 base->CSR |= MMDVSQ_CSR_SRT_MASK;
79 /* Return quotient, if divide-by-zero is enabled and occurred, reading from
80 * RES result is error terminated */
81 return (int32_t)base->RES;
82 }
83
84 /*!
85 * brief Performs the MMDVSQ square root operation.
86 *
87 * This function performs the MMDVSQ square root operation and returns the square root
88 * result of a given radicand value.
89 *
90 * param base MMDVSQ peripheral address
91 * param radicand Radicand value
92 *
93 */
MMDVSQ_Sqrt(MMDVSQ_Type * base,uint32_t radicand)94 uint16_t MMDVSQ_Sqrt(MMDVSQ_Type *base, uint32_t radicand)
95 {
96 /* Write radicand to RCND register , and start calculation */
97 base->RCND = radicand;
98 /* Return result */
99 return (uint16_t)base->RES;
100 }
101
