1 /*
2 * Copyright 2016-2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef FSL_CACHE_H_
9 #define FSL_CACHE_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup cache_lmem
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*! @{ */
24 /*! @brief cache driver version. */
25 #define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 6))
26 /*! @} */
27
28 /*! @brief code bus cache line size is equal to system bus line size, so the unified I/D cache line size equals too. */
29 #define L1CODEBUSCACHE_LINESIZE_BYTE \
30 FSL_FEATURE_L1ICACHE_LINESIZE_BYTE /*!< The code bus CACHE line size is 16B = 128b. */
31 #define L1SYSTEMBUSCACHE_LINESIZE_BYTE \
32 L1CODEBUSCACHE_LINESIZE_BYTE /*!< The system bus CACHE line size is 16B = 128b. */
33
34 /*******************************************************************************
35 * API
36 ******************************************************************************/
37
38 #if defined(__cplusplus)
39 extern "C" {
40 #endif
41
42 #if (FSL_FEATURE_SOC_LMEM_COUNT == 1)
43 /*!
44 * @name cache control for L1 cache (local memory controller for code/system bus cache)
45 *@{
46 */
47
48 /*!
49 * @brief Enables the processor code bus cache.
50 *
51 */
52 void L1CACHE_EnableCodeCache(void);
53
54 /*!
55 * @brief Disables the processor code bus cache.
56 *
57 */
58 void L1CACHE_DisableCodeCache(void);
59
60 /*!
61 * @brief Invalidates the processor code bus cache.
62 *
63 */
64 void L1CACHE_InvalidateCodeCache(void);
65
66 /*!
67 * @brief Invalidates processor code bus cache by range.
68 *
69 * @param address The physical address of cache.
70 * @param size_byte size of the memory to be invalidated.
71 * @note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE".
72 * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if
73 * startAddr is not aligned. For the size_byte, application should make sure the
74 * alignment or make sure the right operation order if the size_byte is not aligned.
75 */
76 void L1CACHE_InvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte);
77
78 /*!
79 * @brief Cleans the processor code bus cache.
80 *
81 */
82 void L1CACHE_CleanCodeCache(void);
83
84 /*!
85 * @brief Cleans processor code bus cache by range.
86 *
87 * @param address The physical address of cache.
88 * @param size_byte size of the memory to be cleaned.
89 * @note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE".
90 * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if
91 * startAddr is not aligned. For the size_byte, application should make sure the
92 * alignment or make sure the right operation order if the size_byte is not aligned.
93 */
94 void L1CACHE_CleanCodeCacheByRange(uint32_t address, uint32_t size_byte);
95
96 /*!
97 * @brief Cleans and invalidates the processor code bus cache.
98 *
99 */
100 void L1CACHE_CleanInvalidateCodeCache(void);
101
102 /*!
103 * @brief Cleans and invalidate processor code bus cache by range.
104 *
105 * @param address The physical address of cache.
106 * @param size_byte size of the memory to be Cleaned and Invalidated.
107 * @note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE".
108 * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if
109 * startAddr is not aligned. For the size_byte, application should make sure the
110 * alignment or make sure the right operation order if the size_byte is not aligned.
111 */
112 void L1CACHE_CleanInvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte);
113
114 /*!
115 * @brief Enables/disables the processor code bus write buffer.
116 *
117 * @param enable The enable or disable flag.
118 * true - enable the code bus write buffer.
119 * false - disable the code bus write buffer.
120 */
L1CACHE_EnableCodeCacheWriteBuffer(bool enable)121 static inline void L1CACHE_EnableCodeCacheWriteBuffer(bool enable)
122 {
123 if (enable)
124 {
125 LMEM->PCCCR |= LMEM_PCCCR_ENWRBUF_MASK;
126 }
127 else
128 {
129 LMEM->PCCCR &= ~LMEM_PCCCR_ENWRBUF_MASK;
130 }
131 }
132
133 #if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
134 /*!
135 * @brief Enables the processor system bus cache.
136 *
137 */
138 void L1CACHE_EnableSystemCache(void);
139
140 /*!
141 * @brief Disables the processor system bus cache.
142 *
143 */
144 void L1CACHE_DisableSystemCache(void);
145
146 /*!
147 * @brief Invalidates the processor system bus cache.
148 *
149 */
150 void L1CACHE_InvalidateSystemCache(void);
151
152 /*!
153 * @brief Invalidates processor system bus cache by range.
154 *
155 * @param address The physical address of cache.
156 * @param size_byte size of the memory to be invalidated.
157 * @note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE".
158 * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if
159 * startAddr is not aligned. For the size_byte, application should make sure the
160 * alignment or make sure the right operation order if the size_byte is not aligned.
161 */
162 void L1CACHE_InvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte);
163
164 /*!
165 * @brief Cleans the processor system bus cache.
166 *
167 */
168 void L1CACHE_CleanSystemCache(void);
169
170 /*!
171 * @brief Cleans processor system bus cache by range.
172 *
173 * @param address The physical address of cache.
174 * @param size_byte size of the memory to be cleaned.
175 * @note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE".
176 * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if
177 * startAddr is not aligned. For the size_byte, application should make sure the
178 * alignment or make sure the right operation order if the size_byte is not aligned.
179 */
180 void L1CACHE_CleanSystemCacheByRange(uint32_t address, uint32_t size_byte);
181
182 /*!
183 * @brief Cleans and invalidates the processor system bus cache.
184 *
185 */
186 void L1CACHE_CleanInvalidateSystemCache(void);
187
188 /*!
189 * @brief Cleans and Invalidates processor system bus cache by range.
190 *
191 * @param address The physical address of cache.
192 * @param size_byte size of the memory to be Clean and Invalidated.
193 * @note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE".
194 * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if
195 * startAddr is not aligned. For the size_byte, application should make sure the
196 * alignment or make sure the right operation order if the size_byte is not aligned.
197 */
198 void L1CACHE_CleanInvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte);
199
200 /*!
201 * @brief Enables/disables the processor system bus write buffer.
202 *
203 * @param enable The enable or disable flag.
204 * true - enable the code bus write buffer.
205 * false - disable the code bus write buffer.
206 */
L1CACHE_EnableSystemCacheWriteBuffer(bool enable)207 static inline void L1CACHE_EnableSystemCacheWriteBuffer(bool enable)
208 {
209 if (enable)
210 {
211 LMEM->PSCCR |= LMEM_PSCCR_ENWRBUF_MASK;
212 }
213 else
214 {
215 LMEM->PSCCR &= ~LMEM_PSCCR_ENWRBUF_MASK;
216 }
217 }
218 /*! @} */
219 #endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
220
221 /*!
222 * @name cache control for unified L1 cache driver
223 *@{
224 */
225
226 /*!
227 * @brief Invalidates cortex-m4 L1 instrument cache by range.
228 *
229 * @param address The start address of the memory to be invalidated.
230 * @param size_byte The memory size.
231 * @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
232 */
233 void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte);
234
235 /*!
236 * @brief Invalidates cortex-m4 L1 data cache by range.
237 *
238 * @param address The start address of the memory to be invalidated.
239 * @param size_byte The memory size.
240 * @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
241 */
L1CACHE_InvalidateDCacheByRange(uint32_t address,uint32_t size_byte)242 static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
243 {
244 L1CACHE_InvalidateICacheByRange(address, size_byte);
245 }
246
247 /*!
248 * @brief Cleans cortex-m4 L1 data cache by range.
249 *
250 * @param address The start address of the memory to be cleaned.
251 * @param size_byte The memory size.
252 * @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
253 */
254 void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte);
255
256 /*!
257 * @brief Cleans and Invalidates cortex-m4 L1 data cache by range.
258 *
259 * @param address The start address of the memory to be clean and invalidated.
260 * @param size_byte The memory size.
261 * @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
262 */
263 void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte);
264 /*! @} */
265 #endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */
266
267 /*!
268 * @name Unified Cache Control for all caches
269 *@{
270 */
271
272 /*!
273 * @brief Invalidates instruction cache by range.
274 *
275 * @param address The physical address.
276 * @param size_byte size of the memory to be invalidated.
277 * @note Address and size should be aligned to 16-Byte due to the cache operation unit
278 * FSL_FEATURE_L1ICACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
279 * size if startAddr is not aligned. For the size_byte, application should make sure the
280 * alignment or make sure the right operation order if the size_byte is not aligned.
281 */
ICACHE_InvalidateByRange(uint32_t address,uint32_t size_byte)282 static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
283 {
284 L1CACHE_InvalidateICacheByRange(address, size_byte);
285 }
286
287 /*!
288 * @brief Invalidates data cache by range.
289 *
290 * @param address The physical address.
291 * @param size_byte size of the memory to be invalidated.
292 * @note Address and size should be aligned to 16-Byte due to the cache operation unit
293 * FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
294 * size if startAddr is not aligned. For the size_byte, application should make sure the
295 * alignment or make sure the right operation order if the size_byte is not aligned.
296 */
DCACHE_InvalidateByRange(uint32_t address,uint32_t size_byte)297 static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
298 {
299 L1CACHE_InvalidateDCacheByRange(address, size_byte);
300 }
301
302 /*!
303 * @brief Clean data cache by range.
304 *
305 * @param address The physical address.
306 * @param size_byte size of the memory to be cleaned.
307 * @note Address and size should be aligned to 16-Byte due to the cache operation unit
308 * FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
309 * size if startAddr is not aligned. For the size_byte, application should make sure the
310 * alignment or make sure the right operation order if the size_byte is not aligned.
311 */
DCACHE_CleanByRange(uint32_t address,uint32_t size_byte)312 static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
313 {
314 L1CACHE_CleanDCacheByRange(address, size_byte);
315 }
316
317 /*!
318 * @brief Cleans and Invalidates data cache by range.
319 *
320 * @param address The physical address.
321 * @param size_byte size of the memory to be Cleaned and Invalidated.
322 * @note Address and size should be aligned to 16-Byte due to the cache operation unit
323 * FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
324 * size if startAddr is not aligned. For the size_byte, application should make sure the
325 * alignment or make sure the right operation order if the size_byte is not aligned.
326 */
DCACHE_CleanInvalidateByRange(uint32_t address,uint32_t size_byte)327 static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
328 {
329 L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
330 }
331
332 /*! @} */
333
334 #if defined(__cplusplus)
335 }
336 #endif
337
338 /*! @}*/
339
340 #endif /* FSL_CACHE_H_*/
341
