1/* ------------------------------------------------------------------------- */ 2/* @file: startup_MKV30F12810.s */ 3/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ 4/* MKV30F12810 */ 5/* @version: 0.5 */ 6/* @date: 2015-2-19 */ 7/* @build: b190918 */ 8/* ------------------------------------------------------------------------- */ 9/* */ 10/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ 11/* Copyright 2016-2019 NXP */ 12/* All rights reserved. */ 13/* */ 14/* SPDX-License-Identifier: BSD-3-Clause */ 15/*****************************************************************************/ 16/* Version: GCC for ARM Embedded Processors */ 17/*****************************************************************************/ 18 .syntax unified 19 .arch armv7-m 20 21 .section .isr_vector, "a" 22 .align 2 23 .globl __isr_vector 24__isr_vector: 25 .long __StackTop /* Top of Stack */ 26 .long Reset_Handler /* Reset Handler */ 27 .long NMI_Handler /* NMI Handler*/ 28 .long HardFault_Handler /* Hard Fault Handler*/ 29 .long MemManage_Handler /* MPU Fault Handler*/ 30 .long BusFault_Handler /* Bus Fault Handler*/ 31 .long UsageFault_Handler /* Usage Fault Handler*/ 32 .long 0 /* Reserved*/ 33 .long 0 /* Reserved*/ 34 .long 0 /* Reserved*/ 35 .long 0 /* Reserved*/ 36 .long SVC_Handler /* SVCall Handler*/ 37 .long DebugMon_Handler /* Debug Monitor Handler*/ 38 .long 0 /* Reserved*/ 39 .long PendSV_Handler /* PendSV Handler*/ 40 .long SysTick_Handler /* SysTick Handler*/ 41 42 /* External Interrupts*/ 43 .long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/ 44 .long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/ 45 .long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/ 46 .long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/ 47 .long Reserved20_IRQHandler /* Reserved interrupt 20*/ 48 .long Reserved21_IRQHandler /* Reserved interrupt 21*/ 49 .long Reserved22_IRQHandler /* Reserved interrupt 22*/ 50 .long Reserved23_IRQHandler /* Reserved interrupt 23*/ 51 .long Reserved24_IRQHandler /* Reserved interrupt 24*/ 52 .long Reserved25_IRQHandler /* Reserved interrupt 25*/ 53 .long Reserved26_IRQHandler /* Reserved interrupt 26*/ 54 .long Reserved27_IRQHandler /* Reserved interrupt 27*/ 55 .long Reserved28_IRQHandler /* Reserved interrupt 28*/ 56 .long Reserved29_IRQHandler /* Reserved interrupt 29*/ 57 .long Reserved30_IRQHandler /* Reserved interrupt 30*/ 58 .long Reserved31_IRQHandler /* Reserved interrupt 31*/ 59 .long DMA_Error_IRQHandler /* DMA Error Interrupt*/ 60 .long MCM_IRQHandler /* Normal Interrupt*/ 61 .long FTF_IRQHandler /* FTFA Command complete interrupt*/ 62 .long Read_Collision_IRQHandler /* Read Collision Interrupt*/ 63 .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/ 64 .long LLWU_IRQHandler /* Low Leakage Wakeup Unit*/ 65 .long WDOG_EWM_IRQHandler /* WDOG Interrupt*/ 66 .long Reserved39_IRQHandler /* Reserved Interrupt 39*/ 67 .long I2C0_IRQHandler /* I2C0 interrupt*/ 68 .long Reserved41_IRQHandler /* Reserved Interrupt 41*/ 69 .long SPI0_IRQHandler /* SPI0 Interrupt*/ 70 .long Reserved43_IRQHandler /* Reserved Interrupt 43*/ 71 .long Reserved44_IRQHandler /* Reserved Interrupt 44*/ 72 .long Reserved45_IRQHandler /* Reserved interrupt 45*/ 73 .long Reserved46_IRQHandler /* Reserved interrupt 46*/ 74 .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/ 75 .long UART0_ERR_IRQHandler /* UART0 Error interrupt*/ 76 .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/ 77 .long UART1_ERR_IRQHandler /* UART1 Error interrupt*/ 78 .long Reserved51_IRQHandler /* Reserved interrupt 51*/ 79 .long Reserved52_IRQHandler /* Reserved interrupt 52*/ 80 .long Reserved53_IRQHandler /* Reserved interrupt 53*/ 81 .long Reserved54_IRQHandler /* Reserved interrupt 54*/ 82 .long ADC0_IRQHandler /* ADC0 interrupt*/ 83 .long CMP0_IRQHandler /* CMP0 interrupt*/ 84 .long CMP1_IRQHandler /* CMP1 interrupt*/ 85 .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/ 86 .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/ 87 .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/ 88 .long Reserved61_IRQHandler /* Reserved interrupt 61*/ 89 .long Reserved62_IRQHandler /* Reserved interrupt 62*/ 90 .long Reserved63_IRQHandler /* Reserved interrupt 63*/ 91 .long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/ 92 .long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/ 93 .long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/ 94 .long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/ 95 .long PDB0_IRQHandler /* PDB0 Interrupt*/ 96 .long Reserved69_IRQHandler /* Reserved interrupt 69*/ 97 .long Reserved70_IRQHandler /* Reserved interrupt 70*/ 98 .long Reserved71_IRQHandler /* Reserved interrupt 71*/ 99 .long DAC0_IRQHandler /* DAC0 interrupt*/ 100 .long MCG_IRQHandler /* MCG Interrupt*/ 101 .long LPTMR0_IRQHandler /* LPTimer interrupt*/ 102 .long PORTA_IRQHandler /* Port A interrupt*/ 103 .long PORTB_IRQHandler /* Port B interrupt*/ 104 .long PORTC_IRQHandler /* Port C interrupt*/ 105 .long PORTD_IRQHandler /* Port D interrupt*/ 106 .long PORTE_IRQHandler /* Port E interrupt*/ 107 .long SWI_IRQHandler /* Software interrupt*/ 108 .long Reserved81_IRQHandler /* Reserved interrupt 81*/ 109 .long Reserved82_IRQHandler /* Reserved interrupt 82*/ 110 .long Reserved83_IRQHandler /* Reserved interrupt 83*/ 111 .long Reserved84_IRQHandler /* Reserved interrupt 84*/ 112 .long Reserved85_IRQHandler /* Reserved interrupt 85*/ 113 .long Reserved86_IRQHandler /* Reserved interrupt 86*/ 114 .long Reserved87_IRQHandler /* Reserved interrupt 87*/ 115 .long Reserved88_IRQHandler /* Reserved interrupt 88*/ 116 .long ADC1_IRQHandler /* ADC1 interrupt*/ 117 .long DefaultISR /* 90*/ 118 .long DefaultISR /* 91*/ 119 .long DefaultISR /* 92*/ 120 .long DefaultISR /* 93*/ 121 .long DefaultISR /* 94*/ 122 .long DefaultISR /* 95*/ 123 .long DefaultISR /* 96*/ 124 .long DefaultISR /* 97*/ 125 .long DefaultISR /* 98*/ 126 .long DefaultISR /* 99*/ 127 .long DefaultISR /* 100*/ 128 .long DefaultISR /* 101*/ 129 .long DefaultISR /* 102*/ 130 .long DefaultISR /* 103*/ 131 .long DefaultISR /* 104*/ 132 .long DefaultISR /* 105*/ 133 .long DefaultISR /* 106*/ 134 .long DefaultISR /* 107*/ 135 .long DefaultISR /* 108*/ 136 .long DefaultISR /* 109*/ 137 .long DefaultISR /* 110*/ 138 .long DefaultISR /* 111*/ 139 .long DefaultISR /* 112*/ 140 .long DefaultISR /* 113*/ 141 .long DefaultISR /* 114*/ 142 .long DefaultISR /* 115*/ 143 .long DefaultISR /* 116*/ 144 .long DefaultISR /* 117*/ 145 .long DefaultISR /* 118*/ 146 .long DefaultISR /* 119*/ 147 .long DefaultISR /* 120*/ 148 .long DefaultISR /* 121*/ 149 .long DefaultISR /* 122*/ 150 .long DefaultISR /* 123*/ 151 .long DefaultISR /* 124*/ 152 .long DefaultISR /* 125*/ 153 .long DefaultISR /* 126*/ 154 .long DefaultISR /* 127*/ 155 .long DefaultISR /* 128*/ 156 .long DefaultISR /* 129*/ 157 .long DefaultISR /* 130*/ 158 .long DefaultISR /* 131*/ 159 .long DefaultISR /* 132*/ 160 .long DefaultISR /* 133*/ 161 .long DefaultISR /* 134*/ 162 .long DefaultISR /* 135*/ 163 .long DefaultISR /* 136*/ 164 .long DefaultISR /* 137*/ 165 .long DefaultISR /* 138*/ 166 .long DefaultISR /* 139*/ 167 .long DefaultISR /* 140*/ 168 .long DefaultISR /* 141*/ 169 .long DefaultISR /* 142*/ 170 .long DefaultISR /* 143*/ 171 .long DefaultISR /* 144*/ 172 .long DefaultISR /* 145*/ 173 .long DefaultISR /* 146*/ 174 .long DefaultISR /* 147*/ 175 .long DefaultISR /* 148*/ 176 .long DefaultISR /* 149*/ 177 .long DefaultISR /* 150*/ 178 .long DefaultISR /* 151*/ 179 .long DefaultISR /* 152*/ 180 .long DefaultISR /* 153*/ 181 .long DefaultISR /* 154*/ 182 .long DefaultISR /* 155*/ 183 .long DefaultISR /* 156*/ 184 .long DefaultISR /* 157*/ 185 .long DefaultISR /* 158*/ 186 .long DefaultISR /* 159*/ 187 .long DefaultISR /* 160*/ 188 .long DefaultISR /* 161*/ 189 .long DefaultISR /* 162*/ 190 .long DefaultISR /* 163*/ 191 .long DefaultISR /* 164*/ 192 .long DefaultISR /* 165*/ 193 .long DefaultISR /* 166*/ 194 .long DefaultISR /* 167*/ 195 .long DefaultISR /* 168*/ 196 .long DefaultISR /* 169*/ 197 .long DefaultISR /* 170*/ 198 .long DefaultISR /* 171*/ 199 .long DefaultISR /* 172*/ 200 .long DefaultISR /* 173*/ 201 .long DefaultISR /* 174*/ 202 .long DefaultISR /* 175*/ 203 .long DefaultISR /* 176*/ 204 .long DefaultISR /* 177*/ 205 .long DefaultISR /* 178*/ 206 .long DefaultISR /* 179*/ 207 .long DefaultISR /* 180*/ 208 .long DefaultISR /* 181*/ 209 .long DefaultISR /* 182*/ 210 .long DefaultISR /* 183*/ 211 .long DefaultISR /* 184*/ 212 .long DefaultISR /* 185*/ 213 .long DefaultISR /* 186*/ 214 .long DefaultISR /* 187*/ 215 .long DefaultISR /* 188*/ 216 .long DefaultISR /* 189*/ 217 .long DefaultISR /* 190*/ 218 .long DefaultISR /* 191*/ 219 .long DefaultISR /* 192*/ 220 .long DefaultISR /* 193*/ 221 .long DefaultISR /* 194*/ 222 .long DefaultISR /* 195*/ 223 .long DefaultISR /* 196*/ 224 .long DefaultISR /* 197*/ 225 .long DefaultISR /* 198*/ 226 .long DefaultISR /* 199*/ 227 .long DefaultISR /* 200*/ 228 .long DefaultISR /* 201*/ 229 .long DefaultISR /* 202*/ 230 .long DefaultISR /* 203*/ 231 .long DefaultISR /* 204*/ 232 .long DefaultISR /* 205*/ 233 .long DefaultISR /* 206*/ 234 .long DefaultISR /* 207*/ 235 .long DefaultISR /* 208*/ 236 .long DefaultISR /* 209*/ 237 .long DefaultISR /* 210*/ 238 .long DefaultISR /* 211*/ 239 .long DefaultISR /* 212*/ 240 .long DefaultISR /* 213*/ 241 .long DefaultISR /* 214*/ 242 .long DefaultISR /* 215*/ 243 .long DefaultISR /* 216*/ 244 .long DefaultISR /* 217*/ 245 .long DefaultISR /* 218*/ 246 .long DefaultISR /* 219*/ 247 .long DefaultISR /* 220*/ 248 .long DefaultISR /* 221*/ 249 .long DefaultISR /* 222*/ 250 .long DefaultISR /* 223*/ 251 .long DefaultISR /* 224*/ 252 .long DefaultISR /* 225*/ 253 .long DefaultISR /* 226*/ 254 .long DefaultISR /* 227*/ 255 .long DefaultISR /* 228*/ 256 .long DefaultISR /* 229*/ 257 .long DefaultISR /* 230*/ 258 .long DefaultISR /* 231*/ 259 .long DefaultISR /* 232*/ 260 .long DefaultISR /* 233*/ 261 .long DefaultISR /* 234*/ 262 .long DefaultISR /* 235*/ 263 .long DefaultISR /* 236*/ 264 .long DefaultISR /* 237*/ 265 .long DefaultISR /* 238*/ 266 .long DefaultISR /* 239*/ 267 .long DefaultISR /* 240*/ 268 .long DefaultISR /* 241*/ 269 .long DefaultISR /* 242*/ 270 .long DefaultISR /* 243*/ 271 .long DefaultISR /* 244*/ 272 .long DefaultISR /* 245*/ 273 .long DefaultISR /* 246*/ 274 .long DefaultISR /* 247*/ 275 .long DefaultISR /* 248*/ 276 .long DefaultISR /* 249*/ 277 .long DefaultISR /* 250*/ 278 .long DefaultISR /* 251*/ 279 .long DefaultISR /* 252*/ 280 .long DefaultISR /* 253*/ 281 .long DefaultISR /* 254*/ 282 .long 0xFFFFFFFF /* Reserved for user TRIM value*/ 283 284 .size __isr_vector, . - __isr_vector 285 286/* Flash Configuration */ 287 .section .FlashConfig, "a" 288 .long 0xFFFFFFFF 289 .long 0xFFFFFFFF 290 .long 0xFFFFFFFF 291 .long 0xFFFFFFFE 292 293 .text 294 .thumb 295 296/* Reset Handler */ 297 298 .thumb_func 299 .align 2 300 .globl Reset_Handler 301 .weak Reset_Handler 302 .type Reset_Handler, %function 303Reset_Handler: 304 cpsid i /* Mask interrupts */ 305 .equ VTOR, 0xE000ED08 306 ldr r0, =VTOR 307 ldr r1, =__isr_vector 308 str r1, [r0] 309 ldr r2, [r1] 310 msr msp, r2 311#ifndef __NO_SYSTEM_INIT 312 ldr r0,=SystemInit 313 blx r0 314#endif 315/* Loop to copy data from read only memory to RAM. The ranges 316 * of copy from/to are specified by following symbols evaluated in 317 * linker script. 318 * __etext: End of code section, i.e., begin of data sections to copy from. 319 * __data_start__/__data_end__: RAM address range that data should be 320 * copied to. Both must be aligned to 4 bytes boundary. */ 321 322 ldr r1, =__etext 323 ldr r2, =__data_start__ 324 ldr r3, =__data_end__ 325 326#ifdef __PERFORMANCE_IMPLEMENTATION 327/* Here are two copies of loop implementations. First one favors performance 328 * and the second one favors code size. Default uses the second one. 329 * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */ 330 subs r3, r2 331 ble .LC1 332.LC0: 333 subs r3, #4 334 ldr r0, [r1, r3] 335 str r0, [r2, r3] 336 bgt .LC0 337.LC1: 338#else /* code size implemenation */ 339.LC0: 340 cmp r2, r3 341 ittt lt 342 ldrlt r0, [r1], #4 343 strlt r0, [r2], #4 344 blt .LC0 345#endif 346 347#ifdef __STARTUP_CLEAR_BSS 348/* This part of work usually is done in C library startup code. Otherwise, 349 * define this macro to enable it in this startup. 350 * 351 * Loop to zero out BSS section, which uses following symbols 352 * in linker script: 353 * __bss_start__: start of BSS section. Must align to 4 354 * __bss_end__: end of BSS section. Must align to 4 355 */ 356 ldr r1, =__bss_start__ 357 ldr r2, =__bss_end__ 358 359 movs r0, 0 360.LC2: 361 cmp r1, r2 362 itt lt 363 strlt r0, [r1], #4 364 blt .LC2 365#endif /* __STARTUP_CLEAR_BSS */ 366 367 cpsie i /* Unmask interrupts */ 368#ifndef __START 369#define __START _start 370#endif 371#ifndef __ATOLLIC__ 372 ldr r0,=__START 373 blx r0 374#else 375 ldr r0,=__libc_init_array 376 blx r0 377 ldr r0,=main 378 bx r0 379#endif 380 .pool 381 .size Reset_Handler, . - Reset_Handler 382 383 .align 1 384 .thumb_func 385 .weak DefaultISR 386 .type DefaultISR, %function 387DefaultISR: 388 b DefaultISR 389 .size DefaultISR, . - DefaultISR 390 391 .align 1 392 .thumb_func 393 .weak NMI_Handler 394 .type NMI_Handler, %function 395NMI_Handler: 396 ldr r0,=NMI_Handler 397 bx r0 398 .size NMI_Handler, . - NMI_Handler 399 400 .align 1 401 .thumb_func 402 .weak HardFault_Handler 403 .type HardFault_Handler, %function 404HardFault_Handler: 405 ldr r0,=HardFault_Handler 406 bx r0 407 .size HardFault_Handler, . - HardFault_Handler 408 409 .align 1 410 .thumb_func 411 .weak SVC_Handler 412 .type SVC_Handler, %function 413SVC_Handler: 414 ldr r0,=SVC_Handler 415 bx r0 416 .size SVC_Handler, . - SVC_Handler 417 418 .align 1 419 .thumb_func 420 .weak PendSV_Handler 421 .type PendSV_Handler, %function 422PendSV_Handler: 423 ldr r0,=PendSV_Handler 424 bx r0 425 .size PendSV_Handler, . - PendSV_Handler 426 427 .align 1 428 .thumb_func 429 .weak SysTick_Handler 430 .type SysTick_Handler, %function 431SysTick_Handler: 432 ldr r0,=SysTick_Handler 433 bx r0 434 .size SysTick_Handler, . - SysTick_Handler 435 436 .align 1 437 .thumb_func 438 .weak DMA0_IRQHandler 439 .type DMA0_IRQHandler, %function 440DMA0_IRQHandler: 441 ldr r0,=DMA0_DriverIRQHandler 442 bx r0 443 .size DMA0_IRQHandler, . - DMA0_IRQHandler 444 445 .align 1 446 .thumb_func 447 .weak DMA1_IRQHandler 448 .type DMA1_IRQHandler, %function 449DMA1_IRQHandler: 450 ldr r0,=DMA1_DriverIRQHandler 451 bx r0 452 .size DMA1_IRQHandler, . - DMA1_IRQHandler 453 454 .align 1 455 .thumb_func 456 .weak DMA2_IRQHandler 457 .type DMA2_IRQHandler, %function 458DMA2_IRQHandler: 459 ldr r0,=DMA2_DriverIRQHandler 460 bx r0 461 .size DMA2_IRQHandler, . - DMA2_IRQHandler 462 463 .align 1 464 .thumb_func 465 .weak DMA3_IRQHandler 466 .type DMA3_IRQHandler, %function 467DMA3_IRQHandler: 468 ldr r0,=DMA3_DriverIRQHandler 469 bx r0 470 .size DMA3_IRQHandler, . - DMA3_IRQHandler 471 472 .align 1 473 .thumb_func 474 .weak DMA_Error_IRQHandler 475 .type DMA_Error_IRQHandler, %function 476DMA_Error_IRQHandler: 477 ldr r0,=DMA_Error_DriverIRQHandler 478 bx r0 479 .size DMA_Error_IRQHandler, . - DMA_Error_IRQHandler 480 481 .align 1 482 .thumb_func 483 .weak I2C0_IRQHandler 484 .type I2C0_IRQHandler, %function 485I2C0_IRQHandler: 486 ldr r0,=I2C0_DriverIRQHandler 487 bx r0 488 .size I2C0_IRQHandler, . - I2C0_IRQHandler 489 490 .align 1 491 .thumb_func 492 .weak SPI0_IRQHandler 493 .type SPI0_IRQHandler, %function 494SPI0_IRQHandler: 495 ldr r0,=SPI0_DriverIRQHandler 496 bx r0 497 .size SPI0_IRQHandler, . - SPI0_IRQHandler 498 499 .align 1 500 .thumb_func 501 .weak UART0_RX_TX_IRQHandler 502 .type UART0_RX_TX_IRQHandler, %function 503UART0_RX_TX_IRQHandler: 504 ldr r0,=UART0_RX_TX_DriverIRQHandler 505 bx r0 506 .size UART0_RX_TX_IRQHandler, . - UART0_RX_TX_IRQHandler 507 508 .align 1 509 .thumb_func 510 .weak UART0_ERR_IRQHandler 511 .type UART0_ERR_IRQHandler, %function 512UART0_ERR_IRQHandler: 513 ldr r0,=UART0_ERR_DriverIRQHandler 514 bx r0 515 .size UART0_ERR_IRQHandler, . - UART0_ERR_IRQHandler 516 517 .align 1 518 .thumb_func 519 .weak UART1_RX_TX_IRQHandler 520 .type UART1_RX_TX_IRQHandler, %function 521UART1_RX_TX_IRQHandler: 522 ldr r0,=UART1_RX_TX_DriverIRQHandler 523 bx r0 524 .size UART1_RX_TX_IRQHandler, . - UART1_RX_TX_IRQHandler 525 526 .align 1 527 .thumb_func 528 .weak UART1_ERR_IRQHandler 529 .type UART1_ERR_IRQHandler, %function 530UART1_ERR_IRQHandler: 531 ldr r0,=UART1_ERR_DriverIRQHandler 532 bx r0 533 .size UART1_ERR_IRQHandler, . - UART1_ERR_IRQHandler 534 535 536/* Macro to define default handlers. Default handler 537 * will be weak symbol and just dead loops. They can be 538 * overwritten by other handlers */ 539 .macro def_irq_handler handler_name 540 .weak \handler_name 541 .set \handler_name, DefaultISR 542 .endm 543 544/* Exception Handlers */ 545 def_irq_handler MemManage_Handler 546 def_irq_handler BusFault_Handler 547 def_irq_handler UsageFault_Handler 548 def_irq_handler DebugMon_Handler 549 def_irq_handler DMA0_DriverIRQHandler 550 def_irq_handler DMA1_DriverIRQHandler 551 def_irq_handler DMA2_DriverIRQHandler 552 def_irq_handler DMA3_DriverIRQHandler 553 def_irq_handler Reserved20_IRQHandler 554 def_irq_handler Reserved21_IRQHandler 555 def_irq_handler Reserved22_IRQHandler 556 def_irq_handler Reserved23_IRQHandler 557 def_irq_handler Reserved24_IRQHandler 558 def_irq_handler Reserved25_IRQHandler 559 def_irq_handler Reserved26_IRQHandler 560 def_irq_handler Reserved27_IRQHandler 561 def_irq_handler Reserved28_IRQHandler 562 def_irq_handler Reserved29_IRQHandler 563 def_irq_handler Reserved30_IRQHandler 564 def_irq_handler Reserved31_IRQHandler 565 def_irq_handler DMA_Error_DriverIRQHandler 566 def_irq_handler MCM_IRQHandler 567 def_irq_handler FTF_IRQHandler 568 def_irq_handler Read_Collision_IRQHandler 569 def_irq_handler LVD_LVW_IRQHandler 570 def_irq_handler LLWU_IRQHandler 571 def_irq_handler WDOG_EWM_IRQHandler 572 def_irq_handler Reserved39_IRQHandler 573 def_irq_handler I2C0_DriverIRQHandler 574 def_irq_handler Reserved41_IRQHandler 575 def_irq_handler SPI0_DriverIRQHandler 576 def_irq_handler Reserved43_IRQHandler 577 def_irq_handler Reserved44_IRQHandler 578 def_irq_handler Reserved45_IRQHandler 579 def_irq_handler Reserved46_IRQHandler 580 def_irq_handler UART0_RX_TX_DriverIRQHandler 581 def_irq_handler UART0_ERR_DriverIRQHandler 582 def_irq_handler UART1_RX_TX_DriverIRQHandler 583 def_irq_handler UART1_ERR_DriverIRQHandler 584 def_irq_handler Reserved51_IRQHandler 585 def_irq_handler Reserved52_IRQHandler 586 def_irq_handler Reserved53_IRQHandler 587 def_irq_handler Reserved54_IRQHandler 588 def_irq_handler ADC0_IRQHandler 589 def_irq_handler CMP0_IRQHandler 590 def_irq_handler CMP1_IRQHandler 591 def_irq_handler FTM0_IRQHandler 592 def_irq_handler FTM1_IRQHandler 593 def_irq_handler FTM2_IRQHandler 594 def_irq_handler Reserved61_IRQHandler 595 def_irq_handler Reserved62_IRQHandler 596 def_irq_handler Reserved63_IRQHandler 597 def_irq_handler PIT0_IRQHandler 598 def_irq_handler PIT1_IRQHandler 599 def_irq_handler PIT2_IRQHandler 600 def_irq_handler PIT3_IRQHandler 601 def_irq_handler PDB0_IRQHandler 602 def_irq_handler Reserved69_IRQHandler 603 def_irq_handler Reserved70_IRQHandler 604 def_irq_handler Reserved71_IRQHandler 605 def_irq_handler DAC0_IRQHandler 606 def_irq_handler MCG_IRQHandler 607 def_irq_handler LPTMR0_IRQHandler 608 def_irq_handler PORTA_IRQHandler 609 def_irq_handler PORTB_IRQHandler 610 def_irq_handler PORTC_IRQHandler 611 def_irq_handler PORTD_IRQHandler 612 def_irq_handler PORTE_IRQHandler 613 def_irq_handler SWI_IRQHandler 614 def_irq_handler Reserved81_IRQHandler 615 def_irq_handler Reserved82_IRQHandler 616 def_irq_handler Reserved83_IRQHandler 617 def_irq_handler Reserved84_IRQHandler 618 def_irq_handler Reserved85_IRQHandler 619 def_irq_handler Reserved86_IRQHandler 620 def_irq_handler Reserved87_IRQHandler 621 def_irq_handler Reserved88_IRQHandler 622 def_irq_handler ADC1_IRQHandler 623 624 .end 625
