1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2019, 2023 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_CLOCK_H_
10 #define _FSL_CLOCK_H_
11
12 #include "fsl_common.h"
13
14 /*! @addtogroup clock */
15 /*! @{ */
16
17 /*! @file */
18
19 /*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23 /*! @brief Configures whether to check a parameter in a function.
24 *
25 * Some MCG settings must be changed with conditions, for example:
26 * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
27 * MCGIRCLK is used as a system clock source.
28 * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used
29 * as a system clock source. For example, in FBE/BLPE/PBE modes.
30 * 3. The users should only switch between the supported clock modes.
31 *
32 * MCG functions check the parameter and MCG status before setting, if not allowed
33 * to change, the functions return error. The parameter checking increases code size,
34 * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
35 * disable parameter checking.
36 */
37 #ifndef MCG_CONFIG_CHECK_PARAM
38 #define MCG_CONFIG_CHECK_PARAM 0U
39 #endif
40
41 /*! @brief Configure whether driver controls clock
42 *
43 * When set to 0, peripheral drivers will enable clock in initialize function
44 * and disable clock in de-initialize function. When set to 1, peripheral
45 * driver will not control the clock, application could control the clock out of
46 * the driver.
47 *
48 * @note All drivers share this feature switcher. If it is set to 1, application
49 * should handle clock enable and disable for all drivers.
50 */
51 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
52 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
53 #endif
54
55 /*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58
59 /*! @name Driver version */
60 /*@{*/
61 /*! @brief CLOCK driver version 2.5.1. */
62 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
63 /*@}*/
64
65 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
66 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY 75000000
67 #endif
68
69 /*! @brief External XTAL0 (OSC0) clock frequency.
70 *
71 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
72 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
73 * if XTAL0 is 8 MHz:
74 * @code
75 * Set up the OSC0
76 * CLOCK_InitOsc0(...);
77 * Set the XTAL0 value to the clock driver.
78 * CLOCK_SetXtal0Freq(80000000);
79 * @endcode
80 *
81 * This is important for the multicore platforms where only one core needs to set up the
82 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
83 * to get a valid clock frequency.
84 */
85 extern volatile uint32_t g_xtal0Freq;
86
87 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
88 *
89 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
90 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
91 *
92 * This is important for the multicore platforms where only one core needs to set up
93 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
94 * to get a valid clock frequency.
95 */
96 extern volatile uint32_t g_xtal32Freq;
97
98 #if (defined(OSC) && !(defined(OSC0)))
99 #define OSC0 OSC
100 #endif
101
102 /*! @brief Clock ip name array for DMAMUX. */
103 #define DMAMUX_CLOCKS \
104 { \
105 kCLOCK_Dmamux0 \
106 }
107
108 /*! @brief Clock ip name array for PORT. */
109 #define PORT_CLOCKS \
110 { \
111 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
112 }
113
114 /*! @brief Clock ip name array for EWM. */
115 #define EWM_CLOCKS \
116 { \
117 kCLOCK_Ewm0 \
118 }
119
120 /*! @brief Clock ip name array for DSPI. */
121 #define DSPI_CLOCKS \
122 { \
123 kCLOCK_Spi0 \
124 }
125
126 /*! @brief Clock ip name array for FTM. */
127 #define FTM_CLOCKS \
128 { \
129 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2 \
130 }
131
132 /*! @brief Clock ip name array for EDMA. */
133 #define EDMA_CLOCKS \
134 { \
135 kCLOCK_Dma0 \
136 }
137
138 /*! @brief Clock ip name array for DAC. */
139 #define DAC_CLOCKS \
140 { \
141 kCLOCK_Dac0 \
142 }
143
144 /*! @brief Clock ip name array for ADC16. */
145 #define ADC16_CLOCKS \
146 { \
147 kCLOCK_Adc0, kCLOCK_Adc1 \
148 }
149
150 /*! @brief Clock ip name array for UART. */
151 #define UART_CLOCKS \
152 { \
153 kCLOCK_Uart0, kCLOCK_Uart1 \
154 }
155
156 /*! @brief Clock ip name array for CRC. */
157 #define CRC_CLOCKS \
158 { \
159 kCLOCK_Crc0 \
160 }
161
162 /*! @brief Clock ip name array for I2C. */
163 #define I2C_CLOCKS \
164 { \
165 kCLOCK_I2c0 \
166 }
167
168 /*! @brief Clock ip name array for LPTMR. */
169 #define LPTMR_CLOCKS \
170 { \
171 kCLOCK_Lptmr0 \
172 }
173
174 /*! @brief Clock ip name array for PDB. */
175 #define PDB_CLOCKS \
176 { \
177 kCLOCK_Pdb0 \
178 }
179
180 /*! @brief Clock ip name array for FTF. */
181 #define FTF_CLOCKS \
182 { \
183 kCLOCK_Ftf0 \
184 }
185
186 /*! @brief Clock ip name array for CMP. */
187 #define CMP_CLOCKS \
188 { \
189 kCLOCK_Cmp0, kCLOCK_Cmp1 \
190 }
191
192 /*!
193 * @brief LPO clock frequency.
194 */
195 #define LPO_CLK_FREQ 1000U
196
197 /*! @brief Peripherals clock source definition. */
198 #define SYS_CLK kCLOCK_CoreSysClk
199 #define BUS_CLK kCLOCK_BusClk
200
201 #define I2C0_CLK_SRC BUS_CLK
202 #define DSPI0_CLK_SRC SYS_CLK
203 #define UART0_CLK_SRC SYS_CLK
204 #define UART1_CLK_SRC BUS_CLK
205
206 /*! @brief Clock name used to get clock frequency. */
207 typedef enum _clock_name
208 {
209
210 /* ----------------------------- System layer clock -------------------------------*/
211 kCLOCK_CoreSysClk, /*!< Core/system clock */
212 kCLOCK_PlatClk, /*!< Platform clock */
213 kCLOCK_BusClk, /*!< Bus clock */
214 kCLOCK_FlashClk, /*!< Flash clock */
215 kCLOCK_AltAdc, /*!< Alternative clock */
216
217 /* ---------------------------------- OSC clock -----------------------------------*/
218 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
219 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
220
221 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
222 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
223 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
224 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
225 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
226
227 /* --------------------------------- Other clock ----------------------------------*/
228 kCLOCK_LpoClk, /*!< LPO clock */
229
230 } clock_name_t;
231
232 /*------------------------------------------------------------------------------
233
234 clock_gate_t definition:
235
236 31 16 0
237 -----------------------------------------------------------------
238 | SIM_SCGC register offset | control bit offset in SCGC |
239 -----------------------------------------------------------------
240
241 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
242 SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as
243
244 kClockGateSdhc0 = (0x1030 << 16) | 17;
245
246 ------------------------------------------------------------------------------*/
247
248 #define CLK_GATE_REG_OFFSET_SHIFT 16U
249 #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
250 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
251 #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
252
253 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
254 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
255 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
256
257 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
258 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
259
260 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
261 typedef enum _clock_ip_name
262 {
263 kCLOCK_IpInvalid = 0U,
264 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
265 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
266 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
267 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
268 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
269 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
270
271 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
272 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
273 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
274 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
275 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
276 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
277
278 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
279 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
280 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
281 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
282 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
283 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
284 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
285 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
286 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
287 kCLOCK_Adc1 = CLK_GATE_DEFINE(0x103CU, 28U),
288 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U),
289
290 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 8U),
291 } clock_ip_name_t;
292
293 /*!@brief SIM configuration structure for clock setting. */
294 typedef struct _sim_clock_config
295 {
296 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
297 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
298 } sim_clock_config_t;
299
300 /*! @brief OSC work mode. */
301 typedef enum _osc_mode
302 {
303 kOSC_ModeExt = 0U, /*!< Use an external clock. */
304 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
305 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
306 #else
307 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
308 #endif
309 kOSC_ModeOscHighGain = 0U
310 #if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
311 | MCG_C2_EREFS_MASK
312 #else
313 | MCG_C2_EREFS0_MASK
314 #endif
315 #if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
316 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
317 #else
318 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
319 #endif
320 } osc_mode_t;
321
322 /*! @brief Oscillator capacitor load setting.*/
323 enum _osc_cap_load
324 {
325 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
326 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
327 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
328 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
329 };
330
331 /*! @brief OSCERCLK enable mode. */
332 enum _oscer_enable_mode
333 {
334 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
335 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
336 };
337
338 /*! @brief OSC configuration for OSCERCLK. */
339 typedef struct _oscer_config
340 {
341 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
342
343 } oscer_config_t;
344
345 /*!
346 * @brief OSC Initialization Configuration Structure
347 *
348 * Defines the configuration data structure to initialize the OSC.
349 * When porting to a new board, set the following members
350 * according to the board setting:
351 * 1. freq: The external frequency.
352 * 2. workMode: The OSC module mode.
353 */
354 typedef struct _osc_config
355 {
356 uint32_t freq; /*!< External clock frequency. */
357 uint8_t capLoad; /*!< Capacitor load setting. */
358 osc_mode_t workMode; /*!< OSC work mode setting. */
359 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
360 } osc_config_t;
361
362 /*! @brief MCG FLL reference clock source select. */
363 typedef enum _mcg_fll_src
364 {
365 kMCG_FllSrcExternal, /*!< External reference clock is selected */
366 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
367 } mcg_fll_src_t;
368
369 /*! @brief MCG internal reference clock select */
370 typedef enum _mcg_irc_mode
371 {
372 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
373 kMCG_IrcFast /*!< Fast internal reference clock selected */
374 } mcg_irc_mode_t;
375
376 /*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
377 typedef enum _mcg_dmx32
378 {
379 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
380 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
381 } mcg_dmx32_t;
382
383 /*! @brief MCG DCO range select */
384 typedef enum _mcg_drs
385 {
386 kMCG_DrsLow, /*!< Low frequency range */
387 kMCG_DrsMid, /*!< Mid frequency range */
388 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
389 kMCG_DrsHigh /*!< High frequency range */
390 } mcg_drs_t;
391
392 /*! @brief MCG PLL reference clock select */
393 typedef enum _mcg_pll_ref_src
394 {
395 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
396 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
397 } mcg_pll_ref_src_t;
398
399 /*! @brief MCGOUT clock source. */
400 typedef enum _mcg_clkout_src
401 {
402 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
403 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
404 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
405 } mcg_clkout_src_t;
406
407 /*! @brief MCG Automatic Trim Machine Select */
408 typedef enum _mcg_atm_select
409 {
410 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
411 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
412 } mcg_atm_select_t;
413
414 /*! @brief MCG OSC Clock Select */
415 typedef enum _mcg_oscsel
416 {
417 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
418 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
419 } mcg_oscsel_t;
420
421 /*! @brief MCG PLLCS select */
422 typedef enum _mcg_pll_clk_select
423 {
424 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
425 kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
426 } mcg_pll_clk_select_t;
427
428 /*! @brief MCG clock monitor mode. */
429 typedef enum _mcg_monitor_mode
430 {
431 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
432 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
433 kMCG_MonitorReset /*!< System reset when clock lost. */
434 } mcg_monitor_mode_t;
435
436 /*! @brief MCG status. */
437 enum _mcg_status
438 {
439 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0), /*!< Can't switch to target mode. */
440 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1), /*!< Current mode invalid for the specific
441 function. */
442 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2), /*!< Invalid bus clock for ATM. */
443 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3), /*!< Invalid desired frequency for ATM. */
444 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4), /*!< IRC is used when using ATM. */
445 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5), /*!< Hardware fail occurs during ATM. */
446 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6) /*!< Can't change the clock source because
447 it is in use. */
448 };
449
450 /*! @brief MCG status flags. */
451 enum _mcg_status_flags_t
452 {
453 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
454 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
455 };
456
457 /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
458 enum _mcg_irclk_enable_mode
459 {
460 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
461 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
462 };
463
464 /*! @brief MCG mode definitions */
465 typedef enum _mcg_mode
466 {
467 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
468 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
469 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
470 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
471 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
472 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
473 kMCG_ModeError /*!< Unknown mode */
474 } mcg_mode_t;
475
476 /*! @brief MCG mode change configuration structure
477 *
478 * When porting to a new board, set the following members
479 * according to the board setting:
480 * 1. frdiv: If the FLL uses the external reference clock, set this
481 * value to ensure that the external reference clock divided by frdiv is
482 * in the 31.25 kHz to 39.0625 kHz range.
483 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
484 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
485 * FSL_FEATURE_MCG_PLL_REF_MAX range.
486 */
487 typedef struct _mcg_config
488 {
489 mcg_mode_t mcgMode; /*!< MCG mode. */
490
491 /* ----------------------- MCGIRCCLK settings ------------------------ */
492 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
493 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
494 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
495
496 /* ------------------------ MCG FLL settings ------------------------- */
497 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
498 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
499 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
500
501 /* ------------------------ MCG PLL settings ------------------------- */
502 } mcg_config_t;
503
504 /*******************************************************************************
505 * API
506 ******************************************************************************/
507
508 #if defined(__cplusplus)
509 extern "C" {
510 #endif /* __cplusplus */
511
512 /*!
513 * @brief Enable the clock for specific IP.
514 *
515 * @param name Which clock to enable, see \ref clock_ip_name_t.
516 */
CLOCK_EnableClock(clock_ip_name_t name)517 static inline void CLOCK_EnableClock(clock_ip_name_t name)
518 {
519 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
520 (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
521 }
522
523 /*!
524 * @brief Disable the clock for specific IP.
525 *
526 * @param name Which clock to disable, see \ref clock_ip_name_t.
527 */
CLOCK_DisableClock(clock_ip_name_t name)528 static inline void CLOCK_DisableClock(clock_ip_name_t name)
529 {
530 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
531 (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
532 }
533
534 /*!
535 * @brief Set ERCLK32K source.
536 *
537 * @param src The value to set ERCLK32K clock source.
538 */
CLOCK_SetEr32kClock(uint32_t src)539 static inline void CLOCK_SetEr32kClock(uint32_t src)
540 {
541 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
542 }
543
544 /*!
545 * @brief Set FTMFFCLKSEL source.
546 *
547 * @param src The value to set FTMFFCLKSEL clock source.
548 */
CLOCK_SetFtmClock(uint32_t src)549 static inline void CLOCK_SetFtmClock(uint32_t src)
550 {
551 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT2_FTMFFCLKSEL_MASK) | SIM_SOPT2_FTMFFCLKSEL(src));
552 }
553
554 /*!
555 * @brief Set CLKOUT source.
556 *
557 * @param src The value to set CLKOUT source.
558 */
CLOCK_SetClkOutClock(uint32_t src)559 static inline void CLOCK_SetClkOutClock(uint32_t src)
560 {
561 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
562 }
563
564 /*!
565 * @brief System clock divider
566 *
567 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV4], SIM_CLKDIV1[OUTDIV5].
568 *
569 * @param outdiv1 Clock 1 output divider value.
570 *
571 * @param outdiv4 Clock 4 output divider value.
572 *
573 * @param outdiv5 Clock 5 output divider value.
574 */
CLOCK_SetOutDiv(uint32_t outdiv1,uint32_t outdiv4,uint32_t outdiv5)575 static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv4, uint32_t outdiv5)
576 {
577 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV4(outdiv4) | SIM_CLKDIV1_OUTDIV5(outdiv5);
578 }
579
580 /*!
581 * @brief Gets the clock frequency for a specific clock name.
582 *
583 * This function checks the current clock configurations and then calculates
584 * the clock frequency for a specific clock name defined in clock_name_t.
585 * The MCG must be properly configured before using this function.
586 *
587 * @param clockName Clock names defined in clock_name_t
588 * @return Clock frequency value in Hertz
589 */
590 uint32_t CLOCK_GetFreq(clock_name_t clockName);
591
592 /*!
593 * @brief Get the core clock or system clock frequency.
594 *
595 * @return Clock frequency in Hz.
596 */
597 uint32_t CLOCK_GetCoreSysClkFreq(void);
598
599 /*!
600 * @brief Get the platform clock frequency.
601 *
602 * @return Clock frequency in Hz.
603 */
604 uint32_t CLOCK_GetPlatClkFreq(void);
605
606 /*!
607 * @brief Get the bus clock frequency.
608 *
609 * @return Clock frequency in Hz.
610 */
611 uint32_t CLOCK_GetBusClkFreq(void);
612
613 /*!
614 * @brief Get the flash clock frequency.
615 *
616 * @return Clock frequency in Hz.
617 */
618 uint32_t CLOCK_GetFlashClkFreq(void);
619
620 /*!
621 * @brief Get the external reference 32K clock frequency (ERCLK32K).
622 *
623 * @return Clock frequency in Hz.
624 */
625 uint32_t CLOCK_GetEr32kClkFreq(void);
626
627 /*!
628 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
629 *
630 * @return Clock frequency in Hz.
631 */
632 uint32_t CLOCK_GetOsc0ErClkFreq(void);
633
634 /*!
635 * @brief Set the clock configure in SIM module.
636 *
637 * This function sets system layer clock settings in SIM module.
638 *
639 * @param config Pointer to the configure structure.
640 */
641 void CLOCK_SetSimConfig(sim_clock_config_t const *config);
642
643 /*!
644 * @brief Set the system clock dividers in SIM to safe value.
645 *
646 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
647 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
648 * changes then the system level clocks may be out of range. This function could
649 * be used before MCG mode change, to make sure system level clocks are in allowed
650 * range.
651 *
652 * @param config Pointer to the configure structure.
653 */
CLOCK_SetSimSafeDivs(void)654 static inline void CLOCK_SetSimSafeDivs(void)
655 {
656 SIM->CLKDIV1 = 0x00040000U;
657 }
658
659 /*! @name MCG frequency functions. */
660 /*@{*/
661
662 /*!
663 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
664 *
665 * This function gets the MCG output clock frequency in Hz based on the current MCG
666 * register value.
667 *
668 * @return The frequency of MCGOUTCLK.
669 */
670 uint32_t CLOCK_GetOutClkFreq(void);
671
672 /*!
673 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
674 *
675 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
676 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
677 * disabled in low power state in other modes.
678 *
679 * @return The frequency of MCGFLLCLK.
680 */
681 uint32_t CLOCK_GetFllFreq(void);
682
683 /*!
684 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
685 *
686 * This function gets the MCG internal reference clock frequency in Hz based
687 * on the current MCG register value.
688 *
689 * @return The frequency of MCGIRCLK.
690 */
691 uint32_t CLOCK_GetInternalRefClkFreq(void);
692
693 /*!
694 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
695 *
696 * This function gets the MCG fixed frequency clock frequency in Hz based
697 * on the current MCG register value.
698 *
699 * @return The frequency of MCGFFCLK.
700 */
701 uint32_t CLOCK_GetFixedFreqClkFreq(void);
702
703 /*@}*/
704
705 /*! @name MCG clock configuration. */
706 /*@{*/
707
708 /*!
709 * @brief Enables or disables the MCG low power.
710 *
711 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
712 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
713 * PBI modes, enabling low power sets the MCG to BLPI mode.
714 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
715 *
716 * @param enable True to enable MCG low power, false to disable MCG low power.
717 */
CLOCK_SetLowPowerEnable(bool enable)718 static inline void CLOCK_SetLowPowerEnable(bool enable)
719 {
720 if (enable)
721 {
722 MCG->C2 |= MCG_C2_LP_MASK;
723 }
724 else
725 {
726 MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
727 }
728 }
729
730 /*!
731 * @brief Configures the Internal Reference clock (MCGIRCLK).
732 *
733 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
734 * source. If the fast IRC is used, this function sets the fast IRC divider.
735 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
736 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
737 * using the function in these modes it is not allowed.
738 *
739 * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
740 * @param ircs MCGIRCLK clock source, choose fast or slow.
741 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
742 * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
743 * the configuration should not be changed. Otherwise, a glitch occurs.
744 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
745 */
746 status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
747
748 /*!
749 * @brief Selects the MCG external reference clock.
750 *
751 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
752 * and waits for the clock source to be stable. Because the external reference
753 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
754 *
755 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
756 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
757 * the configuration should not be changed. Otherwise, a glitch occurs.
758 * @retval kStatus_Success External reference clock set successfully.
759 */
760 status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
761
762 /*!
763 * @brief Set the FLL external reference clock divider value.
764 *
765 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
766 *
767 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
768 */
CLOCK_SetFllExtRefDiv(uint8_t frdiv)769 static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
770 {
771 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
772 }
773
774 /*!
775 * brief Sets the OSC0 clock monitor mode.
776 *
777 * This function sets the OSC0 clock monitor mode. See ref mcg_monitor_mode_t for details.
778 *
779 * param mode Monitor mode to set.
780 */
781 void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
782
783 /*@}*/
784
785 /*! @name MCG clock lock monitor functions. */
786 /*@{*/
787
788 /*!
789 * @brief Sets the OSC0 clock monitor mode.
790 *
791 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
792 *
793 * @param mode Monitor mode to set.
794 */
795 void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
796
797 /*!
798 * @brief Gets the MCG status flags.
799 *
800 * This function gets the MCG clock status flags. All status flags are
801 * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
802 * check a specific flag, compare the return value with the flag.
803 *
804 * Example:
805 * @code
806 * To check the clock lost lock status of OSC0 and PLL0.
807 * uint32_t mcgFlags;
808 *
809 * mcgFlags = CLOCK_GetStatusFlags();
810 *
811 * if (mcgFlags & kMCG_Osc0LostFlag)
812 * {
813 * OSC0 clock lock lost. Do something.
814 * }
815 * if (mcgFlags & kMCG_Pll0LostFlag)
816 * {
817 * PLL0 clock lock lost. Do something.
818 * }
819 * @endcode
820 *
821 * @return Logical OR value of the @ref _mcg_status_flags_t.
822 */
823 uint32_t CLOCK_GetStatusFlags(void);
824
825 /*!
826 * @brief Clears the MCG status flags.
827 *
828 * This function clears the MCG clock lock lost status. The parameter is a logical
829 * OR value of the flags to clear. See @ref _mcg_status_flags_t.
830 *
831 * Example:
832 * @code
833 * To clear the clock lost lock status flags of OSC0 and PLL0.
834 *
835 * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
836 * @endcode
837 *
838 * @param mask The status flags to clear. This is a logical OR of members of the
839 * enumeration @ref _mcg_status_flags_t.
840 */
841 void CLOCK_ClearStatusFlags(uint32_t mask);
842
843 /*@}*/
844
845 /*!
846 * @name OSC configuration
847 * @{
848 */
849
850 /*!
851 * @brief Configures the OSC external reference clock (OSCERCLK).
852 *
853 * This function configures the OSC external reference clock (OSCERCLK).
854 * This is an example to enable the OSCERCLK in normal and stop modes and also set
855 * the output divider to 1:
856 *
857 @code
858 oscer_config_t config =
859 {
860 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
861 .erclkDiv = 1U,
862 };
863
864 OSC_SetExtRefClkConfig(OSC, &config);
865 @endcode
866 *
867 * @param base OSC peripheral address.
868 * @param config Pointer to the configuration structure.
869 */
OSC_SetExtRefClkConfig(OSC_Type * base,oscer_config_t const * config)870 static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
871 {
872 uint8_t reg = base->CR;
873
874 reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK);
875 reg |= config->enableMode;
876
877 base->CR = reg;
878 }
879
880 /*!
881 * @brief Sets the capacitor load configuration for the oscillator.
882 *
883 * This function sets the specified capacitors configuration for the oscillator.
884 * This should be done in the early system level initialization function call
885 * based on the system configuration.
886 *
887 * @param base OSC peripheral address.
888 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
889 *
890 * Example:
891 @code
892 To enable only 2 pF and 8 pF capacitor load, please use like this.
893 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
894 @endcode
895 */
OSC_SetCapLoad(OSC_Type * base,uint8_t capLoad)896 static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
897 {
898 uint8_t reg = base->CR;
899
900 reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK);
901 reg |= capLoad;
902
903 base->CR = reg;
904 }
905
906 /*!
907 * @brief Initializes the OSC0.
908 *
909 * This function initializes the OSC0 according to the board configuration.
910 *
911 * @param config Pointer to the OSC0 configuration structure.
912 */
913 void CLOCK_InitOsc0(osc_config_t const *config);
914
915 /*!
916 * @brief Deinitializes the OSC0.
917 *
918 * This function deinitializes the OSC0.
919 */
920 void CLOCK_DeinitOsc0(void);
921
922 /* @} */
923
924 /*!
925 * @name External clock frequency
926 * @{
927 */
928
929 /*!
930 * @brief Sets the XTAL0 frequency based on board settings.
931 *
932 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
933 */
CLOCK_SetXtal0Freq(uint32_t freq)934 static inline void CLOCK_SetXtal0Freq(uint32_t freq)
935 {
936 g_xtal0Freq = freq;
937 }
938
939 /*!
940 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
941 *
942 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
943 */
CLOCK_SetXtal32Freq(uint32_t freq)944 static inline void CLOCK_SetXtal32Freq(uint32_t freq)
945 {
946 g_xtal32Freq = freq;
947 }
948 /* @} */
949
950 /*!
951 * @name IRCs frequency
952 * @{
953 */
954
955 /*!
956 * @brief Set the Slow IRC frequency based on the trimmed value
957 *
958 * @param freq The Slow IRC frequency input clock frequency in Hz.
959 */
960 void CLOCK_SetSlowIrcFreq(uint32_t freq);
961
962 /*!
963 * @brief Set the Fast IRC frequency based on the trimmed value
964 *
965 * @param freq The Fast IRC frequency input clock frequency in Hz.
966 */
967 void CLOCK_SetFastIrcFreq(uint32_t freq);
968 /* @} */
969
970 /*!
971 * @name MCG auto-trim machine.
972 * @{
973 */
974
975 /*!
976 * @brief Auto trims the internal reference clock.
977 *
978 * This function trims the internal reference clock by using the external clock. If
979 * successful, it returns the kStatus_Success and the frequency after
980 * trimming is received in the parameter @p actualFreq. If an error occurs,
981 * the error code is returned.
982 *
983 * @param extFreq External clock frequency, which should be a bus clock.
984 * @param desireFreq Frequency to trim to.
985 * @param actualFreq Actual frequency after trimming.
986 * @param atms Trim fast or slow internal reference clock.
987 * @retval kStatus_Success ATM success.
988 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
989 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
990 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
991 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
992 */
993 status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
994 /* @} */
995
996 /*! @name MCG mode functions. */
997 /*@{*/
998
999 /*!
1000 * @brief Gets the current MCG mode.
1001 *
1002 * This function checks the MCG registers and determines the current MCG mode.
1003 *
1004 * @return Current MCG mode or error code; See @ref mcg_mode_t.
1005 */
1006 mcg_mode_t CLOCK_GetMode(void);
1007
1008 /*!
1009 * @brief Sets the MCG to FEI mode.
1010 *
1011 * This function sets the MCG to FEI mode. If setting to FEI mode fails
1012 * from the current mode, this function returns an error.
1013 *
1014 * @param dmx32 DMX32 in FEI mode.
1015 * @param drs The DCO range selection.
1016 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
1017 * NULL does not cause a delay.
1018 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1019 * @retval kStatus_Success Switched to the target mode successfully.
1020 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1021 * to a frequency above 32768 Hz.
1022 */
1023 status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1024
1025 /*!
1026 * @brief Sets the MCG to FEE mode.
1027 *
1028 * This function sets the MCG to FEE mode. If setting to FEE mode fails
1029 * from the current mode, this function returns an error.
1030 *
1031 * @param frdiv FLL reference clock divider setting, FRDIV.
1032 * @param dmx32 DMX32 in FEE mode.
1033 * @param drs The DCO range selection.
1034 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
1035 * NULL does not cause a delay.
1036 *
1037 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1038 * @retval kStatus_Success Switched to the target mode successfully.
1039 */
1040 status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1041
1042 /*!
1043 * @brief Sets the MCG to FBI mode.
1044 *
1045 * This function sets the MCG to FBI mode. If setting to FBI mode fails
1046 * from the current mode, this function returns an error.
1047 *
1048 * @param dmx32 DMX32 in FBI mode.
1049 * @param drs The DCO range selection.
1050 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1051 * is not used in FBI mode, this parameter can be NULL. Passing
1052 * NULL does not cause a delay.
1053 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1054 * @retval kStatus_Success Switched to the target mode successfully.
1055 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1056 * to frequency above 32768 Hz.
1057 */
1058 status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1059
1060 /*!
1061 * @brief Sets the MCG to FBE mode.
1062 *
1063 * This function sets the MCG to FBE mode. If setting to FBE mode fails
1064 * from the current mode, this function returns an error.
1065 *
1066 * @param frdiv FLL reference clock divider setting, FRDIV.
1067 * @param dmx32 DMX32 in FBE mode.
1068 * @param drs The DCO range selection.
1069 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1070 * is not used in FBE mode, this parameter can be NULL. Passing NULL
1071 * does not cause a delay.
1072 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1073 * @retval kStatus_Success Switched to the target mode successfully.
1074 */
1075 status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1076
1077 /*!
1078 * @brief Sets the MCG to BLPI mode.
1079 *
1080 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
1081 * from the current mode, this function returns an error.
1082 *
1083 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1084 * @retval kStatus_Success Switched to the target mode successfully.
1085 */
1086 status_t CLOCK_SetBlpiMode(void);
1087
1088 /*!
1089 * @brief Sets the MCG to BLPE mode.
1090 *
1091 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
1092 * from the current mode, this function returns an error.
1093 *
1094 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1095 * @retval kStatus_Success Switched to the target mode successfully.
1096 */
1097 status_t CLOCK_SetBlpeMode(void);
1098
1099 /*!
1100 * @brief Switches the MCG to FBE mode from the external mode.
1101 *
1102 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
1103 * The external clock is used as the system clock source and PLL is disabled. However,
1104 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
1105 * during the mode switch. For example, to switch from PEE mode to FEI mode:
1106 *
1107 * @code
1108 * CLOCK_ExternalModeToFbeModeQuick();
1109 * CLOCK_SetFeiMode(...);
1110 * @endcode
1111 *
1112 * @retval kStatus_Success Switched successfully.
1113 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
1114 */
1115 status_t CLOCK_ExternalModeToFbeModeQuick(void);
1116
1117 /*!
1118 * @brief Switches the MCG to FBI mode from internal modes.
1119 *
1120 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
1121 * The MCGIRCLK is used as the system clock source and PLL is disabled. However,
1122 * FLL settings are not configured. This is a lite function with a small code size, which is useful
1123 * during the mode switch. For example, to switch from PEI mode to FEE mode:
1124 *
1125 * @code
1126 * CLOCK_InternalModeToFbiModeQuick();
1127 * CLOCK_SetFeeMode(...);
1128 * @endcode
1129 *
1130 * @retval kStatus_Success Switched successfully.
1131 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
1132 */
1133 status_t CLOCK_InternalModeToFbiModeQuick(void);
1134
1135 /*!
1136 * @brief Sets the MCG to FEI mode during system boot up.
1137 *
1138 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
1139 * set up MCG during system boot up.
1140 *
1141 * @param dmx32 DMX32 in FEI mode.
1142 * @param drs The DCO range selection.
1143 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1144 *
1145 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1146 * @retval kStatus_Success Switched to the target mode successfully.
1147 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1148 * to frequency above 32768 Hz.
1149 */
1150 status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1151
1152 /*!
1153 * @brief Sets the MCG to FEE mode during system bootup.
1154 *
1155 * This function sets MCG to FEE mode from the reset mode. It can also be used to
1156 * set up the MCG during system boot up.
1157 *
1158 * @param oscsel OSC clock select, OSCSEL.
1159 * @param frdiv FLL reference clock divider setting, FRDIV.
1160 * @param dmx32 DMX32 in FEE mode.
1161 * @param drs The DCO range selection.
1162 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1163 *
1164 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1165 * @retval kStatus_Success Switched to the target mode successfully.
1166 */
1167 status_t CLOCK_BootToFeeMode(
1168 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1169
1170 /*!
1171 * @brief Sets the MCG to BLPI mode during system boot up.
1172 *
1173 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
1174 * set up the MCG during system boot up.
1175 *
1176 * @param fcrdiv Fast IRC divider, FCRDIV.
1177 * @param ircs The internal reference clock to select, IRCS.
1178 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
1179 *
1180 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
1181 * @retval kStatus_Success Switched to the target mode successfully.
1182 */
1183 status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
1184
1185 /*!
1186 * @brief Sets the MCG to BLPE mode during system boot up.
1187 *
1188 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
1189 * set up the MCG during system boot up.
1190 *
1191 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1192 *
1193 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1194 * @retval kStatus_Success Switched to the target mode successfully.
1195 */
1196 status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
1197
1198 /*!
1199 * @brief Sets the MCG to a target mode.
1200 *
1201 * This function sets MCG to a target mode defined by the configuration
1202 * structure. If switching to the target mode fails, this function
1203 * chooses the correct path.
1204 *
1205 * @param config Pointer to the target MCG mode configuration structure.
1206 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
1207 *
1208 * @note If the external clock is used in the target mode, ensure that it is
1209 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
1210 * function.
1211 */
1212 status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
1213
1214 /*@}*/
1215
1216 #if defined(__cplusplus)
1217 }
1218 #endif /* __cplusplus */
1219
1220 /*! @} */
1221
1222 #endif /* _FSL_CLOCK_H_ */
1223
