1/* ------------------------------------------------------------------------- */ 2/* @file: startup_MKM14ZA5.s */ 3/* @purpose: CMSIS Cortex-M0P Core Device Startup File */ 4/* MKM14ZA5 */ 5/* @version: 1.0 */ 6/* @date: 2014-7-22 */ 7/* @build: b231019 */ 8/* ------------------------------------------------------------------------- */ 9/* */ 10/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ 11/* Copyright 2016-2023 NXP */ 12/* SPDX-License-Identifier: BSD-3-Clause */ 13/*****************************************************************************/ 14/* Version: GCC for ARM Embedded Processors */ 15/*****************************************************************************/ 16 .syntax unified 17 .arch armv6-m 18 19 .section .isr_vector, "a" 20 .align 2 21 .globl __isr_vector 22__isr_vector: 23 .long __StackTop /* Top of Stack */ 24 .long Reset_Handler /* Reset Handler */ 25 .long NMI_Handler /* NMI Handler*/ 26 .long HardFault_Handler /* Hard Fault Handler*/ 27 .long 0 /* Reserved*/ 28 .long 0 /* Reserved*/ 29 .long 0 /* Reserved*/ 30 .long 0 /* Reserved*/ 31 .long 0 /* Reserved*/ 32 .long 0 /* Reserved*/ 33 .long 0 /* Reserved*/ 34 .long SVC_Handler /* SVCall Handler*/ 35 .long 0 /* Reserved*/ 36 .long 0 /* Reserved*/ 37 .long PendSV_Handler /* PendSV Handler*/ 38 .long SysTick_Handler /* SysTick Handler*/ 39 40 /* External Interrupts*/ 41 .long DMA0_IRQHandler /* DMA channel 0 transfer complete*/ 42 .long DMA1_IRQHandler /* DMA channel 1 transfer complete*/ 43 .long DMA2_IRQHandler /* DMA channel 2 transfer complete*/ 44 .long DMA3_IRQHandler /* DMA channel 3 transfer complete*/ 45 .long SPI0_IRQHandler /* SPI0 ORed interrupt*/ 46 .long SPI1_IRQHandler /* SPI1 ORed interrupt*/ 47 .long PMC_IRQHandler /* Low-voltage detect, low-voltage warning*/ 48 .long TMR0_IRQHandler /* Quad Timer Channel 0*/ 49 .long TMR1_IRQHandler /* Quad Timer Channel 1*/ 50 .long TMR2_IRQHandler /* Quad Timer Channel 2*/ 51 .long TMR3_IRQHandler /* Quad Timer Channel 3*/ 52 .long PIT0_PIT1_IRQHandler /* PIT0/PIT1 ORed interrupt*/ 53 .long LLWU_IRQHandler /* Low Leakage Wakeup*/ 54 .long FTFA_IRQHandler /* Command complete and read collision*/ 55 .long CMP0_CMP1_IRQHandler /* CMP0/CMP1 ORed interrupt*/ 56 .long Reserved31_IRQHandler /* Reserved interrupt*/ 57 .long ADC_IRQHandler /* ADC interrupt*/ 58 .long PTx_IRQHandler /* Single interrupt vector for GPIOA,GPIOB,GPIOC,GPIOD,GPIOE,GPIOF,GPIOG,GPIOH,GPIOI*/ 59 .long RNGA_IRQHandler /* RNGA interrupt*/ 60 .long UART0_UART1_IRQHandler /* UART0/UART1 ORed interrupt*/ 61 .long UART2_UART3_IRQHandler /* UART2/UART3 ORed interrupt*/ 62 .long AFE_CH0_IRQHandler /* AFE Channel 0*/ 63 .long AFE_CH1_IRQHandler /* AFE Channel 1*/ 64 .long AFE_CH2_IRQHandler /* AFE Channel 2*/ 65 .long AFE_CH3_IRQHandler /* AFE Channel 3*/ 66 .long RTC_IRQHandler /* IRTC interrupt*/ 67 .long I2C0_I2C1_IRQHandler /* I2C0/I2C1 ORed interrupt*/ 68 .long EWM_IRQHandler /* External Watchdog Monitor*/ 69 .long MCG_IRQHandler /* MCG interrupt*/ 70 .long WDOG_IRQHandler /* WDOG ORed interrupt*/ 71 .long LPTMR_IRQHandler /* LPTMR interrupt*/ 72 .long XBAR_IRQHandler /* XBAR interrupt*/ 73 74 .size __isr_vector, . - __isr_vector 75 76/* Flash Configuration */ 77 .section .FlashConfig, "a" 78 .long 0xFFFFFFFF 79 .long 0xFFFFFFFF 80 .long 0xFFFFFFFF 81 .long 0xFFFFFFFE 82 83 .text 84 .thumb 85 86#if defined (__cplusplus) 87#ifdef __REDLIB__ 88#error Redlib does not support C++ 89#endif 90#endif 91/* Reset Handler */ 92 93 .thumb_func 94 .align 2 95 .globl Reset_Handler 96 .weak Reset_Handler 97 .type Reset_Handler, %function 98Reset_Handler: 99 cpsid i /* Mask interrupts */ 100 .equ VTOR, 0xE000ED08 101 ldr r0, =VTOR 102 ldr r1, =__isr_vector 103 str r1, [r0] 104 ldr r2, [r1] 105 msr msp, r2 106#ifndef __NO_SYSTEM_INIT 107 ldr r0,=SystemInit 108 blx r0 109#endif 110/* Loop to copy data from read only memory to RAM. The ranges 111 * of copy from/to are specified by following symbols evaluated in 112 * linker script. 113 * __etext: End of code section, i.e., begin of data sections to copy from. 114 * __data_start__/__data_end__: RAM address range that data should be 115 * copied to. Both must be aligned to 4 bytes boundary. */ 116 117 ldr r1, =__etext 118 ldr r2, =__data_start__ 119 ldr r3, =__data_end__ 120 121 subs r3, r2 122 ble .LC0 123 124.LC1: 125 subs r3, 4 126 ldr r0, [r1,r3] 127 str r0, [r2,r3] 128 bgt .LC1 129.LC0: 130 131#ifdef __STARTUP_CLEAR_BSS 132/* This part of work usually is done in C library startup code. Otherwise, 133 * define this macro to enable it in this startup. 134 * 135 * Loop to zero out BSS section, which uses following symbols 136 * in linker script: 137 * __bss_start__: start of BSS section. Must align to 4 138 * __bss_end__: end of BSS section. Must align to 4 139 */ 140 ldr r1, =__bss_start__ 141 ldr r2, =__bss_end__ 142 143 subs r2, r1 144 ble .LC3 145 146 movs r0, 0 147.LC2: 148 subs r2, 4 149 str r0, [r1, r2] 150 bgt .LC2 151.LC3: 152#endif 153 cpsie i /* Unmask interrupts */ 154#ifndef __START 155#ifdef __REDLIB__ 156#define __START __main 157#else 158#define __START _start 159#endif 160#endif 161#ifndef __ATOLLIC__ 162 ldr r0,=__START 163 blx r0 164#else 165 ldr r0,=__libc_init_array 166 blx r0 167 ldr r0,=main 168 bx r0 169#endif 170 .pool 171 .size Reset_Handler, . - Reset_Handler 172 173 .align 1 174 .thumb_func 175 .weak DefaultISR 176 .type DefaultISR, %function 177DefaultISR: 178 ldr r0, =DefaultISR 179 bx r0 180 .size DefaultISR, . - DefaultISR 181 182 .align 1 183 .thumb_func 184 .weak NMI_Handler 185 .type NMI_Handler, %function 186NMI_Handler: 187 ldr r0,=NMI_Handler 188 bx r0 189 .size NMI_Handler, . - NMI_Handler 190 191 .align 1 192 .thumb_func 193 .weak HardFault_Handler 194 .type HardFault_Handler, %function 195HardFault_Handler: 196 ldr r0,=HardFault_Handler 197 bx r0 198 .size HardFault_Handler, . - HardFault_Handler 199 200 .align 1 201 .thumb_func 202 .weak SVC_Handler 203 .type SVC_Handler, %function 204SVC_Handler: 205 ldr r0,=SVC_Handler 206 bx r0 207 .size SVC_Handler, . - SVC_Handler 208 209 .align 1 210 .thumb_func 211 .weak PendSV_Handler 212 .type PendSV_Handler, %function 213PendSV_Handler: 214 ldr r0,=PendSV_Handler 215 bx r0 216 .size PendSV_Handler, . - PendSV_Handler 217 218 .align 1 219 .thumb_func 220 .weak SysTick_Handler 221 .type SysTick_Handler, %function 222SysTick_Handler: 223 ldr r0,=SysTick_Handler 224 bx r0 225 .size SysTick_Handler, . - SysTick_Handler 226 227 .align 1 228 .thumb_func 229 .weak DMA0_IRQHandler 230 .type DMA0_IRQHandler, %function 231DMA0_IRQHandler: 232 ldr r0,=DMA0_DriverIRQHandler 233 bx r0 234 .size DMA0_IRQHandler, . - DMA0_IRQHandler 235 236 .align 1 237 .thumb_func 238 .weak DMA1_IRQHandler 239 .type DMA1_IRQHandler, %function 240DMA1_IRQHandler: 241 ldr r0,=DMA1_DriverIRQHandler 242 bx r0 243 .size DMA1_IRQHandler, . - DMA1_IRQHandler 244 245 .align 1 246 .thumb_func 247 .weak DMA2_IRQHandler 248 .type DMA2_IRQHandler, %function 249DMA2_IRQHandler: 250 ldr r0,=DMA2_DriverIRQHandler 251 bx r0 252 .size DMA2_IRQHandler, . - DMA2_IRQHandler 253 254 .align 1 255 .thumb_func 256 .weak DMA3_IRQHandler 257 .type DMA3_IRQHandler, %function 258DMA3_IRQHandler: 259 ldr r0,=DMA3_DriverIRQHandler 260 bx r0 261 .size DMA3_IRQHandler, . - DMA3_IRQHandler 262 263 .align 1 264 .thumb_func 265 .weak SPI0_IRQHandler 266 .type SPI0_IRQHandler, %function 267SPI0_IRQHandler: 268 ldr r0,=SPI0_DriverIRQHandler 269 bx r0 270 .size SPI0_IRQHandler, . - SPI0_IRQHandler 271 272 .align 1 273 .thumb_func 274 .weak SPI1_IRQHandler 275 .type SPI1_IRQHandler, %function 276SPI1_IRQHandler: 277 ldr r0,=SPI1_DriverIRQHandler 278 bx r0 279 .size SPI1_IRQHandler, . - SPI1_IRQHandler 280 281 .align 1 282 .thumb_func 283 .weak UART0_UART1_IRQHandler 284 .type UART0_UART1_IRQHandler, %function 285UART0_UART1_IRQHandler: 286 ldr r0,=UART0_UART1_DriverIRQHandler 287 bx r0 288 .size UART0_UART1_IRQHandler, . - UART0_UART1_IRQHandler 289 290 .align 1 291 .thumb_func 292 .weak UART2_UART3_IRQHandler 293 .type UART2_UART3_IRQHandler, %function 294UART2_UART3_IRQHandler: 295 ldr r0,=UART2_UART3_DriverIRQHandler 296 bx r0 297 .size UART2_UART3_IRQHandler, . - UART2_UART3_IRQHandler 298 299 .align 1 300 .thumb_func 301 .weak I2C0_I2C1_IRQHandler 302 .type I2C0_I2C1_IRQHandler, %function 303I2C0_I2C1_IRQHandler: 304 ldr r0,=I2C0_I2C1_DriverIRQHandler 305 bx r0 306 .size I2C0_I2C1_IRQHandler, . - I2C0_I2C1_IRQHandler 307 308 309/* Macro to define default handlers. Default handler 310 * will be weak symbol and just dead loops. They can be 311 * overwritten by other handlers */ 312 .macro def_irq_handler handler_name 313 .weak \handler_name 314 .set \handler_name, DefaultISR 315 .endm 316/* Exception Handlers */ 317 def_irq_handler DMA0_DriverIRQHandler 318 def_irq_handler DMA1_DriverIRQHandler 319 def_irq_handler DMA2_DriverIRQHandler 320 def_irq_handler DMA3_DriverIRQHandler 321 def_irq_handler SPI0_DriverIRQHandler 322 def_irq_handler SPI1_DriverIRQHandler 323 def_irq_handler PMC_IRQHandler 324 def_irq_handler TMR0_IRQHandler 325 def_irq_handler TMR1_IRQHandler 326 def_irq_handler TMR2_IRQHandler 327 def_irq_handler TMR3_IRQHandler 328 def_irq_handler PIT0_PIT1_IRQHandler 329 def_irq_handler LLWU_IRQHandler 330 def_irq_handler FTFA_IRQHandler 331 def_irq_handler CMP0_CMP1_IRQHandler 332 def_irq_handler Reserved31_IRQHandler 333 def_irq_handler ADC_IRQHandler 334 def_irq_handler PTx_IRQHandler 335 def_irq_handler RNGA_IRQHandler 336 def_irq_handler UART0_UART1_DriverIRQHandler 337 def_irq_handler UART2_UART3_DriverIRQHandler 338 def_irq_handler AFE_CH0_IRQHandler 339 def_irq_handler AFE_CH1_IRQHandler 340 def_irq_handler AFE_CH2_IRQHandler 341 def_irq_handler AFE_CH3_IRQHandler 342 def_irq_handler RTC_IRQHandler 343 def_irq_handler I2C0_I2C1_DriverIRQHandler 344 def_irq_handler EWM_IRQHandler 345 def_irq_handler MCG_IRQHandler 346 def_irq_handler WDOG_IRQHandler 347 def_irq_handler LPTMR_IRQHandler 348 def_irq_handler XBAR_IRQHandler 349 350 .end 351
