1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 */ 9 10 #ifndef _RTE_DEVICE_H 11 #define _RTE_DEVICE_H 12 13 #include "pin_mux.h" 14 15 /* UART Select. */ 16 /* Select LPUART0 - LPUART1. */ 17 /* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled 18 * LPUART instance. */ 19 #define RTE_USART0 0 20 #define RTE_USART0_DMA_EN 0 21 #define RTE_USART1 0 22 #define RTE_USART1_DMA_EN 0 23 /* Select UART2. */ 24 #define RTE_USART2 1 25 #define RTE_USART2_DMA_EN 0 26 27 /* UART configuration. */ 28 #define USART_RX_BUFFER_LEN 64 29 #define USART0_RX_BUFFER_ENABLE 0 30 #define USART1_RX_BUFFER_ENABLE 0 31 #define USART2_RX_BUFFER_ENABLE 0 32 33 #define RTE_USART0_PIN_INIT LPUART0_InitPins 34 #define RTE_USART0_PIN_DEINIT LPUART0_DeinitPins 35 #define RTE_USART0_DMA_TX_CH 0 36 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Tx 37 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0 38 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 39 #define RTE_USART0_DMA_RX_CH 1 40 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Rx 41 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0 42 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 43 44 #define RTE_USART1_PIN_INIT LPUART1_InitPins 45 #define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins 46 #define RTE_USART1_DMA_TX_CH 0 47 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Tx 48 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0 49 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 50 #define RTE_USART1_DMA_RX_CH 1 51 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Rx 52 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0 53 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 54 55 #define RTE_USART2_PIN_INIT LPUART2_InitPins 56 #define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins 57 #define RTE_USART2_DMA_TX_CH 0 58 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Tx 59 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0 60 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 61 #define RTE_USART2_DMA_RX_CH 1 62 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Rx 63 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0 64 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 65 66 /* I2C Select, I2C0 - I2C1. */ 67 /* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. 68 */ 69 #define RTE_I2C0 0 70 #define RTE_I2C0_DMA_EN 0 71 #define RTE_I2C1 0 72 #define RTE_I2C1_DMA_EN 0 73 74 /*I2C configuration*/ 75 #define RTE_I2C0_Master_DMA_BASE DMA0 76 #define RTE_I2C0_Master_DMA_CH 0 77 #define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0 78 #define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0 79 80 #define RTE_I2C1_Master_DMA_BASE DMA0 81 #define RTE_I2C1_Master_DMA_CH 1 82 #define RTE_I2C1_Master_DMAMUX_BASE DMAMUX0 83 #define RTE_I2C1_Master_PERI_SEL kDmaRequestMux0I2C1 84 85 /* SPI select, SPI0 - SPI1. */ 86 /* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. 87 */ 88 #define RTE_SPI0 0 89 #define RTE_SPI0_DMA_EN 0 90 #define RTE_SPI1 0 91 #define RTE_SPI1_DMA_EN 0 92 93 /* SPI configuration. */ 94 #define RTE_SPI0_PIN_INIT SPI0_InitPins 95 #define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins 96 #define RTE_SPI0_DMA_TX_CH 0 97 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx 98 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0 99 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 100 #define RTE_SPI0_DMA_RX_CH 1 101 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx 102 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0 103 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 104 105 #define RTE_SPI1_PIN_INIT SPI1_InitPins 106 #define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins 107 #define RTE_SPI1_DMA_TX_CH 2 108 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1Tx 109 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX0 110 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 111 #define RTE_SPI1_DMA_RX_CH 3 112 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1Rx 113 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX0 114 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 115 116 #endif /* _RTE_DEVICE_H */ 117
