1 /* 2 * Copyright 2021 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _RTE_DEVICE_H 9 #define _RTE_DEVICE_H 10 11 #include "pin_mux.h" 12 13 /* UART Select, LPUART0 - LPUART2. */ 14 /* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled 15 * LPUART instance. */ 16 #define RTE_USART0 0 17 #define RTE_USART0_DMA_EN 0 18 #define RTE_USART1 0 19 #define RTE_USART1_DMA_EN 0 20 #define RTE_USART2 0 21 #define RTE_USART2_DMA_EN 0 22 23 /* UART configuration. */ 24 #define USART_RX_BUFFER_LEN 64 25 #define USART0_RX_BUFFER_ENABLE 0 26 #define USART1_RX_BUFFER_ENABLE 0 27 #define USART2_RX_BUFFER_ENABLE 0 28 29 #define RTE_USART0_PIN_INIT LPUART0_InitPins 30 #define RTE_USART0_PIN_DEINIT LPUART0_DeinitPins 31 #define RTE_USART0_DMA_TX_CH 0 32 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Tx 33 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX 34 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 35 #define RTE_USART0_DMA_RX_CH 1 36 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Rx 37 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX 38 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 39 40 #define RTE_USART1_PIN_INIT LPUART1_InitPins 41 #define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins 42 #define RTE_USART1_DMA_TX_CH 0 43 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Tx 44 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX 45 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 46 #define RTE_USART1_DMA_RX_CH 1 47 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART1Rx 48 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX 49 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 50 51 #define RTE_USART2_PIN_INIT LPUART2_InitPins 52 #define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins 53 #define RTE_USART2_DMA_TX_CH 0 54 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART2Tx 55 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX 56 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 57 #define RTE_USART2_DMA_RX_CH 1 58 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART2Rx 59 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX 60 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 61 62 /* I2C Select, LPI2C0. */ 63 /* User needs to provide the implementation of LPI2CX_GetFreq/LPI2CX_InitPins/LPI2CX_DeinitPins for the enabled LPI2C 64 * instance. */ 65 #define RTE_I2C0 0 66 #define RTE_I2C0_DMA_EN 0 67 68 /* LPI2C configuration. */ 69 #define RTE_I2C0_PIN_INIT LPI2C0_InitPins 70 #define RTE_I2C0_PIN_DEINIT LPI2C0_DeinitPins 71 #define RTE_I2C0_DMA_TX_CH 0 72 #define RTE_I2C0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C0Tx 73 #define RTE_I2C0_DMA_TX_DMAMUX_BASE DMAMUX 74 #define RTE_I2C0_DMA_TX_DMA_BASE DMA0 75 #define RTE_I2C0_DMA_RX_CH 1 76 #define RTE_I2C0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C0Rx 77 #define RTE_I2C0_DMA_RX_DMAMUX_BASE DMAMUX 78 #define RTE_I2C0_DMA_RX_DMA_BASE DMA0 79 80 /* SPI Select, LPSPI0. */ 81 /* User needs to provide the implementation of LPSPIX_GetFreq/LPSPIX_InitPins/LPSPIX_DeinitPins for the enabled LPSPI 82 * instance. */ 83 #define RTE_SPI0 0 84 #define RTE_SPI0_DMA_EN 0 85 86 /* SPI configuration. */ 87 #define RTE_SPI0_PCS_TO_SCK_DELAY 1000 88 #define RTE_SPI0_SCK_TO_PSC_DELAY 1000 89 #define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000 90 #define RTE_SPI0_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs3) 91 #define RTE_SPI0_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs3) 92 #define RTE_SPI0_PIN_INIT LPSPI0_InitPins 93 #define RTE_SPI0_PIN_DEINIT LPSPI0_DeinitPins 94 #define RTE_SPI0_DMA_TX_CH 0 95 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI0Tx 96 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX 97 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 98 #define RTE_SPI0_DMA_RX_CH 1 99 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI0Rx 100 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX 101 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 102 103 #endif /* _RTE_DEVICE_H */ 104
