1 /*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #ifndef _FSL_PORT_H_
8 #define _FSL_PORT_H_
9
10 #include "fsl_common.h"
11
12 /*!
13 * @addtogroup port
14 * @{
15 */
16
17 /*******************************************************************************
18 * Definitions
19 ******************************************************************************/
20
21 /*! @name Driver version */
22 /*@{*/
23 /*! Version 2.0.2. */
24 #define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
25 /*@}*/
26
27 #define FSL_PORT_FILTER_SELECT_BITMASK (0x3U) /*!< The IOFLT Filter selection bit mask . */
28 #define PORT_PINNUMS_EACHPORT 8U /* PORT pin numbers in each PTA/PTB etc. */
29
30 /*! @brief Module or peripheral for port pin selection */
31 typedef enum _port_module_t
32 {
33 kPORT_NMI = SIM_SOPT_NMIE_MASK, /*!< NMI port pin select. */
34 kPORT_RESET = SIM_SOPT_RSTPE_MASK, /*!< RESET pin select. */
35 kPORT_SWDE = SIM_SOPT_SWDE_MASK, /*!< Single wire debug port pin. */
36 kPORT_I2C0 = SIM_PINSEL_I2C0PS_MASK, /*!< I2C0 Port pin select. */
37 kPORT_SPI0 = SIM_PINSEL_SPI0PS_MASK, /*!< SPI0 port pin select. */
38 kPORT_UART0 = SIM_PINSEL_UART0PS_MASK, /*!< UART0 port pin select. */
39 kPORT_FTM0CH0 = SIM_PINSEL_FTM0PS0_MASK, /*!< FTM0_CH0 port pin select. */
40 kPORT_FTM0CH1 = SIM_PINSEL_FTM0PS1_MASK, /*!< FTM0_CH1 port pin select. */
41 kPORT_FTM2CH2 = SIM_PINSEL_FTM2PS2_MASK, /*!< FTM2_CH2 port pin select. */
42 kPORT_FTM2CH3 = SIM_PINSEL_FTM2PS3_MASK, /*!< FTM2_CH3 port pin select. */
43 kPORT_FTM0CLK = SIM_PINSEL_FTM0CLKPS_MASK, /*!< FTM0 clock pin select. */
44 kPORT_FTM2CLK = SIM_PINSEL_FTM2CLKPS_MASK, /*!< FTM2 clock pin select. */
45 kPORT_PWTCLK = (int)SIM_PINSEL_PWTCLKPS_MASK /*!< PWT clock pin select. */
46 } port_module_t;
47
48 /*! @brief Port type */
49 typedef enum _port_type_t
50 {
51 kPORT_PTA = 0U, /*!< PORT PTA. */
52 kPORT_PTB = 1U, /*!< PORT PTB. */
53 kPORT_PTC = 2U /*!< PORT PTC. */
54 } port_type_t;
55
56 /*! @brief Pin number, Notice this index enum has been deprecated and it will be removed in the next release. */
57 typedef enum _port_pin_index_t
58 {
59 kPORT_PinIdx0 = 0U, /*!< PORT PIN index 0. */
60 kPORT_PinIdx1 = 1U, /*!< PORT PIN index 1. */
61 kPORT_PinIdx2 = 2U, /*!< PORT PIN index 2. */
62 kPORT_PinIdx3 = 3U, /*!< PORT PIN index 3. */
63 kPORT_PinIdx4 = 4U, /*!< PORT PIN index 4. */
64 kPORT_PinIdx5 = 5U, /*!< PORT PIN index 5. */
65 kPORT_PinIdx6 = 6U, /*!< PORT PIN index 6. */
66 kPORT_PinIdx7 = 7U /*!< PORT PIN index 7. */
67 } port_pin_index_t;
68
69 /*! @brief Pin selection */
70 typedef enum _port_pin_select_t
71 {
72 kPORT_NMI_OTHERS = 0U, /*!< PTB4/FTM2_CH4 etc function as PTB4/FTM2_CH4 etc */
73 kPORT_NMI_NMIE = 1U, /*!< PTB4/FTM2_CH4 etc function as NMI. */
74 kPORT_RST_OTHERS = 0U, /*!< PTA5/IRQ etc function as PTA5/IRQ etc. */
75 kPORT_RST_RSTPE = 1U, /*!< PTA5/IRQ etc function as REST. */
76 kPORT_SWDE_OTHERS = 0U, /*!< PTA4/ACMP0 etc function as PTA4/ACMP0 etc. */
77 kPORT_SWDE_SWDE = 1U, /*!< PTA4/ACMP0 etc function as SWD. */
78 kPORT_I2C0_SCLPTA3_SDAPTA2 = 0U, /*!< I2C0_SCL and I2C0_SDA are mapped on PTA3 and PTA2, respectively. */
79 kPORT_I2C0_SCLPTB7_SDAPTB6 = 1U, /*!< I2C0_SCL and I2C0_SDA are mapped on PTB7 and PTB6, respectively. */
80 kPORT_SPI0_SCKPTB2_MOSIPTB3_MISOPTB4_PCSPTB5 = 0U, /*!< SPI0_SCK/MOSI/MISO/PCS0 are mapped on PTB2/PTB3/PTB4/PTB5.*/
81 kPORT_SPI0_SCKPTA6_MOSIPTA7_MISOPTB1_PCSPTB0 =
82 1U, /*!< SPI0_SCK/MOSI/MISO/PCS0 are mapped on PTA6/PTA7/PTB1/PTB0. */
83 kPORT_UART0_RXPTB0_TXPTB1 = 0U, /*!< UART0_RX and UART0_TX are mapped on PTB0 and PTB1. */
84 kPORT_UART0_RXPTA2_TXPTA3 = 1U, /*!< UART0_RX and UART0_TX are mapped on PTA2 and PTA3. */
85 kPORT_FTM0_CH0_PTA0 = 0U, /*!< FTM0_CH0 channels are mapped on PTA0. */
86 kPORT_FTM0_CH0_PTB2 = 1U, /*!< FTM0_CH0 channels are mapped on PTB2. */
87 kPORT_FTM0_CH1_PTA1 = 0U, /*!< FTM0_CH1 channels are mapped on PTA1. */
88 kPORT_FTM0_CH1_PTB3 = 1U, /*!< FTM0_CH1 channels are mapped on PTB3. */
89 kPORT_FTM2_CH2_PTC2 = 0U, /*!< FTM2_CH2 channels are mapped on PTC2. */
90 kPORT_FTM2_CH2_PTC4 = 1U, /*!< FTM2_CH2 channels are mapped on PTD2. */
91 kPORT_FTM2_CH3_PTC3 = 0U, /*!< FTM2_CH3 channels are mapped on PTC3. */
92 kPORT_FTM2_CH3_PTC5 = 1U, /*!< FTM2_CH3 channels are mapped on PTC5. */
93 kPORT_FTM0CLK_TCLK1 = 0U, /*!< FTM0 CLK using the TCLK1 pin. */
94 kPORT_FTM0CLK_TCLK2 = 1U, /*!< FTM0 CLK using the TCLK2 pin. */
95 kPORT_FTM2CLK_TCLK1 = 0U, /*!< FTM2 CLK using the TCLK1 pin. */
96 kPORT_FTM2CLK_TCLK2 = 1U, /*!< FTM2 CLK using the TCLK2 pin. */
97 kPORT_PWTCLK_TCLK1 = 0U, /*!< PWT CLK using the TCLK1 pin. */
98 kPORT_PWTCLK_TCLK2 = 1U, /*!< PWT CLK using the TCLK2 pin. */
99 } port_pin_select_t;
100
101 /*! @brief The PORT pins for input glitch filter configure */
102 typedef enum _port_filter_pin_t
103 {
104 kPORT_FilterPTA = PORT_IOFLT_FLTA_SHIFT, /*!< Filter for input from PTA. */
105 kPORT_FilterPTB = PORT_IOFLT_FLTB_SHIFT, /*!< Filter for input from PTB. */
106 kPORT_FilterPTC = PORT_IOFLT_FLTC_SHIFT, /*!< Filter for input from PTC. */
107 kPORT_FilterIIC = PORT_IOFLT_FLTIIC_SHIFT, /*!< Filter for input from I2C. */
108 kPORT_FilterFTM0 = PORT_IOFLT_FLTFTM0_SHIFT, /*!< Filter for input from FTM0. */
109 kPORT_FilterPWT = PORT_IOFLT_FLTPWT_SHIFT, /*!< Filter for input from PWT. */
110 kPORT_FilterRST = PORT_IOFLT_FLTRST_SHIFT, /*!< Filter for input from RESET/IRQ. */
111 kPORT_FilterKBI0 = PORT_IOFLT_FLTKBI0_SHIFT, /*!< Filter for input from KBI0. */
112 kPORT_FilterKBI1 = PORT_IOFLT_FLTKBI1_SHIFT, /*!< Filter for input from KBI1. */
113 kPORT_FilterNMI = PORT_IOFLT_FLTNMI_SHIFT, /*!< Filter for input from NMI. */
114 } port_filter_pin_t;
115
116 /*! @brief The Filter selection for input pins */
117 typedef enum _port_filter_select_t
118 {
119 kPORT_BUSCLK_OR_NOFILTER =
120 0U, /*!< Filter section BUSCLK for PTA~PTC, No filter for REST/KBI0/KBI1/NMI/PWT/FTM0/I2C. */
121 kPORT_FILTERDIV1 = 1U, /*!< Filter Division Set 1. */
122 kPORT_FILTERDIV2 = 2U, /*!< Filter Division Set 2. */
123 kPORT_FILTERDIV3_OR_BUSCLK = 3U /*!< Filter Division Set 3. */
124 } port_filter_select_t;
125
126 /*! @brief Port pin for high driver enable/disable control. */
127 typedef enum _port_highdrive_pin_t
128 {
129 kPORT_HighDrive_PTB5 = PORT_HDRVE_PTB5_MASK, /*!< PTB5. */
130 kPORT_HighDrive_PTC1 = PORT_HDRVE_PTC1_MASK, /*!< PTC1. */
131 kPORT_HighDrive_PTC5 = PORT_HDRVE_PTC5_MASK /*!< PTC5. */
132 } port_highdrive_pin_t;
133
134 /*******************************************************************************
135 * API
136 ******************************************************************************/
137
138 #if defined(__cplusplus)
139 extern "C" {
140 #endif
141
142 /*! @name Configuration */
143 /*@{*/
144
145 /*!
146 * @brief Selects pin for modules.
147 *
148 * This API is used to select the port pin for the module with multiple port pin
149 * selection. For example the FTM Channel 0 can be mapped to ether PTA0 or PTB2.
150 * Select FTM channel 0 map to PTA0 port pin as:
151 * @code
152 * PORT_SetPinSelect(kPORT_FTM0CH0, kPORT_FTM0_CH0_PTA0);
153 * @endcode
154 *
155 * @note： This API doesn't support to select specified ALT for a given port pin.
156 * The ALT feature is automatically selected by hardware according to the
157 * ALT priority:
158 * Low -----> high:
159 * Alt1, Alt2, …
160 * when peripheral modules has been enabled.
161 *
162 * If you want to select a specified ALT for a given port pin, please add two more
163 * steps after calling PORT_SetPinSelect:
164 * 1. Enable module or the port control in the module for the ALT you want to select.
165 * For I2C ALT feature:all port enable is controlled by the module enable, so
166 * set IICEN in I2CX_C1 to enable the port pins for I2C feature.
167 * For KBI ALT feature:each port pin is controlled independently by each bit in KBIx_PE.
168 * set related bit in this register to enable the KBI feature in the port pin.
169 * 2. Make sure there is no module enabled with higher priority than the ALT module feature
170 * you want to select.
171 *
172 * @param module Modules for pin selection.
173 * For NMI/RST module are write-once attribute after reset.
174 * @param pin Port pin selection for modules.
175 *
176 */
177 void PORT_SetPinSelect(port_module_t module, port_pin_select_t pin);
178
179 /*!
180 * @brief Selects the glitch filter for input pins.
181 *
182 * @param base PORT peripheral base pointer.
183 * @param port PORT pin, see "port_filter_pin_t".
184 * @param filter Filter select, see "port_filter_select_t".
185 */
PORT_SetFilterSelect(PORT_Type * base,port_filter_pin_t port,port_filter_select_t filter)186 static inline void PORT_SetFilterSelect(PORT_Type *base, port_filter_pin_t port, port_filter_select_t filter)
187 {
188 uint32_t fltReg;
189
190 /* Clear the filed to zero. */
191 fltReg = base->IOFLT & ~((uint32_t)FSL_PORT_FILTER_SELECT_BITMASK << (uint32_t)port);
192 /* Set the filter selection. */
193 base->IOFLT = ((uint32_t)filter << (uint32_t)port) | fltReg;
194 }
195
196 /*!
197 * @brief Sets the width threshold for glitch filter division set 1.
198 *`
199 * @param base PORT peripheral base pointer.
200 * @param threshold PORT glitch filter width threshold, take refer to reference manual for detail information.
201 * 0 - LPOCLK
202 * 1 - LPOCLK/2
203 * 2 - LPOCLK/4
204 * 3 - LPOCLK/8
205 * 4 - LPOCLK/16
206 * 5 - LPOCLK/32
207 * 6 - LPOCLK/64
208 * 7 - LPOCLK/128
209 */
PORT_SetFilterDIV1WidthThreshold(PORT_Type * base,uint8_t threshold)210 static inline void PORT_SetFilterDIV1WidthThreshold(PORT_Type *base, uint8_t threshold)
211 {
212 uint32_t fltReg;
213
214 fltReg = base->IOFLT & ~PORT_IOFLT_FLTDIV1_MASK;
215 base->IOFLT = fltReg | PORT_IOFLT_FLTDIV1(threshold);
216 }
217
218 /*!
219 * @brief Sets the width threshold for glitch filter division set 2.
220 *`
221 * @param base PORT peripheral base pointer.
222 * @param threshold PORT glitch filter width threshold, take refer to reference manual for detail information.
223 * 0 - BUSCLK/32
224 * 1 - BUSCLK/64
225 * 2 - BUSCLK/128
226 * 3 - BUSCLK/256
227 * 4 - BUSCLK/512
228 * 5 - BUSCLK/1024
229 * 6 - BUSCLK/2048
230 * 7 - BUSCLK/4096
231 */
PORT_SetFilterDIV2WidthThreshold(PORT_Type * base,uint8_t threshold)232 static inline void PORT_SetFilterDIV2WidthThreshold(PORT_Type *base, uint8_t threshold)
233 {
234 uint32_t fltReg;
235
236 fltReg = base->IOFLT & ~PORT_IOFLT_FLTDIV2_MASK;
237 base->IOFLT = fltReg | PORT_IOFLT_FLTDIV2(threshold);
238 }
239
240 /*!
241 * @brief Sets the width threshold for glitch filter division set 3.
242 *`
243 * @param base PORT peripheral base pointer.
244 * @param threshold PORT glitch filter width threshold, take refer to reference manual for detail information.
245 * 0 - BUSCLK/2
246 * 1 - BUSCLK/4
247 * 2 - BUSCLK/8
248 * 3 - BUSCLK/16
249 */
PORT_SetFilterDIV3WidthThreshold(PORT_Type * base,uint8_t threshold)250 static inline void PORT_SetFilterDIV3WidthThreshold(PORT_Type *base, uint8_t threshold)
251 {
252 uint32_t fltReg;
253
254 fltReg = base->IOFLT & ~PORT_IOFLT_FLTDIV3_MASK;
255 base->IOFLT = fltReg | PORT_IOFLT_FLTDIV3(threshold);
256 }
257
258 /*!
259 * @brief Enables or disables the port pull up.
260 *
261 * @param base PORT peripheral base pointer.
262 * @param port PORT type, such as PTA/PTB/PTC etc, see "port_type_t".
263 * @param num PORT pin number, such as 0, 1, 2....
264 * For PTC, there are only six pins from 0 ~ 5, the PTC6, PTC7 are not exists in this device.
265 * so when set PTC please don't set the 6 and 7, take refer to the reference manual.
266 * @param enable Enable or disable the pull up feature switch.
267 */
PORT_SetPinPullUpEnable(PORT_Type * base,port_type_t port,uint8_t num,bool enable)268 static inline void PORT_SetPinPullUpEnable(PORT_Type *base, port_type_t port, uint8_t num, bool enable)
269 {
270 if (enable)
271 {
272 /* Enable the pull up */
273 base->PUEL |= (1UL << (PORT_PINNUMS_EACHPORT * (uint32_t)port + (uint32_t)num));
274 }
275 else
276 {
277 /* Disable the pull up */
278 base->PUEL &= ~(1UL << (PORT_PINNUMS_EACHPORT * (uint32_t)port + (uint32_t)num));
279 }
280 }
281
282 /*!
283 * @brief Set High drive for port pins.
284 *
285 * @param base PORT peripheral base pointer.
286 * @param pin PORT pin support high drive.
287 * @param enable Enable or disable the high driver feature switch.
288 */
PORT_SetHighDriveEnable(PORT_Type * base,port_highdrive_pin_t pin,bool enable)289 static inline void PORT_SetHighDriveEnable(PORT_Type *base, port_highdrive_pin_t pin, bool enable)
290 {
291 if (enable)
292 {
293 base->HDRVE |= (uint32_t)pin;
294 }
295 else
296 {
297 base->HDRVE &= ~(uint32_t)pin;
298 }
299 }
300
301 /*@}*/
302
303 #if defined(__cplusplus)
304 }
305 #endif
306
307 /*! @}*/
308
309 #endif /* _FSL_PORT_H_ */
310
