1 /* 2 ** ################################################################### 3 ** Version: rev. 1.0, 2017-05-19 4 ** Build: b210915 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2021 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2017-05-19) 20 ** Initial version. 21 ** 22 ** ################################################################### 23 */ 24 25 #ifndef _MKE04Z4_FEATURES_H_ 26 #define _MKE04Z4_FEATURES_H_ 27 28 /* SOC module features */ 29 30 /* @brief ACMP availability on the SoC. */ 31 #define FSL_FEATURE_SOC_ACMP_COUNT (2) 32 /* @brief ADC availability on the SoC. */ 33 #define FSL_FEATURE_SOC_ADC_COUNT (1) 34 /* @brief CRC availability on the SoC. */ 35 #define FSL_FEATURE_SOC_CRC_COUNT (1) 36 /* @brief FGPIO availability on the SoC. */ 37 #define FSL_FEATURE_SOC_FGPIO_COUNT (1) 38 /* @brief FTM availability on the SoC. */ 39 #define FSL_FEATURE_SOC_FTM_COUNT (2) 40 /* @brief FTMRE availability on the SoC. */ 41 #define FSL_FEATURE_SOC_FTMRE_COUNT (1) 42 /* @brief GPIO availability on the SoC. */ 43 #define FSL_FEATURE_SOC_GPIO_COUNT (1) 44 /* @brief I2C availability on the SoC. */ 45 #define FSL_FEATURE_SOC_I2C_COUNT (1) 46 /* @brief ICS availability on the SoC. */ 47 #define FSL_FEATURE_SOC_ICS_COUNT (1) 48 /* @brief IRQ availability on the SoC. */ 49 #define FSL_FEATURE_SOC_IRQ_COUNT (1) 50 /* @brief KBI availability on the SoC. */ 51 #define FSL_FEATURE_SOC_KBI_COUNT (2) 52 /* @brief MCM availability on the SoC. */ 53 #define FSL_FEATURE_SOC_MCM_COUNT (1) 54 /* @brief OSC availability on the SoC. */ 55 #define FSL_FEATURE_SOC_OSC_COUNT (1) 56 /* @brief PIT availability on the SoC. */ 57 #define FSL_FEATURE_SOC_PIT_COUNT (1) 58 /* @brief PMC availability on the SoC. */ 59 #define FSL_FEATURE_SOC_PMC_COUNT (1) 60 /* @brief PORT availability on the SoC. */ 61 #define FSL_FEATURE_SOC_PORT_COUNT (1) 62 /* @brief PWT availability on the SoC. */ 63 #define FSL_FEATURE_SOC_PWT_COUNT (1) 64 /* @brief ROM availability on the SoC. */ 65 #define FSL_FEATURE_SOC_ROM_COUNT (1) 66 /* @brief RTC availability on the SoC. */ 67 #define FSL_FEATURE_SOC_RTC_COUNT (1) 68 /* @brief SIM availability on the SoC. */ 69 #define FSL_FEATURE_SOC_SIM_COUNT (1) 70 /* @brief SPI availability on the SoC. */ 71 #define FSL_FEATURE_SOC_SPI_COUNT (1) 72 /* @brief UART availability on the SoC. */ 73 #define FSL_FEATURE_SOC_UART_COUNT (1) 74 /* @brief WDOG availability on the SoC. */ 75 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 76 77 /* ADC module features */ 78 79 /* @brief Has status and control register 5. */ 80 #define FSL_FEATURE_ADC_HAS_SC5_REG (1) 81 /* @brief Has hardware trigger multiple conversion enable. */ 82 #define FSL_FEATURE_ADC_HAS_SC4_HTRGME (1) 83 84 /* CRC module features */ 85 86 /* @brief Has data register with name CRC */ 87 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 88 89 /* FGPIO module features */ 90 91 /* No feature definitions */ 92 93 /* FTM module features */ 94 95 /* @brief Number of channels. */ 96 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) (8) 97 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 98 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 99 /* @brief Has extended deadtime value. */ 100 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 101 /* @brief Enable pwm output for the module. */ 102 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) 103 /* @brief Has half-cycle reload for the module. */ 104 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) 105 /* @brief Has reload interrupt. */ 106 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) 107 /* @brief Has reload initialization trigger. */ 108 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) 109 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 110 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (0) 111 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 112 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) 113 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 114 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) 115 /* @brief Has no QDCTRL. */ 116 #define FSL_FEATURE_FTM_HAS_NO_QDCTRL (1) 117 /* @brief If instance has only TPM function. */ 118 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) \ 119 (((x) == FTM0) ? (1) : \ 120 (((x) == FTM2) ? (0) : (-1))) 121 /* @brief TPM Has no CONF. */ 122 #define FSL_FEATURE_TPM_HAS_NO_CONF (1) 123 /* @brief There is CLKS bit in SC register. */ 124 #define FSL_FEATURE_TPM_HAS_SC_CLKS (1) 125 /* @brief Wait CnV register is updated after CnV register is written. */ 126 #define FSL_FEATURE_TPM_WAIT_CnV_REGISTER_UPDATE (1) 127 /* @brief CHF is cleared by write a 0 to the CHF bit in CnSC register. */ 128 #define FSL_FEATURE_TPM_CnSC_CHF_WRITE_0_CLEAR (1) 129 /* @brief Has no STATUS. */ 130 #define FSL_FEATURE_TPM_HAS_NO_STATUS (1) 131 /* @brief Number of channels. */ 132 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ 133 (((x) == FTM0) ? (2) : \ 134 (((x) == FTM2) ? (-1) : (-1))) 135 /* @brief Whether TRIG register has effect. */ 136 #define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (0) 137 /* @brief Whether POL register has effect. */ 138 #define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (0) 139 /* @brief Whether 32 bits counter has effect. */ 140 #define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) (0) 141 142 /* FTMRE module features */ 143 144 /* @brief Is of type FTMRE. */ 145 #define FSL_FEATURE_FLASH_IS_FTMRE (1) 146 /* @brief Is of type FTMRH. */ 147 #define FSL_FEATURE_FLASH_IS_FTMRH (0) 148 /* @brief Has EEPROM region protection (register FEPROT). */ 149 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 150 /* @brief Has flash cache control in FMC module. */ 151 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 152 /* @brief Has flash cache control in MCM module. */ 153 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 154 /* @brief P-Flash higher region start address. */ 155 #define FSL_FEATURE_FLASH_PFLASH_HIGH_START_ADDRESS (0x00007FFF) 156 /* @brief P-Flash start address. */ 157 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 158 /* @brief P-Flash block count. */ 159 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 160 /* @brief P-Flash block size. */ 161 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (8192) 162 /* @brief P-Flash sector size. */ 163 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (512) 164 /* @brief P-Flash write unit size. */ 165 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 166 /* @brief P-Flash data path width. */ 167 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) 168 /* @brief Has EEPROM memory. */ 169 #define FSL_FEATURE_FLASH_HAS_EEPROM (0) 170 /* @brief EEPROM start address. */ 171 #define FSL_FEATURE_FLASH_EEPROM_START_ADDRESS (0x10000000) 172 /* @brief EEPROM block count. */ 173 #define FSL_FEATURE_FLASH_EEPROM_BLOCK_COUNT (0) 174 /* @brief EEPROM block size . */ 175 #define FSL_FEATURE_FLASH_EEPROM_BLOCK_SIZE (0) 176 /* @brief EEPROM sector size. */ 177 #define FSL_FEATURE_FLASH_EEPROM_BLOCK_SECTOR_SIZE (0) 178 /* @brief EEPROM write unit size. */ 179 #define FSL_FEATURE_FLASH_EEPROM_BLOCK_WRITE_UNIT_SIZE (0) 180 /* @brief EEPROM data path width. */ 181 #define FSL_FEATURE_FLASH_EEPROM_BLOCK_DATA_PATH_WIDTH (0) 182 /* @brief Has 0x01 Erase Verify All Blocks command. */ 183 #define FSL_FEATURE_FLASH_HAS_ERASE_VERIFY_ALL_BLOCKS_CMD (1) 184 /* @brief Has 0x02 Erase Verify Block command. */ 185 #define FSL_FEATURE_FLASH_HAS_ERASE_VERIFY_BLOCK_CMD (1) 186 /* @brief Has 0x03 Erase Verify Flash Section command. */ 187 #define FSL_FEATURE_FLASH_HAS_ERASE_VERIFY_FLASH_SECTION_CMD (1) 188 /* @brief Has 0x04 Read Once command. */ 189 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 190 /* @brief Has 0x06 Program Flash command. */ 191 #define FSL_FEATURE_FLASH_HAS_PROGRAM_FLASH_CMD (1) 192 /* @brief Has 0x07 Program Once command. */ 193 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 194 /* @brief Has 0x08 Erase All Blocks command. */ 195 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 196 /* @brief Has 0x09 Erase Flash Block command. */ 197 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 198 /* @brief Has 0x0A Erase Flash Sector command. */ 199 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 200 /* @brief Has 0x0B Unsecure Flash command. */ 201 #define FSL_FEATURE_FLASH_HAS_UNSECURE_FLASH_CMD (1) 202 /* @brief Has 0x0C Verify Backdoor Access Key command. */ 203 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 204 /* @brief Has 0x0D Set User Margin Level command. */ 205 #define FSL_FEATURE_FLASH_HAS_SET_USER_MARGIN_LEVEL_CMD (1) 206 /* @brief Has 0x0E Set Factory Margin Level command. */ 207 #define FSL_FEATURE_FLASH_HAS_SET_FACTORY_MARGIN_LEVEL_CMD (1) 208 /* @brief Has 0x0F Configure NVM command. */ 209 #define FSL_FEATURE_FLASH_HAS_CONFIGURE_NVM_CMD (0) 210 /* @brief Has 0x10 Erase Verify EEPROM Section command. */ 211 #define FSL_FEATURE_FLASH_HAS_ERASE_VERIFY_EEPROM_SECTION_CMD (0) 212 /* @brief Has 0x11 Program EEPROM command. */ 213 #define FSL_FEATURE_FLASH_HAS_PROGRAM_EEPROM_CMD (0) 214 /* @brief Has 0x12 Erase EEPROM Sector command. */ 215 #define FSL_FEATURE_FLASH_HAS_ERASE_EEPROM_SECTOR_CMD (0) 216 /* @brief P-Flash Erase sector command address alignment. */ 217 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 218 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 219 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 220 /* @brief P-Flash Program flash command address alignment. */ 221 #define FSL_FEATURE_FLASH_PFLASH_PROGRAM_CMD_ADDRESS_ALIGMENT (4) 222 223 /* GPIO module features */ 224 225 /* @brief Has GPIO attribute checker register (GACR). */ 226 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 227 228 /* I2C module features */ 229 230 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 231 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 232 /* @brief Maximum supported baud rate in kilobit per second. */ 233 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 234 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 235 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 236 /* @brief Has DMA support (register bit C1[DMAEN]). */ 237 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (0) 238 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 239 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 240 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 241 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 242 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 243 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 244 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 245 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 246 /* @brief Has control of the drive capability of the I2C pins. */ 247 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (0) 248 /* @brief Has double buffering support (register S2). */ 249 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) 250 /* @brief Has double buffer enable. */ 251 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 252 253 /* KBI module features */ 254 255 /* @brief KBI module has source pin. */ 256 #define FSL_FEATURE_KBI_HAS_SOURCE_PIN (0) 257 /* @brief KBI register width. */ 258 #define FSL_FEATURE_KBI_REG_WIDTH (8) 259 260 /* PIT module features */ 261 262 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 263 #define FSL_FEATURE_PIT_TIMER_COUNT (2) 264 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 265 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) 266 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 267 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 268 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 269 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) 270 /* @brief Has timer enable control. */ 271 #define FSL_FEATURE_PIT_HAS_MDIS (1) 272 273 /* SPI module features */ 274 275 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 276 #define FSL_FEATURE_SPI_HAS_FIFO (0) 277 /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */ 278 #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (0) 279 /* @brief Has separate DMA RX and TX requests. */ 280 #define FSL_FEATURE_SPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) 281 /* @brief Receive/transmit FIFO size in number of 16-bit communication items. */ 282 #define FSL_FEATURE_SPI_FIFO_SIZEn(x) (0) 283 /* @brief Maximum transfer data width in bits. */ 284 #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (8) 285 /* @brief The data register name has postfix (L as low and H as high). */ 286 #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0) 287 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 288 #define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 289 /* @brief Has 16-bit data transfer support. */ 290 #define FSL_FEATURE_SPI_16BIT_TRANSFERS (0) 291 292 /* UART module features */ 293 294 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 295 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 296 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 297 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 298 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 299 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0) 300 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 301 #define FSL_FEATURE_UART_HAS_FIFO (0) 302 /* @brief Hardware flow control (RTS, CTS) is supported. */ 303 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0) 304 /* @brief Infrared (modulation) is supported. */ 305 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) 306 /* @brief 2 bits long stop bit is available. */ 307 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 308 /* @brief If 10-bit mode is supported. */ 309 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0) 310 /* @brief Baud rate fine adjustment is available. */ 311 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 312 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 313 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 314 /* @brief Baud rate oversampling is available. */ 315 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (1) 316 /* @brief Baud rate oversampling is available. */ 317 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 318 /* @brief Peripheral type. */ 319 #define FSL_FEATURE_UART_IS_SCI (0) 320 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 321 #define FSL_FEATURE_UART_FIFO_SIZE (0) 322 /* @brief Supports two match addresses to filter incoming frames. */ 323 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (0) 324 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 325 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 326 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 327 #define FSL_FEATURE_UART_HAS_DMA_SELECT (0) 328 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 329 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (0) 330 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 331 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0) 332 /* @brief Has improved smart card (ISO7816 protocol) support. */ 333 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 334 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 335 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 336 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 337 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 338 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 339 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 340 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 341 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 342 /* @brief Has separate DMA RX and TX requests. */ 343 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) 344 345 #endif /* _MKE04Z4_FEATURES_H_ */ 346 347
