1 /*
2  * Copyright 2017 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 #ifndef _FSL_PORT_H_
8 #define _FSL_PORT_H_
9 
10 #include "fsl_common.h"
11 
12 /*!
13  * @addtogroup port
14  * @{
15  */
16 
17 /*******************************************************************************
18  * Definitions
19  ******************************************************************************/
20 
21 /*! @name Driver version */
22 /*@{*/
23 /*! Version 2.0.2. */
24 #define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
25 /*@}*/
26 
27 #define PORT_MODULEPS_BITWIDTH_OFFSET  (5U) /*　The bit width offset in the module enum type . */
28 #define PORT_MODULEPS_BITWIDTH_MASK    (0x7U) /* The bit width mask */
29 #define PORT_PINSEL_REG_OFFSET (0x20000U) /* The offset to identify the modules in different pin selection register. */
30 #define PORT_FILTER_REG_OFFSET (0x1000000U) /* The offset to identify the filter part in different filter register. */\
31 
32 /*! @brief Module or peripheral for port pin selection */
33 typedef enum _port_module_t {
34     kPORT_NMI = SIM_SOPT0_NMIE_SHIFT,  /*!< NMI port pin select. */
35     kPORT_RESET = SIM_SOPT0_RSTPE_SHIFT, /*!< RESET pin select. */
36     kPORT_SWDE = SIM_SOPT0_SWDE_SHIFT,    /*!< Single wire debug port pin. */
37     kPORT_IRQ = (SIM_PINSEL0_IRQPS_SHIFT | (3 << PORT_MODULEPS_BITWIDTH_OFFSET)), /*!< IRQ port pin select. */
38     kPORT_RTC = (SIM_PINSEL0_RTCPS_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET)), /*!< RTC port pin select. */
39     kPORT_I2C0 = (SIM_PINSEL0_I2C0PS_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET)),     /*!< I2C0 Port pin select. */
40     kPORT_SPI0 = (SIM_PINSEL0_SPI0PS_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET)),     /*!< SPI0 port pin select. */
41     kPORT_UART0 = (SIM_PINSEL0_UART0PS_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET)),   /*!< UART0 port pin select. */
42     kPORT_FTM0CH0 = (SIM_PINSEL0_FTM0PS0_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET)), /*!< FTM0_CH0 port pin select. */
43     kPORT_FTM0CH1 = (SIM_PINSEL0_FTM0PS1_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET)), /*!< FTM0_CH1 port pin select. */
44     kPORT_FTM1CH0 = (SIM_PINSEL0_FTM1PS0_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET)), /*!< FTM1_CH0 port pin select. */
45     kPORT_FTM1CH1 = (SIM_PINSEL0_FTM1PS1_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET)),  /*!< FTM1_CH1 port pin select. */
46     kPORT_FTM0CLK = (SIM_PINSEL0_FTM0CLKPS_SHIFT | (2 << PORT_MODULEPS_BITWIDTH_OFFSET)), /*!< FTM0 Clock pin select. */
47     kPORT_FTM1CLK = (SIM_PINSEL0_FTM1CLKPS_SHIFT | (2 << PORT_MODULEPS_BITWIDTH_OFFSET)), /*!< FTM1 Clock pin select. */
48     kPORT_FTM2CLK = (SIM_PINSEL0_FTM2CLKPS_SHIFT | (2 << PORT_MODULEPS_BITWIDTH_OFFSET)), /*!< FTM2 Clock pin select. */
49     kPORT_PWTCLK = (SIM_PINSEL0_PWTCLKPS_SHIFT | (2 << PORT_MODULEPS_BITWIDTH_OFFSET)), /*!< PWT Clock pin select. */
50     kPORT_FTM2CH0 = (SIM_PINSEL1_FTM2PS0_SHIFT | (2 << PORT_MODULEPS_BITWIDTH_OFFSET) | PORT_PINSEL_REG_OFFSET), /*!< FTM2_CH0 port pin select. */
51     kPORT_FTM2CH1 = (SIM_PINSEL1_FTM2PS1_SHIFT | (2 << PORT_MODULEPS_BITWIDTH_OFFSET) | PORT_PINSEL_REG_OFFSET), /*!< FTM2_CH1 port pin select. */
52     kPORT_FTM2CH2 = (SIM_PINSEL1_FTM2PS2_SHIFT | (2 << PORT_MODULEPS_BITWIDTH_OFFSET) | PORT_PINSEL_REG_OFFSET), /*!< FTM2_CH2 port pin select. */
53     kPORT_FTM2CH3 = (SIM_PINSEL1_FTM2PS3_SHIFT | (2 << PORT_MODULEPS_BITWIDTH_OFFSET) | PORT_PINSEL_REG_OFFSET), /*!< FTM2_CH3 port pin select. */
54     kPORT_FTM2CH4 = (SIM_PINSEL1_FTM2PS4_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET) | PORT_PINSEL_REG_OFFSET), /*!< FTM2_CH4 port pin select. */
55     kPORT_FTM2CH5 = (SIM_PINSEL1_FTM2PS5_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET) | PORT_PINSEL_REG_OFFSET), /*!< FTM2_CH5 port pin select. */
56     kPORT_I2C1 = (SIM_PINSEL1_I2C1PS_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET) | PORT_PINSEL_REG_OFFSET), /*!< I2C1 port pin select. */
57     kPORT_SPI1 = (SIM_PINSEL1_SPI1PS_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET) | PORT_PINSEL_REG_OFFSET), /*!< SPI1 port pin select. */
58     kPORT_UART1 = (SIM_PINSEL1_UART1PS_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET) | PORT_PINSEL_REG_OFFSET), /*!< UART1 port pin select. */
59     kPORT_UART2 = (SIM_PINSEL1_UART2PS_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET) | PORT_PINSEL_REG_OFFSET), /*!< UART2 port pin select. */
60     kPORT_PWTIN0 = (SIM_PINSEL1_PWTIN0PS_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET) | PORT_PINSEL_REG_OFFSET), /*!< PWT_IN0 port pin select. */
61     kPORT_PWTIN1 = (SIM_PINSEL1_PWTIN1PS_SHIFT | (1 << PORT_MODULEPS_BITWIDTH_OFFSET) | PORT_PINSEL_REG_OFFSET), /*!< PWT_IN1 port pin select. */
62 } port_module_t;
63 
64 /*! @brief Port type */
65 typedef enum _port_type_t {
66     kPORT_PTA = 0U, /*!< PORT PTA. */
67     kPORT_PTB = 1U, /*!< PORT PTB. */
68     kPORT_PTC = 2U, /*!< PORT PTC. */
69     kPORT_PTD = 3U, /*!< PORT PTD. */
70     kPORT_PTE = 4U, /*!< PORT PTE. */
71     kPORT_PTF = 5U, /*!< PORT PTF. */
72     kPORT_PTG = 6U, /*!< PORT PTG. */
73     kPORT_PTH = 7U, /*!< PORT PTH. */
74     kPORT_PTI = 8U  /*!< PORT PTI. */
75 } port_type_t;
76 
77 /*! @brief Pin number, Notice this index enum has been deprecated and it will be removed in the next release. */
78 typedef enum _port_pin_index_t {
79     kPORT_PinIdx0 = 0U, /*!< PORT PIN index 0. */
80     kPORT_PinIdx1 = 1U, /*!< PORT PIN index 1. */
81     kPORT_PinIdx2 = 2U, /*!< PORT PIN index 2. */
82     kPORT_PinIdx3 = 3U, /*!< PORT PIN index 3. */
83     kPORT_PinIdx4 = 4U, /*!< PORT PIN index 4. */
84     kPORT_PinIdx5 = 5U, /*!< PORT PIN index 5. */
85     kPORT_PinIdx6 = 6U, /*!< PORT PIN index 6. */
86     kPORT_PinIdx7 = 7U  /*!< PORT PIN index 7. */
87 } port_pin_index_t;
88 
89 /*! @brief Pin selection */
90 typedef enum _port_pin_select_t {
91     kPORT_NMI_OTHERS = 0U,           /*!< PTB4/FTM2_CH4 etc function as PTB4/FTM2_CH4 etc */
92     kPORT_NMI_NMIE = 1U,             /*!< PTB4/FTM2_CH4 etc function as NMI. */
93     kPORT_RST_OTHERS = 0U,           /*!< PTA5/IRQ etc function as PTA5/IRQ etc. */
94     kPORT_RST_RSTPE = 1U,            /*!< PTA5/IRQ etc function as REST. */
95     kPORT_SWDE_OTHERS = 0U,          /*!< PTA4/ACMP0 etc function as PTA4/ACMP0 etc. */
96     kPORT_SWDE_SWDE = 1U,            /*!< PTA4/ACMP0 etc function as SWD. */
97     kPORT_IRQ_PTA5 = 0U,             /*!< IRQ is mapped to PTA5. */
98     kPORT_IRQ_PTI0 = 1U,             /*!< IRQ is mapped to PTI0. */
99     kPORT_IRQ_PTI1 = 2U,             /*!< IRQ is mapped to PTI1. */
100     kPORT_IRQ_PTI2 = 3U,             /*!< IRQ is mapped to PTI2. */
101     kPORT_IRQ_PTI3 = 4U,             /*!< IRQ is mapped to PTI3. */
102     kPORT_IRQ_PTI4 = 5U,             /*!< IRQ is mapped to PTI4. */
103     kPORT_IRQ_PTI5 = 6U,             /*!< IRQ is mapped to PTI5. */
104     kPORT_IRQ_PTI6 = 7U,             /*!< IRQ is mapped to PTI6. */
105     kPORT_RTCO_PTC4 = 0U,            /*!< RTCO is mapped to PTC4. */
106     kPORT_RTCO_PTC5 = 1U,            /*!< RTCO is mapped to RTC5. */
107     kPORT_I2C0_SCLPTA3_SDAPTA2 = 0U, /*!< I2C0_SCL and I2C0_SDA are mapped on PTA3 and PTA2, respectively. */
108     kPORT_I2C0_SCLPTB7_SDAPTB6 = 1U, /*!< I2C0_SCL and I2C0_SDA are mapped on PTB7 and PTB6, respectively. */
109     kPORT_SPI0_SCKPTB2_MOSIPTB3_MISOPTB4_PCSPTB5 = 0U, /*!< SPI0_SCK/MOSI/MISO/PCS0 are mapped on PTB2/PTB3/PTB4/PTB5.*/
110     kPORT_SPI0_SCKPTE0_MOSIPTE1_MISOPTE2_PCSPTE3 =
111         1U,                         /*!< SPI0_SCK/MOSI/MISO/PCS0 are mapped on PTE0/PTE1/PTE2/PTE3. */
112     kPORT_UART0_RXPTB0_TXPTB1 = 0U, /*!< UART0_RX and UART0_TX are mapped on PTB0 and PTB1. */
113     kPORT_UART0_RXPTA2_TXPTA3 = 1U, /*!< UART0_RX and UART0_TX are mapped on PTA2 and PTA3. */
114     kPORT_FTM0_CH0_PTA0 = 0U,       /*!< FTM0_CH0 channels are mapped on PTA0. */
115     kPORT_FTM0_CH0_PTB2 = 1U,       /*!< FTM0_CH0 channels are mapped on PTB2. */
116     kPORT_FTM0_CH1_PTA1 = 0U,       /*!< FTM0_CH1 channels are mapped on PTA1. */
117     kPORT_FTM0_CH1_PTB3 = 1U,       /*!< FTM0_CH1 channels are mapped on PTB3. */
118     kPORT_FTM0CLK_TCLK0 = 0U,       /*!< FTM0 CLK using the TCLK0 pin. */
119     kPORT_FTM0CLK_TCLK1 = 1U,       /*!< FTM0 CLK using the TCLK1 pin. */
120     kPORT_FTM0CLK_TCLK2 = 2U,       /*!< FTM0 CLK using the TCLK2 pin. */
121     kPORT_FTM1CLK_TCLK0 = 0U,       /*!< FTM1 CLK using the TCLK0 pin. */
122     kPORT_FTM1CLK_TCLK1 = 1U,       /*!< FTM1 CLK using the TCLK1 pin. */
123     kPORT_FTM1CLK_TCLK2 = 2U,       /*!< FTM1 CLK using the TCLK2 pin. */
124     kPORT_FTM2CLK_TCLK0 = 0U,       /*!< FTM2 CLK using the TCLK0 pin. */
125     kPORT_FTM2CLK_TCLK1 = 1U,       /*!< FTM2 CLK using the TCLK1 pin. */
126     kPORT_FTM2CLK_TCLK2 = 2U,       /*!< FTM2 CLK using the TCLK2 pin. */
127     kPORT_PWTCLK_TCLK0 = 0U,        /*!< PWT CLK using the TCLK0 pin. */
128     kPORT_PWTCLK_TCLK1 = 1U,        /*!< PWT CLK using the TCLK1 pin. */
129     kPORT_PWTCLK_TCLK2 = 2U,        /*!< PWT CLK using the TCLK2 pin. */
130     kPORT_FTM1_CH0_PTC4 = 0U,       /*!< FTM1_CH0 channels are mapped on PTC4. */
131     kPORT_FTM1_CH0_PTH2 = 1U,       /*!< FTM1_CH0 channels are mapped on PTH2. */
132     kPORT_FTM1_CH1_PTC5 = 0U,       /*!< FTM1_CH1 channels are mapped on PTC5. */
133     kPORT_FTM1_CH1_PTE7 = 1U,       /*!< FTM1_CH1 channels are mapped on PTE7. */
134     kPORT_FTM2_CH0_PTC0 = 0U,       /*!< FTM2_CH0 channels are mapped on PTC0. */
135     kPORT_FTM2_CH0_PTH0 = 1U,       /*!< FTM2_CH0 channels are mapped on PTH0. */
136     kPORT_FTM2_CH0_PTF0 = 2U,       /*!< FTM2_CH0 channels are mapped on PTF0. */
137     kPORT_FTM2_CH1_PTC1 = 0U,       /*!< FTM2_CH1 channels are mapped on PTC1. */
138     kPORT_FTM2_CH1_PTH1 = 1U,       /*!< FTM2_CH1 channels are mapped on PTH1. */
139     kPORT_FTM2_CH1_PTF1 = 2U,       /*!< FTM2_CH1 channels are mapped on PTF1. */
140     kPORT_FTM2_CH2_PTC2 = 0U,       /*!< FTM2_CH2 channels are mapped on PTC2. */
141     kPORT_FTM2_CH2_PTD0 = 1U,       /*!< FTM2_CH2 channels are mapped on PTD0. */
142     kPORT_FTM2_CH2_PTG4 = 2U,       /*!< FTM2_CH2 channels are mapped on PTG4. */
143     kPORT_FTM2_CH3_PTC3 = 0U,       /*!< FTM2_CH3 channels are mapped on PTC3. */
144     kPORT_FTM2_CH3_PTD1 = 1U,       /*!< FTM2_CH3 channels are mapped on PTD1. */
145     kPORT_FTM2_CH3_PTG5 = 2U,       /*!< FTM2_CH3 channels are mapped on PTG5. */
146     kPORT_FTM2_CH4_PTB4 = 0U,       /*!< FTM2_CH4 channels are mapped on PTB4. */
147     kPORT_FTM2_CH4_PTG6 = 1U,       /*!< FTM2_CH4 channels are mapped on PTG6. */
148     kPORT_FTM2_CH5_PTB5 = 0U,       /*!< FTM2_CH5 channels are mapped on PTB5. */
149     kPORT_FTM2_CH5_PTG7 = 1U,       /*!< FTM2_CH5 channels are mapped on PTG7. */
150     kPORT_I2C1_SCLPTE1_SDAPTE0 = 0U, /*!< I2C1_SCL and I2C1_SDA are mapped on PTE1 and PTE0, respectively. */
151     kPORT_I2C1_SCLPTH4_SDAPTH3 = 1U, /*!< I2C1_SCL and I2C1_SDA are mapped on PTH4 and PTH3, respectively. */
152     kPORT_SPI1_SCKPTD0_MOSIPTD1_MISOPTD2_PCSPTD3 = 0U, /*!< SPI1_SCK/MOSI/MISO/PCS0 are mapped on PTD0/PTD1/PTD2/PTD3.*/
153     kPORT_SPI1_SCKPTG4_MOSIPTG5_MISOPTG6_PCSPTG7 =
154         1U,                         /*!< SPI1_SCK/MOSI/MISO/PCS0 are mapped on PTG4/PTG5/PTG6/PTG7. */
155     kPORT_UART1_RXPTC7_TXPTC6 = 0U, /*!< UART1_RX and UART1_TX are mapped on PTC7 and PTC6. */
156     kPORT_UART1_RXPTF3_TXPTF2 = 1U,  /*!< UART1_RX and UART1_TX are mapped on PTF3 and PTF2. */
157     kPORT_UART2_RXPTD7_TXPTD6 = 0U, /*!< UART2_RX and UART2_TX are mapped on PTD7 and PTD6. */
158     kPORT_UART2_RXPTI1_TXPTI0 = 1U,  /*!< UART2_RX and UART2_TX are mapped on PTI1 and PTI0. */
159     kPORT_PWTIN0_PTD5 = 0U,         /*!< PWTIN0 is mapped to PTD5. */
160     kPORT_PWTIN0_PTE2 = 1U,         /*!< PWTIN0 is mapped to PTE2. */
161     kPORT_PWTIN1_PTB0 = 0U,         /*!< PWTIN0 is mapped to PTB0. */
162     kPORT_PWTIN1_PTH7 = 1U,         /*!< PWTIN0 is mapped to PTH7. */
163     kPORT_MSCAN_TXPTC7_RXPTC6 = 0U, /*!< CAN_TX, RXis mapped to PTC7, PTC6. */
164     kPORT_MSCAN_TXPTE7_RXPTH2 = 1U  /*!< CAN_TX, RXis mapped to PTE7, PTH2. */
165 } port_pin_select_t;
166 
167 /*! @brief The PORT pins for input glitch filter configure */
168 typedef enum _port_filter_pin_t {
169     kPORT_FilterPTA = PORT_IOFLT0_FLTA_SHIFT,     /*!< Filter for input from PTA. */
170     kPORT_FilterPTB = PORT_IOFLT0_FLTB_SHIFT,     /*!< Filter for input from PTB. */
171     kPORT_FilterPTC = PORT_IOFLT0_FLTC_SHIFT,     /*!< Filter for input from PTC. */
172     kPORT_FilterPTD = PORT_IOFLT0_FLTD_SHIFT,     /*!< Filter for input from PTD. */
173     kPORT_FilterPTE = PORT_IOFLT0_FLTE_SHIFT,     /*!< Filter for input from PTE. */
174     kPORT_FilterPTF = PORT_IOFLT0_FLTF_SHIFT,     /*!< Filter for input from PTF. */
175     kPORT_FilterPTG = PORT_IOFLT0_FLTG_SHIFT,     /*!< Filter for input from PTG. */
176     kPORT_FilterPTH = PORT_IOFLT0_FLTH_SHIFT,     /*!< Filter for input from PTH. */
177     kPORT_FilterRST = PORT_IOFLT0_FLTRST_SHIFT,   /*!< Filter for input from RESET/IRQ. */
178     kPORT_FilterKBI0 = PORT_IOFLT0_FLTKBI0_SHIFT, /*!< Filter for input from KBI0. */
179     kPORT_FilterKBI1 = PORT_IOFLT0_FLTKBI1_SHIFT, /*!< Filter for input from KBI1. */
180     kPORT_FilterNMI = PORT_IOFLT0_FLTNMI_SHIFT,   /*!< Filter for input from NMI. */
181     KPORT_Filter0MAX = PORT_IOFLT0_FLTNMI_SHIFT + 1U,                      /*!< The max shift for Filter0 */
182     kPORT_FilterPTI = PORT_IOFLT1_FLTI_SHIFT + PORT_FILTER_REG_OFFSET,     /*!< Filter for input from PTI. */
183     kPORT_FilterIRQ = PORT_IOFLT1_FLTIRQ_SHIFT + PORT_FILTER_REG_OFFSET,   /*!< Filter for input from IRQ. */
184     kPORT_FilterFTM0 = PORT_IOFLT1_FLTFTM0_SHIFT + PORT_FILTER_REG_OFFSET, /*!< Filter for input from FTM0. */
185     kPORT_FilterFTM1 = PORT_IOFLT1_FLTFTM1_SHIFT + PORT_FILTER_REG_OFFSET, /*!< Filter for input form FTM1. */
186     kPORT_FilterPWT = PORT_IOFLT1_FLTPWT_SHIFT + PORT_FILTER_REG_OFFSET,   /*!< Filter for input from PWT. */
187     kPORT_FilterI2C0 = PORT_IOFLT1_FLTI2C0_SHIFT + PORT_FILTER_REG_OFFSET, /*!< Filter for input form I2C0. */
188     kPORT_FilterI2C1 = PORT_IOFLT1_FLTI2C1_SHIFT + PORT_FILTER_REG_OFFSET  /*!< Filter for input from I2C1. */
189 } port_filter_pin_t;
190 
191 /*! @brief The Filter selection for input pins */
192 typedef enum _port_filter_select_t {
193     kPORT_BUSCLK_OR_NOFILTER = 0U, /*!< Filter section BUSCLK for PTA~PTH,= or no filter for REST/KBI0/KBI1/NMI/IRQ/FTM0/FTM1/PWT/I2C0/I2C1. */
194     kPORT_FILTERDIV1 = 1U,      /*!< Filter Division Set 1. */
195     kPORT_FILTERDIV2 = 2U,      /*!< Filter Division Set 2. */
196     kPORT_FILTERDIV3_OR_BUSCLK = 3U /*!< Filter Division Set 3 for NMI/KBI1/KNI0/IRQ/PTA~PTH/PWT/FTM0/FTM1/IRQ/PTI or BUSCLK for I2C0/I2C1/ */
197 } port_filter_select_t;
198 
199 /*! @brief Port pin for high driver enable/disable control. */
200 typedef enum _port_highdrive_pin_t {
201     kPORT_HighDrive_PTB4 = PORT_HDRVE_PTB4_MASK, /*!< PTB4. */
202     kPORT_HighDrive_PTB5 = PORT_HDRVE_PTB5_MASK, /*!< PTB5. */
203     kPORT_HighDrive_PTD0 = PORT_HDRVE_PTD0_MASK, /*!< PTD0. */
204     kPORT_HighDrive_PTD1 = PORT_HDRVE_PTD1_MASK, /*!< PTD1. */
205     kPORT_HighDrive_PTE0 = PORT_HDRVE_PTE0_MASK, /*!< PTE0. */
206     kPORT_HighDrive_PTE1 = PORT_HDRVE_PTE1_MASK, /*!< PTE1. */
207     kPORT_HighDrive_PTH0 = PORT_HDRVE_PTH0_MASK, /*!< PTH0. */
208     kPORT_HighDrive_PTH1 = PORT_HDRVE_PTH1_MASK  /*!< PTH1. */
209 } port_highdrive_pin_t;
210 
211 /*******************************************************************************
212 * API
213 ******************************************************************************/
214 
215 #if defined(__cplusplus)
216 extern "C" {
217 #endif
218 
219 /*! @name Configuration */
220 /*@{*/
221 
222 /*!
223  * @brief Selects pin for modules.
224  *
225  * This API is used to select the port pin for the module with multiple port pin
226  * selection. For example the FTM Channel 0 can be mapped to ether PTA0 or PTB2.
227  * Select FTM channel 0 map to PTA0 port pin as:
228  * @code
229  * PORT_SetPinSelect(kPORT_FTM0CH0, kPORT_FTM0_CH0_PTA0);
230  * @endcode
231  *
232  * @Note： This API doesn't support to select specified ALT for a given port pin.
233  * The ALT feature is automatically selected by hardware according to the
234  * ALT priority:
235  *     Low -----> high:
236  *     Alt1, Alt2, …
237  * when peripheral modules has been enabled.
238  *
239  * If you want to select a specified ALT for a given port pin, please add two more
240  * steps after calling PORT_SetPinSelect:
241  * 1. Enable module or the port control in the module for the ALT you want to select.
242  *   For I2C ALT feature:all port enable is controlled by the module enable, so
243  *   set IICEN in I2CX_C1 to enable the port pins for I2C feature.
244  *   For KBI ALT feature:each port pin is controlled independently by each bit in KBIx_PE.
245  *   set related bit in this register to enable the KBI feature in the port pin.
246  * 2. Make sure there is no module enabled with higher priority than the ALT module feature
247  *  you want to select.
248  *
249  * @param module   Modules for pin selection.
250  *        For NMI/RST module are write-once attribute after reset.
251  * @param pin   Port pin selection for modules.
252  *
253  */
254 void PORT_SetPinSelect(port_module_t module, port_pin_select_t pin);
255 
256 /*!
257  * @brief Selects the glitch filter for input pins.
258  *
259  * @param base   PORT peripheral base pointer.
260  * @param port   PORT pin, see "port_filter_pin_t".
261  * @param filter  Filter select, see "port_filter_select_t".
262  */
263 void PORT_SetFilterSelect(PORT_Type *base, port_filter_pin_t port, port_filter_select_t filter);
264 
265 /*!
266  * @brief Sets the width threshold for glitch filter division set 1.
267  *`
268  * @param base   PORT peripheral base pointer.
269  * @param threshold PORT glitch filter width threshold, take refer to reference manual for detail information.
270  *        0  -   LPOCLK
271  *        1  -   LPOCLK/2
272  *        2  -   LPOCLK/4
273  *        3  -   LPOCLK/8
274  *        4  -   LPOCLK/16
275  *        5  -   LPOCLK/32
276  *        6  -   LPOCLK/64
277  *        7  -   LPOCLK/128
278  */
PORT_SetFilterDIV1WidthThreshold(PORT_Type * base,uint8_t threshold)279 static inline void PORT_SetFilterDIV1WidthThreshold(PORT_Type *base, uint8_t threshold)
280 {
281     uint32_t fltReg;
282 
283     fltReg = base->IOFLT0 & ~PORT_IOFLT0_FLTDIV1_MASK;
284     base->IOFLT0 = fltReg | PORT_IOFLT0_FLTDIV1(threshold);
285 }
286 
287 /*!
288  * @brief Sets the width threshold for glitch filter division set 2.
289  *`
290  * @param base   PORT peripheral base pointer.
291  * @param threshold PORT glitch filter width threshold, take refer to reference manual for detail information.
292  *        0  -   BUSCLK/32
293  *        1  -   BUSCLK/64
294  *        2  -   BUSCLK/128
295  *        3  -   BUSCLK/256
296  *        4  -   BUSCLK/512
297  *        5  -   BUSCLK/1024
298  *        6  -   BUSCLK/2048
299  *        7  -   BUSCLK/4096
300  */
PORT_SetFilterDIV2WidthThreshold(PORT_Type * base,uint8_t threshold)301 static inline void PORT_SetFilterDIV2WidthThreshold(PORT_Type *base, uint8_t threshold)
302 {
303     uint32_t fltReg;
304 
305     fltReg = base->IOFLT0 & ~PORT_IOFLT0_FLTDIV2_MASK;
306     base->IOFLT0 = fltReg | PORT_IOFLT0_FLTDIV2(threshold);
307 }
308 
309 /*!
310  * @brief Sets the width threshold for glitch filter division set 3.
311  *`
312  * @param base   PORT peripheral base pointer.
313  * @param threshold PORT glitch filter width threshold, take refer to reference manual for detail information.
314  *        0  -   BUSCLK/2
315  *        1  -   BUSCLK/4
316  *        2  -   BUSCLK/8
317  *        3  -   BUSCLK/16
318  */
PORT_SetFilterDIV3WidthThreshold(PORT_Type * base,uint8_t threshold)319 static inline void PORT_SetFilterDIV3WidthThreshold(PORT_Type *base, uint8_t threshold)
320 {
321     uint32_t fltReg;
322 
323     fltReg = base->IOFLT0 & ~PORT_IOFLT0_FLTDIV3_MASK;
324     base->IOFLT0 = fltReg | PORT_IOFLT0_FLTDIV3(threshold);
325 }
326 
327 /*!
328  * @brief Enables or disables the port pull up.
329  *
330  * @param base   PORT peripheral base pointer.
331  * @param port   PORT type, such as PTA/PTB/PTC etc, see "port_type_t".
332  * @param num    PORT pin number, such as 0, 1, 2...
333  *               For PTI, only PTI0 ~ PTI6 pins are supported. so when set pull
334  *               up feature for PTI, please don't set number 7. see reference manual for more details.
335  * @param enable  Enable or disable the pull up feature switch.
336  */
337 void PORT_SetPinPullUpEnable(PORT_Type *base, port_type_t port, uint8_t num, bool enable);
338 
339 /*!
340  * @brief Set High drive for port pins.
341  *
342  * @param base PORT peripheral base pointer.
343  * @param pin PORT pin support high drive.
344  * @param enable Enable or disable the high driver feature switch.
345  */
PORT_SetHighDriveEnable(PORT_Type * base,port_highdrive_pin_t pin,bool enable)346 static inline void PORT_SetHighDriveEnable(PORT_Type *base, port_highdrive_pin_t pin, bool enable)
347 {
348     if (enable)
349     {
350         base->HDRVE |= (uint32_t)pin;
351     }
352     else
353     {
354         base->HDRVE &= ~(uint32_t)pin;
355     }
356 }
357 
358 /*@}*/
359 
360 #if defined(__cplusplus)
361 }
362 #endif
363 
364 /*! @}*/
365 
366 #endif /* _FSL_PORT_H_ */
367