1 /*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #ifndef _FSL_PORT_H_
8 #define _FSL_PORT_H_
9
10 #include "fsl_common.h"
11
12 /*!
13 * @addtogroup port
14 * @{
15 */
16
17 /*******************************************************************************
18 * Definitions
19 ******************************************************************************/
20
21 /*! @name Driver version */
22 /*@{*/
23 /*! Version 2.0.2. */
24 #define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
25 /*@}*/
26
27 #define FSL_PORT_FILTER_SELECT_BITMASK (0x3U) /*!< The IOFLT Filter selection bit mask . */
28
29 /*! @brief Module or peripheral for port pin selection */
30 typedef enum _port_module_t {
31 kPORT_NMI = SIM_SOPT_NMIE_MASK, /*!< NMI port pin select. */
32 kPORT_RESET = SIM_SOPT_RSTPE_MASK, /*!< RESET pin select. */
33 kPORT_SWDE = SIM_SOPT_SWDE_MASK, /*!< Single wire debug port pin. */
34 kPORT_RTC = SIM_PINSEL_RTCPS_MASK, /*!< RTCO port pin select. */
35 kPORT_I2C0 = SIM_PINSEL_I2C0PS_MASK, /*!< I2C0 Port pin select. */
36 kPORT_SPI0 = SIM_PINSEL_SPI0PS_MASK, /*!< SPI0 port pin select. */
37 kPORT_UART0 = SIM_PINSEL_UART0PS_MASK, /*!< UART0 port pin select. */
38 kPORT_FTM0CH0 = SIM_PINSEL_FTM0PS0_MASK, /*!< FTM0_CH0 port pin select. */
39 kPORT_FTM0CH1 = SIM_PINSEL_FTM0PS1_MASK, /*!< FTM0_CH1 port pin select. */
40 kPORT_FTM1CH0 = SIM_PINSEL_FTM1PS0_MASK, /*!< FTM1_CH0 port pin select. */
41 kPORT_FTM1CH1 = SIM_PINSEL_FTM1PS1_MASK, /*!< FTM1_CH1 port pin select. */
42 kPORT_FTM2CH0 = SIM_PINSEL_FTM2PS0_MASK, /*!< FTM2_CH0 port pin select. */
43 kPORT_FTM2CH1 = SIM_PINSEL_FTM2PS1_MASK, /*!< FTM2_CH1 port pin select. */
44 kPORT_FTM2CH2 = SIM_PINSEL_FTM2PS2_MASK, /*!< FTM2_CH2 port pin select. */
45 kPORT_FTM2CH3 = SIM_PINSEL_FTM2PS3_MASK /*!< FTM2_CH3 port pin select. */
46 } port_module_t;
47
48 /*! @brief Port type */
49 typedef enum _port_type_t {
50 kPORT_PTA = 0U, /*!< PORT PTA. */
51 kPORT_PTB = 1U, /*!< PORT PTB. */
52 kPORT_PTC = 2U, /*!< PORT PTC. */
53 kPORT_PTD = 3U, /*!< PORT PTD. */
54 kPORT_PTE = 4U, /*!< PORT PTE. */
55 kPORT_PTF = 5U, /*!< PORT PTF. */
56 kPORT_PTG = 6U, /*!< PORT PTG. */
57 kPORT_PTH = 7U /*!< PORT PTH. */
58 } port_type_t;
59
60 /*! @brief Pin number, Notice this index enum has been deprecated and it will be removed in the next release. */
61 typedef enum _port_pin_index_t {
62 kPORT_PinIdx0 = 0U, /*!< PORT PIN index 0. */
63 kPORT_PinIdx1 = 1U, /*!< PORT PIN index 1. */
64 kPORT_PinIdx2 = 2U, /*!< PORT PIN index 2. */
65 kPORT_PinIdx3 = 3U, /*!< PORT PIN index 3. */
66 kPORT_PinIdx4 = 4U, /*!< PORT PIN index 4. */
67 kPORT_PinIdx5 = 5U, /*!< PORT PIN index 5. */
68 kPORT_PinIdx6 = 6U, /*!< PORT PIN index 6. */
69 kPORT_PinIdx7 = 7U /*!< PORT PIN index 7. */
70 } port_pin_index_t;
71
72 /*! @brief Pin selection */
73 typedef enum _port_pin_select_t {
74 kPORT_NMI_OTHERS = 0U, /*!< PTB4/FTM2_CH4 etc function as PTB4/FTM2_CH4 etc */
75 kPORT_NMI_NMIE = 1U, /*!< PTB4/FTM2_CH4 etc function as NMI. */
76 kPORT_RST_OTHERS = 0U, /*!< PTA5/IRQ etc function as PTA5/IRQ etc. */
77 kPORT_RST_RSTPE = 1U, /*!< PTA5/IRQ etc function as REST. */
78 kPORT_SWDE_OTHERS = 0U, /*!< PTA4/ACMP0 etc function as PTA4/ACMP0 etc. */
79 kPORT_SWDE_SWDE = 1U, /*!< PTA4/ACMP0 etc function as SWD. */
80 kPORT_RTCO_PTC4 = 0U, /*!< RTCO is mapped to PTC4. */
81 kPORT_RTCO_PTC5 = 1U, /*!< RTCO is mapped to PTC5. */
82 kPORT_I2C0_SCLPTA3_SDAPTA2 = 0U, /*!< I2C0_SCL and I2C0_SDA are mapped on PTA3 and PTA2, respectively. */
83 kPORT_I2C0_SCLPTB7_SDAPTB6 = 1U, /*!< I2C0_SCL and I2C0_SDA are mapped on PTB7 and PTB6, respectively. */
84 kPORT_SPI0_SCKPTB2_MOSIPTB3_MISOPTB4_PCSPTB5 = 0U, /*!< SPI0_SCK/MOSI/MISO/PCS0 are mapped on PTB2/PTB3/PTB4/PTB5.*/
85 kPORT_SPI0_SCKPTE0_MOSIPTE1_MISOPTE2_PCSPTE3 =
86 1U, /*!< SPI0_SCK/MOSI/MISO/PCS0 are mapped on PTE0/PTE1/PTE2/PTE3. */
87 kPORT_UART0_RXPTB0_TXPTB1 = 0U, /*!< UART0_RX and UART0_TX are mapped on PTB0 and PTB1. */
88 kPORT_UART0_RXPTA2_TXPTA3 = 1U, /*!< UART0_RX and UART0_TX are mapped on PTA2 and PTA3. */
89 kPORT_FTM0_CH0_PTA0 = 0U, /*!< FTM0_CH0 channels are mapped on PTA0. */
90 kPORT_FTM0_CH0_PTB2 = 1U, /*!< FTM0_CH0 channels are mapped on PTB2. */
91 kPORT_FTM0_CH1_PTA1 = 0U, /*!< FTM0_CH1 channels are mapped on PTA1. */
92 kPORT_FTM0_CH1_PTB3 = 1U, /*!< FTM0_CH1 channels are mapped on PTB3. */
93 kPORT_FTM1_CH0_PTC4 = 0U, /*!< FTM1_CH0 channels are mapped on PTC4. */
94 kPORT_FTM1_CH0_PTH2 = 1U, /*!< FTM1_CH0 channels are mapped on PTH2. */
95 kPORT_FTM1_CH1_PTC5 = 0U, /*!< FTM1_CH1 channels are mapped on PTC5. */
96 kPORT_FTM1_CH1_PTE7 = 1U, /*!< FTM1_CH1 channels are mapped on PTE7. */
97 kPORT_FTM2_CH0_PTC0 = 0U, /*!< FTM2_CH0 channels are mapped on PTC0. */
98 kPORT_FTM2_CH0_PTH0 = 1U, /*!< FTM2_CH0 channels are mapped on PTH0. */
99 kPORT_FTM2_CH1_PTC1 = 0U, /*!< FTM2_CH1 channels are mapped on PTC1. */
100 kPORT_FTM2_CH1_PTH1 = 1U, /*!< FTM2_CH1 channels are mapped on PTH1. */
101 kPORT_FTM2_CH2_PTC2 = 0U, /*!< FTM2_CH2 channels are mapped on PTC2. */
102 kPORT_FTM2_CH2_PTD0 = 1U, /*!< FTM2_CH2 channels are mapped on PTD0. */
103 kPORT_FTM2_CH3_PTC3 = 0U, /*!< FTM2_CH3 channels are mapped on PTC3. */
104 kPORT_FTM2_CH3_PTD1 = 1U, /*!< FTM2_CH3 channels are mapped on PTD1. */
105 } port_pin_select_t;
106
107 /*! @brief The PORT pins for input glitch filter configure */
108 typedef enum _port_filter_pin_t {
109 kPORT_FilterPTA = PORT_IOFLT_FLTA_SHIFT, /*!< Filter for input from PTA. */
110 kPORT_FilterPTB = PORT_IOFLT_FLTB_SHIFT, /*!< Filter for input from PTB. */
111 kPORT_FilterPTC = PORT_IOFLT_FLTC_SHIFT, /*!< Filter for input from PTC. */
112 kPORT_FilterPTD = PORT_IOFLT_FLTD_SHIFT, /*!< Filter for input from PTD. */
113 kPORT_FilterPTE = PORT_IOFLT_FLTE_SHIFT, /*!< Filter for input from PTE. */
114 kPORT_FilterPTF = PORT_IOFLT_FLTF_SHIFT, /*!< Filter for input from PTF. */
115 kPORT_FilterPTG = PORT_IOFLT_FLTG_SHIFT, /*!< Filter for input from PTG. */
116 kPORT_FilterPTH = PORT_IOFLT_FLTH_SHIFT, /*!< Filter for input from PTH. */
117 kPORT_FilterRST = PORT_IOFLT_FLTRST_SHIFT, /*!< Filter for input from RESET/IRQ. */
118 kPORT_FilterKBI0 = PORT_IOFLT_FLTKBI0_SHIFT, /*!< Filter for input from KBI0. */
119 kPORT_FilterKBI1 = PORT_IOFLT_FLTKBI1_SHIFT, /*!< Filter for input from KBI1. */
120 kPORT_FilterNMI = PORT_IOFLT_FLTNMI_SHIFT, /*!< Filter for input from NMI. */
121 } port_filter_pin_t;
122
123 /*! @brief The Filter selection for input pins */
124 typedef enum _port_filter_select_t {
125 kPORT_BUSCLK_OR_NOFILTER = 0U, /*!< Filter section BUSCLK for PTA~PTH, No filter for REST/KBI0/KBI1/NMI. */
126 kPORT_FILTERDIV1 = 1U, /*!< Filter Division Set 1. */
127 kPORT_FILTERDIV2 = 2U, /*!< Filter Division Set 2. */
128 kPORT_FILTERDIV3 = 3U /*!< Filter Division Set 3. */
129 } port_filter_select_t;
130
131 /*! @brief Port pin for high driver enable/disable control. */
132 typedef enum _port_highdrive_pin_t {
133 kPORT_HighDrive_PTB4 = PORT_HDRVE_PTB4_MASK, /*!< PTB4. */
134 kPORT_HighDrive_PTB5 = PORT_HDRVE_PTB5_MASK, /*!< PTB5. */
135 kPORT_HighDrive_PTD0 = PORT_HDRVE_PTD0_MASK, /*!< PTD0. */
136 kPORT_HighDrive_PTD1 = PORT_HDRVE_PTD1_MASK, /*!< PTD1. */
137 kPORT_HighDrive_PTE0 = PORT_HDRVE_PTE0_MASK, /*!< PTE0. */
138 kPORT_HighDrive_PTE1 = PORT_HDRVE_PTE1_MASK, /*!< PTE1. */
139 kPORT_HighDrive_PTH0 = PORT_HDRVE_PTH0_MASK, /*!< PTH0. */
140 kPORT_HighDrive_PTH1 = PORT_HDRVE_PTH1_MASK /*!< PTH1. */
141 } port_highdrive_pin_t;
142
143 /*******************************************************************************
144 * API
145 ******************************************************************************/
146
147 #if defined(__cplusplus)
148 extern "C" {
149 #endif
150
151 /*! @name Configuration */
152 /*@{*/
153
154 /*!
155 * @brief Selects pin for modules.
156 *
157 * This API is used to select the port pin for the module with multiple port pin
158 * selection. For example the FTM Channel 0 can be mapped to ether PTA0 or PTB2.
159 * Select FTM channel 0 map to PTA0 port pin as:
160 * @code
161 * PORT_SetPinSelect(kPORT_FTM0CH0, kPORT_FTM0_CH0_PTA0);
162 * @endcode
163 *
164 * @note This API doesn't support to select specified ALT for a given port pin.
165 * The ALT feature is automatically selected by hardware according to the
166 * ALT priority:
167 * Low -----> high:
168 * Alt1, Alt2, …
169 * when peripheral modules has been enabled.
170 *
171 * If you want to select a specified ALT for a given port pin, please add two more
172 * steps after calling PORT_SetPinSelect:
173 * 1. Enable module or the port control in the module for the ALT you want to select.
174 * For I2C ALT feature:all port enable is controlled by the module enable, so
175 * set IICEN in I2CX_C1 to enable the port pins for I2C feature.
176 * For KBI ALT feature:each port pin is controlled independently by each bit in KBIx_PE.
177 * set related bit in this register to enable the KBI feature in the port pin.
178 * 2. Make sure there is no module enabled with higher priority than the ALT module feature
179 * you want to select.
180 *
181 * @param module Modules for pin selection.
182 * For NMI/RST module are write-once attribute after reset.
183 * @param pin Port pin selection for modules.
184 *
185 */
186 void PORT_SetPinSelect(port_module_t module, port_pin_select_t pin);
187
188 /*!
189 * @brief Selects the glitch filter for input pins.
190 *
191 * @param base PORT peripheral base pointer.
192 * @param port PORT pin, see "port_filter_pin_t".
193 * @param filter Filter select, see "port_filter_select_t".
194 */
PORT_SetFilterSelect(PORT_Type * base,port_filter_pin_t port,port_filter_select_t filter)195 static inline void PORT_SetFilterSelect(PORT_Type *base, port_filter_pin_t port, port_filter_select_t filter)
196 {
197 uint32_t fltReg;
198
199 /* Clear the filed to zero. */
200 fltReg = base->IOFLT & ~((uint32_t)FSL_PORT_FILTER_SELECT_BITMASK << (uint32_t)port);
201 /* Set the filter selection. */
202 base->IOFLT = ((uint32_t)filter << (uint32_t)port) | fltReg;
203 }
204
205 /*!
206 * @brief Sets the width threshold for glitch filter division set 1.
207 *`
208 * @param base PORT peripheral base pointer.
209 * @param threshold PORT glitch filter width threshold, take refer to reference manual for detail information.
210 * 0 - LPOCLK
211 * 1 - LPOCLK/2
212 * 2 - LPOCLK/4
213 * 3 - LPOCLK/8
214 * 4 - LPOCLK/16
215 * 5 - LPOCLK/32
216 * 6 - LPOCLK/64
217 * 7 - LPOCLK/128
218 */
PORT_SetFilterDIV1WidthThreshold(PORT_Type * base,uint8_t threshold)219 static inline void PORT_SetFilterDIV1WidthThreshold(PORT_Type *base, uint8_t threshold)
220 {
221 uint32_t fltReg;
222
223 fltReg = base->IOFLT & ~PORT_IOFLT_FLTDIV1_MASK;
224 base->IOFLT = fltReg | PORT_IOFLT_FLTDIV1(threshold);
225 }
226
227 /*!
228 * @brief Sets the width threshold for glitch filter division set 2.
229 *`
230 * @param base PORT peripheral base pointer.
231 * @param threshold PORT glitch filter width threshold, take refer to reference manual for detail information.
232 * 0 - BUSCLK/32
233 * 1 - BUSCLK/64
234 * 2 - BUSCLK/128
235 * 3 - BUSCLK/256
236 * 4 - BUSCLK/512
237 * 5 - BUSCLK/1024
238 * 6 - BUSCLK/2048
239 * 7 - BUSCLK/4096
240 */
PORT_SetFilterDIV2WidthThreshold(PORT_Type * base,uint8_t threshold)241 static inline void PORT_SetFilterDIV2WidthThreshold(PORT_Type *base, uint8_t threshold)
242 {
243 uint32_t fltReg;
244
245 fltReg = base->IOFLT & ~PORT_IOFLT_FLTDIV2_MASK;
246 base->IOFLT = fltReg | PORT_IOFLT_FLTDIV2(threshold);
247 }
248
249 /*!
250 * @brief Sets the width threshold for glitch filter division set 3.
251 *`
252 * @param base PORT peripheral base pointer.
253 * @param threshold PORT glitch filter width threshold, take refer to reference manual for detail information.
254 * 0 - BUSCLK/2
255 * 1 - BUSCLK/4
256 * 2 - BUSCLK/8
257 * 3 - BUSCLK/16
258 */
PORT_SetFilterDIV3WidthThreshold(PORT_Type * base,uint8_t threshold)259 static inline void PORT_SetFilterDIV3WidthThreshold(PORT_Type *base, uint8_t threshold)
260 {
261 uint32_t fltReg;
262
263 fltReg = base->IOFLT & ~PORT_IOFLT_FLTDIV3_MASK;
264 base->IOFLT = fltReg | PORT_IOFLT_FLTDIV3(threshold);
265 }
266
267 /*!
268 * @brief Enables or disables the port pull up.
269 *
270 * @param base PORT peripheral base pointer.
271 * @param port PORT type, such as PTA/PTB/PTC etc, see "port_type_t".
272 * @param num PORT Pin number, such as 0, 1, 2....
273 * There are seven pins not exists in this device:
274 * PTG: PTG4, PTG5, PTG6, PTG7. PTH: PTH3, PTH4, PTH5.
275 * so, when set PTG, and PTH, please don't set the pins mentioned above.
276 * Please take refer to the reference manual.
277 * @param enable Enable or disable the pull up feature switch.
278 */
279 void PORT_SetPinPullUpEnable(PORT_Type *base, port_type_t port, uint8_t num, bool enable);
280
281 /*!
282 * @brief Set High drive for port pins.
283 *
284 * @param base PORT peripheral base pointer.
285 * @param pin PORT pin support high drive.
286 * @param enable Enable or disable the high driver feature switch.
287 */
PORT_SetHighDriveEnable(PORT_Type * base,port_highdrive_pin_t pin,bool enable)288 static inline void PORT_SetHighDriveEnable(PORT_Type *base, port_highdrive_pin_t pin, bool enable)
289 {
290 if (enable)
291 {
292 base->HDRVE |= (uint32_t)pin;
293 }
294 else
295 {
296 base->HDRVE &= ~(uint32_t)pin;
297 }
298 }
299
300 /*@}*/
301
302 #if defined(__cplusplus)
303 }
304 #endif
305
306 /*! @}*/
307
308 #endif /* _FSL_PORT_H_ */
309
