1 /*
2 ** ###################################################################
3 **     Processors:          MIMXRT1176AVM8A_cm7
4 **                          MIMXRT1176CVM8A_cm7
5 **                          MIMXRT1176DVMAA_cm7
6 **
7 **     Compilers:           Freescale C/C++ for Embedded ARM
8 **                          GNU C Compiler
9 **                          IAR ANSI C/C++ Compiler for ARM
10 **                          Keil ARM C/C++ Compiler
11 **                          MCUXpresso Compiler
12 **
13 **     Reference manual:    IMXRT1170RM, Rev 1, 02/2021
14 **     Version:             rev. 1.0, 2020-12-29
15 **     Build:               b230914
16 **
17 **     Abstract:
18 **         CMSIS Peripheral Access Layer for MIMXRT1176_cm7
19 **
20 **     Copyright 1997-2016 Freescale Semiconductor, Inc.
21 **     Copyright 2016-2023 NXP
22 **     SPDX-License-Identifier: BSD-3-Clause
23 **
24 **     http:                 www.nxp.com
25 **     mail:                 support@nxp.com
26 **
27 **     Revisions:
28 **     - rev. 0.1 (2018-03-05)
29 **         Initial version.
30 **     - rev. 1.0 (2020-12-29)
31 **         Update header files to align with IMXRT1170RM Rev.0.
32 **
33 ** ###################################################################
34 */
35 
36 /*!
37  * @file MIMXRT1176_cm7.h
38  * @version 1.0
39  * @date 2020-12-29
40  * @brief CMSIS Peripheral Access Layer for MIMXRT1176_cm7
41  *
42  * CMSIS Peripheral Access Layer for MIMXRT1176_cm7
43  */
44 
45 #ifndef _MIMXRT1176_CM7_H_
46 #define _MIMXRT1176_CM7_H_                       /**< Symbol preventing repeated inclusion */
47 
48 /** Memory map major version (memory maps with equal major version number are
49  * compatible) */
50 #define MCU_MEM_MAP_VERSION 0x0100U
51 /** Memory map minor version */
52 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U
53 
54 /* ----------------------------------------------------------------------------
55    --
56    ---------------------------------------------------------------------------- */
57 
58 /* Extra XRDC2 definition */
59 #define XRDC2_MAKE_MEM(mrc, mrgd) (((mrc) << 5U) | (mrgd))
60 #define XRDC2_GET_MRC(mem) ((mem) >> 5U)
61 #define XRDC2_GET_MRGD(mem) ((mem) & 31U)
62 #define XRDC2_MAKE_PERIPH(pac, pdac) (((pac) << 8U) | (pdac))
63 #define XRDC2_GET_PAC(periph) ((periph) >> 8U)
64 #define XRDC2_GET_PDAC(periph) ((periph) & 255U)
65 
66 
67 
68 /* ----------------------------------------------------------------------------
69    -- Interrupt vector numbers
70    ---------------------------------------------------------------------------- */
71 
72 /*!
73  * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
74  * @{
75  */
76 
77 /** Interrupt Number Definitions */
78 #define NUMBER_OF_INT_VECTORS 234                /**< Number of interrupts in the Vector table */
79 
80 typedef enum IRQn {
81   /* Auxiliary constants */
82   NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
83 
84   /* Core interrupts */
85   NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
86   HardFault_IRQn               = -13,              /**< Cortex-M7 SV Hard Fault Interrupt */
87   MemoryManagement_IRQn        = -12,              /**< Cortex-M7 Memory Management Interrupt */
88   BusFault_IRQn                = -11,              /**< Cortex-M7 Bus Fault Interrupt */
89   UsageFault_IRQn              = -10,              /**< Cortex-M7 Usage Fault Interrupt */
90   SVCall_IRQn                  = -5,               /**< Cortex-M7 SV Call Interrupt */
91   DebugMonitor_IRQn            = -4,               /**< Cortex-M7 Debug Monitor Interrupt */
92   PendSV_IRQn                  = -2,               /**< Cortex-M7 Pend SV Interrupt */
93   SysTick_IRQn                 = -1,               /**< Cortex-M7 System Tick Interrupt */
94 
95   /* Device specific interrupts */
96   DMA0_DMA16_IRQn              = 0,                /**< DMA channel 0/16 transfer complete */
97   DMA1_DMA17_IRQn              = 1,                /**< DMA channel 1/17 transfer complete */
98   DMA2_DMA18_IRQn              = 2,                /**< DMA channel 2/18 transfer complete */
99   DMA3_DMA19_IRQn              = 3,                /**< DMA channel 3/19 transfer complete */
100   DMA4_DMA20_IRQn              = 4,                /**< DMA channel 4/20 transfer complete */
101   DMA5_DMA21_IRQn              = 5,                /**< DMA channel 5/21 transfer complete */
102   DMA6_DMA22_IRQn              = 6,                /**< DMA channel 6/22 transfer complete */
103   DMA7_DMA23_IRQn              = 7,                /**< DMA channel 7/23 transfer complete */
104   DMA8_DMA24_IRQn              = 8,                /**< DMA channel 8/24 transfer complete */
105   DMA9_DMA25_IRQn              = 9,                /**< DMA channel 9/25 transfer complete */
106   DMA10_DMA26_IRQn             = 10,               /**< DMA channel 10/26 transfer complete */
107   DMA11_DMA27_IRQn             = 11,               /**< DMA channel 11/27 transfer complete */
108   DMA12_DMA28_IRQn             = 12,               /**< DMA channel 12/28 transfer complete */
109   DMA13_DMA29_IRQn             = 13,               /**< DMA channel 13/29 transfer complete */
110   DMA14_DMA30_IRQn             = 14,               /**< DMA channel 14/30 transfer complete */
111   DMA15_DMA31_IRQn             = 15,               /**< DMA channel 15/31 transfer complete */
112   DMA_ERROR_IRQn               = 16,               /**< DMA error interrupt channels 0-15 / 16-31 */
113   CTI_TRIGGER_OUT0_IRQn        = 17,               /**< CTI_TRIGGER_OUT0 */
114   CTI_TRIGGER_OUT1_IRQn        = 18,               /**< CTI_TRIGGER_OUT1 */
115   CORE_IRQn                    = 19,               /**< CorePlatform exception IRQ */
116   LPUART1_IRQn                 = 20,               /**< LPUART1 TX interrupt and RX interrupt */
117   LPUART2_IRQn                 = 21,               /**< LPUART2 TX interrupt and RX interrupt */
118   LPUART3_IRQn                 = 22,               /**< LPUART3 TX interrupt and RX interrupt */
119   LPUART4_IRQn                 = 23,               /**< LPUART4 TX interrupt and RX interrupt */
120   LPUART5_IRQn                 = 24,               /**< LPUART5 TX interrupt and RX interrupt */
121   LPUART6_IRQn                 = 25,               /**< LPUART6 TX interrupt and RX interrupt */
122   LPUART7_IRQn                 = 26,               /**< LPUART7 TX interrupt and RX interrupt */
123   LPUART8_IRQn                 = 27,               /**< LPUART8 TX interrupt and RX interrupt */
124   LPUART9_IRQn                 = 28,               /**< LPUART9 TX interrupt and RX interrupt */
125   LPUART10_IRQn                = 29,               /**< LPUART10 TX interrupt and RX interrupt */
126   LPUART11_IRQn                = 30,               /**< LPUART11 TX interrupt and RX interrupt */
127   LPUART12_IRQn                = 31,               /**< LPUART12 TX interrupt and RX interrupt */
128   LPI2C1_IRQn                  = 32,               /**< LPI2C1 interrupt */
129   LPI2C2_IRQn                  = 33,               /**< LPI2C2 interrupt */
130   LPI2C3_IRQn                  = 34,               /**< LPI2C3 interrupt */
131   LPI2C4_IRQn                  = 35,               /**< LPI2C4 interrupt */
132   LPI2C5_IRQn                  = 36,               /**< LPI2C5 interrupt */
133   LPI2C6_IRQn                  = 37,               /**< LPI2C6 interrupt */
134   LPSPI1_IRQn                  = 38,               /**< LPSPI1 interrupt request line to the core */
135   LPSPI2_IRQn                  = 39,               /**< LPSPI2 interrupt request line to the core */
136   LPSPI3_IRQn                  = 40,               /**< LPSPI3 interrupt request line to the core */
137   LPSPI4_IRQn                  = 41,               /**< LPSPI4 interrupt request line to the core */
138   LPSPI5_IRQn                  = 42,               /**< LPSPI5 interrupt request line to the core */
139   LPSPI6_IRQn                  = 43,               /**< LPSPI6 interrupt request line to the core */
140   CAN1_IRQn                    = 44,               /**< CAN1 interrupt */
141   CAN1_ERROR_IRQn              = 45,               /**< CAN1 error interrupt */
142   CAN2_IRQn                    = 46,               /**< CAN2 interrupt */
143   CAN2_ERROR_IRQn              = 47,               /**< CAN2 error interrupt */
144   CAN3_IRQn                    = 48,               /**< CAN3 interrupt */
145   CAN3_ERROR_IRQn              = 49,               /**< CAN3 error interrupt */
146   FLEXRAM_IRQn                 = 50,               /**< FlexRAM address out of range Or access hit IRQ */
147   KPP_IRQn                     = 51,               /**< Keypad interrupt */
148   Reserved68_IRQn              = 52,               /**< Reserved interrupt */
149   GPR_IRQ_IRQn                 = 53,               /**< GPR interrupt */
150   eLCDIF_IRQn                  = 54,               /**< eLCDIF interrupt */
151   LCDIFv2_IRQn                 = 55,               /**< LCDIFv2 interrupt */
152   CSI_IRQn                     = 56,               /**< CSI interrupt */
153   PXP_IRQn                     = 57,               /**< PXP interrupt */
154   MIPI_CSI_IRQn                = 58,               /**< MIPI_CSI interrupt */
155   MIPI_DSI_IRQn                = 59,               /**< MIPI_DSI interrupt */
156   GPU2D_IRQn                   = 60,               /**< GPU2D interrupt */
157   GPIO6_Combined_0_15_IRQn     = 61,               /**< Combined interrupt indication for GPIO6 signal 0 throughout 15 */
158   GPIO6_Combined_16_31_IRQn    = 62,               /**< Combined interrupt indication for GPIO6 signal 16 throughout 31 */
159   DAC_IRQn                     = 63,               /**< DAC interrupt */
160   KEY_MANAGER_IRQn             = 64,               /**< PUF interrupt */
161   WDOG2_IRQn                   = 65,               /**< WDOG2 interrupt */
162   SNVS_HP_NON_TZ_IRQn          = 66,               /**< SRTC Consolidated Interrupt. Non TZ */
163   SNVS_HP_TZ_IRQn              = 67,               /**< SRTC Security Interrupt. TZ */
164   SNVS_PULSE_EVENT_IRQn        = 68,               /**< ON-OFF button press shorter than 5 secs (pulse event) */
165   CAAM_IRQ0_IRQn               = 69,               /**< CAAM interrupt queue for JQ0 */
166   CAAM_IRQ1_IRQn               = 70,               /**< CAAM interrupt queue for JQ1 */
167   CAAM_IRQ2_IRQn               = 71,               /**< CAAM interrupt queue for JQ2 */
168   CAAM_IRQ3_IRQn               = 72,               /**< CAAM interrupt queue for JQ3 */
169   CAAM_RECORVE_ERRPR_IRQn      = 73,               /**< CAAM interrupt for recoverable error */
170   CAAM_RTIC_IRQn               = 74,               /**< CAAM interrupt for RTIC */
171   CDOG_IRQn                    = 75,               /**< CDOG interrupt */
172   SAI1_IRQn                    = 76,               /**< SAI1 interrupt */
173   SAI2_IRQn                    = 77,               /**< SAI1 interrupt */
174   SAI3_RX_IRQn                 = 78,               /**< SAI3 interrupt */
175   SAI3_TX_IRQn                 = 79,               /**< SAI3 interrupt */
176   SAI4_RX_IRQn                 = 80,               /**< SAI4 interrupt */
177   SAI4_TX_IRQn                 = 81,               /**< SAI4 interrupt */
178   SPDIF_IRQn                   = 82,               /**< SPDIF interrupt */
179   TMPSNS_INT_IRQn              = 83,               /**< TMPSNS interrupt */
180   TMPSNS_LOW_HIGH_IRQn         = 84,               /**< TMPSNS low high interrupt */
181   TMPSNS_PANIC_IRQn            = 85,               /**< TMPSNS panic interrupt */
182   LPSR_LP8_BROWNOUT_IRQn       = 86,               /**< LPSR 1p8 brownout interrupt */
183   LPSR_LP0_BROWNOUT_IRQn       = 87,               /**< LPSR 1p0 brownout interrupt */
184   ADC1_IRQn                    = 88,               /**< ADC1 interrupt */
185   ADC2_IRQn                    = 89,               /**< ADC2 interrupt */
186   USBPHY1_IRQn                 = 90,               /**< USBPHY1 interrupt */
187   USBPHY2_IRQn                 = 91,               /**< USBPHY2 interrupt */
188   RDC_IRQn                     = 92,               /**< RDC interrupt */
189   GPIO13_Combined_0_31_IRQn    = 93,               /**< Combined interrupt indication for GPIO13 signal 0 throughout 31 */
190   Reserved110_IRQn             = 94,               /**< Reserved interrupt */
191   DCIC1_IRQn                   = 95,               /**< DCIC1 interrupt */
192   DCIC2_IRQn                   = 96,               /**< DCIC2 interrupt */
193   ASRC_IRQn                    = 97,               /**< ASRC interrupt */
194   FLEXRAM_ECC_IRQn             = 98,               /**< FlexRAM ECC fatal interrupt */
195   CM7_GPIO2_3_IRQn             = 99,               /**< CM7_GPIO2,CM7_GPIO3 interrupt */
196   GPIO1_Combined_0_15_IRQn     = 100,              /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
197   GPIO1_Combined_16_31_IRQn    = 101,              /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
198   GPIO2_Combined_0_15_IRQn     = 102,              /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
199   GPIO2_Combined_16_31_IRQn    = 103,              /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
200   GPIO3_Combined_0_15_IRQn     = 104,              /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
201   GPIO3_Combined_16_31_IRQn    = 105,              /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
202   GPIO4_Combined_0_15_IRQn     = 106,              /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
203   GPIO4_Combined_16_31_IRQn    = 107,              /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
204   GPIO5_Combined_0_15_IRQn     = 108,              /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
205   GPIO5_Combined_16_31_IRQn    = 109,              /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
206   FLEXIO1_IRQn                 = 110,              /**< FLEXIO1 interrupt */
207   FLEXIO2_IRQn                 = 111,              /**< FLEXIO2 interrupt */
208   WDOG1_IRQn                   = 112,              /**< WDOG1 interrupt */
209   RTWDOG3_IRQn                 = 113,              /**< RTWDOG3 interrupt */
210   EWM_IRQn                     = 114,              /**< EWM interrupt */
211   OCOTP_READ_FUSE_ERROR_IRQn   = 115,              /**< OCOTP read fuse error interrupt */
212   OCOTP_READ_DONE_ERROR_IRQn   = 116,              /**< OCOTP read fuse done interrupt */
213   GPC_IRQn                     = 117,              /**< GPC interrupt */
214   MUA_IRQn                     = 118,              /**< MUA interrupt */
215   GPT1_IRQn                    = 119,              /**< GPT1 interrupt */
216   GPT2_IRQn                    = 120,              /**< GPT2 interrupt */
217   GPT3_IRQn                    = 121,              /**< GPT3 interrupt */
218   GPT4_IRQn                    = 122,              /**< GPT4 interrupt */
219   GPT5_IRQn                    = 123,              /**< GPT5 interrupt */
220   GPT6_IRQn                    = 124,              /**< GPT6 interrupt */
221   PWM1_0_IRQn                  = 125,              /**< PWM1 capture 0, compare 0, or reload 0 interrupt */
222   PWM1_1_IRQn                  = 126,              /**< PWM1 capture 1, compare 1, or reload 0 interrupt */
223   PWM1_2_IRQn                  = 127,              /**< PWM1 capture 2, compare 2, or reload 0 interrupt */
224   PWM1_3_IRQn                  = 128,              /**< PWM1 capture 3, compare 3, or reload 0 interrupt */
225   PWM1_FAULT_IRQn              = 129,              /**< PWM1 fault or reload error interrupt */
226   FLEXSPI1_IRQn                = 130,              /**< FlexSPI1 interrupt */
227   FLEXSPI2_IRQn                = 131,              /**< FlexSPI2 interrupt */
228   SEMC_IRQn                    = 132,              /**< SEMC interrupt */
229   USDHC1_IRQn                  = 133,              /**< USDHC1 interrupt */
230   USDHC2_IRQn                  = 134,              /**< USDHC2 interrupt */
231   USB_OTG2_IRQn                = 135,              /**< USBO2 USB OTG2 */
232   USB_OTG1_IRQn                = 136,              /**< USBO2 USB OTG1 */
233   ENET_IRQn                    = 137,              /**< ENET interrupt */
234   ENET_1588_Timer_IRQn         = 138,              /**< ENET_1588_Timer interrupt */
235   ENET_1G_MAC0_Tx_Rx_1_IRQn    = 139,              /**< ENET 1G MAC0 transmit/receive 1 */
236   ENET_1G_MAC0_Tx_Rx_2_IRQn    = 140,              /**< ENET 1G MAC0 transmit/receive 2 */
237   ENET_1G_IRQn                 = 141,              /**< ENET 1G interrupt */
238   ENET_1G_1588_Timer_IRQn      = 142,              /**< ENET_1G_1588_Timer interrupt */
239   XBAR1_IRQ_0_1_IRQn           = 143,              /**< XBARA1 output signal 0, 1 interrupt */
240   XBAR1_IRQ_2_3_IRQn           = 144,              /**< XBARA1 output signal 2, 3 interrupt */
241   ADC_ETC_IRQ0_IRQn            = 145,              /**< ADCETC IRQ0 interrupt */
242   ADC_ETC_IRQ1_IRQn            = 146,              /**< ADCETC IRQ1 interrupt */
243   ADC_ETC_IRQ2_IRQn            = 147,              /**< ADCETC IRQ2 interrupt */
244   ADC_ETC_IRQ3_IRQn            = 148,              /**< ADCETC IRQ3 interrupt */
245   ADC_ETC_ERROR_IRQ_IRQn       = 149,              /**< ADCETC Error IRQ interrupt */
246   Reserved166_IRQn             = 150,              /**< Reserved interrupt */
247   Reserved167_IRQn             = 151,              /**< Reserved interrupt */
248   Reserved168_IRQn             = 152,              /**< Reserved interrupt */
249   Reserved169_IRQn             = 153,              /**< Reserved interrupt */
250   Reserved170_IRQn             = 154,              /**< Reserved interrupt */
251   PIT1_IRQn                    = 155,              /**< PIT1 interrupt */
252   PIT2_IRQn                    = 156,              /**< PIT2 interrupt */
253   ACMP1_IRQn                   = 157,              /**< ACMP interrupt */
254   ACMP2_IRQn                   = 158,              /**< ACMP interrupt */
255   ACMP3_IRQn                   = 159,              /**< ACMP interrupt */
256   ACMP4_IRQn                   = 160,              /**< ACMP interrupt */
257   Reserved177_IRQn             = 161,              /**< Reserved interrupt */
258   Reserved178_IRQn             = 162,              /**< Reserved interrupt */
259   Reserved179_IRQn             = 163,              /**< Reserved interrupt */
260   Reserved180_IRQn             = 164,              /**< Reserved interrupt */
261   ENC1_IRQn                    = 165,              /**< ENC1 interrupt */
262   ENC2_IRQn                    = 166,              /**< ENC2 interrupt */
263   ENC3_IRQn                    = 167,              /**< ENC3 interrupt */
264   ENC4_IRQn                    = 168,              /**< ENC4 interrupt */
265   Reserved185_IRQn             = 169,              /**< Reserved interrupt */
266   Reserved186_IRQn             = 170,              /**< Reserved interrupt */
267   TMR1_IRQn                    = 171,              /**< TMR1 interrupt */
268   TMR2_IRQn                    = 172,              /**< TMR2 interrupt */
269   TMR3_IRQn                    = 173,              /**< TMR3 interrupt */
270   TMR4_IRQn                    = 174,              /**< TMR4 interrupt */
271   SEMA4_CP0_IRQn               = 175,              /**< SEMA4 CP0 interrupt */
272   SEMA4_CP1_IRQn               = 176,              /**< SEMA4 CP1 interrupt */
273   PWM2_0_IRQn                  = 177,              /**< PWM2 capture 0, compare 0, or reload 0 interrupt */
274   PWM2_1_IRQn                  = 178,              /**< PWM2 capture 1, compare 1, or reload 0 interrupt */
275   PWM2_2_IRQn                  = 179,              /**< PWM2 capture 2, compare 2, or reload 0 interrupt */
276   PWM2_3_IRQn                  = 180,              /**< PWM2 capture 3, compare 3, or reload 0 interrupt */
277   PWM2_FAULT_IRQn              = 181,              /**< PWM2 fault or reload error interrupt */
278   PWM3_0_IRQn                  = 182,              /**< PWM3 capture 0, compare 0, or reload 0 interrupt */
279   PWM3_1_IRQn                  = 183,              /**< PWM3 capture 1, compare 1, or reload 0 interrupt */
280   PWM3_2_IRQn                  = 184,              /**< PWM3 capture 2, compare 2, or reload 0 interrupt */
281   PWM3_3_IRQn                  = 185,              /**< PWM3 capture 3, compare 3, or reload 0 interrupt */
282   PWM3_FAULT_IRQn              = 186,              /**< PWM3 fault or reload error interrupt */
283   PWM4_0_IRQn                  = 187,              /**< PWM4 capture 0, compare 0, or reload 0 interrupt */
284   PWM4_1_IRQn                  = 188,              /**< PWM4 capture 1, compare 1, or reload 0 interrupt */
285   PWM4_2_IRQn                  = 189,              /**< PWM4 capture 2, compare 2, or reload 0 interrupt */
286   PWM4_3_IRQn                  = 190,              /**< PWM4 capture 3, compare 3, or reload 0 interrupt */
287   PWM4_FAULT_IRQn              = 191,              /**< PWM4 fault or reload error interrupt */
288   Reserved208_IRQn             = 192,              /**< Reserved interrupt */
289   Reserved209_IRQn             = 193,              /**< Reserved interrupt */
290   Reserved210_IRQn             = 194,              /**< Reserved interrupt */
291   Reserved211_IRQn             = 195,              /**< Reserved interrupt */
292   Reserved212_IRQn             = 196,              /**< Reserved interrupt */
293   Reserved213_IRQn             = 197,              /**< Reserved interrupt */
294   Reserved214_IRQn             = 198,              /**< Reserved interrupt */
295   Reserved215_IRQn             = 199,              /**< Reserved interrupt */
296   PDM_HWVAD_EVENT_IRQn         = 200,              /**< HWVAD event interrupt */
297   PDM_HWVAD_ERROR_IRQn         = 201,              /**< HWVAD error interrupt */
298   PDM_EVENT_IRQn               = 202,              /**< PDM event interrupt */
299   PDM_ERROR_IRQn               = 203,              /**< PDM error interrupt */
300   EMVSIM1_IRQn                 = 204,              /**< EMVSIM1 interrupt */
301   EMVSIM2_IRQn                 = 205,              /**< EMVSIM2 interrupt */
302   MECC1_INT_IRQn               = 206,              /**< MECC1 int */
303   MECC1_FATAL_INT_IRQn         = 207,              /**< MECC1 fatal int */
304   MECC2_INT_IRQn               = 208,              /**< MECC2 int */
305   MECC2_FATAL_INT_IRQn         = 209,              /**< MECC2 fatal int */
306   XECC_FLEXSPI1_INT_IRQn       = 210,              /**< XECC int */
307   XECC_FLEXSPI1_FATAL_INT_IRQn = 211,              /**< XECC fatal int */
308   XECC_FLEXSPI2_INT_IRQn       = 212,              /**< XECC int */
309   XECC_FLEXSPI2_FATAL_INT_IRQn = 213,              /**< XECC fatal int */
310   XECC_SEMC_INT_IRQn           = 214,              /**< XECC int */
311   XECC_SEMC_FATAL_INT_IRQn     = 215,              /**< XECC fatal int */
312   ENET_QOS_IRQn                = 216,              /**< ENET_QOS interrupt */
313   ENET_QOS_PMT_IRQn            = 217               /**< ENET_QOS_PMT interrupt */
314 } IRQn_Type;
315 
316 /*!
317  * @}
318  */ /* end of group Interrupt_vector_numbers */
319 
320 
321 /* ----------------------------------------------------------------------------
322    -- Cortex M7 Core Configuration
323    ---------------------------------------------------------------------------- */
324 
325 /*!
326  * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
327  * @{
328  */
329 
330 #define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
331 #define __ICACHE_PRESENT               1         /**< Defines if an ICACHE is present or not */
332 #define __DCACHE_PRESENT               1         /**< Defines if an DCACHE is present or not */
333 #define __DTCM_PRESENT                 1         /**< Defines if an DTCM is present or not */
334 #define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
335 #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
336 #define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
337 
338 #include "core_cm7.h"                  /* Core Peripheral Access Layer */
339 #include "system_MIMXRT1176_cm7.h"     /* Device specific configuration file */
340 
341 /*!
342  * @}
343  */ /* end of group Cortex_Core_Configuration */
344 
345 
346 /* ----------------------------------------------------------------------------
347    -- Mapping Information
348    ---------------------------------------------------------------------------- */
349 
350 /*!
351  * @addtogroup Mapping_Information Mapping Information
352  * @{
353  */
354 
355 /** Mapping Information */
356 /*!
357  * @addtogroup rdc_mapping
358  * @{
359  */
360 
361 /*******************************************************************************
362  * Definitions
363  ******************************************************************************/
364 
365 /*!
366  * @brief Structure for the RDC mapping
367  *
368  * Defines the structure for the RDC resource collections.
369  */
370 /*
371  * Domain of these masters are not assigned by RDC
372  * CM7, CM7_DMA: Always use domain ID 0.
373  * CM4, CM4_DMA: Use domain ID 0 in single core case, 1 in dual core case.
374  * CAAM: Defined in CAAM mst_a[x]icid[10]
375  * LCDIFv2: Defined in LCDIF2 user bit[0]
376  * SSARC: Defined in SSARC user bit[0]
377  */
378 
379 typedef enum _rdc_master
380 {
381     kRDC_Master_ENET_1G_TX          = 1U,          /**< ENET_1G_TX */
382     kRDC_Master_ENET_1G_RX          = 2U,          /**< ENET_1G_RX */
383     kRDC_Master_ENET                = 3U,          /**< ENET */
384     kRDC_Master_ENET_QOS            = 4U,          /**< ENET_QOS */
385     kRDC_Master_USDHC1              = 5U,          /**< USDHC1 */
386     kRDC_Master_USDHC2              = 6U,          /**< USDHC2 */
387     kRDC_Master_USB                 = 7U,          /**< USB */
388     kRDC_Master_GPU                 = 8U,          /**< GPU */
389     kRDC_Master_PXP                 = 9U,          /**< PXP */
390     kRDC_Master_LCDIF               = 10U,         /**< LCDIF */
391     kRDC_Master_CSI                 = 11U,         /**< CSI */
392 } rdc_master_t;
393 
394 typedef enum _rdc_mem
395 {
396     kRDC_Mem_MRC0_0                 = 0U,
397     kRDC_Mem_MRC0_1                 = 1U,
398     kRDC_Mem_MRC0_2                 = 2U,
399     kRDC_Mem_MRC0_3                 = 3U,
400     kRDC_Mem_MRC0_4                 = 4U,
401     kRDC_Mem_MRC0_5                 = 5U,
402     kRDC_Mem_MRC0_6                 = 6U,
403     kRDC_Mem_MRC0_7                 = 7U,
404     kRDC_Mem_MRC1_0                 = 8U,
405     kRDC_Mem_MRC1_1                 = 9U,
406     kRDC_Mem_MRC1_2                 = 10U,
407     kRDC_Mem_MRC1_3                 = 11U,
408     kRDC_Mem_MRC1_4                 = 12U,
409     kRDC_Mem_MRC1_5                 = 13U,
410     kRDC_Mem_MRC1_6                 = 14U,
411     kRDC_Mem_MRC1_7                 = 15U,
412     kRDC_Mem_MRC2_0                 = 16U,
413     kRDC_Mem_MRC2_1                 = 17U,
414     kRDC_Mem_MRC2_2                 = 18U,
415     kRDC_Mem_MRC2_3                 = 19U,
416     kRDC_Mem_MRC2_4                 = 20U,
417     kRDC_Mem_MRC2_5                 = 21U,
418     kRDC_Mem_MRC2_6                 = 22U,
419     kRDC_Mem_MRC2_7                 = 23U,
420     kRDC_Mem_MRC3_0                 = 24U,
421     kRDC_Mem_MRC3_1                 = 25U,
422     kRDC_Mem_MRC3_2                 = 26U,
423     kRDC_Mem_MRC3_3                 = 27U,
424     kRDC_Mem_MRC3_4                 = 28U,
425     kRDC_Mem_MRC3_5                 = 29U,
426     kRDC_Mem_MRC3_6                 = 30U,
427     kRDC_Mem_MRC3_7                 = 31U,
428     kRDC_Mem_MRC4_0                 = 32U,
429     kRDC_Mem_MRC4_1                 = 33U,
430     kRDC_Mem_MRC4_2                 = 34U,
431     kRDC_Mem_MRC4_3                 = 35U,
432     kRDC_Mem_MRC4_4                 = 36U,
433     kRDC_Mem_MRC4_5                 = 37U,
434     kRDC_Mem_MRC4_6                 = 38U,
435     kRDC_Mem_MRC4_7                 = 39U,
436     kRDC_Mem_MRC5_0                 = 40U,
437     kRDC_Mem_MRC5_1                 = 41U,
438     kRDC_Mem_MRC5_2                 = 42U,
439     kRDC_Mem_MRC5_3                 = 43U,
440     kRDC_Mem_MRC6_0                 = 44U,
441     kRDC_Mem_MRC6_1                 = 45U,
442     kRDC_Mem_MRC6_2                 = 46U,
443     kRDC_Mem_MRC6_3                 = 47U,
444     kRDC_Mem_MRC7_0                 = 48U,
445     kRDC_Mem_MRC7_1                 = 49U,
446     kRDC_Mem_MRC7_2                 = 50U,
447     kRDC_Mem_MRC7_3                 = 51U,
448     kRDC_Mem_MRC7_4                 = 52U,
449     kRDC_Mem_MRC7_5                 = 53U,
450     kRDC_Mem_MRC7_6                 = 54U,
451     kRDC_Mem_MRC7_7                 = 55U,
452     kRDC_Mem_MRC8_0                 = 56U,
453     kRDC_Mem_MRC8_1                 = 57U,
454     kRDC_Mem_MRC8_2                 = 58U,
455 } rdc_mem_t;
456 
457 typedef enum _rdc_periph
458 {
459     kRDC_Periph_MTR                 = 0U,          /**< MTR */
460     kRDC_Periph_MECC1               = 1U,          /**< MECC1 */
461     kRDC_Periph_MECC2               = 2U,          /**< MECC2 */
462     kRDC_Periph_FLEXSPI1            = 3U,          /**< FlexSPI1 */
463     kRDC_Periph_FLEXSPI2            = 4U,          /**< FlexSPI2 */
464     kRDC_Periph_SEMC                = 5U,          /**< SEMC */
465     kRDC_Periph_CM7_IMXRT           = 6U,          /**< CM7_IMXRT */
466     kRDC_Periph_EWM                 = 7U,          /**< EWM */
467     kRDC_Periph_WDOG1               = 8U,          /**< WDOG1 */
468     kRDC_Periph_WDOG2               = 9U,          /**< WDOG2 */
469     kRDC_Periph_WDOG3               = 10U,         /**< WDOG3 */
470     kRDC_Periph_AOI_XBAR            = 11U,         /**< AOI_XBAR */
471     kRDC_Periph_ADC_ETC             = 12U,         /**< ADC_ETC */
472     kRDC_Periph_CAAM_1              = 13U,         /**< CAAM_1 */
473     kRDC_Periph_ADC1                = 14U,         /**< ADC1 */
474     kRDC_Periph_ADC2                = 15U,         /**< ADC2 */
475     kRDC_Periph_TSC_DIG             = 16U,         /**< TSC_DIG */
476     kRDC_Periph_DAC                 = 17U,         /**< DAC */
477     kRDC_Periph_IEE                 = 18U,         /**< IEE */
478     kRDC_Periph_DMAMUX              = 19U,         /**< DMAMUX */
479     kRDC_Periph_EDMA                = 19U,         /**< EDMA */
480     kRDC_Periph_LPUART1             = 20U,         /**< LPUART1 */
481     kRDC_Periph_LPUART2             = 21U,         /**< LPUART2 */
482     kRDC_Periph_LPUART3             = 22U,         /**< LPUART3 */
483     kRDC_Periph_LPUART4             = 23U,         /**< LPUART4 */
484     kRDC_Periph_LPUART5             = 24U,         /**< LPUART5 */
485     kRDC_Periph_LPUART6             = 25U,         /**< LPUART6 */
486     kRDC_Periph_LPUART7             = 26U,         /**< LPUART7 */
487     kRDC_Periph_LPUART8             = 27U,         /**< LPUART8 */
488     kRDC_Periph_LPUART9             = 28U,         /**< LPUART9 */
489     kRDC_Periph_LPUART10            = 29U,         /**< LPUART10 */
490     kRDC_Periph_FLEXIO1             = 30U,         /**< FlexIO1 */
491     kRDC_Periph_FLEXIO2             = 31U,         /**< FlexIO2 */
492     kRDC_Periph_CAN1                = 32U,         /**< CAN1 */
493     kRDC_Periph_CAN2                = 33U,         /**< CAN2 */
494     kRDC_Periph_PIT1                = 34U,         /**< PIT1 */
495     kRDC_Periph_KPP                 = 35U,         /**< KPP */
496     kRDC_Periph_IOMUXC_GPR          = 36U,         /**< IOMUXC_GPR */
497     kRDC_Periph_IOMUXC              = 37U,         /**< IOMUXC */
498     kRDC_Periph_GPT1                = 38U,         /**< GPT1 */
499     kRDC_Periph_GPT2                = 39U,         /**< GPT2 */
500     kRDC_Periph_GPT3                = 40U,         /**< GPT3 */
501     kRDC_Periph_GPT4                = 41U,         /**< GPT4 */
502     kRDC_Periph_GPT5                = 42U,         /**< GPT5 */
503     kRDC_Periph_GPT6                = 43U,         /**< GPT6 */
504     kRDC_Periph_LPI2C1              = 44U,         /**< LPI2C1 */
505     kRDC_Periph_LPI2C2              = 45U,         /**< LPI2C2 */
506     kRDC_Periph_LPI2C3              = 46U,         /**< LPI2C3 */
507     kRDC_Periph_LPI2C4              = 47U,         /**< LPI2C4 */
508     kRDC_Periph_LPSPI1              = 48U,         /**< LPSPI1 */
509     kRDC_Periph_LPSPI2              = 49U,         /**< LPSPI2 */
510     kRDC_Periph_LPSPI3              = 50U,         /**< LPSPI3 */
511     kRDC_Periph_LPSPI4              = 51U,         /**< LPSPI4 */
512     kRDC_Periph_GPIO_1_6            = 52U,         /**< GPIO_1_6 */
513     kRDC_Periph_CCM_OBS             = 53U,         /**< CCM_OBS */
514     kRDC_Periph_SIM1                = 54U,         /**< SIM1 */
515     kRDC_Periph_SIM2                = 55U,         /**< SIM2 */
516     kRDC_Periph_QTIMER1             = 56U,         /**< QTimer1 */
517     kRDC_Periph_QTIMER2             = 57U,         /**< QTimer2 */
518     kRDC_Periph_QTIMER3             = 58U,         /**< QTimer3 */
519     kRDC_Periph_QTIMER4             = 59U,         /**< QTimer4 */
520     kRDC_Periph_ENC1                = 60U,         /**< ENC1 */
521     kRDC_Periph_ENC2                = 61U,         /**< ENC2 */
522     kRDC_Periph_ENC3                = 62U,         /**< ENC3 */
523     kRDC_Periph_ENC4                = 63U,         /**< ENC4 */
524     kRDC_Periph_FLEXPWM1            = 64U,         /**< FLEXPWM1 */
525     kRDC_Periph_FLEXPWM2            = 65U,         /**< FLEXPWM2 */
526     kRDC_Periph_FLEXPWM3            = 66U,         /**< FLEXPWM3 */
527     kRDC_Periph_FLEXPWM4            = 67U,         /**< FLEXPWM4 */
528     kRDC_Periph_CAAM_2              = 68U,         /**< CAAM_2 */
529     kRDC_Periph_CAAM_3              = 69U,         /**< CAAM_3 */
530     kRDC_Periph_ACMP1               = 70U,         /**< ACMP1 */
531     kRDC_Periph_ACMP2               = 71U,         /**< ACMP2 */
532     kRDC_Periph_ACMP3               = 72U,         /**< ACMP3 */
533     kRDC_Periph_ACMP4               = 73U,         /**< ACMP4 */
534     kRDC_Periph_CAAM                = 74U,         /**< CAAM */
535     kRDC_Periph_SPDIF               = 75U,         /**< SPDIF */
536     kRDC_Periph_SAI1                = 76U,         /**< SAI1 */
537     kRDC_Periph_SAI2                = 77U,         /**< SAI2 */
538     kRDC_Periph_SAI3                = 78U,         /**< SAI3 */
539     kRDC_Periph_ASRC                = 79U,         /**< ASRC */
540     kRDC_Periph_USDHC1              = 80U,         /**< USDHC1 */
541     kRDC_Periph_USDHC2              = 81U,         /**< USDHC2 */
542     kRDC_Periph_ENET_1G             = 82U,         /**< ENET_1G */
543     kRDC_Periph_ENET                = 83U,         /**< ENET */
544     kRDC_Periph_USB_PL301           = 84U,         /**< USB_PL301 */
545     kRDC_Periph_USBPHY2             = 85U,         /**< USBPHY2 */
546     kRDC_Periph_USB_OTG2            = 85U,         /**< USB_OTG2 */
547     kRDC_Periph_USBPHY1             = 86U,         /**< USBPHY1 */
548     kRDC_Periph_USB_OTG1            = 86U,         /**< USB_OTG1 */
549     kRDC_Periph_ENET_QOS            = 87U,         /**< ENET_QOS */
550     kRDC_Periph_CAAM_5              = 88U,         /**< CAAM_5 */
551     kRDC_Periph_CSI                 = 89U,         /**< CSI */
552     kRDC_Periph_LCDIF1              = 90U,         /**< LCDIF1 */
553     kRDC_Periph_LCDIF2              = 91U,         /**< LCDIF2 */
554     kRDC_Periph_MIPI_DSI            = 92U,         /**< MIPI_DSI */
555     kRDC_Periph_MIPI_CSI            = 93U,         /**< MIPI_CSI */
556     kRDC_Periph_PXP                 = 94U,         /**< PXP */
557     kRDC_Periph_VIDEO_MUX           = 95U,         /**< VIDEO_MUX */
558     kRDC_Periph_PGMC_SRC_GPC        = 96U,         /**< PGMC_SRC_GPC */
559     kRDC_Periph_IOMUXC_LPSR         = 97U,         /**< IOMUXC_LPSR */
560     kRDC_Periph_IOMUXC_LPSR_GPR     = 98U,         /**< IOMUXC_LPSR_GPR */
561     kRDC_Periph_WDOG4               = 99U,         /**< WDOG4 */
562     kRDC_Periph_DMAMUX_LPSR         = 100U,        /**< DMAMUX_LPSR */
563     kRDC_Periph_EDMA_LPSR           = 100U,        /**< EDMA_LPSR */
564     kRDC_Periph_Reserved            = 101U,        /**< Reserved */
565     kRDC_Periph_MIC                 = 102U,        /**< MIC */
566     kRDC_Periph_LPUART11            = 103U,        /**< LPUART11 */
567     kRDC_Periph_LPUART12            = 104U,        /**< LPUART12 */
568     kRDC_Periph_LPSPI5              = 105U,        /**< LPSPI5 */
569     kRDC_Periph_LPSPI6              = 106U,        /**< LPSPI6 */
570     kRDC_Periph_LPI2C5              = 107U,        /**< LPI2C5 */
571     kRDC_Periph_LPI2C6              = 108U,        /**< LPI2C6 */
572     kRDC_Periph_CAN3                = 109U,        /**< CAN3 */
573     kRDC_Periph_SAI4                = 110U,        /**< SAI4 */
574     kRDC_Periph_SEMA1               = 111U,        /**< SEMA1 */
575     kRDC_Periph_GPIO_7_12           = 112U,        /**< GPIO_7_12 */
576     kRDC_Periph_KEY_MANAGER         = 113U,        /**< KEY_MANAGER */
577     kRDC_Periph_ANATOP              = 114U,        /**< ANATOP */
578     kRDC_Periph_SNVS_HP_WRAPPER     = 115U,        /**< SNVS_HP_WRAPPER */
579     kRDC_Periph_IOMUXC_SNVS         = 116U,        /**< IOMUXC_SNVS */
580     kRDC_Periph_IOMUXC_SNVS_GPR     = 117U,        /**< IOMUXC_SNVS_GPR */
581     kRDC_Periph_SNVS_SRAM           = 118U,        /**< SNVS_SRAM */
582     kRDC_Periph_GPIO13              = 119U,        /**< GPIO13 */
583     kRDC_Periph_ROMCP               = 120U,        /**< ROMCP */
584     kRDC_Periph_DCDC                = 121U,        /**< DCDC */
585     kRDC_Periph_OCOTP_CTRL_WRAPPER  = 122U,        /**< OCOTP_CTRL_WRAPPER */
586     kRDC_Periph_PIT2                = 123U,        /**< PIT2 */
587     kRDC_Periph_SSARC               = 124U,        /**< SSARC */
588     kRDC_Periph_CCM                 = 125U,        /**< CCM */
589     kRDC_Periph_CAAM_6              = 126U,        /**< CAAM_6 */
590     kRDC_Periph_CAAM_7              = 127U,        /**< CAAM_7 */
591 } rdc_periph_t;
592 
593 /* @} */
594 
595 typedef enum _xbar_input_signal
596 {
597     kXBARA1_InputLogicLow           = 0|0x100U,    /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */
598     kXBARA1_InputLogicHigh          = 1|0x100U,    /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */
599     kXBARA1_InputRESERVED2          = 2|0x100U,    /**< XBARA1_IN2 input is reserved. */
600     kXBARA1_InputRESERVED3          = 3|0x100U,    /**< XBARA1_IN3 input is reserved. */
601     kXBARA1_InputIomuxXbarInout04   = 4|0x100U,    /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
602     kXBARA1_InputIomuxXbarInout05   = 5|0x100U,    /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
603     kXBARA1_InputIomuxXbarInout06   = 6|0x100U,    /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
604     kXBARA1_InputIomuxXbarInout07   = 7|0x100U,    /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
605     kXBARA1_InputIomuxXbarInout08   = 8|0x100U,    /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
606     kXBARA1_InputIomuxXbarInout09   = 9|0x100U,    /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
607     kXBARA1_InputIomuxXbarInout10   = 10|0x100U,   /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
608     kXBARA1_InputIomuxXbarInout11   = 11|0x100U,   /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
609     kXBARA1_InputIomuxXbarInout12   = 12|0x100U,   /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
610     kXBARA1_InputIomuxXbarInout13   = 13|0x100U,   /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
611     kXBARA1_InputIomuxXbarInout14   = 14|0x100U,   /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
612     kXBARA1_InputIomuxXbarInout15   = 15|0x100U,   /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
613     kXBARA1_InputIomuxXbarInout16   = 16|0x100U,   /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
614     kXBARA1_InputIomuxXbarInout17   = 17|0x100U,   /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
615     kXBARA1_InputIomuxXbarInout18   = 18|0x100U,   /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
616     kXBARA1_InputIomuxXbarInout19   = 19|0x100U,   /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
617     kXBARA1_InputIomuxXbarInout20   = 20|0x100U,   /**< IOMUX_XBAR_INOUT20 output assigned to XBARA1_IN20 input. */
618     kXBARA1_InputIomuxXbarInout21   = 21|0x100U,   /**< IOMUX_XBAR_INOUT21 output assigned to XBARA1_IN21 input. */
619     kXBARA1_InputIomuxXbarInout22   = 22|0x100U,   /**< IOMUX_XBAR_INOUT22 output assigned to XBARA1_IN22 input. */
620     kXBARA1_InputIomuxXbarInout23   = 23|0x100U,   /**< IOMUX_XBAR_INOUT23 output assigned to XBARA1_IN23 input. */
621     kXBARA1_InputIomuxXbarInout24   = 24|0x100U,   /**< IOMUX_XBAR_INOUT24 output assigned to XBARA1_IN24 input. */
622     kXBARA1_InputIomuxXbarInout25   = 25|0x100U,   /**< IOMUX_XBAR_INOUT25 output assigned to XBARA1_IN25 input. */
623     kXBARA1_InputIomuxXbarInout26   = 26|0x100U,   /**< IOMUX_XBAR_INOUT26 output assigned to XBARA1_IN26 input. */
624     kXBARA1_InputIomuxXbarInout27   = 27|0x100U,   /**< IOMUX_XBAR_INOUT27 output assigned to XBARA1_IN27 input. */
625     kXBARA1_InputIomuxXbarInout28   = 28|0x100U,   /**< IOMUX_XBAR_INOUT28 output assigned to XBARA1_IN28 input. */
626     kXBARA1_InputIomuxXbarInout29   = 29|0x100U,   /**< IOMUX_XBAR_INOUT29 output assigned to XBARA1_IN29 input. */
627     kXBARA1_InputIomuxXbarInout30   = 30|0x100U,   /**< IOMUX_XBAR_INOUT30 output assigned to XBARA1_IN30 input. */
628     kXBARA1_InputIomuxXbarInout31   = 31|0x100U,   /**< IOMUX_XBAR_INOUT31 output assigned to XBARA1_IN31 input. */
629     kXBARA1_InputIomuxXbarInout32   = 32|0x100U,   /**< IOMUX_XBAR_INOUT32 output assigned to XBARA1_IN32 input. */
630     kXBARA1_InputIomuxXbarInout33   = 33|0x100U,   /**< IOMUX_XBAR_INOUT33 output assigned to XBARA1_IN33 input. */
631     kXBARA1_InputIomuxXbarInout34   = 34|0x100U,   /**< IOMUX_XBAR_INOUT34 output assigned to XBARA1_IN34 input. */
632     kXBARA1_InputIomuxXbarInout35   = 35|0x100U,   /**< IOMUX_XBAR_INOUT35 output assigned to XBARA1_IN35 input. */
633     kXBARA1_InputIomuxXbarInout36   = 36|0x100U,   /**< IOMUX_XBAR_INOUT36 output assigned to XBARA1_IN36 input. */
634     kXBARA1_InputIomuxXbarInout37   = 37|0x100U,   /**< IOMUX_XBAR_INOUT37 output assigned to XBARA1_IN37 input. */
635     kXBARA1_InputIomuxXbarInout38   = 38|0x100U,   /**< IOMUX_XBAR_INOUT38 output assigned to XBARA1_IN38 input. */
636     kXBARA1_InputIomuxXbarInout39   = 39|0x100U,   /**< IOMUX_XBAR_INOUT39 output assigned to XBARA1_IN39 input. */
637     kXBARA1_InputIomuxXbarInout40   = 40|0x100U,   /**< IOMUX_XBAR_INOUT40 output assigned to XBARA1_IN40 input. */
638     kXBARA1_InputRESERVED41         = 41|0x100U,   /**< XBARA1_IN41 input is reserved. */
639     kXBARA1_InputAcmp1Out           = 42|0x100U,   /**< ACMP1_OUT output assigned to XBARA1_IN42 input. */
640     kXBARA1_InputAcmp2Out           = 43|0x100U,   /**< ACMP2_OUT output assigned to XBARA1_IN43 input. */
641     kXBARA1_InputAcmp3Out           = 44|0x100U,   /**< ACMP3_OUT output assigned to XBARA1_IN44 input. */
642     kXBARA1_InputAcmp4Out           = 45|0x100U,   /**< ACMP4_OUT output assigned to XBARA1_IN45 input. */
643     kXBARA1_InputRESERVED46         = 46|0x100U,   /**< XBARA1_IN46 input is reserved. */
644     kXBARA1_InputRESERVED47         = 47|0x100U,   /**< XBARA1_IN47 input is reserved. */
645     kXBARA1_InputRESERVED48         = 48|0x100U,   /**< XBARA1_IN48 input is reserved. */
646     kXBARA1_InputRESERVED49         = 49|0x100U,   /**< XBARA1_IN49 input is reserved. */
647     kXBARA1_InputQtimer1Timer0      = 50|0x100U,   /**< QTIMER1_TIMER0 output assigned to XBARA1_IN50 input. */
648     kXBARA1_InputQtimer1Timer1      = 51|0x100U,   /**< QTIMER1_TIMER1 output assigned to XBARA1_IN51 input. */
649     kXBARA1_InputQtimer1Timer2      = 52|0x100U,   /**< QTIMER1_TIMER2 output assigned to XBARA1_IN52 input. */
650     kXBARA1_InputQtimer1Timer3      = 53|0x100U,   /**< QTIMER1_TIMER3 output assigned to XBARA1_IN53 input. */
651     kXBARA1_InputQtimer2Timer0      = 54|0x100U,   /**< QTIMER2_TIMER0 output assigned to XBARA1_IN54 input. */
652     kXBARA1_InputQtimer2Timer1      = 55|0x100U,   /**< QTIMER2_TIMER1 output assigned to XBARA1_IN55 input. */
653     kXBARA1_InputQtimer2Timer2      = 56|0x100U,   /**< QTIMER2_TIMER2 output assigned to XBARA1_IN56 input. */
654     kXBARA1_InputQtimer2Timer3      = 57|0x100U,   /**< QTIMER2_TIMER3 output assigned to XBARA1_IN57 input. */
655     kXBARA1_InputQtimer3Timer0      = 58|0x100U,   /**< QTIMER3_TIMER0 output assigned to XBARA1_IN58 input. */
656     kXBARA1_InputQtimer3Timer1      = 59|0x100U,   /**< QTIMER3_TIMER1 output assigned to XBARA1_IN59 input. */
657     kXBARA1_InputQtimer3Timer2      = 60|0x100U,   /**< QTIMER3_TIMER2 output assigned to XBARA1_IN60 input. */
658     kXBARA1_InputQtimer3Timer3      = 61|0x100U,   /**< QTIMER3_TIMER3 output assigned to XBARA1_IN61 input. */
659     kXBARA1_InputQtimer4Timer0      = 62|0x100U,   /**< QTIMER4_TIMER0 output assigned to XBARA1_IN62 input. */
660     kXBARA1_InputQtimer4Timer1      = 63|0x100U,   /**< QTIMER4_TIMER1 output assigned to XBARA1_IN63 input. */
661     kXBARA1_InputQtimer4Timer2      = 64|0x100U,   /**< QTIMER4_TIMER2 output assigned to XBARA1_IN64 input. */
662     kXBARA1_InputQtimer4Timer3      = 65|0x100U,   /**< QTIMER4_TIMER3 output assigned to XBARA1_IN65 input. */
663     kXBARA1_InputRESERVED66         = 66|0x100U,   /**< XBARA1_IN66 input is reserved. */
664     kXBARA1_InputRESERVED67         = 67|0x100U,   /**< XBARA1_IN67 input is reserved. */
665     kXBARA1_InputRESERVED68         = 68|0x100U,   /**< XBARA1_IN68 input is reserved. */
666     kXBARA1_InputRESERVED69         = 69|0x100U,   /**< XBARA1_IN69 input is reserved. */
667     kXBARA1_InputRESERVED70         = 70|0x100U,   /**< XBARA1_IN70 input is reserved. */
668     kXBARA1_InputRESERVED71         = 71|0x100U,   /**< XBARA1_IN71 input is reserved. */
669     kXBARA1_InputRESERVED72         = 72|0x100U,   /**< XBARA1_IN72 input is reserved. */
670     kXBARA1_InputRESERVED73         = 73|0x100U,   /**< XBARA1_IN73 input is reserved. */
671     kXBARA1_InputFlexpwm1Pwm0OutTrig0 = 74|0x100U, /**< FLEXPWM1_PWM0_OUT_TRIG0 output assigned to XBARA1_IN74 input. */
672     kXBARA1_InputFlexpwm1Pwm0OutTrig1 = 75|0x100U, /**< FLEXPWM1_PWM0_OUT_TRIG1 output assigned to XBARA1_IN75 input. */
673     kXBARA1_InputFlexpwm1Pwm1OutTrig0 = 76|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0 output assigned to XBARA1_IN76 input. */
674     kXBARA1_InputFlexpwm1Pwm1OutTrig1 = 77|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG1 output assigned to XBARA1_IN77 input. */
675     kXBARA1_InputFlexpwm1Pwm2OutTrig0 = 78|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0 output assigned to XBARA1_IN78 input. */
676     kXBARA1_InputFlexpwm1Pwm2OutTrig1 = 79|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG1 output assigned to XBARA1_IN79 input. */
677     kXBARA1_InputFlexpwm1Pwm3OutTrig0 = 80|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0 output assigned to XBARA1_IN80 input. */
678     kXBARA1_InputFlexpwm1Pwm3OutTrig1 = 81|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG1 output assigned to XBARA1_IN81 input. */
679     kXBARA1_InputFlexpwm2Pwm0OutTrig01 = 82|0x100U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN82 input. */
680     kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 83|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN83 input. */
681     kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 84|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN84 input. */
682     kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 85|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN85 input. */
683     kXBARA1_InputFlexpwm3Pwm0OutTrig01 = 86|0x100U, /**< FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN86 input. */
684     kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 87|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN87 input. */
685     kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 88|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN88 input. */
686     kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 89|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN89 input. */
687     kXBARA1_InputFlexpwm4Pwm0OutTrig01 = 90|0x100U, /**< FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN90 input. */
688     kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 91|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN91 input. */
689     kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 92|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN92 input. */
690     kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 93|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN93 input. */
691     kXBARA1_InputRESERVED94         = 94|0x100U,   /**< XBARA1_IN94 input is reserved. */
692     kXBARA1_InputRESERVED95         = 95|0x100U,   /**< XBARA1_IN95 input is reserved. */
693     kXBARA1_InputRESERVED96         = 96|0x100U,   /**< XBARA1_IN96 input is reserved. */
694     kXBARA1_InputRESERVED97         = 97|0x100U,   /**< XBARA1_IN97 input is reserved. */
695     kXBARA1_InputRESERVED98         = 98|0x100U,   /**< XBARA1_IN98 input is reserved. */
696     kXBARA1_InputRESERVED99         = 99|0x100U,   /**< XBARA1_IN99 input is reserved. */
697     kXBARA1_InputRESERVED100        = 100|0x100U,  /**< XBARA1_IN100 input is reserved. */
698     kXBARA1_InputRESERVED101        = 101|0x100U,  /**< XBARA1_IN101 input is reserved. */
699     kXBARA1_InputPit1Trigger0       = 102|0x100U,  /**< PIT1_TRIGGER0 output assigned to XBARA1_IN102 input. */
700     kXBARA1_InputPit1Trigger1       = 103|0x100U,  /**< PIT1_TRIGGER1 output assigned to XBARA1_IN103 input. */
701     kXBARA1_InputPit1Trigger2       = 104|0x100U,  /**< PIT1_TRIGGER2 output assigned to XBARA1_IN104 input. */
702     kXBARA1_InputPit1Trigger3       = 105|0x100U,  /**< PIT1_TRIGGER3 output assigned to XBARA1_IN105 input. */
703     kXBARA1_InputDec1PosMatch       = 106|0x100U,  /**< DEC1_POS_MATCH output assigned to XBARA1_IN106 input. */
704     kXBARA1_InputDec2PosMatch       = 107|0x100U,  /**< DEC2_POS_MATCH output assigned to XBARA1_IN107 input. */
705     kXBARA1_InputDec3PosMatch       = 108|0x100U,  /**< DEC3_POS_MATCH output assigned to XBARA1_IN108 input. */
706     kXBARA1_InputDec4PosMatch       = 109|0x100U,  /**< DEC4_POS_MATCH output assigned to XBARA1_IN109 input. */
707     kXBARA1_InputRESERVED110        = 110|0x100U,  /**< XBARA1_IN110 input is reserved. */
708     kXBARA1_InputRESERVED111        = 111|0x100U,  /**< XBARA1_IN111 input is reserved. */
709     kXBARA1_InputDmaDone0           = 112|0x100U,  /**< DMA_DONE0 output assigned to XBARA1_IN112 input. */
710     kXBARA1_InputDmaDone1           = 113|0x100U,  /**< DMA_DONE1 output assigned to XBARA1_IN113 input. */
711     kXBARA1_InputDmaDone2           = 114|0x100U,  /**< DMA_DONE2 output assigned to XBARA1_IN114 input. */
712     kXBARA1_InputDmaDone3           = 115|0x100U,  /**< DMA_DONE3 output assigned to XBARA1_IN115 input. */
713     kXBARA1_InputDmaDone4           = 116|0x100U,  /**< DMA_DONE4 output assigned to XBARA1_IN116 input. */
714     kXBARA1_InputDmaDone5           = 117|0x100U,  /**< DMA_DONE5 output assigned to XBARA1_IN117 input. */
715     kXBARA1_InputDmaDone6           = 118|0x100U,  /**< DMA_DONE6 output assigned to XBARA1_IN118 input. */
716     kXBARA1_InputDmaDone7           = 119|0x100U,  /**< DMA_DONE7 output assigned to XBARA1_IN119 input. */
717     kXBARA1_InputDmaLpsrDone0       = 120|0x100U,  /**< DMA_LPSR_DONE0 output assigned to XBARA1_IN120 input. */
718     kXBARA1_InputDmaLpsrDone1       = 121|0x100U,  /**< DMA_LPSR_DONE1 output assigned to XBARA1_IN121 input. */
719     kXBARA1_InputDmaLpsrDone2       = 122|0x100U,  /**< DMA_LPSR_DONE2 output assigned to XBARA1_IN122 input. */
720     kXBARA1_InputDmaLpsrDone3       = 123|0x100U,  /**< DMA_LPSR_DONE3 output assigned to XBARA1_IN123 input. */
721     kXBARA1_InputDmaLpsrDone4       = 124|0x100U,  /**< DMA_LPSR_DONE4 output assigned to XBARA1_IN124 input. */
722     kXBARA1_InputDmaLpsrDone5       = 125|0x100U,  /**< DMA_LPSR_DONE5 output assigned to XBARA1_IN125 input. */
723     kXBARA1_InputDmaLpsrDone6       = 126|0x100U,  /**< DMA_LPSR_DONE6 output assigned to XBARA1_IN126 input. */
724     kXBARA1_InputDmaLpsrDone7       = 127|0x100U,  /**< DMA_LPSR_DONE7 output assigned to XBARA1_IN127 input. */
725     kXBARA1_InputAoi1Out0           = 128|0x100U,  /**< AOI1_OUT0 output assigned to XBARA1_IN128 input. */
726     kXBARA1_InputAoi1Out1           = 129|0x100U,  /**< AOI1_OUT1 output assigned to XBARA1_IN129 input. */
727     kXBARA1_InputAoi1Out2           = 130|0x100U,  /**< AOI1_OUT2 output assigned to XBARA1_IN130 input. */
728     kXBARA1_InputAoi1Out3           = 131|0x100U,  /**< AOI1_OUT3 output assigned to XBARA1_IN131 input. */
729     kXBARA1_InputAoi2Out0           = 132|0x100U,  /**< AOI2_OUT0 output assigned to XBARA1_IN132 input. */
730     kXBARA1_InputAoi2Out1           = 133|0x100U,  /**< AOI2_OUT1 output assigned to XBARA1_IN133 input. */
731     kXBARA1_InputAoi2Out2           = 134|0x100U,  /**< AOI2_OUT2 output assigned to XBARA1_IN134 input. */
732     kXBARA1_InputAoi2Out3           = 135|0x100U,  /**< AOI2_OUT3 output assigned to XBARA1_IN135 input. */
733     kXBARA1_InputAdcEtc0Coco0       = 136|0x100U,  /**< ADC_ETC0_COCO0 output assigned to XBARA1_IN136 input. */
734     kXBARA1_InputAdcEtc0Coco1       = 137|0x100U,  /**< ADC_ETC0_COCO1 output assigned to XBARA1_IN137 input. */
735     kXBARA1_InputAdcEtc0Coco2       = 138|0x100U,  /**< ADC_ETC0_COCO2 output assigned to XBARA1_IN138 input. */
736     kXBARA1_InputAdcEtc0Coco3       = 139|0x100U,  /**< ADC_ETC0_COCO3 output assigned to XBARA1_IN139 input. */
737     kXBARA1_InputAdcEtc1Coco0       = 140|0x100U,  /**< ADC_ETC1_COCO0 output assigned to XBARA1_IN140 input. */
738     kXBARA1_InputAdcEtc1Coco1       = 141|0x100U,  /**< ADC_ETC1_COCO1 output assigned to XBARA1_IN141 input. */
739     kXBARA1_InputAdcEtc1Coco2       = 142|0x100U,  /**< ADC_ETC1_COCO2 output assigned to XBARA1_IN142 input. */
740     kXBARA1_InputAdcEtc1Coco3       = 143|0x100U,  /**< ADC_ETC1_COCO3 output assigned to XBARA1_IN143 input. */
741     kXBARB2_InputLogicLow           = 0|0x200U,    /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */
742     kXBARB2_InputLogicHigh          = 1|0x200U,    /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */
743     kXBARB2_InputAcmp1Out           = 2|0x200U,    /**< ACMP1_OUT output assigned to XBARB2_IN2 input. */
744     kXBARB2_InputAcmp2Out           = 3|0x200U,    /**< ACMP2_OUT output assigned to XBARB2_IN3 input. */
745     kXBARB2_InputAcmp3Out           = 4|0x200U,    /**< ACMP3_OUT output assigned to XBARB2_IN4 input. */
746     kXBARB2_InputAcmp4Out           = 5|0x200U,    /**< ACMP4_OUT output assigned to XBARB2_IN5 input. */
747     kXBARB2_InputRESERVED6          = 6|0x200U,    /**< XBARB2_IN6 input is reserved. */
748     kXBARB2_InputRESERVED7          = 7|0x200U,    /**< XBARB2_IN7 input is reserved. */
749     kXBARB2_InputRESERVED8          = 8|0x200U,    /**< XBARB2_IN8 input is reserved. */
750     kXBARB2_InputRESERVED9          = 9|0x200U,    /**< XBARB2_IN9 input is reserved. */
751     kXBARB2_InputQtimer1Timer0      = 10|0x200U,   /**< QTIMER1_TIMER0 output assigned to XBARB2_IN10 input. */
752     kXBARB2_InputQtimer1Timer1      = 11|0x200U,   /**< QTIMER1_TIMER1 output assigned to XBARB2_IN11 input. */
753     kXBARB2_InputQtimer1Timer2      = 12|0x200U,   /**< QTIMER1_TIMER2 output assigned to XBARB2_IN12 input. */
754     kXBARB2_InputQtimer1Timer3      = 13|0x200U,   /**< QTIMER1_TIMER3 output assigned to XBARB2_IN13 input. */
755     kXBARB2_InputQtimer2Timer0      = 14|0x200U,   /**< QTIMER2_TIMER0 output assigned to XBARB2_IN14 input. */
756     kXBARB2_InputQtimer2Timer1      = 15|0x200U,   /**< QTIMER2_TIMER1 output assigned to XBARB2_IN15 input. */
757     kXBARB2_InputQtimer2Timer2      = 16|0x200U,   /**< QTIMER2_TIMER2 output assigned to XBARB2_IN16 input. */
758     kXBARB2_InputQtimer2Timer3      = 17|0x200U,   /**< QTIMER2_TIMER3 output assigned to XBARB2_IN17 input. */
759     kXBARB2_InputQtimer3Timer0      = 18|0x200U,   /**< QTIMER3_TIMER0 output assigned to XBARB2_IN18 input. */
760     kXBARB2_InputQtimer3Timer1      = 19|0x200U,   /**< QTIMER3_TIMER1 output assigned to XBARB2_IN19 input. */
761     kXBARB2_InputQtimer3Timer2      = 20|0x200U,   /**< QTIMER3_TIMER2 output assigned to XBARB2_IN20 input. */
762     kXBARB2_InputQtimer3Timer3      = 21|0x200U,   /**< QTIMER3_TIMER3 output assigned to XBARB2_IN21 input. */
763     kXBARB2_InputQtimer4Timer0      = 22|0x200U,   /**< QTIMER4_TIMER0 output assigned to XBARB2_IN22 input. */
764     kXBARB2_InputQtimer4Timer1      = 23|0x200U,   /**< QTIMER4_TIMER1 output assigned to XBARB2_IN23 input. */
765     kXBARB2_InputQtimer4Timer2      = 24|0x200U,   /**< QTIMER4_TIMER2 output assigned to XBARB2_IN24 input. */
766     kXBARB2_InputQtimer4Timer3      = 25|0x200U,   /**< QTIMER4_TIMER3 output assigned to XBARB2_IN25 input. */
767     kXBARB2_InputRESERVED26         = 26|0x200U,   /**< XBARB2_IN26 input is reserved. */
768     kXBARB2_InputRESERVED27         = 27|0x200U,   /**< XBARB2_IN27 input is reserved. */
769     kXBARB2_InputRESERVED28         = 28|0x200U,   /**< XBARB2_IN28 input is reserved. */
770     kXBARB2_InputRESERVED29         = 29|0x200U,   /**< XBARB2_IN29 input is reserved. */
771     kXBARB2_InputRESERVED30         = 30|0x200U,   /**< XBARB2_IN30 input is reserved. */
772     kXBARB2_InputRESERVED31         = 31|0x200U,   /**< XBARB2_IN31 input is reserved. */
773     kXBARB2_InputRESERVED32         = 32|0x200U,   /**< XBARB2_IN32 input is reserved. */
774     kXBARB2_InputRESERVED33         = 33|0x200U,   /**< XBARB2_IN33 input is reserved. */
775     kXBARB2_InputFlexpwm1Pwm0OutTrig01 = 34|0x200U, /**< FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
776     kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 35|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
777     kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 36|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN36 input. */
778     kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 37|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN37 input. */
779     kXBARB2_InputFlexpwm2Pwm0OutTrig01 = 38|0x200U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN38 input. */
780     kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 39|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN39 input. */
781     kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 40|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN40 input. */
782     kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 41|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN41 input. */
783     kXBARB2_InputFlexpwm3Pwm0OutTrig01 = 42|0x200U, /**< FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN42 input. */
784     kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 43|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN43 input. */
785     kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 44|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN44 input. */
786     kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 45|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN45 input. */
787     kXBARB2_InputFlexpwm4Pwm0OutTrig01 = 46|0x200U, /**< FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN46 input. */
788     kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 47|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN47 input. */
789     kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 48|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN48 input. */
790     kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 49|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN49 input. */
791     kXBARB2_InputRESERVED50         = 50|0x200U,   /**< XBARB2_IN50 input is reserved. */
792     kXBARB2_InputRESERVED51         = 51|0x200U,   /**< XBARB2_IN51 input is reserved. */
793     kXBARB2_InputRESERVED52         = 52|0x200U,   /**< XBARB2_IN52 input is reserved. */
794     kXBARB2_InputRESERVED53         = 53|0x200U,   /**< XBARB2_IN53 input is reserved. */
795     kXBARB2_InputRESERVED54         = 54|0x200U,   /**< XBARB2_IN54 input is reserved. */
796     kXBARB2_InputRESERVED55         = 55|0x200U,   /**< XBARB2_IN55 input is reserved. */
797     kXBARB2_InputRESERVED56         = 56|0x200U,   /**< XBARB2_IN56 input is reserved. */
798     kXBARB2_InputRESERVED57         = 57|0x200U,   /**< XBARB2_IN57 input is reserved. */
799     kXBARB2_InputPit1Trigger0       = 58|0x200U,   /**< PIT1_TRIGGER0 output assigned to XBARB2_IN58 input. */
800     kXBARB2_InputPit1Trigger1       = 59|0x200U,   /**< PIT1_TRIGGER1 output assigned to XBARB2_IN59 input. */
801     kXBARB2_InputAdcEtc0Coco0       = 60|0x200U,   /**< ADC_ETC0_COCO0 output assigned to XBARB2_IN60 input. */
802     kXBARB2_InputAdcEtc0Coco1       = 61|0x200U,   /**< ADC_ETC0_COCO1 output assigned to XBARB2_IN61 input. */
803     kXBARB2_InputAdcEtc0Coco2       = 62|0x200U,   /**< ADC_ETC0_COCO2 output assigned to XBARB2_IN62 input. */
804     kXBARB2_InputAdcEtc0Coco3       = 63|0x200U,   /**< ADC_ETC0_COCO3 output assigned to XBARB2_IN63 input. */
805     kXBARB2_InputAdcEtc1Coco0       = 64|0x200U,   /**< ADC_ETC1_COCO0 output assigned to XBARB2_IN64 input. */
806     kXBARB2_InputAdcEtc1Coco1       = 65|0x200U,   /**< ADC_ETC1_COCO1 output assigned to XBARB2_IN65 input. */
807     kXBARB2_InputAdcEtc1Coco2       = 66|0x200U,   /**< ADC_ETC1_COCO2 output assigned to XBARB2_IN66 input. */
808     kXBARB2_InputAdcEtc1Coco3       = 67|0x200U,   /**< ADC_ETC1_COCO3 output assigned to XBARB2_IN67 input. */
809     kXBARB2_InputRESERVED68         = 68|0x200U,   /**< XBARB2_IN68 input is reserved. */
810     kXBARB2_InputRESERVED69         = 69|0x200U,   /**< XBARB2_IN69 input is reserved. */
811     kXBARB2_InputRESERVED70         = 70|0x200U,   /**< XBARB2_IN70 input is reserved. */
812     kXBARB2_InputRESERVED71         = 71|0x200U,   /**< XBARB2_IN71 input is reserved. */
813     kXBARB2_InputRESERVED72         = 72|0x200U,   /**< XBARB2_IN72 input is reserved. */
814     kXBARB2_InputRESERVED73         = 73|0x200U,   /**< XBARB2_IN73 input is reserved. */
815     kXBARB2_InputRESERVED74         = 74|0x200U,   /**< XBARB2_IN74 input is reserved. */
816     kXBARB2_InputRESERVED75         = 75|0x200U,   /**< XBARB2_IN75 input is reserved. */
817     kXBARB2_InputDec1PosMatch       = 76|0x200U,   /**< DEC1_POS_MATCH output assigned to XBARB2_IN76 input. */
818     kXBARB2_InputDec2PosMatch       = 77|0x200U,   /**< DEC2_POS_MATCH output assigned to XBARB2_IN77 input. */
819     kXBARB2_InputDec3PosMatch       = 78|0x200U,   /**< DEC3_POS_MATCH output assigned to XBARB2_IN78 input. */
820     kXBARB2_InputDec4PosMatch       = 79|0x200U,   /**< DEC4_POS_MATCH output assigned to XBARB2_IN79 input. */
821     kXBARB2_InputRESERVED80         = 80|0x200U,   /**< XBARB2_IN80 input is reserved. */
822     kXBARB2_InputRESERVED81         = 81|0x200U,   /**< XBARB2_IN81 input is reserved. */
823     kXBARB2_InputDmaDone0           = 82|0x200U,   /**< DMA_DONE0 output assigned to XBARB2_IN82 input. */
824     kXBARB2_InputDmaDone1           = 83|0x200U,   /**< DMA_DONE1 output assigned to XBARB2_IN83 input. */
825     kXBARB2_InputDmaDone2           = 84|0x200U,   /**< DMA_DONE2 output assigned to XBARB2_IN84 input. */
826     kXBARB2_InputDmaDone3           = 85|0x200U,   /**< DMA_DONE3 output assigned to XBARB2_IN85 input. */
827     kXBARB2_InputDmaDone4           = 86|0x200U,   /**< DMA_DONE4 output assigned to XBARB2_IN86 input. */
828     kXBARB2_InputDmaDone5           = 87|0x200U,   /**< DMA_DONE5 output assigned to XBARB2_IN87 input. */
829     kXBARB2_InputDmaDone6           = 88|0x200U,   /**< DMA_DONE6 output assigned to XBARB2_IN88 input. */
830     kXBARB2_InputDmaDone7           = 89|0x200U,   /**< DMA_DONE7 output assigned to XBARB2_IN89 input. */
831     kXBARB2_InputDmaLpsrDone0       = 90|0x200U,   /**< DMA_LPSR_DONE0 output assigned to XBARB2_IN90 input. */
832     kXBARB2_InputDmaLpsrDone1       = 91|0x200U,   /**< DMA_LPSR_DONE1 output assigned to XBARB2_IN91 input. */
833     kXBARB2_InputDmaLpsrDone2       = 92|0x200U,   /**< DMA_LPSR_DONE2 output assigned to XBARB2_IN92 input. */
834     kXBARB2_InputDmaLpsrDone3       = 93|0x200U,   /**< DMA_LPSR_DONE3 output assigned to XBARB2_IN93 input. */
835     kXBARB2_InputDmaLpsrDone4       = 94|0x200U,   /**< DMA_LPSR_DONE4 output assigned to XBARB2_IN94 input. */
836     kXBARB2_InputDmaLpsrDone5       = 95|0x200U,   /**< DMA_LPSR_DONE5 output assigned to XBARB2_IN95 input. */
837     kXBARB2_InputDmaLpsrDone6       = 96|0x200U,   /**< DMA_LPSR_DONE6 output assigned to XBARB2_IN96 input. */
838     kXBARB2_InputDmaLpsrDone7       = 97|0x200U,   /**< DMA_LPSR_DONE7 output assigned to XBARB2_IN97 input. */
839     kXBARB3_InputLogicLow           = 0|0x300U,    /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */
840     kXBARB3_InputLogicHigh          = 1|0x300U,    /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */
841     kXBARB3_InputAcmp1Out           = 2|0x300U,    /**< ACMP1_OUT output assigned to XBARB3_IN2 input. */
842     kXBARB3_InputAcmp2Out           = 3|0x300U,    /**< ACMP2_OUT output assigned to XBARB3_IN3 input. */
843     kXBARB3_InputAcmp3Out           = 4|0x300U,    /**< ACMP3_OUT output assigned to XBARB3_IN4 input. */
844     kXBARB3_InputAcmp4Out           = 5|0x300U,    /**< ACMP4_OUT output assigned to XBARB3_IN5 input. */
845     kXBARB3_InputRESERVED6          = 6|0x300U,    /**< XBARB3_IN6 input is reserved. */
846     kXBARB3_InputRESERVED7          = 7|0x300U,    /**< XBARB3_IN7 input is reserved. */
847     kXBARB3_InputRESERVED8          = 8|0x300U,    /**< XBARB3_IN8 input is reserved. */
848     kXBARB3_InputRESERVED9          = 9|0x300U,    /**< XBARB3_IN9 input is reserved. */
849     kXBARB3_InputQtimer1Timer0      = 10|0x300U,   /**< QTIMER1_TIMER0 output assigned to XBARB3_IN10 input. */
850     kXBARB3_InputQtimer1Timer1      = 11|0x300U,   /**< QTIMER1_TIMER1 output assigned to XBARB3_IN11 input. */
851     kXBARB3_InputQtimer1Timer2      = 12|0x300U,   /**< QTIMER1_TIMER2 output assigned to XBARB3_IN12 input. */
852     kXBARB3_InputQtimer1Timer3      = 13|0x300U,   /**< QTIMER1_TIMER3 output assigned to XBARB3_IN13 input. */
853     kXBARB3_InputQtimer2Timer0      = 14|0x300U,   /**< QTIMER2_TIMER0 output assigned to XBARB3_IN14 input. */
854     kXBARB3_InputQtimer2Timer1      = 15|0x300U,   /**< QTIMER2_TIMER1 output assigned to XBARB3_IN15 input. */
855     kXBARB3_InputQtimer2Timer2      = 16|0x300U,   /**< QTIMER2_TIMER2 output assigned to XBARB3_IN16 input. */
856     kXBARB3_InputQtimer2Timer3      = 17|0x300U,   /**< QTIMER2_TIMER3 output assigned to XBARB3_IN17 input. */
857     kXBARB3_InputQtimer3Timer0      = 18|0x300U,   /**< QTIMER3_TIMER0 output assigned to XBARB3_IN18 input. */
858     kXBARB3_InputQtimer3Timer1      = 19|0x300U,   /**< QTIMER3_TIMER1 output assigned to XBARB3_IN19 input. */
859     kXBARB3_InputQtimer3Timer2      = 20|0x300U,   /**< QTIMER3_TIMER2 output assigned to XBARB3_IN20 input. */
860     kXBARB3_InputQtimer3Timer3      = 21|0x300U,   /**< QTIMER3_TIMER3 output assigned to XBARB3_IN21 input. */
861     kXBARB3_InputQtimer4Timer0      = 22|0x300U,   /**< QTIMER4_TIMER0 output assigned to XBARB3_IN22 input. */
862     kXBARB3_InputQtimer4Timer1      = 23|0x300U,   /**< QTIMER4_TIMER1 output assigned to XBARB3_IN23 input. */
863     kXBARB3_InputQtimer4Timer2      = 24|0x300U,   /**< QTIMER4_TIMER2 output assigned to XBARB3_IN24 input. */
864     kXBARB3_InputQtimer4Timer3      = 25|0x300U,   /**< QTIMER4_TIMER3 output assigned to XBARB3_IN25 input. */
865     kXBARB3_InputRESERVED26         = 26|0x300U,   /**< XBARB3_IN26 input is reserved. */
866     kXBARB3_InputRESERVED27         = 27|0x300U,   /**< XBARB3_IN27 input is reserved. */
867     kXBARB3_InputRESERVED28         = 28|0x300U,   /**< XBARB3_IN28 input is reserved. */
868     kXBARB3_InputRESERVED29         = 29|0x300U,   /**< XBARB3_IN29 input is reserved. */
869     kXBARB3_InputRESERVED30         = 30|0x300U,   /**< XBARB3_IN30 input is reserved. */
870     kXBARB3_InputRESERVED31         = 31|0x300U,   /**< XBARB3_IN31 input is reserved. */
871     kXBARB3_InputRESERVED32         = 32|0x300U,   /**< XBARB3_IN32 input is reserved. */
872     kXBARB3_InputRESERVED33         = 33|0x300U,   /**< XBARB3_IN33 input is reserved. */
873     kXBARB3_InputFlexpwm1Pwm0OutTrig01 = 34|0x300U, /**< FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
874     kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 35|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
875     kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 36|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN36 input. */
876     kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 37|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN37 input. */
877     kXBARB3_InputFlexpwm2Pwm0OutTrig01 = 38|0x300U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN38 input. */
878     kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 39|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN39 input. */
879     kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 40|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN40 input. */
880     kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 41|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN41 input. */
881     kXBARB3_InputFlexpwm3Pwm0OutTrig01 = 42|0x300U, /**< FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN42 input. */
882     kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 43|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN43 input. */
883     kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 44|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN44 input. */
884     kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 45|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN45 input. */
885     kXBARB3_InputFlexpwm4Pwm0OutTrig01 = 46|0x300U, /**< FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN46 input. */
886     kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 47|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN47 input. */
887     kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 48|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN48 input. */
888     kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 49|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN49 input. */
889     kXBARB3_InputRESERVED50         = 50|0x300U,   /**< XBARB3_IN50 input is reserved. */
890     kXBARB3_InputRESERVED51         = 51|0x300U,   /**< XBARB3_IN51 input is reserved. */
891     kXBARB3_InputRESERVED52         = 52|0x300U,   /**< XBARB3_IN52 input is reserved. */
892     kXBARB3_InputRESERVED53         = 53|0x300U,   /**< XBARB3_IN53 input is reserved. */
893     kXBARB3_InputRESERVED54         = 54|0x300U,   /**< XBARB3_IN54 input is reserved. */
894     kXBARB3_InputRESERVED55         = 55|0x300U,   /**< XBARB3_IN55 input is reserved. */
895     kXBARB3_InputRESERVED56         = 56|0x300U,   /**< XBARB3_IN56 input is reserved. */
896     kXBARB3_InputRESERVED57         = 57|0x300U,   /**< XBARB3_IN57 input is reserved. */
897     kXBARB3_InputPit1Trigger0       = 58|0x300U,   /**< PIT1_TRIGGER0 output assigned to XBARB3_IN58 input. */
898     kXBARB3_InputPit1Trigger1       = 59|0x300U,   /**< PIT1_TRIGGER1 output assigned to XBARB3_IN59 input. */
899     kXBARB3_InputAdcEtc0Coco0       = 60|0x300U,   /**< ADC_ETC0_COCO0 output assigned to XBARB3_IN60 input. */
900     kXBARB3_InputAdcEtc0Coco1       = 61|0x300U,   /**< ADC_ETC0_COCO1 output assigned to XBARB3_IN61 input. */
901     kXBARB3_InputAdcEtc0Coco2       = 62|0x300U,   /**< ADC_ETC0_COCO2 output assigned to XBARB3_IN62 input. */
902     kXBARB3_InputAdcEtc0Coco3       = 63|0x300U,   /**< ADC_ETC0_COCO3 output assigned to XBARB3_IN63 input. */
903     kXBARB3_InputAdcEtc1Coco0       = 64|0x300U,   /**< ADC_ETC1_COCO0 output assigned to XBARB3_IN64 input. */
904     kXBARB3_InputAdcEtc1Coco1       = 65|0x300U,   /**< ADC_ETC1_COCO1 output assigned to XBARB3_IN65 input. */
905     kXBARB3_InputAdcEtc1Coco2       = 66|0x300U,   /**< ADC_ETC1_COCO2 output assigned to XBARB3_IN66 input. */
906     kXBARB3_InputAdcEtc1Coco3       = 67|0x300U,   /**< ADC_ETC1_COCO3 output assigned to XBARB3_IN67 input. */
907     kXBARB3_InputRESERVED68         = 68|0x300U,   /**< XBARB3_IN68 input is reserved. */
908     kXBARB3_InputRESERVED69         = 69|0x300U,   /**< XBARB3_IN69 input is reserved. */
909     kXBARB3_InputRESERVED70         = 70|0x300U,   /**< XBARB3_IN70 input is reserved. */
910     kXBARB3_InputRESERVED71         = 71|0x300U,   /**< XBARB3_IN71 input is reserved. */
911     kXBARB3_InputRESERVED72         = 72|0x300U,   /**< XBARB3_IN72 input is reserved. */
912     kXBARB3_InputRESERVED73         = 73|0x300U,   /**< XBARB3_IN73 input is reserved. */
913     kXBARB3_InputRESERVED74         = 74|0x300U,   /**< XBARB3_IN74 input is reserved. */
914     kXBARB3_InputRESERVED75         = 75|0x300U,   /**< XBARB3_IN75 input is reserved. */
915     kXBARB3_InputDec1PosMatch       = 76|0x300U,   /**< DEC1_POS_MATCH output assigned to XBARB3_IN76 input. */
916     kXBARB3_InputDec2PosMatch       = 77|0x300U,   /**< DEC2_POS_MATCH output assigned to XBARB3_IN77 input. */
917     kXBARB3_InputDec3PosMatch       = 78|0x300U,   /**< DEC3_POS_MATCH output assigned to XBARB3_IN78 input. */
918     kXBARB3_InputDec4PosMatch       = 79|0x300U,   /**< DEC4_POS_MATCH output assigned to XBARB3_IN79 input. */
919     kXBARB3_InputRESERVED80         = 80|0x300U,   /**< XBARB3_IN80 input is reserved. */
920     kXBARB3_InputRESERVED81         = 81|0x300U,   /**< XBARB3_IN81 input is reserved. */
921     kXBARB3_InputDmaDone0           = 82|0x300U,   /**< DMA_DONE0 output assigned to XBARB3_IN82 input. */
922     kXBARB3_InputDmaDone1           = 83|0x300U,   /**< DMA_DONE1 output assigned to XBARB3_IN83 input. */
923     kXBARB3_InputDmaDone2           = 84|0x300U,   /**< DMA_DONE2 output assigned to XBARB3_IN84 input. */
924     kXBARB3_InputDmaDone3           = 85|0x300U,   /**< DMA_DONE3 output assigned to XBARB3_IN85 input. */
925     kXBARB3_InputDmaDone4           = 86|0x300U,   /**< DMA_DONE4 output assigned to XBARB3_IN86 input. */
926     kXBARB3_InputDmaDone5           = 87|0x300U,   /**< DMA_DONE5 output assigned to XBARB3_IN87 input. */
927     kXBARB3_InputDmaDone6           = 88|0x300U,   /**< DMA_DONE6 output assigned to XBARB3_IN88 input. */
928     kXBARB3_InputDmaDone7           = 89|0x300U,   /**< DMA_DONE7 output assigned to XBARB3_IN89 input. */
929     kXBARB3_InputDmaLpsrDone0       = 90|0x300U,   /**< DMA_LPSR_DONE0 output assigned to XBARB3_IN90 input. */
930     kXBARB3_InputDmaLpsrDone1       = 91|0x300U,   /**< DMA_LPSR_DONE1 output assigned to XBARB3_IN91 input. */
931     kXBARB3_InputDmaLpsrDone2       = 92|0x300U,   /**< DMA_LPSR_DONE2 output assigned to XBARB3_IN92 input. */
932     kXBARB3_InputDmaLpsrDone3       = 93|0x300U,   /**< DMA_LPSR_DONE3 output assigned to XBARB3_IN93 input. */
933     kXBARB3_InputDmaLpsrDone4       = 94|0x300U,   /**< DMA_LPSR_DONE4 output assigned to XBARB3_IN94 input. */
934     kXBARB3_InputDmaLpsrDone5       = 95|0x300U,   /**< DMA_LPSR_DONE5 output assigned to XBARB3_IN95 input. */
935     kXBARB3_InputDmaLpsrDone6       = 96|0x300U,   /**< DMA_LPSR_DONE6 output assigned to XBARB3_IN96 input. */
936     kXBARB3_InputDmaLpsrDone7       = 97|0x300U,   /**< DMA_LPSR_DONE7 output assigned to XBARB3_IN97 input. */
937 } xbar_input_signal_t;
938 
939 typedef enum _xbar_output_signal
940 {
941     kXBARA1_OutputDmaChMuxReq81     = 0|0x100U,    /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ81 */
942     kXBARA1_OutputDmaChMuxReq82     = 1|0x100U,    /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ82 */
943     kXBARA1_OutputDmaChMuxReq83     = 2|0x100U,    /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ83 */
944     kXBARA1_OutputDmaChMuxReq84     = 3|0x100U,    /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ84 */
945     kXBARA1_OutputIomuxXbarInout04  = 4|0x100U,    /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
946     kXBARA1_OutputIomuxXbarInout05  = 5|0x100U,    /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
947     kXBARA1_OutputIomuxXbarInout06  = 6|0x100U,    /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
948     kXBARA1_OutputIomuxXbarInout07  = 7|0x100U,    /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
949     kXBARA1_OutputIomuxXbarInout08  = 8|0x100U,    /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
950     kXBARA1_OutputIomuxXbarInout09  = 9|0x100U,    /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
951     kXBARA1_OutputIomuxXbarInout10  = 10|0x100U,   /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
952     kXBARA1_OutputIomuxXbarInout11  = 11|0x100U,   /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
953     kXBARA1_OutputIomuxXbarInout12  = 12|0x100U,   /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
954     kXBARA1_OutputIomuxXbarInout13  = 13|0x100U,   /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
955     kXBARA1_OutputIomuxXbarInout14  = 14|0x100U,   /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
956     kXBARA1_OutputIomuxXbarInout15  = 15|0x100U,   /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
957     kXBARA1_OutputIomuxXbarInout16  = 16|0x100U,   /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
958     kXBARA1_OutputIomuxXbarInout17  = 17|0x100U,   /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
959     kXBARA1_OutputIomuxXbarInout18  = 18|0x100U,   /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
960     kXBARA1_OutputIomuxXbarInout19  = 19|0x100U,   /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
961     kXBARA1_OutputIomuxXbarInout20  = 20|0x100U,   /**< XBARA1_OUT20 output assigned to IOMUX_XBAR_INOUT20 */
962     kXBARA1_OutputIomuxXbarInout21  = 21|0x100U,   /**< XBARA1_OUT21 output assigned to IOMUX_XBAR_INOUT21 */
963     kXBARA1_OutputIomuxXbarInout22  = 22|0x100U,   /**< XBARA1_OUT22 output assigned to IOMUX_XBAR_INOUT22 */
964     kXBARA1_OutputIomuxXbarInout23  = 23|0x100U,   /**< XBARA1_OUT23 output assigned to IOMUX_XBAR_INOUT23 */
965     kXBARA1_OutputIomuxXbarInout24  = 24|0x100U,   /**< XBARA1_OUT24 output assigned to IOMUX_XBAR_INOUT24 */
966     kXBARA1_OutputIomuxXbarInout25  = 25|0x100U,   /**< XBARA1_OUT25 output assigned to IOMUX_XBAR_INOUT25 */
967     kXBARA1_OutputIomuxXbarInout26  = 26|0x100U,   /**< XBARA1_OUT26 output assigned to IOMUX_XBAR_INOUT26 */
968     kXBARA1_OutputIomuxXbarInout27  = 27|0x100U,   /**< XBARA1_OUT27 output assigned to IOMUX_XBAR_INOUT27 */
969     kXBARA1_OutputIomuxXbarInout28  = 28|0x100U,   /**< XBARA1_OUT28 output assigned to IOMUX_XBAR_INOUT28 */
970     kXBARA1_OutputIomuxXbarInout29  = 29|0x100U,   /**< XBARA1_OUT29 output assigned to IOMUX_XBAR_INOUT29 */
971     kXBARA1_OutputIomuxXbarInout30  = 30|0x100U,   /**< XBARA1_OUT30 output assigned to IOMUX_XBAR_INOUT30 */
972     kXBARA1_OutputIomuxXbarInout31  = 31|0x100U,   /**< XBARA1_OUT31 output assigned to IOMUX_XBAR_INOUT31 */
973     kXBARA1_OutputIomuxXbarInout32  = 32|0x100U,   /**< XBARA1_OUT32 output assigned to IOMUX_XBAR_INOUT32 */
974     kXBARA1_OutputIomuxXbarInout33  = 33|0x100U,   /**< XBARA1_OUT33 output assigned to IOMUX_XBAR_INOUT33 */
975     kXBARA1_OutputIomuxXbarInout34  = 34|0x100U,   /**< XBARA1_OUT34 output assigned to IOMUX_XBAR_INOUT34 */
976     kXBARA1_OutputIomuxXbarInout35  = 35|0x100U,   /**< XBARA1_OUT35 output assigned to IOMUX_XBAR_INOUT35 */
977     kXBARA1_OutputIomuxXbarInout36  = 36|0x100U,   /**< XBARA1_OUT36 output assigned to IOMUX_XBAR_INOUT36 */
978     kXBARA1_OutputIomuxXbarInout37  = 37|0x100U,   /**< XBARA1_OUT37 output assigned to IOMUX_XBAR_INOUT37 */
979     kXBARA1_OutputIomuxXbarInout38  = 38|0x100U,   /**< XBARA1_OUT38 output assigned to IOMUX_XBAR_INOUT38 */
980     kXBARA1_OutputIomuxXbarInout39  = 39|0x100U,   /**< XBARA1_OUT39 output assigned to IOMUX_XBAR_INOUT39 */
981     kXBARA1_OutputIomuxXbarInout40  = 40|0x100U,   /**< XBARA1_OUT40 output assigned to IOMUX_XBAR_INOUT40 */
982     kXBARA1_OutputAcmp1Sample       = 41|0x100U,   /**< XBARA1_OUT41 output assigned to ACMP1_SAMPLE */
983     kXBARA1_OutputAcmp2Sample       = 42|0x100U,   /**< XBARA1_OUT42 output assigned to ACMP2_SAMPLE */
984     kXBARA1_OutputAcmp3Sample       = 43|0x100U,   /**< XBARA1_OUT43 output assigned to ACMP3_SAMPLE */
985     kXBARA1_OutputAcmp4Sample       = 44|0x100U,   /**< XBARA1_OUT44 output assigned to ACMP4_SAMPLE */
986     kXBARA1_OutputRESERVED45        = 45|0x100U,   /**< XBARA1_OUT45 output is reserved. */
987     kXBARA1_OutputRESERVED46        = 46|0x100U,   /**< XBARA1_OUT46 output is reserved. */
988     kXBARA1_OutputRESERVED47        = 47|0x100U,   /**< XBARA1_OUT47 output is reserved. */
989     kXBARA1_OutputRESERVED48        = 48|0x100U,   /**< XBARA1_OUT48 output is reserved. */
990     kXBARA1_OutputFlexpwm1Pwm0Exta  = 49|0x100U,   /**< XBARA1_OUT49 output assigned to FLEXPWM1_PWM0_EXTA */
991     kXBARA1_OutputFlexpwm1Pwm1Exta  = 50|0x100U,   /**< XBARA1_OUT50 output assigned to FLEXPWM1_PWM1_EXTA */
992     kXBARA1_OutputFlexpwm1Pwm2Exta  = 51|0x100U,   /**< XBARA1_OUT51 output assigned to FLEXPWM1_PWM2_EXTA */
993     kXBARA1_OutputFlexpwm1Pwm3Exta  = 52|0x100U,   /**< XBARA1_OUT52 output assigned to FLEXPWM1_PWM3_EXTA */
994     kXBARA1_OutputFlexpwm1Pwm0ExtSync = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM1_PWM0_EXT_SYNC */
995     kXBARA1_OutputFlexpwm1Pwm1ExtSync = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM1_PWM1_EXT_SYNC */
996     kXBARA1_OutputFlexpwm1Pwm2ExtSync = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM1_PWM2_EXT_SYNC */
997     kXBARA1_OutputFlexpwm1Pwm3ExtSync = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM1_PWM3_EXT_SYNC */
998     kXBARA1_OutputFlexpwm1ExtClk    = 57|0x100U,   /**< XBARA1_OUT57 output assigned to FLEXPWM1_EXT_CLK */
999     kXBARA1_OutputFlexpwm1Fault0    = 58|0x100U,   /**< XBARA1_OUT58 output assigned to FLEXPWM1_FAULT0 */
1000     kXBARA1_OutputFlexpwm1Fault1    = 59|0x100U,   /**< XBARA1_OUT59 output assigned to FLEXPWM1_FAULT1 */
1001     kXBARA1_OutputFlexpwm1234Fault2 = 60|0x100U,   /**< XBARA1_OUT60 output assigned to FLEXPWM1_2_3_4_FAULT2 */
1002     kXBARA1_OutputFlexpwm1234Fault3 = 61|0x100U,   /**< XBARA1_OUT61 output assigned to FLEXPWM1_2_3_4_FAULT3 */
1003     kXBARA1_OutputFlexpwm1ExtForce  = 62|0x100U,   /**< XBARA1_OUT62 output assigned to FLEXPWM1_EXT_FORCE */
1004     kXBARA1_OutputFlexpwm2Pwm0Exta  = 63|0x100U,   /**< XBARA1_OUT63 output assigned to FLEXPWM2_PWM0_EXTA */
1005     kXBARA1_OutputFlexpwm2Pwm1Exta  = 64|0x100U,   /**< XBARA1_OUT64 output assigned to FLEXPWM2_PWM1_EXTA */
1006     kXBARA1_OutputFlexpwm2Pwm2Exta  = 65|0x100U,   /**< XBARA1_OUT65 output assigned to FLEXPWM2_PWM2_EXTA */
1007     kXBARA1_OutputFlexpwm2Pwm3Exta  = 66|0x100U,   /**< XBARA1_OUT66 output assigned to FLEXPWM2_PWM3_EXTA */
1008     kXBARA1_OutputFlexpwm2Pwm0ExtSync = 67|0x100U, /**< XBARA1_OUT67 output assigned to FLEXPWM2_PWM0_EXT_SYNC */
1009     kXBARA1_OutputFlexpwm2Pwm1ExtSync = 68|0x100U, /**< XBARA1_OUT68 output assigned to FLEXPWM2_PWM1_EXT_SYNC */
1010     kXBARA1_OutputFlexpwm2Pwm2ExtSync = 69|0x100U, /**< XBARA1_OUT69 output assigned to FLEXPWM2_PWM2_EXT_SYNC */
1011     kXBARA1_OutputFlexpwm2Pwm3ExtSync = 70|0x100U, /**< XBARA1_OUT70 output assigned to FLEXPWM2_PWM3_EXT_SYNC */
1012     kXBARA1_OutputFlexpwm2ExtClk    = 71|0x100U,   /**< XBARA1_OUT71 output assigned to FLEXPWM2_EXT_CLK */
1013     kXBARA1_OutputFlexpwm2Fault0    = 72|0x100U,   /**< XBARA1_OUT72 output assigned to FLEXPWM2_FAULT0 */
1014     kXBARA1_OutputFlexpwm2Fault1    = 73|0x100U,   /**< XBARA1_OUT73 output assigned to FLEXPWM2_FAULT1 */
1015     kXBARA1_OutputFlexpwm2ExtForce  = 74|0x100U,   /**< XBARA1_OUT74 output assigned to FLEXPWM2_EXT_FORCE */
1016     kXBARA1_OutputFlexpwm34Pwm0Exta = 75|0x100U,   /**< XBARA1_OUT75 output assigned to FLEXPWM3_4_PWM0_EXTA */
1017     kXBARA1_OutputFlexpwm34Pwm1Exta = 76|0x100U,   /**< XBARA1_OUT76 output assigned to FLEXPWM3_4_PWM1_EXTA */
1018     kXBARA1_OutputFlexpwm34Pwm2Exta = 77|0x100U,   /**< XBARA1_OUT77 output assigned to FLEXPWM3_4_PWM2_EXTA */
1019     kXBARA1_OutputFlexpwm34Pwm3Exta = 78|0x100U,   /**< XBARA1_OUT78 output assigned to FLEXPWM3_4_PWM3_EXTA */
1020     kXBARA1_OutputFlexpwm34ExtClk   = 79|0x100U,   /**< XBARA1_OUT79 output assigned to FLEXPWM3_4_EXT_CLK */
1021     kXBARA1_OutputFlexpwm3Pwm0ExtSync = 80|0x100U, /**< XBARA1_OUT80 output assigned to FLEXPWM3_PWM0_EXT_SYNC */
1022     kXBARA1_OutputFlexpwm3Pwm1ExtSync = 81|0x100U, /**< XBARA1_OUT81 output assigned to FLEXPWM3_PWM1_EXT_SYNC */
1023     kXBARA1_OutputFlexpwm3Pwm2ExtSync = 82|0x100U, /**< XBARA1_OUT82 output assigned to FLEXPWM3_PWM2_EXT_SYNC */
1024     kXBARA1_OutputFlexpwm3Pwm3ExtSync = 83|0x100U, /**< XBARA1_OUT83 output assigned to FLEXPWM3_PWM3_EXT_SYNC */
1025     kXBARA1_OutputFlexpwm3Fault0    = 84|0x100U,   /**< XBARA1_OUT84 output assigned to FLEXPWM3_FAULT0 */
1026     kXBARA1_OutputFlexpwm3Fault1    = 85|0x100U,   /**< XBARA1_OUT85 output assigned to FLEXPWM3_FAULT1 */
1027     kXBARA1_OutputFlexpwm3ExtForce  = 86|0x100U,   /**< XBARA1_OUT86 output assigned to FLEXPWM3_EXT_FORCE */
1028     kXBARA1_OutputFlexpwm4Pwm0ExtSync = 87|0x100U, /**< XBARA1_OUT87 output assigned to FLEXPWM4_PWM0_EXT_SYNC */
1029     kXBARA1_OutputFlexpwm4Pwm1ExtSync = 88|0x100U, /**< XBARA1_OUT88 output assigned to FLEXPWM4_PWM1_EXT_SYNC */
1030     kXBARA1_OutputFlexpwm4Pwm2ExtSync = 89|0x100U, /**< XBARA1_OUT89 output assigned to FLEXPWM4_PWM2_EXT_SYNC */
1031     kXBARA1_OutputFlexpwm4Pwm3ExtSync = 90|0x100U, /**< XBARA1_OUT90 output assigned to FLEXPWM4_PWM3_EXT_SYNC */
1032     kXBARA1_OutputFlexpwm4Fault0    = 91|0x100U,   /**< XBARA1_OUT91 output assigned to FLEXPWM4_FAULT0 */
1033     kXBARA1_OutputFlexpwm4Fault1    = 92|0x100U,   /**< XBARA1_OUT92 output assigned to FLEXPWM4_FAULT1 */
1034     kXBARA1_OutputFlexpwm4ExtForce  = 93|0x100U,   /**< XBARA1_OUT93 output assigned to FLEXPWM4_EXT_FORCE */
1035     kXBARA1_OutputRESERVED94        = 94|0x100U,   /**< XBARA1_OUT94 output is reserved. */
1036     kXBARA1_OutputRESERVED95        = 95|0x100U,   /**< XBARA1_OUT95 output is reserved. */
1037     kXBARA1_OutputRESERVED96        = 96|0x100U,   /**< XBARA1_OUT96 output is reserved. */
1038     kXBARA1_OutputRESERVED97        = 97|0x100U,   /**< XBARA1_OUT97 output is reserved. */
1039     kXBARA1_OutputRESERVED98        = 98|0x100U,   /**< XBARA1_OUT98 output is reserved. */
1040     kXBARA1_OutputRESERVED99        = 99|0x100U,   /**< XBARA1_OUT99 output is reserved. */
1041     kXBARA1_OutputRESERVED100       = 100|0x100U,  /**< XBARA1_OUT100 output is reserved. */
1042     kXBARA1_OutputRESERVED101       = 101|0x100U,  /**< XBARA1_OUT101 output is reserved. */
1043     kXBARA1_OutputRESERVED102       = 102|0x100U,  /**< XBARA1_OUT102 output is reserved. */
1044     kXBARA1_OutputRESERVED103       = 103|0x100U,  /**< XBARA1_OUT103 output is reserved. */
1045     kXBARA1_OutputRESERVED104       = 104|0x100U,  /**< XBARA1_OUT104 output is reserved. */
1046     kXBARA1_OutputRESERVED105       = 105|0x100U,  /**< XBARA1_OUT105 output is reserved. */
1047     kXBARA1_OutputRESERVED106       = 106|0x100U,  /**< XBARA1_OUT106 output is reserved. */
1048     kXBARA1_OutputRESERVED107       = 107|0x100U,  /**< XBARA1_OUT107 output is reserved. */
1049     kXBARA1_OutputDec1Phasea        = 108|0x100U,  /**< XBARA1_OUT108 output assigned to DEC1_PHASEA */
1050     kXBARA1_OutputDec1Phaseb        = 109|0x100U,  /**< XBARA1_OUT109 output assigned to DEC1_PHASEB */
1051     kXBARA1_OutputDec1Index         = 110|0x100U,  /**< XBARA1_OUT110 output assigned to DEC1_INDEX */
1052     kXBARA1_OutputDec1Home          = 111|0x100U,  /**< XBARA1_OUT111 output assigned to DEC1_HOME */
1053     kXBARA1_OutputDec1Trigger       = 112|0x100U,  /**< XBARA1_OUT112 output assigned to DEC1_TRIGGER */
1054     kXBARA1_OutputDec2Phasea        = 113|0x100U,  /**< XBARA1_OUT113 output assigned to DEC2_PHASEA */
1055     kXBARA1_OutputDec2Phaseb        = 114|0x100U,  /**< XBARA1_OUT114 output assigned to DEC2_PHASEB */
1056     kXBARA1_OutputDec2Index         = 115|0x100U,  /**< XBARA1_OUT115 output assigned to DEC2_INDEX */
1057     kXBARA1_OutputDec2Home          = 116|0x100U,  /**< XBARA1_OUT116 output assigned to DEC2_HOME */
1058     kXBARA1_OutputDec2Trigger       = 117|0x100U,  /**< XBARA1_OUT117 output assigned to DEC2_TRIGGER */
1059     kXBARA1_OutputDec3Phasea        = 118|0x100U,  /**< XBARA1_OUT118 output assigned to DEC3_PHASEA */
1060     kXBARA1_OutputDec3Phaseb        = 119|0x100U,  /**< XBARA1_OUT119 output assigned to DEC3_PHASEB */
1061     kXBARA1_OutputDec3Index         = 120|0x100U,  /**< XBARA1_OUT120 output assigned to DEC3_INDEX */
1062     kXBARA1_OutputDec3Home          = 121|0x100U,  /**< XBARA1_OUT121 output assigned to DEC3_HOME */
1063     kXBARA1_OutputDec3Trigger       = 122|0x100U,  /**< XBARA1_OUT122 output assigned to DEC3_TRIGGER */
1064     kXBARA1_OutputDec4Phasea        = 123|0x100U,  /**< XBARA1_OUT123 output assigned to DEC4_PHASEA */
1065     kXBARA1_OutputDec4Phaseb        = 124|0x100U,  /**< XBARA1_OUT124 output assigned to DEC4_PHASEB */
1066     kXBARA1_OutputDec4Index         = 125|0x100U,  /**< XBARA1_OUT125 output assigned to DEC4_INDEX */
1067     kXBARA1_OutputDec4Home          = 126|0x100U,  /**< XBARA1_OUT126 output assigned to DEC4_HOME */
1068     kXBARA1_OutputDec4Trigger       = 127|0x100U,  /**< XBARA1_OUT127 output assigned to DEC4_TRIGGER */
1069     kXBARA1_OutputRESERVED128       = 128|0x100U,  /**< XBARA1_OUT128 output is reserved. */
1070     kXBARA1_OutputRESERVED129       = 129|0x100U,  /**< XBARA1_OUT129 output is reserved. */
1071     kXBARA1_OutputRESERVED130       = 130|0x100U,  /**< XBARA1_OUT130 output is reserved. */
1072     kXBARA1_OutputRESERVED131       = 131|0x100U,  /**< XBARA1_OUT131 output is reserved. */
1073     kXBARA1_OutputCan1              = 132|0x100U,  /**< XBARA1_OUT132 output assigned to CAN1 */
1074     kXBARA1_OutputCan2              = 133|0x100U,  /**< XBARA1_OUT133 output assigned to CAN2 */
1075     kXBARA1_OutputRESERVED134       = 134|0x100U,  /**< XBARA1_OUT134 output is reserved. */
1076     kXBARA1_OutputRESERVED135       = 135|0x100U,  /**< XBARA1_OUT135 output is reserved. */
1077     kXBARA1_OutputRESERVED136       = 136|0x100U,  /**< XBARA1_OUT136 output is reserved. */
1078     kXBARA1_OutputRESERVED137       = 137|0x100U,  /**< XBARA1_OUT137 output is reserved. */
1079     kXBARA1_OutputQtimer1Timer0     = 138|0x100U,  /**< XBARA1_OUT138 output assigned to QTIMER1_TIMER0 */
1080     kXBARA1_OutputQtimer1Timer1     = 139|0x100U,  /**< XBARA1_OUT139 output assigned to QTIMER1_TIMER1 */
1081     kXBARA1_OutputQtimer1Timer2     = 140|0x100U,  /**< XBARA1_OUT140 output assigned to QTIMER1_TIMER2 */
1082     kXBARA1_OutputQtimer1Timer3     = 141|0x100U,  /**< XBARA1_OUT141 output assigned to QTIMER1_TIMER3 */
1083     kXBARA1_OutputQtimer2Timer0     = 142|0x100U,  /**< XBARA1_OUT142 output assigned to QTIMER2_TIMER0 */
1084     kXBARA1_OutputQtimer2Timer1     = 143|0x100U,  /**< XBARA1_OUT143 output assigned to QTIMER2_TIMER1 */
1085     kXBARA1_OutputQtimer2Timer2     = 144|0x100U,  /**< XBARA1_OUT144 output assigned to QTIMER2_TIMER2 */
1086     kXBARA1_OutputQtimer2Timer3     = 145|0x100U,  /**< XBARA1_OUT145 output assigned to QTIMER2_TIMER3 */
1087     kXBARA1_OutputQtimer3Timer0     = 146|0x100U,  /**< XBARA1_OUT146 output assigned to QTIMER3_TIMER0 */
1088     kXBARA1_OutputQtimer3Timer1     = 147|0x100U,  /**< XBARA1_OUT147 output assigned to QTIMER3_TIMER1 */
1089     kXBARA1_OutputQtimer3Timer2     = 148|0x100U,  /**< XBARA1_OUT148 output assigned to QTIMER3_TIMER2 */
1090     kXBARA1_OutputQtimer3Timer3     = 149|0x100U,  /**< XBARA1_OUT149 output assigned to QTIMER3_TIMER3 */
1091     kXBARA1_OutputQtimer4Timer0     = 150|0x100U,  /**< XBARA1_OUT150 output assigned to QTIMER4_TIMER0 */
1092     kXBARA1_OutputQtimer4Timer1     = 151|0x100U,  /**< XBARA1_OUT151 output assigned to QTIMER4_TIMER1 */
1093     kXBARA1_OutputQtimer4Timer2     = 152|0x100U,  /**< XBARA1_OUT152 output assigned to QTIMER4_TIMER2 */
1094     kXBARA1_OutputQtimer4Timer3     = 153|0x100U,  /**< XBARA1_OUT153 output assigned to QTIMER4_TIMER3 */
1095     kXBARA1_OutputEwmEwmIn          = 154|0x100U,  /**< XBARA1_OUT154 output assigned to EWM_EWM_IN */
1096     kXBARA1_OutputAdcEtc0Coco0      = 155|0x100U,  /**< XBARA1_OUT155 output assigned to ADC_ETC0_COCO0 */
1097     kXBARA1_OutputAdcEtc0Coco1      = 156|0x100U,  /**< XBARA1_OUT156 output assigned to ADC_ETC0_COCO1 */
1098     kXBARA1_OutputAdcEtc0Coco2      = 157|0x100U,  /**< XBARA1_OUT157 output assigned to ADC_ETC0_COCO2 */
1099     kXBARA1_OutputAdcEtc0Coco3      = 158|0x100U,  /**< XBARA1_OUT158 output assigned to ADC_ETC0_COCO3 */
1100     kXBARA1_OutputAdcEtc1Coco0      = 159|0x100U,  /**< XBARA1_OUT159 output assigned to ADC_ETC1_COCO0 */
1101     kXBARA1_OutputAdcEtc1Coco1      = 160|0x100U,  /**< XBARA1_OUT160 output assigned to ADC_ETC1_COCO1 */
1102     kXBARA1_OutputAdcEtc1Coco2      = 161|0x100U,  /**< XBARA1_OUT161 output assigned to ADC_ETC1_COCO2 */
1103     kXBARA1_OutputAdcEtc1Coco3      = 162|0x100U,  /**< XBARA1_OUT162 output assigned to ADC_ETC1_COCO3 */
1104     kXBARA1_OutputRESERVED163       = 163|0x100U,  /**< XBARA1_OUT163 output is reserved. */
1105     kXBARA1_OutputRESERVED164       = 164|0x100U,  /**< XBARA1_OUT164 output is reserved. */
1106     kXBARA1_OutputRESERVED165       = 165|0x100U,  /**< XBARA1_OUT165 output is reserved. */
1107     kXBARA1_OutputRESERVED166       = 166|0x100U,  /**< XBARA1_OUT166 output is reserved. */
1108     kXBARA1_OutputRESERVED167       = 167|0x100U,  /**< XBARA1_OUT167 output is reserved. */
1109     kXBARA1_OutputRESERVED168       = 168|0x100U,  /**< XBARA1_OUT168 output is reserved. */
1110     kXBARA1_OutputRESERVED169       = 169|0x100U,  /**< XBARA1_OUT169 output is reserved. */
1111     kXBARA1_OutputRESERVED170       = 170|0x100U,  /**< XBARA1_OUT170 output is reserved. */
1112     kXBARA1_OutputFlexio1TrigIn0    = 171|0x100U,  /**< XBARA1_OUT171 output assigned to FLEXIO1_TRIG_IN0 */
1113     kXBARA1_OutputFlexio1TrigIn1    = 172|0x100U,  /**< XBARA1_OUT172 output assigned to FLEXIO1_TRIG_IN1 */
1114     kXBARA1_OutputFlexio2TrigIn0    = 173|0x100U,  /**< XBARA1_OUT173 output assigned to FLEXIO2_TRIG_IN0 */
1115     kXBARA1_OutputFlexio2TrigIn1    = 174|0x100U,  /**< XBARA1_OUT174 output assigned to FLEXIO2_TRIG_IN1 */
1116     kXBARB2_OutputAoi1In00          = 0|0x200U,    /**< XBARB2_OUT0 output assigned to AOI1_IN00 */
1117     kXBARB2_OutputAoi1In01          = 1|0x200U,    /**< XBARB2_OUT1 output assigned to AOI1_IN01 */
1118     kXBARB2_OutputAoi1In02          = 2|0x200U,    /**< XBARB2_OUT2 output assigned to AOI1_IN02 */
1119     kXBARB2_OutputAoi1In03          = 3|0x200U,    /**< XBARB2_OUT3 output assigned to AOI1_IN03 */
1120     kXBARB2_OutputAoi1In04          = 4|0x200U,    /**< XBARB2_OUT4 output assigned to AOI1_IN04 */
1121     kXBARB2_OutputAoi1In05          = 5|0x200U,    /**< XBARB2_OUT5 output assigned to AOI1_IN05 */
1122     kXBARB2_OutputAoi1In06          = 6|0x200U,    /**< XBARB2_OUT6 output assigned to AOI1_IN06 */
1123     kXBARB2_OutputAoi1In07          = 7|0x200U,    /**< XBARB2_OUT7 output assigned to AOI1_IN07 */
1124     kXBARB2_OutputAoi1In08          = 8|0x200U,    /**< XBARB2_OUT8 output assigned to AOI1_IN08 */
1125     kXBARB2_OutputAoi1In09          = 9|0x200U,    /**< XBARB2_OUT9 output assigned to AOI1_IN09 */
1126     kXBARB2_OutputAoi1In10          = 10|0x200U,   /**< XBARB2_OUT10 output assigned to AOI1_IN10 */
1127     kXBARB2_OutputAoi1In11          = 11|0x200U,   /**< XBARB2_OUT11 output assigned to AOI1_IN11 */
1128     kXBARB2_OutputAoi1In12          = 12|0x200U,   /**< XBARB2_OUT12 output assigned to AOI1_IN12 */
1129     kXBARB2_OutputAoi1In13          = 13|0x200U,   /**< XBARB2_OUT13 output assigned to AOI1_IN13 */
1130     kXBARB2_OutputAoi1In14          = 14|0x200U,   /**< XBARB2_OUT14 output assigned to AOI1_IN14 */
1131     kXBARB2_OutputAoi1In15          = 15|0x200U,   /**< XBARB2_OUT15 output assigned to AOI1_IN15 */
1132     kXBARB3_OutputAoi2In00          = 0|0x300U,    /**< XBARB3_OUT0 output assigned to AOI2_IN00 */
1133     kXBARB3_OutputAoi2In01          = 1|0x300U,    /**< XBARB3_OUT1 output assigned to AOI2_IN01 */
1134     kXBARB3_OutputAoi2In02          = 2|0x300U,    /**< XBARB3_OUT2 output assigned to AOI2_IN02 */
1135     kXBARB3_OutputAoi2In03          = 3|0x300U,    /**< XBARB3_OUT3 output assigned to AOI2_IN03 */
1136     kXBARB3_OutputAoi2In04          = 4|0x300U,    /**< XBARB3_OUT4 output assigned to AOI2_IN04 */
1137     kXBARB3_OutputAoi2In05          = 5|0x300U,    /**< XBARB3_OUT5 output assigned to AOI2_IN05 */
1138     kXBARB3_OutputAoi2In06          = 6|0x300U,    /**< XBARB3_OUT6 output assigned to AOI2_IN06 */
1139     kXBARB3_OutputAoi2In07          = 7|0x300U,    /**< XBARB3_OUT7 output assigned to AOI2_IN07 */
1140     kXBARB3_OutputAoi2In08          = 8|0x300U,    /**< XBARB3_OUT8 output assigned to AOI2_IN08 */
1141     kXBARB3_OutputAoi2In09          = 9|0x300U,    /**< XBARB3_OUT9 output assigned to AOI2_IN09 */
1142     kXBARB3_OutputAoi2In10          = 10|0x300U,   /**< XBARB3_OUT10 output assigned to AOI2_IN10 */
1143     kXBARB3_OutputAoi2In11          = 11|0x300U,   /**< XBARB3_OUT11 output assigned to AOI2_IN11 */
1144     kXBARB3_OutputAoi2In12          = 12|0x300U,   /**< XBARB3_OUT12 output assigned to AOI2_IN12 */
1145     kXBARB3_OutputAoi2In13          = 13|0x300U,   /**< XBARB3_OUT13 output assigned to AOI2_IN13 */
1146     kXBARB3_OutputAoi2In14          = 14|0x300U,   /**< XBARB3_OUT14 output assigned to AOI2_IN14 */
1147     kXBARB3_OutputAoi2In15          = 15|0x300U,   /**< XBARB3_OUT15 output assigned to AOI2_IN15 */
1148 } xbar_output_signal_t;
1149 
1150 /*!
1151  * @addtogroup iomuxc_lpsr_pads
1152  * @{ */
1153 
1154 /*******************************************************************************
1155  * Definitions
1156 *******************************************************************************/
1157 
1158 /*!
1159  * @brief Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD
1160  *
1161  * Defines the enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD collections.
1162  */
1163 typedef enum _iomuxc_lpsr_sw_mux_ctl_pad
1164 {
1165     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
1166     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
1167     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
1168     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
1169     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
1170     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
1171     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
1172     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
1173     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
1174     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
1175     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
1176     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
1177     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
1178     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
1179     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
1180     kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
1181 } iomuxc_lpsr_sw_mux_ctl_pad_t;
1182 
1183 /* @} */
1184 
1185 /*!
1186  * @addtogroup iomuxc_lpsr_pads
1187  * @{ */
1188 
1189 /*******************************************************************************
1190  * Definitions
1191 *******************************************************************************/
1192 
1193 /*!
1194  * @brief Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD
1195  *
1196  * Defines the enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD collections.
1197  */
1198 typedef enum _iomuxc_lpsr_sw_pad_ctl_pad
1199 {
1200     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
1201     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
1202     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
1203     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
1204     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
1205     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
1206     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
1207     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
1208     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
1209     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
1210     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
1211     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
1212     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
1213     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
1214     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
1215     kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
1216 } iomuxc_lpsr_sw_pad_ctl_pad_t;
1217 
1218 /* @} */
1219 
1220 /*!
1221  * @brief Enumeration for the IOMUXC_LPSR select input
1222  *
1223  * Defines the enumeration for the IOMUXC_LPSR select input collections.
1224  */
1225 typedef enum _iomuxc_lpsr_select_input
1226 {
1227     kIOMUXC_LPSR_CAN3_IPP_IND_CANRX_SELECT_INPUT = 0U, /**< IOMUXC select input index */
1228     kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT = 1U, /**< IOMUXC select input index */
1229     kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT = 2U, /**< IOMUXC select input index */
1230     kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT = 3U, /**< IOMUXC select input index */
1231     kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT = 4U, /**< IOMUXC select input index */
1232     kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 5U, /**< IOMUXC select input index */
1233     kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT = 6U, /**< IOMUXC select input index */
1234     kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT = 7U, /**< IOMUXC select input index */
1235     kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT = 8U, /**< IOMUXC select input index */
1236     kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT = 9U, /**< IOMUXC select input index */
1237     kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT = 10U, /**< IOMUXC select input index */
1238     kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT = 11U, /**< IOMUXC select input index */
1239     kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT = 12U, /**< IOMUXC select input index */
1240     kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 = 13U, /**< IOMUXC select input index */
1241     kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 = 14U, /**< IOMUXC select input index */
1242     kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 = 15U, /**< IOMUXC select input index */
1243     kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 = 16U, /**< IOMUXC select input index */
1244     kIOMUXC_LPSR_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT = 17U, /**< IOMUXC select input index */
1245     kIOMUXC_LPSR_SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT = 18U, /**< IOMUXC select input index */
1246     kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 19U, /**< IOMUXC select input index */
1247     kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 20U, /**< IOMUXC select input index */
1248     kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 21U, /**< IOMUXC select input index */
1249     kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 22U, /**< IOMUXC select input index */
1250     kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 23U, /**< IOMUXC select input index */
1251 } iomuxc_lpsr_select_input_t;
1252 
1253 /*!
1254  * @addtogroup ssarc_mapping
1255  * @{
1256  */
1257 
1258 /*******************************************************************************
1259  * Definitions
1260  ******************************************************************************/
1261 
1262 /*!
1263  * @brief Structure for the SSARC mapping
1264  *
1265  * The name of power domain.
1266  */
1267 
1268 typedef enum _ssarc_power_domain_name
1269 {
1270     kSSARC_MEGAMIXPowerDomain       = 0U,          /**< MEGAMIX Power Domain, request from BPC0. */
1271     kSSARC_DISPLAYMIXPowerDomain    = 1U,          /**< DISPLAYMIX Power Domain, request from BPC1. */
1272     kSSARC_WAKEUPMIXPowerDomain     = 2U,          /**< WAKEUPMIX Power Domain, request from BPC2. */
1273     kSSARC_LPSRMIXPowerDomain       = 3U,          /**< LPSRMIX Power Domain, request from BPC3. */
1274     kSSARC_PowerDomain4             = 4U,          /**< MIPI PHY Power Domain, request from BPC4. */
1275     kSSARC_PowerDomain5             = 5U,          /**< Virtual power domain, request from BPC5. */
1276     kSSARC_PowerDomain6             = 6U,          /**< Virtual power domain, request from BPC6. */
1277     kSSARC_PowerDomain7             = 7U,          /**< Virtual power domain, request from BPC7. */
1278 } ssarc_power_domain_name_t;
1279 
1280  /*
1281  * @brief The name of cpu domain.
1282  */
1283 typedef enum _ssarc_cpu_domain_name
1284 {
1285     kSSARC_CM7Core                  = 0U,          /**< CM7 Core domain. */
1286     kSSARC_CM4Core                  = 1U,          /**< CM4 Core domain. */
1287 } ssarc_cpu_domain_name_t;
1288 
1289 /* @} */
1290 
1291 /*!
1292  * @addtogroup xrdc2_mapping
1293  * @{
1294  */
1295 
1296 /*******************************************************************************
1297  * Definitions
1298  ******************************************************************************/
1299 
1300 /*!
1301  * @brief Structure for the XRDC2 mapping
1302  *
1303  * Defines the structure for the XRDC2 resource collections.
1304  */
1305 
1306 typedef enum _xrdc2_master
1307 {
1308     kXRDC2_Master_M7_AHB            = 0U,          /**< M7 AHB */
1309     kXRDC2_Master_M4_AHBC           = 0U,          /**< M4 AHBC */
1310     kXRDC2_Master_M7_AXI            = 1U,          /**< M7 AXI */
1311     kXRDC2_Master_M4_AHBS           = 1U,          /**< M4 AHBS */
1312     kXRDC2_Master_CAAM              = 2U,          /**< CAAM */
1313     kXRDC2_Master_CSI               = 3U,          /**< CSI */
1314     kXRDC2_Master_M7_EDMA           = 4U,          /**< M7 EDMA */
1315     kXRDC2_Master_M4_EDMA           = 4U,          /**< M4 EDMA */
1316     kXRDC2_Master_ENET              = 5U,          /**< ENET */
1317     kXRDC2_Master_ENET_1G_RX        = 6U,          /**< ENET_1G_RX */
1318     kXRDC2_Master_ENET_1G_TX        = 7U,          /**< ENET_1G_TX */
1319     kXRDC2_Master_ENET_QOS          = 8U,          /**< ENET_QOS */
1320     kXRDC2_Master_GPU               = 9U,          /**< GPU */
1321     kXRDC2_Master_LCDIF             = 10U,         /**< LCDIF */
1322     kXRDC2_Master_LCDIFV2           = 11U,         /**< LCDIFV2 */
1323     kXRDC2_Master_PXP               = 12U,         /**< PXP */
1324     kXRDC2_Master_SSARC             = 14U,         /**< SSARC */
1325     kXRDC2_Master_USB               = 15U,         /**< USB */
1326     kXRDC2_Master_USDHC1            = 16U,         /**< USDHC1 */
1327     kXRDC2_Master_USDHC2            = 17U,         /**< USDHC2 */
1328 } xrdc2_master_t;
1329 
1330 typedef enum _xrdc2_mem
1331 {
1332     kXRDC2_Mem_CAAM_Region0         = XRDC2_MAKE_MEM(0, 0), /**< MRC0 Memory 0 */
1333     kXRDC2_Mem_CAAM_Region1         = XRDC2_MAKE_MEM(0, 1), /**< MRC0 Memory 1 */
1334     kXRDC2_Mem_CAAM_Region2         = XRDC2_MAKE_MEM(0, 2), /**< MRC0 Memory 2 */
1335     kXRDC2_Mem_CAAM_Region3         = XRDC2_MAKE_MEM(0, 3), /**< MRC0 Memory 3 */
1336     kXRDC2_Mem_CAAM_Region4         = XRDC2_MAKE_MEM(0, 4), /**< MRC0 Memory 4 */
1337     kXRDC2_Mem_CAAM_Region5         = XRDC2_MAKE_MEM(0, 5), /**< MRC0 Memory 5 */
1338     kXRDC2_Mem_CAAM_Region6         = XRDC2_MAKE_MEM(0, 6), /**< MRC0 Memory 6 */
1339     kXRDC2_Mem_CAAM_Region7         = XRDC2_MAKE_MEM(0, 7), /**< MRC0 Memory 7 */
1340     kXRDC2_Mem_CAAM_Region8         = XRDC2_MAKE_MEM(0, 8), /**< MRC0 Memory 8 */
1341     kXRDC2_Mem_CAAM_Region9         = XRDC2_MAKE_MEM(0, 9), /**< MRC0 Memory 9 */
1342     kXRDC2_Mem_CAAM_Region10        = XRDC2_MAKE_MEM(0, 10), /**< MRC0 Memory 10 */
1343     kXRDC2_Mem_CAAM_Region11        = XRDC2_MAKE_MEM(0, 11), /**< MRC0 Memory 11 */
1344     kXRDC2_Mem_CAAM_Region12        = XRDC2_MAKE_MEM(0, 12), /**< MRC0 Memory 12 */
1345     kXRDC2_Mem_CAAM_Region13        = XRDC2_MAKE_MEM(0, 13), /**< MRC0 Memory 13 */
1346     kXRDC2_Mem_CAAM_Region14        = XRDC2_MAKE_MEM(0, 14), /**< MRC0 Memory 14 */
1347     kXRDC2_Mem_CAAM_Region15        = XRDC2_MAKE_MEM(0, 15), /**< MRC0 Memory 15 */
1348     kXRDC2_Mem_FLEXSPI1_Region0     = XRDC2_MAKE_MEM(1, 0), /**< MRC1 Memory 0 */
1349     kXRDC2_Mem_FLEXSPI1_Region1     = XRDC2_MAKE_MEM(1, 1), /**< MRC1 Memory 1 */
1350     kXRDC2_Mem_FLEXSPI1_Region2     = XRDC2_MAKE_MEM(1, 2), /**< MRC1 Memory 2 */
1351     kXRDC2_Mem_FLEXSPI1_Region3     = XRDC2_MAKE_MEM(1, 3), /**< MRC1 Memory 3 */
1352     kXRDC2_Mem_FLEXSPI1_Region4     = XRDC2_MAKE_MEM(1, 4), /**< MRC1 Memory 4 */
1353     kXRDC2_Mem_FLEXSPI1_Region5     = XRDC2_MAKE_MEM(1, 5), /**< MRC1 Memory 5 */
1354     kXRDC2_Mem_FLEXSPI1_Region6     = XRDC2_MAKE_MEM(1, 6), /**< MRC1 Memory 6 */
1355     kXRDC2_Mem_FLEXSPI1_Region7     = XRDC2_MAKE_MEM(1, 7), /**< MRC1 Memory 7 */
1356     kXRDC2_Mem_FLEXSPI1_Region8     = XRDC2_MAKE_MEM(1, 8), /**< MRC1 Memory 8 */
1357     kXRDC2_Mem_FLEXSPI1_Region9     = XRDC2_MAKE_MEM(1, 9), /**< MRC1 Memory 9 */
1358     kXRDC2_Mem_FLEXSPI1_Region10    = XRDC2_MAKE_MEM(1, 10), /**< MRC1 Memory 10 */
1359     kXRDC2_Mem_FLEXSPI1_Region11    = XRDC2_MAKE_MEM(1, 11), /**< MRC1 Memory 11 */
1360     kXRDC2_Mem_FLEXSPI1_Region12    = XRDC2_MAKE_MEM(1, 12), /**< MRC1 Memory 12 */
1361     kXRDC2_Mem_FLEXSPI1_Region13    = XRDC2_MAKE_MEM(1, 13), /**< MRC1 Memory 13 */
1362     kXRDC2_Mem_FLEXSPI1_Region14    = XRDC2_MAKE_MEM(1, 14), /**< MRC1 Memory 14 */
1363     kXRDC2_Mem_FLEXSPI1_Region15    = XRDC2_MAKE_MEM(1, 15), /**< MRC1 Memory 15 */
1364     kXRDC2_Mem_FLEXSPI2_Region0     = XRDC2_MAKE_MEM(2, 0), /**< MRC2 Memory 0 */
1365     kXRDC2_Mem_FLEXSPI2_Region1     = XRDC2_MAKE_MEM(2, 1), /**< MRC2 Memory 1 */
1366     kXRDC2_Mem_FLEXSPI2_Region2     = XRDC2_MAKE_MEM(2, 2), /**< MRC2 Memory 2 */
1367     kXRDC2_Mem_FLEXSPI2_Region3     = XRDC2_MAKE_MEM(2, 3), /**< MRC2 Memory 3 */
1368     kXRDC2_Mem_FLEXSPI2_Region4     = XRDC2_MAKE_MEM(2, 4), /**< MRC2 Memory 4 */
1369     kXRDC2_Mem_FLEXSPI2_Region5     = XRDC2_MAKE_MEM(2, 5), /**< MRC2 Memory 5 */
1370     kXRDC2_Mem_FLEXSPI2_Region6     = XRDC2_MAKE_MEM(2, 6), /**< MRC2 Memory 6 */
1371     kXRDC2_Mem_FLEXSPI2_Region7     = XRDC2_MAKE_MEM(2, 7), /**< MRC2 Memory 7 */
1372     kXRDC2_Mem_FLEXSPI2_Region8     = XRDC2_MAKE_MEM(2, 8), /**< MRC2 Memory 8 */
1373     kXRDC2_Mem_FLEXSPI2_Region9     = XRDC2_MAKE_MEM(2, 9), /**< MRC2 Memory 9 */
1374     kXRDC2_Mem_FLEXSPI2_Region10    = XRDC2_MAKE_MEM(2, 10), /**< MRC2 Memory 10 */
1375     kXRDC2_Mem_FLEXSPI2_Region11    = XRDC2_MAKE_MEM(2, 11), /**< MRC2 Memory 11 */
1376     kXRDC2_Mem_FLEXSPI2_Region12    = XRDC2_MAKE_MEM(2, 12), /**< MRC2 Memory 12 */
1377     kXRDC2_Mem_FLEXSPI2_Region13    = XRDC2_MAKE_MEM(2, 13), /**< MRC2 Memory 13 */
1378     kXRDC2_Mem_FLEXSPI2_Region14    = XRDC2_MAKE_MEM(2, 14), /**< MRC2 Memory 14 */
1379     kXRDC2_Mem_FLEXSPI2_Region15    = XRDC2_MAKE_MEM(2, 15), /**< MRC2 Memory 15 */
1380     kXRDC2_Mem_M4LMEM_Region0       = XRDC2_MAKE_MEM(3, 0), /**< MRC3 Memory 0 */
1381     kXRDC2_Mem_M4LMEM_Region1       = XRDC2_MAKE_MEM(3, 1), /**< MRC3 Memory 1 */
1382     kXRDC2_Mem_M4LMEM_Region2       = XRDC2_MAKE_MEM(3, 2), /**< MRC3 Memory 2 */
1383     kXRDC2_Mem_M4LMEM_Region3       = XRDC2_MAKE_MEM(3, 3), /**< MRC3 Memory 3 */
1384     kXRDC2_Mem_M4LMEM_Region4       = XRDC2_MAKE_MEM(3, 4), /**< MRC3 Memory 4 */
1385     kXRDC2_Mem_M4LMEM_Region5       = XRDC2_MAKE_MEM(3, 5), /**< MRC3 Memory 5 */
1386     kXRDC2_Mem_M4LMEM_Region6       = XRDC2_MAKE_MEM(3, 6), /**< MRC3 Memory 6 */
1387     kXRDC2_Mem_M4LMEM_Region7       = XRDC2_MAKE_MEM(3, 7), /**< MRC3 Memory 7 */
1388     kXRDC2_Mem_M4LMEM_Region8       = XRDC2_MAKE_MEM(3, 8), /**< MRC3 Memory 8 */
1389     kXRDC2_Mem_M4LMEM_Region9       = XRDC2_MAKE_MEM(3, 9), /**< MRC3 Memory 9 */
1390     kXRDC2_Mem_M4LMEM_Region10      = XRDC2_MAKE_MEM(3, 10), /**< MRC3 Memory 10 */
1391     kXRDC2_Mem_M4LMEM_Region11      = XRDC2_MAKE_MEM(3, 11), /**< MRC3 Memory 11 */
1392     kXRDC2_Mem_M4LMEM_Region12      = XRDC2_MAKE_MEM(3, 12), /**< MRC3 Memory 12 */
1393     kXRDC2_Mem_M4LMEM_Region13      = XRDC2_MAKE_MEM(3, 13), /**< MRC3 Memory 13 */
1394     kXRDC2_Mem_M4LMEM_Region14      = XRDC2_MAKE_MEM(3, 14), /**< MRC3 Memory 14 */
1395     kXRDC2_Mem_M4LMEM_Region15      = XRDC2_MAKE_MEM(3, 15), /**< MRC3 Memory 15 */
1396     kXRDC2_Mem_M7OC_Region0         = XRDC2_MAKE_MEM(4, 0), /**< MRC4 Memory 0 */
1397     kXRDC2_Mem_M7OC_Region1         = XRDC2_MAKE_MEM(4, 1), /**< MRC4 Memory 1 */
1398     kXRDC2_Mem_M7OC_Region2         = XRDC2_MAKE_MEM(4, 2), /**< MRC4 Memory 2 */
1399     kXRDC2_Mem_M7OC_Region3         = XRDC2_MAKE_MEM(4, 3), /**< MRC4 Memory 3 */
1400     kXRDC2_Mem_M7OC_Region4         = XRDC2_MAKE_MEM(4, 4), /**< MRC4 Memory 4 */
1401     kXRDC2_Mem_M7OC_Region5         = XRDC2_MAKE_MEM(4, 5), /**< MRC4 Memory 5 */
1402     kXRDC2_Mem_M7OC_Region6         = XRDC2_MAKE_MEM(4, 6), /**< MRC4 Memory 6 */
1403     kXRDC2_Mem_M7OC_Region7         = XRDC2_MAKE_MEM(4, 7), /**< MRC4 Memory 7 */
1404     kXRDC2_Mem_M7OC_Region8         = XRDC2_MAKE_MEM(4, 8), /**< MRC4 Memory 8 */
1405     kXRDC2_Mem_M7OC_Region9         = XRDC2_MAKE_MEM(4, 9), /**< MRC4 Memory 9 */
1406     kXRDC2_Mem_M7OC_Region10        = XRDC2_MAKE_MEM(4, 10), /**< MRC4 Memory 10 */
1407     kXRDC2_Mem_M7OC_Region11        = XRDC2_MAKE_MEM(4, 11), /**< MRC4 Memory 11 */
1408     kXRDC2_Mem_M7OC_Region12        = XRDC2_MAKE_MEM(4, 12), /**< MRC4 Memory 12 */
1409     kXRDC2_Mem_M7OC_Region13        = XRDC2_MAKE_MEM(4, 13), /**< MRC4 Memory 13 */
1410     kXRDC2_Mem_M7OC_Region14        = XRDC2_MAKE_MEM(4, 14), /**< MRC4 Memory 14 */
1411     kXRDC2_Mem_M7OC_Region15        = XRDC2_MAKE_MEM(4, 15), /**< MRC4 Memory 15 */
1412     kXRDC2_Mem_MECC1_Region0        = XRDC2_MAKE_MEM(5, 0), /**< MRC5 Memory 0 */
1413     kXRDC2_Mem_MECC1_Region1        = XRDC2_MAKE_MEM(5, 1), /**< MRC5 Memory 1 */
1414     kXRDC2_Mem_MECC1_Region2        = XRDC2_MAKE_MEM(5, 2), /**< MRC5 Memory 2 */
1415     kXRDC2_Mem_MECC1_Region3        = XRDC2_MAKE_MEM(5, 3), /**< MRC5 Memory 3 */
1416     kXRDC2_Mem_MECC1_Region4        = XRDC2_MAKE_MEM(5, 4), /**< MRC5 Memory 4 */
1417     kXRDC2_Mem_MECC1_Region5        = XRDC2_MAKE_MEM(5, 5), /**< MRC5 Memory 5 */
1418     kXRDC2_Mem_MECC1_Region6        = XRDC2_MAKE_MEM(5, 6), /**< MRC5 Memory 6 */
1419     kXRDC2_Mem_MECC1_Region7        = XRDC2_MAKE_MEM(5, 7), /**< MRC5 Memory 7 */
1420     kXRDC2_Mem_MECC1_Region8        = XRDC2_MAKE_MEM(5, 8), /**< MRC5 Memory 8 */
1421     kXRDC2_Mem_MECC1_Region9        = XRDC2_MAKE_MEM(5, 9), /**< MRC5 Memory 9 */
1422     kXRDC2_Mem_MECC1_Region10       = XRDC2_MAKE_MEM(5, 10), /**< MRC5 Memory 10 */
1423     kXRDC2_Mem_MECC1_Region11       = XRDC2_MAKE_MEM(5, 11), /**< MRC5 Memory 11 */
1424     kXRDC2_Mem_MECC1_Region12       = XRDC2_MAKE_MEM(5, 12), /**< MRC5 Memory 12 */
1425     kXRDC2_Mem_MECC1_Region13       = XRDC2_MAKE_MEM(5, 13), /**< MRC5 Memory 13 */
1426     kXRDC2_Mem_MECC1_Region14       = XRDC2_MAKE_MEM(5, 14), /**< MRC5 Memory 14 */
1427     kXRDC2_Mem_MECC1_Region15       = XRDC2_MAKE_MEM(5, 15), /**< MRC5 Memory 15 */
1428     kXRDC2_Mem_MECC2_Region0        = XRDC2_MAKE_MEM(6, 0), /**< MRC6 Memory 0 */
1429     kXRDC2_Mem_MECC2_Region1        = XRDC2_MAKE_MEM(6, 1), /**< MRC6 Memory 1 */
1430     kXRDC2_Mem_MECC2_Region2        = XRDC2_MAKE_MEM(6, 2), /**< MRC6 Memory 2 */
1431     kXRDC2_Mem_MECC2_Region3        = XRDC2_MAKE_MEM(6, 3), /**< MRC6 Memory 3 */
1432     kXRDC2_Mem_MECC2_Region4        = XRDC2_MAKE_MEM(6, 4), /**< MRC6 Memory 4 */
1433     kXRDC2_Mem_MECC2_Region5        = XRDC2_MAKE_MEM(6, 5), /**< MRC6 Memory 5 */
1434     kXRDC2_Mem_MECC2_Region6        = XRDC2_MAKE_MEM(6, 6), /**< MRC6 Memory 6 */
1435     kXRDC2_Mem_MECC2_Region7        = XRDC2_MAKE_MEM(6, 7), /**< MRC6 Memory 7 */
1436     kXRDC2_Mem_MECC2_Region8        = XRDC2_MAKE_MEM(6, 8), /**< MRC6 Memory 8 */
1437     kXRDC2_Mem_MECC2_Region9        = XRDC2_MAKE_MEM(6, 9), /**< MRC6 Memory 9 */
1438     kXRDC2_Mem_MECC2_Region10       = XRDC2_MAKE_MEM(6, 10), /**< MRC6 Memory 10 */
1439     kXRDC2_Mem_MECC2_Region11       = XRDC2_MAKE_MEM(6, 11), /**< MRC6 Memory 11 */
1440     kXRDC2_Mem_MECC2_Region12       = XRDC2_MAKE_MEM(6, 12), /**< MRC6 Memory 12 */
1441     kXRDC2_Mem_MECC2_Region13       = XRDC2_MAKE_MEM(6, 13), /**< MRC6 Memory 13 */
1442     kXRDC2_Mem_MECC2_Region14       = XRDC2_MAKE_MEM(6, 14), /**< MRC6 Memory 14 */
1443     kXRDC2_Mem_MECC2_Region15       = XRDC2_MAKE_MEM(6, 15), /**< MRC6 Memory 15 */
1444     kXRDC2_Mem_SEMC_Region0         = XRDC2_MAKE_MEM(7, 0), /**< MRC7 Memory 0 */
1445     kXRDC2_Mem_SEMC_Region1         = XRDC2_MAKE_MEM(7, 1), /**< MRC7 Memory 1 */
1446     kXRDC2_Mem_SEMC_Region2         = XRDC2_MAKE_MEM(7, 2), /**< MRC7 Memory 2 */
1447     kXRDC2_Mem_SEMC_Region3         = XRDC2_MAKE_MEM(7, 3), /**< MRC7 Memory 3 */
1448     kXRDC2_Mem_SEMC_Region4         = XRDC2_MAKE_MEM(7, 4), /**< MRC7 Memory 4 */
1449     kXRDC2_Mem_SEMC_Region5         = XRDC2_MAKE_MEM(7, 5), /**< MRC7 Memory 5 */
1450     kXRDC2_Mem_SEMC_Region6         = XRDC2_MAKE_MEM(7, 6), /**< MRC7 Memory 6 */
1451     kXRDC2_Mem_SEMC_Region7         = XRDC2_MAKE_MEM(7, 7), /**< MRC7 Memory 7 */
1452     kXRDC2_Mem_SEMC_Region8         = XRDC2_MAKE_MEM(7, 8), /**< MRC7 Memory 8 */
1453     kXRDC2_Mem_SEMC_Region9         = XRDC2_MAKE_MEM(7, 9), /**< MRC7 Memory 9 */
1454     kXRDC2_Mem_SEMC_Region10        = XRDC2_MAKE_MEM(7, 10), /**< MRC7 Memory 10 */
1455     kXRDC2_Mem_SEMC_Region11        = XRDC2_MAKE_MEM(7, 11), /**< MRC7 Memory 11 */
1456     kXRDC2_Mem_SEMC_Region12        = XRDC2_MAKE_MEM(7, 12), /**< MRC7 Memory 12 */
1457     kXRDC2_Mem_SEMC_Region13        = XRDC2_MAKE_MEM(7, 13), /**< MRC7 Memory 13 */
1458     kXRDC2_Mem_SEMC_Region14        = XRDC2_MAKE_MEM(7, 14), /**< MRC7 Memory 14 */
1459     kXRDC2_Mem_SEMC_Region15        = XRDC2_MAKE_MEM(7, 15), /**< MRC7 Memory 15 */
1460 } xrdc2_mem_t;
1461 
1462 typedef enum _xrdc2_mem_slot
1463 {
1464     kXRDC2_MemSlot_GPV0             = 0U,          /**< GPV0 */
1465     kXRDC2_MemSlot_GPV1             = 1U,          /**< GPV1 */
1466     kXRDC2_MemSlot_GPV2             = 2U,          /**< GPV2 */
1467     kXRDC2_MemSlot_ROMCP            = 3U,          /**< ROMCP */
1468 } xrdc2_mem_slot_t;
1469 
1470 typedef enum _xrdc2_periph
1471 {
1472     kXRDC2_Periph_ACMP4             = XRDC2_MAKE_PERIPH(0, 108), /**< ACMP4 */
1473     kXRDC2_Periph_ACMP3             = XRDC2_MAKE_PERIPH(0, 107), /**< ACMP3 */
1474     kXRDC2_Periph_ACMP2             = XRDC2_MAKE_PERIPH(0, 106), /**< ACMP2 */
1475     kXRDC2_Periph_ACMP1             = XRDC2_MAKE_PERIPH(0, 105), /**< ACMP1 */
1476     kXRDC2_Periph_FLEXPWM4          = XRDC2_MAKE_PERIPH(0, 102), /**< FLEXPWM4 */
1477     kXRDC2_Periph_FLEXPWM3          = XRDC2_MAKE_PERIPH(0, 101), /**< FLEXPWM3 */
1478     kXRDC2_Periph_FLEXPWM2          = XRDC2_MAKE_PERIPH(0, 100), /**< FLEXPWM2 */
1479     kXRDC2_Periph_FLEXPWM1          = XRDC2_MAKE_PERIPH(0, 99 ), /**< FLEXPWM1 */
1480     kXRDC2_Periph_ENC4              = XRDC2_MAKE_PERIPH(0, 96 ), /**< ENC4 */
1481     kXRDC2_Periph_ENC3              = XRDC2_MAKE_PERIPH(0, 95 ), /**< ENC3 */
1482     kXRDC2_Periph_ENC2              = XRDC2_MAKE_PERIPH(0, 94 ), /**< ENC2 */
1483     kXRDC2_Periph_ENC1              = XRDC2_MAKE_PERIPH(0, 93 ), /**< ENC1 */
1484     kXRDC2_Periph_QTIMER4           = XRDC2_MAKE_PERIPH(0, 90 ), /**< QTIMER4 */
1485     kXRDC2_Periph_QTIMER3           = XRDC2_MAKE_PERIPH(0, 89 ), /**< QTIMER3 */
1486     kXRDC2_Periph_QTIMER2           = XRDC2_MAKE_PERIPH(0, 88 ), /**< QTIMER2 */
1487     kXRDC2_Periph_QTIMER1           = XRDC2_MAKE_PERIPH(0, 87 ), /**< QTIMER1 */
1488     kXRDC2_Periph_SIM2              = XRDC2_MAKE_PERIPH(0, 86 ), /**< SIM2 */
1489     kXRDC2_Periph_SIM1              = XRDC2_MAKE_PERIPH(0, 85 ), /**< SIM1 */
1490     kXRDC2_Periph_CCM_OBS           = XRDC2_MAKE_PERIPH(0, 84 ), /**< CCM_OBS */
1491     kXRDC2_Periph_GPIO6             = XRDC2_MAKE_PERIPH(0, 80 ), /**< GPIO6 */
1492     kXRDC2_Periph_GPIO5             = XRDC2_MAKE_PERIPH(0, 79 ), /**< GPIO5 */
1493     kXRDC2_Periph_GPIO4             = XRDC2_MAKE_PERIPH(0, 78 ), /**< GPIO4 */
1494     kXRDC2_Periph_GPIO3             = XRDC2_MAKE_PERIPH(0, 77 ), /**< GPIO3 */
1495     kXRDC2_Periph_GPIO2             = XRDC2_MAKE_PERIPH(0, 76 ), /**< GPIO2 */
1496     kXRDC2_Periph_GPIO1             = XRDC2_MAKE_PERIPH(0, 75 ), /**< GPIO1 */
1497     kXRDC2_Periph_LPSPI4            = XRDC2_MAKE_PERIPH(0, 72 ), /**< LPSPI4 */
1498     kXRDC2_Periph_LPSPI3            = XRDC2_MAKE_PERIPH(0, 71 ), /**< LPSPI3 */
1499     kXRDC2_Periph_LPSPI2            = XRDC2_MAKE_PERIPH(0, 70 ), /**< LPSPI2 */
1500     kXRDC2_Periph_LPSPI1            = XRDC2_MAKE_PERIPH(0, 69 ), /**< LPSPI1 */
1501     kXRDC2_Periph_LPI2C4            = XRDC2_MAKE_PERIPH(0, 68 ), /**< LPI2C4 */
1502     kXRDC2_Periph_LPI2C3            = XRDC2_MAKE_PERIPH(0, 67 ), /**< LPI2C3 */
1503     kXRDC2_Periph_LPI2C2            = XRDC2_MAKE_PERIPH(0, 66 ), /**< LPI2C2 */
1504     kXRDC2_Periph_LPI2C1            = XRDC2_MAKE_PERIPH(0, 65 ), /**< LPI2C1 */
1505     kXRDC2_Periph_GPT6              = XRDC2_MAKE_PERIPH(0, 64 ), /**< GPT6 */
1506     kXRDC2_Periph_GPT5              = XRDC2_MAKE_PERIPH(0, 63 ), /**< GPT5 */
1507     kXRDC2_Periph_GPT4              = XRDC2_MAKE_PERIPH(0, 62 ), /**< GPT4 */
1508     kXRDC2_Periph_GPT3              = XRDC2_MAKE_PERIPH(0, 61 ), /**< GPT3 */
1509     kXRDC2_Periph_GPT2              = XRDC2_MAKE_PERIPH(0, 60 ), /**< GPT2 */
1510     kXRDC2_Periph_GPT1              = XRDC2_MAKE_PERIPH(0, 59 ), /**< GPT1 */
1511     kXRDC2_Periph_IOMUXC            = XRDC2_MAKE_PERIPH(0, 58 ), /**< IOMUXC */
1512     kXRDC2_Periph_IOMUXC_GPR        = XRDC2_MAKE_PERIPH(0, 57 ), /**< IOMUXC_GPR */
1513     kXRDC2_Periph_KPP               = XRDC2_MAKE_PERIPH(0, 56 ), /**< KPP */
1514     kXRDC2_Periph_PIT1              = XRDC2_MAKE_PERIPH(0, 54 ), /**< PIT1 */
1515     kXRDC2_Periph_SEMC              = XRDC2_MAKE_PERIPH(0, 53 ), /**< SEMC */
1516     kXRDC2_Periph_FLEXSPI2          = XRDC2_MAKE_PERIPH(0, 52 ), /**< FLEXSPI2 */
1517     kXRDC2_Periph_FLEXSPI1          = XRDC2_MAKE_PERIPH(0, 51 ), /**< FLEXSPI1 */
1518     kXRDC2_Periph_CAN2              = XRDC2_MAKE_PERIPH(0, 50 ), /**< CAN2 */
1519     kXRDC2_Periph_CAN1              = XRDC2_MAKE_PERIPH(0, 49 ), /**< CAN1 */
1520     kXRDC2_Periph_AOI2              = XRDC2_MAKE_PERIPH(0, 47 ), /**< AOI2 */
1521     kXRDC2_Periph_AOI1              = XRDC2_MAKE_PERIPH(0, 46 ), /**< AOI1 */
1522     kXRDC2_Periph_FLEXIO2           = XRDC2_MAKE_PERIPH(0, 44 ), /**< FLEXIO2 */
1523     kXRDC2_Periph_FLEXIO1           = XRDC2_MAKE_PERIPH(0, 43 ), /**< FLEXIO1 */
1524     kXRDC2_Periph_LPUART10          = XRDC2_MAKE_PERIPH(0, 40 ), /**< LPUART10 */
1525     kXRDC2_Periph_LPUART9           = XRDC2_MAKE_PERIPH(0, 39 ), /**< LPUART9 */
1526     kXRDC2_Periph_LPUART8           = XRDC2_MAKE_PERIPH(0, 38 ), /**< LPUART8 */
1527     kXRDC2_Periph_LPUART7           = XRDC2_MAKE_PERIPH(0, 37 ), /**< LPUART7 */
1528     kXRDC2_Periph_LPUART6           = XRDC2_MAKE_PERIPH(0, 36 ), /**< LPUART6 */
1529     kXRDC2_Periph_LPUART5           = XRDC2_MAKE_PERIPH(0, 35 ), /**< LPUART5 */
1530     kXRDC2_Periph_LPUART4           = XRDC2_MAKE_PERIPH(0, 34 ), /**< LPUART4 */
1531     kXRDC2_Periph_LPUART3           = XRDC2_MAKE_PERIPH(0, 33 ), /**< LPUART3 */
1532     kXRDC2_Periph_LPUART2           = XRDC2_MAKE_PERIPH(0, 32 ), /**< LPUART2 */
1533     kXRDC2_Periph_LPUART1           = XRDC2_MAKE_PERIPH(0, 31 ), /**< LPUART1 */
1534     kXRDC2_Periph_DMA_CH_MUX        = XRDC2_MAKE_PERIPH(0, 29 ), /**< DMA_CH_MUX */
1535     kXRDC2_Periph_EDMA              = XRDC2_MAKE_PERIPH(0, 28 ), /**< EDMA */
1536     kXRDC2_Periph_IEE               = XRDC2_MAKE_PERIPH(0, 27 ), /**< IEE */
1537     kXRDC2_Periph_DAC               = XRDC2_MAKE_PERIPH(0, 25 ), /**< DAC */
1538     kXRDC2_Periph_TSC_DIG           = XRDC2_MAKE_PERIPH(0, 23 ), /**< TSC_DIG */
1539     kXRDC2_Periph_ADC2              = XRDC2_MAKE_PERIPH(0, 21 ), /**< ADC2 */
1540     kXRDC2_Periph_ADC1              = XRDC2_MAKE_PERIPH(0, 20 ), /**< ADC1 */
1541     kXRDC2_Periph_ADC_ETC           = XRDC2_MAKE_PERIPH(0, 18 ), /**< ADC_ETC */
1542     kXRDC2_Periph_XBAR3             = XRDC2_MAKE_PERIPH(0, 17 ), /**< XBAR3 */
1543     kXRDC2_Periph_XBAR2             = XRDC2_MAKE_PERIPH(0, 16 ), /**< XBAR2 */
1544     kXRDC2_Periph_XBAR1             = XRDC2_MAKE_PERIPH(0, 15 ), /**< XBAR1 */
1545     kXRDC2_Periph_WDOG3             = XRDC2_MAKE_PERIPH(0, 14 ), /**< WDOG3 */
1546     kXRDC2_Periph_WDOG2             = XRDC2_MAKE_PERIPH(0, 13 ), /**< WDOG2 */
1547     kXRDC2_Periph_WDOG1             = XRDC2_MAKE_PERIPH(0, 12 ), /**< WDOG1 */
1548     kXRDC2_Periph_EWM               = XRDC2_MAKE_PERIPH(0, 11 ), /**< EWM */
1549     kXRDC2_Periph_FLEXRAM           = XRDC2_MAKE_PERIPH(0, 10 ), /**< FLEXRAM */
1550     kXRDC2_Periph_XECC_SEMC         = XRDC2_MAKE_PERIPH(0, 9  ), /**< XECC_SEMC */
1551     kXRDC2_Periph_XECC_FLEXSPI2     = XRDC2_MAKE_PERIPH(0, 8  ), /**< XECC_FLEXSPI2 */
1552     kXRDC2_Periph_XECC_FLEXSPI1     = XRDC2_MAKE_PERIPH(0, 7  ), /**< XECC_FLEXSPI1 */
1553     kXRDC2_Periph_MECC2             = XRDC2_MAKE_PERIPH(0, 6  ), /**< MECC2 */
1554     kXRDC2_Periph_MECC1             = XRDC2_MAKE_PERIPH(0, 5  ), /**< MECC1 */
1555     kXRDC2_Periph_MTR               = XRDC2_MAKE_PERIPH(0, 4  ), /**< MTR */
1556     kXRDC2_Periph_SFA               = XRDC2_MAKE_PERIPH(0, 3  ), /**< SFA */
1557     kXRDC2_Periph_CAAM_DEBUG_3      = XRDC2_MAKE_PERIPH(1, 51 ), /**< CAAM_DEBUG_3 */
1558     kXRDC2_Periph_CAAM_DEBUG_2      = XRDC2_MAKE_PERIPH(1, 50 ), /**< CAAM_DEBUG_2 */
1559     kXRDC2_Periph_CAAM_DEBUG_1      = XRDC2_MAKE_PERIPH(1, 49 ), /**< CAAM_DEBUG_1 */
1560     kXRDC2_Periph_CAAM_DEBUG_0      = XRDC2_MAKE_PERIPH(1, 48 ), /**< CAAM_DEBUG_0 */
1561     kXRDC2_Periph_CAAM_RTIC_3       = XRDC2_MAKE_PERIPH(1, 43 ), /**< CAAM_RTIC_3 */
1562     kXRDC2_Periph_CAAM_RTIC_2       = XRDC2_MAKE_PERIPH(1, 42 ), /**< CAAM_RTIC_2 */
1563     kXRDC2_Periph_CAAM_RTIC_1       = XRDC2_MAKE_PERIPH(1, 41 ), /**< CAAM_RTIC_1 */
1564     kXRDC2_Periph_CAAM_RTIC_0       = XRDC2_MAKE_PERIPH(1, 40 ), /**< CAAM_RTIC_0 */
1565     kXRDC2_Periph_CAAM_JR3_3        = XRDC2_MAKE_PERIPH(1, 35 ), /**< CAAM_JR3_3 */
1566     kXRDC2_Periph_CAAM_JR3_2        = XRDC2_MAKE_PERIPH(1, 34 ), /**< CAAM_JR3_2 */
1567     kXRDC2_Periph_CAAM_JR3_1        = XRDC2_MAKE_PERIPH(1, 33 ), /**< CAAM_JR3_1 */
1568     kXRDC2_Periph_CAAM_JR3_0        = XRDC2_MAKE_PERIPH(1, 32 ), /**< CAAM_JR3_0 */
1569     kXRDC2_Periph_CAAM_JR2_3        = XRDC2_MAKE_PERIPH(1, 31 ), /**< CAAM_JR2_3 */
1570     kXRDC2_Periph_CAAM_JR2_2        = XRDC2_MAKE_PERIPH(1, 30 ), /**< CAAM_JR2_2 */
1571     kXRDC2_Periph_CAAM_JR2_1        = XRDC2_MAKE_PERIPH(1, 29 ), /**< CAAM_JR2_1 */
1572     kXRDC2_Periph_CAAM_JR2_0        = XRDC2_MAKE_PERIPH(1, 28 ), /**< CAAM_JR2_0 */
1573     kXRDC2_Periph_CAAM_JR1_3        = XRDC2_MAKE_PERIPH(1, 27 ), /**< CAAM_JR1_3 */
1574     kXRDC2_Periph_CAAM_JR1_2        = XRDC2_MAKE_PERIPH(1, 26 ), /**< CAAM_JR1_2 */
1575     kXRDC2_Periph_CAAM_JR1_1        = XRDC2_MAKE_PERIPH(1, 25 ), /**< CAAM_JR1_1 */
1576     kXRDC2_Periph_CAAM_JR1_0        = XRDC2_MAKE_PERIPH(1, 24 ), /**< CAAM_JR1_0 */
1577     kXRDC2_Periph_CAAM_JR0_3        = XRDC2_MAKE_PERIPH(1, 23 ), /**< CAAM_JR0_3 */
1578     kXRDC2_Periph_CAAM_JR0_2        = XRDC2_MAKE_PERIPH(1, 22 ), /**< CAAM_JR0_2 */
1579     kXRDC2_Periph_CAAM_JR0_1        = XRDC2_MAKE_PERIPH(1, 21 ), /**< CAAM_JR0_1 */
1580     kXRDC2_Periph_CAAM_JR0_0        = XRDC2_MAKE_PERIPH(1, 20 ), /**< CAAM_JR0_0 */
1581     kXRDC2_Periph_CAAM_GENERAL_3    = XRDC2_MAKE_PERIPH(1, 19 ), /**< CAAM_GENERAL_3 */
1582     kXRDC2_Periph_CAAM_GENERAL_2    = XRDC2_MAKE_PERIPH(1, 18 ), /**< CAAM_GENERAL_2 */
1583     kXRDC2_Periph_CAAM_GENERAL_1    = XRDC2_MAKE_PERIPH(1, 17 ), /**< CAAM_GENERAL_1 */
1584     kXRDC2_Periph_CAAM_GENERAL_0    = XRDC2_MAKE_PERIPH(1, 16 ), /**< CAAM_GENERAL_0 */
1585     kXRDC2_Periph_ENET_QOS          = XRDC2_MAKE_PERIPH(1, 15 ), /**< ENET_QOS */
1586     kXRDC2_Periph_USBPHY2           = XRDC2_MAKE_PERIPH(1, 14 ), /**< USBPHY2 */
1587     kXRDC2_Periph_USBPHY1           = XRDC2_MAKE_PERIPH(1, 13 ), /**< USBPHY1 */
1588     kXRDC2_Periph_USB_OTG           = XRDC2_MAKE_PERIPH(1, 12 ), /**< USB_OTG */
1589     kXRDC2_Periph_USB_OTG2          = XRDC2_MAKE_PERIPH(1, 11 ), /**< USB_OTG2 */
1590     kXRDC2_Periph_USB_PL301         = XRDC2_MAKE_PERIPH(1, 10 ), /**< USB_PL301 */
1591     kXRDC2_Periph_ENET              = XRDC2_MAKE_PERIPH(1, 9  ), /**< ENET */
1592     kXRDC2_Periph_ENET_1G           = XRDC2_MAKE_PERIPH(1, 8  ), /**< ENET_1G */
1593     kXRDC2_Periph_USDHC2            = XRDC2_MAKE_PERIPH(1, 7  ), /**< USDHC2 */
1594     kXRDC2_Periph_USDHC1            = XRDC2_MAKE_PERIPH(1, 6  ), /**< USDHC1 */
1595     kXRDC2_Periph_ASRC              = XRDC2_MAKE_PERIPH(1, 5  ), /**< ASRC */
1596     kXRDC2_Periph_SAI3              = XRDC2_MAKE_PERIPH(1, 3  ), /**< SAI3 */
1597     kXRDC2_Periph_SAI2              = XRDC2_MAKE_PERIPH(1, 2  ), /**< SAI2 */
1598     kXRDC2_Periph_SAI1              = XRDC2_MAKE_PERIPH(1, 1  ), /**< SAI1 */
1599     kXRDC2_Periph_SPDIF             = XRDC2_MAKE_PERIPH(1, 0  ), /**< SPDIF */
1600     kXRDC2_Periph_VIDEO_MUX         = XRDC2_MAKE_PERIPH(2, 6  ), /**< VIDEO_MUX */
1601     kXRDC2_Periph_PXP               = XRDC2_MAKE_PERIPH(2, 5  ), /**< PXP */
1602     kXRDC2_Periph_MIPI_CSI          = XRDC2_MAKE_PERIPH(2, 4  ), /**< MIPI_CSI */
1603     kXRDC2_Periph_MIPI_DSI          = XRDC2_MAKE_PERIPH(2, 3  ), /**< MIPI_DSI */
1604     kXRDC2_Periph_LCDIFV2           = XRDC2_MAKE_PERIPH(2, 2  ), /**< LCDIFV2 */
1605     kXRDC2_Periph_LCDIF             = XRDC2_MAKE_PERIPH(2, 1  ), /**< LCDIF */
1606     kXRDC2_Periph_CSI               = XRDC2_MAKE_PERIPH(2, 0  ), /**< CSI */
1607     kXRDC2_Periph_XRDC2_MGR_M7_3    = XRDC2_MAKE_PERIPH(3, 59 ), /**< XRDC2_MGR_M7_3 */
1608     kXRDC2_Periph_XRDC2_MGR_M7_2    = XRDC2_MAKE_PERIPH(3, 58 ), /**< XRDC2_MGR_M7_2 */
1609     kXRDC2_Periph_XRDC2_MGR_M7_1    = XRDC2_MAKE_PERIPH(3, 57 ), /**< XRDC2_MGR_M7_1 */
1610     kXRDC2_Periph_XRDC2_MGR_M7_0    = XRDC2_MAKE_PERIPH(3, 56 ), /**< XRDC2_MGR_M7_0 */
1611     kXRDC2_Periph_XRDC2_MGR_M4_3    = XRDC2_MAKE_PERIPH(3, 55 ), /**< XRDC2_MGR_M4_3 */
1612     kXRDC2_Periph_XRDC2_MGR_M4_2    = XRDC2_MAKE_PERIPH(3, 54 ), /**< XRDC2_MGR_M4_2 */
1613     kXRDC2_Periph_XRDC2_MGR_M4_1    = XRDC2_MAKE_PERIPH(3, 53 ), /**< XRDC2_MGR_M4_1 */
1614     kXRDC2_Periph_XRDC2_MGR_M4_0    = XRDC2_MAKE_PERIPH(3, 52 ), /**< XRDC2_MGR_M4_0 */
1615     kXRDC2_Periph_SEMA2             = XRDC2_MAKE_PERIPH(3, 51 ), /**< SEMA2 */
1616     kXRDC2_Periph_SEMA_HS           = XRDC2_MAKE_PERIPH(3, 50 ), /**< SEMA_HS */
1617     kXRDC2_Periph_CCM_1             = XRDC2_MAKE_PERIPH(3, 49 ), /**< CCM_1 */
1618     kXRDC2_Periph_CCM_0             = XRDC2_MAKE_PERIPH(3, 48 ), /**< CCM_0 */
1619     kXRDC2_Periph_SSARC_LP          = XRDC2_MAKE_PERIPH(3, 46 ), /**< SSARC_LP */
1620     kXRDC2_Periph_SSARC_HP          = XRDC2_MAKE_PERIPH(3, 45 ), /**< SSARC_HP */
1621     kXRDC2_Periph_PIT2              = XRDC2_MAKE_PERIPH(3, 44 ), /**< PIT2 */
1622     kXRDC2_Periph_OCOTP_CTRL_WRAPPER = XRDC2_MAKE_PERIPH(3, 43 ), /**< OCOTP_CTRL_WRAPPER */
1623     kXRDC2_Periph_DCDC              = XRDC2_MAKE_PERIPH(3, 42 ), /**< DCDC */
1624     kXRDC2_Periph_ROMCP             = XRDC2_MAKE_PERIPH(3, 41 ), /**< ROMCP */
1625     kXRDC2_Periph_GPIO13            = XRDC2_MAKE_PERIPH(3, 40 ), /**< GPIO13 */
1626     kXRDC2_Periph_SNVS_SRAM         = XRDC2_MAKE_PERIPH(3, 39 ), /**< SNVS_SRAM */
1627     kXRDC2_Periph_IOMUXC_SNVS_GPR   = XRDC2_MAKE_PERIPH(3, 38 ), /**< IOMUXC_SNVS_GPR */
1628     kXRDC2_Periph_IOMUXC_SNVS       = XRDC2_MAKE_PERIPH(3, 37 ), /**< IOMUXC_SNVS */
1629     kXRDC2_Periph_SNVS_HP_WRAPPER   = XRDC2_MAKE_PERIPH(3, 36 ), /**< SNVS_HP_WRAPPER */
1630     kXRDC2_Periph_PGMC              = XRDC2_MAKE_PERIPH(3, 34 ), /**< PGMC */
1631     kXRDC2_Periph_ANATOP            = XRDC2_MAKE_PERIPH(3, 33 ), /**< ANATOP */
1632     kXRDC2_Periph_KEY_MANAGER       = XRDC2_MAKE_PERIPH(3, 32 ), /**< KEY_MANAGER */
1633     kXRDC2_Periph_RDC               = XRDC2_MAKE_PERIPH(3, 30 ), /**< RDC */
1634     kXRDC2_Periph_GPIO12            = XRDC2_MAKE_PERIPH(3, 28 ), /**< GPIO12 */
1635     kXRDC2_Periph_GPIO11            = XRDC2_MAKE_PERIPH(3, 27 ), /**< GPIO11 */
1636     kXRDC2_Periph_GPIO10            = XRDC2_MAKE_PERIPH(3, 26 ), /**< GPIO10 */
1637     kXRDC2_Periph_GPIO9             = XRDC2_MAKE_PERIPH(3, 25 ), /**< GPIO9 */
1638     kXRDC2_Periph_GPIO8             = XRDC2_MAKE_PERIPH(3, 24 ), /**< GPIO8 */
1639     kXRDC2_Periph_GPIO7             = XRDC2_MAKE_PERIPH(3, 23 ), /**< GPIO7 */
1640     kXRDC2_Periph_MU_B              = XRDC2_MAKE_PERIPH(3, 19 ), /**< MU_B */
1641     kXRDC2_Periph_MU_A              = XRDC2_MAKE_PERIPH(3, 18 ), /**< MU_A */
1642     kXRDC2_Periph_SEMA1             = XRDC2_MAKE_PERIPH(3, 17 ), /**< SEMA1 */
1643     kXRDC2_Periph_SAI4              = XRDC2_MAKE_PERIPH(3, 16 ), /**< SAI4 */
1644     kXRDC2_Periph_CAN3              = XRDC2_MAKE_PERIPH(3, 15 ), /**< CAN3 */
1645     kXRDC2_Periph_LPI2C6            = XRDC2_MAKE_PERIPH(3, 14 ), /**< LPI2C6 */
1646     kXRDC2_Periph_LPI2C5            = XRDC2_MAKE_PERIPH(3, 13 ), /**< LPI2C5 */
1647     kXRDC2_Periph_LPSPI6            = XRDC2_MAKE_PERIPH(3, 12 ), /**< LPSPI6 */
1648     kXRDC2_Periph_LPSPI5            = XRDC2_MAKE_PERIPH(3, 11 ), /**< LPSPI5 */
1649     kXRDC2_Periph_LPUART12          = XRDC2_MAKE_PERIPH(3, 10 ), /**< LPUART12 */
1650     kXRDC2_Periph_LPUART11          = XRDC2_MAKE_PERIPH(3, 9  ), /**< LPUART11 */
1651     kXRDC2_Periph_MIC               = XRDC2_MAKE_PERIPH(3, 8  ), /**< MIC */
1652     kXRDC2_Periph_DMA_CH_MUX_LPSR   = XRDC2_MAKE_PERIPH(3, 6  ), /**< DMA_CH_MUX_LPSR */
1653     kXRDC2_Periph_EDMA_LPSR         = XRDC2_MAKE_PERIPH(3, 5  ), /**< EDMA_LPSR */
1654     kXRDC2_Periph_WDOG4             = XRDC2_MAKE_PERIPH(3, 4  ), /**< WDOG4 */
1655     kXRDC2_Periph_IOMUXC_LPSR_GPR   = XRDC2_MAKE_PERIPH(3, 3  ), /**< IOMUXC_LPSR_GPR */
1656     kXRDC2_Periph_IOMUXC_LPSR       = XRDC2_MAKE_PERIPH(3, 2  ), /**< IOMUXC_LPSR */
1657     kXRDC2_Periph_SRC               = XRDC2_MAKE_PERIPH(3, 1  ), /**< SRC */
1658     kXRDC2_Periph_GPC               = XRDC2_MAKE_PERIPH(3, 0  ), /**< GPC */
1659     kXRDC2_Periph_GPU               = XRDC2_MAKE_PERIPH(4, 0  ), /**< GPU */
1660 } xrdc2_periph_t;
1661 
1662 /* @} */
1663 
1664 /*!
1665  * @addtogroup asrc_clock_source
1666  * @{
1667  */
1668 
1669 /*******************************************************************************
1670  * Definitions
1671  ******************************************************************************/
1672 
1673 /*!
1674  * @brief The ASRC clock source
1675  */
1676 
1677 typedef enum _asrc_clock_source
1678 {
1679     kASRC_ClockSourceNotAvalible    = -1,          /**< not avalible */
1680     kASRC_ClockSourceBitClock0_SAI1_TX = 0U,       /**< SAI1 TX */
1681     kASRC_ClockSourceBitClock1_SAI1_RX = 1U,       /**< SAI1 RX */
1682     kASRC_ClockSourceBitClock2_SAI2_TX = 2U,       /**< SAI2 TX */
1683     kASRC_ClockSourceBitClock3_SAI2_RX = 3U,       /**< SAI2 RX */
1684     kASRC_ClockSourceBitClock4_SAI3_TX = 4U,       /**< SAI3 TX */
1685     kASRC_ClockSourceBitClock5_SAI3_RX = 5U,       /**< SAI3 RX */
1686     kASRC_ClockSourceBitClock6_SAI4_TX = 6U,       /**< SAI4 TX */
1687     kASRC_ClockSourceBitClock7_SAI4_RX = 7U,       /**< SAI4 RX */
1688     kASRC_ClockSourceBitClock8_SPDIF_TX = 8U,      /**< SPDIF TX */
1689     kASRC_ClockSourceBitClock9_SPDIF_RX = 9U,      /**< SPDIF RX */
1690     kASRC_ClockSourceBitClocka_SAI2_CLOCK_ROOT = 10U, /**< SAI2 CLOCK ROOT */
1691     kASRC_ClockSourceBitClockb_SAI3_CLOCK_ROOT = 11U, /**< SAI3 CLOCK ROOT */
1692     kASRC_ClockSourceBitClockc_SAI4_CLOCK_ROOT = 12U, /**< SAI4 CLOCK ROOT */
1693     kASRC_ClockSourceBitClockd_MIC_CLOCK_ROOT = 13U, /**< MIC CLOCK ROOT */
1694     kASRC_ClockSourceBitClocke_MQS_CLOCK_ROOT = 14U, /**< MQS CLOCK ROOT */
1695 } asrc_clock_source_t;
1696 
1697 /*!
1698  * @addtogroup edma_request
1699  * @{
1700  */
1701 
1702 /*******************************************************************************
1703  * Definitions
1704  ******************************************************************************/
1705 
1706 /*!
1707  * @brief Structure for the DMA hardware request
1708  *
1709  * Defines the structure for the DMA hardware request collections. The user can configure the
1710  * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
1711  * of the hardware request varies according  to the to SoC.
1712  */
1713 typedef enum _dma_request_source
1714 {
1715     kDmaRequestMuxFlexIO1Request2Request3 = 1|0x100U, /**< FlexIO1 Request2 and Request3 */
1716     kDmaRequestMuxFlexIO1Request4Request5 = 2|0x100U, /**< FlexIO1 Request4 and Request5 */
1717     kDmaRequestMuxFlexIO1Request6Request7 = 3|0x100U, /**< FlexIO1 Request6 and Request7 */
1718     kDmaRequestMuxFlexIO2Request0Request1 = 4|0x100U, /**< FlexIO2 Request0 and Request1 */
1719     kDmaRequestMuxFlexIO2Request2Request3 = 5|0x100U, /**< FlexIO2 Request2 and Request3 */
1720     kDmaRequestMuxFlexIO2Request4Request5 = 6|0x100U, /**< FlexIO2 Request4 and Request5 */
1721     kDmaRequestMuxFlexIO2Request6Request7 = 7|0x100U, /**< FlexIO2 Request6 and Request7 */
1722     kDmaRequestMuxLPUART1Tx         = 8|0x100U,    /**< LPUART1 Transmit */
1723     kDmaRequestMuxLPUART1Rx         = 9|0x100U,    /**< LPUART1 Receive */
1724     kDmaRequestMuxLPUART2Tx         = 10|0x100U,   /**< LPUART2 Transmit */
1725     kDmaRequestMuxLPUART2Rx         = 11|0x100U,   /**< LPUART2 Receive */
1726     kDmaRequestMuxLPUART3Tx         = 12|0x100U,   /**< LPUART3 Transmit */
1727     kDmaRequestMuxLPUART3Rx         = 13|0x100U,   /**< LPUART3 Receive */
1728     kDmaRequestMuxLPUART4Tx         = 14|0x100U,   /**< LPUART4 Transmit */
1729     kDmaRequestMuxLPUART4Rx         = 15|0x100U,   /**< LPUART4 Receive */
1730     kDmaRequestMuxLPUART5Tx         = 16|0x100U,   /**< LPUART5 Transmit */
1731     kDmaRequestMuxLPUART5Rx         = 17|0x100U,   /**< LPUART5 Receive */
1732     kDmaRequestMuxLPUART6Tx         = 18|0x100U,   /**< LPUART6 Transmit */
1733     kDmaRequestMuxLPUART6Rx         = 19|0x100U,   /**< LPUART6 Receive */
1734     kDmaRequestMuxLPUART7Tx         = 20|0x100U,   /**< LPUART7 Transmit */
1735     kDmaRequestMuxLPUART7Rx         = 21|0x100U,   /**< LPUART7 Receive */
1736     kDmaRequestMuxLPUART8Tx         = 22|0x100U,   /**< LPUART8 Transmit */
1737     kDmaRequestMuxLPUART8Rx         = 23|0x100U,   /**< LPUART8 Receive */
1738     kDmaRequestMuxLPUART9Tx         = 24|0x100U,   /**< LPUART9 Transmit */
1739     kDmaRequestMuxLPUART9Rx         = 25|0x100U,   /**< LPUART9 Receive */
1740     kDmaRequestMuxLPUART10Tx        = 26|0x100U,   /**< LPUART10 Transmit */
1741     kDmaRequestMuxLPUART10Rx        = 27|0x100U,   /**< LPUART10 Receive */
1742     kDmaRequestMuxLPUART11Tx        = 28|0x100U,   /**< LPUART11 Transmit */
1743     kDmaRequestMuxLPUART11Rx        = 29|0x100U,   /**< LPUART11 Receive */
1744     kDmaRequestMuxLPUART12Tx        = 30|0x100U,   /**< LPUART12 Transmit */
1745     kDmaRequestMuxLPUART12Rx        = 31|0x100U,   /**< LPUART12 Receive */
1746     kDmaRequestMuxCSI               = 32|0x100U,   /**< CSI */
1747     kDmaRequestMuxPxp               = 33|0x100U,   /**< PXP */
1748     kDmaRequestMuxeLCDIF            = 34|0x100U,   /**< eLCDIF */
1749     kDmaRequestMuxLCDIFv2           = 35|0x100U,   /**< LCDIFv2 */
1750     kDmaRequestMuxLPSPI1Rx          = 36|0x100U,   /**< LPSPI1 Receive */
1751     kDmaRequestMuxLPSPI1Tx          = 37|0x100U,   /**< LPSPI1 Transmit */
1752     kDmaRequestMuxLPSPI2Rx          = 38|0x100U,   /**< LPSPI2 Receive */
1753     kDmaRequestMuxLPSPI2Tx          = 39|0x100U,   /**< LPSPI2 Transmit */
1754     kDmaRequestMuxLPSPI3Rx          = 40|0x100U,   /**< LPSPI3 Receive */
1755     kDmaRequestMuxLPSPI3Tx          = 41|0x100U,   /**< LPSPI3 Transmit */
1756     kDmaRequestMuxLPSPI4Rx          = 42|0x100U,   /**< LPSPI4 Receive */
1757     kDmaRequestMuxLPSPI4Tx          = 43|0x100U,   /**< LPSPI4 Transmit */
1758     kDmaRequestMuxLPSPI5Rx          = 44|0x100U,   /**< LPSPI5 Receive */
1759     kDmaRequestMuxLPSPI5Tx          = 45|0x100U,   /**< LPSPI5 Transmit */
1760     kDmaRequestMuxLPSPI6Rx          = 46|0x100U,   /**< LPSPI6 Receive */
1761     kDmaRequestMuxLPSPI6Tx          = 47|0x100U,   /**< LPSPI6 Transmit */
1762     kDmaRequestMuxLPI2C1            = 48|0x100U,   /**< LPI2C1 */
1763     kDmaRequestMuxLPI2C2            = 49|0x100U,   /**< LPI2C2 */
1764     kDmaRequestMuxLPI2C3            = 50|0x100U,   /**< LPI2C3 */
1765     kDmaRequestMuxLPI2C4            = 51|0x100U,   /**< LPI2C4 */
1766     kDmaRequestMuxLPI2C5            = 52|0x100U,   /**< LPI2C5 */
1767     kDmaRequestMuxLPI2C6            = 53|0x100U,   /**< LPI2C6 */
1768     kDmaRequestMuxSai1Rx            = 54|0x100U,   /**< SAI1 Receive */
1769     kDmaRequestMuxSai1Tx            = 55|0x100U,   /**< SAI1 Transmit */
1770     kDmaRequestMuxSai2Rx            = 56|0x100U,   /**< SAI2 Receive */
1771     kDmaRequestMuxSai2Tx            = 57|0x100U,   /**< SAI2 Transmit */
1772     kDmaRequestMuxSai3Rx            = 58|0x100U,   /**< SAI3 Receive */
1773     kDmaRequestMuxSai3Tx            = 59|0x100U,   /**< SAI3 Transmit */
1774     kDmaRequestMuxSai4Rx            = 60|0x100U,   /**< SAI4 Receive */
1775     kDmaRequestMuxSai4Tx            = 61|0x100U,   /**< SAI4 Transmit */
1776     kDmaRequestMuxSpdifRx           = 62|0x100U,   /**< SPDIF Receive */
1777     kDmaRequestMuxSpdifTx           = 63|0x100U,   /**< SPDIF Transmit */
1778     kDmaRequestMuxADC_ETC           = 64|0x100U,   /**< ADC_ETC */
1779     kDmaRequestMuxFlexIO1Request0Request1 = 65|0x100U, /**< FlexIO1 Request0 and Request1 */
1780     kDmaRequestMuxADC1              = 66|0x100U,   /**< ADC1 */
1781     kDmaRequestMuxADC2              = 67|0x100U,   /**< ADC2 */
1782     kDmaRequestMuxACMP1             = 69|0x100U,   /**< ACMP1 */
1783     kDmaRequestMuxACMP2             = 70|0x100U,   /**< ACMP2 */
1784     kDmaRequestMuxACMP3             = 71|0x100U,   /**< ACMP3 */
1785     kDmaRequestMuxACMP4             = 72|0x100U,   /**< ACMP4 */
1786     kDmaRequestMuxFlexSPI1Rx        = 77|0x100U,   /**< FlexSPI1 Receive */
1787     kDmaRequestMuxFlexSPI1Tx        = 78|0x100U,   /**< FlexSPI1 Transmit */
1788     kDmaRequestMuxFlexSPI2Rx        = 79|0x100U,   /**< FlexSPI2 Receive */
1789     kDmaRequestMuxFlexSPI2Tx        = 80|0x100U,   /**< FlexSPI2 Transmit */
1790     kDmaRequestMuxXBAR1Request0     = 81|0x100U,   /**< XBAR1 Request 0 */
1791     kDmaRequestMuxXBAR1Request1     = 82|0x100U,   /**< XBAR1 Request 1 */
1792     kDmaRequestMuxXBAR1Request2     = 83|0x100U,   /**< XBAR1 Request 2 */
1793     kDmaRequestMuxXBAR1Request3     = 84|0x100U,   /**< XBAR1 Request 3 */
1794     kDmaRequestMuxFlexPWM1CaptureSub0 = 85|0x100U, /**< FlexPWM1 Capture sub-module0 */
1795     kDmaRequestMuxFlexPWM1CaptureSub1 = 86|0x100U, /**< FlexPWM1 Capture sub-module1 */
1796     kDmaRequestMuxFlexPWM1CaptureSub2 = 87|0x100U, /**< FlexPWM1 Capture sub-module2 */
1797     kDmaRequestMuxFlexPWM1CaptureSub3 = 88|0x100U, /**< FlexPWM1 Capture sub-module3 */
1798     kDmaRequestMuxFlexPWM1ValueSub0 = 89|0x100U,   /**< FlexPWM1 Value sub-module 0 */
1799     kDmaRequestMuxFlexPWM1ValueSub1 = 90|0x100U,   /**< FlexPWM1 Value sub-module 1 */
1800     kDmaRequestMuxFlexPWM1ValueSub2 = 91|0x100U,   /**< FlexPWM1 Value sub-module 2 */
1801     kDmaRequestMuxFlexPWM1ValueSub3 = 92|0x100U,   /**< FlexPWM1 Value sub-module 3 */
1802     kDmaRequestMuxFlexPWM2CaptureSub0 = 93|0x100U, /**< FlexPWM2 Capture sub-module0 */
1803     kDmaRequestMuxFlexPWM2CaptureSub1 = 94|0x100U, /**< FlexPWM2 Capture sub-module1 */
1804     kDmaRequestMuxFlexPWM2CaptureSub2 = 95|0x100U, /**< FlexPWM2 Capture sub-module2 */
1805     kDmaRequestMuxFlexPWM2CaptureSub3 = 96|0x100U, /**< FlexPWM2 Capture sub-module3 */
1806     kDmaRequestMuxFlexPWM2ValueSub0 = 97|0x100U,   /**< FlexPWM2 Value sub-module 0 */
1807     kDmaRequestMuxFlexPWM2ValueSub1 = 98|0x100U,   /**< FlexPWM2 Value sub-module 1 */
1808     kDmaRequestMuxFlexPWM2ValueSub2 = 99|0x100U,   /**< FlexPWM2 Value sub-module 2 */
1809     kDmaRequestMuxFlexPWM2ValueSub3 = 100|0x100U,  /**< FlexPWM2 Value sub-module 3 */
1810     kDmaRequestMuxFlexPWM3CaptureSub0 = 101|0x100U, /**< FlexPWM3 Capture sub-module0 */
1811     kDmaRequestMuxFlexPWM3CaptureSub1 = 102|0x100U, /**< FlexPWM3 Capture sub-module1 */
1812     kDmaRequestMuxFlexPWM3CaptureSub2 = 103|0x100U, /**< FlexPWM3 Capture sub-module2 */
1813     kDmaRequestMuxFlexPWM3CaptureSub3 = 104|0x100U, /**< FlexPWM3 Capture sub-module3 */
1814     kDmaRequestMuxFlexPWM3ValueSub0 = 105|0x100U,  /**< FlexPWM3 Value sub-module 0 */
1815     kDmaRequestMuxFlexPWM3ValueSub1 = 106|0x100U,  /**< FlexPWM3 Value sub-module 1 */
1816     kDmaRequestMuxFlexPWM3ValueSub2 = 107|0x100U,  /**< FlexPWM3 Value sub-module 2 */
1817     kDmaRequestMuxFlexPWM3ValueSub3 = 108|0x100U,  /**< FlexPWM3 Value sub-module 3 */
1818     kDmaRequestMuxFlexPWM4CaptureSub0 = 109|0x100U, /**< FlexPWM4 Capture sub-module0 */
1819     kDmaRequestMuxFlexPWM4CaptureSub1 = 110|0x100U, /**< FlexPWM4 Capture sub-module1 */
1820     kDmaRequestMuxFlexPWM4CaptureSub2 = 111|0x100U, /**< FlexPWM4 Capture sub-module2 */
1821     kDmaRequestMuxFlexPWM4CaptureSub3 = 112|0x100U, /**< FlexPWM4 Capture sub-module3 */
1822     kDmaRequestMuxFlexPWM4ValueSub0 = 113|0x100U,  /**< FlexPWM4 Value sub-module 0 */
1823     kDmaRequestMuxFlexPWM4ValueSub1 = 114|0x100U,  /**< FlexPWM4 Value sub-module 1 */
1824     kDmaRequestMuxFlexPWM4ValueSub2 = 115|0x100U,  /**< FlexPWM4 Value sub-module 2 */
1825     kDmaRequestMuxFlexPWM4ValueSub3 = 116|0x100U,  /**< FlexPWM4 Value sub-module 3 */
1826     kDmaRequestMuxQTIMER1CaptTimer0 = 133|0x100U,  /**< TMR1 Capture timer 0 */
1827     kDmaRequestMuxQTIMER1CaptTimer1 = 134|0x100U,  /**< TMR1 Capture timer 1 */
1828     kDmaRequestMuxQTIMER1CaptTimer2 = 135|0x100U,  /**< TMR1 Capture timer 2 */
1829     kDmaRequestMuxQTIMER1CaptTimer3 = 136|0x100U,  /**< TMR1 Capture timer 3 */
1830     kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 137|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */
1831     kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 138|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */
1832     kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 139|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */
1833     kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 140|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */
1834     kDmaRequestMuxQTIMER2CaptTimer0 = 141|0x100U,  /**< TMR2 Capture timer 0 */
1835     kDmaRequestMuxQTIMER2CaptTimer1 = 142|0x100U,  /**< TMR2 Capture timer 1 */
1836     kDmaRequestMuxQTIMER2CaptTimer2 = 143|0x100U,  /**< TMR2 Capture timer 2 */
1837     kDmaRequestMuxQTIMER2CaptTimer3 = 144|0x100U,  /**< TMR2 Capture timer 3 */
1838     kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 145|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */
1839     kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 146|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */
1840     kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 147|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */
1841     kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 148|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */
1842     kDmaRequestMuxQTIMER3CaptTimer0 = 149|0x100U,  /**< TMR3 Capture timer 0 */
1843     kDmaRequestMuxQTIMER3CaptTimer1 = 150|0x100U,  /**< TMR3 Capture timer 1 */
1844     kDmaRequestMuxQTIMER3CaptTimer2 = 151|0x100U,  /**< TMR3 Capture timer 2 */
1845     kDmaRequestMuxQTIMER3CaptTimer3 = 152|0x100U,  /**< TMR3 Capture timer 3 */
1846     kDmaRequestMuxQTIMER3Cmpld1Timer0Cmpld2Timer1 = 153|0x100U, /**< TMR3 cmpld1 in timer 0 or cmpld2 in timer 1 */
1847     kDmaRequestMuxQTIMER3Cmpld1Timer1Cmpld2Timer0 = 154|0x100U, /**< TMR3 cmpld1 in timer 1 or cmpld2 in timer 0 */
1848     kDmaRequestMuxQTIMER3Cmpld1Timer2Cmpld2Timer3 = 155|0x100U, /**< TMR3 cmpld1 in timer 2 or cmpld2 in timer 3 */
1849     kDmaRequestMuxQTIMER3Cmpld1Timer3Cmpld2Timer2 = 156|0x100U, /**< TMR3 cmpld1 in timer 3 or cmpld2 in timer 2 */
1850     kDmaRequestMuxQTIMER4CaptTimer0 = 157|0x100U,  /**< TMR4 Capture timer 0 */
1851     kDmaRequestMuxQTIMER4CaptTimer1 = 158|0x100U,  /**< TMR4 Capture timer 1 */
1852     kDmaRequestMuxQTIMER4CaptTimer2 = 159|0x100U,  /**< TMR4 Capture timer 2 */
1853     kDmaRequestMuxQTIMER4CaptTimer3 = 160|0x100U,  /**< TMR4 Capture timer 3 */
1854     kDmaRequestMuxQTIMER4Cmpld1Timer0Cmpld2Timer1 = 161|0x100U, /**< TMR4 cmpld1 in timer 0 or cmpld2 in timer 1 */
1855     kDmaRequestMuxQTIMER4Cmpld1Timer1Cmpld2Timer0 = 162|0x100U, /**< TMR4 cmpld1 in timer 1 or cmpld2 in timer 0 */
1856     kDmaRequestMuxQTIMER4Cmpld1Timer2Cmpld2Timer3 = 163|0x100U, /**< TMR4 cmpld1 in timer 2 or cmpld2 in timer 3 */
1857     kDmaRequestMuxQTIMER4Cmpld1Timer3Cmpld2Timer2 = 164|0x100U, /**< TMR4 cmpld1 in timer 3 or cmpld2 in timer 2 */
1858     kDmaRequestMuxPdm               = 181|0x100U,  /**< PDM */
1859     kDmaRequestMuxEnetTimer0        = 182|0x100U,  /**< ENET Timer0 */
1860     kDmaRequestMuxEnetTimer1        = 183|0x100U,  /**< ENET Timer1 */
1861     kDmaRequestMuxEnet1GTimer0      = 184|0x100U,  /**< ENET 1G Timer0 */
1862     kDmaRequestMuxEnet1GTimer1      = 185|0x100U,  /**< ENET 1G Timer1 */
1863     kDmaRequestMuxCAN1              = 186|0x100U,  /**< CAN1 */
1864     kDmaRequestMuxCAN2              = 187|0x100U,  /**< CAN2 */
1865     kDmaRequestMuxCAN3              = 188|0x100U,  /**< CAN3 */
1866     kDmaRequestMuxDAC               = 189|0x100U,  /**< DAC */
1867     kDmaRequestMuxASRCRequest1      = 191|0x100U,  /**< ASRC request 1 pair A input request */
1868     kDmaRequestMuxASRCRequest2      = 192|0x100U,  /**< ASRC request 2 pair B input request */
1869     kDmaRequestMuxASRCRequest3      = 193|0x100U,  /**< ASRC request 3 pair C input request */
1870     kDmaRequestMuxASRCRequest4      = 194|0x100U,  /**< ASRC request 4 pair A output request */
1871     kDmaRequestMuxASRCRequest5      = 195|0x100U,  /**< ASRC request 5 pair B output request */
1872     kDmaRequestMuxASRCRequest6      = 196|0x100U,  /**< ASRC request 6 pair C output request */
1873     kDmaRequestMuxEmvsim1Tx         = 197|0x100U,  /**< Emvsim1 Transmit */
1874     kDmaRequestMuxEmvsim1Rx         = 198|0x100U,  /**< Emvsim1 Receive */
1875     kDmaRequestMuxEmvsim2Tx         = 199|0x100U,  /**< Emvsim2 Transmit */
1876     kDmaRequestMuxEmvsim2Rx         = 200|0x100U,  /**< Emvsim2 Receive */
1877     kDmaRequestMuxEnetQosTimer0     = 201|0x100U,  /**< ENET_QOS Timer0 */
1878     kDmaRequestMuxEnetQosTimer1     = 202|0x100U,  /**< ENET_QOS Timer1 */
1879 } dma_request_source_t;
1880 
1881 /* @} */
1882 
1883 /*!
1884  * @addtogroup iomuxc_pads
1885  * @{ */
1886 
1887 /*******************************************************************************
1888  * Definitions
1889 *******************************************************************************/
1890 
1891 /*!
1892  * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
1893  *
1894  * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
1895  */
1896 typedef enum _iomuxc_sw_mux_ctl_pad
1897 {
1898     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 = 0U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1899     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 = 1U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1900     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 = 2U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1901     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 = 3U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1902     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 = 4U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1903     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 = 5U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1904     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 = 6U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1905     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 = 7U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1906     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 = 8U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1907     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 = 9U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1908     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 = 10U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1909     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 = 11U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1910     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 = 12U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1911     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 = 13U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1912     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 = 14U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1913     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 = 15U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1914     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 = 16U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1915     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 = 17U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1916     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 = 18U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1917     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 = 19U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1918     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 = 20U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1919     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 = 21U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1920     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 = 22U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1921     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 = 23U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1922     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 = 24U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1923     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 = 25U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1924     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 = 26U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1925     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 = 27U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1926     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 = 28U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1927     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 = 29U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1928     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 = 30U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1929     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 = 31U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1930     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 = 32U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1931     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 = 33U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1932     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 = 34U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1933     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 = 35U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1934     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 = 36U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1935     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 = 37U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1936     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 = 38U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1937     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 = 39U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1938     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 = 40U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1939     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 = 41U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1940     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 = 42U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1941     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 = 43U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1942     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 = 44U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1943     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 = 45U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1944     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 = 46U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1945     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 = 47U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1946     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 = 48U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1947     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 = 49U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1948     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 = 50U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1949     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 = 51U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1950     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 = 52U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1951     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 = 53U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1952     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 = 54U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1953     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 = 55U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1954     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 = 56U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1955     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 = 57U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1956     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 = 58U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1957     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 = 59U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1958     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 = 60U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1959     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 = 61U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1960     kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 = 62U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1961     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 = 63U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1962     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 = 64U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1963     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 = 65U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1964     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 = 66U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1965     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 = 67U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1966     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 = 68U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1967     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 = 69U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1968     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 = 70U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1969     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 = 71U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1970     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 = 72U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1971     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 = 73U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1972     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 = 74U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1973     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 = 75U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1974     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 = 76U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1975     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 = 77U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1976     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 = 78U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1977     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 = 79U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1978     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 = 80U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1979     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 = 81U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1980     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 = 82U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1981     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 = 83U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1982     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 = 84U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1983     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 = 85U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1984     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 = 86U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1985     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 = 87U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1986     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 = 88U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1987     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 = 89U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1988     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 = 90U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1989     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 = 91U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1990     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 = 92U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1991     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 = 93U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1992     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 = 94U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1993     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 = 95U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1994     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 = 96U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1995     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 = 97U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1996     kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 = 98U,       /**< IOMUXC SW_MUX_CTL_PAD index */
1997     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 99U,    /**< IOMUXC SW_MUX_CTL_PAD index */
1998     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 100U,   /**< IOMUXC SW_MUX_CTL_PAD index */
1999     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 101U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2000     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 102U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2001     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 103U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2002     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 104U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2003     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 = 105U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2004     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 = 106U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2005     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 = 107U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2006     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 = 108U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2007     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 = 109U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2008     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 = 110U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2009     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 = 111U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2010     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 = 112U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2011     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 = 113U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2012     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 = 114U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2013     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 = 115U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2014     kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 = 116U,   /**< IOMUXC SW_MUX_CTL_PAD index */
2015     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
2016     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
2017     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
2018     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
2019     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
2020     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
2021     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
2022     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 = 124U, /**< IOMUXC SW_MUX_CTL_PAD index */
2023     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 = 125U, /**< IOMUXC SW_MUX_CTL_PAD index */
2024     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 = 126U, /**< IOMUXC SW_MUX_CTL_PAD index */
2025     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 = 127U, /**< IOMUXC SW_MUX_CTL_PAD index */
2026     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 = 128U, /**< IOMUXC SW_MUX_CTL_PAD index */
2027     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 = 129U, /**< IOMUXC SW_MUX_CTL_PAD index */
2028     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 = 130U, /**< IOMUXC SW_MUX_CTL_PAD index */
2029     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 = 131U, /**< IOMUXC SW_MUX_CTL_PAD index */
2030     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 = 132U, /**< IOMUXC SW_MUX_CTL_PAD index */
2031     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 = 133U, /**< IOMUXC SW_MUX_CTL_PAD index */
2032     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 = 134U, /**< IOMUXC SW_MUX_CTL_PAD index */
2033     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 = 135U, /**< IOMUXC SW_MUX_CTL_PAD index */
2034     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 = 136U, /**< IOMUXC SW_MUX_CTL_PAD index */
2035     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 = 137U, /**< IOMUXC SW_MUX_CTL_PAD index */
2036     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 = 138U, /**< IOMUXC SW_MUX_CTL_PAD index */
2037     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 = 139U, /**< IOMUXC SW_MUX_CTL_PAD index */
2038     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 = 140U, /**< IOMUXC SW_MUX_CTL_PAD index */
2039     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 = 141U, /**< IOMUXC SW_MUX_CTL_PAD index */
2040     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 = 142U, /**< IOMUXC SW_MUX_CTL_PAD index */
2041     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 = 143U, /**< IOMUXC SW_MUX_CTL_PAD index */
2042     kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 = 144U, /**< IOMUXC SW_MUX_CTL_PAD index */
2043 } iomuxc_sw_mux_ctl_pad_t;
2044 
2045 /* @} */
2046 
2047 /*!
2048  * @addtogroup iomuxc_pads
2049  * @{ */
2050 
2051 /*******************************************************************************
2052  * Definitions
2053 *******************************************************************************/
2054 
2055 /*!
2056  * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
2057  *
2058  * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
2059  */
2060 typedef enum _iomuxc_sw_pad_ctl_pad
2061 {
2062     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 = 0U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2063     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 = 1U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2064     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 = 2U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2065     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 = 3U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2066     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 = 4U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2067     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 = 5U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2068     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 = 6U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2069     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 = 7U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2070     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 = 8U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2071     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 = 9U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2072     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 = 10U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2073     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 = 11U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2074     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 = 12U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2075     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 = 13U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2076     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 = 14U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2077     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 = 15U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2078     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 = 16U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2079     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 = 17U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2080     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 = 18U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2081     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 = 19U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2082     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 = 20U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2083     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 = 21U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2084     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 = 22U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2085     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 = 23U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2086     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 = 24U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2087     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 = 25U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2088     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 = 26U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2089     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 = 27U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2090     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 = 28U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2091     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 = 29U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2092     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 = 30U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2093     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 = 31U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2094     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 = 32U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2095     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 = 33U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2096     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 = 34U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2097     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 = 35U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2098     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 = 36U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2099     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 = 37U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2100     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 = 38U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2101     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 = 39U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2102     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 = 40U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2103     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 = 41U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2104     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 = 42U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2105     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 = 43U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2106     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 = 44U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2107     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 = 45U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2108     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 = 46U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2109     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 = 47U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2110     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 = 48U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2111     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 = 49U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2112     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 = 50U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2113     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 = 51U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2114     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 = 52U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2115     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 = 53U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2116     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 = 54U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2117     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 = 55U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2118     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 = 56U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2119     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 = 57U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2120     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 = 58U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2121     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 = 59U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2122     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 = 60U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2123     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 = 61U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2124     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 = 62U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2125     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 = 63U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2126     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 = 64U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2127     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 = 65U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2128     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 = 66U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2129     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 = 67U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2130     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 = 68U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2131     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 = 69U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2132     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 = 70U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2133     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 = 71U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2134     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 = 72U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2135     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 = 73U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2136     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 = 74U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2137     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 = 75U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2138     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 = 76U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2139     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 = 77U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2140     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 = 78U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2141     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 = 79U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2142     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 = 80U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2143     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 = 81U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2144     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 = 82U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2145     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 = 83U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2146     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 = 84U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2147     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 = 85U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2148     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 = 86U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2149     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 = 87U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2150     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 = 88U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2151     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 = 89U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2152     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 = 90U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2153     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 = 91U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2154     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 = 92U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2155     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 = 93U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2156     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 = 94U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2157     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 = 95U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2158     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 = 96U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2159     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 = 97U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2160     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 = 98U,       /**< IOMUXC SW_PAD_CTL_PAD index */
2161     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 99U,    /**< IOMUXC SW_PAD_CTL_PAD index */
2162     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 100U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2163     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 101U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2164     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 102U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2165     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 103U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2166     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 104U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2167     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 = 105U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2168     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 = 106U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2169     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 = 107U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2170     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 = 108U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2171     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 = 109U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2172     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 = 110U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2173     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 = 111U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2174     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 = 112U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2175     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 = 113U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2176     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 = 114U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2177     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 = 115U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2178     kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 = 116U,   /**< IOMUXC SW_PAD_CTL_PAD index */
2179     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
2180     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
2181     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
2182     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
2183     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
2184     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
2185     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
2186     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 = 124U, /**< IOMUXC SW_PAD_CTL_PAD index */
2187     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 = 125U, /**< IOMUXC SW_PAD_CTL_PAD index */
2188     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 = 126U, /**< IOMUXC SW_PAD_CTL_PAD index */
2189     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 = 127U, /**< IOMUXC SW_PAD_CTL_PAD index */
2190     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 = 128U, /**< IOMUXC SW_PAD_CTL_PAD index */
2191     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 = 129U, /**< IOMUXC SW_PAD_CTL_PAD index */
2192     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 = 130U, /**< IOMUXC SW_PAD_CTL_PAD index */
2193     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 = 131U, /**< IOMUXC SW_PAD_CTL_PAD index */
2194     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 = 132U, /**< IOMUXC SW_PAD_CTL_PAD index */
2195     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 = 133U, /**< IOMUXC SW_PAD_CTL_PAD index */
2196     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 = 134U, /**< IOMUXC SW_PAD_CTL_PAD index */
2197     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 = 135U, /**< IOMUXC SW_PAD_CTL_PAD index */
2198     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 = 136U, /**< IOMUXC SW_PAD_CTL_PAD index */
2199     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 = 137U, /**< IOMUXC SW_PAD_CTL_PAD index */
2200     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 = 138U, /**< IOMUXC SW_PAD_CTL_PAD index */
2201     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 = 139U, /**< IOMUXC SW_PAD_CTL_PAD index */
2202     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 = 140U, /**< IOMUXC SW_PAD_CTL_PAD index */
2203     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 = 141U, /**< IOMUXC SW_PAD_CTL_PAD index */
2204     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 = 142U, /**< IOMUXC SW_PAD_CTL_PAD index */
2205     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 = 143U, /**< IOMUXC SW_PAD_CTL_PAD index */
2206     kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 = 144U, /**< IOMUXC SW_PAD_CTL_PAD index */
2207 } iomuxc_sw_pad_ctl_pad_t;
2208 
2209 /* @} */
2210 
2211 /*!
2212  * @brief Enumeration for the IOMUXC select input
2213  *
2214  * Defines the enumeration for the IOMUXC select input collections.
2215  */
2216 typedef enum _iomuxc_select_input
2217 {
2218     kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 0U,         /**< IOMUXC select input index */
2219     kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 1U,         /**< IOMUXC select input index */
2220     kIOMUXC_CCM_ENET_QOS_REF_CLK_SELECT_INPUT = 2U, /**< IOMUXC select input index */
2221     kIOMUXC_CCM_ENET_QOS_TX_CLK_SELECT_INPUT = 3U, /**< IOMUXC select input index */
2222     kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 4U,   /**< IOMUXC select input index */
2223     kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT = 5U,      /**< IOMUXC select input index */
2224     kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 = 6U,  /**< IOMUXC select input index */
2225     kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 = 7U,  /**< IOMUXC select input index */
2226     kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT = 8U,      /**< IOMUXC select input index */
2227     kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT = 9U,     /**< IOMUXC select input index */
2228     kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT = 10U,    /**< IOMUXC select input index */
2229     kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT = 11U, /**< IOMUXC select input index */
2230     kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT = 12U,  /**< IOMUXC select input index */
2231     kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT = 13U, /**< IOMUXC select input index */
2232     kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT = 14U, /**< IOMUXC select input index */
2233     kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT = 15U, /**< IOMUXC select input index */
2234     kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT = 16U, /**< IOMUXC select input index */
2235     kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT = 17U, /**< IOMUXC select input index */
2236     kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT = 18U,  /**< IOMUXC select input index */
2237     kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT = 19U, /**< IOMUXC select input index */
2238     kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT = 20U, /**< IOMUXC select input index */
2239     kIOMUXC_ENET_QOS_GMII_MDI_I_SELECT_INPUT = 21U, /**< IOMUXC select input index */
2240     kIOMUXC_ENET_QOS_PHY_RXD_I_SELECT_INPUT_0 = 22U, /**< IOMUXC select input index */
2241     kIOMUXC_ENET_QOS_PHY_RXD_I_SELECT_INPUT_1 = 23U, /**< IOMUXC select input index */
2242     kIOMUXC_ENET_QOS_PHY_RXDV_I_SELECT_INPUT = 24U, /**< IOMUXC select input index */
2243     kIOMUXC_ENET_QOS_PHY_RXER_I_SELECT_INPUT = 25U, /**< IOMUXC select input index */
2244     kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 = 26U,    /**< IOMUXC select input index */
2245     kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 = 27U,    /**< IOMUXC select input index */
2246     kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 = 28U,    /**< IOMUXC select input index */
2247     kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 = 29U,    /**< IOMUXC select input index */
2248     kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 = 30U,    /**< IOMUXC select input index */
2249     kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 = 31U,    /**< IOMUXC select input index */
2250     kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 = 32U,    /**< IOMUXC select input index */
2251     kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 = 33U,    /**< IOMUXC select input index */
2252     kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 = 34U,    /**< IOMUXC select input index */
2253     kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 = 35U,    /**< IOMUXC select input index */
2254     kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 = 36U,    /**< IOMUXC select input index */
2255     kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 = 37U,    /**< IOMUXC select input index */
2256     kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 = 38U,    /**< IOMUXC select input index */
2257     kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 = 39U,    /**< IOMUXC select input index */
2258     kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 = 40U,    /**< IOMUXC select input index */
2259     kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 = 41U,    /**< IOMUXC select input index */
2260     kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 = 42U,    /**< IOMUXC select input index */
2261     kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 = 43U,    /**< IOMUXC select input index */
2262     kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 = 44U,    /**< IOMUXC select input index */
2263     kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 = 45U,    /**< IOMUXC select input index */
2264     kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT = 46U,  /**< IOMUXC select input index */
2265     kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 = 47U, /**< IOMUXC select input index */
2266     kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 = 48U, /**< IOMUXC select input index */
2267     kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 = 49U, /**< IOMUXC select input index */
2268     kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 = 50U, /**< IOMUXC select input index */
2269     kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 = 51U, /**< IOMUXC select input index */
2270     kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 = 52U, /**< IOMUXC select input index */
2271     kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 = 53U, /**< IOMUXC select input index */
2272     kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 = 54U, /**< IOMUXC select input index */
2273     kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT = 55U,  /**< IOMUXC select input index */
2274     kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT = 56U,  /**< IOMUXC select input index */
2275     kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 = 57U, /**< IOMUXC select input index */
2276     kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 = 58U, /**< IOMUXC select input index */
2277     kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 = 59U, /**< IOMUXC select input index */
2278     kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 = 60U, /**< IOMUXC select input index */
2279     kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT = 61U,  /**< IOMUXC select input index */
2280     kIOMUXC_GPT3_CAPIN1_SELECT_INPUT = 62U,        /**< IOMUXC select input index */
2281     kIOMUXC_GPT3_CAPIN2_SELECT_INPUT = 63U,        /**< IOMUXC select input index */
2282     kIOMUXC_GPT3_CLKIN_SELECT_INPUT = 64U,         /**< IOMUXC select input index */
2283     kIOMUXC_KPP_COL_SELECT_INPUT_6  = 65U,         /**< IOMUXC select input index */
2284     kIOMUXC_KPP_COL_SELECT_INPUT_7  = 66U,         /**< IOMUXC select input index */
2285     kIOMUXC_KPP_ROW_SELECT_INPUT_6  = 67U,         /**< IOMUXC select input index */
2286     kIOMUXC_KPP_ROW_SELECT_INPUT_7  = 68U,         /**< IOMUXC select input index */
2287     kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT = 69U,   /**< IOMUXC select input index */
2288     kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT = 70U,   /**< IOMUXC select input index */
2289     kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT = 71U,   /**< IOMUXC select input index */
2290     kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT = 72U,   /**< IOMUXC select input index */
2291     kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT = 73U,   /**< IOMUXC select input index */
2292     kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT = 74U,   /**< IOMUXC select input index */
2293     kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT = 75U,   /**< IOMUXC select input index */
2294     kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT = 76U,   /**< IOMUXC select input index */
2295     kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 = 77U, /**< IOMUXC select input index */
2296     kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT = 78U,   /**< IOMUXC select input index */
2297     kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT = 79U,   /**< IOMUXC select input index */
2298     kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT = 80U,   /**< IOMUXC select input index */
2299     kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 = 81U, /**< IOMUXC select input index */
2300     kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 = 82U, /**< IOMUXC select input index */
2301     kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT = 83U,   /**< IOMUXC select input index */
2302     kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT = 84U,   /**< IOMUXC select input index */
2303     kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT = 85U,   /**< IOMUXC select input index */
2304     kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 = 86U, /**< IOMUXC select input index */
2305     kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 = 87U, /**< IOMUXC select input index */
2306     kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 = 88U, /**< IOMUXC select input index */
2307     kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 = 89U, /**< IOMUXC select input index */
2308     kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT = 90U,   /**< IOMUXC select input index */
2309     kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT = 91U,   /**< IOMUXC select input index */
2310     kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT = 92U,   /**< IOMUXC select input index */
2311     kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 = 93U, /**< IOMUXC select input index */
2312     kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT = 94U,   /**< IOMUXC select input index */
2313     kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT = 95U,   /**< IOMUXC select input index */
2314     kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT = 96U,   /**< IOMUXC select input index */
2315     kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT = 97U, /**< IOMUXC select input index */
2316     kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT = 98U, /**< IOMUXC select input index */
2317     kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT = 99U, /**< IOMUXC select input index */
2318     kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT = 100U, /**< IOMUXC select input index */
2319     kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT = 101U, /**< IOMUXC select input index */
2320     kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT = 102U, /**< IOMUXC select input index */
2321     kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT = 103U, /**< IOMUXC select input index */
2322     kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT = 104U, /**< IOMUXC select input index */
2323     kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT = 105U, /**< IOMUXC select input index */
2324     kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT = 106U, /**< IOMUXC select input index */
2325     kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT = 107U, /**< IOMUXC select input index */
2326     kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT = 108U, /**< IOMUXC select input index */
2327     kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT = 109U, /**< IOMUXC select input index */
2328     kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT = 110U, /**< IOMUXC select input index */
2329     kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT = 111U, /**< IOMUXC select input index */
2330     kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT = 112U, /**< IOMUXC select input index */
2331     kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT = 113U, /**< IOMUXC select input index */
2332     kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT = 114U, /**< IOMUXC select input index */
2333     kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT = 115U, /**< IOMUXC select input index */
2334     kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT = 116U, /**< IOMUXC select input index */
2335     kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT = 117U, /**< IOMUXC select input index */
2336     kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT = 118U,   /**< IOMUXC select input index */
2337     kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 = 119U, /**< IOMUXC select input index */
2338     kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT = 120U,   /**< IOMUXC select input index */
2339     kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT = 121U,   /**< IOMUXC select input index */
2340     kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT = 122U,   /**< IOMUXC select input index */
2341     kIOMUXC_EMVSIM1_SIO_SELECT_INPUT = 129U,       /**< IOMUXC select input index */
2342     kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT = 130U, /**< IOMUXC select input index */
2343     kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT = 131U, /**< IOMUXC select input index */
2344     kIOMUXC_EMVSIM2_SIO_SELECT_INPUT = 132U,       /**< IOMUXC select input index */
2345     kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT = 133U, /**< IOMUXC select input index */
2346     kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT = 134U, /**< IOMUXC select input index */
2347     kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 135U,   /**< IOMUXC select input index */
2348     kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 136U,       /**< IOMUXC select input index */
2349     kIOMUXC_USB_OTG_OC_SELECT_INPUT = 137U,        /**< IOMUXC select input index */
2350     kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT = 138U,    /**< IOMUXC select input index */
2351     kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT = 139U,    /**< IOMUXC select input index */
2352     kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT = 140U, /**< IOMUXC select input index */
2353     kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT = 141U,  /**< IOMUXC select input index */
2354     kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT = 142U, /**< IOMUXC select input index */
2355     kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT = 143U,  /**< IOMUXC select input index */
2356     kIOMUXC_XBAR1_IN_SELECT_INPUT_20 = 144U,       /**< IOMUXC select input index */
2357     kIOMUXC_XBAR1_IN_SELECT_INPUT_21 = 145U,       /**< IOMUXC select input index */
2358     kIOMUXC_XBAR1_IN_SELECT_INPUT_22 = 146U,       /**< IOMUXC select input index */
2359     kIOMUXC_XBAR1_IN_SELECT_INPUT_23 = 147U,       /**< IOMUXC select input index */
2360     kIOMUXC_XBAR1_IN_SELECT_INPUT_24 = 148U,       /**< IOMUXC select input index */
2361     kIOMUXC_XBAR1_IN_SELECT_INPUT_25 = 149U,       /**< IOMUXC select input index */
2362     kIOMUXC_XBAR1_IN_SELECT_INPUT_26 = 150U,       /**< IOMUXC select input index */
2363     kIOMUXC_XBAR1_IN_SELECT_INPUT_27 = 151U,       /**< IOMUXC select input index */
2364     kIOMUXC_XBAR1_IN_SELECT_INPUT_28 = 152U,       /**< IOMUXC select input index */
2365     kIOMUXC_XBAR1_IN_SELECT_INPUT_29 = 153U,       /**< IOMUXC select input index */
2366     kIOMUXC_XBAR1_IN_SELECT_INPUT_30 = 154U,       /**< IOMUXC select input index */
2367     kIOMUXC_XBAR1_IN_SELECT_INPUT_31 = 155U,       /**< IOMUXC select input index */
2368     kIOMUXC_XBAR1_IN_SELECT_INPUT_32 = 156U,       /**< IOMUXC select input index */
2369     kIOMUXC_XBAR1_IN_SELECT_INPUT_33 = 157U,       /**< IOMUXC select input index */
2370     kIOMUXC_XBAR1_IN_SELECT_INPUT_34 = 158U,       /**< IOMUXC select input index */
2371     kIOMUXC_XBAR1_IN_SELECT_INPUT_35 = 159U,       /**< IOMUXC select input index */
2372 } iomuxc_select_input_t;
2373 
2374 
2375 /*!
2376  * @}
2377  */ /* end of group Mapping_Information */
2378 
2379 
2380 /* ----------------------------------------------------------------------------
2381    -- Device Peripheral Access Layer
2382    ---------------------------------------------------------------------------- */
2383 
2384 /*!
2385  * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
2386  * @{
2387  */
2388 
2389 
2390 /*
2391 ** Start of section using anonymous unions
2392 */
2393 
2394 #if defined(__ARMCC_VERSION)
2395   #if (__ARMCC_VERSION >= 6010050)
2396     #pragma clang diagnostic push
2397   #else
2398     #pragma push
2399     #pragma anon_unions
2400   #endif
2401 #elif defined(__CWCC__)
2402   #pragma push
2403   #pragma cpp_extensions on
2404 #elif defined(__GNUC__)
2405   /* anonymous unions are enabled by default */
2406 #elif defined(__IAR_SYSTEMS_ICC__)
2407   #pragma language=extended
2408 #else
2409   #error Not supported compiler type
2410 #endif
2411 
2412 /* ----------------------------------------------------------------------------
2413    -- ADC Peripheral Access Layer
2414    ---------------------------------------------------------------------------- */
2415 
2416 /*!
2417  * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
2418  * @{
2419  */
2420 
2421 /** ADC - Register Layout Typedef */
2422 typedef struct {
2423   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
2424   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
2425        uint8_t RESERVED_0[8];
2426   __IO uint32_t CTRL;                              /**< LPADC Control Register, offset: 0x10 */
2427   __IO uint32_t STAT;                              /**< LPADC Status Register, offset: 0x14 */
2428   __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
2429   __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
2430   __IO uint32_t CFG;                               /**< LPADC Configuration Register, offset: 0x20 */
2431   __IO uint32_t PAUSE;                             /**< LPADC Pause Register, offset: 0x24 */
2432        uint8_t RESERVED_1[8];
2433   __IO uint32_t FCTRL;                             /**< LPADC FIFO Control Register, offset: 0x30 */
2434   __O  uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
2435        uint8_t RESERVED_2[136];
2436   __IO uint32_t TCTRL[8];                          /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
2437        uint8_t RESERVED_3[32];
2438   struct {                                         /* offset: 0x100, array step: 0x8 */
2439     __IO uint32_t CMDL;                              /**< LPADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
2440     __IO uint32_t CMDH;                              /**< LPADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
2441   } CMD[15];
2442        uint8_t RESERVED_4[136];
2443   __IO uint32_t CV[4];                             /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
2444        uint8_t RESERVED_5[240];
2445   __I  uint32_t RESFIFO;                           /**< LPADC Data Result FIFO Register, offset: 0x300 */
2446 } ADC_Type;
2447 
2448 /* ----------------------------------------------------------------------------
2449    -- ADC Register Masks
2450    ---------------------------------------------------------------------------- */
2451 
2452 /*!
2453  * @addtogroup ADC_Register_Masks ADC Register Masks
2454  * @{
2455  */
2456 
2457 /*! @name VERID - Version ID Register */
2458 /*! @{ */
2459 
2460 #define ADC_VERID_RES_MASK                       (0x1U)
2461 #define ADC_VERID_RES_SHIFT                      (0U)
2462 /*! RES - Resolution
2463  *  0b0..Up to 13-bit differential/12-bit single ended resolution supported.
2464  *  0b1..Up to 16-bit differential/15-bit single ended resolution supported.
2465  */
2466 #define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
2467 
2468 #define ADC_VERID_DIFFEN_MASK                    (0x2U)
2469 #define ADC_VERID_DIFFEN_SHIFT                   (1U)
2470 /*! DIFFEN - Differential Supported
2471  *  0b0..Differential operation not supported.
2472  *  0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
2473  */
2474 #define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
2475 
2476 #define ADC_VERID_MVI_MASK                       (0x8U)
2477 #define ADC_VERID_MVI_SHIFT                      (3U)
2478 /*! MVI - Multi Vref Implemented
2479  *  0b0..Single voltage reference input supported.
2480  *  0b1..Multiple voltage reference inputs supported.
2481  */
2482 #define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
2483 
2484 #define ADC_VERID_CSW_MASK                       (0x70U)
2485 #define ADC_VERID_CSW_SHIFT                      (4U)
2486 /*! CSW - Channel Scale Width
2487  *  0b000..Channel scaling not supported.
2488  *  0b001..Channel scaling supported. 1-bit CSCALE control field.
2489  *  0b110..Channel scaling supported. 6-bit CSCALE control field.
2490  */
2491 #define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
2492 
2493 #define ADC_VERID_VR1RNGI_MASK                   (0x100U)
2494 #define ADC_VERID_VR1RNGI_SHIFT                  (8U)
2495 /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
2496  *  0b0..Range control not required. CFG[VREF1RNG] is not implemented.
2497  *  0b1..Range control required. CFG[VREF1RNG] is implemented.
2498  */
2499 #define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
2500 
2501 #define ADC_VERID_IADCKI_MASK                    (0x200U)
2502 #define ADC_VERID_IADCKI_SHIFT                   (9U)
2503 /*! IADCKI - Internal LPADC Clock implemented
2504  *  0b0..Internal clock source not implemented.
2505  *  0b1..Internal clock source (and CFG[ADCKEN]) implemented.
2506  */
2507 #define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
2508 
2509 #define ADC_VERID_CALOFSI_MASK                   (0x400U)
2510 #define ADC_VERID_CALOFSI_SHIFT                  (10U)
2511 /*! CALOFSI - Calibration Offset Function Implemented
2512  *  0b0..Offset calibration and offset trimming not implemented.
2513  *  0b1..Offset calibration and offset trimming implemented.
2514  */
2515 #define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
2516 
2517 #define ADC_VERID_MINOR_MASK                     (0xFF0000U)
2518 #define ADC_VERID_MINOR_SHIFT                    (16U)
2519 /*! MINOR - Minor Version Number */
2520 #define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
2521 
2522 #define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
2523 #define ADC_VERID_MAJOR_SHIFT                    (24U)
2524 /*! MAJOR - Major Version Number */
2525 #define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
2526 /*! @} */
2527 
2528 /*! @name PARAM - Parameter Register */
2529 /*! @{ */
2530 
2531 #define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
2532 #define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
2533 /*! TRIG_NUM - Trigger Number
2534  *  0b00001000..8 hardware triggers implemented
2535  */
2536 #define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
2537 
2538 #define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
2539 #define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
2540 /*! FIFOSIZE - Result FIFO Depth
2541  *  0b00010000..Result FIFO depth = 16 datawords.
2542  */
2543 #define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
2544 
2545 #define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
2546 #define ADC_PARAM_CV_NUM_SHIFT                   (16U)
2547 /*! CV_NUM - Compare Value Number
2548  *  0b00000100..4 compare value registers implemented
2549  */
2550 #define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
2551 
2552 #define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
2553 #define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
2554 /*! CMD_NUM - Command Buffer Number
2555  *  0b00001111..15 command buffers implemented
2556  */
2557 #define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
2558 /*! @} */
2559 
2560 /*! @name CTRL - LPADC Control Register */
2561 /*! @{ */
2562 
2563 #define ADC_CTRL_ADCEN_MASK                      (0x1U)
2564 #define ADC_CTRL_ADCEN_SHIFT                     (0U)
2565 /*! ADCEN - LPADC Enable
2566  *  0b0..LPADC is disabled.
2567  *  0b1..LPADC is enabled.
2568  */
2569 #define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
2570 
2571 #define ADC_CTRL_RST_MASK                        (0x2U)
2572 #define ADC_CTRL_RST_SHIFT                       (1U)
2573 /*! RST - Software Reset
2574  *  0b0..LPADC logic is not reset.
2575  *  0b1..LPADC logic is reset.
2576  */
2577 #define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
2578 
2579 #define ADC_CTRL_DOZEN_MASK                      (0x4U)
2580 #define ADC_CTRL_DOZEN_SHIFT                     (2U)
2581 /*! DOZEN - Doze Enable
2582  *  0b0..LPADC is enabled in Doze mode.
2583  *  0b1..LPADC is disabled in Doze mode.
2584  */
2585 #define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
2586 
2587 #define ADC_CTRL_TRIG_SRC_MASK                   (0x18U)
2588 #define ADC_CTRL_TRIG_SRC_SHIFT                  (3U)
2589 /*! TRIG_SRC - Hardware trigger source selection
2590  *  0b00..ADC_ETC hw trigger , and HW trigger are enabled
2591  *  0b01..ADC_ETC hw trigger is enabled
2592  *  0b10..HW trigger is enabled
2593  *  0b11..Reserved
2594  */
2595 #define ADC_CTRL_TRIG_SRC(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TRIG_SRC_SHIFT)) & ADC_CTRL_TRIG_SRC_MASK)
2596 
2597 #define ADC_CTRL_RSTFIFO_MASK                    (0x100U)
2598 #define ADC_CTRL_RSTFIFO_SHIFT                   (8U)
2599 /*! RSTFIFO - Reset FIFO
2600  *  0b0..No effect.
2601  *  0b1..FIFO is reset.
2602  */
2603 #define ADC_CTRL_RSTFIFO(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
2604 /*! @} */
2605 
2606 /*! @name STAT - LPADC Status Register */
2607 /*! @{ */
2608 
2609 #define ADC_STAT_RDY_MASK                        (0x1U)
2610 #define ADC_STAT_RDY_SHIFT                       (0U)
2611 /*! RDY - Result FIFO Ready Flag
2612  *  0b0..Result FIFO data level not above watermark level.
2613  *  0b1..Result FIFO holding data above watermark level.
2614  */
2615 #define ADC_STAT_RDY(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
2616 
2617 #define ADC_STAT_FOF_MASK                        (0x2U)
2618 #define ADC_STAT_FOF_SHIFT                       (1U)
2619 /*! FOF - Result FIFO Overflow Flag
2620  *  0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
2621  *  0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
2622  */
2623 #define ADC_STAT_FOF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
2624 
2625 #define ADC_STAT_ADC_ACTIVE_MASK                 (0x100U)
2626 #define ADC_STAT_ADC_ACTIVE_SHIFT                (8U)
2627 /*! ADC_ACTIVE - ADC Active
2628  *  0b0..The LPADC is IDLE. There are no pending triggers to service and no active commands are being processed.
2629  *  0b1..The LPADC is processing a conversion, running through the power up delay, or servicing a trigger.
2630  */
2631 #define ADC_STAT_ADC_ACTIVE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
2632 
2633 #define ADC_STAT_TRGACT_MASK                     (0x70000U)
2634 #define ADC_STAT_TRGACT_SHIFT                    (16U)
2635 /*! TRGACT - Trigger Active
2636  *  0b000..Command (sequence) associated with Trigger 0 currently being executed.
2637  *  0b001..Command (sequence) associated with Trigger 1 currently being executed.
2638  *  0b010..Command (sequence) associated with Trigger 2 currently being executed.
2639  *  0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed.
2640  */
2641 #define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
2642 
2643 #define ADC_STAT_CMDACT_MASK                     (0xF000000U)
2644 #define ADC_STAT_CMDACT_SHIFT                    (24U)
2645 /*! CMDACT - Command Active
2646  *  0b0000..No command is currently in progress.
2647  *  0b0001..Command 1 currently being executed.
2648  *  0b0010..Command 2 currently being executed.
2649  *  0b0011-0b1111..Associated command number is currently being executed.
2650  */
2651 #define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
2652 /*! @} */
2653 
2654 /*! @name IE - Interrupt Enable Register */
2655 /*! @{ */
2656 
2657 #define ADC_IE_FWMIE_MASK                        (0x1U)
2658 #define ADC_IE_FWMIE_SHIFT                       (0U)
2659 /*! FWMIE - FIFO Watermark Interrupt Enable
2660  *  0b0..FIFO watermark interrupts are not enabled.
2661  *  0b1..FIFO watermark interrupts are enabled.
2662  */
2663 #define ADC_IE_FWMIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
2664 
2665 #define ADC_IE_FOFIE_MASK                        (0x2U)
2666 #define ADC_IE_FOFIE_SHIFT                       (1U)
2667 /*! FOFIE - Result FIFO Overflow Interrupt Enable
2668  *  0b0..FIFO overflow interrupts are not enabled.
2669  *  0b1..FIFO overflow interrupts are enabled.
2670  */
2671 #define ADC_IE_FOFIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
2672 /*! @} */
2673 
2674 /*! @name DE - DMA Enable Register */
2675 /*! @{ */
2676 
2677 #define ADC_DE_FWMDE_MASK                        (0x1U)
2678 #define ADC_DE_FWMDE_SHIFT                       (0U)
2679 /*! FWMDE - FIFO Watermark DMA Enable
2680  *  0b0..DMA request disabled.
2681  *  0b1..DMA request enabled.
2682  */
2683 #define ADC_DE_FWMDE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
2684 /*! @} */
2685 
2686 /*! @name CFG - LPADC Configuration Register */
2687 /*! @{ */
2688 
2689 #define ADC_CFG_TPRICTRL_MASK                    (0x1U)
2690 #define ADC_CFG_TPRICTRL_SHIFT                   (0U)
2691 /*! TPRICTRL - LPADC trigger priority control
2692  *  0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and
2693  *       the new command specified by the trigger is started.
2694  *  0b1..If a higher priority trigger is received during command processing, the current conversion is completed
2695  *       (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority
2696  *       trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true
2697  *       conversion.
2698  */
2699 #define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
2700 
2701 #define ADC_CFG_PWRSEL_MASK                      (0x30U)
2702 #define ADC_CFG_PWRSEL_SHIFT                     (4U)
2703 /*! PWRSEL - Power Configuration Select
2704  *  0b00..Level 1 (Lowest power setting)
2705  *  0b01..Level 2
2706  *  0b10..Level 3
2707  *  0b11..Level 4 (Highest power setting)
2708  */
2709 #define ADC_CFG_PWRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
2710 
2711 #define ADC_CFG_REFSEL_MASK                      (0xC0U)
2712 #define ADC_CFG_REFSEL_SHIFT                     (6U)
2713 /*! REFSEL - Voltage Reference Selection
2714  *  0b00..(Default) Option 1 setting.
2715  *  0b01..Option 2 setting.
2716  *  0b10..Option 3 setting.
2717  *  0b11..Reserved
2718  */
2719 #define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
2720 
2721 #define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
2722 #define ADC_CFG_PUDLY_SHIFT                      (16U)
2723 /*! PUDLY - Power Up Delay */
2724 #define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
2725 
2726 #define ADC_CFG_PWREN_MASK                       (0x10000000U)
2727 #define ADC_CFG_PWREN_SHIFT                      (28U)
2728 /*! PWREN - LPADC Analog Pre-Enable
2729  *  0b0..LPADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
2730  *  0b1..LPADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the
2731  *       cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any
2732  *       detected trigger does not begin ADC operation until the power up delay time has passed.
2733  */
2734 #define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
2735 /*! @} */
2736 
2737 /*! @name PAUSE - LPADC Pause Register */
2738 /*! @{ */
2739 
2740 #define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
2741 #define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
2742 /*! PAUSEDLY - Pause Delay */
2743 #define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
2744 
2745 #define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
2746 #define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
2747 /*! PAUSEEN - PAUSE Option Enable
2748  *  0b0..Pause operation disabled
2749  *  0b1..Pause operation enabled
2750  */
2751 #define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
2752 /*! @} */
2753 
2754 /*! @name FCTRL - LPADC FIFO Control Register */
2755 /*! @{ */
2756 
2757 #define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
2758 #define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
2759 /*! FCOUNT - Result FIFO counter
2760  *  0b00000..No data stored in FIFO
2761  *  0b00001..1 dataword stored in FIFO
2762  *  0b00010..2 datawords stored in FIFO
2763  *  0b00100..4 datawords stored in FIFO
2764  *  0b01000..8 datawords stored in FIFO
2765  *  0b10000..16 datawords stored in FIFO
2766  */
2767 #define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
2768 
2769 #define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
2770 #define ADC_FCTRL_FWMARK_SHIFT                   (16U)
2771 /*! FWMARK - Watermark level selection
2772  *  0b0000..Generates STAT[RDY] flag after 1st successful conversion - single conversion
2773  *  0b0001..Generates STAT[RDY] flag after 2nd successful conversion
2774  *  0b0010..Generates STAT[RDY] flag after 3rd successful conversion
2775  *  0b0011..Generates STAT[RDY] flag after 4th successful conversion
2776  *  0b0100..Generates STAT[RDY] flag after 5th successful conversion
2777  *  0b0101..Generates STAT[RDY] flag after 6th successful conversion
2778  *  0b0110..Generates STAT[RDY] flag after 7th successful conversion
2779  *  0b0111..Generates STAT[RDY] flag after 8th successful conversion
2780  *  0b1000..Generates STAT[RDY] flag after 9th successful conversion
2781  *  0b1001..Generates STAT[RDY] flag after 10th successful conversion
2782  *  0b1010..Generates STAT[RDY] flag after 11th successful conversion
2783  *  0b1011..Generates STAT[RDY] flag after 12th successful conversion
2784  *  0b1100..Generates STAT[RDY] flag after 13th successful conversion
2785  *  0b1101..Generates STAT[RDY] flag after 14th successful conversion
2786  *  0b1110..Generates STAT[RDY] flag after 15th successful conversion
2787  *  0b1111..Generates STAT[RDY] flag after 16th successful conversion
2788  */
2789 #define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
2790 /*! @} */
2791 
2792 /*! @name SWTRIG - Software Trigger Register */
2793 /*! @{ */
2794 
2795 #define ADC_SWTRIG_SWT0_MASK                     (0x1U)
2796 #define ADC_SWTRIG_SWT0_SHIFT                    (0U)
2797 /*! SWT0 - Software trigger 0 event
2798  *  0b0..No trigger 0 event generated.
2799  *  0b1..Trigger 0 event generated.
2800  */
2801 #define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
2802 
2803 #define ADC_SWTRIG_SWT1_MASK                     (0x2U)
2804 #define ADC_SWTRIG_SWT1_SHIFT                    (1U)
2805 /*! SWT1 - Software trigger 1 event
2806  *  0b0..No trigger 1 event generated.
2807  *  0b1..Trigger 1 event generated.
2808  */
2809 #define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
2810 
2811 #define ADC_SWTRIG_SWT2_MASK                     (0x4U)
2812 #define ADC_SWTRIG_SWT2_SHIFT                    (2U)
2813 /*! SWT2 - Software trigger 2 event
2814  *  0b0..No trigger 2 event generated.
2815  *  0b1..Trigger 2 event generated.
2816  */
2817 #define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
2818 
2819 #define ADC_SWTRIG_SWT3_MASK                     (0x8U)
2820 #define ADC_SWTRIG_SWT3_SHIFT                    (3U)
2821 /*! SWT3 - Software trigger 3 event
2822  *  0b0..No trigger 3 event generated.
2823  *  0b1..Trigger 3 event generated.
2824  */
2825 #define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
2826 
2827 #define ADC_SWTRIG_SWT4_MASK                     (0x10U)
2828 #define ADC_SWTRIG_SWT4_SHIFT                    (4U)
2829 /*! SWT4 - Software trigger 4 event
2830  *  0b0..No trigger 4 event generated.
2831  *  0b1..Trigger 4 event generated.
2832  */
2833 #define ADC_SWTRIG_SWT4(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
2834 
2835 #define ADC_SWTRIG_SWT5_MASK                     (0x20U)
2836 #define ADC_SWTRIG_SWT5_SHIFT                    (5U)
2837 /*! SWT5 - Software trigger 5 event
2838  *  0b0..No trigger 5 event generated.
2839  *  0b1..Trigger 5 event generated.
2840  */
2841 #define ADC_SWTRIG_SWT5(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
2842 
2843 #define ADC_SWTRIG_SWT6_MASK                     (0x40U)
2844 #define ADC_SWTRIG_SWT6_SHIFT                    (6U)
2845 /*! SWT6 - Software trigger 6 event
2846  *  0b0..No trigger 6 event generated.
2847  *  0b1..Trigger 6 event generated.
2848  */
2849 #define ADC_SWTRIG_SWT6(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
2850 
2851 #define ADC_SWTRIG_SWT7_MASK                     (0x80U)
2852 #define ADC_SWTRIG_SWT7_SHIFT                    (7U)
2853 /*! SWT7 - Software trigger 7 event
2854  *  0b0..No trigger 7 event generated.
2855  *  0b1..Trigger 7 event generated.
2856  */
2857 #define ADC_SWTRIG_SWT7(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
2858 /*! @} */
2859 
2860 /*! @name TCTRL - Trigger Control Register */
2861 /*! @{ */
2862 
2863 #define ADC_TCTRL_HTEN_MASK                      (0x1U)
2864 #define ADC_TCTRL_HTEN_SHIFT                     (0U)
2865 /*! HTEN - Trigger enable
2866  *  0b0..Hardware trigger source disabled
2867  *  0b1..Hardware trigger source enabled
2868  */
2869 #define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
2870 
2871 #define ADC_TCTRL_CMD_SEL_MASK                   (0x2U)
2872 #define ADC_TCTRL_CMD_SEL_SHIFT                  (1U)
2873 /*! CMD_SEL
2874  *  0b0..TCTRLa[TCMD] will determine the command
2875  *  0b1..Software TCDM is bypassed , and hardware TCMD from ADC_ETC module will be used. The trigger command is
2876  *       then defined by ADC hardware trigger command selection field in ADC_ETC->TRIGx_CHAINy_z_n[CSEL].
2877  */
2878 #define ADC_TCTRL_CMD_SEL(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_CMD_SEL_SHIFT)) & ADC_TCTRL_CMD_SEL_MASK)
2879 
2880 #define ADC_TCTRL_TPRI_MASK                      (0x700U)
2881 #define ADC_TCTRL_TPRI_SHIFT                     (8U)
2882 /*! TPRI - Trigger priority setting
2883  *  0b000..Set to highest priority, Level 1
2884  *  0b001-0b110..Set to corresponding priority level
2885  *  0b111..Set to lowest priority, Level 8
2886  */
2887 #define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
2888 
2889 #define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
2890 #define ADC_TCTRL_TDLY_SHIFT                     (16U)
2891 /*! TDLY - Trigger delay select */
2892 #define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
2893 
2894 #define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
2895 #define ADC_TCTRL_TCMD_SHIFT                     (24U)
2896 /*! TCMD - Trigger command select
2897  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
2898  *  0b0001..CMD1 is executed
2899  *  0b0010-0b1110..Corresponding CMD is executed
2900  *  0b1111..CMD15 is executed
2901  */
2902 #define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
2903 /*! @} */
2904 
2905 /* The count of ADC_TCTRL */
2906 #define ADC_TCTRL_COUNT                          (8U)
2907 
2908 /*! @name CMDL - LPADC Command Low Buffer Register */
2909 /*! @{ */
2910 
2911 #define ADC_CMDL_ADCH_MASK                       (0x1FU)
2912 #define ADC_CMDL_ADCH_SHIFT                      (0U)
2913 /*! ADCH - Input channel select
2914  *  0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
2915  *  0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
2916  *  0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
2917  *  0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
2918  *  0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
2919  *  0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
2920  *  0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
2921  */
2922 #define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
2923 
2924 #define ADC_CMDL_ABSEL_MASK                      (0x20U)
2925 #define ADC_CMDL_ABSEL_SHIFT                     (5U)
2926 /*! ABSEL - A-side vs. B-side Select
2927  *  0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
2928  *  0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
2929  */
2930 #define ADC_CMDL_ABSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
2931 
2932 #define ADC_CMDL_DIFF_MASK                       (0x40U)
2933 #define ADC_CMDL_DIFF_SHIFT                      (6U)
2934 /*! DIFF - Differential Mode Enable
2935  *  0b0..Single-ended mode.
2936  *  0b1..Differential mode.
2937  */
2938 #define ADC_CMDL_DIFF(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
2939 
2940 #define ADC_CMDL_CSCALE_MASK                     (0x2000U)
2941 #define ADC_CMDL_CSCALE_SHIFT                    (13U)
2942 /*! CSCALE - Channel Scale
2943  *  0b0..Scale selected analog channel (Factor of 30/64)
2944  *  0b1..(Default) Full scale (Factor of 1)
2945  */
2946 #define ADC_CMDL_CSCALE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
2947 /*! @} */
2948 
2949 /* The count of ADC_CMDL */
2950 #define ADC_CMDL_COUNT                           (15U)
2951 
2952 /*! @name CMDH - LPADC Command High Buffer Register */
2953 /*! @{ */
2954 
2955 #define ADC_CMDH_CMPEN_MASK                      (0x3U)
2956 #define ADC_CMDH_CMPEN_SHIFT                     (0U)
2957 /*! CMPEN - Compare Function Enable
2958  *  0b00..Compare disabled.
2959  *  0b01..Reserved
2960  *  0b10..Compare enabled. Store on true.
2961  *  0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
2962  */
2963 #define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
2964 
2965 #define ADC_CMDH_LWI_MASK                        (0x80U)
2966 #define ADC_CMDH_LWI_SHIFT                       (7U)
2967 /*! LWI - Loop with Increment
2968  *  0b0..Auto channel increment disabled
2969  *  0b1..Auto channel increment enabled
2970  */
2971 #define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
2972 
2973 #define ADC_CMDH_STS_MASK                        (0x700U)
2974 #define ADC_CMDH_STS_SHIFT                       (8U)
2975 /*! STS - Sample Time Select
2976  *  0b000..Minimum sample time of 3.5 ADCK cycles.
2977  *  0b001..3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time.
2978  *  0b010..3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time.
2979  *  0b011..3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time.
2980  *  0b100..3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time.
2981  *  0b101..3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time.
2982  *  0b110..3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time.
2983  *  0b111..3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
2984  */
2985 #define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
2986 
2987 #define ADC_CMDH_AVGS_MASK                       (0x7000U)
2988 #define ADC_CMDH_AVGS_SHIFT                      (12U)
2989 /*! AVGS - Hardware Average Select
2990  *  0b000..Single conversion.
2991  *  0b001..2 conversions averaged.
2992  *  0b010..4 conversions averaged.
2993  *  0b011..8 conversions averaged.
2994  *  0b100..16 conversions averaged.
2995  *  0b101..32 conversions averaged.
2996  *  0b110..64 conversions averaged.
2997  *  0b111..128 conversions averaged.
2998  */
2999 #define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
3000 
3001 #define ADC_CMDH_LOOP_MASK                       (0xF0000U)
3002 #define ADC_CMDH_LOOP_SHIFT                      (16U)
3003 /*! LOOP - Loop Count Select
3004  *  0b0000..Looping not enabled. Command executes 1 time.
3005  *  0b0001..Loop 1 time. Command executes 2 times.
3006  *  0b0010..Loop 2 times. Command executes 3 times.
3007  *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
3008  *  0b1111..Loop 15 times. Command executes 16 times.
3009  */
3010 #define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
3011 
3012 #define ADC_CMDH_NEXT_MASK                       (0xF000000U)
3013 #define ADC_CMDH_NEXT_SHIFT                      (24U)
3014 /*! NEXT - Next Command Select
3015  *  0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
3016  *          trigger pending, begin command associated with lower priority trigger.
3017  *  0b0001..Select CMD1 command buffer register as next command.
3018  *  0b0010-0b1110..Select corresponding CMD command buffer register as next command
3019  *  0b1111..Select CMD15 command buffer register as next command.
3020  */
3021 #define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
3022 /*! @} */
3023 
3024 /* The count of ADC_CMDH */
3025 #define ADC_CMDH_COUNT                           (15U)
3026 
3027 /*! @name CV - Compare Value Register */
3028 /*! @{ */
3029 
3030 #define ADC_CV_CVL_MASK                          (0xFFFFU)
3031 #define ADC_CV_CVL_SHIFT                         (0U)
3032 /*! CVL - Compare Value Low */
3033 #define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
3034 
3035 #define ADC_CV_CVH_MASK                          (0xFFFF0000U)
3036 #define ADC_CV_CVH_SHIFT                         (16U)
3037 /*! CVH - Compare Value High. */
3038 #define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
3039 /*! @} */
3040 
3041 /* The count of ADC_CV */
3042 #define ADC_CV_COUNT                             (4U)
3043 
3044 /*! @name RESFIFO - LPADC Data Result FIFO Register */
3045 /*! @{ */
3046 
3047 #define ADC_RESFIFO_D_MASK                       (0xFFFFU)
3048 #define ADC_RESFIFO_D_SHIFT                      (0U)
3049 /*! D - Data result */
3050 #define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
3051 
3052 #define ADC_RESFIFO_TSRC_MASK                    (0x70000U)
3053 #define ADC_RESFIFO_TSRC_SHIFT                   (16U)
3054 /*! TSRC - Trigger Source
3055  *  0b000..Trigger source 0 initiated this conversion.
3056  *  0b001..Trigger source 1 initiated this conversion.
3057  *  0b010-0b110..Corresponding trigger source initiated this conversion.
3058  *  0b111..Trigger source 7 initiated this conversion.
3059  */
3060 #define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
3061 
3062 #define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
3063 #define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
3064 /*! LOOPCNT - Loop count value
3065  *  0b0000..Result is from initial conversion in command.
3066  *  0b0001..Result is from second conversion in command.
3067  *  0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
3068  *  0b1111..Result is from 16th conversion in command.
3069  */
3070 #define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
3071 
3072 #define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
3073 #define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
3074 /*! CMDSRC - Command Buffer Source
3075  *  0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
3076  *          prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
3077  *  0b0001..CMD1 buffer used as control settings for this conversion.
3078  *  0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
3079  *  0b1111..CMD15 buffer used as control settings for this conversion.
3080  */
3081 #define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
3082 
3083 #define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
3084 #define ADC_RESFIFO_VALID_SHIFT                  (31U)
3085 /*! VALID - FIFO entry is valid
3086  *  0b0..FIFO is empty. Discard any read from RESFIFO.
3087  *  0b1..FIFO record read from RESFIFO is valid.
3088  */
3089 #define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
3090 /*! @} */
3091 
3092 
3093 /*!
3094  * @}
3095  */ /* end of group ADC_Register_Masks */
3096 
3097 
3098 /* ADC - Peripheral instance base addresses */
3099 /** Peripheral LPADC1 base address */
3100 #define LPADC1_BASE                              (0x40050000u)
3101 /** Peripheral LPADC1 base pointer */
3102 #define LPADC1                                   ((ADC_Type *)LPADC1_BASE)
3103 /** Peripheral LPADC2 base address */
3104 #define LPADC2_BASE                              (0x40054000u)
3105 /** Peripheral LPADC2 base pointer */
3106 #define LPADC2                                   ((ADC_Type *)LPADC2_BASE)
3107 /** Array initializer of ADC peripheral base addresses */
3108 #define ADC_BASE_ADDRS                           { 0u, LPADC1_BASE, LPADC2_BASE }
3109 /** Array initializer of ADC peripheral base pointers */
3110 #define ADC_BASE_PTRS                            { (ADC_Type *)0u, LPADC1, LPADC2 }
3111 /** Interrupt vectors for the ADC peripheral type */
3112 #define ADC_IRQS                                 { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
3113 
3114 /*!
3115  * @}
3116  */ /* end of group ADC_Peripheral_Access_Layer */
3117 
3118 
3119 /* ----------------------------------------------------------------------------
3120    -- ADC_ETC Peripheral Access Layer
3121    ---------------------------------------------------------------------------- */
3122 
3123 /*!
3124  * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer
3125  * @{
3126  */
3127 
3128 /** ADC_ETC - Register Layout Typedef */
3129 typedef struct {
3130   __IO uint32_t CTRL;                              /**< ADC_ETC Global Control Register, offset: 0x0 */
3131   __IO uint32_t DONE0_1_IRQ;                       /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */
3132   __IO uint32_t DONE2_3_ERR_IRQ;                   /**< ETC DONE_2, DONE_3 and DONE_ERR IRQ State Register, offset: 0x8 */
3133   __IO uint32_t DMA_CTRL;                          /**< ETC DMA control Register, offset: 0xC */
3134   struct {                                         /* offset: 0x10, array step: 0x28 */
3135     __IO uint32_t TRIGn_CTRL;                        /**< ETC_TRIG Control Register, array offset: 0x10, array step: 0x28 */
3136     __IO uint32_t TRIGn_COUNTER;                     /**< ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28 */
3137     __IO uint32_t TRIGn_CHAIN_1_0;                   /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */
3138     __IO uint32_t TRIGn_CHAIN_3_2;                   /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */
3139     __IO uint32_t TRIGn_CHAIN_5_4;                   /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */
3140     __IO uint32_t TRIGn_CHAIN_7_6;                   /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */
3141     __I  uint32_t TRIGn_RESULT_1_0;                  /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */
3142     __I  uint32_t TRIGn_RESULT_3_2;                  /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */
3143     __I  uint32_t TRIGn_RESULT_5_4;                  /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */
3144     __I  uint32_t TRIGn_RESULT_7_6;                  /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */
3145   } TRIG[8];
3146 } ADC_ETC_Type;
3147 
3148 /* ----------------------------------------------------------------------------
3149    -- ADC_ETC Register Masks
3150    ---------------------------------------------------------------------------- */
3151 
3152 /*!
3153  * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks
3154  * @{
3155  */
3156 
3157 /*! @name CTRL - ADC_ETC Global Control Register */
3158 /*! @{ */
3159 
3160 #define ADC_ETC_CTRL_TRIG_ENABLE_MASK            (0xFFU)
3161 #define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT           (0U)
3162 /*! TRIG_ENABLE
3163  *  0b00000000..disable all 8 external XBAR triggers.
3164  *  0b00000001..enable external XBAR trigger0.
3165  *  0b00000010..enable external XBAR trigger1.
3166  *  0b00000011..enable external XBAR trigger0 and trigger1.
3167  *  0b11111111..enable all 8 external XBAR triggers.
3168  */
3169 #define ADC_ETC_CTRL_TRIG_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
3170 
3171 #define ADC_ETC_CTRL_PRE_DIVIDER_MASK            (0xFF0000U)
3172 #define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT           (16U)
3173 #define ADC_ETC_CTRL_PRE_DIVIDER(x)              (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
3174 
3175 #define ADC_ETC_CTRL_DMA_MODE_SEL_MASK           (0x20000000U)
3176 #define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT          (29U)
3177 /*! DMA_MODE_SEL
3178  *  0b0..Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared.
3179  *  0b1..Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only.
3180  */
3181 #define ADC_ETC_CTRL_DMA_MODE_SEL(x)             (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
3182 
3183 #define ADC_ETC_CTRL_SOFTRST_MASK                (0x80000000U)
3184 #define ADC_ETC_CTRL_SOFTRST_SHIFT               (31U)
3185 /*! SOFTRST
3186  *  0b0..ADC_ETC works normally.
3187  *  0b1..All registers inside ADC_ETC will be reset to the default value.
3188  */
3189 #define ADC_ETC_CTRL_SOFTRST(x)                  (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
3190 /*! @} */
3191 
3192 /*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */
3193 /*! @{ */
3194 
3195 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK     (0x1U)
3196 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT    (0U)
3197 /*! TRIG0_DONE0
3198  *  0b0..No TRIG0_DONE0 interrupt detected
3199  *  0b1..TRIG0_DONE0 interrupt detected
3200  */
3201 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
3202 
3203 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK     (0x2U)
3204 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT    (1U)
3205 /*! TRIG1_DONE0
3206  *  0b0..No TRIG1_DONE0 interrupt detected
3207  *  0b1..TRIG1_DONE0 interrupt detected
3208  */
3209 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
3210 
3211 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK     (0x4U)
3212 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT    (2U)
3213 /*! TRIG2_DONE0
3214  *  0b0..No TRIG2_DONE0 interrupt detected
3215  *  0b1..TRIG2_DONE0 interrupt detected
3216  */
3217 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
3218 
3219 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK     (0x8U)
3220 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT    (3U)
3221 /*! TRIG3_DONE0
3222  *  0b0..No TRIG3_DONE0 interrupt detected
3223  *  0b1..TRIG3_DONE0 interrupt detected
3224  */
3225 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
3226 
3227 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK     (0x10U)
3228 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT    (4U)
3229 /*! TRIG4_DONE0
3230  *  0b0..No TRIG4_DONE0 interrupt detected
3231  *  0b1..TRIG4_DONE0 interrupt detected
3232  */
3233 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
3234 
3235 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK     (0x20U)
3236 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT    (5U)
3237 /*! TRIG5_DONE0
3238  *  0b0..No TRIG5_DONE0 interrupt detected
3239  *  0b1..TRIG5_DONE0 interrupt detected
3240  */
3241 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
3242 
3243 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK     (0x40U)
3244 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT    (6U)
3245 /*! TRIG6_DONE0
3246  *  0b0..No TRIG6_DONE0 interrupt detected
3247  *  0b1..TRIG6_DONE0 interrupt detected
3248  */
3249 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
3250 
3251 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK     (0x80U)
3252 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT    (7U)
3253 /*! TRIG7_DONE0
3254  *  0b0..No TRIG7_DONE0 interrupt detected
3255  *  0b1..TRIG7_DONE0 interrupt detected
3256  */
3257 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
3258 
3259 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK     (0x10000U)
3260 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT    (16U)
3261 /*! TRIG0_DONE1
3262  *  0b0..No TRIG0_DONE1 interrupt detected
3263  *  0b1..TRIG0_DONE1 interrupt detected
3264  */
3265 #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
3266 
3267 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK     (0x20000U)
3268 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT    (17U)
3269 /*! TRIG1_DONE1
3270  *  0b0..No TRIG1_DONE1 interrupt detected
3271  *  0b1..TRIG1_DONE1 interrupt detected
3272  */
3273 #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
3274 
3275 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK     (0x40000U)
3276 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT    (18U)
3277 /*! TRIG2_DONE1
3278  *  0b0..No TRIG2_DONE1 interrupt detected
3279  *  0b1..TRIG2_DONE1 interrupt detected
3280  */
3281 #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
3282 
3283 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK     (0x80000U)
3284 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT    (19U)
3285 /*! TRIG3_DONE1
3286  *  0b0..No TRIG3_DONE1 interrupt detected
3287  *  0b1..TRIG3_DONE1 interrupt detected
3288  */
3289 #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
3290 
3291 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK     (0x100000U)
3292 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT    (20U)
3293 /*! TRIG4_DONE1
3294  *  0b0..No TRIG4_DONE1 interrupt detected
3295  *  0b1..TRIG4_DONE1 interrupt detected
3296  */
3297 #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
3298 
3299 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK     (0x200000U)
3300 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT    (21U)
3301 /*! TRIG5_DONE1
3302  *  0b0..No TRIG5_DONE1 interrupt detected
3303  *  0b1..TRIG5_DONE1 interrupt detected
3304  */
3305 #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
3306 
3307 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK     (0x400000U)
3308 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT    (22U)
3309 /*! TRIG6_DONE1
3310  *  0b0..No TRIG6_DONE1 interrupt detected
3311  *  0b1..TRIG6_DONE1 interrupt detected
3312  */
3313 #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
3314 
3315 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK     (0x800000U)
3316 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT    (23U)
3317 /*! TRIG7_DONE1
3318  *  0b0..No TRIG7_DONE1 interrupt detected
3319  *  0b1..TRIG7_DONE1 interrupt detected
3320  */
3321 #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x)       (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
3322 /*! @} */
3323 
3324 /*! @name DONE2_3_ERR_IRQ - ETC DONE_2, DONE_3 and DONE_ERR IRQ State Register */
3325 /*! @{ */
3326 
3327 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
3328 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
3329 /*! TRIG0_DONE2
3330  *  0b0..No TRIG0_DONE2 interrupt detected
3331  *  0b1..TRIG0_DONE2 interrupt detected
3332  */
3333 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK)
3334 
3335 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
3336 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
3337 /*! TRIG1_DONE2
3338  *  0b0..No TRIG1_DONE2 interrupt detected
3339  *  0b1..TRIG1_DONE2 interrupt detected
3340  */
3341 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK)
3342 
3343 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
3344 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
3345 /*! TRIG2_DONE2
3346  *  0b0..No TRIG2_DONE2 interrupt detected
3347  *  0b1..TRIG2_DONE2 interrupt detected
3348  */
3349 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK)
3350 
3351 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
3352 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
3353 /*! TRIG3_DONE2
3354  *  0b0..No TRIG3_DONE2 interrupt detected
3355  *  0b1..TRIG3_DONE2 interrupt detected
3356  */
3357 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK)
3358 
3359 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
3360 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
3361 /*! TRIG4_DONE2
3362  *  0b0..No TRIG4_DONE2 interrupt detected
3363  *  0b1..TRIG4_DONE2 interrupt detected
3364  */
3365 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK)
3366 
3367 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
3368 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
3369 /*! TRIG5_DONE2
3370  *  0b0..No TRIG5_DONE2 interrupt detected
3371  *  0b1..TRIG5_DONE2 interrupt detected
3372  */
3373 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK)
3374 
3375 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
3376 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
3377 /*! TRIG6_DONE2
3378  *  0b0..No TRIG6_DONE2 interrupt detected
3379  *  0b1..TRIG6_DONE2 interrupt detected
3380  */
3381 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK)
3382 
3383 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
3384 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
3385 /*! TRIG7_DONE2
3386  *  0b0..No TRIG7_DONE2 interrupt detected
3387  *  0b1..TRIG7_DONE2 interrupt detected
3388  */
3389 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK)
3390 
3391 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK (0x100U)
3392 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_SHIFT (8U)
3393 /*! TRIG0_DONE3
3394  *  0b0..No TRIG0_DONE3 interrupt detected
3395  *  0b1..TRIG0_DONE3 interrupt detected
3396  */
3397 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK)
3398 
3399 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_MASK (0x200U)
3400 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_SHIFT (9U)
3401 /*! TRIG1_DONE3
3402  *  0b0..No TRIG1_DONE3 interrupt detected
3403  *  0b1..TRIG1_DONE3 interrupt detected
3404  */
3405 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_MASK)
3406 
3407 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_MASK (0x400U)
3408 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_SHIFT (10U)
3409 /*! TRIG2_DONE3
3410  *  0b0..No TRIG2_DONE3 interrupt detected
3411  *  0b1..TRIG2_DONE3 interrupt detected
3412  */
3413 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_MASK)
3414 
3415 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_MASK (0x800U)
3416 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_SHIFT (11U)
3417 /*! TRIG3_DONE3
3418  *  0b0..No TRIG3_DONE3 interrupt detected
3419  *  0b1..TRIG3_DONE3 interrupt detected
3420  */
3421 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_MASK)
3422 
3423 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_MASK (0x1000U)
3424 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_SHIFT (12U)
3425 /*! TRIG4_DONE3
3426  *  0b0..No TRIG4_DONE3 interrupt detected
3427  *  0b1..TRIG4_DONE3 interrupt detected
3428  */
3429 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_MASK)
3430 
3431 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_MASK (0x2000U)
3432 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_SHIFT (13U)
3433 /*! TRIG5_DONE3
3434  *  0b0..No TRIG5_DONE3 interrupt detected
3435  *  0b1..TRIG5_DONE3 interrupt detected
3436  */
3437 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_MASK)
3438 
3439 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_MASK (0x4000U)
3440 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_SHIFT (14U)
3441 /*! TRIG6_DONE3
3442  *  0b0..No TRIG6_DONE3 interrupt detected
3443  *  0b1..TRIG6_DONE3 interrupt detected
3444  */
3445 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_MASK)
3446 
3447 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_MASK (0x8000U)
3448 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_SHIFT (15U)
3449 /*! TRIG7_DONE3
3450  *  0b0..No TRIG7_DONE3 interrupt detected
3451  *  0b1..TRIG7_DONE3 interrupt detected
3452  */
3453 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_MASK)
3454 
3455 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK   (0x10000U)
3456 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT  (16U)
3457 /*! TRIG0_ERR
3458  *  0b0..No TRIG0_ERR interrupt detected
3459  *  0b1..TRIG0_ERR interrupt detected
3460  */
3461 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK)
3462 
3463 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK   (0x20000U)
3464 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT  (17U)
3465 /*! TRIG1_ERR
3466  *  0b0..No TRIG1_ERR interrupt detected
3467  *  0b1..TRIG1_ERR interrupt detected
3468  */
3469 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK)
3470 
3471 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK   (0x40000U)
3472 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT  (18U)
3473 /*! TRIG2_ERR
3474  *  0b0..No TRIG2_ERR interrupt detected
3475  *  0b1..TRIG2_ERR interrupt detected
3476  */
3477 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK)
3478 
3479 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK   (0x80000U)
3480 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT  (19U)
3481 /*! TRIG3_ERR
3482  *  0b0..No TRIG3_ERR interrupt detected
3483  *  0b1..TRIG3_ERR interrupt detected
3484  */
3485 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK)
3486 
3487 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK   (0x100000U)
3488 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT  (20U)
3489 /*! TRIG4_ERR
3490  *  0b0..No TRIG4_ERR interrupt detected
3491  *  0b1..TRIG4_ERR interrupt detected
3492  */
3493 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK)
3494 
3495 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK   (0x200000U)
3496 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT  (21U)
3497 /*! TRIG5_ERR
3498  *  0b0..No TRIG5_ERR interrupt detected
3499  *  0b1..TRIG5_ERR interrupt detected
3500  */
3501 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK)
3502 
3503 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK   (0x400000U)
3504 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT  (22U)
3505 /*! TRIG6_ERR
3506  *  0b0..No TRIG6_ERR interrupt detected
3507  *  0b1..TRIG6_ERR interrupt detected
3508  */
3509 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK)
3510 
3511 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK   (0x800000U)
3512 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT  (23U)
3513 /*! TRIG7_ERR
3514  *  0b0..No TRIG7_ERR interrupt detected
3515  *  0b1..TRIG7_ERR interrupt detected
3516  */
3517 #define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR(x)     (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK)
3518 /*! @} */
3519 
3520 /*! @name DMA_CTRL - ETC DMA control Register */
3521 /*! @{ */
3522 
3523 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK       (0x1U)
3524 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT      (0U)
3525 /*! TRIG0_ENABLE
3526  *  0b0..TRIG0 DMA request disabled.
3527  *  0b1..TRIG0 DMA request enabled.
3528  */
3529 #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
3530 
3531 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK       (0x2U)
3532 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT      (1U)
3533 /*! TRIG1_ENABLE
3534  *  0b0..TRIG1 DMA request disabled.
3535  *  0b1..TRIG1 DMA request enabled.
3536  */
3537 #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
3538 
3539 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK       (0x4U)
3540 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT      (2U)
3541 /*! TRIG2_ENABLE
3542  *  0b0..TRIG2 DMA request disabled.
3543  *  0b1..TRIG2 DMA request enabled.
3544  */
3545 #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
3546 
3547 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK       (0x8U)
3548 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT      (3U)
3549 /*! TRIG3_ENABLE
3550  *  0b0..TRIG3 DMA request disabled.
3551  *  0b1..TRIG3 DMA request enabled.
3552  */
3553 #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
3554 
3555 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK       (0x10U)
3556 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT      (4U)
3557 /*! TRIG4_ENABLE
3558  *  0b0..TRIG4 DMA request disabled.
3559  *  0b1..TRIG4 DMA request enabled.
3560  */
3561 #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
3562 
3563 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK       (0x20U)
3564 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT      (5U)
3565 /*! TRIG5_ENABLE
3566  *  0b0..TRIG5 DMA request disabled.
3567  *  0b1..TRIG5 DMA request enabled.
3568  */
3569 #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
3570 
3571 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK       (0x40U)
3572 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT      (6U)
3573 /*! TRIG6_ENABLE
3574  *  0b0..TRIG6 DMA request disabled.
3575  *  0b1..TRIG6 DMA request enabled.
3576  */
3577 #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
3578 
3579 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK       (0x80U)
3580 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT      (7U)
3581 /*! TRIG7_ENABLE
3582  *  0b0..TRIG7 DMA request disabled.
3583  *  0b1..TRIG7 DMA request enabled.
3584  */
3585 #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
3586 
3587 #define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK          (0x10000U)
3588 #define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT         (16U)
3589 /*! TRIG0_REQ
3590  *  0b0..TRIG0_REQ not detected.
3591  *  0b1..TRIG0_REQ detected.
3592  */
3593 #define ADC_ETC_DMA_CTRL_TRIG0_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
3594 
3595 #define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK          (0x20000U)
3596 #define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT         (17U)
3597 /*! TRIG1_REQ
3598  *  0b0..TRIG1_REQ not detected.
3599  *  0b1..TRIG1_REQ detected.
3600  */
3601 #define ADC_ETC_DMA_CTRL_TRIG1_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
3602 
3603 #define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK          (0x40000U)
3604 #define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT         (18U)
3605 /*! TRIG2_REQ
3606  *  0b0..TRIG2_REQ not detected.
3607  *  0b1..TRIG2_REQ detected.
3608  */
3609 #define ADC_ETC_DMA_CTRL_TRIG2_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
3610 
3611 #define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK          (0x80000U)
3612 #define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT         (19U)
3613 /*! TRIG3_REQ
3614  *  0b0..TRIG3_REQ not detected.
3615  *  0b1..TRIG3_REQ detected.
3616  */
3617 #define ADC_ETC_DMA_CTRL_TRIG3_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
3618 
3619 #define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK          (0x100000U)
3620 #define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT         (20U)
3621 /*! TRIG4_REQ
3622  *  0b0..TRIG4_REQ not detected.
3623  *  0b1..TRIG4_REQ detected.
3624  */
3625 #define ADC_ETC_DMA_CTRL_TRIG4_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
3626 
3627 #define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK          (0x200000U)
3628 #define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT         (21U)
3629 /*! TRIG5_REQ
3630  *  0b0..TRIG5_REQ not detected.
3631  *  0b1..TRIG5_REQ detected.
3632  */
3633 #define ADC_ETC_DMA_CTRL_TRIG5_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
3634 
3635 #define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK          (0x400000U)
3636 #define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT         (22U)
3637 /*! TRIG6_REQ
3638  *  0b0..TRIG6_REQ not detected.
3639  *  0b1..TRIG6_REQ detected.
3640  */
3641 #define ADC_ETC_DMA_CTRL_TRIG6_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
3642 
3643 #define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK          (0x800000U)
3644 #define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT         (23U)
3645 /*! TRIG7_REQ
3646  *  0b0..TRIG7_REQ not detected.
3647  *  0b1..TRIG7_REQ detected.
3648  */
3649 #define ADC_ETC_DMA_CTRL_TRIG7_REQ(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
3650 /*! @} */
3651 
3652 /*! @name TRIGn_CTRL - ETC_TRIG Control Register */
3653 /*! @{ */
3654 
3655 #define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK          (0x1U)
3656 #define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT         (0U)
3657 /*! SW_TRIG
3658  *  0b0..No software trigger event generated.
3659  *  0b1..Software trigger event generated.
3660  */
3661 #define ADC_ETC_TRIGn_CTRL_SW_TRIG(x)            (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
3662 
3663 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK        (0x10U)
3664 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT       (4U)
3665 /*! TRIG_MODE
3666  *  0b0..Hardware trigger. The softerware trigger will be ignored.
3667  *  0b1..Software trigger. The hardware trigger will be ignored.
3668  */
3669 #define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
3670 
3671 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK       (0x700U)
3672 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT      (8U)
3673 /*! TRIG_CHAIN
3674  *  0b000..Trigger chain length is 1
3675  *  0b001..Trigger chain length is 2
3676  *  0b010..Trigger chain length is 3
3677  *  0b011..Trigger chain length is 4
3678  *  0b100..Trigger chain length is 5
3679  *  0b101..Trigger chain length is 6
3680  *  0b110..Trigger chain length is 7
3681  *  0b111..Trigger chain length is 8
3682  */
3683 #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
3684 
3685 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK    (0x7000U)
3686 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT   (12U)
3687 #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
3688 
3689 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK        (0x10000U)
3690 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT       (16U)
3691 /*! SYNC_MODE
3692  *  0b0..Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently.
3693  *  0b1..Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously.
3694  */
3695 #define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
3696 
3697 #define ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK      (0xFF000000U)
3698 #define ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT     (24U)
3699 /*! CHAINx_DONE
3700  *  0b00000000..segment x done not detected.
3701  *  0b00000001..segment x done detected.
3702  */
3703 #define ADC_ETC_TRIGn_CTRL_CHAINx_DONE(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT)) & ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK)
3704 /*! @} */
3705 
3706 /* The count of ADC_ETC_TRIGn_CTRL */
3707 #define ADC_ETC_TRIGn_CTRL_COUNT                 (8U)
3708 
3709 /*! @name TRIGn_COUNTER - ETC_TRIG Counter Register */
3710 /*! @{ */
3711 
3712 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK    (0xFFFFU)
3713 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT   (0U)
3714 #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x)      (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
3715 
3716 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
3717 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
3718 #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
3719 /*! @} */
3720 
3721 /* The count of ADC_ETC_TRIGn_COUNTER */
3722 #define ADC_ETC_TRIGn_COUNTER_COUNT              (8U)
3723 
3724 /*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */
3725 /*! @{ */
3726 
3727 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK       (0xFU)
3728 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT      (0U)
3729 /*! CSEL0
3730  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
3731  *  0b0001..ADC CMD1 selected.
3732  *  0b0010..ADC CMD2 selected.
3733  *  0b0011..ADC CMD3 selected.
3734  *  0b0100..ADC CMD4 selected.
3735  *  0b0101..ADC CMD5 selected.
3736  *  0b0110..ADC CMD6 selected.
3737  *  0b0111..ADC CMD7 selected.
3738  *  0b1000..ADC CMD8 selected.
3739  *  0b1001..ADC CMD9 selected.
3740  *  0b1010..ADC CMD10 selected.
3741  *  0b1011..ADC CMD11 selected.
3742  *  0b1100..ADC CMD12 selected.
3743  *  0b1101..ADC CMD13 selected.
3744  *  0b1110..ADC CMD14 selected.
3745  *  0b1111..ADC CMD15 selected.
3746  */
3747 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
3748 
3749 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK       (0xFF0U)
3750 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT      (4U)
3751 /*! HWTS0
3752  *  0b00000000..no trigger selected
3753  *  0b00000001..ADC TRIG0 selected
3754  *  0b00000010..ADC TRIG1 selected
3755  *  0b00000100..ADC TRIG2 selected
3756  *  0b00001000..ADC TRIG3 selected
3757  *  0b00010000..ADC TRIG4 selected
3758  *  0b00100000..ADC TRIG5 selected
3759  *  0b01000000..ADC TRIG6 selected
3760  *  0b10000000..ADC TRIG7 selected
3761  */
3762 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
3763 
3764 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK        (0x1000U)
3765 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT       (12U)
3766 /*! B2B0
3767  *  0b0..Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached
3768  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
3769  */
3770 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
3771 
3772 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK         (0x6000U)
3773 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT        (13U)
3774 /*! IE0
3775  *  0b00..Generate interrupt on Done0 when segment 0 finish.
3776  *  0b01..Generate interrupt on Done1 when segment 0 finish.
3777  *  0b10..Generate interrupt on Done2 when segment 0 finish.
3778  *  0b11..Generate interrupt on Done3 when segment 0 finish.
3779  */
3780 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
3781 
3782 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK      (0x8000U)
3783 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT     (15U)
3784 /*! IE0_EN
3785  *  0b0..Interrupt DONE disabled.
3786  *  0b1..Interrupt DONE enabled. When segment 0 finish, an interrupt will be generated on the specific port configured by the IE0.
3787  */
3788 #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK)
3789 
3790 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK       (0xF0000U)
3791 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT      (16U)
3792 /*! CSEL1
3793  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
3794  *  0b0001..ADC CMD1 selected.
3795  *  0b0010..ADC CMD2 selected.
3796  *  0b0011..ADC CMD3 selected.
3797  *  0b0100..ADC CMD4 selected.
3798  *  0b0101..ADC CMD5 selected.
3799  *  0b0110..ADC CMD6 selected.
3800  *  0b0111..ADC CMD7 selected.
3801  *  0b1000..ADC CMD8 selected.
3802  *  0b1001..ADC CMD9 selected.
3803  *  0b1010..ADC CMD10 selected.
3804  *  0b1011..ADC CMD11 selected.
3805  *  0b1100..ADC CMD12 selected.
3806  *  0b1101..ADC CMD13 selected.
3807  *  0b1110..ADC CMD14 selected.
3808  *  0b1111..ADC CMD15 selected.
3809  */
3810 #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
3811 
3812 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK       (0xFF00000U)
3813 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT      (20U)
3814 /*! HWTS1
3815  *  0b00000000..no trigger selected
3816  *  0b00000001..ADC TRIG0 selected
3817  *  0b00000010..ADC TRIG1 selected
3818  *  0b00000100..ADC TRIG2 selected
3819  *  0b00001000..ADC TRIG3 selected
3820  *  0b00010000..ADC TRIG4 selected
3821  *  0b00100000..ADC TRIG5 selected
3822  *  0b01000000..ADC TRIG6 selected
3823  *  0b10000000..ADC TRIG7 selected
3824  */
3825 #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
3826 
3827 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK        (0x10000000U)
3828 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT       (28U)
3829 /*! B2B1
3830  *  0b0..Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached
3831  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
3832  */
3833 #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
3834 
3835 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK         (0x60000000U)
3836 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT        (29U)
3837 /*! IE1
3838  *  0b00..Generate interrupt on Done0 when Segment 1 finish.
3839  *  0b01..Generate interrupt on Done1 when Segment 1 finish.
3840  *  0b10..Generate interrupt on Done2 when Segment 1 finish.
3841  *  0b11..Generate interrupt on Done3 when Segment 1 finish.
3842  */
3843 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
3844 
3845 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK      (0x80000000U)
3846 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT     (31U)
3847 /*! IE1_EN
3848  *  0b0..Interrupt DONE disabled.
3849  *  0b1..Interrupt DONE enabled. When segment 1 finish, an interrupt will be generated on the specific port configured by the IE1.
3850  */
3851 #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK)
3852 /*! @} */
3853 
3854 /* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
3855 #define ADC_ETC_TRIGn_CHAIN_1_0_COUNT            (8U)
3856 
3857 /*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */
3858 /*! @{ */
3859 
3860 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK       (0xFU)
3861 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT      (0U)
3862 /*! CSEL2
3863  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
3864  *  0b0001..ADC CMD1 selected.
3865  *  0b0010..ADC CMD2 selected.
3866  *  0b0011..ADC CMD3 selected.
3867  *  0b0100..ADC CMD4 selected.
3868  *  0b0101..ADC CMD5 selected.
3869  *  0b0110..ADC CMD6 selected.
3870  *  0b0111..ADC CMD7 selected.
3871  *  0b1000..ADC CMD8 selected.
3872  *  0b1001..ADC CMD9 selected.
3873  *  0b1010..ADC CMD10 selected.
3874  *  0b1011..ADC CMD11 selected.
3875  *  0b1100..ADC CMD12 selected.
3876  *  0b1101..ADC CMD13 selected.
3877  *  0b1110..ADC CMD14 selected.
3878  *  0b1111..ADC CMD15 selected.
3879  */
3880 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
3881 
3882 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK       (0xFF0U)
3883 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT      (4U)
3884 /*! HWTS2
3885  *  0b00000000..no trigger selected
3886  *  0b00000001..ADC TRIG0 selected
3887  *  0b00000010..ADC TRIG1 selected
3888  *  0b00000100..ADC TRIG2 selected
3889  *  0b00001000..ADC TRIG3 selected
3890  *  0b00010000..ADC TRIG4 selected
3891  *  0b00100000..ADC TRIG5 selected
3892  *  0b01000000..ADC TRIG6 selected
3893  *  0b10000000..ADC TRIG7 selected
3894  */
3895 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
3896 
3897 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK        (0x1000U)
3898 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT       (12U)
3899 /*! B2B2
3900  *  0b0..Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached
3901  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
3902  */
3903 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
3904 
3905 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK         (0x6000U)
3906 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT        (13U)
3907 /*! IE2
3908  *  0b00..Generate interrupt on Done0 when segment 2 finish.
3909  *  0b01..Generate interrupt on Done1 when segment 2 finish.
3910  *  0b10..Generate interrupt on Done2 when segment 2 finish.
3911  *  0b11..Generate interrupt on Done3 when segment 2 finish.
3912  */
3913 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
3914 
3915 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK      (0x8000U)
3916 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT     (15U)
3917 /*! IE2_EN
3918  *  0b0..Interrupt DONE disabled.
3919  *  0b1..Interrupt DONE enabled. When segment 2 finish, an interrupt will be generated on the specific port configured by the IE2.
3920  */
3921 #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK)
3922 
3923 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK       (0xF0000U)
3924 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT      (16U)
3925 /*! CSEL3
3926  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
3927  *  0b0001..ADC CMD1 selected.
3928  *  0b0010..ADC CMD2 selected.
3929  *  0b0011..ADC CMD3 selected.
3930  *  0b0100..ADC CMD4 selected.
3931  *  0b0101..ADC CMD5 selected.
3932  *  0b0110..ADC CMD6 selected.
3933  *  0b0111..ADC CMD7 selected.
3934  *  0b1000..ADC CMD8 selected.
3935  *  0b1001..ADC CMD9 selected.
3936  *  0b1010..ADC CMD10 selected.
3937  *  0b1011..ADC CMD11 selected.
3938  *  0b1100..ADC CMD12 selected.
3939  *  0b1101..ADC CMD13 selected.
3940  *  0b1110..ADC CMD14 selected.
3941  *  0b1111..ADC CMD15 selected.
3942  */
3943 #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
3944 
3945 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK       (0xFF00000U)
3946 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT      (20U)
3947 /*! HWTS3
3948  *  0b00000000..no trigger selected
3949  *  0b00000001..ADC TRIG0 selected
3950  *  0b00000010..ADC TRIG1 selected
3951  *  0b00000100..ADC TRIG2 selected
3952  *  0b00001000..ADC TRIG3 selected
3953  *  0b00010000..ADC TRIG4 selected
3954  *  0b00100000..ADC TRIG5 selected
3955  *  0b01000000..ADC TRIG6 selected
3956  *  0b10000000..ADC TRIG7 selected
3957  */
3958 #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
3959 
3960 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK        (0x10000000U)
3961 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT       (28U)
3962 /*! B2B3
3963  *  0b0..Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached
3964  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
3965  */
3966 #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
3967 
3968 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK         (0x60000000U)
3969 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT        (29U)
3970 /*! IE3
3971  *  0b00..Generate interrupt on Done0 when segment 3 finish.
3972  *  0b01..Generate interrupt on Done1 when segment 3 finish.
3973  *  0b10..Generate interrupt on Done2 when segment 3 finish.
3974  *  0b11..Generate interrupt on Done3 when segment 3 finish.
3975  */
3976 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
3977 
3978 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK      (0x80000000U)
3979 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT     (31U)
3980 /*! IE3_EN
3981  *  0b0..Interrupt DONE disabled.
3982  *  0b1..Interrupt DONE enabled. When segment 3 finish, an interrupt will be generated on the specific port configured by the IE3.
3983  */
3984 #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK)
3985 /*! @} */
3986 
3987 /* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
3988 #define ADC_ETC_TRIGn_CHAIN_3_2_COUNT            (8U)
3989 
3990 /*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */
3991 /*! @{ */
3992 
3993 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK       (0xFU)
3994 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT      (0U)
3995 /*! CSEL4
3996  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
3997  *  0b0001..ADC CMD1 selected.
3998  *  0b0010..ADC CMD2 selected.
3999  *  0b0011..ADC CMD3 selected.
4000  *  0b0100..ADC CMD4 selected.
4001  *  0b0101..ADC CMD5 selected.
4002  *  0b0110..ADC CMD6 selected.
4003  *  0b0111..ADC CMD7 selected.
4004  *  0b1000..ADC CMD8 selected.
4005  *  0b1001..ADC CMD9 selected.
4006  *  0b1010..ADC CMD10 selected.
4007  *  0b1011..ADC CMD11 selected.
4008  *  0b1100..ADC CMD12 selected.
4009  *  0b1101..ADC CMD13 selected.
4010  *  0b1110..ADC CMD14 selected.
4011  *  0b1111..ADC CMD15 selected.
4012  */
4013 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
4014 
4015 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK       (0xFF0U)
4016 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT      (4U)
4017 /*! HWTS4
4018  *  0b00000000..no trigger selected
4019  *  0b00000001..ADC TRIG0 selected
4020  *  0b00000010..ADC TRIG1 selected
4021  *  0b00000100..ADC TRIG2 selected
4022  *  0b00001000..ADC TRIG3 selected
4023  *  0b00010000..ADC TRIG4 selected
4024  *  0b00100000..ADC TRIG5 selected
4025  *  0b01000000..ADC TRIG6 selected
4026  *  0b10000000..ADC TRIG7 selected
4027  */
4028 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
4029 
4030 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK        (0x1000U)
4031 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT       (12U)
4032 /*! B2B4
4033  *  0b0..Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached
4034  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
4035  */
4036 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
4037 
4038 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK         (0x6000U)
4039 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT        (13U)
4040 /*! IE4
4041  *  0b00..Generate interrupt on Done0 when segment 4 finish.
4042  *  0b01..Generate interrupt on Done1 when segment 4 finish.
4043  *  0b10..Generate interrupt on Done2 when segment 4 finish.
4044  *  0b11..Generate interrupt on Done3 when segment 4 finish.
4045  */
4046 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
4047 
4048 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK      (0x8000U)
4049 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT     (15U)
4050 /*! IE4_EN
4051  *  0b0..Interrupt DONE disabled.
4052  *  0b1..Interrupt DONE enabled. When segment 4 finish, an interrupt will be generated on the specific port configured by the IE4.
4053  */
4054 #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK)
4055 
4056 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK       (0xF0000U)
4057 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT      (16U)
4058 /*! CSEL5
4059  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
4060  *  0b0001..ADC CMD1 selected.
4061  *  0b0010..ADC CMD2 selected.
4062  *  0b0011..ADC CMD3 selected.
4063  *  0b0100..ADC CMD4 selected.
4064  *  0b0101..ADC CMD5 selected.
4065  *  0b0110..ADC CMD6 selected.
4066  *  0b0111..ADC CMD7 selected.
4067  *  0b1000..ADC CMD8 selected.
4068  *  0b1001..ADC CMD9 selected.
4069  *  0b1010..ADC CMD10 selected.
4070  *  0b1011..ADC CMD11 selected.
4071  *  0b1100..ADC CMD12 selected.
4072  *  0b1101..ADC CMD13 selected.
4073  *  0b1110..ADC CMD14 selected.
4074  *  0b1111..ADC CMD15 selected.
4075  */
4076 #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
4077 
4078 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK       (0xFF00000U)
4079 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT      (20U)
4080 /*! HWTS5
4081  *  0b00000000..no trigger selected
4082  *  0b00000001..ADC TRIG0 selected
4083  *  0b00000010..ADC TRIG1 selected
4084  *  0b00000100..ADC TRIG2 selected
4085  *  0b00001000..ADC TRIG3 selected
4086  *  0b00010000..ADC TRIG4 selected
4087  *  0b00100000..ADC TRIG5 selected
4088  *  0b01000000..ADC TRIG6 selected
4089  *  0b10000000..ADC TRIG7 selected
4090  */
4091 #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
4092 
4093 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK        (0x10000000U)
4094 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT       (28U)
4095 /*! B2B5
4096  *  0b0..Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached
4097  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
4098  */
4099 #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
4100 
4101 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK         (0x60000000U)
4102 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT        (29U)
4103 /*! IE5
4104  *  0b00..Generate interrupt on Done0 when segment 5 finish.
4105  *  0b01..Generate interrupt on Done1 when segment 5 finish.
4106  *  0b10..Generate interrupt on Done2 when segment 5 finish.
4107  *  0b11..Generate interrupt on Done3 when segment 5 finish.
4108  */
4109 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
4110 
4111 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK      (0x80000000U)
4112 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT     (31U)
4113 /*! IE5_EN
4114  *  0b0..Interrupt DONE disabled.
4115  *  0b1..Interrupt DONE enabled. When segment 5 finish, an interrupt will be generated on the specific port configured by the IE5.
4116  */
4117 #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK)
4118 /*! @} */
4119 
4120 /* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
4121 #define ADC_ETC_TRIGn_CHAIN_5_4_COUNT            (8U)
4122 
4123 /*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */
4124 /*! @{ */
4125 
4126 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK       (0xFU)
4127 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT      (0U)
4128 /*! CSEL6
4129  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
4130  *  0b0001..ADC CMD1 selected.
4131  *  0b0010..ADC CMD2 selected.
4132  *  0b0011..ADC CMD3 selected.
4133  *  0b0100..ADC CMD4 selected.
4134  *  0b0101..ADC CMD5 selected.
4135  *  0b0110..ADC CMD6 selected.
4136  *  0b0111..ADC CMD7 selected.
4137  *  0b1000..ADC CMD8 selected.
4138  *  0b1001..ADC CMD9 selected.
4139  *  0b1010..ADC CMD10 selected.
4140  *  0b1011..ADC CMD11 selected.
4141  *  0b1100..ADC CMD12 selected.
4142  *  0b1101..ADC CMD13 selected.
4143  *  0b1110..ADC CMD14 selected.
4144  *  0b1111..ADC CMD15 selected.
4145  */
4146 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
4147 
4148 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK       (0xFF0U)
4149 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT      (4U)
4150 /*! HWTS6
4151  *  0b00000000..no trigger selected
4152  *  0b00000001..ADC TRIG0 selected
4153  *  0b00000010..ADC TRIG1 selected
4154  *  0b00000100..ADC TRIG2 selected
4155  *  0b00001000..ADC TRIG3 selected
4156  *  0b00010000..ADC TRIG4 selected
4157  *  0b00100000..ADC TRIG5 selected
4158  *  0b01000000..ADC TRIG6 selected
4159  *  0b10000000..ADC TRIG7 selected
4160  */
4161 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
4162 
4163 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK        (0x1000U)
4164 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT       (12U)
4165 /*! B2B6
4166  *  0b0..Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached
4167  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
4168  */
4169 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
4170 
4171 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK         (0x6000U)
4172 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT        (13U)
4173 /*! IE6
4174  *  0b00..Generate interrupt on Done0 when segment 6 finish.
4175  *  0b01..Generate interrupt on Done1 when segment 6 finish.
4176  *  0b10..Generate interrupt on Done2 when segment 6 finish.
4177  *  0b11..Generate interrupt on Done3 when segment 6 finish.
4178  */
4179 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
4180 
4181 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK      (0x8000U)
4182 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT     (15U)
4183 /*! IE6_EN
4184  *  0b0..Interrupt DONE disabled.
4185  *  0b1..Interrupt DONE enabled. When segment 6 finish, an interrupt will be generated on the specific port configured by the IE6.
4186  */
4187 #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK)
4188 
4189 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK       (0xF0000U)
4190 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT      (16U)
4191 /*! CSEL7
4192  *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
4193  *  0b0001..ADC CMD1 selected.
4194  *  0b0010..ADC CMD2 selected.
4195  *  0b0011..ADC CMD3 selected.
4196  *  0b0100..ADC CMD4 selected.
4197  *  0b0101..ADC CMD5 selected.
4198  *  0b0110..ADC CMD6 selected.
4199  *  0b0111..ADC CMD7 selected.
4200  *  0b1000..ADC CMD8 selected.
4201  *  0b1001..ADC CMD9 selected.
4202  *  0b1010..ADC CMD10 selected.
4203  *  0b1011..ADC CMD11 selected.
4204  *  0b1100..ADC CMD12 selected.
4205  *  0b1101..ADC CMD13 selected.
4206  *  0b1110..ADC CMD14 selected.
4207  *  0b1111..ADC CMD15 selected.
4208  */
4209 #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
4210 
4211 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK       (0xFF00000U)
4212 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT      (20U)
4213 /*! HWTS7
4214  *  0b00000000..no trigger selected
4215  *  0b00000001..ADC TRIG0 selected
4216  *  0b00000010..ADC TRIG1 selected
4217  *  0b00000100..ADC TRIG2 selected
4218  *  0b00001000..ADC TRIG3 selected
4219  *  0b00010000..ADC TRIG4 selected
4220  *  0b00100000..ADC TRIG5 selected
4221  *  0b01000000..ADC TRIG6 selected
4222  *  0b10000000..ADC TRIG7 selected
4223  */
4224 #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x)         (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
4225 
4226 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK        (0x10000000U)
4227 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT       (28U)
4228 /*! B2B7
4229  *  0b0..Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached
4230  *  0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
4231  */
4232 #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x)          (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
4233 
4234 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK         (0x60000000U)
4235 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT        (29U)
4236 /*! IE7
4237  *  0b00..Generate interrupt on Done0 when segment 7 finish.
4238  *  0b01..Generate interrupt on Done1 when segment 7 finish.
4239  *  0b10..Generate interrupt on Done2 when segment 7 finish.
4240  *  0b11..Generate interrupt on Done3 when segment 7 finish.
4241  */
4242 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x)           (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
4243 
4244 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK      (0x80000000U)
4245 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT     (31U)
4246 /*! IE7_EN
4247  *  0b0..Interrupt DONE disabled.
4248  *  0b1..Interrupt DONE enabled. When segment 7 finish, an interrupt will be generated on the specific port configured by the IE7.
4249  */
4250 #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK)
4251 /*! @} */
4252 
4253 /* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
4254 #define ADC_ETC_TRIGn_CHAIN_7_6_COUNT            (8U)
4255 
4256 /*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */
4257 /*! @{ */
4258 
4259 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK      (0xFFFU)
4260 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT     (0U)
4261 #define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
4262 
4263 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK      (0xFFF0000U)
4264 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT     (16U)
4265 #define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
4266 /*! @} */
4267 
4268 /* The count of ADC_ETC_TRIGn_RESULT_1_0 */
4269 #define ADC_ETC_TRIGn_RESULT_1_0_COUNT           (8U)
4270 
4271 /*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */
4272 /*! @{ */
4273 
4274 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK      (0xFFFU)
4275 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT     (0U)
4276 #define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
4277 
4278 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK      (0xFFF0000U)
4279 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT     (16U)
4280 #define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
4281 /*! @} */
4282 
4283 /* The count of ADC_ETC_TRIGn_RESULT_3_2 */
4284 #define ADC_ETC_TRIGn_RESULT_3_2_COUNT           (8U)
4285 
4286 /*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */
4287 /*! @{ */
4288 
4289 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK      (0xFFFU)
4290 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT     (0U)
4291 #define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
4292 
4293 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK      (0xFFF0000U)
4294 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT     (16U)
4295 #define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
4296 /*! @} */
4297 
4298 /* The count of ADC_ETC_TRIGn_RESULT_5_4 */
4299 #define ADC_ETC_TRIGn_RESULT_5_4_COUNT           (8U)
4300 
4301 /*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */
4302 /*! @{ */
4303 
4304 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK      (0xFFFU)
4305 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT     (0U)
4306 #define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
4307 
4308 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK      (0xFFF0000U)
4309 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT     (16U)
4310 #define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x)        (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
4311 /*! @} */
4312 
4313 /* The count of ADC_ETC_TRIGn_RESULT_7_6 */
4314 #define ADC_ETC_TRIGn_RESULT_7_6_COUNT           (8U)
4315 
4316 
4317 /*!
4318  * @}
4319  */ /* end of group ADC_ETC_Register_Masks */
4320 
4321 
4322 /* ADC_ETC - Peripheral instance base addresses */
4323 /** Peripheral ADC_ETC base address */
4324 #define ADC_ETC_BASE                             (0x40048000u)
4325 /** Peripheral ADC_ETC base pointer */
4326 #define ADC_ETC                                  ((ADC_ETC_Type *)ADC_ETC_BASE)
4327 /** Array initializer of ADC_ETC peripheral base addresses */
4328 #define ADC_ETC_BASE_ADDRS                       { ADC_ETC_BASE }
4329 /** Array initializer of ADC_ETC peripheral base pointers */
4330 #define ADC_ETC_BASE_PTRS                        { ADC_ETC }
4331 /** Interrupt vectors for the ADC_ETC peripheral type */
4332 #define ADC_ETC_IRQS                             { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn, ADC_ETC_IRQ3_IRQn } }
4333 #define ADC_ETC_FAULT_IRQS                       { ADC_ETC_ERROR_IRQ_IRQn }
4334 
4335 /*!
4336  * @}
4337  */ /* end of group ADC_ETC_Peripheral_Access_Layer */
4338 
4339 
4340 /* ----------------------------------------------------------------------------
4341    -- ANADIG_LDO_SNVS Peripheral Access Layer
4342    ---------------------------------------------------------------------------- */
4343 
4344 /*!
4345  * @addtogroup ANADIG_LDO_SNVS_Peripheral_Access_Layer ANADIG_LDO_SNVS Peripheral Access Layer
4346  * @{
4347  */
4348 
4349 /** ANADIG_LDO_SNVS - Register Layout Typedef */
4350 typedef struct {
4351        uint8_t RESERVED_0[1296];
4352   __IO uint32_t PMU_LDO_LPSR_ANA;                  /**< PMU_LDO_LPSR_ANA_REGISTER, offset: 0x510 */
4353        uint8_t RESERVED_1[12];
4354   __IO uint32_t PMU_LDO_LPSR_DIG_2;                /**< PMU_LDO_LPSR_DIG_2_REGISTER, offset: 0x520 */
4355        uint8_t RESERVED_2[12];
4356   __IO uint32_t PMU_LDO_LPSR_DIG;                  /**< PMU_LDO_LPSR_DIG_REGISTER, offset: 0x530 */
4357 } ANADIG_LDO_SNVS_Type;
4358 
4359 /* ----------------------------------------------------------------------------
4360    -- ANADIG_LDO_SNVS Register Masks
4361    ---------------------------------------------------------------------------- */
4362 
4363 /*!
4364  * @addtogroup ANADIG_LDO_SNVS_Register_Masks ANADIG_LDO_SNVS Register Masks
4365  * @{
4366  */
4367 
4368 /*! @name PMU_LDO_LPSR_ANA - PMU_LDO_LPSR_ANA_REGISTER */
4369 /*! @{ */
4370 
4371 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK (0x1U)
4372 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_SHIFT (0U)
4373 /*! REG_LP_EN - reg_lp_en */
4374 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK)
4375 
4376 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK (0x4U)
4377 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_SHIFT (2U)
4378 /*! REG_DISABLE - reg_disable */
4379 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK)
4380 
4381 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK (0x8U)
4382 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_SHIFT (3U)
4383 /*! PULL_DOWN_2MA_EN - pull_down_2ma_en */
4384 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK)
4385 
4386 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK (0x10U)
4387 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_SHIFT (4U)
4388 /*! LPSR_ANA_CONTROL_MODE - LPSR_ANA_CONTROL_MODE
4389  *  0b0..SW Control
4390  *  0b1..HW Control
4391  */
4392 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK)
4393 
4394 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK (0x20U)
4395 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_SHIFT (5U)
4396 /*! BYPASS_MODE_EN - bypass_mode_en */
4397 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK)
4398 
4399 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK (0x40U)
4400 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_SHIFT (6U)
4401 /*! STANDBY_EN - standby_en */
4402 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK)
4403 
4404 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK (0x100U)
4405 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT (8U)
4406 /*! ALWAYS_4MA_PULLDOWN_EN - always_4ma_pulldown_en */
4407 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK)
4408 
4409 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK (0x80000U)
4410 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_SHIFT (19U)
4411 /*! TRACK_MODE_EN - Track Mode Enable
4412  *  0b0..Normal use
4413  *  0b1..Switch preparation
4414  */
4415 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK)
4416 
4417 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK (0x100000U)
4418 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_SHIFT (20U)
4419 /*! PULL_DOWN_20UA_EN - pull_down_20ua_en */
4420 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK)
4421 /*! @} */
4422 
4423 /*! @name PMU_LDO_LPSR_DIG_2 - PMU_LDO_LPSR_DIG_2_REGISTER */
4424 /*! @{ */
4425 
4426 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK (0x3U)
4427 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_SHIFT (0U)
4428 /*! VOLTAGE_STEP_INC - voltage_step_inc */
4429 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK)
4430 /*! @} */
4431 
4432 /*! @name PMU_LDO_LPSR_DIG - PMU_LDO_LPSR_DIG_REGISTER */
4433 /*! @{ */
4434 
4435 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK (0x4U)
4436 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_SHIFT (2U)
4437 /*! REG_EN - ENABLE_ILIMIT */
4438 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK)
4439 
4440 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK (0x20U)
4441 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_SHIFT (5U)
4442 /*! LPSR_DIG_CONTROL_MODE - LPSR_DIG_CONTROL_MODE
4443  *  0b0..SW Control
4444  *  0b1..HW Control
4445  */
4446 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK)
4447 
4448 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_MASK (0x40U)
4449 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_SHIFT (6U)
4450 /*! STANDBY_EN - standby_en */
4451 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_MASK)
4452 
4453 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK (0x20000U)
4454 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_SHIFT (17U)
4455 /*! TRACKING_MODE - tracking_mode */
4456 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK)
4457 
4458 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK (0x40000U)
4459 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_SHIFT (18U)
4460 /*! BYPASS_MODE - bypass_mode */
4461 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK)
4462 
4463 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK (0x1F00000U)
4464 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_SHIFT (20U)
4465 /*! VOLTAGE_SELECT - VOLTAGE_SELECT
4466  *  0b00000..Stable Voltage (range)
4467  *  0b00001..Stable Voltage (range)
4468  *  0b00010..Stable Voltage (range)
4469  *  0b00011..Stable Voltage (range)
4470  *  0b00100..Stable Voltage (range)
4471  *  0b00101..Stable Voltage (range)
4472  *  0b00110..Stable Voltage (range)
4473  *  0b00111..Stable Voltage (range)
4474  *  0b01000..Stable Voltage (range)
4475  *  0b01001..Stable Voltage (range)
4476  *  0b01010..Stable Voltage (range)
4477  *  0b01011..Stable Voltage (range)
4478  *  0b01100..Stable Voltage (range)
4479  *  0b01101..Stable Voltage (range)
4480  *  0b01110..Stable Voltage (range)
4481  *  0b01111..Stable Voltage (range)
4482  *  0b10000..Stable Voltage (range)
4483  *  0b10001..Stable Voltage (range)
4484  *  0b10010..Stable Voltage (range)
4485  *  0b10011..Stable Voltage (range)
4486  *  0b10100..Stable Voltage (range)
4487  *  0b10101..Stable Voltage (range)
4488  *  0b10110..Stable Voltage (range)
4489  *  0b10111..Stable Voltage (range)
4490  *  0b11000..Stable Voltage (range)
4491  *  0b11001..Stable Voltage (range)
4492  *  0b11010..Stable Voltage (range)
4493  *  0b11011..Stable Voltage (range)
4494  *  0b11100..Stable Voltage (range)
4495  *  0b11101..Stable Voltage (range)
4496  *  0b11110..Stable Voltage (range)
4497  *  0b11111..Stable Voltage (range)
4498  */
4499 #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK)
4500 /*! @} */
4501 
4502 
4503 /*!
4504  * @}
4505  */ /* end of group ANADIG_LDO_SNVS_Register_Masks */
4506 
4507 
4508 /* ANADIG_LDO_SNVS - Peripheral instance base addresses */
4509 /** Peripheral ANADIG_LDO_SNVS base address */
4510 #define ANADIG_LDO_SNVS_BASE                     (0x40C84000u)
4511 /** Peripheral ANADIG_LDO_SNVS base pointer */
4512 #define ANADIG_LDO_SNVS                          ((ANADIG_LDO_SNVS_Type *)ANADIG_LDO_SNVS_BASE)
4513 /** Array initializer of ANADIG_LDO_SNVS peripheral base addresses */
4514 #define ANADIG_LDO_SNVS_BASE_ADDRS               { ANADIG_LDO_SNVS_BASE }
4515 /** Array initializer of ANADIG_LDO_SNVS peripheral base pointers */
4516 #define ANADIG_LDO_SNVS_BASE_PTRS                { ANADIG_LDO_SNVS }
4517 
4518 /*!
4519  * @}
4520  */ /* end of group ANADIG_LDO_SNVS_Peripheral_Access_Layer */
4521 
4522 
4523 /* ----------------------------------------------------------------------------
4524    -- ANADIG_LDO_SNVS_DIG Peripheral Access Layer
4525    ---------------------------------------------------------------------------- */
4526 
4527 /*!
4528  * @addtogroup ANADIG_LDO_SNVS_DIG_Peripheral_Access_Layer ANADIG_LDO_SNVS_DIG Peripheral Access Layer
4529  * @{
4530  */
4531 
4532 /** ANADIG_LDO_SNVS_DIG - Register Layout Typedef */
4533 typedef struct {
4534        uint8_t RESERVED_0[1344];
4535   __IO uint32_t PMU_LDO_SNVS_DIG;                  /**< PMU_LDO_SNVS_DIG_REGISTER, offset: 0x540 */
4536 } ANADIG_LDO_SNVS_DIG_Type;
4537 
4538 /* ----------------------------------------------------------------------------
4539    -- ANADIG_LDO_SNVS_DIG Register Masks
4540    ---------------------------------------------------------------------------- */
4541 
4542 /*!
4543  * @addtogroup ANADIG_LDO_SNVS_DIG_Register_Masks ANADIG_LDO_SNVS_DIG Register Masks
4544  * @{
4545  */
4546 
4547 /*! @name PMU_LDO_SNVS_DIG - PMU_LDO_SNVS_DIG_REGISTER */
4548 /*! @{ */
4549 
4550 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK (0x1U)
4551 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_SHIFT (0U)
4552 /*! REG_LP_EN - REG_LP_EN */
4553 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK)
4554 
4555 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_MASK (0x2U)
4556 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_SHIFT (1U)
4557 /*! TEST_OVERRIDE - test_override */
4558 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_MASK)
4559 
4560 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK (0x4U)
4561 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_SHIFT (2U)
4562 /*! REG_EN - REG_EN */
4563 #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK)
4564 /*! @} */
4565 
4566 
4567 /*!
4568  * @}
4569  */ /* end of group ANADIG_LDO_SNVS_DIG_Register_Masks */
4570 
4571 
4572 /* ANADIG_LDO_SNVS_DIG - Peripheral instance base addresses */
4573 /** Peripheral ANADIG_LDO_SNVS_DIG base address */
4574 #define ANADIG_LDO_SNVS_DIG_BASE                 (0x40C84000u)
4575 /** Peripheral ANADIG_LDO_SNVS_DIG base pointer */
4576 #define ANADIG_LDO_SNVS_DIG                      ((ANADIG_LDO_SNVS_DIG_Type *)ANADIG_LDO_SNVS_DIG_BASE)
4577 /** Array initializer of ANADIG_LDO_SNVS_DIG peripheral base addresses */
4578 #define ANADIG_LDO_SNVS_DIG_BASE_ADDRS           { ANADIG_LDO_SNVS_DIG_BASE }
4579 /** Array initializer of ANADIG_LDO_SNVS_DIG peripheral base pointers */
4580 #define ANADIG_LDO_SNVS_DIG_BASE_PTRS            { ANADIG_LDO_SNVS_DIG }
4581 
4582 /*!
4583  * @}
4584  */ /* end of group ANADIG_LDO_SNVS_DIG_Peripheral_Access_Layer */
4585 
4586 
4587 /* ----------------------------------------------------------------------------
4588    -- ANADIG_MISC Peripheral Access Layer
4589    ---------------------------------------------------------------------------- */
4590 
4591 /*!
4592  * @addtogroup ANADIG_MISC_Peripheral_Access_Layer ANADIG_MISC Peripheral Access Layer
4593  * @{
4594  */
4595 
4596 /** ANADIG_MISC - Register Layout Typedef */
4597 typedef struct {
4598        uint8_t RESERVED_0[2048];
4599   __I  uint32_t MISC_DIFPROG;                      /**< Chip Silicon Version Register, offset: 0x800 */
4600        uint8_t RESERVED_1[28];
4601   __IO uint32_t VDDSOC_AI_CTRL;                    /**< VDDSOC_AI_CTRL_REGISTER, offset: 0x820 */
4602        uint8_t RESERVED_2[12];
4603   __IO uint32_t VDDSOC_AI_WDATA;                   /**< VDDSOC_AI_WDATA_REGISTER, offset: 0x830 */
4604        uint8_t RESERVED_3[12];
4605   __I  uint32_t VDDSOC_AI_RDATA;                   /**< VDDSOC_AI_RDATA_REGISTER, offset: 0x840 */
4606        uint8_t RESERVED_4[12];
4607   __IO uint32_t VDDSOC2PLL_AI_CTRL_1G;             /**< VDDSOC2PLL_AI_CTRL_1G_REGISTER, offset: 0x850 */
4608        uint8_t RESERVED_5[12];
4609   __IO uint32_t VDDSOC2PLL_AI_WDATA_1G;            /**< VDDSOC2PLL_AI_WDATA_1G_REGISTER, offset: 0x860 */
4610        uint8_t RESERVED_6[12];
4611   __I  uint32_t VDDSOC2PLL_AI_RDATA_1G;            /**< VDDSOC2PLL_AI_RDATA_1G_REGISTER, offset: 0x870 */
4612        uint8_t RESERVED_7[12];
4613   __IO uint32_t VDDSOC2PLL_AI_CTRL_AUDIO;          /**< VDDSOC_AI_CTRL_AUDIO_REGISTER, offset: 0x880 */
4614        uint8_t RESERVED_8[12];
4615   __IO uint32_t VDDSOC2PLL_AI_WDATA_AUDIO;         /**< VDDSOC_AI_WDATA_AUDIO_REGISTER, offset: 0x890 */
4616        uint8_t RESERVED_9[12];
4617   __I  uint32_t VDDSOC2PLL_AI_RDATA_AUDIO;         /**< VDDSOC2PLL_AI_RDATA_REGISTER, offset: 0x8A0 */
4618        uint8_t RESERVED_10[12];
4619   __IO uint32_t VDDSOC2PLL_AI_CTRL_VIDEO;          /**< VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER, offset: 0x8B0 */
4620        uint8_t RESERVED_11[12];
4621   __IO uint32_t VDDSOC2PLL_AI_WDATA_VIDEO;         /**< VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER, offset: 0x8C0 */
4622        uint8_t RESERVED_12[12];
4623   __I  uint32_t VDDSOC2PLL_AI_RDATA_VIDEO;         /**< VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER, offset: 0x8D0 */
4624        uint8_t RESERVED_13[12];
4625   __IO uint32_t VDDLPSR_AI_CTRL;                   /**< VDDSOC_AI_CTRL_REGISTER, offset: 0x8E0 */
4626        uint8_t RESERVED_14[12];
4627   __IO uint32_t VDDLPSR_AI_WDATA;                  /**< VDDLPSR_AI_WDATA_REGISTER, offset: 0x8F0 */
4628        uint8_t RESERVED_15[12];
4629   __I  uint32_t VDDLPSR_AI_RDATA_REFTOP;           /**< VDDLPSR_AI_RDATA_REFTOP_REGISTER, offset: 0x900 */
4630        uint8_t RESERVED_16[12];
4631   __I  uint32_t VDDLPSR_AI_RDATA_TMPSNS;           /**< VDDLPSR_AI_RDATA_TMPSNS_REGISTER, offset: 0x910 */
4632        uint8_t RESERVED_17[12];
4633   __IO uint32_t VDDLPSR_AI400M_CTRL;               /**< VDDLPSR_AI400M_CTRL_REGISTER, offset: 0x920 */
4634        uint8_t RESERVED_18[12];
4635   __IO uint32_t VDDLPSR_AI400M_WDATA;              /**< VDDLPSR_AI400M_WDATA_REGISTER, offset: 0x930 */
4636        uint8_t RESERVED_19[12];
4637   __I  uint32_t VDDLPSR_AI400M_RDATA;              /**< VDDLPSR_AI400M_RDATA_REGISTER, offset: 0x940 */
4638 } ANADIG_MISC_Type;
4639 
4640 /* ----------------------------------------------------------------------------
4641    -- ANADIG_MISC Register Masks
4642    ---------------------------------------------------------------------------- */
4643 
4644 /*!
4645  * @addtogroup ANADIG_MISC_Register_Masks ANADIG_MISC Register Masks
4646  * @{
4647  */
4648 
4649 /*! @name MISC_DIFPROG - Chip Silicon Version Register */
4650 /*! @{ */
4651 
4652 #define ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK     (0xFFFFFFFFU)
4653 #define ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT    (0U)
4654 /*! CHIPID - Chip ID */
4655 #define ANADIG_MISC_MISC_DIFPROG_CHIPID(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT)) & ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK)
4656 /*! @} */
4657 
4658 /*! @name VDDSOC_AI_CTRL - VDDSOC_AI_CTRL_REGISTER */
4659 /*! @{ */
4660 
4661 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK (0xFFU)
4662 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT (0U)
4663 /*! VDDSOC_AI_ADDR - VDDSOC_AI_ADDR */
4664 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK)
4665 
4666 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK (0x10000U)
4667 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT (16U)
4668 /*! VDDSOC_AIRWB - VDDSOC_AIRWB */
4669 #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK)
4670 /*! @} */
4671 
4672 /*! @name VDDSOC_AI_WDATA - VDDSOC_AI_WDATA_REGISTER */
4673 /*! @{ */
4674 
4675 #define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK (0xFFFFFFFFU)
4676 #define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT (0U)
4677 /*! VDDSOC_AI_WDATA - VDDSOC_AI_WDATA */
4678 #define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK)
4679 /*! @} */
4680 
4681 /*! @name VDDSOC_AI_RDATA - VDDSOC_AI_RDATA_REGISTER */
4682 /*! @{ */
4683 
4684 #define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK (0xFFFFFFFFU)
4685 #define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT (0U)
4686 /*! VDDSOC_AI_RDATA - VDDSOC_AI_RDATA */
4687 #define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK)
4688 /*! @} */
4689 
4690 /*! @name VDDSOC2PLL_AI_CTRL_1G - VDDSOC2PLL_AI_CTRL_1G_REGISTER */
4691 /*! @{ */
4692 
4693 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK (0xFFU)
4694 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT (0U)
4695 /*! VDDSOC2PLL_AIADDR_1G - VDDSOC2PLL_AIADDR_1G */
4696 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK)
4697 
4698 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK (0x100U)
4699 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT (8U)
4700 /*! VDDSOC2PLL_AITOGGLE_1G - VDDSOC2PLL_AITOGGLE_1G */
4701 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK)
4702 
4703 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK (0x200U)
4704 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT (9U)
4705 /*! VDDSOC2PLL_AITOGGLE_DONE_1G - VDDSOC2PLL_AITOGGLE_DONE_1G */
4706 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK)
4707 
4708 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK (0x10000U)
4709 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT (16U)
4710 /*! VDDSOC2PLL_AIRWB_1G - VDDSOC2PLL_AIRWB_1G */
4711 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK)
4712 /*! @} */
4713 
4714 /*! @name VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G_REGISTER */
4715 /*! @{ */
4716 
4717 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK (0xFFFFFFFFU)
4718 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT (0U)
4719 /*! VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G */
4720 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK)
4721 /*! @} */
4722 
4723 /*! @name VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G_REGISTER */
4724 /*! @{ */
4725 
4726 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK (0xFFFFFFFFU)
4727 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT (0U)
4728 /*! VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G */
4729 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK)
4730 /*! @} */
4731 
4732 /*! @name VDDSOC2PLL_AI_CTRL_AUDIO - VDDSOC_AI_CTRL_AUDIO_REGISTER */
4733 /*! @{ */
4734 
4735 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK (0xFFU)
4736 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT (0U)
4737 /*! VDDSOC2PLL_AI_ADDR_AUDIO - VDDSOC2PLL_AI_ADDR_AUDIO */
4738 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK)
4739 
4740 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK (0x100U)
4741 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT (8U)
4742 /*! VDDSOC2PLL_AITOGGLE_AUDIO - VDDSOC2PLL_AITOGGLE_AUDIO */
4743 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK)
4744 
4745 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK (0x200U)
4746 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT (9U)
4747 /*! VDDSOC2PLL_AITOGGLE_DONE_AUDIO - VDDSOC2PLL_AITOGGLE_DONE_AUDIO */
4748 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK)
4749 
4750 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK (0x10000U)
4751 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT (16U)
4752 /*! VDDSOC2PLL_AIRWB_AUDIO - VDDSOC_AIRWB */
4753 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK)
4754 /*! @} */
4755 
4756 /*! @name VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC_AI_WDATA_AUDIO_REGISTER */
4757 /*! @{ */
4758 
4759 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK (0xFFFFFFFFU)
4760 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT (0U)
4761 /*! VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC2PLL_AI_WDATA_AUDIO */
4762 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK)
4763 /*! @} */
4764 
4765 /*! @name VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_REGISTER */
4766 /*! @{ */
4767 
4768 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK (0xFFFFFFFFU)
4769 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT (0U)
4770 /*! VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_AUDIO */
4771 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK)
4772 /*! @} */
4773 
4774 /*! @name VDDSOC2PLL_AI_CTRL_VIDEO - VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER */
4775 /*! @{ */
4776 
4777 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK (0xFFU)
4778 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT (0U)
4779 /*! VDDSOC2PLL_AIADDR_VIDEO - VDDSOC2PLL_AIADDR_VIDEO */
4780 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK)
4781 
4782 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK (0x100U)
4783 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT (8U)
4784 /*! VDDSOC2PLL_AITOGGLE_VIDEO - VDDSOC2PLL_AITOGGLE_VIDEO */
4785 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK)
4786 
4787 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK (0x200U)
4788 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT (9U)
4789 /*! VDDSOC2PLL_AITOGGLE_DONE_VIDEO - VDDSOC2PLL_AITOGGLE_DONE_VIDEO */
4790 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK)
4791 
4792 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK (0x10000U)
4793 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT (16U)
4794 /*! VDDSOC2PLL_AIRWB_VIDEO - VDDSOC2PLL_AIRWB_VIDEO */
4795 #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK)
4796 /*! @} */
4797 
4798 /*! @name VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER */
4799 /*! @{ */
4800 
4801 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK (0xFFFFFFFFU)
4802 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT (0U)
4803 /*! VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO */
4804 #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK)
4805 /*! @} */
4806 
4807 /*! @name VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER */
4808 /*! @{ */
4809 
4810 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK (0xFFFFFFFFU)
4811 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT (0U)
4812 /*! VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO */
4813 #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK)
4814 /*! @} */
4815 
4816 /*! @name VDDLPSR_AI_CTRL - VDDSOC_AI_CTRL_REGISTER */
4817 /*! @{ */
4818 
4819 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK (0xFFU)
4820 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT (0U)
4821 /*! VDDLPSR_AI_ADDR - VDDLPSR_AI_ADDR */
4822 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK)
4823 
4824 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK (0x10000U)
4825 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT (16U)
4826 /*! VDDLPSR_AIRWB - VDDLPSR_AIRWB */
4827 #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK)
4828 /*! @} */
4829 
4830 /*! @name VDDLPSR_AI_WDATA - VDDLPSR_AI_WDATA_REGISTER */
4831 /*! @{ */
4832 
4833 #define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK (0xFFFFFFFFU)
4834 #define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT (0U)
4835 /*! VDDLPSR_AI_WDATA - VDD_LPSR_AI_WDATA */
4836 #define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK)
4837 /*! @} */
4838 
4839 /*! @name VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP_REGISTER */
4840 /*! @{ */
4841 
4842 #define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK (0xFFFFFFFFU)
4843 #define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT (0U)
4844 /*! VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP */
4845 #define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK)
4846 /*! @} */
4847 
4848 /*! @name VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS_REGISTER */
4849 /*! @{ */
4850 
4851 #define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK (0xFFFFFFFFU)
4852 #define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT (0U)
4853 /*! VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS */
4854 #define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK)
4855 /*! @} */
4856 
4857 /*! @name VDDLPSR_AI400M_CTRL - VDDLPSR_AI400M_CTRL_REGISTER */
4858 /*! @{ */
4859 
4860 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK (0xFFU)
4861 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT (0U)
4862 /*! VDDLPSR_AI400M_ADDR - VDDLPSR_AI400M_ADDR */
4863 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK)
4864 
4865 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK (0x100U)
4866 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT (8U)
4867 /*! VDDLPSR_AITOGGLE_400M - VDDLPSR_AITOGGLE_400M */
4868 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK)
4869 
4870 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK (0x200U)
4871 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT (9U)
4872 /*! VDDLPSR_AITOGGLE_DONE_400M - VDDLPSR_AITOGGLE_DONE_400M */
4873 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK)
4874 
4875 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK (0x10000U)
4876 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT (16U)
4877 /*! VDDLPSR_AI400M_RWB - VDDLPSR_AI400M_RWB */
4878 #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK)
4879 /*! @} */
4880 
4881 /*! @name VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA_REGISTER */
4882 /*! @{ */
4883 
4884 #define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK (0xFFFFFFFFU)
4885 #define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT (0U)
4886 /*! VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA */
4887 #define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK)
4888 /*! @} */
4889 
4890 /*! @name VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA_REGISTER */
4891 /*! @{ */
4892 
4893 #define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK (0xFFFFFFFFU)
4894 #define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT (0U)
4895 /*! VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA */
4896 #define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK)
4897 /*! @} */
4898 
4899 
4900 /*!
4901  * @}
4902  */ /* end of group ANADIG_MISC_Register_Masks */
4903 
4904 
4905 /* ANADIG_MISC - Peripheral instance base addresses */
4906 /** Peripheral ANADIG_MISC base address */
4907 #define ANADIG_MISC_BASE                         (0x40C84000u)
4908 /** Peripheral ANADIG_MISC base pointer */
4909 #define ANADIG_MISC                              ((ANADIG_MISC_Type *)ANADIG_MISC_BASE)
4910 /** Array initializer of ANADIG_MISC peripheral base addresses */
4911 #define ANADIG_MISC_BASE_ADDRS                   { ANADIG_MISC_BASE }
4912 /** Array initializer of ANADIG_MISC peripheral base pointers */
4913 #define ANADIG_MISC_BASE_PTRS                    { ANADIG_MISC }
4914 
4915 /*!
4916  * @}
4917  */ /* end of group ANADIG_MISC_Peripheral_Access_Layer */
4918 
4919 
4920 /* ----------------------------------------------------------------------------
4921    -- ANADIG_OSC Peripheral Access Layer
4922    ---------------------------------------------------------------------------- */
4923 
4924 /*!
4925  * @addtogroup ANADIG_OSC_Peripheral_Access_Layer ANADIG_OSC Peripheral Access Layer
4926  * @{
4927  */
4928 
4929 /** ANADIG_OSC - Register Layout Typedef */
4930 typedef struct {
4931        uint8_t RESERVED_0[16];
4932   __IO uint32_t OSC_48M_CTRL;                      /**< 48MHz RCOSC Control Register, offset: 0x10 */
4933        uint8_t RESERVED_1[12];
4934   __IO uint32_t OSC_24M_CTRL;                      /**< 24MHz OSC Control Register, offset: 0x20 */
4935        uint8_t RESERVED_2[28];
4936   __I  uint32_t OSC_400M_CTRL0;                    /**< 400MHz RCOSC Control0 Register, offset: 0x40 */
4937        uint8_t RESERVED_3[12];
4938   __IO uint32_t OSC_400M_CTRL1;                    /**< 400MHz RCOSC Control1 Register, offset: 0x50 */
4939        uint8_t RESERVED_4[12];
4940   __IO uint32_t OSC_400M_CTRL2;                    /**< 400MHz RCOSC Control2 Register, offset: 0x60 */
4941        uint8_t RESERVED_5[92];
4942   __IO uint32_t OSC_16M_CTRL;                      /**< 16MHz RCOSC Control Register, offset: 0xC0 */
4943 } ANADIG_OSC_Type;
4944 
4945 /* ----------------------------------------------------------------------------
4946    -- ANADIG_OSC Register Masks
4947    ---------------------------------------------------------------------------- */
4948 
4949 /*!
4950  * @addtogroup ANADIG_OSC_Register_Masks ANADIG_OSC Register Masks
4951  * @{
4952  */
4953 
4954 /*! @name OSC_48M_CTRL - 48MHz RCOSC Control Register */
4955 /*! @{ */
4956 
4957 #define ANADIG_OSC_OSC_48M_CTRL_TEN_MASK         (0x2U)
4958 #define ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT        (1U)
4959 /*! TEN - 48MHz RCOSC Enable
4960  *  0b0..Power down
4961  *  0b1..Power up
4962  */
4963 #define ANADIG_OSC_OSC_48M_CTRL_TEN(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TEN_MASK)
4964 
4965 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK (0x1000000U)
4966 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT (24U)
4967 /*! RC_48M_DIV2_EN - RCOSC_48M_DIV2 Enable
4968  *  0b0..Disable
4969  *  0b1..Enable
4970  */
4971 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK)
4972 
4973 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK (0x40000000U)
4974 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT (30U)
4975 /*! RC_48M_DIV2_CONTROL_MODE - RCOSC_48M_DIV2 Control Mode
4976  *  0b0..Software mode (default)
4977  *  0b1..GPC mode (Setpoint)
4978  */
4979 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK)
4980 
4981 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK (0x80000000U)
4982 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT (31U)
4983 /*! RC_48M_CONTROL_MODE - 48MHz RCOSC Control Mode
4984  *  0b0..Software mode (default)
4985  *  0b1..GPC mode (Setpoint)
4986  */
4987 #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK)
4988 /*! @} */
4989 
4990 /*! @name OSC_24M_CTRL - 24MHz OSC Control Register */
4991 /*! @{ */
4992 
4993 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK  (0x1U)
4994 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT (0U)
4995 /*! BYPASS_CLK - 24MHz OSC Bypass Clock */
4996 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK)
4997 
4998 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK   (0x2U)
4999 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT  (1U)
5000 /*! BYPASS_EN - 24MHz OSC Bypass Enable
5001  *  0b0..Disable
5002  *  0b1..Enable
5003  */
5004 #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK)
5005 
5006 #define ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK       (0x4U)
5007 #define ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT      (2U)
5008 /*! LP_EN - 24MHz OSC Low-Power Mode Enable
5009  *  0b0..High Gain mode (HP)
5010  *  0b1..Low-power mode (LP)
5011  */
5012 #define ANADIG_OSC_OSC_24M_CTRL_LP_EN(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK)
5013 
5014 #define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK (0x8U)
5015 #define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT (3U)
5016 /*! OSC_COMP_MODE - 24MHz OSC Comparator Mode
5017  *  0b0..Single-ended mode (default)
5018  *  0b1..Differential mode (test mode)
5019  */
5020 #define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK)
5021 
5022 #define ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK      (0x10U)
5023 #define ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT     (4U)
5024 /*! OSC_EN - 24MHz OSC Enable
5025  *  0b0..Disable
5026  *  0b1..Enable
5027  */
5028 #define ANADIG_OSC_OSC_24M_CTRL_OSC_EN(x)        (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK)
5029 
5030 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK (0x80U)
5031 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT (7U)
5032 /*! OSC_24M_GATE - 24MHz OSC Gate Control
5033  *  0b0..Not Gated
5034  *  0b1..Gated
5035  */
5036 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK)
5037 
5038 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK (0x40000000U)
5039 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT (30U)
5040 /*! OSC_24M_STABLE - 24MHz OSC Stable
5041  *  0b0..Not Stable
5042  *  0b1..Stable
5043  */
5044 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)
5045 
5046 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK (0x80000000U)
5047 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT (31U)
5048 /*! OSC_24M_CONTROL_MODE - 24MHz OSC Control Mode
5049  *  0b0..Software mode (default)
5050  *  0b1..GPC mode (Setpoint)
5051  */
5052 #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK)
5053 /*! @} */
5054 
5055 /*! @name OSC_400M_CTRL0 - 400MHz RCOSC Control0 Register */
5056 /*! @{ */
5057 
5058 #define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK (0x80000000U)
5059 #define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT (31U)
5060 /*! OSC400M_AI_BUSY - 400MHz OSC AI BUSY */
5061 #define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK)
5062 /*! @} */
5063 
5064 /*! @name OSC_400M_CTRL1 - 400MHz RCOSC Control1 Register */
5065 /*! @{ */
5066 
5067 #define ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK       (0x1U)
5068 #define ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT      (0U)
5069 /*! PWD - Power down control for 400MHz RCOSC
5070  *  0b0..No Power down
5071  *  0b1..Power down
5072  */
5073 #define ANADIG_OSC_OSC_400M_CTRL1_PWD(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK)
5074 
5075 #define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK (0x2U)
5076 #define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT (1U)
5077 /*! CLKGATE_400MEG - Clock gate control for 400MHz RCOSC
5078  *  0b0..Not Gated
5079  *  0b1..Gated
5080  */
5081 #define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK)
5082 
5083 #define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK (0x80000000U)
5084 #define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT (31U)
5085 /*! RC_400M_CONTROL_MODE - 400MHz RCOSC Control mode
5086  *  0b0..Software mode (default)
5087  *  0b1..GPC mode (Setpoint)
5088  */
5089 #define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK)
5090 /*! @} */
5091 
5092 /*! @name OSC_400M_CTRL2 - 400MHz RCOSC Control2 Register */
5093 /*! @{ */
5094 
5095 #define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK (0x1U)
5096 #define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT (0U)
5097 /*! ENABLE_CLK - Clock enable
5098  *  0b0..Clock is disabled before entering GPC mode
5099  *  0b1..Clock is enabled before entering GPC mode
5100  */
5101 #define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK)
5102 
5103 #define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK  (0x400U)
5104 #define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT (10U)
5105 /*! TUNE_BYP - Bypass tuning logic
5106  *  0b0..Use the output of tuning logic to run the oscillator
5107  *  0b1..Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator
5108  */
5109 #define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK)
5110 
5111 #define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U)
5112 #define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U)
5113 /*! OSC_TUNE_VAL - Oscillator Tune Value */
5114 #define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK)
5115 /*! @} */
5116 
5117 /*! @name OSC_16M_CTRL - 16MHz RCOSC Control Register */
5118 /*! @{ */
5119 
5120 #define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK (0x2U)
5121 #define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT (1U)
5122 /*! EN_IRC4M16M - Enable Clock Output
5123  *  0b0..Disable
5124  *  0b1..Enable
5125  */
5126 #define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK)
5127 
5128 #define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK (0x8U)
5129 #define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT (3U)
5130 /*! EN_POWER_SAVE - Power Save Enable
5131  *  0b0..Disable
5132  *  0b1..Enable
5133  */
5134 #define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK)
5135 
5136 #define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK (0x100U)
5137 #define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT (8U)
5138 /*! SOURCE_SEL_16M - Source select
5139  *  0b0..16MHz Oscillator
5140  *  0b1..24MHz Oscillator
5141  */
5142 #define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK)
5143 
5144 #define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK (0x80000000U)
5145 #define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT (31U)
5146 /*! RC_16M_CONTROL_MODE - Control Mode for 16MHz Oscillator
5147  *  0b0..Software mode (default)
5148  *  0b1..GPC mode (Setpoint)
5149  */
5150 #define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK)
5151 /*! @} */
5152 
5153 
5154 /*!
5155  * @}
5156  */ /* end of group ANADIG_OSC_Register_Masks */
5157 
5158 
5159 /* ANADIG_OSC - Peripheral instance base addresses */
5160 /** Peripheral ANADIG_OSC base address */
5161 #define ANADIG_OSC_BASE                          (0x40C84000u)
5162 /** Peripheral ANADIG_OSC base pointer */
5163 #define ANADIG_OSC                               ((ANADIG_OSC_Type *)ANADIG_OSC_BASE)
5164 /** Array initializer of ANADIG_OSC peripheral base addresses */
5165 #define ANADIG_OSC_BASE_ADDRS                    { ANADIG_OSC_BASE }
5166 /** Array initializer of ANADIG_OSC peripheral base pointers */
5167 #define ANADIG_OSC_BASE_PTRS                     { ANADIG_OSC }
5168 
5169 /*!
5170  * @}
5171  */ /* end of group ANADIG_OSC_Peripheral_Access_Layer */
5172 
5173 
5174 /* ----------------------------------------------------------------------------
5175    -- ANADIG_PLL Peripheral Access Layer
5176    ---------------------------------------------------------------------------- */
5177 
5178 /*!
5179  * @addtogroup ANADIG_PLL_Peripheral_Access_Layer ANADIG_PLL Peripheral Access Layer
5180  * @{
5181  */
5182 
5183 /** ANADIG_PLL - Register Layout Typedef */
5184 typedef struct {
5185        uint8_t RESERVED_0[512];
5186   __IO uint32_t ARM_PLL_CTRL;                      /**< ARM_PLL_CTRL_REGISTER, offset: 0x200 */
5187        uint8_t RESERVED_1[12];
5188   __IO uint32_t SYS_PLL3_CTRL;                     /**< SYS_PLL3_CTRL_REGISTER, offset: 0x210 */
5189        uint8_t RESERVED_2[12];
5190   __IO uint32_t SYS_PLL3_UPDATE;                   /**< SYS_PLL3_UPDATE_REGISTER, offset: 0x220 */
5191        uint8_t RESERVED_3[12];
5192   __IO uint32_t SYS_PLL3_PFD;                      /**< SYS_PLL3_PFD_REGISTER, offset: 0x230 */
5193        uint8_t RESERVED_4[12];
5194   __IO uint32_t SYS_PLL2_CTRL;                     /**< SYS_PLL2_CTRL_REGISTER, offset: 0x240 */
5195        uint8_t RESERVED_5[12];
5196   __IO uint32_t SYS_PLL2_UPDATE;                   /**< SYS_PLL2_UPDATE_REGISTER, offset: 0x250 */
5197        uint8_t RESERVED_6[12];
5198   __IO uint32_t SYS_PLL2_SS;                       /**< SYS_PLL2_SS_REGISTER, offset: 0x260 */
5199        uint8_t RESERVED_7[12];
5200   __IO uint32_t SYS_PLL2_PFD;                      /**< SYS_PLL2_PFD_REGISTER, offset: 0x270 */
5201        uint8_t RESERVED_8[44];
5202   __IO uint32_t SYS_PLL2_MFD;                      /**< SYS_PLL2_MFD_REGISTER, offset: 0x2A0 */
5203        uint8_t RESERVED_9[12];
5204   __IO uint32_t SYS_PLL1_SS;                       /**< SYS_PLL1_SS_REGISTER, offset: 0x2B0 */
5205        uint8_t RESERVED_10[12];
5206   __IO uint32_t SYS_PLL1_CTRL;                     /**< SYS_PLL1_CTRL_REGISTER, offset: 0x2C0 */
5207        uint8_t RESERVED_11[12];
5208   __IO uint32_t SYS_PLL1_DENOMINATOR;              /**< SYS_PLL1_DENOMINATOR_REGISTER, offset: 0x2D0 */
5209        uint8_t RESERVED_12[12];
5210   __IO uint32_t SYS_PLL1_NUMERATOR;                /**< SYS_PLL1_NUMERATOR_REGISTER, offset: 0x2E0 */
5211        uint8_t RESERVED_13[12];
5212   __IO uint32_t SYS_PLL1_DIV_SELECT;               /**< SYS_PLL1_DIV_SELECT_REGISTER, offset: 0x2F0 */
5213        uint8_t RESERVED_14[12];
5214   __IO uint32_t PLL_AUDIO_CTRL;                    /**< PLL_AUDIO_CTRL_REGISTER, offset: 0x300 */
5215        uint8_t RESERVED_15[12];
5216   __IO uint32_t PLL_AUDIO_SS;                      /**< PLL_AUDIO_SS_REGISTER, offset: 0x310 */
5217        uint8_t RESERVED_16[12];
5218   __IO uint32_t PLL_AUDIO_DENOMINATOR;             /**< PLL_AUDIO_DENOMINATOR_REGISTER, offset: 0x320 */
5219        uint8_t RESERVED_17[12];
5220   __IO uint32_t PLL_AUDIO_NUMERATOR;               /**< PLL_AUDIO_NUMERATOR_REGISTER, offset: 0x330 */
5221        uint8_t RESERVED_18[12];
5222   __IO uint32_t PLL_AUDIO_DIV_SELECT;              /**< PLL_AUDIO_DIV_SELECT_REGISTER, offset: 0x340 */
5223        uint8_t RESERVED_19[12];
5224   __IO uint32_t PLL_VIDEO_CTRL;                    /**< PLL_VIDEO_CTRL_REGISTER, offset: 0x350 */
5225        uint8_t RESERVED_20[12];
5226   __IO uint32_t PLL_VIDEO_SS;                      /**< PLL_VIDEO_SS_REGISTER, offset: 0x360 */
5227        uint8_t RESERVED_21[12];
5228   __IO uint32_t PLL_VIDEO_DENOMINATOR;             /**< PLL_VIDEO_DENOMINATOR_REGISTER, offset: 0x370 */
5229        uint8_t RESERVED_22[12];
5230   __IO uint32_t PLL_VIDEO_NUMERATOR;               /**< PLL_VIDEO_NUMERATOR_REGISTER, offset: 0x380 */
5231        uint8_t RESERVED_23[12];
5232   __IO uint32_t PLL_VIDEO_DIV_SELECT;              /**< PLL_VIDEO_DIV_SELECT_REGISTER, offset: 0x390 */
5233 } ANADIG_PLL_Type;
5234 
5235 /* ----------------------------------------------------------------------------
5236    -- ANADIG_PLL Register Masks
5237    ---------------------------------------------------------------------------- */
5238 
5239 /*!
5240  * @addtogroup ANADIG_PLL_Register_Masks ANADIG_PLL Register Masks
5241  * @{
5242  */
5243 
5244 /*! @name ARM_PLL_CTRL - ARM_PLL_CTRL_REGISTER */
5245 /*! @{ */
5246 
5247 #define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK  (0xFFU)
5248 #define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT (0U)
5249 /*! DIV_SELECT - DIV_SELECT */
5250 #define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK)
5251 
5252 #define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK (0x1000U)
5253 #define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT (12U)
5254 /*! HOLD_RING_OFF - PLL Start up initialization
5255  *  0b0..Normal operation
5256  *  0b1..Initialize PLL start up
5257  */
5258 #define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK)
5259 
5260 #define ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK     (0x2000U)
5261 #define ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT    (13U)
5262 /*! POWERUP - Powers up the PLL.
5263  *  0b1..Power Up the PLL
5264  *  0b0..Power down the PLL
5265  */
5266 #define ANADIG_PLL_ARM_PLL_CTRL_POWERUP(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK)
5267 
5268 #define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK  (0x4000U)
5269 #define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT (14U)
5270 /*! ENABLE_CLK - Enable the clock output.
5271  *  0b0..Disable the clock
5272  *  0b1..Enable the clock
5273  */
5274 #define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK)
5275 
5276 #define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK (0x18000U)
5277 #define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT (15U)
5278 /*! POST_DIV_SEL - POST_DIV_SEL
5279  *  0b00..Divide by 2
5280  *  0b01..Divide by 4
5281  *  0b10..Divide by 8
5282  *  0b11..Divide by 1
5283  */
5284 #define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK)
5285 
5286 #define ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK      (0x20000U)
5287 #define ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT     (17U)
5288 /*! BYPASS - Bypass the pll.
5289  *  0b1..Bypass Mode
5290  *  0b0..Function mode
5291  */
5292 #define ANADIG_PLL_ARM_PLL_CTRL_BYPASS(x)        (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK)
5293 
5294 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK (0x20000000U)
5295 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT (29U)
5296 /*! ARM_PLL_STABLE - ARM_PLL_STABLE
5297  *  0b1..ARM PLL is stable
5298  *  0b0..ARM PLL is not stable
5299  */
5300 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK)
5301 
5302 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK (0x40000000U)
5303 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT (30U)
5304 /*! ARM_PLL_GATE - ARM_PLL_GATE
5305  *  0b1..Clock is gated
5306  *  0b0..Clock is not gated
5307  */
5308 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK)
5309 
5310 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK (0x80000000U)
5311 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT (31U)
5312 /*! ARM_PLL_CONTROL_MODE - pll_arm_control_mode
5313  *  0b0..Software Mode (Default)
5314  *  0b1..GPC Mode
5315  */
5316 #define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK)
5317 /*! @} */
5318 
5319 /*! @name SYS_PLL3_CTRL - SYS_PLL3_CTRL_REGISTER */
5320 /*! @{ */
5321 
5322 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK (0x8U)
5323 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT (3U)
5324 /*! SYS_PLL3_DIV2 - SYS PLL3 DIV2 gate */
5325 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK)
5326 
5327 #define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK (0x10U)
5328 #define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT (4U)
5329 /*! PLL_REG_EN - Enable Internal PLL Regulator */
5330 #define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK)
5331 
5332 #define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK (0x800U)
5333 #define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT (11U)
5334 /*! HOLD_RING_OFF - PLL Start up initialization
5335  *  0b0..Normal operation
5336  *  0b1..Initialize PLL start up
5337  */
5338 #define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK)
5339 
5340 #define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK (0x2000U)
5341 #define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT (13U)
5342 /*! ENABLE_CLK - Enable the clock output.
5343  *  0b0..Disable the clock
5344  *  0b1..Enable the clock
5345  */
5346 #define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK)
5347 
5348 #define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK     (0x10000U)
5349 #define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT    (16U)
5350 /*! BYPASS - BYPASS
5351  *  0b1..Bypass Mode
5352  *  0b0..Function mode
5353  */
5354 #define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK)
5355 
5356 #define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK    (0x200000U)
5357 #define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT   (21U)
5358 /*! POWERUP - Powers up the PLL.
5359  *  0b1..Power Up the PLL
5360  *  0b0..Power down the PLL
5361  */
5362 #define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP(x)      (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK)
5363 
5364 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK (0x10000000U)
5365 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT (28U)
5366 /*! SYS_PLL3_DIV2_CONTROL_MODE - SYS_PLL3_DIV2_CONTROL_MODE
5367  *  0b0..Software Mode (Default)
5368  *  0b1..GPC Mode
5369  */
5370 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK)
5371 
5372 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK (0x20000000U)
5373 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT (29U)
5374 /*! SYS_PLL3_STABLE - SYS_PLL3_STABLE */
5375 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK)
5376 
5377 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK (0x40000000U)
5378 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT (30U)
5379 /*! SYS_PLL3_GATE - SYS_PLL3_GATE
5380  *  0b1..Clock is gated
5381  *  0b0..Clock is not gated
5382  */
5383 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK)
5384 
5385 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK (0x80000000U)
5386 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT (31U)
5387 /*! SYS_PLL3_CONTROL_MODE - SYS_PLL3_control_mode
5388  *  0b0..Software Mode (Default)
5389  *  0b1..GPC Mode
5390  */
5391 #define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK)
5392 /*! @} */
5393 
5394 /*! @name SYS_PLL3_UPDATE - SYS_PLL3_UPDATE_REGISTER */
5395 /*! @{ */
5396 
5397 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK (0x2U)
5398 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT (1U)
5399 /*! PFD0_UPDATE - PFD0_OVERRIDE */
5400 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK)
5401 
5402 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK (0x4U)
5403 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT (2U)
5404 /*! PFD1_UPDATE - PFD1_OVERRIDE */
5405 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK)
5406 
5407 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK (0x8U)
5408 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT (3U)
5409 /*! PFD2_UPDATE - PFD2_OVERRIDE */
5410 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK)
5411 
5412 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK (0x10U)
5413 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT (4U)
5414 /*! PFD3_UPDATE - PFD3_UPDATE */
5415 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK)
5416 
5417 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
5418 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
5419 /*! PFD0_CONTROL_MODE - pfd0_control_mode
5420  *  0b0..Software Mode (Default)
5421  *  0b1..GPC Mode
5422  */
5423 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK)
5424 
5425 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
5426 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
5427 /*! PFD1_CONTROL_MODE - pfd1_control_mode
5428  *  0b0..Software Mode (Default)
5429  *  0b1..GPC Mode
5430  */
5431 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK)
5432 
5433 #define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK (0x80U)
5434 #define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT (7U)
5435 /*! PDF2_CONTROL_MODE - pdf2_control_mode
5436  *  0b0..Software Mode (Default)
5437  *  0b1..GPC Mode
5438  */
5439 #define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK)
5440 
5441 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
5442 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
5443 /*! PFD3_CONTROL_MODE - pfd3_control_mode
5444  *  0b0..Software Mode (Default)
5445  *  0b1..GPC Mode
5446  */
5447 #define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK)
5448 /*! @} */
5449 
5450 /*! @name SYS_PLL3_PFD - SYS_PLL3_PFD_REGISTER */
5451 /*! @{ */
5452 
5453 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK   (0x3FU)
5454 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT  (0U)
5455 /*! PFD0_FRAC - PFD0_FRAC */
5456 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK)
5457 
5458 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK (0x40U)
5459 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT (6U)
5460 /*! PFD0_STABLE - PFD0_STABLE */
5461 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK)
5462 
5463 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
5464 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
5465 /*! PFD0_DIV1_CLKGATE - PFD0_DIV1_CLKGATE
5466  *  0b1..Fractional divider clock (reference ref_pfd0) is off (power savings
5467  *  0b0..ref_pfd0 fractional divider clock is enabled
5468  */
5469 #define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK)
5470 
5471 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK   (0x3F00U)
5472 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT  (8U)
5473 /*! PFD1_FRAC - PFD1_FRAC */
5474 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK)
5475 
5476 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK (0x4000U)
5477 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT (14U)
5478 /*! PFD1_STABLE - PFD1_STABLE */
5479 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK)
5480 
5481 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
5482 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
5483 /*! PFD1_DIV1_CLKGATE - PFD1_DIV1_CLKGATE
5484  *  0b1..Fractional divider clock (reference ref_pfd1) is off (power savings)
5485  *  0b0..ref_pfd1 fractional divider clock is enabled
5486  */
5487 #define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK)
5488 
5489 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK   (0x3F0000U)
5490 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT  (16U)
5491 /*! PFD2_FRAC - PFD2_FRAC */
5492 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK)
5493 
5494 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK (0x400000U)
5495 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT (22U)
5496 /*! PFD2_STABLE - PFD2_STABLE */
5497 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK)
5498 
5499 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
5500 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
5501 /*! PFD2_DIV1_CLKGATE - PFD2_DIV1_CLKGATE
5502  *  0b1..Fractional divider clock (reference ref_pfd2) is off (power savings)
5503  *  0b0..ref_pfd2 fractional divider clock is enabled
5504  */
5505 #define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK)
5506 
5507 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK   (0x3F000000U)
5508 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT  (24U)
5509 /*! PFD3_FRAC - PFD3_FRAC */
5510 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK)
5511 
5512 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK (0x40000000U)
5513 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT (30U)
5514 /*! PFD3_STABLE - PFD3_STABLE */
5515 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK)
5516 
5517 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
5518 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
5519 /*! PFD3_DIV1_CLKGATE - PFD3_DIV1_CLKGATE
5520  *  0b1..Fractional divider clock (reference ref_pfd3) is off (power savings)
5521  *  0b0..ref_pfd3 fractional divider clock is enabled
5522  */
5523 #define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK)
5524 /*! @} */
5525 
5526 /*! @name SYS_PLL2_CTRL - SYS_PLL2_CTRL_REGISTER */
5527 /*! @{ */
5528 
5529 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK (0x8U)
5530 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT (3U)
5531 /*! PLL_REG_EN - Enable Internal PLL Regulator */
5532 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK)
5533 
5534 #define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK (0x800U)
5535 #define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT (11U)
5536 /*! HOLD_RING_OFF - PLL Start up initialization
5537  *  0b0..Normal operation
5538  *  0b1..Initialize PLL start up
5539  */
5540 #define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK)
5541 
5542 #define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK (0x2000U)
5543 #define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT (13U)
5544 /*! ENABLE_CLK - Enable the clock output.
5545  *  0b0..Disable the clock
5546  *  0b1..Enable the clock
5547  */
5548 #define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)
5549 
5550 #define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK     (0x10000U)
5551 #define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT    (16U)
5552 /*! BYPASS - Bypass the pll.
5553  *  0b1..Bypass Mode
5554  *  0b0..Function mode
5555  */
5556 #define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK)
5557 
5558 #define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK (0x20000U)
5559 #define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT (17U)
5560 /*! DITHER_ENABLE - DITHER_ENABLE
5561  *  0b0..Disable Dither
5562  *  0b1..Enable Dither
5563  */
5564 #define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK)
5565 
5566 #define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK (0x40000U)
5567 #define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT (18U)
5568 /*! PFD_OFFSET_EN - PFD_OFFSET_EN */
5569 #define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK)
5570 
5571 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK (0x80000U)
5572 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT (19U)
5573 /*! PLL_DDR_OVERRIDE - PLL_DDR_OVERRIDE */
5574 #define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK)
5575 
5576 #define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK    (0x800000U)
5577 #define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT   (23U)
5578 /*! POWERUP - Powers up the PLL.
5579  *  0b1..Power Up the PLL
5580  *  0b0..Power down the PLL
5581  */
5582 #define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP(x)      (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK)
5583 
5584 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK (0x20000000U)
5585 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT (29U)
5586 /*! SYS_PLL2_STABLE - SYS_PLL2_STABLE */
5587 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK)
5588 
5589 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK (0x40000000U)
5590 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT (30U)
5591 /*! SYS_PLL2_GATE - SYS_PLL2_GATE
5592  *  0b1..Clock is gated
5593  *  0b0..Clock is not gated
5594  */
5595 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK)
5596 
5597 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK (0x80000000U)
5598 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT (31U)
5599 /*! SYS_PLL2_CONTROL_MODE - SYS_PLL2_control_mode
5600  *  0b0..Software Mode (Default)
5601  *  0b1..GPC Mode
5602  */
5603 #define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK)
5604 /*! @} */
5605 
5606 /*! @name SYS_PLL2_UPDATE - SYS_PLL2_UPDATE_REGISTER */
5607 /*! @{ */
5608 
5609 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK (0x2U)
5610 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT (1U)
5611 /*! PFD0_UPDATE - PFD0_UPDATE */
5612 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK)
5613 
5614 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK (0x4U)
5615 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT (2U)
5616 /*! PFD1_UPDATE - PFD1_UPDATE */
5617 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK)
5618 
5619 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK (0x8U)
5620 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT (3U)
5621 /*! PFD2_UPDATE - PFD2_UPDATE */
5622 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK)
5623 
5624 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK (0x10U)
5625 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT (4U)
5626 /*! PFD3_UPDATE - PFD3_UPDATE */
5627 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK)
5628 
5629 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
5630 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
5631 /*! PFD0_CONTROL_MODE - pfd0_control_mode
5632  *  0b0..Software Mode (Default)
5633  *  0b1..GPC Mode
5634  */
5635 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK)
5636 
5637 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
5638 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
5639 /*! PFD1_CONTROL_MODE - pfd1_control_mode
5640  *  0b0..Software Mode (Default)
5641  *  0b1..GPC Mode
5642  */
5643 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK)
5644 
5645 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK (0x80U)
5646 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT (7U)
5647 /*! PFD2_CONTROL_MODE - pfd2_control_mode
5648  *  0b0..Software Mode (Default)
5649  *  0b1..GPC Mode
5650  */
5651 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK)
5652 
5653 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
5654 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
5655 /*! PFD3_CONTROL_MODE - pfd3_control_mode
5656  *  0b0..Software Mode (Default)
5657  *  0b1..GPC Mode
5658  */
5659 #define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK)
5660 /*! @} */
5661 
5662 /*! @name SYS_PLL2_SS - SYS_PLL2_SS_REGISTER */
5663 /*! @{ */
5664 
5665 #define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK         (0x7FFFU)
5666 #define ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT        (0U)
5667 /*! STEP - STEP */
5668 #define ANADIG_PLL_SYS_PLL2_SS_STEP(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
5669 
5670 #define ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK       (0x8000U)
5671 #define ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT      (15U)
5672 /*! ENABLE - ENABLE
5673  *  0b1..Enable Spread Spectrum
5674  *  0b0..Disable Spread Spectrum
5675  */
5676 #define ANADIG_PLL_SYS_PLL2_SS_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK)
5677 
5678 #define ANADIG_PLL_SYS_PLL2_SS_STOP_MASK         (0xFFFF0000U)
5679 #define ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT        (16U)
5680 /*! STOP - STOP */
5681 #define ANADIG_PLL_SYS_PLL2_SS_STOP(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STOP_MASK)
5682 /*! @} */
5683 
5684 /*! @name SYS_PLL2_PFD - SYS_PLL2_PFD_REGISTER */
5685 /*! @{ */
5686 
5687 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK   (0x3FU)
5688 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT  (0U)
5689 /*! PFD0_FRAC - PFD0_FRAC */
5690 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK)
5691 
5692 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK (0x40U)
5693 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT (6U)
5694 /*! PFD0_STABLE - PFD0_STABLE */
5695 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK)
5696 
5697 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
5698 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
5699 /*! PFD0_DIV1_CLKGATE - PFD0_DIV1_CLKGATE */
5700 #define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK)
5701 
5702 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK   (0x3F00U)
5703 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT  (8U)
5704 /*! PFD1_FRAC - PFD1_FRAC */
5705 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK)
5706 
5707 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK (0x4000U)
5708 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT (14U)
5709 /*! PFD1_STABLE - PFD1_STABLE */
5710 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK)
5711 
5712 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
5713 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
5714 /*! PFD1_DIV1_CLKGATE - PFD1_DIV1_CLKGATE */
5715 #define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK)
5716 
5717 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK   (0x3F0000U)
5718 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT  (16U)
5719 /*! PFD2_FRAC - PFD2_FRAC */
5720 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK)
5721 
5722 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK (0x400000U)
5723 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT (22U)
5724 /*! PFD2_STABLE - PFD2_STABLE */
5725 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK)
5726 
5727 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
5728 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
5729 /*! PFD2_DIV1_CLKGATE - PFD2_DIV1_CLKGATE */
5730 #define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK)
5731 
5732 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK   (0x3F000000U)
5733 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT  (24U)
5734 /*! PFD3_FRAC - PFD3_FRAC */
5735 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK)
5736 
5737 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK (0x40000000U)
5738 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT (30U)
5739 /*! PFD3_STABLE - PFD3_STABLE */
5740 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK)
5741 
5742 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
5743 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
5744 /*! PFD3_DIV1_CLKGATE - PFD3_DIV1_CLKGATE */
5745 #define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK)
5746 /*! @} */
5747 
5748 /*! @name SYS_PLL2_MFD - SYS_PLL2_MFD_REGISTER */
5749 /*! @{ */
5750 
5751 #define ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK         (0x3FFFFFFFU)
5752 #define ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT        (0U)
5753 /*! MFD - Denominator */
5754 #define ANADIG_PLL_SYS_PLL2_MFD_MFD(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT)) & ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK)
5755 /*! @} */
5756 
5757 /*! @name SYS_PLL1_SS - SYS_PLL1_SS_REGISTER */
5758 /*! @{ */
5759 
5760 #define ANADIG_PLL_SYS_PLL1_SS_STEP_MASK         (0x7FFFU)
5761 #define ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT        (0U)
5762 /*! STEP - STEP */
5763 #define ANADIG_PLL_SYS_PLL1_SS_STEP(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STEP_MASK)
5764 
5765 #define ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK       (0x8000U)
5766 #define ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT      (15U)
5767 /*! ENABLE - ENABLE
5768  *  0b1..Enable Spread Spectrum
5769  *  0b0..Disable Spread Spectrum
5770  */
5771 #define ANADIG_PLL_SYS_PLL1_SS_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK)
5772 
5773 #define ANADIG_PLL_SYS_PLL1_SS_STOP_MASK         (0xFFFF0000U)
5774 #define ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT        (16U)
5775 /*! STOP - STOP */
5776 #define ANADIG_PLL_SYS_PLL1_SS_STOP(x)           (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STOP_MASK)
5777 /*! @} */
5778 
5779 /*! @name SYS_PLL1_CTRL - SYS_PLL1_CTRL_REGISTER */
5780 /*! @{ */
5781 
5782 #define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK (0x2000U)
5783 #define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT (13U)
5784 /*! ENABLE_CLK - ENABLE_CLK */
5785 #define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK)
5786 
5787 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK (0x4000U)
5788 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT (14U)
5789 /*! SYS_PLL1_GATE - SYS_PLL1_GATE
5790  *  0b1..Gate the output
5791  *  0b0..No gate
5792  */
5793 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK)
5794 
5795 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK (0x2000000U)
5796 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT (25U)
5797 /*! SYS_PLL1_DIV2 - SYS_PLL1_DIV2 */
5798 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK)
5799 
5800 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK (0x4000000U)
5801 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT (26U)
5802 /*! SYS_PLL1_DIV5 - SYS_PLL1_DIV5 */
5803 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK)
5804 
5805 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK (0x8000000U)
5806 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT (27U)
5807 /*! SYS_PLL1_DIV5_CONTROL_MODE - SYS_PLL1_DIV5_CONTROL_MODE
5808  *  0b0..Software Mode (Default)
5809  *  0b1..GPC Mode
5810  */
5811 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK)
5812 
5813 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK (0x10000000U)
5814 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT (28U)
5815 /*! SYS_PLL1_DIV2_CONTROL_MODE - SYS_PLL1_DIV2_CONTROL_MODE
5816  *  0b0..Software Mode (Default)
5817  *  0b1..GPC Mode
5818  */
5819 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK)
5820 
5821 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK (0x20000000U)
5822 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT (29U)
5823 /*! SYS_PLL1_STABLE - SYS_PLL1_STABLE */
5824 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK)
5825 
5826 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK (0x40000000U)
5827 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT (30U)
5828 /*! SYS_PLL1_AI_BUSY - SYS_PLL1_AI_BUSY */
5829 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK)
5830 
5831 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK (0x80000000U)
5832 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT (31U)
5833 /*! SYS_PLL1_CONTROL_MODE - SYS_PLL1_CONTROL_MODE
5834  *  0b0..Software Mode (Default)
5835  *  0b1..GPC Mode
5836  */
5837 #define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK)
5838 /*! @} */
5839 
5840 /*! @name SYS_PLL1_DENOMINATOR - SYS_PLL1_DENOMINATOR_REGISTER */
5841 /*! @{ */
5842 
5843 #define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
5844 #define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT (0U)
5845 /*! DENOM - DENOM */
5846 #define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK)
5847 /*! @} */
5848 
5849 /*! @name SYS_PLL1_NUMERATOR - SYS_PLL1_NUMERATOR_REGISTER */
5850 /*! @{ */
5851 
5852 #define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK   (0x3FFFFFFFU)
5853 #define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT  (0U)
5854 /*! NUM - NUM */
5855 #define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM(x)     (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK)
5856 /*! @} */
5857 
5858 /*! @name SYS_PLL1_DIV_SELECT - SYS_PLL1_DIV_SELECT_REGISTER */
5859 /*! @{ */
5860 
5861 #define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK (0x7FU)
5862 #define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT (0U)
5863 /*! DIV_SELECT - DIV_SELECT */
5864 #define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK)
5865 /*! @} */
5866 
5867 /*! @name PLL_AUDIO_CTRL - PLL_AUDIO_CTRL_REGISTER */
5868 /*! @{ */
5869 
5870 #define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK (0x2000U)
5871 #define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT (13U)
5872 /*! ENABLE_CLK - ENABLE_CLK */
5873 #define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK)
5874 
5875 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK (0x4000U)
5876 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT (14U)
5877 /*! PLL_AUDIO_GATE - PLL_AUDIO_GATE
5878  *  0b1..Gate the output
5879  *  0b0..No gate
5880  */
5881 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK)
5882 
5883 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK (0x20000000U)
5884 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT (29U)
5885 /*! PLL_AUDIO_STABLE - PLL_AUDIO_STABLE */
5886 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK)
5887 
5888 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK (0x40000000U)
5889 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT (30U)
5890 /*! PLL_AUDIO_AI_BUSY - pll_audio_ai_busy */
5891 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK)
5892 
5893 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK (0x80000000U)
5894 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT (31U)
5895 /*! PLL_AUDIO_CONTROL_MODE - pll_audio_control_mode
5896  *  0b0..Software Mode (Default)
5897  *  0b1..GPC Mode
5898  */
5899 #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK)
5900 /*! @} */
5901 
5902 /*! @name PLL_AUDIO_SS - PLL_AUDIO_SS_REGISTER */
5903 /*! @{ */
5904 
5905 #define ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK        (0x7FFFU)
5906 #define ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT       (0U)
5907 /*! STEP - STEP */
5908 #define ANADIG_PLL_PLL_AUDIO_SS_STEP(x)          (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK)
5909 
5910 #define ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK      (0x8000U)
5911 #define ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT     (15U)
5912 /*! ENABLE - ENABLE
5913  *  0b1..Enable Spread Spectrum
5914  *  0b0..Disable Spread Spectrum
5915  */
5916 #define ANADIG_PLL_PLL_AUDIO_SS_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK)
5917 
5918 #define ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK        (0xFFFF0000U)
5919 #define ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT       (16U)
5920 /*! STOP - STOP */
5921 #define ANADIG_PLL_PLL_AUDIO_SS_STOP(x)          (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK)
5922 /*! @} */
5923 
5924 /*! @name PLL_AUDIO_DENOMINATOR - PLL_AUDIO_DENOMINATOR_REGISTER */
5925 /*! @{ */
5926 
5927 #define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
5928 #define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT (0U)
5929 /*! DENOM - DENOM */
5930 #define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK)
5931 /*! @} */
5932 
5933 /*! @name PLL_AUDIO_NUMERATOR - PLL_AUDIO_NUMERATOR_REGISTER */
5934 /*! @{ */
5935 
5936 #define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK  (0x3FFFFFFFU)
5937 #define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT (0U)
5938 /*! NUM - NUM */
5939 #define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK)
5940 /*! @} */
5941 
5942 /*! @name PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT_REGISTER */
5943 /*! @{ */
5944 
5945 #define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
5946 #define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
5947 /*! PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT */
5948 #define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK)
5949 /*! @} */
5950 
5951 /*! @name PLL_VIDEO_CTRL - PLL_VIDEO_CTRL_REGISTER */
5952 /*! @{ */
5953 
5954 #define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK (0x2000U)
5955 #define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT (13U)
5956 /*! ENABLE_CLK - ENABLE_CLK */
5957 #define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK)
5958 
5959 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK (0x4000U)
5960 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT (14U)
5961 /*! PLL_VIDEO_GATE - PLL_VIDEO_GATE
5962  *  0b1..Gate the output
5963  *  0b0..No gate
5964  */
5965 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK)
5966 
5967 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK (0x1000000U)
5968 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT (24U)
5969 /*! PLL_VIDEO_COUNTER_CLR - pll_video_counter_clr */
5970 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK)
5971 
5972 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK (0x20000000U)
5973 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT (29U)
5974 /*! PLL_VIDEO_STABLE - PLL_VIDEO_STABLE */
5975 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK)
5976 
5977 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK (0x40000000U)
5978 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT (30U)
5979 /*! PLL_VIDEO_AI_BUSY - pll_video_ai_busy */
5980 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK)
5981 
5982 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK (0x80000000U)
5983 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT (31U)
5984 /*! PLL_VIDEO_CONTROL_MODE - pll_video_control_mode
5985  *  0b0..Software Mode (Default)
5986  *  0b1..GPC Mode
5987  */
5988 #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK)
5989 /*! @} */
5990 
5991 /*! @name PLL_VIDEO_SS - PLL_VIDEO_SS_REGISTER */
5992 /*! @{ */
5993 
5994 #define ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK        (0x7FFFU)
5995 #define ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT       (0U)
5996 /*! STEP - STEP */
5997 #define ANADIG_PLL_PLL_VIDEO_SS_STEP(x)          (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK)
5998 
5999 #define ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK      (0x8000U)
6000 #define ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT     (15U)
6001 /*! ENABLE - ENABLE
6002  *  0b1..Enable Spread Spectrum
6003  *  0b0..Disable Spread Spectrum
6004  */
6005 #define ANADIG_PLL_PLL_VIDEO_SS_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK)
6006 
6007 #define ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK        (0xFFFF0000U)
6008 #define ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT       (16U)
6009 /*! STOP - STOP */
6010 #define ANADIG_PLL_PLL_VIDEO_SS_STOP(x)          (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK)
6011 /*! @} */
6012 
6013 /*! @name PLL_VIDEO_DENOMINATOR - PLL_VIDEO_DENOMINATOR_REGISTER */
6014 /*! @{ */
6015 
6016 #define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
6017 #define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT (0U)
6018 /*! DENOM - DENOM */
6019 #define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK)
6020 /*! @} */
6021 
6022 /*! @name PLL_VIDEO_NUMERATOR - PLL_VIDEO_NUMERATOR_REGISTER */
6023 /*! @{ */
6024 
6025 #define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK  (0x3FFFFFFFU)
6026 #define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT (0U)
6027 /*! NUM - NUM */
6028 #define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK)
6029 /*! @} */
6030 
6031 /*! @name PLL_VIDEO_DIV_SELECT - PLL_VIDEO_DIV_SELECT_REGISTER */
6032 /*! @{ */
6033 
6034 #define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK (0x7FU)
6035 #define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT (0U)
6036 /*! DIV_SELECT - DIV_SELECT */
6037 #define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK)
6038 /*! @} */
6039 
6040 
6041 /*!
6042  * @}
6043  */ /* end of group ANADIG_PLL_Register_Masks */
6044 
6045 
6046 /* ANADIG_PLL - Peripheral instance base addresses */
6047 /** Peripheral ANADIG_PLL base address */
6048 #define ANADIG_PLL_BASE                          (0x40C84000u)
6049 /** Peripheral ANADIG_PLL base pointer */
6050 #define ANADIG_PLL                               ((ANADIG_PLL_Type *)ANADIG_PLL_BASE)
6051 /** Array initializer of ANADIG_PLL peripheral base addresses */
6052 #define ANADIG_PLL_BASE_ADDRS                    { ANADIG_PLL_BASE }
6053 /** Array initializer of ANADIG_PLL peripheral base pointers */
6054 #define ANADIG_PLL_BASE_PTRS                     { ANADIG_PLL }
6055 
6056 /*!
6057  * @}
6058  */ /* end of group ANADIG_PLL_Peripheral_Access_Layer */
6059 
6060 
6061 /* ----------------------------------------------------------------------------
6062    -- ANADIG_PMU Peripheral Access Layer
6063    ---------------------------------------------------------------------------- */
6064 
6065 /*!
6066  * @addtogroup ANADIG_PMU_Peripheral_Access_Layer ANADIG_PMU Peripheral Access Layer
6067  * @{
6068  */
6069 
6070 /** ANADIG_PMU - Register Layout Typedef */
6071 typedef struct {
6072        uint8_t RESERVED_0[1280];
6073   __IO uint32_t PMU_LDO_PLL;                       /**< PMU_LDO_PLL_REGISTER, offset: 0x500 */
6074        uint8_t RESERVED_1[76];
6075   __IO uint32_t PMU_BIAS_CTRL;                     /**< PMU_BIAS_CTRL_REGISTER, offset: 0x550 */
6076        uint8_t RESERVED_2[12];
6077   __IO uint32_t PMU_BIAS_CTRL2;                    /**< PMU_BIAS_CTRL2_REGISTER, offset: 0x560 */
6078        uint8_t RESERVED_3[12];
6079   __IO uint32_t PMU_REF_CTRL;                      /**< PMU_REF_CTRL_REGISTER, offset: 0x570 */
6080        uint8_t RESERVED_4[12];
6081   __IO uint32_t PMU_POWER_DETECT_CTRL;             /**< PMU_POWER_DETECT_CTRL_REGISTER, offset: 0x580 */
6082        uint8_t RESERVED_5[124];
6083   __IO uint32_t LDO_PLL_ENABLE_SP;                 /**< LDO_PLL_ENABLE_SP_REGISTER, offset: 0x600 */
6084        uint8_t RESERVED_6[12];
6085   __IO uint32_t LDO_LPSR_ANA_ENABLE_SP;            /**< LDO_LPSR_ANA_ENABLE_SP_REGISTER, offset: 0x610 */
6086        uint8_t RESERVED_7[12];
6087   __IO uint32_t LDO_LPSR_ANA_LP_MODE_SP;           /**< LDO_LPSR_ANA_LP_MODE_SP_REGISTER, offset: 0x620 */
6088        uint8_t RESERVED_8[12];
6089   __IO uint32_t LDO_LPSR_ANA_TRACKING_EN_SP;       /**< LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER, offset: 0x630 */
6090        uint8_t RESERVED_9[12];
6091   __IO uint32_t LDO_LPSR_ANA_BYPASS_EN_SP;         /**< LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER, offset: 0x640 */
6092        uint8_t RESERVED_10[12];
6093   __IO uint32_t LDO_LPSR_ANA_STBY_EN_SP;           /**< LDO_LPSR_ANA_STBY_EN_SP_REGISTER, offset: 0x650 */
6094        uint8_t RESERVED_11[12];
6095   __IO uint32_t LDO_LPSR_DIG_ENABLE_SP;            /**< LDO_LPSR_DIG_ENABLE_SP_REGISTER, offset: 0x660 */
6096        uint8_t RESERVED_12[12];
6097   __IO uint32_t LDO_LPSR_DIG_TRG_SP0;              /**< LDO_LPSR_DIG_TRG_SP0_REGISTER, offset: 0x670 */
6098        uint8_t RESERVED_13[12];
6099   __IO uint32_t LDO_LPSR_DIG_TRG_SP1;              /**< LDO_LPSR_DIG_TRG_SP1_REGISTER, offset: 0x680 */
6100        uint8_t RESERVED_14[12];
6101   __IO uint32_t LDO_LPSR_DIG_TRG_SP2;              /**< LDO_LPSR_DIG_TRG_SP2_REGISTER, offset: 0x690 */
6102        uint8_t RESERVED_15[12];
6103   __IO uint32_t LDO_LPSR_DIG_TRG_SP3;              /**< LDO_LPSR_DIG_TRG_SP3_REGISTER, offset: 0x6A0 */
6104        uint8_t RESERVED_16[12];
6105   __IO uint32_t LDO_LPSR_DIG_LP_MODE_SP;           /**< LDO_LPSR_DIG_LP_MODE_SP_REGISTER, offset: 0x6B0 */
6106        uint8_t RESERVED_17[12];
6107   __IO uint32_t LDO_LPSR_DIG_TRACKING_EN_SP;       /**< LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER, offset: 0x6C0 */
6108        uint8_t RESERVED_18[12];
6109   __IO uint32_t LDO_LPSR_DIG_BYPASS_EN_SP;         /**< LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER, offset: 0x6D0 */
6110        uint8_t RESERVED_19[12];
6111   __IO uint32_t LDO_LPSR_DIG_STBY_EN_SP;           /**< LDO_LPSR_DIG_STBY_EN_SP_REGISTER, offset: 0x6E0 */
6112        uint8_t RESERVED_20[12];
6113   __IO uint32_t BANDGAP_ENABLE_SP;                 /**< BANDGAP_ENABLE_SP_REGISTER, offset: 0x6F0 */
6114        uint8_t RESERVED_21[12];
6115   __IO uint32_t FBB_M7_ENABLE_SP;                  /**< FBB_M7_ENABLE_SP_REGISTER, offset: 0x700 */
6116        uint8_t RESERVED_22[12];
6117   __IO uint32_t RBB_SOC_ENABLE_SP;                 /**< RBB_SOC_ENABLE_SP_REGISTER, offset: 0x710 */
6118        uint8_t RESERVED_23[12];
6119   __IO uint32_t RBB_LPSR_ENABLE_SP;                /**< RBB_LPSR_ENABLE_SP_REGISTER, offset: 0x720 */
6120        uint8_t RESERVED_24[12];
6121   __IO uint32_t BANDGAP_STBY_EN_SP;                /**< BANDGAP_STBY_EN_SP_REGISTER, offset: 0x730 */
6122        uint8_t RESERVED_25[12];
6123   __IO uint32_t PLL_LDO_STBY_EN_SP;                /**< PLL_LDO_STBY_EN_SP_REGISTER, offset: 0x740 */
6124        uint8_t RESERVED_26[12];
6125   __IO uint32_t FBB_M7_STBY_EN_SP;                 /**< FBB_M7_STBY_EN_SP_REGISTER, offset: 0x750 */
6126        uint8_t RESERVED_27[12];
6127   __IO uint32_t RBB_SOC_STBY_EN_SP;                /**< RBB_SOC_STBY_EN_SP_REGISTER, offset: 0x760 */
6128        uint8_t RESERVED_28[12];
6129   __IO uint32_t RBB_LPSR_STBY_EN_SP;               /**< RBB_LPSR_STBY_EN_SP_REGISTER, offset: 0x770 */
6130        uint8_t RESERVED_29[12];
6131   __IO uint32_t FBB_M7_CONFIGURE;                  /**< FBB_M7_CONFIGURE_REGISTER, offset: 0x780 */
6132        uint8_t RESERVED_30[12];
6133   __IO uint32_t RBB_LPSR_CONFIGURE;                /**< RBB_LPSR_CONFIGURE_REGISTER, offset: 0x790 */
6134        uint8_t RESERVED_31[12];
6135   __IO uint32_t RBB_SOC_CONFIGURE;                 /**< RBB_SOC_CONFIGURE_REGISTER, offset: 0x7A0 */
6136        uint8_t RESERVED_32[12];
6137   __I  uint32_t REFTOP_OTP_TRIM_VALUE;             /**< REFTOP_OTP_TRIM_VALUE_REGISTER, offset: 0x7B0 */
6138        uint8_t RESERVED_33[28];
6139   __I  uint32_t LPSR_1P8_LDO_OTP_TRIM_VALUE;       /**< LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER, offset: 0x7D0 */
6140 } ANADIG_PMU_Type;
6141 
6142 /* ----------------------------------------------------------------------------
6143    -- ANADIG_PMU Register Masks
6144    ---------------------------------------------------------------------------- */
6145 
6146 /*!
6147  * @addtogroup ANADIG_PMU_Register_Masks ANADIG_PMU Register Masks
6148  * @{
6149  */
6150 
6151 /*! @name PMU_LDO_PLL - PMU_LDO_PLL_REGISTER */
6152 /*! @{ */
6153 
6154 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK (0x1U)
6155 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT (0U)
6156 /*! LDO_PLL_ENABLE - LDO_PLL_ENABLE */
6157 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK)
6158 
6159 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK (0x2U)
6160 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT (1U)
6161 /*! LDO_PLL_CONTROL_MODE - LDO_PLL_CONTROL_MODE
6162  *  0b0..SW Control
6163  *  0b1..HW Control
6164  */
6165 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK)
6166 
6167 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK (0x10000U)
6168 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT (16U)
6169 /*! LDO_PLL_AI_TOGGLE - ldo_pll_ai_toggle */
6170 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK)
6171 
6172 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK (0x40000000U)
6173 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT (30U)
6174 /*! LDO_PLL_AI_BUSY - ldo_pll_busy */
6175 #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK)
6176 /*! @} */
6177 
6178 /*! @name PMU_BIAS_CTRL - PMU_BIAS_CTRL_REGISTER */
6179 /*! @{ */
6180 
6181 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK (0x1FFFU)
6182 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT (0U)
6183 /*! WB_CFG_1P8 - wb_cfg_1p8 */
6184 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK)
6185 
6186 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK (0x4000U)
6187 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT (14U)
6188 /*! WB_VDD_SEL_1P8 - wb_vdd_sel_1p8
6189  *  0b0..VDD_LV1
6190  *  0b1..VDD_LV2
6191  */
6192 #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK)
6193 /*! @} */
6194 
6195 /*! @name PMU_BIAS_CTRL2 - PMU_BIAS_CTRL2_REGISTER */
6196 /*! @{ */
6197 
6198 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK (0x3FEU)
6199 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT (1U)
6200 /*! WB_TST_MD - TMOD_wb_tst_md_1p8 */
6201 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK)
6202 
6203 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK (0x1C00U)
6204 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT (10U)
6205 /*! WB_PWR_SW_EN_1P8 - MODSEL_wb_tst_md_1p8
6206  *  0b001..No BB
6207  *  0b010..BB
6208  *  0b100..BB
6209  */
6210 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK)
6211 
6212 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK (0x1FE000U)
6213 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT (13U)
6214 /*! WB_ADJ_1P8 - wb_adj_1p8
6215  *  0b00000000..Cref= 0fF Cspl= 0fF DeltaC= 0fF
6216  *  0b00000001..Cref= 0fF Cspl= 30fF DeltaC= -30fF
6217  *  0b00000010..Cref= 0fF Cspl= 43fF DeltaC= -43fF
6218  *  0b00000011..Cref= 0fF Cspl= 62fF DeltaC=-62fF
6219  *  0b00000100..Cref= 0fF Cspl=105fF DeltaC=-105fF
6220  *  0b00000101..Cref= 30fF Cspl= 0fF DeltaC= 30fF
6221  *  0b00000110..Cref= 30fF Cspl= 43fF DeltaC= -12fF
6222  *  0b00000111..Cref= 30fF Cspl=105fF DeltaC= -75fF
6223  *  0b00001000..Cref= 43fF Cspl= 0fF DeltaC= 43fF
6224  *  0b00001001..Cref= 43fF Cspl= 30fF DeltaC= 13fF
6225  *  0b00001010..Cref= 43fF Cspl= 62fF DeltaC= -19fF
6226  *  0b00001011..Cref= 62fF Cspl= 0fF DeltaC= 62fF
6227  *  0b00001100..Cref= 62fF Cspl= 43fF DeltaC= 19fF
6228  *  0b00001101..Cref=105fF Cspl= 0fF DeltaC= 105fF
6229  *  0b00001110..Cref=105fF Cspl=30fF DeltaC= 75fF
6230  *  0b00001111..Cref=0fF Cspl=0fF DeltaC= 0fF
6231  */
6232 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(x)  (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK)
6233 
6234 #define ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK (0x200000U)
6235 #define ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_SHIFT (21U)
6236 /*! FBB_M7_CONTROL_MODE - FBB_M7_CONTROL_MODE
6237  *  0b0..SW Control
6238  *  0b1..HW Control
6239  */
6240 #define ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK)
6241 
6242 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK (0x400000U)
6243 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT (22U)
6244 /*! RBB_SOC_CONTROL_MODE - RBB_SOC_CONTROL_MODE
6245  *  0b0..SW Control
6246  *  0b1..HW Control
6247  */
6248 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK)
6249 
6250 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK (0x800000U)
6251 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT (23U)
6252 /*! RBB_LPSR_CONTROL_MODE - RBB_LPSR_CONTROL_MODE
6253  *  0b0..SW Control
6254  *  0b1..HW Control
6255  */
6256 #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK)
6257 
6258 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK     (0x1000000U)
6259 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT    (24U)
6260 /*! WB_EN - wb_en */
6261 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK)
6262 
6263 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK (0x2000000U)
6264 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT (25U)
6265 /*! WB_TST_DIG_OUT - Digital output */
6266 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK)
6267 
6268 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK     (0x4000000U)
6269 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT    (26U)
6270 /*! WB_OK - Digital Output pin. */
6271 #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK(x)       (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK)
6272 /*! @} */
6273 
6274 /*! @name PMU_REF_CTRL - PMU_REF_CTRL_REGISTER */
6275 /*! @{ */
6276 
6277 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK (0x1U)
6278 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT (0U)
6279 /*! REF_AI_TOGGLE - ref_ai_toggle */
6280 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK)
6281 
6282 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK (0x2U)
6283 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT (1U)
6284 /*! REF_AI_BUSY - ref_ai_busy */
6285 #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY(x)   (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK)
6286 
6287 #define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK  (0x4U)
6288 #define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT (2U)
6289 /*! REF_ENABLE - REF_ENABLE */
6290 #define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE(x)    (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK)
6291 
6292 #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK (0x8U)
6293 #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT (3U)
6294 /*! REF_CONTROL_MODE - REF_CONTROL_MODE
6295  *  0b0..SW Control
6296  *  0b1..HW Control
6297  */
6298 #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK)
6299 
6300 #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK (0x10U)
6301 #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT (4U)
6302 /*! EN_PLL_VOL_REF_BUFFER - en_pll_vol_ref_buffer */
6303 #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK)
6304 /*! @} */
6305 
6306 /*! @name PMU_POWER_DETECT_CTRL - PMU_POWER_DETECT_CTRL_REGISTER */
6307 /*! @{ */
6308 
6309 #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK (0x100U)
6310 #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT (8U)
6311 /*! CKGB_LPSR1P0 - ckgb_lpsr1p0 */
6312 #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT)) & ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK)
6313 /*! @} */
6314 
6315 /*! @name LDO_PLL_ENABLE_SP - LDO_PLL_ENABLE_SP_REGISTER */
6316 /*! @{ */
6317 
6318 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
6319 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
6320 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
6321  *  0b0..ON
6322  *  0b1..OFF
6323  */
6324 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
6325 
6326 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
6327 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
6328 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
6329  *  0b0..ON
6330  *  0b1..OFF
6331  */
6332 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
6333 
6334 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
6335 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
6336 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
6337  *  0b0..ON
6338  *  0b1..OFF
6339  */
6340 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
6341 
6342 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
6343 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
6344 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
6345  *  0b0..ON
6346  *  0b1..OFF
6347  */
6348 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
6349 
6350 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
6351 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
6352 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
6353  *  0b0..ON
6354  *  0b1..OFF
6355  */
6356 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
6357 
6358 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
6359 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
6360 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
6361  *  0b0..ON
6362  *  0b1..OFF
6363  */
6364 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
6365 
6366 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
6367 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
6368 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
6369  *  0b0..ON
6370  *  0b1..OFF
6371  */
6372 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
6373 
6374 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
6375 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
6376 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
6377  *  0b0..ON
6378  *  0b1..OFF
6379  */
6380 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
6381 
6382 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
6383 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
6384 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
6385  *  0b0..ON
6386  *  0b1..OFF
6387  */
6388 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
6389 
6390 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
6391 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
6392 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
6393  *  0b0..ON
6394  *  0b1..OFF
6395  */
6396 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
6397 
6398 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
6399 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
6400 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
6401  *  0b0..ON
6402  *  0b1..OFF
6403  */
6404 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
6405 
6406 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
6407 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
6408 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
6409  *  0b0..ON
6410  *  0b1..OFF
6411  */
6412 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
6413 
6414 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
6415 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
6416 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
6417  *  0b0..ON
6418  *  0b1..OFF
6419  */
6420 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
6421 
6422 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
6423 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
6424 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
6425  *  0b0..ON
6426  *  0b1..OFF
6427  */
6428 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
6429 
6430 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
6431 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
6432 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
6433  *  0b0..ON
6434  *  0b1..OFF
6435  */
6436 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
6437 
6438 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
6439 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
6440 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
6441  *  0b0..ON
6442  *  0b1..OFF
6443  */
6444 #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
6445 /*! @} */
6446 
6447 /*! @name LDO_LPSR_ANA_ENABLE_SP - LDO_LPSR_ANA_ENABLE_SP_REGISTER */
6448 /*! @{ */
6449 
6450 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
6451 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
6452 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
6453  *  0b0..ON
6454  *  0b1..OFF
6455  */
6456 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
6457 
6458 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
6459 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
6460 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
6461  *  0b0..ON
6462  *  0b1..OFF
6463  */
6464 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
6465 
6466 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
6467 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
6468 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
6469  *  0b0..ON
6470  *  0b1..OFF
6471  */
6472 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
6473 
6474 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
6475 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
6476 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
6477  *  0b0..ON
6478  *  0b1..OFF
6479  */
6480 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
6481 
6482 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
6483 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
6484 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
6485  *  0b0..ON
6486  *  0b1..OFF
6487  */
6488 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
6489 
6490 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
6491 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
6492 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
6493  *  0b0..ON
6494  *  0b1..OFF
6495  */
6496 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
6497 
6498 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
6499 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
6500 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
6501  *  0b0..ON
6502  *  0b1..OFF
6503  */
6504 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
6505 
6506 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
6507 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
6508 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
6509  *  0b0..ON
6510  *  0b1..OFF
6511  */
6512 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
6513 
6514 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
6515 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
6516 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
6517  *  0b0..ON
6518  *  0b1..OFF
6519  */
6520 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
6521 
6522 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
6523 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
6524 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
6525  *  0b0..ON
6526  *  0b1..OFF
6527  */
6528 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
6529 
6530 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
6531 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
6532 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
6533  *  0b0..ON
6534  *  0b1..OFF
6535  */
6536 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
6537 
6538 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
6539 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
6540 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
6541  *  0b0..ON
6542  *  0b1..OFF
6543  */
6544 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
6545 
6546 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
6547 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
6548 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
6549  *  0b0..ON
6550  *  0b1..OFF
6551  */
6552 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
6553 
6554 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
6555 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
6556 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
6557  *  0b0..ON
6558  *  0b1..OFF
6559  */
6560 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
6561 
6562 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
6563 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
6564 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
6565  *  0b0..ON
6566  *  0b1..OFF
6567  */
6568 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
6569 
6570 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
6571 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
6572 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
6573  *  0b0..ON
6574  *  0b1..OFF
6575  */
6576 #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
6577 /*! @} */
6578 
6579 /*! @name LDO_LPSR_ANA_LP_MODE_SP - LDO_LPSR_ANA_LP_MODE_SP_REGISTER */
6580 /*! @{ */
6581 
6582 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U)
6583 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U)
6584 /*! LP_MODE_SETPOINT0 - LP_MODE_SETPOINT0
6585  *  0b0..LP
6586  *  0b1..HP
6587  */
6588 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK)
6589 
6590 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U)
6591 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U)
6592 /*! LP_MODE_SETPOINT1 - LP_MODE_SETPOINT1
6593  *  0b0..LP
6594  *  0b1..HP
6595  */
6596 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK)
6597 
6598 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK (0x4U)
6599 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT (2U)
6600 /*! LP_MODE_SETPONIT2 - LP_MODE_SETPOINT2
6601  *  0b0..LP
6602  *  0b1..HP
6603  */
6604 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK)
6605 
6606 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK (0x8U)
6607 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT (3U)
6608 /*! LP_MODE_SETPONIT3 - LP_MODE_SETPOINT3
6609  *  0b0..LP
6610  *  0b1..HP
6611  */
6612 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK)
6613 
6614 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK (0x10U)
6615 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT (4U)
6616 /*! LP_MODE_SETPONIT4 - LP_MODE_SETPOINT4
6617  *  0b0..LP
6618  *  0b1..HP
6619  */
6620 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK)
6621 
6622 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK (0x20U)
6623 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT (5U)
6624 /*! LP_MODE_SETPONIT5 - LP_MODE_SETPOINT5
6625  *  0b0..LP
6626  *  0b1..HP
6627  */
6628 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK)
6629 
6630 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK (0x40U)
6631 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT (6U)
6632 /*! LP_MODE_SETPONIT6 - LP_MODE_SETPOINT6
6633  *  0b0..LP
6634  *  0b1..HP
6635  */
6636 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK)
6637 
6638 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK (0x80U)
6639 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT (7U)
6640 /*! LP_MODE_SETPONIT7 - LP_MODE_SETPOINT7
6641  *  0b0..LP
6642  *  0b1..HP
6643  */
6644 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK)
6645 
6646 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK (0x100U)
6647 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT (8U)
6648 /*! LP_MODE_SETPONIT8 - LP_MODE_SETPOINT8
6649  *  0b0..LP
6650  *  0b1..HP
6651  */
6652 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK)
6653 
6654 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK (0x200U)
6655 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT (9U)
6656 /*! LP_MODE_SETPONIT9 - LP_MODE_SETPOINT9
6657  *  0b0..LP
6658  *  0b1..HP
6659  */
6660 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK)
6661 
6662 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK (0x400U)
6663 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT (10U)
6664 /*! LP_MODE_SETPONIT10 - LP_MODE_SETPOINT10
6665  *  0b0..LP
6666  *  0b1..HP
6667  */
6668 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK)
6669 
6670 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK (0x800U)
6671 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT (11U)
6672 /*! LP_MODE_SETPONIT11 - LP_MODE_SETPOINT11
6673  *  0b0..LP
6674  *  0b1..HP
6675  */
6676 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK)
6677 
6678 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK (0x1000U)
6679 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT (12U)
6680 /*! LP_MODE_SETPONIT12 - LP_MODE_SETPOINT12
6681  *  0b0..LP
6682  *  0b1..HP
6683  */
6684 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK)
6685 
6686 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK (0x2000U)
6687 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT (13U)
6688 /*! LP_MODE_SETPONIT13 - LP_MODE_SETPOINT13
6689  *  0b0..LP
6690  *  0b1..HP
6691  */
6692 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK)
6693 
6694 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK (0x4000U)
6695 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT (14U)
6696 /*! LP_MODE_SETPONIT14 - LP_MODE_SETPOINT14
6697  *  0b0..LP
6698  *  0b1..HP
6699  */
6700 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK)
6701 
6702 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK (0x8000U)
6703 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT (15U)
6704 /*! LP_MODE_SETPONIT15 - LP_MODE_SETPOINT15
6705  *  0b0..LP
6706  *  0b1..HP
6707  */
6708 #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK)
6709 /*! @} */
6710 
6711 /*! @name LDO_LPSR_ANA_TRACKING_EN_SP - LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER */
6712 /*! @{ */
6713 
6714 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U)
6715 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U)
6716 /*! TRACKING_EN_SETPOINT0 - TRACKING_EN_SETPOINT0
6717  *  0b0..Disabled
6718  *  0b1..Enabled
6719  */
6720 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK)
6721 
6722 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U)
6723 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U)
6724 /*! TRACKING_EN_SETPOINT1 - TRACKING_EN_SETPOINT1
6725  *  0b0..Disabled
6726  *  0b1..Enabled
6727  */
6728 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK)
6729 
6730 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U)
6731 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U)
6732 /*! TRACKING_EN_SETPOINT2 - TRACKING_EN_SETPOINT2
6733  *  0b0..Disabled
6734  *  0b1..Enabled
6735  */
6736 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK)
6737 
6738 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U)
6739 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U)
6740 /*! TRACKING_EN_SETPOINT3 - TRACKING_EN_SETPOINT3
6741  *  0b0..Disabled
6742  *  0b1..Enabled
6743  */
6744 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK)
6745 
6746 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U)
6747 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U)
6748 /*! TRACKING_EN_SETPOINT4 - TRACKING_EN_SETPOINT4
6749  *  0b0..Disabled
6750  *  0b1..Enabled
6751  */
6752 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK)
6753 
6754 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U)
6755 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U)
6756 /*! TRACKING_EN_SETPOINT5 - TRACKING_EN_SETPOINT5
6757  *  0b0..Disabled
6758  *  0b1..Enabled
6759  */
6760 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK)
6761 
6762 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U)
6763 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U)
6764 /*! TRACKING_EN_SETPOINT6 - TRACKING_EN_SETPOINT6
6765  *  0b0..Disabled
6766  *  0b1..Enabled
6767  */
6768 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK)
6769 
6770 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U)
6771 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U)
6772 /*! TRACKING_EN_SETPOINT7 - TRACKING_EN_SETPOINT7
6773  *  0b0..Disabled
6774  *  0b1..Enabled
6775  */
6776 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK)
6777 
6778 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U)
6779 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U)
6780 /*! TRACKING_EN_SETPOINT8 - TRACKING_EN_SETPOINT8
6781  *  0b0..Disabled
6782  *  0b1..Enabled
6783  */
6784 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK)
6785 
6786 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U)
6787 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U)
6788 /*! TRACKING_EN_SETPOINT9 - TRACKING_EN_SETPOINT9
6789  *  0b0..Disabled
6790  *  0b1..Enabled
6791  */
6792 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK)
6793 
6794 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U)
6795 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U)
6796 /*! TRACKING_EN_SETPOINT10 - TRACKING_EN_SETPOINT10
6797  *  0b0..Disabled
6798  *  0b1..Enabled
6799  */
6800 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK)
6801 
6802 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U)
6803 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U)
6804 /*! TRACKING_EN_SETPOINT11 - TRACKING_EN_SETPOINT11
6805  *  0b0..Disabled
6806  *  0b1..Enabled
6807  */
6808 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK)
6809 
6810 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U)
6811 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U)
6812 /*! TRACKING_EN_SETPOINT12 - TRACKING_EN_SETPOINT12
6813  *  0b0..Disabled
6814  *  0b1..Enabled
6815  */
6816 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK)
6817 
6818 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U)
6819 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U)
6820 /*! TRACKING_EN_SETPOINT13 - TRACKING_EN_SETPOINT13
6821  *  0b0..Disabled
6822  *  0b1..Enabled
6823  */
6824 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK)
6825 
6826 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U)
6827 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U)
6828 /*! TRACKING_EN_SETPOINT14 - TRACKING_EN_SETPOINT14
6829  *  0b0..Disabled
6830  *  0b1..Enabled
6831  */
6832 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK)
6833 
6834 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U)
6835 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U)
6836 /*! TRACKING_EN_SETPOINT15 - TRACKING_EN_SETPOINT15
6837  *  0b0..Disabled
6838  *  0b1..Enabled
6839  */
6840 #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK)
6841 /*! @} */
6842 
6843 /*! @name LDO_LPSR_ANA_BYPASS_EN_SP - LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER */
6844 /*! @{ */
6845 
6846 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U)
6847 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U)
6848 /*! BYPASS_EN_SETPOINT0 - BYPASS_EN_SETPOINT0
6849  *  0b0..Disabled
6850  *  0b1..Enabled
6851  */
6852 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK)
6853 
6854 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U)
6855 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U)
6856 /*! BYPASS_EN_SETPOINT1 - BYPASS_EN_SETPOINT1
6857  *  0b0..Disabled
6858  *  0b1..Enabled
6859  */
6860 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK)
6861 
6862 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U)
6863 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U)
6864 /*! BYPASS_EN_SETPOINT2 - BYPASS_EN_SETPOINT2
6865  *  0b0..Disabled
6866  *  0b1..Enabled
6867  */
6868 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK)
6869 
6870 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U)
6871 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U)
6872 /*! BYPASS_EN_SETPOINT3 - BYPASS_EN_SETPOINT3
6873  *  0b0..Disabled
6874  *  0b1..Enabled
6875  */
6876 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK)
6877 
6878 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U)
6879 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U)
6880 /*! BYPASS_EN_SETPOINT4 - BYPASS_EN_SETPOINT4
6881  *  0b0..Disabled
6882  *  0b1..Enabled
6883  */
6884 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK)
6885 
6886 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U)
6887 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U)
6888 /*! BYPASS_EN_SETPOINT5 - BYPASS_EN_SETPOINT5
6889  *  0b0..Disabled
6890  *  0b1..Enabled
6891  */
6892 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK)
6893 
6894 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U)
6895 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U)
6896 /*! BYPASS_EN_SETPOINT6 - BYPASS_EN_SETPOINT6
6897  *  0b0..Disabled
6898  *  0b1..Enabled
6899  */
6900 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK)
6901 
6902 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U)
6903 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U)
6904 /*! BYPASS_EN_SETPOINT7 - BYPASS_EN_SETPOINT7
6905  *  0b0..Disabled
6906  *  0b1..Enabled
6907  */
6908 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK)
6909 
6910 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U)
6911 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U)
6912 /*! BYPASS_EN_SETPOINT8 - BYPASS_EN_SETPOINT
6913  *  0b0..Disabled
6914  *  0b1..Enabled
6915  */
6916 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK)
6917 
6918 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U)
6919 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U)
6920 /*! BYPASS_EN_SETPOINT9 - BYPASS_EN_SETPOINT9
6921  *  0b0..Disabled
6922  *  0b1..Enabled
6923  */
6924 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK)
6925 
6926 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U)
6927 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U)
6928 /*! BYPASS_EN_SETPOINT10 - BYPASS_EN_SETPOINT10
6929  *  0b0..Disabled
6930  *  0b1..Enabled
6931  */
6932 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK)
6933 
6934 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U)
6935 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U)
6936 /*! BYPASS_EN_SETPOINT11 - BYPASS_EN_SETPOINT11
6937  *  0b0..Disabled
6938  *  0b1..Enabled
6939  */
6940 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK)
6941 
6942 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U)
6943 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U)
6944 /*! BYPASS_EN_SETPOINT12 - BYPASS_EN_SETPOINT12
6945  *  0b0..Disabled
6946  *  0b1..Enabled
6947  */
6948 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK)
6949 
6950 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U)
6951 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U)
6952 /*! BYPASS_EN_SETPOINT13 - BYPASS_EN_SETPOINT13
6953  *  0b0..Disabled
6954  *  0b1..Enabled
6955  */
6956 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK)
6957 
6958 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U)
6959 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U)
6960 /*! BYPASS_EN_SETPOINT14 - BYPASS_EN_SETPOINT14
6961  *  0b0..Disabled
6962  *  0b1..Enabled
6963  */
6964 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK)
6965 
6966 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U)
6967 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U)
6968 /*! BYPASS_EN_SETPOINT15 - BYPASS_EN_SETPOINT15
6969  *  0b0..Disabled
6970  *  0b1..Enabled
6971  */
6972 #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK)
6973 /*! @} */
6974 
6975 /*! @name LDO_LPSR_ANA_STBY_EN_SP - LDO_LPSR_ANA_STBY_EN_SP_REGISTER */
6976 /*! @{ */
6977 
6978 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
6979 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
6980 /*! STBY_EN_SETPOINT0 - STBY_EN_SETPOINT0
6981  *  0b0..Disabled
6982  *  0b1..Enabled
6983  */
6984 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
6985 
6986 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
6987 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
6988 /*! STBY_EN_SETPOINT1 - STBY_EN_SETPOINT1
6989  *  0b0..Disabled
6990  *  0b1..Enabled
6991  */
6992 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
6993 
6994 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
6995 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
6996 /*! STBY_EN_SETPOINT2 - STBY_EN_SETPOINT2
6997  *  0b0..Disabled
6998  *  0b1..Enabled
6999  */
7000 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
7001 
7002 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
7003 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
7004 /*! STBY_EN_SETPOINT3 - STBY_EN_SETPOINT3
7005  *  0b0..Disabled
7006  *  0b1..Enabled
7007  */
7008 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
7009 
7010 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
7011 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
7012 /*! STBY_EN_SETPOINT4 - STBY_EN_SETPOINT4
7013  *  0b0..Disabled
7014  *  0b1..Enabled
7015  */
7016 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
7017 
7018 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
7019 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
7020 /*! STBY_EN_SETPOINT5 - STBY_EN_SETPOINT5
7021  *  0b0..Disabled
7022  *  0b1..Enabled
7023  */
7024 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
7025 
7026 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
7027 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
7028 /*! STBY_EN_SETPOINT6 - STBY_EN_SETPOINT6
7029  *  0b0..Disabled
7030  *  0b1..Enabled
7031  */
7032 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
7033 
7034 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
7035 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
7036 /*! STBY_EN_SETPOINT7 - STBY_EN_SETPOINT7
7037  *  0b0..Disabled
7038  *  0b1..Enabled
7039  */
7040 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
7041 
7042 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
7043 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
7044 /*! STBY_EN_SETPOINT8 - STBY_EN_SETPOINT8
7045  *  0b0..Disabled
7046  *  0b1..Enabled
7047  */
7048 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
7049 
7050 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
7051 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
7052 /*! STBY_EN_SETPOINT9 - STBY_EN_SETPOINT9
7053  *  0b0..Disabled
7054  *  0b1..Enabled
7055  */
7056 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
7057 
7058 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
7059 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
7060 /*! STBY_EN_SETPOINT10 - STBY_EN_SETPOINT10
7061  *  0b0..Disabled
7062  *  0b1..Enabled
7063  */
7064 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
7065 
7066 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
7067 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
7068 /*! STBY_EN_SETPOINT11 - STBY_EN_SETPOINT11
7069  *  0b0..Disabled
7070  *  0b1..Enabled
7071  */
7072 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
7073 
7074 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
7075 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
7076 /*! STBY_EN_SETPOINT12 - STBY_EN_SETPOINT12
7077  *  0b0..Disabled
7078  *  0b1..Enabled
7079  */
7080 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
7081 
7082 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
7083 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
7084 /*! STBY_EN_SETPOINT13 - STBY_EN_SETPOINT13
7085  *  0b0..Disabled
7086  *  0b1..Enabled
7087  */
7088 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
7089 
7090 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
7091 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
7092 /*! STBY_EN_SETPOINT14 - STBY_EN_SETPOINT14
7093  *  0b0..Disabled
7094  *  0b1..Enabled
7095  */
7096 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
7097 
7098 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
7099 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
7100 /*! STBY_EN_SETPOINT15 - STBY_EN_SETPOINT15
7101  *  0b0..Disabled
7102  *  0b1..Enabled
7103  */
7104 #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
7105 /*! @} */
7106 
7107 /*! @name LDO_LPSR_DIG_ENABLE_SP - LDO_LPSR_DIG_ENABLE_SP_REGISTER */
7108 /*! @{ */
7109 
7110 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
7111 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
7112 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
7113  *  0b0..ON
7114  *  0b1..OFF
7115  */
7116 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
7117 
7118 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
7119 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
7120 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
7121  *  0b0..ON
7122  *  0b1..OFF
7123  */
7124 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
7125 
7126 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
7127 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
7128 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
7129  *  0b0..ON
7130  *  0b1..OFF
7131  */
7132 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
7133 
7134 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
7135 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
7136 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
7137  *  0b0..ON
7138  *  0b1..OFF
7139  */
7140 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
7141 
7142 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
7143 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
7144 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
7145  *  0b0..ON
7146  *  0b1..OFF
7147  */
7148 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
7149 
7150 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
7151 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
7152 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
7153  *  0b0..ON
7154  *  0b1..OFF
7155  */
7156 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
7157 
7158 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
7159 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
7160 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
7161  *  0b0..ON
7162  *  0b1..OFF
7163  */
7164 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
7165 
7166 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
7167 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
7168 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
7169  *  0b0..ON
7170  *  0b1..OFF
7171  */
7172 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
7173 
7174 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
7175 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
7176 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
7177  *  0b0..ON
7178  *  0b1..OFF
7179  */
7180 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
7181 
7182 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
7183 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
7184 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
7185  *  0b0..ON
7186  *  0b1..OFF
7187  */
7188 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
7189 
7190 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
7191 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
7192 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
7193  *  0b0..ON
7194  *  0b1..OFF
7195  */
7196 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
7197 
7198 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
7199 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
7200 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
7201  *  0b0..ON
7202  *  0b1..OFF
7203  */
7204 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
7205 
7206 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
7207 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
7208 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
7209  *  0b0..ON
7210  *  0b1..OFF
7211  */
7212 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
7213 
7214 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
7215 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
7216 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
7217  *  0b0..ON
7218  *  0b1..OFF
7219  */
7220 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
7221 
7222 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
7223 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
7224 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
7225  *  0b0..ON
7226  *  0b1..OFF
7227  */
7228 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
7229 
7230 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
7231 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
7232 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
7233  *  0b0..ON
7234  *  0b1..OFF
7235  */
7236 #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
7237 /*! @} */
7238 
7239 /*! @name LDO_LPSR_DIG_TRG_SP0 - LDO_LPSR_DIG_TRG_SP0_REGISTER */
7240 /*! @{ */
7241 
7242 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK (0xFFU)
7243 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT (0U)
7244 /*! VOLTAGE_SETPOINT0 - VOLTAGE_SETPOINT0 */
7245 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK)
7246 
7247 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK (0xFF00U)
7248 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT (8U)
7249 /*! VOLTAGE_SETPOINT1 - VOLTAGE_SETPOINT1 */
7250 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK)
7251 
7252 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK (0xFF0000U)
7253 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT (16U)
7254 /*! VOLTAGE_SETPOINT2 - VOLTAGE_SETPOINT2 */
7255 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK)
7256 
7257 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK (0xFF000000U)
7258 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT (24U)
7259 /*! VOLTAGE_SETPOINT3 - VOLTAGE_SETPOINT3 */
7260 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK)
7261 /*! @} */
7262 
7263 /*! @name LDO_LPSR_DIG_TRG_SP1 - LDO_LPSR_DIG_TRG_SP1_REGISTER */
7264 /*! @{ */
7265 
7266 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK (0xFFU)
7267 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT (0U)
7268 /*! VOLTAGE_SETPOINT4 - VOLTAGE_SETPOINT4 */
7269 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK)
7270 
7271 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK (0xFF00U)
7272 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT (8U)
7273 /*! VOLTAGE_SETPOINT5 - VOLTAGE_SETPOINT5 */
7274 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK)
7275 
7276 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK (0xFF0000U)
7277 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT (16U)
7278 /*! VOLTAGE_SETPOINT6 - VOLTAGE_SETPOINT6 */
7279 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK)
7280 
7281 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK (0xFF000000U)
7282 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT (24U)
7283 /*! VOLTAGE_SETPOINT7 - VOLTAGE_SETPOINT7 */
7284 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK)
7285 /*! @} */
7286 
7287 /*! @name LDO_LPSR_DIG_TRG_SP2 - LDO_LPSR_DIG_TRG_SP2_REGISTER */
7288 /*! @{ */
7289 
7290 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK (0xFFU)
7291 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT (0U)
7292 /*! VOLTAGE_SETPOINT8 - VOLTAGE_SETPOINT8 */
7293 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK)
7294 
7295 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK (0xFF00U)
7296 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT (8U)
7297 /*! VOLTAGE_SETPOINT9 - VOLTAGE_SETPOINT9 */
7298 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK)
7299 
7300 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK (0xFF0000U)
7301 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT (16U)
7302 /*! VOLTAGE_SETPOINT10 - VOLTAGE_SETPOINT10 */
7303 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK)
7304 
7305 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK (0xFF000000U)
7306 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT (24U)
7307 /*! VOLTAGE_SETPOINT11 - VOLTAGE_SETPOINT11 */
7308 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK)
7309 /*! @} */
7310 
7311 /*! @name LDO_LPSR_DIG_TRG_SP3 - LDO_LPSR_DIG_TRG_SP3_REGISTER */
7312 /*! @{ */
7313 
7314 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK (0xFFU)
7315 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT (0U)
7316 /*! VOLTAGE_SETPOINT12 - VOLTAGE_SETPOINT12 */
7317 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK)
7318 
7319 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK (0xFF00U)
7320 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT (8U)
7321 /*! VOLTAGE_SETPOINT13 - VOLTAGE_SETPOINT13 */
7322 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK)
7323 
7324 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK (0xFF0000U)
7325 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT (16U)
7326 /*! VOLTAGE_SETPOINT14 - VOLTAGE_SETPOINT14 */
7327 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK)
7328 
7329 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK (0xFF000000U)
7330 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT (24U)
7331 /*! VOLTAGE_SETPOINT15 - VOLTAGE_SETPOINT15 */
7332 #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK)
7333 /*! @} */
7334 
7335 /*! @name LDO_LPSR_DIG_LP_MODE_SP - LDO_LPSR_DIG_LP_MODE_SP_REGISTER */
7336 /*! @{ */
7337 
7338 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U)
7339 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U)
7340 /*! LP_MODE_SETPOINT0 - LP_MODE_SETPOINT0
7341  *  0b0..LP
7342  *  0b1..HP
7343  */
7344 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK)
7345 
7346 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U)
7347 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U)
7348 /*! LP_MODE_SETPOINT1 - LP_MODE_SETPOINT1
7349  *  0b0..LP
7350  *  0b1..HP
7351  */
7352 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK)
7353 
7354 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK (0x4U)
7355 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT (2U)
7356 /*! LP_MODE_SETPOINT2 - LP_MODE_SETPOINT2
7357  *  0b0..LP
7358  *  0b1..HP
7359  */
7360 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK)
7361 
7362 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK (0x8U)
7363 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT (3U)
7364 /*! LP_MODE_SETPOINT3 - LP_MODE_SETPOINT3
7365  *  0b0..LP
7366  *  0b1..HP
7367  */
7368 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK)
7369 
7370 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK (0x10U)
7371 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT (4U)
7372 /*! LP_MODE_SETPOINT4 - LP_MODE_SETPOINT4
7373  *  0b0..LP
7374  *  0b1..HP
7375  */
7376 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK)
7377 
7378 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK (0x20U)
7379 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT (5U)
7380 /*! LP_MODE_SETPOINT5 - LP_MODE_SETPOINT5
7381  *  0b0..LP
7382  *  0b1..HP
7383  */
7384 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK)
7385 
7386 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK (0x40U)
7387 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT (6U)
7388 /*! LP_MODE_SETPOINT6 - LP_MODE_SETPOINT6
7389  *  0b0..LP
7390  *  0b1..HP
7391  */
7392 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK)
7393 
7394 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK (0x80U)
7395 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT (7U)
7396 /*! LP_MODE_SETPOINT7 - LP_MODE_SETPOINT7
7397  *  0b0..LP
7398  *  0b1..HP
7399  */
7400 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK)
7401 
7402 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK (0x100U)
7403 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT (8U)
7404 /*! LP_MODE_SETPOINT8 - LP_MODE_SETPOINT8
7405  *  0b0..LP
7406  *  0b1..HP
7407  */
7408 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK)
7409 
7410 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK (0x200U)
7411 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT (9U)
7412 /*! LP_MODE_SETPOINT9 - LP_MODE_SETPOINT9
7413  *  0b0..LP
7414  *  0b1..HP
7415  */
7416 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK)
7417 
7418 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK (0x400U)
7419 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT (10U)
7420 /*! LP_MODE_SETPOINT10 - LP_MODE_SETPOINT10
7421  *  0b0..LP
7422  *  0b1..HP
7423  */
7424 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK)
7425 
7426 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK (0x800U)
7427 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT (11U)
7428 /*! LP_MODE_SETPOINT11 - LP_MODE_SETPOINT11
7429  *  0b0..LP
7430  *  0b1..HP
7431  */
7432 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK)
7433 
7434 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK (0x1000U)
7435 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT (12U)
7436 /*! LP_MODE_SETPOINT12 - LP_MODE_SETPOINT12
7437  *  0b0..LP
7438  *  0b1..HP
7439  */
7440 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK)
7441 
7442 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK (0x2000U)
7443 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT (13U)
7444 /*! LP_MODE_SETPOINT13 - LP_MODE_SETPOINT13
7445  *  0b0..LP
7446  *  0b1..HP
7447  */
7448 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK)
7449 
7450 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK (0x4000U)
7451 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT (14U)
7452 /*! LP_MODE_SETPOINT14 - LP_MODE_SETPOINT14
7453  *  0b0..LP
7454  *  0b1..HP
7455  */
7456 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK)
7457 
7458 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK (0x8000U)
7459 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT (15U)
7460 /*! LP_MODE_SETPOINT15 - LP_MODE_SETPOINT15
7461  *  0b0..LP
7462  *  0b1..HP
7463  */
7464 #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK)
7465 /*! @} */
7466 
7467 /*! @name LDO_LPSR_DIG_TRACKING_EN_SP - LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER */
7468 /*! @{ */
7469 
7470 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U)
7471 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U)
7472 /*! TRACKING_EN_SETPOINT0 - TRACKING_EN_SETPOINT0
7473  *  0b0..Disabled
7474  *  0b1..Enabled
7475  */
7476 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK)
7477 
7478 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U)
7479 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U)
7480 /*! TRACKING_EN_SETPOINT1 - TRACKING_EN_SETPOINT1
7481  *  0b0..Disabled
7482  *  0b1..Enabled
7483  */
7484 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK)
7485 
7486 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U)
7487 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U)
7488 /*! TRACKING_EN_SETPOINT2 - TRACKING_EN_SETPOINT2
7489  *  0b0..Disabled
7490  *  0b1..Enabled
7491  */
7492 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK)
7493 
7494 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U)
7495 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U)
7496 /*! TRACKING_EN_SETPOINT3 - TRACKING_EN_SETPOINT3
7497  *  0b0..Disabled
7498  *  0b1..Enabled
7499  */
7500 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK)
7501 
7502 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U)
7503 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U)
7504 /*! TRACKING_EN_SETPOINT4 - TRACKING_EN_SETPOINT4
7505  *  0b0..Disabled
7506  *  0b1..Enabled
7507  */
7508 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK)
7509 
7510 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U)
7511 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U)
7512 /*! TRACKING_EN_SETPOINT5 - TRACKING_EN_SETPOINT5
7513  *  0b0..Disabled
7514  *  0b1..Enabled
7515  */
7516 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK)
7517 
7518 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U)
7519 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U)
7520 /*! TRACKING_EN_SETPOINT6 - TRACKING_EN_SETPOINT6
7521  *  0b0..Disabled
7522  *  0b1..Enabled
7523  */
7524 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK)
7525 
7526 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U)
7527 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U)
7528 /*! TRACKING_EN_SETPOINT7 - TRACKING_EN_SETPOINT7
7529  *  0b0..Disabled
7530  *  0b1..Enabled
7531  */
7532 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK)
7533 
7534 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U)
7535 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U)
7536 /*! TRACKING_EN_SETPOINT8 - TRACKING_EN_SETPOINT8
7537  *  0b0..Disabled
7538  *  0b1..Enabled
7539  */
7540 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK)
7541 
7542 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U)
7543 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U)
7544 /*! TRACKING_EN_SETPOINT9 - TRACKING_EN_SETPOINT9
7545  *  0b0..Disabled
7546  *  0b1..Enabled
7547  */
7548 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK)
7549 
7550 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U)
7551 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U)
7552 /*! TRACKING_EN_SETPOINT10 - TRACKING_EN_SETPOINT10
7553  *  0b0..Disabled
7554  *  0b1..Enabled
7555  */
7556 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK)
7557 
7558 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U)
7559 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U)
7560 /*! TRACKING_EN_SETPOINT11 - TRACKING_EN_SETPOINT11
7561  *  0b0..Disabled
7562  *  0b1..Enabled
7563  */
7564 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK)
7565 
7566 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U)
7567 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U)
7568 /*! TRACKING_EN_SETPOINT12 - TRACKING_EN_SETPOINT12
7569  *  0b0..Disabled
7570  *  0b1..Enabled
7571  */
7572 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK)
7573 
7574 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U)
7575 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U)
7576 /*! TRACKING_EN_SETPOINT13 - TRACKING_EN_SETPOINT13
7577  *  0b0..Disabled
7578  *  0b1..Enabled
7579  */
7580 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK)
7581 
7582 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U)
7583 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U)
7584 /*! TRACKING_EN_SETPOINT14 - TRACKING_EN_SETPOINT14
7585  *  0b0..Disabled
7586  *  0b1..Enabled
7587  */
7588 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK)
7589 
7590 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U)
7591 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U)
7592 /*! TRACKING_EN_SETPOINT15 - TRACKING_EN_SETPOINT15
7593  *  0b0..Disabled
7594  *  0b1..Enabled
7595  */
7596 #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK)
7597 /*! @} */
7598 
7599 /*! @name LDO_LPSR_DIG_BYPASS_EN_SP - LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER */
7600 /*! @{ */
7601 
7602 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U)
7603 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U)
7604 /*! BYPASS_EN_SETPOINT0 - BYPASS_EN_SETPOINT0
7605  *  0b0..Disabled
7606  *  0b1..Enabled
7607  */
7608 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK)
7609 
7610 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U)
7611 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U)
7612 /*! BYPASS_EN_SETPOINT1 - BYPASS_EN_SETPOINT1
7613  *  0b0..Disabled
7614  *  0b1..Enabled
7615  */
7616 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK)
7617 
7618 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U)
7619 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U)
7620 /*! BYPASS_EN_SETPOINT2 - BYPASS_EN_SETPOINT2
7621  *  0b0..Disabled
7622  *  0b1..Enabled
7623  */
7624 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK)
7625 
7626 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U)
7627 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U)
7628 /*! BYPASS_EN_SETPOINT3 - BYPASS_EN_SETPOINT3
7629  *  0b0..Disabled
7630  *  0b1..Enabled
7631  */
7632 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK)
7633 
7634 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U)
7635 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U)
7636 /*! BYPASS_EN_SETPOINT4 - BYPASS_EN_SETPOINT4
7637  *  0b0..Disabled
7638  *  0b1..Enabled
7639  */
7640 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK)
7641 
7642 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U)
7643 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U)
7644 /*! BYPASS_EN_SETPOINT5 - BYPASS_EN_SETPOINT5
7645  *  0b0..Disabled
7646  *  0b1..Enabled
7647  */
7648 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK)
7649 
7650 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U)
7651 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U)
7652 /*! BYPASS_EN_SETPOINT6 - BYPASS_EN_SETPOINT6
7653  *  0b0..Disabled
7654  *  0b1..Enabled
7655  */
7656 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK)
7657 
7658 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U)
7659 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U)
7660 /*! BYPASS_EN_SETPOINT7 - BYPASS_EN_SETPOINT7
7661  *  0b0..Disabled
7662  *  0b1..Enabled
7663  */
7664 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK)
7665 
7666 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U)
7667 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U)
7668 /*! BYPASS_EN_SETPOINT8 - BYPASS_EN_SETPOINT8
7669  *  0b0..Disabled
7670  *  0b1..Enabled
7671  */
7672 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK)
7673 
7674 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U)
7675 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U)
7676 /*! BYPASS_EN_SETPOINT9 - BYPASS_EN_SETPOINT9
7677  *  0b0..Disabled
7678  *  0b1..Enabled
7679  */
7680 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK)
7681 
7682 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U)
7683 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U)
7684 /*! BYPASS_EN_SETPOINT10 - BYPASS_EN_SETPOINT10
7685  *  0b0..Disabled
7686  *  0b1..Enabled
7687  */
7688 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK)
7689 
7690 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U)
7691 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U)
7692 /*! BYPASS_EN_SETPOINT11 - BYPASS_EN_SETPOINT11
7693  *  0b0..Disabled
7694  *  0b1..Enabled
7695  */
7696 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK)
7697 
7698 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U)
7699 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U)
7700 /*! BYPASS_EN_SETPOINT12 - BYPASS_EN_SETPOINT12
7701  *  0b0..Disabled
7702  *  0b1..Enabled
7703  */
7704 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK)
7705 
7706 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U)
7707 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U)
7708 /*! BYPASS_EN_SETPOINT13 - BYPASS_EN_SETPOINT13
7709  *  0b0..Disabled
7710  *  0b1..Enabled
7711  */
7712 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK)
7713 
7714 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U)
7715 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U)
7716 /*! BYPASS_EN_SETPOINT14 - BYPASS_EN_SETPOINT14
7717  *  0b0..Disabled
7718  *  0b1..Enabled
7719  */
7720 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK)
7721 
7722 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U)
7723 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U)
7724 /*! BYPASS_EN_SETPOINT15 - BYPASS_EN_SETPOINT15
7725  *  0b0..Disabled
7726  *  0b1..Enabled
7727  */
7728 #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK)
7729 /*! @} */
7730 
7731 /*! @name LDO_LPSR_DIG_STBY_EN_SP - LDO_LPSR_DIG_STBY_EN_SP_REGISTER */
7732 /*! @{ */
7733 
7734 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
7735 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
7736 /*! STBY_EN_SETPOINT0 - STBY_EN_SETPOINT0
7737  *  0b0..Disabled
7738  *  0b1..Enabled
7739  */
7740 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
7741 
7742 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
7743 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
7744 /*! STBY_EN_SETPOINT1 - STBY_EN_SETPOINT1
7745  *  0b0..Disabled
7746  *  0b1..Enabled
7747  */
7748 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
7749 
7750 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
7751 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
7752 /*! STBY_EN_SETPOINT2 - STBY_EN_SETPOINT2
7753  *  0b0..Disabled
7754  *  0b1..Enabled
7755  */
7756 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
7757 
7758 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
7759 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
7760 /*! STBY_EN_SETPOINT3 - STBY_EN_SETPOINT3
7761  *  0b0..Disabled
7762  *  0b1..Enabled
7763  */
7764 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
7765 
7766 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
7767 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
7768 /*! STBY_EN_SETPOINT4 - STBY_EN_SETPOINT4
7769  *  0b0..Disabled
7770  *  0b1..Enabled
7771  */
7772 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
7773 
7774 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
7775 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
7776 /*! STBY_EN_SETPOINT5 - STBY_EN_SETPOINT5
7777  *  0b0..Disabled
7778  *  0b1..Enabled
7779  */
7780 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
7781 
7782 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
7783 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
7784 /*! STBY_EN_SETPOINT6 - STBY_EN_SETPOINT6
7785  *  0b0..Disabled
7786  *  0b1..Enabled
7787  */
7788 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
7789 
7790 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
7791 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
7792 /*! STBY_EN_SETPOINT7 - STBY_EN_SETPOINT7
7793  *  0b0..Disabled
7794  *  0b1..Enabled
7795  */
7796 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
7797 
7798 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
7799 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
7800 /*! STBY_EN_SETPOINT8 - STBY_EN_SETPOINT8
7801  *  0b0..Disabled
7802  *  0b1..Enabled
7803  */
7804 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
7805 
7806 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
7807 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
7808 /*! STBY_EN_SETPOINT9 - STBY_EN_SETPOINT9
7809  *  0b0..Disabled
7810  *  0b1..Enabled
7811  */
7812 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
7813 
7814 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
7815 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
7816 /*! STBY_EN_SETPOINT10 - STBY_EN_SETPOINT10
7817  *  0b0..Disabled
7818  *  0b1..Enabled
7819  */
7820 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
7821 
7822 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
7823 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
7824 /*! STBY_EN_SETPOINT11 - STBY_EN_SETPOINT11
7825  *  0b0..Disabled
7826  *  0b1..Enabled
7827  */
7828 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
7829 
7830 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
7831 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
7832 /*! STBY_EN_SETPOINT12 - STBY_EN_SETPOINT12
7833  *  0b0..Disabled
7834  *  0b1..Enabled
7835  */
7836 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
7837 
7838 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
7839 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
7840 /*! STBY_EN_SETPOINT13 - STBY_EN_SETPOINT13
7841  *  0b0..Disabled
7842  *  0b1..Enabled
7843  */
7844 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
7845 
7846 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
7847 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
7848 /*! STBY_EN_SETPOINT14 - STBY_EN_SETPOINT14
7849  *  0b0..Disabled
7850  *  0b1..Enabled
7851  */
7852 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
7853 
7854 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
7855 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
7856 /*! STBY_EN_SETPOINT15 - STBY_EN_SETPOINT15
7857  *  0b0..Disabled
7858  *  0b1..Enabled
7859  */
7860 #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
7861 /*! @} */
7862 
7863 /*! @name BANDGAP_ENABLE_SP - BANDGAP_ENABLE_SP_REGISTER */
7864 /*! @{ */
7865 
7866 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
7867 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
7868 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
7869  *  0b0..ON
7870  *  0b1..OFF
7871  */
7872 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
7873 
7874 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
7875 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
7876 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
7877  *  0b0..ON
7878  *  0b1..OFF
7879  */
7880 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
7881 
7882 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
7883 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
7884 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
7885  *  0b0..ON
7886  *  0b1..OFF
7887  */
7888 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
7889 
7890 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
7891 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
7892 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
7893  *  0b0..ON
7894  *  0b1..OFF
7895  */
7896 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
7897 
7898 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
7899 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
7900 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
7901  *  0b0..ON
7902  *  0b1..OFF
7903  */
7904 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
7905 
7906 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
7907 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
7908 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
7909  *  0b0..ON
7910  *  0b1..OFF
7911  */
7912 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
7913 
7914 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
7915 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
7916 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT5
7917  *  0b0..ON
7918  *  0b1..OFF
7919  */
7920 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
7921 
7922 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
7923 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
7924 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
7925  *  0b0..ON
7926  *  0b1..OFF
7927  */
7928 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
7929 
7930 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
7931 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
7932 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
7933  *  0b0..ON
7934  *  0b1..OFF
7935  */
7936 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
7937 
7938 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
7939 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
7940 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
7941  *  0b0..ON
7942  *  0b1..OFF
7943  */
7944 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
7945 
7946 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
7947 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
7948 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
7949  *  0b0..ON
7950  *  0b1..OFF
7951  */
7952 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
7953 
7954 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
7955 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
7956 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
7957  *  0b0..ON
7958  *  0b1..OFF
7959  */
7960 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
7961 
7962 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
7963 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
7964 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
7965  *  0b0..ON
7966  *  0b1..OFF
7967  */
7968 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
7969 
7970 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
7971 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
7972 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
7973  *  0b0..ON
7974  *  0b1..OFF
7975  */
7976 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
7977 
7978 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
7979 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
7980 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
7981  *  0b0..ON
7982  *  0b1..OFF
7983  */
7984 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
7985 
7986 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
7987 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
7988 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
7989  *  0b0..ON
7990  *  0b1..OFF
7991  */
7992 #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
7993 /*! @} */
7994 
7995 /*! @name FBB_M7_ENABLE_SP - FBB_M7_ENABLE_SP_REGISTER */
7996 /*! @{ */
7997 
7998 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
7999 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
8000 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
8001  *  0b0..ON
8002  *  0b1..OFF
8003  */
8004 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
8005 
8006 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
8007 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
8008 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
8009  *  0b0..ON
8010  *  0b1..OFF
8011  */
8012 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
8013 
8014 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
8015 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
8016 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
8017  *  0b0..ON
8018  *  0b1..OFF
8019  */
8020 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
8021 
8022 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
8023 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
8024 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
8025  *  0b0..ON
8026  *  0b1..OFF
8027  */
8028 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
8029 
8030 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
8031 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
8032 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
8033  *  0b0..ON
8034  *  0b1..OFF
8035  */
8036 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
8037 
8038 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
8039 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
8040 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
8041  *  0b0..ON
8042  *  0b1..OFF
8043  */
8044 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
8045 
8046 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
8047 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
8048 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
8049  *  0b0..ON
8050  *  0b1..OFF
8051  */
8052 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
8053 
8054 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
8055 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
8056 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
8057  *  0b0..ON
8058  *  0b1..OFF
8059  */
8060 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
8061 
8062 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
8063 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
8064 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
8065  *  0b0..ON
8066  *  0b1..OFF
8067  */
8068 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
8069 
8070 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
8071 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
8072 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
8073  *  0b0..ON
8074  *  0b1..OFF
8075  */
8076 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
8077 
8078 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
8079 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
8080 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
8081  *  0b0..ON
8082  *  0b1..OFF
8083  */
8084 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
8085 
8086 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
8087 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
8088 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
8089  *  0b0..ON
8090  *  0b1..OFF
8091  */
8092 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
8093 
8094 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
8095 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
8096 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
8097  *  0b0..ON
8098  *  0b1..OFF
8099  */
8100 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
8101 
8102 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
8103 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
8104 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
8105  *  0b0..ON
8106  *  0b1..OFF
8107  */
8108 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
8109 
8110 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
8111 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
8112 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
8113  *  0b0..ON
8114  *  0b1..OFF
8115  */
8116 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
8117 
8118 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
8119 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
8120 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
8121  *  0b0..ON
8122  *  0b1..OFF
8123  */
8124 #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
8125 /*! @} */
8126 
8127 /*! @name RBB_SOC_ENABLE_SP - RBB_SOC_ENABLE_SP_REGISTER */
8128 /*! @{ */
8129 
8130 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
8131 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
8132 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
8133  *  0b0..ON
8134  *  0b1..OFF
8135  */
8136 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
8137 
8138 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
8139 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
8140 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
8141  *  0b0..ON
8142  *  0b1..OFF
8143  */
8144 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
8145 
8146 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
8147 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
8148 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
8149  *  0b0..ON
8150  *  0b1..OFF
8151  */
8152 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
8153 
8154 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
8155 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
8156 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
8157  *  0b0..ON
8158  *  0b1..OFF
8159  */
8160 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
8161 
8162 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
8163 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
8164 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
8165  *  0b0..ON
8166  *  0b1..OFF
8167  */
8168 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
8169 
8170 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
8171 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
8172 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
8173  *  0b0..ON
8174  *  0b1..OFF
8175  */
8176 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
8177 
8178 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
8179 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
8180 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
8181  *  0b0..ON
8182  *  0b1..OFF
8183  */
8184 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
8185 
8186 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
8187 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
8188 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
8189  *  0b0..ON
8190  *  0b1..OFF
8191  */
8192 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
8193 
8194 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
8195 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
8196 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
8197  *  0b0..ON
8198  *  0b1..OFF
8199  */
8200 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
8201 
8202 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
8203 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
8204 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
8205  *  0b0..ON
8206  *  0b1..OFF
8207  */
8208 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
8209 
8210 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
8211 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
8212 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
8213  *  0b0..ON
8214  *  0b1..OFF
8215  */
8216 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
8217 
8218 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
8219 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
8220 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
8221  *  0b0..ON
8222  *  0b1..OFF
8223  */
8224 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
8225 
8226 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
8227 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
8228 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
8229  *  0b0..ON
8230  *  0b1..OFF
8231  */
8232 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
8233 
8234 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
8235 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
8236 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
8237  *  0b0..ON
8238  *  0b1..OFF
8239  */
8240 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
8241 
8242 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
8243 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
8244 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
8245  *  0b0..ON
8246  *  0b1..OFF
8247  */
8248 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
8249 
8250 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
8251 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
8252 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
8253  *  0b0..ON
8254  *  0b1..OFF
8255  */
8256 #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
8257 /*! @} */
8258 
8259 /*! @name RBB_LPSR_ENABLE_SP - RBB_LPSR_ENABLE_SP_REGISTER */
8260 /*! @{ */
8261 
8262 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
8263 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
8264 /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
8265  *  0b0..ON
8266  *  0b1..OFF
8267  */
8268 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
8269 
8270 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
8271 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
8272 /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
8273  *  0b0..ON
8274  *  0b1..OFF
8275  */
8276 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
8277 
8278 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
8279 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
8280 /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
8281  *  0b0..ON
8282  *  0b1..OFF
8283  */
8284 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
8285 
8286 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
8287 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
8288 /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
8289  *  0b0..ON
8290  *  0b1..OFF
8291  */
8292 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
8293 
8294 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
8295 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
8296 /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
8297  *  0b0..ON
8298  *  0b1..OFF
8299  */
8300 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
8301 
8302 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
8303 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
8304 /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
8305  *  0b0..ON
8306  *  0b1..OFF
8307  */
8308 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
8309 
8310 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
8311 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
8312 /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
8313  *  0b0..ON
8314  *  0b1..OFF
8315  */
8316 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
8317 
8318 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
8319 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
8320 /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
8321  *  0b0..ON
8322  *  0b1..OFF
8323  */
8324 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
8325 
8326 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
8327 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
8328 /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
8329  *  0b0..ON
8330  *  0b1..OFF
8331  */
8332 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
8333 
8334 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
8335 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
8336 /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
8337  *  0b0..ON
8338  *  0b1..OFF
8339  */
8340 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
8341 
8342 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
8343 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
8344 /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
8345  *  0b0..ON
8346  *  0b1..OFF
8347  */
8348 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
8349 
8350 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
8351 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
8352 /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
8353  *  0b0..ON
8354  *  0b1..OFF
8355  */
8356 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
8357 
8358 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
8359 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
8360 /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
8361  *  0b0..ON
8362  *  0b1..OFF
8363  */
8364 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
8365 
8366 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
8367 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
8368 /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
8369  *  0b0..ON
8370  *  0b1..OFF
8371  */
8372 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
8373 
8374 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
8375 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
8376 /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
8377  *  0b0..ON
8378  *  0b1..OFF
8379  */
8380 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
8381 
8382 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
8383 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
8384 /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
8385  *  0b0..ON
8386  *  0b1..OFF
8387  */
8388 #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
8389 /*! @} */
8390 
8391 /*! @name BANDGAP_STBY_EN_SP - BANDGAP_STBY_EN_SP_REGISTER */
8392 /*! @{ */
8393 
8394 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8395 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8396 /*! STBY_EN_SETPOINT0 - STBY_EN_SETPOINT
8397  *  0b0..Disabled
8398  *  0b1..Enabled
8399  */
8400 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8401 
8402 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8403 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8404 /*! STBY_EN_SETPOINT1 - STBY_EN_SETPOINT
8405  *  0b0..Disabled
8406  *  0b1..Enabled
8407  */
8408 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8409 
8410 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8411 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8412 /*! STBY_EN_SETPOINT2 - STBY_EN_SETPOINT
8413  *  0b0..Disabled
8414  *  0b1..Enabled
8415  */
8416 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8417 
8418 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8419 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8420 /*! STBY_EN_SETPOINT3 - STBY_EN_SETPOINT
8421  *  0b0..Disabled
8422  *  0b1..Enabled
8423  */
8424 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8425 
8426 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8427 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8428 /*! STBY_EN_SETPOINT4 - STBY_EN_SETPOINT
8429  *  0b0..Disabled
8430  *  0b1..Enabled
8431  */
8432 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8433 
8434 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8435 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8436 /*! STBY_EN_SETPOINT5 - STBY_EN_SETPOINT
8437  *  0b0..Disabled
8438  *  0b1..Enabled
8439  */
8440 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8441 
8442 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8443 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8444 /*! STBY_EN_SETPOINT6 - STBY_EN_SETPOINT
8445  *  0b0..Disabled
8446  *  0b1..Enabled
8447  */
8448 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8449 
8450 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8451 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8452 /*! STBY_EN_SETPOINT7 - STBY_EN_SETPOINT
8453  *  0b0..Disabled
8454  *  0b1..Enabled
8455  */
8456 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8457 
8458 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8459 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8460 /*! STBY_EN_SETPOINT8 - STBY_EN_SETPOINT
8461  *  0b0..Disabled
8462  *  0b1..Enabled
8463  */
8464 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8465 
8466 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8467 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8468 /*! STBY_EN_SETPOINT9 - STBY_EN_SETPOINT
8469  *  0b0..Disabled
8470  *  0b1..Enabled
8471  */
8472 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
8473 
8474 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
8475 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
8476 /*! STBY_EN_SETPOINT10 - STBY_EN_SETPOINT
8477  *  0b0..Disabled
8478  *  0b1..Enabled
8479  */
8480 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
8481 
8482 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
8483 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
8484 /*! STBY_EN_SETPOINT11 - STBY_EN_SETPOINT
8485  *  0b0..Disabled
8486  *  0b1..Enabled
8487  */
8488 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
8489 
8490 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
8491 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
8492 /*! STBY_EN_SETPOINT12 - STBY_EN_SETPOINT
8493  *  0b0..Disabled
8494  *  0b1..Enabled
8495  */
8496 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
8497 
8498 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
8499 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
8500 /*! STBY_EN_SETPOINT13 - STBY_EN_SETPOINT
8501  *  0b0..Disabled
8502  *  0b1..Enabled
8503  */
8504 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
8505 
8506 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
8507 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
8508 /*! STBY_EN_SETPOINT14 - STBY_EN_SETPOINT
8509  *  0b0..Disabled
8510  *  0b1..Enabled
8511  */
8512 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
8513 
8514 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
8515 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
8516 /*! STBY_EN_SETPOINT15 - STBY_EN_SETPOINT
8517  *  0b0..Disabled
8518  *  0b1..Enabled
8519  */
8520 #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
8521 /*! @} */
8522 
8523 /*! @name PLL_LDO_STBY_EN_SP - PLL_LDO_STBY_EN_SP_REGISTER */
8524 /*! @{ */
8525 
8526 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8527 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8528 /*! STBY_EN_SETPOINT0 - Standby mode
8529  *  0b0..Disabled
8530  *  0b1..Enabled
8531  */
8532 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8533 
8534 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8535 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8536 /*! STBY_EN_SETPOINT1 - Standby mode
8537  *  0b0..Disabled
8538  *  0b1..Enabled
8539  */
8540 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8541 
8542 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8543 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8544 /*! STBY_EN_SETPOINT2 - Standby mode
8545  *  0b0..Disabled
8546  *  0b1..Enabled
8547  */
8548 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8549 
8550 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8551 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8552 /*! STBY_EN_SETPOINT3 - Standby mode
8553  *  0b0..Disabled
8554  *  0b1..Enabled
8555  */
8556 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8557 
8558 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8559 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8560 /*! STBY_EN_SETPOINT4 - Standby mode
8561  *  0b0..Disabled
8562  *  0b1..Enabled
8563  */
8564 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8565 
8566 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8567 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8568 /*! STBY_EN_SETPOINT5 - Standby mode
8569  *  0b0..Disabled
8570  *  0b1..Enabled
8571  */
8572 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8573 
8574 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8575 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8576 /*! STBY_EN_SETPOINT6 - Standby mode
8577  *  0b0..Disabled
8578  *  0b1..Enabled
8579  */
8580 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8581 
8582 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8583 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8584 /*! STBY_EN_SETPOINT7 - Standby mode
8585  *  0b0..Disabled
8586  *  0b1..Enabled
8587  */
8588 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8589 
8590 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8591 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8592 /*! STBY_EN_SETPOINT8 - Standby mode
8593  *  0b0..Disabled
8594  *  0b1..Enabled
8595  */
8596 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8597 
8598 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8599 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8600 /*! STBY_EN_SETPOINT9 - Standby mode
8601  *  0b0..Disabled
8602  *  0b1..Enabled
8603  */
8604 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
8605 
8606 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
8607 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
8608 /*! STBY_EN_SETPOINT10 - Standby mode
8609  *  0b0..Disabled
8610  *  0b1..Enabled
8611  */
8612 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
8613 
8614 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
8615 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
8616 /*! STBY_EN_SETPOINT11 - Standby mode
8617  *  0b0..Disabled
8618  *  0b1..Enabled
8619  */
8620 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
8621 
8622 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
8623 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
8624 /*! STBY_EN_SETPOINT12 - Standby mode
8625  *  0b0..Disabled
8626  *  0b1..Enabled
8627  */
8628 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
8629 
8630 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
8631 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
8632 /*! STBY_EN_SETPOINT13 - Standby mode
8633  *  0b0..Disabled
8634  *  0b1..Enabled
8635  */
8636 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
8637 
8638 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
8639 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
8640 /*! STBY_EN_SETPOINT14 - Standby mode
8641  *  0b0..Disabled
8642  *  0b1..Enabled
8643  */
8644 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
8645 
8646 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
8647 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
8648 /*! STBY_EN_SETPOINT15 - Standby mode
8649  *  0b0..Disabled
8650  *  0b1..Enabled
8651  */
8652 #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
8653 /*! @} */
8654 
8655 /*! @name FBB_M7_STBY_EN_SP - FBB_M7_STBY_EN_SP_REGISTER */
8656 /*! @{ */
8657 
8658 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8659 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8660 /*! STBY_EN_SETPOINT0 - Standby mode
8661  *  0b0..Disabled
8662  *  0b1..Enabled
8663  */
8664 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8665 
8666 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8667 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8668 /*! STBY_EN_SETPOINT1 - Standby mode
8669  *  0b0..Disabled
8670  *  0b1..Enabled
8671  */
8672 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8673 
8674 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8675 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8676 /*! STBY_EN_SETPOINT2 - Standby mode
8677  *  0b0..Disabled
8678  *  0b1..Enabled
8679  */
8680 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8681 
8682 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8683 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8684 /*! STBY_EN_SETPOINT3 - Standby mode
8685  *  0b0..Disabled
8686  *  0b1..Enabled
8687  */
8688 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8689 
8690 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8691 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8692 /*! STBY_EN_SETPOINT4 - Standby mode
8693  *  0b0..Disabled
8694  *  0b1..Enabled
8695  */
8696 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8697 
8698 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8699 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8700 /*! STBY_EN_SETPOINT5 - Standby mode
8701  *  0b0..Disabled
8702  *  0b1..Enabled
8703  */
8704 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8705 
8706 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8707 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8708 /*! STBY_EN_SETPOINT6 - Standby mode
8709  *  0b0..Disabled
8710  *  0b1..Enabled
8711  */
8712 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8713 
8714 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8715 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8716 /*! STBY_EN_SETPOINT7 - Standby mode
8717  *  0b0..Disabled
8718  *  0b1..Enabled
8719  */
8720 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8721 
8722 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8723 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8724 /*! STBY_EN_SETPOINT8 - Standby mode
8725  *  0b0..Disabled
8726  *  0b1..Enabled
8727  */
8728 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8729 
8730 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8731 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8732 /*! STBY_EN_SETPOINT9 - Standby mode
8733  *  0b0..Disabled
8734  *  0b1..Enabled
8735  */
8736 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
8737 
8738 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
8739 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
8740 /*! STBY_EN_SETPOINT10 - Standby mode
8741  *  0b0..Disabled
8742  *  0b1..Enabled
8743  */
8744 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
8745 
8746 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
8747 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
8748 /*! STBY_EN_SETPOINT11 - Standby mode
8749  *  0b0..Disabled
8750  *  0b1..Enabled
8751  */
8752 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
8753 
8754 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
8755 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
8756 /*! STBY_EN_SETPOINT12 - Standby mode
8757  *  0b0..Disabled
8758  *  0b1..Enabled
8759  */
8760 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
8761 
8762 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
8763 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
8764 /*! STBY_EN_SETPOINT13 - Standby mode
8765  *  0b0..Disabled
8766  *  0b1..Enabled
8767  */
8768 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
8769 
8770 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
8771 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
8772 /*! STBY_EN_SETPOINT14 - Standby mode
8773  *  0b0..Disabled
8774  *  0b1..Enabled
8775  */
8776 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
8777 
8778 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
8779 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
8780 /*! STBY_EN_SETPOINT15 - Standby mode
8781  *  0b0..Disabled
8782  *  0b1..Enabled
8783  */
8784 #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
8785 /*! @} */
8786 
8787 /*! @name RBB_SOC_STBY_EN_SP - RBB_SOC_STBY_EN_SP_REGISTER */
8788 /*! @{ */
8789 
8790 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8791 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8792 /*! STBY_EN_SETPOINT0 - Standby mode
8793  *  0b0..Disabled
8794  *  0b1..Enabled
8795  */
8796 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8797 
8798 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8799 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8800 /*! STBY_EN_SETPOINT1 - Standby mode
8801  *  0b0..Disabled
8802  *  0b1..Enabled
8803  */
8804 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8805 
8806 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8807 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8808 /*! STBY_EN_SETPOINT2 - Standby mode
8809  *  0b0..Disabled
8810  *  0b1..Enabled
8811  */
8812 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8813 
8814 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8815 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8816 /*! STBY_EN_SETPOINT3 - Standby mode
8817  *  0b0..Disabled
8818  *  0b1..Enabled
8819  */
8820 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8821 
8822 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8823 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8824 /*! STBY_EN_SETPOINT4 - Standby mode
8825  *  0b0..Disabled
8826  *  0b1..Enabled
8827  */
8828 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8829 
8830 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8831 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8832 /*! STBY_EN_SETPOINT5 - Standby mode
8833  *  0b0..Disabled
8834  *  0b1..Enabled
8835  */
8836 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8837 
8838 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8839 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8840 /*! STBY_EN_SETPOINT6 - Standby mode
8841  *  0b0..Disabled
8842  *  0b1..Enabled
8843  */
8844 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8845 
8846 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8847 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8848 /*! STBY_EN_SETPOINT7 - Standby mode
8849  *  0b0..Disabled
8850  *  0b1..Enabled
8851  */
8852 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8853 
8854 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8855 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8856 /*! STBY_EN_SETPOINT8 - Standby mode
8857  *  0b0..Disabled
8858  *  0b1..Enabled
8859  */
8860 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8861 
8862 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8863 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8864 /*! STBY_EN_SETPOINT9 - Standby mode
8865  *  0b0..Disabled
8866  *  0b1..Enabled
8867  */
8868 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
8869 
8870 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
8871 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
8872 /*! STBY_EN_SETPOINT10 - Standby mode
8873  *  0b0..Disabled
8874  *  0b1..Enabled
8875  */
8876 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
8877 
8878 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
8879 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
8880 /*! STBY_EN_SETPOINT11 - Standby mode
8881  *  0b0..Disabled
8882  *  0b1..Enabled
8883  */
8884 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
8885 
8886 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
8887 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
8888 /*! STBY_EN_SETPOINT12 - Standby mode
8889  *  0b0..Disabled
8890  *  0b1..Enabled
8891  */
8892 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
8893 
8894 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
8895 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
8896 /*! STBY_EN_SETPOINT13 - Standby mode
8897  *  0b0..Disabled
8898  *  0b1..Enabled
8899  */
8900 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
8901 
8902 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
8903 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
8904 /*! STBY_EN_SETPOINT14 - Standby mode
8905  *  0b0..Disabled
8906  *  0b1..Enabled
8907  */
8908 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
8909 
8910 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
8911 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
8912 /*! STBY_EN_SETPOINT15 - Standby mode
8913  *  0b0..Disabled
8914  *  0b1..Enabled
8915  */
8916 #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
8917 /*! @} */
8918 
8919 /*! @name RBB_LPSR_STBY_EN_SP - RBB_LPSR_STBY_EN_SP_REGISTER */
8920 /*! @{ */
8921 
8922 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
8923 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
8924 /*! STBY_EN_SETPOINT0 - Standby mode
8925  *  0b0..Disabled
8926  *  0b1..Enabled
8927  */
8928 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
8929 
8930 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
8931 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
8932 /*! STBY_EN_SETPOINT1 - Standby mode
8933  *  0b0..Disabled
8934  *  0b1..Enabled
8935  */
8936 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
8937 
8938 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
8939 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
8940 /*! STBY_EN_SETPOINT2 - Standby mode
8941  *  0b0..Disabled
8942  *  0b1..Enabled
8943  */
8944 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
8945 
8946 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
8947 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
8948 /*! STBY_EN_SETPOINT3 - Standby mode
8949  *  0b0..Disabled
8950  *  0b1..Enabled
8951  */
8952 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
8953 
8954 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
8955 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
8956 /*! STBY_EN_SETPOINT4 - Standby mode
8957  *  0b0..Disabled
8958  *  0b1..Enabled
8959  */
8960 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
8961 
8962 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
8963 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
8964 /*! STBY_EN_SETPOINT5 - Standby mode
8965  *  0b0..Disabled
8966  *  0b1..Enabled
8967  */
8968 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
8969 
8970 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
8971 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
8972 /*! STBY_EN_SETPOINT6 - Standby mode
8973  *  0b0..Disabled
8974  *  0b1..Enabled
8975  */
8976 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
8977 
8978 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
8979 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
8980 /*! STBY_EN_SETPOINT7 - Standby mode
8981  *  0b0..Disabled
8982  *  0b1..Enabled
8983  */
8984 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
8985 
8986 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
8987 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
8988 /*! STBY_EN_SETPOINT8 - Standby mode
8989  *  0b0..Disabled
8990  *  0b1..Enabled
8991  */
8992 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
8993 
8994 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
8995 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
8996 /*! STBY_EN_SETPOINT9 - Standby mode
8997  *  0b0..Disabled
8998  *  0b1..Enabled
8999  */
9000 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
9001 
9002 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
9003 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
9004 /*! STBY_EN_SETPOINT10 - Standby mode
9005  *  0b0..Disabled
9006  *  0b1..Enabled
9007  */
9008 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
9009 
9010 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
9011 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
9012 /*! STBY_EN_SETPOINT11 - Standby mode
9013  *  0b0..Disabled
9014  *  0b1..Enabled
9015  */
9016 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
9017 
9018 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
9019 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
9020 /*! STBY_EN_SETPOINT12 - Standby mode
9021  *  0b0..Disabled
9022  *  0b1..Enabled
9023  */
9024 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
9025 
9026 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
9027 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
9028 /*! STBY_EN_SETPOINT13 - Standby mode
9029  *  0b0..Disabled
9030  *  0b1..Enabled
9031  */
9032 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
9033 
9034 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
9035 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
9036 /*! STBY_EN_SETPOINT14 - Standby mode
9037  *  0b0..Disabled
9038  *  0b1..Enabled
9039  */
9040 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
9041 
9042 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
9043 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
9044 /*! STBY_EN_SETPOINT15 - Standby mode
9045  *  0b0..Disabled
9046  *  0b1..Enabled
9047  */
9048 #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
9049 /*! @} */
9050 
9051 /*! @name FBB_M7_CONFIGURE - FBB_M7_CONFIGURE_REGISTER */
9052 /*! @{ */
9053 
9054 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_MASK (0xFU)
9055 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_SHIFT (0U)
9056 /*! WB_CFG_PW - wb_cfg_pw */
9057 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_MASK)
9058 
9059 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_MASK (0xF0U)
9060 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_SHIFT (4U)
9061 /*! WB_CFG_NW - wb_cfg_nw */
9062 #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_MASK)
9063 
9064 #define ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U)
9065 #define ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U)
9066 /*! OSCILLATOR_BITS - oscillator_bits */
9067 #define ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_MASK)
9068 
9069 #define ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U)
9070 #define ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U)
9071 /*! REGULATOR_STRENGTH - regulator_strength */
9072 #define ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_MASK)
9073 /*! @} */
9074 
9075 /*! @name RBB_LPSR_CONFIGURE - RBB_LPSR_CONFIGURE_REGISTER */
9076 /*! @{ */
9077 
9078 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK (0xFU)
9079 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT (0U)
9080 /*! WB_CFG_PW - wb_cfg_pw */
9081 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK)
9082 
9083 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK (0xF0U)
9084 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT (4U)
9085 /*! WB_CFG_NW - wb_cfg_nw */
9086 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK)
9087 
9088 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U)
9089 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U)
9090 /*! OSCILLATOR_BITS - oscillator_bits */
9091 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK)
9092 
9093 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U)
9094 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U)
9095 /*! REGULATOR_STRENGTH - regulator_strength */
9096 #define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK)
9097 /*! @} */
9098 
9099 /*! @name RBB_SOC_CONFIGURE - RBB_SOC_CONFIGURE_REGISTER */
9100 /*! @{ */
9101 
9102 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK (0xFU)
9103 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT (0U)
9104 /*! WB_CFG_PW - wb_cfg_pw */
9105 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK)
9106 
9107 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK (0xF0U)
9108 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT (4U)
9109 /*! WB_CFG_NW - wb_cfg_nw */
9110 #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK)
9111 
9112 #define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U)
9113 #define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U)
9114 /*! OSCILLATOR_BITS - oscillator_bits */
9115 #define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK)
9116 
9117 #define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U)
9118 #define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U)
9119 /*! REGULATOR_STRENGTH - regulator_strength */
9120 #define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK)
9121 /*! @} */
9122 
9123 /*! @name REFTOP_OTP_TRIM_VALUE - REFTOP_OTP_TRIM_VALUE_REGISTER */
9124 /*! @{ */
9125 
9126 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK (0x7U)
9127 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT (0U)
9128 /*! REFTOP_IBZTCADJ - REFTOP_IBZTCADJ */
9129 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK)
9130 
9131 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK (0x38U)
9132 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT (3U)
9133 /*! REFTOP_VBGADJ - REFTOP_VBGADJ */
9134 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK)
9135 
9136 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK (0x40U)
9137 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT (6U)
9138 /*! REFTOP_TRIM_EN - REFTOP_TRIM_EN */
9139 #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK)
9140 /*! @} */
9141 
9142 /*! @name LPSR_1P8_LDO_OTP_TRIM_VALUE - LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER */
9143 /*! @{ */
9144 
9145 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK (0x3U)
9146 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT (0U)
9147 /*! LPSR_LDO_1P8_TRIM - LPSR_LDO_1P8_TRIM */
9148 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT)) & ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK)
9149 
9150 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK (0x4U)
9151 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT (2U)
9152 /*! LPSR_LDO_1P8_TRIM_EN - LPSR_LDO_1P8_TRIM_EN */
9153 #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT)) & ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK)
9154 /*! @} */
9155 
9156 
9157 /*!
9158  * @}
9159  */ /* end of group ANADIG_PMU_Register_Masks */
9160 
9161 
9162 /* ANADIG_PMU - Peripheral instance base addresses */
9163 /** Peripheral ANADIG_PMU base address */
9164 #define ANADIG_PMU_BASE                          (0x40C84000u)
9165 /** Peripheral ANADIG_PMU base pointer */
9166 #define ANADIG_PMU                               ((ANADIG_PMU_Type *)ANADIG_PMU_BASE)
9167 /** Array initializer of ANADIG_PMU peripheral base addresses */
9168 #define ANADIG_PMU_BASE_ADDRS                    { ANADIG_PMU_BASE }
9169 /** Array initializer of ANADIG_PMU peripheral base pointers */
9170 #define ANADIG_PMU_BASE_PTRS                     { ANADIG_PMU }
9171 
9172 /*!
9173  * @}
9174  */ /* end of group ANADIG_PMU_Peripheral_Access_Layer */
9175 
9176 
9177 /* ----------------------------------------------------------------------------
9178    -- ANADIG_TEMPSENSOR Peripheral Access Layer
9179    ---------------------------------------------------------------------------- */
9180 
9181 /*!
9182  * @addtogroup ANADIG_TEMPSENSOR_Peripheral_Access_Layer ANADIG_TEMPSENSOR Peripheral Access Layer
9183  * @{
9184  */
9185 
9186 /** ANADIG_TEMPSENSOR - Register Layout Typedef */
9187 typedef struct {
9188        uint8_t RESERVED_0[1024];
9189   __IO uint32_t TEMPSENSOR;                        /**< Tempsensor Register, offset: 0x400 */
9190        uint8_t RESERVED_1[44];
9191   __I  uint32_t TEMPSNS_OTP_TRIM_VALUE;            /**< TEMPSNS_OTP_TRIM_VALUE_REGISTER, offset: 0x430 */
9192 } ANADIG_TEMPSENSOR_Type;
9193 
9194 /* ----------------------------------------------------------------------------
9195    -- ANADIG_TEMPSENSOR Register Masks
9196    ---------------------------------------------------------------------------- */
9197 
9198 /*!
9199  * @addtogroup ANADIG_TEMPSENSOR_Register_Masks ANADIG_TEMPSENSOR Register Masks
9200  * @{
9201  */
9202 
9203 /*! @name TEMPSENSOR - Tempsensor Register */
9204 /*! @{ */
9205 
9206 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK (0x8000U)
9207 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_SHIFT (15U)
9208 /*! TEMPSNS_AI_TOGGLE - AI toggle */
9209 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK)
9210 
9211 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_MASK (0x10000U)
9212 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_SHIFT (16U)
9213 /*! TEMPSNS_AI_BUSY - AI Busy monitor */
9214 #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_MASK)
9215 /*! @} */
9216 
9217 /*! @name TEMPSNS_OTP_TRIM_VALUE - TEMPSNS_OTP_TRIM_VALUE_REGISTER */
9218 /*! @{ */
9219 
9220 #define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK (0x3FFC00U)
9221 #define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT (10U)
9222 /*! TEMPSNS_TEMP_VAL - Temperature Value at 25C */
9223 #define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK)
9224 /*! @} */
9225 
9226 
9227 /*!
9228  * @}
9229  */ /* end of group ANADIG_TEMPSENSOR_Register_Masks */
9230 
9231 
9232 /* ANADIG_TEMPSENSOR - Peripheral instance base addresses */
9233 /** Peripheral ANADIG_TEMPSENSOR base address */
9234 #define ANADIG_TEMPSENSOR_BASE                   (0x40C84000u)
9235 /** Peripheral ANADIG_TEMPSENSOR base pointer */
9236 #define ANADIG_TEMPSENSOR                        ((ANADIG_TEMPSENSOR_Type *)ANADIG_TEMPSENSOR_BASE)
9237 /** Array initializer of ANADIG_TEMPSENSOR peripheral base addresses */
9238 #define ANADIG_TEMPSENSOR_BASE_ADDRS             { ANADIG_TEMPSENSOR_BASE }
9239 /** Array initializer of ANADIG_TEMPSENSOR peripheral base pointers */
9240 #define ANADIG_TEMPSENSOR_BASE_PTRS              { ANADIG_TEMPSENSOR }
9241 
9242 /*!
9243  * @}
9244  */ /* end of group ANADIG_TEMPSENSOR_Peripheral_Access_Layer */
9245 
9246 
9247 /* ----------------------------------------------------------------------------
9248    -- AOI Peripheral Access Layer
9249    ---------------------------------------------------------------------------- */
9250 
9251 /*!
9252  * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
9253  * @{
9254  */
9255 
9256 /** AOI - Register Layout Typedef */
9257 typedef struct {
9258   struct {                                         /* offset: 0x0, array step: 0x4 */
9259     __IO uint16_t BFCRT01;                           /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */
9260     __IO uint16_t BFCRT23;                           /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */
9261   } BFCRT[4];
9262 } AOI_Type;
9263 
9264 /* ----------------------------------------------------------------------------
9265    -- AOI Register Masks
9266    ---------------------------------------------------------------------------- */
9267 
9268 /*!
9269  * @addtogroup AOI_Register_Masks AOI Register Masks
9270  * @{
9271  */
9272 
9273 /*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */
9274 /*! @{ */
9275 
9276 #define AOI_BFCRT01_PT1_DC_MASK                  (0x3U)
9277 #define AOI_BFCRT01_PT1_DC_SHIFT                 (0U)
9278 /*! PT1_DC - Product term 1, D input configuration
9279  *  0b00..Force the D input in this product term to a logical zero
9280  *  0b01..Pass the D input in this product term
9281  *  0b10..Complement the D input in this product term
9282  *  0b11..Force the D input in this product term to a logical one
9283  */
9284 #define AOI_BFCRT01_PT1_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
9285 
9286 #define AOI_BFCRT01_PT1_CC_MASK                  (0xCU)
9287 #define AOI_BFCRT01_PT1_CC_SHIFT                 (2U)
9288 /*! PT1_CC - Product term 1, C input configuration
9289  *  0b00..Force the C input in this product term to a logical zero
9290  *  0b01..Pass the C input in this product term
9291  *  0b10..Complement the C input in this product term
9292  *  0b11..Force the C input in this product term to a logical one
9293  */
9294 #define AOI_BFCRT01_PT1_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
9295 
9296 #define AOI_BFCRT01_PT1_BC_MASK                  (0x30U)
9297 #define AOI_BFCRT01_PT1_BC_SHIFT                 (4U)
9298 /*! PT1_BC - Product term 1, B input configuration
9299  *  0b00..Force the B input in this product term to a logical zero
9300  *  0b01..Pass the B input in this product term
9301  *  0b10..Complement the B input in this product term
9302  *  0b11..Force the B input in this product term to a logical one
9303  */
9304 #define AOI_BFCRT01_PT1_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
9305 
9306 #define AOI_BFCRT01_PT1_AC_MASK                  (0xC0U)
9307 #define AOI_BFCRT01_PT1_AC_SHIFT                 (6U)
9308 /*! PT1_AC - Product term 1, A input configuration
9309  *  0b00..Force the A input in this product term to a logical zero
9310  *  0b01..Pass the A input in this product term
9311  *  0b10..Complement the A input in this product term
9312  *  0b11..Force the A input in this product term to a logical one
9313  */
9314 #define AOI_BFCRT01_PT1_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
9315 
9316 #define AOI_BFCRT01_PT0_DC_MASK                  (0x300U)
9317 #define AOI_BFCRT01_PT0_DC_SHIFT                 (8U)
9318 /*! PT0_DC - Product term 0, D input configuration
9319  *  0b00..Force the D input in this product term to a logical zero
9320  *  0b01..Pass the D input in this product term
9321  *  0b10..Complement the D input in this product term
9322  *  0b11..Force the D input in this product term to a logical one
9323  */
9324 #define AOI_BFCRT01_PT0_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
9325 
9326 #define AOI_BFCRT01_PT0_CC_MASK                  (0xC00U)
9327 #define AOI_BFCRT01_PT0_CC_SHIFT                 (10U)
9328 /*! PT0_CC - Product term 0, C input configuration
9329  *  0b00..Force the C input in this product term to a logical zero
9330  *  0b01..Pass the C input in this product term
9331  *  0b10..Complement the C input in this product term
9332  *  0b11..Force the C input in this product term to a logical one
9333  */
9334 #define AOI_BFCRT01_PT0_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
9335 
9336 #define AOI_BFCRT01_PT0_BC_MASK                  (0x3000U)
9337 #define AOI_BFCRT01_PT0_BC_SHIFT                 (12U)
9338 /*! PT0_BC - Product term 0, B input configuration
9339  *  0b00..Force the B input in this product term to a logical zero
9340  *  0b01..Pass the B input in this product term
9341  *  0b10..Complement the B input in this product term
9342  *  0b11..Force the B input in this product term to a logical one
9343  */
9344 #define AOI_BFCRT01_PT0_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
9345 
9346 #define AOI_BFCRT01_PT0_AC_MASK                  (0xC000U)
9347 #define AOI_BFCRT01_PT0_AC_SHIFT                 (14U)
9348 /*! PT0_AC - Product term 0, A input configuration
9349  *  0b00..Force the A input in this product term to a logical zero
9350  *  0b01..Pass the A input in this product term
9351  *  0b10..Complement the A input in this product term
9352  *  0b11..Force the A input in this product term to a logical one
9353  */
9354 #define AOI_BFCRT01_PT0_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
9355 /*! @} */
9356 
9357 /* The count of AOI_BFCRT01 */
9358 #define AOI_BFCRT01_COUNT                        (4U)
9359 
9360 /*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */
9361 /*! @{ */
9362 
9363 #define AOI_BFCRT23_PT3_DC_MASK                  (0x3U)
9364 #define AOI_BFCRT23_PT3_DC_SHIFT                 (0U)
9365 /*! PT3_DC - Product term 3, D input configuration
9366  *  0b00..Force the D input in this product term to a logical zero
9367  *  0b01..Pass the D input in this product term
9368  *  0b10..Complement the D input in this product term
9369  *  0b11..Force the D input in this product term to a logical one
9370  */
9371 #define AOI_BFCRT23_PT3_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
9372 
9373 #define AOI_BFCRT23_PT3_CC_MASK                  (0xCU)
9374 #define AOI_BFCRT23_PT3_CC_SHIFT                 (2U)
9375 /*! PT3_CC - Product term 3, C input configuration
9376  *  0b00..Force the C input in this product term to a logical zero
9377  *  0b01..Pass the C input in this product term
9378  *  0b10..Complement the C input in this product term
9379  *  0b11..Force the C input in this product term to a logical one
9380  */
9381 #define AOI_BFCRT23_PT3_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
9382 
9383 #define AOI_BFCRT23_PT3_BC_MASK                  (0x30U)
9384 #define AOI_BFCRT23_PT3_BC_SHIFT                 (4U)
9385 /*! PT3_BC - Product term 3, B input configuration
9386  *  0b00..Force the B input in this product term to a logical zero
9387  *  0b01..Pass the B input in this product term
9388  *  0b10..Complement the B input in this product term
9389  *  0b11..Force the B input in this product term to a logical one
9390  */
9391 #define AOI_BFCRT23_PT3_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
9392 
9393 #define AOI_BFCRT23_PT3_AC_MASK                  (0xC0U)
9394 #define AOI_BFCRT23_PT3_AC_SHIFT                 (6U)
9395 /*! PT3_AC - Product term 3, A input configuration
9396  *  0b00..Force the A input in this product term to a logical zero
9397  *  0b01..Pass the A input in this product term
9398  *  0b10..Complement the A input in this product term
9399  *  0b11..Force the A input in this product term to a logical one
9400  */
9401 #define AOI_BFCRT23_PT3_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
9402 
9403 #define AOI_BFCRT23_PT2_DC_MASK                  (0x300U)
9404 #define AOI_BFCRT23_PT2_DC_SHIFT                 (8U)
9405 /*! PT2_DC - Product term 2, D input configuration
9406  *  0b00..Force the D input in this product term to a logical zero
9407  *  0b01..Pass the D input in this product term
9408  *  0b10..Complement the D input in this product term
9409  *  0b11..Force the D input in this product term to a logical one
9410  */
9411 #define AOI_BFCRT23_PT2_DC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
9412 
9413 #define AOI_BFCRT23_PT2_CC_MASK                  (0xC00U)
9414 #define AOI_BFCRT23_PT2_CC_SHIFT                 (10U)
9415 /*! PT2_CC - Product term 2, C input configuration
9416  *  0b00..Force the C input in this product term to a logical zero
9417  *  0b01..Pass the C input in this product term
9418  *  0b10..Complement the C input in this product term
9419  *  0b11..Force the C input in this product term to a logical one
9420  */
9421 #define AOI_BFCRT23_PT2_CC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
9422 
9423 #define AOI_BFCRT23_PT2_BC_MASK                  (0x3000U)
9424 #define AOI_BFCRT23_PT2_BC_SHIFT                 (12U)
9425 /*! PT2_BC - Product term 2, B input configuration
9426  *  0b00..Force the B input in this product term to a logical zero
9427  *  0b01..Pass the B input in this product term
9428  *  0b10..Complement the B input in this product term
9429  *  0b11..Force the B input in this product term to a logical one
9430  */
9431 #define AOI_BFCRT23_PT2_BC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
9432 
9433 #define AOI_BFCRT23_PT2_AC_MASK                  (0xC000U)
9434 #define AOI_BFCRT23_PT2_AC_SHIFT                 (14U)
9435 /*! PT2_AC - Product term 2, A input configuration
9436  *  0b00..Force the A input in this product term to a logical zero
9437  *  0b01..Pass the A input in this product term
9438  *  0b10..Complement the A input in this product term
9439  *  0b11..Force the A input in this product term to a logical one
9440  */
9441 #define AOI_BFCRT23_PT2_AC(x)                    (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
9442 /*! @} */
9443 
9444 /* The count of AOI_BFCRT23 */
9445 #define AOI_BFCRT23_COUNT                        (4U)
9446 
9447 
9448 /*!
9449  * @}
9450  */ /* end of group AOI_Register_Masks */
9451 
9452 
9453 /* AOI - Peripheral instance base addresses */
9454 /** Peripheral AOI1 base address */
9455 #define AOI1_BASE                                (0x400B8000u)
9456 /** Peripheral AOI1 base pointer */
9457 #define AOI1                                     ((AOI_Type *)AOI1_BASE)
9458 /** Peripheral AOI2 base address */
9459 #define AOI2_BASE                                (0x400BC000u)
9460 /** Peripheral AOI2 base pointer */
9461 #define AOI2                                     ((AOI_Type *)AOI2_BASE)
9462 /** Array initializer of AOI peripheral base addresses */
9463 #define AOI_BASE_ADDRS                           { 0u, AOI1_BASE, AOI2_BASE }
9464 /** Array initializer of AOI peripheral base pointers */
9465 #define AOI_BASE_PTRS                            { (AOI_Type *)0u, AOI1, AOI2 }
9466 
9467 /*!
9468  * @}
9469  */ /* end of group AOI_Peripheral_Access_Layer */
9470 
9471 
9472 /* ----------------------------------------------------------------------------
9473    -- ASRC Peripheral Access Layer
9474    ---------------------------------------------------------------------------- */
9475 
9476 /*!
9477  * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
9478  * @{
9479  */
9480 
9481 /** ASRC - Register Layout Typedef */
9482 typedef struct {
9483   __IO uint32_t ASRCTR;                            /**< ASRC Control Register, offset: 0x0 */
9484   __IO uint32_t ASRIER;                            /**< ASRC Interrupt Enable Register, offset: 0x4 */
9485        uint8_t RESERVED_0[4];
9486   __IO uint32_t ASRCNCR;                           /**< ASRC Channel Number Configuration Register, offset: 0xC */
9487   __IO uint32_t ASRCFG;                            /**< ASRC Filter Configuration Status Register, offset: 0x10 */
9488   __IO uint32_t ASRCSR;                            /**< ASRC Clock Source Register, offset: 0x14 */
9489   __IO uint32_t ASRCDR1;                           /**< ASRC Clock Divider Register 1, offset: 0x18 */
9490   __IO uint32_t ASRCDR2;                           /**< ASRC Clock Divider Register 2, offset: 0x1C */
9491   __I  uint32_t ASRSTR;                            /**< ASRC Status Register, offset: 0x20 */
9492        uint8_t RESERVED_1[28];
9493   __IO uint32_t ASRPM[5];                          /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */
9494   __IO uint32_t ASRTFR1;                           /**< ASRC Task Queue FIFO Register 1, offset: 0x54 */
9495        uint8_t RESERVED_2[4];
9496   __IO uint32_t ASRCCR;                            /**< ASRC Channel Counter Register, offset: 0x5C */
9497   __O  uint32_t ASRDIA;                            /**< ASRC Data Input Register for Pair x, offset: 0x60 */
9498   __I  uint32_t ASRDOA;                            /**< ASRC Data Output Register for Pair x, offset: 0x64 */
9499   __O  uint32_t ASRDIB;                            /**< ASRC Data Input Register for Pair x, offset: 0x68 */
9500   __I  uint32_t ASRDOB;                            /**< ASRC Data Output Register for Pair x, offset: 0x6C */
9501   __O  uint32_t ASRDIC;                            /**< ASRC Data Input Register for Pair x, offset: 0x70 */
9502   __I  uint32_t ASRDOC;                            /**< ASRC Data Output Register for Pair x, offset: 0x74 */
9503        uint8_t RESERVED_3[8];
9504   __IO uint32_t ASRIDRHA;                          /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */
9505   __IO uint32_t ASRIDRLA;                          /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */
9506   __IO uint32_t ASRIDRHB;                          /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */
9507   __IO uint32_t ASRIDRLB;                          /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */
9508   __IO uint32_t ASRIDRHC;                          /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */
9509   __IO uint32_t ASRIDRLC;                          /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */
9510   __IO uint32_t ASR76K;                            /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */
9511   __IO uint32_t ASR56K;                            /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */
9512   __IO uint32_t ASRMCRA;                           /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */
9513   __I  uint32_t ASRFSTA;                           /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */
9514   __IO uint32_t ASRMCRB;                           /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */
9515   __I  uint32_t ASRFSTB;                           /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */
9516   __IO uint32_t ASRMCRC;                           /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */
9517   __I  uint32_t ASRFSTC;                           /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */
9518        uint8_t RESERVED_4[8];
9519   __IO uint32_t ASRMCR1[3];                        /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */
9520 } ASRC_Type;
9521 
9522 /* ----------------------------------------------------------------------------
9523    -- ASRC Register Masks
9524    ---------------------------------------------------------------------------- */
9525 
9526 /*!
9527  * @addtogroup ASRC_Register_Masks ASRC Register Masks
9528  * @{
9529  */
9530 
9531 /*! @name ASRCTR - ASRC Control Register */
9532 /*! @{ */
9533 
9534 #define ASRC_ASRCTR_ASRCEN_MASK                  (0x1U)
9535 #define ASRC_ASRCTR_ASRCEN_SHIFT                 (0U)
9536 /*! ASRCEN - ASRCEN
9537  *  0b0..operation of ASRC disabled
9538  *  0b1..operation ASRC is enabled
9539  */
9540 #define ASRC_ASRCTR_ASRCEN(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK)
9541 
9542 #define ASRC_ASRCTR_ASREA_MASK                   (0x2U)
9543 #define ASRC_ASRCTR_ASREA_SHIFT                  (1U)
9544 /*! ASREA - ASREA
9545  *  0b0..operation of conversion A is disabled
9546  *  0b1..operation of conversion A is enabled
9547  */
9548 #define ASRC_ASRCTR_ASREA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK)
9549 
9550 #define ASRC_ASRCTR_ASREB_MASK                   (0x4U)
9551 #define ASRC_ASRCTR_ASREB_SHIFT                  (2U)
9552 /*! ASREB - ASREB
9553  *  0b0..operation of conversion B is disabled
9554  *  0b1..operation of conversion B is enabled
9555  */
9556 #define ASRC_ASRCTR_ASREB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK)
9557 
9558 #define ASRC_ASRCTR_ASREC_MASK                   (0x8U)
9559 #define ASRC_ASRCTR_ASREC_SHIFT                  (3U)
9560 /*! ASREC - ASREC
9561  *  0b0..operation of conversion C is disabled
9562  *  0b1..operation of conversion C is enabled
9563  */
9564 #define ASRC_ASRCTR_ASREC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK)
9565 
9566 #define ASRC_ASRCTR_SRST_MASK                    (0x10U)
9567 #define ASRC_ASRCTR_SRST_SHIFT                   (4U)
9568 /*! SRST - SRST
9569  *  0b0..ASRC Software reset cleared
9570  *  0b1..ASRC Software reset generated. NOTE: This is a self-clear bit
9571  */
9572 #define ASRC_ASRCTR_SRST(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK)
9573 
9574 #define ASRC_ASRCTR_IDRA_MASK                    (0x2000U)
9575 #define ASRC_ASRCTR_IDRA_SHIFT                   (13U)
9576 /*! IDRA - IDRA
9577  *  0b0..ASRC internal measured ratio is used
9578  *  0b1..Ideal ratio from the interface register ASRIDRHA, ASRIDRLA is used
9579  */
9580 #define ASRC_ASRCTR_IDRA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK)
9581 
9582 #define ASRC_ASRCTR_USRA_MASK                    (0x4000U)
9583 #define ASRC_ASRCTR_USRA_SHIFT                   (14U)
9584 /*! USRA - USRA
9585  *  0b1..Use ratio as the input to ASRC for pair A
9586  *  0b0..Do not use ratio as the input to ASRC for pair A
9587  */
9588 #define ASRC_ASRCTR_USRA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK)
9589 
9590 #define ASRC_ASRCTR_IDRB_MASK                    (0x8000U)
9591 #define ASRC_ASRCTR_IDRB_SHIFT                   (15U)
9592 /*! IDRB - IDRB
9593  *  0b0..ASRC internal measured ratio is used
9594  *  0b1..Ideal ratio from the interface register ASRIDRHB, ASRIDRLB is used
9595  */
9596 #define ASRC_ASRCTR_IDRB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK)
9597 
9598 #define ASRC_ASRCTR_USRB_MASK                    (0x10000U)
9599 #define ASRC_ASRCTR_USRB_SHIFT                   (16U)
9600 /*! USRB - USRB
9601  *  0b1..Use ratio as the input to ASRC for pair B
9602  *  0b0..Do not use ratio as the input to ASRC for pair B
9603  */
9604 #define ASRC_ASRCTR_USRB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK)
9605 
9606 #define ASRC_ASRCTR_IDRC_MASK                    (0x20000U)
9607 #define ASRC_ASRCTR_IDRC_SHIFT                   (17U)
9608 /*! IDRC - IDRC
9609  *  0b0..ASRC internal measured ratio is used
9610  *  0b1..Ideal ratio from the interface register ASRIDRHC, ASRIDRLC is used
9611  */
9612 #define ASRC_ASRCTR_IDRC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK)
9613 
9614 #define ASRC_ASRCTR_USRC_MASK                    (0x40000U)
9615 #define ASRC_ASRCTR_USRC_SHIFT                   (18U)
9616 /*! USRC - USRC
9617  *  0b1..Use ratio as the input to ASRC for pair C
9618  *  0b0..Do not use ratio as the input to ASRC for pair C
9619  */
9620 #define ASRC_ASRCTR_USRC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK)
9621 
9622 #define ASRC_ASRCTR_ATSA_MASK                    (0x100000U)
9623 #define ASRC_ASRCTR_ATSA_SHIFT                   (20U)
9624 /*! ATSA - ATSA
9625  *  0b1..Pair A automatically updates its pre-processing and post-processing options
9626  *  0b0..Pair A does not automatically update its pre-processing and post-processing options
9627  */
9628 #define ASRC_ASRCTR_ATSA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK)
9629 
9630 #define ASRC_ASRCTR_ATSB_MASK                    (0x200000U)
9631 #define ASRC_ASRCTR_ATSB_SHIFT                   (21U)
9632 /*! ATSB - ATSB
9633  *  0b1..Pair B automatically updates its pre-processing and post-processing options
9634  *  0b0..Pair B does not automatically update its pre-processing and post-processing options
9635  */
9636 #define ASRC_ASRCTR_ATSB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK)
9637 
9638 #define ASRC_ASRCTR_ATSC_MASK                    (0x400000U)
9639 #define ASRC_ASRCTR_ATSC_SHIFT                   (22U)
9640 /*! ATSC - ATSC
9641  *  0b1..Pair C automatically updates its pre-processing and post-processing options
9642  *  0b0..Pair C does not automatically update its pre-processing and post-processing options
9643  */
9644 #define ASRC_ASRCTR_ATSC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK)
9645 /*! @} */
9646 
9647 /*! @name ASRIER - ASRC Interrupt Enable Register */
9648 /*! @{ */
9649 
9650 #define ASRC_ASRIER_ADIEA_MASK                   (0x1U)
9651 #define ASRC_ASRIER_ADIEA_SHIFT                  (0U)
9652 /*! ADIEA - ADIEA
9653  *  0b1..interrupt enabled
9654  *  0b0..interrupt disabled
9655  */
9656 #define ASRC_ASRIER_ADIEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK)
9657 
9658 #define ASRC_ASRIER_ADIEB_MASK                   (0x2U)
9659 #define ASRC_ASRIER_ADIEB_SHIFT                  (1U)
9660 /*! ADIEB - ADIEB
9661  *  0b1..interrupt enabled
9662  *  0b0..interrupt disabled
9663  */
9664 #define ASRC_ASRIER_ADIEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK)
9665 
9666 #define ASRC_ASRIER_ADIEC_MASK                   (0x4U)
9667 #define ASRC_ASRIER_ADIEC_SHIFT                  (2U)
9668 /*! ADIEC - ADIEC
9669  *  0b1..interrupt enabled
9670  *  0b0..interrupt disabled
9671  */
9672 #define ASRC_ASRIER_ADIEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK)
9673 
9674 #define ASRC_ASRIER_ADOEA_MASK                   (0x8U)
9675 #define ASRC_ASRIER_ADOEA_SHIFT                  (3U)
9676 /*! ADOEA - ADOEA
9677  *  0b1..interrupt enabled
9678  *  0b0..interrupt disabled
9679  */
9680 #define ASRC_ASRIER_ADOEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK)
9681 
9682 #define ASRC_ASRIER_ADOEB_MASK                   (0x10U)
9683 #define ASRC_ASRIER_ADOEB_SHIFT                  (4U)
9684 /*! ADOEB - ADOEB
9685  *  0b1..interrupt enabled
9686  *  0b0..interrupt disabled
9687  */
9688 #define ASRC_ASRIER_ADOEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK)
9689 
9690 #define ASRC_ASRIER_ADOEC_MASK                   (0x20U)
9691 #define ASRC_ASRIER_ADOEC_SHIFT                  (5U)
9692 /*! ADOEC - ADOEC
9693  *  0b1..interrupt enabled
9694  *  0b0..interrupt disabled
9695  */
9696 #define ASRC_ASRIER_ADOEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK)
9697 
9698 #define ASRC_ASRIER_AOLIE_MASK                   (0x40U)
9699 #define ASRC_ASRIER_AOLIE_SHIFT                  (6U)
9700 /*! AOLIE - AOLIE
9701  *  0b1..interrupt enabled
9702  *  0b0..interrupt disabled
9703  */
9704 #define ASRC_ASRIER_AOLIE(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK)
9705 
9706 #define ASRC_ASRIER_AFPWE_MASK                   (0x80U)
9707 #define ASRC_ASRIER_AFPWE_SHIFT                  (7U)
9708 /*! AFPWE - AFPWE
9709  *  0b1..interrupt enabled
9710  *  0b0..interrupt disabled
9711  */
9712 #define ASRC_ASRIER_AFPWE(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK)
9713 /*! @} */
9714 
9715 /*! @name ASRCNCR - ASRC Channel Number Configuration Register */
9716 /*! @{ */
9717 
9718 #define ASRC_ASRCNCR_ANCA_MASK                   (0xFU)
9719 #define ASRC_ASRCNCR_ANCA_SHIFT                  (0U)
9720 /*! ANCA - ANCA
9721  *  0b0000..0 channels in A (Pair A is disabled)
9722  *  0b0001..1 channel in A
9723  *  0b0010..2 channels in A
9724  *  0b0011..3 channels in A
9725  *  0b0100..4 channels in A
9726  *  0b0101..5 channels in A
9727  *  0b0110..6 channels in A
9728  *  0b0111..7 channels in A
9729  *  0b1000..8 channels in A
9730  *  0b1001..9 channels in A
9731  *  0b1010..10 channels in A
9732  *  0b1011-0b1111..Should not be used.
9733  */
9734 #define ASRC_ASRCNCR_ANCA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK)
9735 
9736 #define ASRC_ASRCNCR_ANCB_MASK                   (0xF0U)
9737 #define ASRC_ASRCNCR_ANCB_SHIFT                  (4U)
9738 /*! ANCB - ANCB
9739  *  0b0000..0 channels in B (Pair B is disabled)
9740  *  0b0001..1 channel in B
9741  *  0b0010..2 channels in B
9742  *  0b0011..3 channels in B
9743  *  0b0100..4 channels in B
9744  *  0b0101..5 channels in B
9745  *  0b0110..6 channels in B
9746  *  0b0111..7 channels in B
9747  *  0b1000..8 channels in B
9748  *  0b1001..9 channels in B
9749  *  0b1010..10 channels in B
9750  *  0b1011-0b1111..Should not be used.
9751  */
9752 #define ASRC_ASRCNCR_ANCB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK)
9753 
9754 #define ASRC_ASRCNCR_ANCC_MASK                   (0xF00U)
9755 #define ASRC_ASRCNCR_ANCC_SHIFT                  (8U)
9756 /*! ANCC - ANCC
9757  *  0b0000..0 channels in C (Pair C is disabled)
9758  *  0b0001..1 channel in C
9759  *  0b0010..2 channels in C
9760  *  0b0011..3 channels in C
9761  *  0b0100..4 channels in C
9762  *  0b0101..5 channels in C
9763  *  0b0110..6 channels in C
9764  *  0b0111..7 channels in C
9765  *  0b1000..8 channels in C
9766  *  0b1001..9 channels in C
9767  *  0b1010..10 channels in C
9768  *  0b1011-0b1111..Should not be used.
9769  */
9770 #define ASRC_ASRCNCR_ANCC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK)
9771 /*! @} */
9772 
9773 /*! @name ASRCFG - ASRC Filter Configuration Status Register */
9774 /*! @{ */
9775 
9776 #define ASRC_ASRCFG_PREMODA_MASK                 (0xC0U)
9777 #define ASRC_ASRCFG_PREMODA_SHIFT                (6U)
9778 /*! PREMODA - PREMODA
9779  *  0b00..Select Upsampling-by-2
9780  *  0b01..Select Direct-Connection
9781  *  0b10..Select Downsampling-by-2
9782  *  0b11..Select passthrough mode. In this case, POSTMODA[1:0] have no use.
9783  */
9784 #define ASRC_ASRCFG_PREMODA(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK)
9785 
9786 #define ASRC_ASRCFG_POSTMODA_MASK                (0x300U)
9787 #define ASRC_ASRCFG_POSTMODA_SHIFT               (8U)
9788 /*! POSTMODA - POSTMODA
9789  *  0b00..Select Upsampling-by-2
9790  *  0b01..Select Direct-Connection
9791  *  0b10..Select Downsampling-by-2
9792  *  0b11..Reserved.
9793  */
9794 #define ASRC_ASRCFG_POSTMODA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK)
9795 
9796 #define ASRC_ASRCFG_PREMODB_MASK                 (0xC00U)
9797 #define ASRC_ASRCFG_PREMODB_SHIFT                (10U)
9798 /*! PREMODB - PREMODB
9799  *  0b00..Select Upsampling-by-2
9800  *  0b01..Select Direct-Connection
9801  *  0b10..Select Downsampling-by-2
9802  *  0b11..Select passthrough mode. In this case, POSTMODB[1:0] have no use.
9803  */
9804 #define ASRC_ASRCFG_PREMODB(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK)
9805 
9806 #define ASRC_ASRCFG_POSTMODB_MASK                (0x3000U)
9807 #define ASRC_ASRCFG_POSTMODB_SHIFT               (12U)
9808 /*! POSTMODB - POSTMODB
9809  *  0b00..Select Upsampling-by-2
9810  *  0b01..Select Direct-Connection
9811  *  0b10..Select Downsampling-by-2
9812  *  0b11..Reserved.
9813  */
9814 #define ASRC_ASRCFG_POSTMODB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK)
9815 
9816 #define ASRC_ASRCFG_PREMODC_MASK                 (0xC000U)
9817 #define ASRC_ASRCFG_PREMODC_SHIFT                (14U)
9818 /*! PREMODC - PREMODC
9819  *  0b00..Select Upsampling-by-2
9820  *  0b01..Select Direct-Connection
9821  *  0b10..Select Downsampling-by-2
9822  *  0b11..Select passthrough mode. In this case, POSTMODC[1:0] have no use.
9823  */
9824 #define ASRC_ASRCFG_PREMODC(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK)
9825 
9826 #define ASRC_ASRCFG_POSTMODC_MASK                (0x30000U)
9827 #define ASRC_ASRCFG_POSTMODC_SHIFT               (16U)
9828 /*! POSTMODC - POSTMODC
9829  *  0b00..Select Upsampling-by-2 as defined in Signal Processing Flow.
9830  *  0b01..Select Direct-Connection as defined in Signal Processing Flow.
9831  *  0b10..Select Downsampling-by-2 as defined in Signal Processing Flow.
9832  *  0b11..Reserved.
9833  */
9834 #define ASRC_ASRCFG_POSTMODC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK)
9835 
9836 #define ASRC_ASRCFG_NDPRA_MASK                   (0x40000U)
9837 #define ASRC_ASRCFG_NDPRA_SHIFT                  (18U)
9838 /*! NDPRA - NDPRA
9839  *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
9840  *  0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
9841  */
9842 #define ASRC_ASRCFG_NDPRA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK)
9843 
9844 #define ASRC_ASRCFG_NDPRB_MASK                   (0x80000U)
9845 #define ASRC_ASRCFG_NDPRB_SHIFT                  (19U)
9846 /*! NDPRB - NDPRB
9847  *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
9848  *  0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.
9849  */
9850 #define ASRC_ASRCFG_NDPRB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK)
9851 
9852 #define ASRC_ASRCFG_NDPRC_MASK                   (0x100000U)
9853 #define ASRC_ASRCFG_NDPRC_SHIFT                  (20U)
9854 /*! NDPRC - NDPRC
9855  *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
9856  *  0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
9857  */
9858 #define ASRC_ASRCFG_NDPRC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK)
9859 
9860 #define ASRC_ASRCFG_INIRQA_MASK                  (0x200000U)
9861 #define ASRC_ASRCFG_INIRQA_SHIFT                 (21U)
9862 /*! INIRQA - INIRQA
9863  *  0b0..Initialization for Conversion Pair A not served
9864  *  0b1..Initialization for Conversion Pair A served
9865  */
9866 #define ASRC_ASRCFG_INIRQA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK)
9867 
9868 #define ASRC_ASRCFG_INIRQB_MASK                  (0x400000U)
9869 #define ASRC_ASRCFG_INIRQB_SHIFT                 (22U)
9870 /*! INIRQB - INIRQB
9871  *  0b0..Initialization for Conversion Pair B not served
9872  *  0b1..Initialization for Conversion Pair B served
9873  */
9874 #define ASRC_ASRCFG_INIRQB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK)
9875 
9876 #define ASRC_ASRCFG_INIRQC_MASK                  (0x800000U)
9877 #define ASRC_ASRCFG_INIRQC_SHIFT                 (23U)
9878 /*! INIRQC - INIRQC
9879  *  0b0..Initialization for Conversion Pair C not served
9880  *  0b1..Initialization for Conversion Pair C served
9881  */
9882 #define ASRC_ASRCFG_INIRQC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK)
9883 /*! @} */
9884 
9885 /*! @name ASRCSR - ASRC Clock Source Register */
9886 /*! @{ */
9887 
9888 #define ASRC_ASRCSR_AICSA_MASK                   (0xFU)
9889 #define ASRC_ASRCSR_AICSA_SHIFT                  (0U)
9890 /*! AICSA - AICSA
9891  *  0b0000..bit clock 0
9892  *  0b0001..bit clock 1
9893  *  0b0010..bit clock 2
9894  *  0b0011..bit clock 3
9895  *  0b0100..bit clock 4
9896  *  0b0101..bit clock 5
9897  *  0b0110..bit clock 6
9898  *  0b0111..bit clock 7
9899  *  0b1000..bit clock 8
9900  *  0b1001..bit clock 9
9901  *  0b1010..bit clock A
9902  *  0b1011..bit clock B
9903  *  0b1100..bit clock C
9904  *  0b1101..bit clock D
9905  *  0b1110..bit clock E
9906  *  0b1111..clock disabled, connected to zero
9907  */
9908 #define ASRC_ASRCSR_AICSA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK)
9909 
9910 #define ASRC_ASRCSR_AICSB_MASK                   (0xF0U)
9911 #define ASRC_ASRCSR_AICSB_SHIFT                  (4U)
9912 /*! AICSB - AICSB
9913  *  0b0000..bit clock 0
9914  *  0b0001..bit clock 1
9915  *  0b0010..bit clock 2
9916  *  0b0011..bit clock 3
9917  *  0b0100..bit clock 4
9918  *  0b0101..bit clock 5
9919  *  0b0110..bit clock 6
9920  *  0b0111..bit clock 7
9921  *  0b1000..bit clock 8
9922  *  0b1001..bit clock 9
9923  *  0b1010..bit clock A
9924  *  0b1011..bit clock B
9925  *  0b1100..bit clock C
9926  *  0b1101..bit clock D
9927  *  0b1110..bit clock E
9928  *  0b1111..clock disabled, connected to zero
9929  */
9930 #define ASRC_ASRCSR_AICSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK)
9931 
9932 #define ASRC_ASRCSR_AICSC_MASK                   (0xF00U)
9933 #define ASRC_ASRCSR_AICSC_SHIFT                  (8U)
9934 /*! AICSC - AICSC
9935  *  0b0000..bit clock 0
9936  *  0b0001..bit clock 1
9937  *  0b0010..bit clock 2
9938  *  0b0011..bit clock 3
9939  *  0b0100..bit clock 4
9940  *  0b0101..bit clock 5
9941  *  0b0110..bit clock 6
9942  *  0b0111..bit clock 7
9943  *  0b1000..bit clock 8
9944  *  0b1001..bit clock 9
9945  *  0b1010..bit clock A
9946  *  0b1011..bit clock B
9947  *  0b1100..bit clock C
9948  *  0b1101..bit clock D
9949  *  0b1110..bit clock E
9950  *  0b1111..clock disabled, connected to zero
9951  */
9952 #define ASRC_ASRCSR_AICSC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK)
9953 
9954 #define ASRC_ASRCSR_AOCSA_MASK                   (0xF000U)
9955 #define ASRC_ASRCSR_AOCSA_SHIFT                  (12U)
9956 /*! AOCSA - AOCSA
9957  *  0b0000..bit clock 0
9958  *  0b0001..bit clock 1
9959  *  0b0010..bit clock 2
9960  *  0b0011..bit clock 3
9961  *  0b0100..bit clock 4
9962  *  0b0101..bit clock 5
9963  *  0b0110..bit clock 6
9964  *  0b0111..bit clock 7
9965  *  0b1000..bit clock 8
9966  *  0b1001..bit clock 9
9967  *  0b1010..bit clock A
9968  *  0b1011..bit clock B
9969  *  0b1100..bit clock C
9970  *  0b1101..bit clock D
9971  *  0b1110..bit clock E
9972  *  0b1111..clock disabled, connected to zero
9973  */
9974 #define ASRC_ASRCSR_AOCSA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK)
9975 
9976 #define ASRC_ASRCSR_AOCSB_MASK                   (0xF0000U)
9977 #define ASRC_ASRCSR_AOCSB_SHIFT                  (16U)
9978 /*! AOCSB - AOCSB
9979  *  0b0000..bit clock 0
9980  *  0b0001..bit clock 1
9981  *  0b0010..bit clock 2
9982  *  0b0011..bit clock 3
9983  *  0b0100..bit clock 4
9984  *  0b0101..bit clock 5
9985  *  0b0110..bit clock 6
9986  *  0b0111..bit clock 7
9987  *  0b1000..bit clock 8
9988  *  0b1001..bit clock 9
9989  *  0b1010..bit clock A
9990  *  0b1011..bit clock B
9991  *  0b1100..bit clock C
9992  *  0b1101..bit clock D
9993  *  0b1110..bit clock E
9994  *  0b1111..clock disabled, connected to zero
9995  */
9996 #define ASRC_ASRCSR_AOCSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK)
9997 
9998 #define ASRC_ASRCSR_AOCSC_MASK                   (0xF00000U)
9999 #define ASRC_ASRCSR_AOCSC_SHIFT                  (20U)
10000 /*! AOCSC - AOCSC
10001  *  0b0000..bit clock 0
10002  *  0b0001..bit clock 1
10003  *  0b0010..bit clock 2
10004  *  0b0011..bit clock 3
10005  *  0b0100..bit clock 4
10006  *  0b0101..bit clock 5
10007  *  0b0110..bit clock 6
10008  *  0b0111..bit clock 7
10009  *  0b1000..bit clock 8
10010  *  0b1001..bit clock 9
10011  *  0b1010..bit clock A
10012  *  0b1011..bit clock B
10013  *  0b1100..bit clock C
10014  *  0b1101..bit clock D
10015  *  0b1110..bit clock E
10016  *  0b1111..clock disabled, connected to zero
10017  */
10018 #define ASRC_ASRCSR_AOCSC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK)
10019 /*! @} */
10020 
10021 /*! @name ASRCDR1 - ASRC Clock Divider Register 1 */
10022 /*! @{ */
10023 
10024 #define ASRC_ASRCDR1_AICPA_MASK                  (0x7U)
10025 #define ASRC_ASRCDR1_AICPA_SHIFT                 (0U)
10026 /*! AICPA - AICPA */
10027 #define ASRC_ASRCDR1_AICPA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK)
10028 
10029 #define ASRC_ASRCDR1_AICDA_MASK                  (0x38U)
10030 #define ASRC_ASRCDR1_AICDA_SHIFT                 (3U)
10031 /*! AICDA - AICDA */
10032 #define ASRC_ASRCDR1_AICDA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK)
10033 
10034 #define ASRC_ASRCDR1_AICPB_MASK                  (0x1C0U)
10035 #define ASRC_ASRCDR1_AICPB_SHIFT                 (6U)
10036 /*! AICPB - AICPB */
10037 #define ASRC_ASRCDR1_AICPB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK)
10038 
10039 #define ASRC_ASRCDR1_AICDB_MASK                  (0xE00U)
10040 #define ASRC_ASRCDR1_AICDB_SHIFT                 (9U)
10041 /*! AICDB - AICDB */
10042 #define ASRC_ASRCDR1_AICDB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK)
10043 
10044 #define ASRC_ASRCDR1_AOCPA_MASK                  (0x7000U)
10045 #define ASRC_ASRCDR1_AOCPA_SHIFT                 (12U)
10046 /*! AOCPA - AOCPA */
10047 #define ASRC_ASRCDR1_AOCPA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK)
10048 
10049 #define ASRC_ASRCDR1_AOCDA_MASK                  (0x38000U)
10050 #define ASRC_ASRCDR1_AOCDA_SHIFT                 (15U)
10051 /*! AOCDA - AOCDA */
10052 #define ASRC_ASRCDR1_AOCDA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK)
10053 
10054 #define ASRC_ASRCDR1_AOCPB_MASK                  (0x1C0000U)
10055 #define ASRC_ASRCDR1_AOCPB_SHIFT                 (18U)
10056 /*! AOCPB - AOCPB */
10057 #define ASRC_ASRCDR1_AOCPB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK)
10058 
10059 #define ASRC_ASRCDR1_AOCDB_MASK                  (0xE00000U)
10060 #define ASRC_ASRCDR1_AOCDB_SHIFT                 (21U)
10061 /*! AOCDB - AOCDB */
10062 #define ASRC_ASRCDR1_AOCDB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK)
10063 /*! @} */
10064 
10065 /*! @name ASRCDR2 - ASRC Clock Divider Register 2 */
10066 /*! @{ */
10067 
10068 #define ASRC_ASRCDR2_AICPC_MASK                  (0x7U)
10069 #define ASRC_ASRCDR2_AICPC_SHIFT                 (0U)
10070 /*! AICPC - AICPC */
10071 #define ASRC_ASRCDR2_AICPC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK)
10072 
10073 #define ASRC_ASRCDR2_AICDC_MASK                  (0x38U)
10074 #define ASRC_ASRCDR2_AICDC_SHIFT                 (3U)
10075 /*! AICDC - AICDC */
10076 #define ASRC_ASRCDR2_AICDC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK)
10077 
10078 #define ASRC_ASRCDR2_AOCPC_MASK                  (0x1C0U)
10079 #define ASRC_ASRCDR2_AOCPC_SHIFT                 (6U)
10080 /*! AOCPC - AOCPC */
10081 #define ASRC_ASRCDR2_AOCPC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK)
10082 
10083 #define ASRC_ASRCDR2_AOCDC_MASK                  (0xE00U)
10084 #define ASRC_ASRCDR2_AOCDC_SHIFT                 (9U)
10085 /*! AOCDC - AOCDC */
10086 #define ASRC_ASRCDR2_AOCDC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK)
10087 /*! @} */
10088 
10089 /*! @name ASRSTR - ASRC Status Register */
10090 /*! @{ */
10091 
10092 #define ASRC_ASRSTR_AIDEA_MASK                   (0x1U)
10093 #define ASRC_ASRSTR_AIDEA_SHIFT                  (0U)
10094 /*! AIDEA - AIDEA
10095  *  0b1..When AIDEA is set, the ASRC generates data input A interrupt request to the processor if ASRIER[AIDEA] = 1
10096  *  0b0..The threshold has been met and no data input A interrupt is generated
10097  */
10098 #define ASRC_ASRSTR_AIDEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK)
10099 
10100 #define ASRC_ASRSTR_AIDEB_MASK                   (0x2U)
10101 #define ASRC_ASRSTR_AIDEB_SHIFT                  (1U)
10102 /*! AIDEB - AIDEB
10103  *  0b1..When AIDEB is set, the ASRC generates data input B interrupt request to the processor if ASRIER[AIDEB] = 1
10104  *  0b0..The threshold has been met and no data input B interrupt is generated
10105  */
10106 #define ASRC_ASRSTR_AIDEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK)
10107 
10108 #define ASRC_ASRSTR_AIDEC_MASK                   (0x4U)
10109 #define ASRC_ASRSTR_AIDEC_SHIFT                  (2U)
10110 /*! AIDEC - AIDEC
10111  *  0b1..When AIDEC is set, the ASRC generates data input C interrupt request to the processor if ASRIER[AIDEC] = 1
10112  *  0b0..The threshold has been met and no data input C interrupt is generated
10113  */
10114 #define ASRC_ASRSTR_AIDEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK)
10115 
10116 #define ASRC_ASRSTR_AODFA_MASK                   (0x8U)
10117 #define ASRC_ASRSTR_AODFA_SHIFT                  (3U)
10118 /*! AODFA - AODFA
10119  *  0b1..When AODFA is set, the ASRC generates data output A interrupt request to the processor if ASRIER[ADOEA] = 1
10120  *  0b0..The threshold has not yet been met and no data output A interrupt is generated
10121  */
10122 #define ASRC_ASRSTR_AODFA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK)
10123 
10124 #define ASRC_ASRSTR_AODFB_MASK                   (0x10U)
10125 #define ASRC_ASRSTR_AODFB_SHIFT                  (4U)
10126 /*! AODFB - AODFB
10127  *  0b1..When AODFB is set, the ASRC generates data output B interrupt request to the processor if ASRIER[ADOEB] = 1
10128  *  0b0..The threshold has not yet been met and no data output B interrupt is generated
10129  */
10130 #define ASRC_ASRSTR_AODFB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK)
10131 
10132 #define ASRC_ASRSTR_AODFC_MASK                   (0x20U)
10133 #define ASRC_ASRSTR_AODFC_SHIFT                  (5U)
10134 /*! AODFC - AODFC
10135  *  0b1..When AODFC is set, the ASRC generates data output C interrupt request to the processor if ASRIER[ADOEC] = 1
10136  *  0b0..The threshold has not yet been met and no data output C interrupt is generated
10137  */
10138 #define ASRC_ASRSTR_AODFC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK)
10139 
10140 #define ASRC_ASRSTR_AOLE_MASK                    (0x40U)
10141 #define ASRC_ASRSTR_AOLE_SHIFT                   (6U)
10142 /*! AOLE - AOLE
10143  *  0b1..Task rate is too high
10144  *  0b0..No overload
10145  */
10146 #define ASRC_ASRSTR_AOLE(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK)
10147 
10148 #define ASRC_ASRSTR_FPWT_MASK                    (0x80U)
10149 #define ASRC_ASRSTR_FPWT_SHIFT                   (7U)
10150 /*! FPWT - FPWT
10151  *  0b0..ASRC is not in wait state
10152  *  0b1..ASRC is in wait state
10153  */
10154 #define ASRC_ASRSTR_FPWT(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK)
10155 
10156 #define ASRC_ASRSTR_AIDUA_MASK                   (0x100U)
10157 #define ASRC_ASRSTR_AIDUA_SHIFT                  (8U)
10158 /*! AIDUA - AIDUA
10159  *  0b0..No Underflow in Input data buffer A
10160  *  0b1..Underflow in Input data buffer A
10161  */
10162 #define ASRC_ASRSTR_AIDUA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK)
10163 
10164 #define ASRC_ASRSTR_AIDUB_MASK                   (0x200U)
10165 #define ASRC_ASRSTR_AIDUB_SHIFT                  (9U)
10166 /*! AIDUB - AIDUB
10167  *  0b0..No Underflow in Input data buffer B
10168  *  0b1..Underflow in Input data buffer B
10169  */
10170 #define ASRC_ASRSTR_AIDUB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK)
10171 
10172 #define ASRC_ASRSTR_AIDUC_MASK                   (0x400U)
10173 #define ASRC_ASRSTR_AIDUC_SHIFT                  (10U)
10174 /*! AIDUC - AIDUC
10175  *  0b0..No Underflow in Input data buffer C
10176  *  0b1..Underflow in Input data buffer C
10177  */
10178 #define ASRC_ASRSTR_AIDUC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK)
10179 
10180 #define ASRC_ASRSTR_AODOA_MASK                   (0x800U)
10181 #define ASRC_ASRSTR_AODOA_SHIFT                  (11U)
10182 /*! AODOA - AODOA
10183  *  0b0..No Overflow in Output data buffer A
10184  *  0b1..Overflow in Output data buffer A
10185  */
10186 #define ASRC_ASRSTR_AODOA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK)
10187 
10188 #define ASRC_ASRSTR_AODOB_MASK                   (0x1000U)
10189 #define ASRC_ASRSTR_AODOB_SHIFT                  (12U)
10190 /*! AODOB - AODOB
10191  *  0b0..No Overflow in Output data buffer B
10192  *  0b1..Overflow in Output data buffer B
10193  */
10194 #define ASRC_ASRSTR_AODOB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK)
10195 
10196 #define ASRC_ASRSTR_AODOC_MASK                   (0x2000U)
10197 #define ASRC_ASRSTR_AODOC_SHIFT                  (13U)
10198 /*! AODOC - AODOC
10199  *  0b0..No Overflow in Output data buffer C
10200  *  0b1..Overflow in Output data buffer C
10201  */
10202 #define ASRC_ASRSTR_AODOC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK)
10203 
10204 #define ASRC_ASRSTR_AIOLA_MASK                   (0x4000U)
10205 #define ASRC_ASRSTR_AIOLA_SHIFT                  (14U)
10206 /*! AIOLA - AIOLA
10207  *  0b0..Pair A input task is not oveloaded
10208  *  0b1..Pair A input task is oveloaded
10209  */
10210 #define ASRC_ASRSTR_AIOLA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK)
10211 
10212 #define ASRC_ASRSTR_AIOLB_MASK                   (0x8000U)
10213 #define ASRC_ASRSTR_AIOLB_SHIFT                  (15U)
10214 /*! AIOLB - AIOLB
10215  *  0b0..Pair B input task is not oveloaded
10216  *  0b1..Pair B input task is oveloaded
10217  */
10218 #define ASRC_ASRSTR_AIOLB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK)
10219 
10220 #define ASRC_ASRSTR_AIOLC_MASK                   (0x10000U)
10221 #define ASRC_ASRSTR_AIOLC_SHIFT                  (16U)
10222 /*! AIOLC - AIOLC
10223  *  0b0..Pair C input task is not oveloaded
10224  *  0b1..Pair C input task is oveloaded
10225  */
10226 #define ASRC_ASRSTR_AIOLC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK)
10227 
10228 #define ASRC_ASRSTR_AOOLA_MASK                   (0x20000U)
10229 #define ASRC_ASRSTR_AOOLA_SHIFT                  (17U)
10230 /*! AOOLA - AOOLA
10231  *  0b0..Pair A output task is not oveloaded
10232  *  0b1..Pair A output task is oveloaded
10233  */
10234 #define ASRC_ASRSTR_AOOLA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK)
10235 
10236 #define ASRC_ASRSTR_AOOLB_MASK                   (0x40000U)
10237 #define ASRC_ASRSTR_AOOLB_SHIFT                  (18U)
10238 /*! AOOLB - AOOLB
10239  *  0b0..Pair B output task is not oveloaded
10240  *  0b1..Pair B output task is oveloaded
10241  */
10242 #define ASRC_ASRSTR_AOOLB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK)
10243 
10244 #define ASRC_ASRSTR_AOOLC_MASK                   (0x80000U)
10245 #define ASRC_ASRSTR_AOOLC_SHIFT                  (19U)
10246 /*! AOOLC - AOOLC
10247  *  0b0..Pair C output task is not oveloaded
10248  *  0b1..Pair C output task is oveloaded
10249  */
10250 #define ASRC_ASRSTR_AOOLC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK)
10251 
10252 #define ASRC_ASRSTR_ATQOL_MASK                   (0x100000U)
10253 #define ASRC_ASRSTR_ATQOL_SHIFT                  (20U)
10254 /*! ATQOL - ATQOL
10255  *  0b0..Task queue FIFO logic is not oveloaded
10256  *  0b1..Task queue FIFO logic is oveloaded
10257  */
10258 #define ASRC_ASRSTR_ATQOL(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK)
10259 
10260 #define ASRC_ASRSTR_DSLCNT_MASK                  (0x200000U)
10261 #define ASRC_ASRSTR_DSLCNT_SHIFT                 (21U)
10262 /*! DSLCNT - DSLCNT
10263  *  0b0..New DSL counter information is in the process of storage into the internal ASRC FIFO
10264  *  0b1..New DSL counter information is stored in the internal ASRC FIFO
10265  */
10266 #define ASRC_ASRSTR_DSLCNT(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK)
10267 /*! @} */
10268 
10269 /*! @name ASRPM - ASRC Parameter Register n */
10270 /*! @{ */
10271 
10272 #define ASRC_ASRPM_PARAMETER_VALUE_MASK          (0xFFFFFFU)
10273 #define ASRC_ASRPM_PARAMETER_VALUE_SHIFT         (0U)
10274 /*! PARAMETER_VALUE - PARAMETER_VALUE */
10275 #define ASRC_ASRPM_PARAMETER_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK)
10276 /*! @} */
10277 
10278 /* The count of ASRC_ASRPM */
10279 #define ASRC_ASRPM_COUNT                         (5U)
10280 
10281 /*! @name ASRTFR1 - ASRC Task Queue FIFO Register 1 */
10282 /*! @{ */
10283 
10284 #define ASRC_ASRTFR1_TF_BASE_MASK                (0x1FC0U)
10285 #define ASRC_ASRTFR1_TF_BASE_SHIFT               (6U)
10286 /*! TF_BASE - TF_BASE */
10287 #define ASRC_ASRTFR1_TF_BASE(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK)
10288 
10289 #define ASRC_ASRTFR1_TF_FILL_MASK                (0xFE000U)
10290 #define ASRC_ASRTFR1_TF_FILL_SHIFT               (13U)
10291 /*! TF_FILL - TF_FILL */
10292 #define ASRC_ASRTFR1_TF_FILL(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK)
10293 /*! @} */
10294 
10295 /*! @name ASRCCR - ASRC Channel Counter Register */
10296 /*! @{ */
10297 
10298 #define ASRC_ASRCCR_ACIA_MASK                    (0xFU)
10299 #define ASRC_ASRCCR_ACIA_SHIFT                   (0U)
10300 /*! ACIA - ACIA */
10301 #define ASRC_ASRCCR_ACIA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK)
10302 
10303 #define ASRC_ASRCCR_ACIB_MASK                    (0xF0U)
10304 #define ASRC_ASRCCR_ACIB_SHIFT                   (4U)
10305 /*! ACIB - ACIB */
10306 #define ASRC_ASRCCR_ACIB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK)
10307 
10308 #define ASRC_ASRCCR_ACIC_MASK                    (0xF00U)
10309 #define ASRC_ASRCCR_ACIC_SHIFT                   (8U)
10310 /*! ACIC - ACIC */
10311 #define ASRC_ASRCCR_ACIC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK)
10312 
10313 #define ASRC_ASRCCR_ACOA_MASK                    (0xF000U)
10314 #define ASRC_ASRCCR_ACOA_SHIFT                   (12U)
10315 /*! ACOA - ACOA */
10316 #define ASRC_ASRCCR_ACOA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK)
10317 
10318 #define ASRC_ASRCCR_ACOB_MASK                    (0xF0000U)
10319 #define ASRC_ASRCCR_ACOB_SHIFT                   (16U)
10320 /*! ACOB - ACOB */
10321 #define ASRC_ASRCCR_ACOB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK)
10322 
10323 #define ASRC_ASRCCR_ACOC_MASK                    (0xF00000U)
10324 #define ASRC_ASRCCR_ACOC_SHIFT                   (20U)
10325 /*! ACOC - ACOC */
10326 #define ASRC_ASRCCR_ACOC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK)
10327 /*! @} */
10328 
10329 /*! @name ASRDIA - ASRC Data Input Register for Pair x */
10330 /*! @{ */
10331 
10332 #define ASRC_ASRDIA_DATA_MASK                    (0xFFFFFFU)
10333 #define ASRC_ASRDIA_DATA_SHIFT                   (0U)
10334 /*! DATA - DATA */
10335 #define ASRC_ASRDIA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK)
10336 /*! @} */
10337 
10338 /*! @name ASRDOA - ASRC Data Output Register for Pair x */
10339 /*! @{ */
10340 
10341 #define ASRC_ASRDOA_DATA_MASK                    (0xFFFFFFU)
10342 #define ASRC_ASRDOA_DATA_SHIFT                   (0U)
10343 /*! DATA - DATA */
10344 #define ASRC_ASRDOA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK)
10345 /*! @} */
10346 
10347 /*! @name ASRDIB - ASRC Data Input Register for Pair x */
10348 /*! @{ */
10349 
10350 #define ASRC_ASRDIB_DATA_MASK                    (0xFFFFFFU)
10351 #define ASRC_ASRDIB_DATA_SHIFT                   (0U)
10352 /*! DATA - DATA */
10353 #define ASRC_ASRDIB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK)
10354 /*! @} */
10355 
10356 /*! @name ASRDOB - ASRC Data Output Register for Pair x */
10357 /*! @{ */
10358 
10359 #define ASRC_ASRDOB_DATA_MASK                    (0xFFFFFFU)
10360 #define ASRC_ASRDOB_DATA_SHIFT                   (0U)
10361 /*! DATA - DATA */
10362 #define ASRC_ASRDOB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK)
10363 /*! @} */
10364 
10365 /*! @name ASRDIC - ASRC Data Input Register for Pair x */
10366 /*! @{ */
10367 
10368 #define ASRC_ASRDIC_DATA_MASK                    (0xFFFFFFU)
10369 #define ASRC_ASRDIC_DATA_SHIFT                   (0U)
10370 /*! DATA - DATA */
10371 #define ASRC_ASRDIC_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK)
10372 /*! @} */
10373 
10374 /*! @name ASRDOC - ASRC Data Output Register for Pair x */
10375 /*! @{ */
10376 
10377 #define ASRC_ASRDOC_DATA_MASK                    (0xFFFFFFU)
10378 #define ASRC_ASRDOC_DATA_SHIFT                   (0U)
10379 /*! DATA - DATA */
10380 #define ASRC_ASRDOC_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK)
10381 /*! @} */
10382 
10383 /*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */
10384 /*! @{ */
10385 
10386 #define ASRC_ASRIDRHA_IDRATIOA_H_MASK            (0xFFU)
10387 #define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT           (0U)
10388 /*! IDRATIOA_H - IDRATIOA_H */
10389 #define ASRC_ASRIDRHA_IDRATIOA_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK)
10390 /*! @} */
10391 
10392 /*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */
10393 /*! @{ */
10394 
10395 #define ASRC_ASRIDRLA_IDRATIOA_L_MASK            (0xFFFFFFU)
10396 #define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT           (0U)
10397 /*! IDRATIOA_L - IDRATIOA_L */
10398 #define ASRC_ASRIDRLA_IDRATIOA_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK)
10399 /*! @} */
10400 
10401 /*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */
10402 /*! @{ */
10403 
10404 #define ASRC_ASRIDRHB_IDRATIOB_H_MASK            (0xFFU)
10405 #define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT           (0U)
10406 /*! IDRATIOB_H - IDRATIOB_H */
10407 #define ASRC_ASRIDRHB_IDRATIOB_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK)
10408 /*! @} */
10409 
10410 /*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */
10411 /*! @{ */
10412 
10413 #define ASRC_ASRIDRLB_IDRATIOB_L_MASK            (0xFFFFFFU)
10414 #define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT           (0U)
10415 /*! IDRATIOB_L - IDRATIOB_L */
10416 #define ASRC_ASRIDRLB_IDRATIOB_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK)
10417 /*! @} */
10418 
10419 /*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */
10420 /*! @{ */
10421 
10422 #define ASRC_ASRIDRHC_IDRATIOC_H_MASK            (0xFFU)
10423 #define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT           (0U)
10424 /*! IDRATIOC_H - IDRATIOC_H */
10425 #define ASRC_ASRIDRHC_IDRATIOC_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK)
10426 /*! @} */
10427 
10428 /*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */
10429 /*! @{ */
10430 
10431 #define ASRC_ASRIDRLC_IDRATIOC_L_MASK            (0xFFFFFFU)
10432 #define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT           (0U)
10433 /*! IDRATIOC_L - IDRATIOC_L */
10434 #define ASRC_ASRIDRLC_IDRATIOC_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK)
10435 /*! @} */
10436 
10437 /*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */
10438 /*! @{ */
10439 
10440 #define ASRC_ASR76K_ASR76K_MASK                  (0x1FFFFU)
10441 #define ASRC_ASR76K_ASR76K_SHIFT                 (0U)
10442 /*! ASR76K - ASR76K */
10443 #define ASRC_ASR76K_ASR76K(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK)
10444 /*! @} */
10445 
10446 /*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */
10447 /*! @{ */
10448 
10449 #define ASRC_ASR56K_ASR56K_MASK                  (0x1FFFFU)
10450 #define ASRC_ASR56K_ASR56K_SHIFT                 (0U)
10451 /*! ASR56K - ASR56K */
10452 #define ASRC_ASR56K_ASR56K(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK)
10453 /*! @} */
10454 
10455 /*! @name ASRMCRA - ASRC Misc Control Register for Pair A */
10456 /*! @{ */
10457 
10458 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK      (0x3FU)
10459 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT     (0U)
10460 /*! INFIFO_THRESHOLDA - INFIFO_THRESHOLDA */
10461 #define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
10462 
10463 #define ASRC_ASRMCRA_RSYNOFA_MASK                (0x400U)
10464 #define ASRC_ASRMCRA_RSYNOFA_SHIFT               (10U)
10465 /*! RSYNOFA - RSYNOFA
10466  *  0b1..Force ASRCCR[ACOA]=0
10467  *  0b0..Do not touch ASRCCR[ACOA]
10468  */
10469 #define ASRC_ASRMCRA_RSYNOFA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK)
10470 
10471 #define ASRC_ASRMCRA_RSYNIFA_MASK                (0x800U)
10472 #define ASRC_ASRMCRA_RSYNIFA_SHIFT               (11U)
10473 /*! RSYNIFA - RSYNIFA
10474  *  0b1..Force ASRCCR[ACIA]=0
10475  *  0b0..Do not touch ASRCCR[ACIA]
10476  */
10477 #define ASRC_ASRMCRA_RSYNIFA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK)
10478 
10479 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK     (0x3F000U)
10480 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT    (12U)
10481 /*! OUTFIFO_THRESHOLDA - OUTFIFO_THRESHOLDA */
10482 #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
10483 
10484 #define ASRC_ASRMCRA_BYPASSPOLYA_MASK            (0x100000U)
10485 #define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT           (20U)
10486 /*! BYPASSPOLYA - BYPASSPOLYA
10487  *  0b1..Bypass polyphase filtering.
10488  *  0b0..Don't bypass polyphase filtering.
10489  */
10490 #define ASRC_ASRMCRA_BYPASSPOLYA(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK)
10491 
10492 #define ASRC_ASRMCRA_BUFSTALLA_MASK              (0x200000U)
10493 #define ASRC_ASRMCRA_BUFSTALLA_SHIFT             (21U)
10494 /*! BUFSTALLA - BUFSTALLA
10495  *  0b1..Stall Pair A conversion in case of near empty/full FIFO conditions.
10496  *  0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions.
10497  */
10498 #define ASRC_ASRMCRA_BUFSTALLA(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK)
10499 
10500 #define ASRC_ASRMCRA_EXTTHRSHA_MASK              (0x400000U)
10501 #define ASRC_ASRMCRA_EXTTHRSHA_SHIFT             (22U)
10502 /*! EXTTHRSHA - EXTTHRSHA
10503  *  0b1..Use external defined thresholds.
10504  *  0b0..Use default thresholds.
10505  */
10506 #define ASRC_ASRMCRA_EXTTHRSHA(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK)
10507 
10508 #define ASRC_ASRMCRA_ZEROBUFA_MASK               (0x800000U)
10509 #define ASRC_ASRMCRA_ZEROBUFA_SHIFT              (23U)
10510 /*! ZEROBUFA - ZEROBUFA
10511  *  0b1..Don't zeroize the buffer
10512  *  0b0..Zeroize the buffer
10513  */
10514 #define ASRC_ASRMCRA_ZEROBUFA(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK)
10515 /*! @} */
10516 
10517 /*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */
10518 /*! @{ */
10519 
10520 #define ASRC_ASRFSTA_INFIFO_FILLA_MASK           (0x7FU)
10521 #define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT          (0U)
10522 /*! INFIFO_FILLA - INFIFO_FILLA */
10523 #define ASRC_ASRFSTA_INFIFO_FILLA(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK)
10524 
10525 #define ASRC_ASRFSTA_IAEA_MASK                   (0x800U)
10526 #define ASRC_ASRFSTA_IAEA_SHIFT                  (11U)
10527 /*! IAEA - IAEA
10528  *  0b1..Input FIFO is near empty for Pair A
10529  *  0b0..Input FIFO is not near empty for Pair A
10530  */
10531 #define ASRC_ASRFSTA_IAEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK)
10532 
10533 #define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK          (0x7F000U)
10534 #define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT         (12U)
10535 /*! OUTFIFO_FILLA - OUTFIFO_FILLA */
10536 #define ASRC_ASRFSTA_OUTFIFO_FILLA(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
10537 
10538 #define ASRC_ASRFSTA_OAFA_MASK                   (0x800000U)
10539 #define ASRC_ASRFSTA_OAFA_SHIFT                  (23U)
10540 /*! OAFA - OAFA
10541  *  0b1..Output FIFO is near full for Pair A
10542  *  0b0..Output FIFO is not near full for Pair A
10543  */
10544 #define ASRC_ASRFSTA_OAFA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK)
10545 /*! @} */
10546 
10547 /*! @name ASRMCRB - ASRC Misc Control Register for Pair B */
10548 /*! @{ */
10549 
10550 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK      (0x3FU)
10551 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT     (0U)
10552 /*! INFIFO_THRESHOLDB - INFIFO_THRESHOLDB */
10553 #define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
10554 
10555 #define ASRC_ASRMCRB_RSYNOFB_MASK                (0x400U)
10556 #define ASRC_ASRMCRB_RSYNOFB_SHIFT               (10U)
10557 /*! RSYNOFB - RSYNOFB
10558  *  0b1..Force ASRCCR[ACOB]=0
10559  *  0b0..Do not touch ASRCCR[ACOB]
10560  */
10561 #define ASRC_ASRMCRB_RSYNOFB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK)
10562 
10563 #define ASRC_ASRMCRB_RSYNIFB_MASK                (0x800U)
10564 #define ASRC_ASRMCRB_RSYNIFB_SHIFT               (11U)
10565 /*! RSYNIFB - RSYNIFB
10566  *  0b1..Force ASRCCR[ACIB]=0
10567  *  0b0..Do not touch ASRCCR[ACIB]
10568  */
10569 #define ASRC_ASRMCRB_RSYNIFB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK)
10570 
10571 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK     (0x3F000U)
10572 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT    (12U)
10573 /*! OUTFIFO_THRESHOLDB - OUTFIFO_THRESHOLDB */
10574 #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
10575 
10576 #define ASRC_ASRMCRB_BYPASSPOLYB_MASK            (0x100000U)
10577 #define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT           (20U)
10578 /*! BYPASSPOLYB - BYPASSPOLYB
10579  *  0b1..Bypass polyphase filtering.
10580  *  0b0..Don't bypass polyphase filtering.
10581  */
10582 #define ASRC_ASRMCRB_BYPASSPOLYB(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK)
10583 
10584 #define ASRC_ASRMCRB_BUFSTALLB_MASK              (0x200000U)
10585 #define ASRC_ASRMCRB_BUFSTALLB_SHIFT             (21U)
10586 /*! BUFSTALLB - BUFSTALLB
10587  *  0b1..Stall Pair B conversion in case of near empty/full FIFO conditions.
10588  *  0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions.
10589  */
10590 #define ASRC_ASRMCRB_BUFSTALLB(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK)
10591 
10592 #define ASRC_ASRMCRB_EXTTHRSHB_MASK              (0x400000U)
10593 #define ASRC_ASRMCRB_EXTTHRSHB_SHIFT             (22U)
10594 /*! EXTTHRSHB - EXTTHRSHB
10595  *  0b1..Use external defined thresholds.
10596  *  0b0..Use default thresholds.
10597  */
10598 #define ASRC_ASRMCRB_EXTTHRSHB(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK)
10599 
10600 #define ASRC_ASRMCRB_ZEROBUFB_MASK               (0x800000U)
10601 #define ASRC_ASRMCRB_ZEROBUFB_SHIFT              (23U)
10602 /*! ZEROBUFB - ZEROBUFB
10603  *  0b1..Don't zeroize the buffer
10604  *  0b0..Zeroize the buffer
10605  */
10606 #define ASRC_ASRMCRB_ZEROBUFB(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK)
10607 /*! @} */
10608 
10609 /*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */
10610 /*! @{ */
10611 
10612 #define ASRC_ASRFSTB_INFIFO_FILLB_MASK           (0x7FU)
10613 #define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT          (0U)
10614 /*! INFIFO_FILLB - INFIFO_FILLB */
10615 #define ASRC_ASRFSTB_INFIFO_FILLB(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK)
10616 
10617 #define ASRC_ASRFSTB_IAEB_MASK                   (0x800U)
10618 #define ASRC_ASRFSTB_IAEB_SHIFT                  (11U)
10619 /*! IAEB - IAEB
10620  *  0b1..Input FIFO is near empty for Pair B
10621  *  0b0..Input FIFO is not near empty for Pair B
10622  */
10623 #define ASRC_ASRFSTB_IAEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK)
10624 
10625 #define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK          (0x7F000U)
10626 #define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT         (12U)
10627 /*! OUTFIFO_FILLB - OUTFIFO_FILLB */
10628 #define ASRC_ASRFSTB_OUTFIFO_FILLB(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
10629 
10630 #define ASRC_ASRFSTB_OAFB_MASK                   (0x800000U)
10631 #define ASRC_ASRFSTB_OAFB_SHIFT                  (23U)
10632 /*! OAFB - OAFB
10633  *  0b1..Output FIFO is near full for Pair B
10634  *  0b0..Output FIFO is not near full for Pair B
10635  */
10636 #define ASRC_ASRFSTB_OAFB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK)
10637 /*! @} */
10638 
10639 /*! @name ASRMCRC - ASRC Misc Control Register for Pair C */
10640 /*! @{ */
10641 
10642 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK      (0x3FU)
10643 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT     (0U)
10644 /*! INFIFO_THRESHOLDC - INFIFO_THRESHOLDC */
10645 #define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
10646 
10647 #define ASRC_ASRMCRC_RSYNOFC_MASK                (0x400U)
10648 #define ASRC_ASRMCRC_RSYNOFC_SHIFT               (10U)
10649 /*! RSYNOFC - RSYNOFC
10650  *  0b1..Force ASRCCR[ACOC]=0
10651  *  0b0..Do not touch ASRCCR[ACOC]
10652  */
10653 #define ASRC_ASRMCRC_RSYNOFC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK)
10654 
10655 #define ASRC_ASRMCRC_RSYNIFC_MASK                (0x800U)
10656 #define ASRC_ASRMCRC_RSYNIFC_SHIFT               (11U)
10657 /*! RSYNIFC - RSYNIFC
10658  *  0b1..Force ASRCCR[ACIC]=0
10659  *  0b0..Do not touch ASRCCR[ACIC]
10660  */
10661 #define ASRC_ASRMCRC_RSYNIFC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK)
10662 
10663 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK     (0x3F000U)
10664 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT    (12U)
10665 /*! OUTFIFO_THRESHOLDC - OUTFIFO_THRESHOLDC */
10666 #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
10667 
10668 #define ASRC_ASRMCRC_BYPASSPOLYC_MASK            (0x100000U)
10669 #define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT           (20U)
10670 /*! BYPASSPOLYC - BYPASSPOLYC
10671  *  0b1..Bypass polyphase filtering.
10672  *  0b0..Don't bypass polyphase filtering.
10673  */
10674 #define ASRC_ASRMCRC_BYPASSPOLYC(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK)
10675 
10676 #define ASRC_ASRMCRC_BUFSTALLC_MASK              (0x200000U)
10677 #define ASRC_ASRMCRC_BUFSTALLC_SHIFT             (21U)
10678 /*! BUFSTALLC - BUFSTALLC
10679  *  0b1..Stall Pair C conversion in case of near empty/full FIFO conditions.
10680  *  0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions.
10681  */
10682 #define ASRC_ASRMCRC_BUFSTALLC(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK)
10683 
10684 #define ASRC_ASRMCRC_EXTTHRSHC_MASK              (0x400000U)
10685 #define ASRC_ASRMCRC_EXTTHRSHC_SHIFT             (22U)
10686 /*! EXTTHRSHC - EXTTHRSHC
10687  *  0b1..Use external defined thresholds.
10688  *  0b0..Use default thresholds.
10689  */
10690 #define ASRC_ASRMCRC_EXTTHRSHC(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK)
10691 
10692 #define ASRC_ASRMCRC_ZEROBUFC_MASK               (0x800000U)
10693 #define ASRC_ASRMCRC_ZEROBUFC_SHIFT              (23U)
10694 /*! ZEROBUFC - ZEROBUFC
10695  *  0b1..Don't zeroize the buffer
10696  *  0b0..Zeroize the buffer
10697  */
10698 #define ASRC_ASRMCRC_ZEROBUFC(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK)
10699 /*! @} */
10700 
10701 /*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */
10702 /*! @{ */
10703 
10704 #define ASRC_ASRFSTC_INFIFO_FILLC_MASK           (0x7FU)
10705 #define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT          (0U)
10706 /*! INFIFO_FILLC - INFIFO_FILLC */
10707 #define ASRC_ASRFSTC_INFIFO_FILLC(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK)
10708 
10709 #define ASRC_ASRFSTC_IAEC_MASK                   (0x800U)
10710 #define ASRC_ASRFSTC_IAEC_SHIFT                  (11U)
10711 /*! IAEC - IAEC
10712  *  0b1..Input FIFO is near empty for Pair C
10713  *  0b0..Input FIFO is not near empty for Pair C
10714  */
10715 #define ASRC_ASRFSTC_IAEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK)
10716 
10717 #define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK          (0x7F000U)
10718 #define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT         (12U)
10719 /*! OUTFIFO_FILLC - OUTFIFO_FILLC */
10720 #define ASRC_ASRFSTC_OUTFIFO_FILLC(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
10721 
10722 #define ASRC_ASRFSTC_OAFC_MASK                   (0x800000U)
10723 #define ASRC_ASRFSTC_OAFC_SHIFT                  (23U)
10724 /*! OAFC - OAFC
10725  *  0b1..Output FIFO is near full for Pair C
10726  *  0b0..Output FIFO is not near full for Pair C
10727  */
10728 #define ASRC_ASRFSTC_OAFC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK)
10729 /*! @} */
10730 
10731 /*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */
10732 /*! @{ */
10733 
10734 #define ASRC_ASRMCR1_OW16_MASK                   (0x1U)
10735 #define ASRC_ASRMCR1_OW16_SHIFT                  (0U)
10736 /*! OW16 - OW16
10737  *  0b1..16-bit output data
10738  *  0b0..24-bit output data.
10739  */
10740 #define ASRC_ASRMCR1_OW16(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK)
10741 
10742 #define ASRC_ASRMCR1_OSGN_MASK                   (0x2U)
10743 #define ASRC_ASRMCR1_OSGN_SHIFT                  (1U)
10744 /*! OSGN - OSGN
10745  *  0b1..Sign extension.
10746  *  0b0..No sign extension.
10747  */
10748 #define ASRC_ASRMCR1_OSGN(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK)
10749 
10750 #define ASRC_ASRMCR1_OMSB_MASK                   (0x4U)
10751 #define ASRC_ASRMCR1_OMSB_SHIFT                  (2U)
10752 /*! OMSB - OMSB
10753  *  0b1..MSB aligned.
10754  *  0b0..LSB aligned.
10755  */
10756 #define ASRC_ASRMCR1_OMSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK)
10757 
10758 #define ASRC_ASRMCR1_IMSB_MASK                   (0x100U)
10759 #define ASRC_ASRMCR1_IMSB_SHIFT                  (8U)
10760 /*! IMSB - IMSB
10761  *  0b1..MSB aligned.
10762  *  0b0..LSB aligned.
10763  */
10764 #define ASRC_ASRMCR1_IMSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK)
10765 
10766 #define ASRC_ASRMCR1_IWD_MASK                    (0x600U)
10767 #define ASRC_ASRMCR1_IWD_SHIFT                   (9U)
10768 /*! IWD - IWD
10769  *  0b00..24-bit audio data.
10770  *  0b01..16-bit audio data.
10771  *  0b10..8-bit audio data.
10772  *  0b11..Reserved.
10773  */
10774 #define ASRC_ASRMCR1_IWD(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK)
10775 /*! @} */
10776 
10777 /* The count of ASRC_ASRMCR1 */
10778 #define ASRC_ASRMCR1_COUNT                       (3U)
10779 
10780 
10781 /*!
10782  * @}
10783  */ /* end of group ASRC_Register_Masks */
10784 
10785 
10786 /* ASRC - Peripheral instance base addresses */
10787 /** Peripheral ASRC base address */
10788 #define ASRC_BASE                                (0x40414000u)
10789 /** Peripheral ASRC base pointer */
10790 #define ASRC                                     ((ASRC_Type *)ASRC_BASE)
10791 /** Array initializer of ASRC peripheral base addresses */
10792 #define ASRC_BASE_ADDRS                          { ASRC_BASE }
10793 /** Array initializer of ASRC peripheral base pointers */
10794 #define ASRC_BASE_PTRS                           { ASRC }
10795 /** Interrupt vectors for the ASRC peripheral type */
10796 #define ASRC_IRQS                                { ASRC_IRQn }
10797 
10798 /*!
10799  * @}
10800  */ /* end of group ASRC_Peripheral_Access_Layer */
10801 
10802 
10803 /* ----------------------------------------------------------------------------
10804    -- AUDIO_PLL Peripheral Access Layer
10805    ---------------------------------------------------------------------------- */
10806 
10807 /*!
10808  * @addtogroup AUDIO_PLL_Peripheral_Access_Layer AUDIO_PLL Peripheral Access Layer
10809  * @{
10810  */
10811 
10812 /** AUDIO_PLL - Register Layout Typedef */
10813 typedef struct {
10814   struct {                                         /* offset: 0x0 */
10815     __IO uint32_t RW;                                /**< Fractional PLL Control Register, offset: 0x0 */
10816     __IO uint32_t SET;                               /**< Fractional PLL Control Register, offset: 0x4 */
10817     __IO uint32_t CLR;                               /**< Fractional PLL Control Register, offset: 0x8 */
10818     __IO uint32_t TOG;                               /**< Fractional PLL Control Register, offset: 0xC */
10819   } CTRL0;
10820   struct {                                         /* offset: 0x10 */
10821     __IO uint32_t RW;                                /**< Fractional PLL Spread Spectrum Control Register, offset: 0x10 */
10822     __IO uint32_t SET;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x14 */
10823     __IO uint32_t CLR;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x18 */
10824     __IO uint32_t TOG;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x1C */
10825   } SPREAD_SPECTRUM;
10826   struct {                                         /* offset: 0x20 */
10827     __IO uint32_t RW;                                /**< Fractional PLL Numerator Control Register, offset: 0x20 */
10828     __IO uint32_t SET;                               /**< Fractional PLL Numerator Control Register, offset: 0x24 */
10829     __IO uint32_t CLR;                               /**< Fractional PLL Numerator Control Register, offset: 0x28 */
10830     __IO uint32_t TOG;                               /**< Fractional PLL Numerator Control Register, offset: 0x2C */
10831   } NUMERATOR;
10832   struct {                                         /* offset: 0x30 */
10833     __IO uint32_t RW;                                /**< Fractional PLL Denominator Control Register, offset: 0x30 */
10834     __IO uint32_t SET;                               /**< Fractional PLL Denominator Control Register, offset: 0x34 */
10835     __IO uint32_t CLR;                               /**< Fractional PLL Denominator Control Register, offset: 0x38 */
10836     __IO uint32_t TOG;                               /**< Fractional PLL Denominator Control Register, offset: 0x3C */
10837   } DENOMINATOR;
10838 } AUDIO_PLL_Type;
10839 
10840 /* ----------------------------------------------------------------------------
10841    -- AUDIO_PLL Register Masks
10842    ---------------------------------------------------------------------------- */
10843 
10844 /*!
10845  * @addtogroup AUDIO_PLL_Register_Masks AUDIO_PLL Register Masks
10846  * @{
10847  */
10848 
10849 /*! @name CTRL0 - Fractional PLL Control Register */
10850 /*! @{ */
10851 
10852 #define AUDIO_PLL_CTRL0_DIV_SELECT_MASK          (0x7FU)
10853 #define AUDIO_PLL_CTRL0_DIV_SELECT_SHIFT         (0U)
10854 /*! DIV_SELECT - DIV_SELECT */
10855 #define AUDIO_PLL_CTRL0_DIV_SELECT(x)            (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DIV_SELECT_SHIFT)) & AUDIO_PLL_CTRL0_DIV_SELECT_MASK)
10856 
10857 #define AUDIO_PLL_CTRL0_ENABLE_ALT_MASK          (0x100U)
10858 #define AUDIO_PLL_CTRL0_ENABLE_ALT_SHIFT         (8U)
10859 /*! ENABLE_ALT - ENABLE_ALT
10860  *  0b0..Disable the alternate clock output
10861  *  0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed
10862  */
10863 #define AUDIO_PLL_CTRL0_ENABLE_ALT(x)            (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_ENABLE_ALT_SHIFT)) & AUDIO_PLL_CTRL0_ENABLE_ALT_MASK)
10864 
10865 #define AUDIO_PLL_CTRL0_HOLD_RING_OFF_MASK       (0x2000U)
10866 #define AUDIO_PLL_CTRL0_HOLD_RING_OFF_SHIFT      (13U)
10867 /*! HOLD_RING_OFF - PLL Start up initialization
10868  *  0b0..Normal operation
10869  *  0b1..Initialize PLL start up
10870  */
10871 #define AUDIO_PLL_CTRL0_HOLD_RING_OFF(x)         (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & AUDIO_PLL_CTRL0_HOLD_RING_OFF_MASK)
10872 
10873 #define AUDIO_PLL_CTRL0_POWERUP_MASK             (0x4000U)
10874 #define AUDIO_PLL_CTRL0_POWERUP_SHIFT            (14U)
10875 /*! POWERUP - POWERUP
10876  *  0b1..Power Up the PLL
10877  *  0b0..Power down the PLL
10878  */
10879 #define AUDIO_PLL_CTRL0_POWERUP(x)               (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POWERUP_SHIFT)) & AUDIO_PLL_CTRL0_POWERUP_MASK)
10880 
10881 #define AUDIO_PLL_CTRL0_ENABLE_MASK              (0x8000U)
10882 #define AUDIO_PLL_CTRL0_ENABLE_SHIFT             (15U)
10883 /*! ENABLE - ENABLE
10884  *  0b1..Enable the clock output
10885  *  0b0..Disable the clock output
10886  */
10887 #define AUDIO_PLL_CTRL0_ENABLE(x)                (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_ENABLE_SHIFT)) & AUDIO_PLL_CTRL0_ENABLE_MASK)
10888 
10889 #define AUDIO_PLL_CTRL0_BYPASS_MASK              (0x10000U)
10890 #define AUDIO_PLL_CTRL0_BYPASS_SHIFT             (16U)
10891 /*! BYPASS - BYPASS
10892  *  0b1..Bypass the PLL
10893  *  0b0..No Bypass
10894  */
10895 #define AUDIO_PLL_CTRL0_BYPASS(x)                (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BYPASS_SHIFT)) & AUDIO_PLL_CTRL0_BYPASS_MASK)
10896 
10897 #define AUDIO_PLL_CTRL0_DITHER_EN_MASK           (0x20000U)
10898 #define AUDIO_PLL_CTRL0_DITHER_EN_SHIFT          (17U)
10899 /*! DITHER_EN - DITHER_EN
10900  *  0b0..Disable Dither
10901  *  0b1..Enable Dither
10902  */
10903 #define AUDIO_PLL_CTRL0_DITHER_EN(x)             (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DITHER_EN_SHIFT)) & AUDIO_PLL_CTRL0_DITHER_EN_MASK)
10904 
10905 #define AUDIO_PLL_CTRL0_BIAS_TRIM_MASK           (0x380000U)
10906 #define AUDIO_PLL_CTRL0_BIAS_TRIM_SHIFT          (19U)
10907 /*! BIAS_TRIM - BIAS_TRIM */
10908 #define AUDIO_PLL_CTRL0_BIAS_TRIM(x)             (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BIAS_TRIM_SHIFT)) & AUDIO_PLL_CTRL0_BIAS_TRIM_MASK)
10909 
10910 #define AUDIO_PLL_CTRL0_PLL_REG_EN_MASK          (0x400000U)
10911 #define AUDIO_PLL_CTRL0_PLL_REG_EN_SHIFT         (22U)
10912 /*! PLL_REG_EN - PLL_REG_EN */
10913 #define AUDIO_PLL_CTRL0_PLL_REG_EN(x)            (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_PLL_REG_EN_SHIFT)) & AUDIO_PLL_CTRL0_PLL_REG_EN_MASK)
10914 
10915 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK        (0xE000000U)
10916 #define AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT       (25U)
10917 /*! POST_DIV_SEL - Post Divide Select
10918  *  0b000..Divide by 1
10919  *  0b001..Divide by 2
10920  *  0b010..Divide by 4
10921  *  0b011..Divide by 8
10922  *  0b100..Divide by 16
10923  *  0b101..Divide by 32
10924  */
10925 #define AUDIO_PLL_CTRL0_POST_DIV_SEL(x)          (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
10926 
10927 #define AUDIO_PLL_CTRL0_BIAS_SELECT_MASK         (0x20000000U)
10928 #define AUDIO_PLL_CTRL0_BIAS_SELECT_SHIFT        (29U)
10929 /*! BIAS_SELECT - BIAS_SELECT
10930  *  0b0..Used in SoCs with a bias current of 10uA
10931  *  0b1..Used in SoCs with a bias current of 2uA
10932  */
10933 #define AUDIO_PLL_CTRL0_BIAS_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BIAS_SELECT_SHIFT)) & AUDIO_PLL_CTRL0_BIAS_SELECT_MASK)
10934 /*! @} */
10935 
10936 /*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */
10937 /*! @{ */
10938 
10939 #define AUDIO_PLL_SPREAD_SPECTRUM_STEP_MASK      (0x7FFFU)
10940 #define AUDIO_PLL_SPREAD_SPECTRUM_STEP_SHIFT     (0U)
10941 /*! STEP - Step */
10942 #define AUDIO_PLL_SPREAD_SPECTRUM_STEP(x)        (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_STEP_MASK)
10943 
10944 #define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK    (0x8000U)
10945 #define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT   (15U)
10946 /*! ENABLE - Enable */
10947 #define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK)
10948 
10949 #define AUDIO_PLL_SPREAD_SPECTRUM_STOP_MASK      (0xFFFF0000U)
10950 #define AUDIO_PLL_SPREAD_SPECTRUM_STOP_SHIFT     (16U)
10951 /*! STOP - Stop */
10952 #define AUDIO_PLL_SPREAD_SPECTRUM_STOP(x)        (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_STOP_MASK)
10953 /*! @} */
10954 
10955 /*! @name NUMERATOR - Fractional PLL Numerator Control Register */
10956 /*! @{ */
10957 
10958 #define AUDIO_PLL_NUMERATOR_NUM_MASK             (0x3FFFFFFFU)
10959 #define AUDIO_PLL_NUMERATOR_NUM_SHIFT            (0U)
10960 /*! NUM - Numerator */
10961 #define AUDIO_PLL_NUMERATOR_NUM(x)               (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_NUMERATOR_NUM_SHIFT)) & AUDIO_PLL_NUMERATOR_NUM_MASK)
10962 /*! @} */
10963 
10964 /*! @name DENOMINATOR - Fractional PLL Denominator Control Register */
10965 /*! @{ */
10966 
10967 #define AUDIO_PLL_DENOMINATOR_DENOM_MASK         (0x3FFFFFFFU)
10968 #define AUDIO_PLL_DENOMINATOR_DENOM_SHIFT        (0U)
10969 /*! DENOM - Denominator */
10970 #define AUDIO_PLL_DENOMINATOR_DENOM(x)           (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_DENOMINATOR_DENOM_SHIFT)) & AUDIO_PLL_DENOMINATOR_DENOM_MASK)
10971 /*! @} */
10972 
10973 
10974 /*!
10975  * @}
10976  */ /* end of group AUDIO_PLL_Register_Masks */
10977 
10978 
10979 /* AUDIO_PLL - Peripheral instance base addresses */
10980 /** Peripheral AUDIO_PLL base address */
10981 #define AUDIO_PLL_BASE                           (0u)
10982 /** Peripheral AUDIO_PLL base pointer */
10983 #define AUDIO_PLL                                ((AUDIO_PLL_Type *)AUDIO_PLL_BASE)
10984 /** Array initializer of AUDIO_PLL peripheral base addresses */
10985 #define AUDIO_PLL_BASE_ADDRS                     { AUDIO_PLL_BASE }
10986 /** Array initializer of AUDIO_PLL peripheral base pointers */
10987 #define AUDIO_PLL_BASE_PTRS                      { AUDIO_PLL }
10988 
10989 /*!
10990  * @}
10991  */ /* end of group AUDIO_PLL_Peripheral_Access_Layer */
10992 
10993 
10994 /* ----------------------------------------------------------------------------
10995    -- CAAM Peripheral Access Layer
10996    ---------------------------------------------------------------------------- */
10997 
10998 /*!
10999  * @addtogroup CAAM_Peripheral_Access_Layer CAAM Peripheral Access Layer
11000  * @{
11001  */
11002 
11003 /** CAAM - Register Layout Typedef */
11004 typedef struct {
11005        uint8_t RESERVED_0[4];
11006   __IO uint32_t MCFGR;                             /**< Master Configuration Register, offset: 0x4 */
11007   __IO uint32_t PAGE0_SDID;                        /**< Page 0 SDID Register, offset: 0x8 */
11008   __IO uint32_t SCFGR;                             /**< Security Configuration Register, offset: 0xC */
11009   struct {                                         /* offset: 0x10, array step: 0x8 */
11010     __IO uint32_t JRDID_MS;                          /**< Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half, array offset: 0x10, array step: 0x8 */
11011     __IO uint32_t JRDID_LS;                          /**< Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half, array offset: 0x14, array step: 0x8 */
11012   } JRADID[4];
11013        uint8_t RESERVED_1[40];
11014   __IO uint32_t DEBUGCTL;                          /**< Debug Control Register, offset: 0x58 */
11015   __IO uint32_t JRSTARTR;                          /**< Job Ring Start Register, offset: 0x5C */
11016   __IO uint32_t RTIC_OWN;                          /**< RTIC OWN Register, offset: 0x60 */
11017   struct {                                         /* offset: 0x64, array step: 0x8 */
11018     __IO uint32_t RTIC_DID;                          /**< RTIC DID Register for Block A..RTIC DID Register for Block D, array offset: 0x64, array step: 0x8 */
11019          uint8_t RESERVED_0[4];
11020   } RTICADID[4];
11021        uint8_t RESERVED_2[16];
11022   __IO uint32_t DECORSR;                           /**< DECO Request Source Register, offset: 0x94 */
11023        uint8_t RESERVED_3[4];
11024   __IO uint32_t DECORR;                            /**< DECO Request Register, offset: 0x9C */
11025   struct {                                         /* offset: 0xA0, array step: 0x8 */
11026     __IO uint32_t DECODID_MS;                        /**< DECO0 DID Register - most significant half, array offset: 0xA0, array step: 0x8 */
11027     __IO uint32_t DECODID_LS;                        /**< DECO0 DID Register - least significant half, array offset: 0xA4, array step: 0x8 */
11028   } DECONDID[1];
11029        uint8_t RESERVED_4[120];
11030   __IO uint32_t DAR;                               /**< DECO Availability Register, offset: 0x120 */
11031   __O  uint32_t DRR;                               /**< DECO Reset Register, offset: 0x124 */
11032        uint8_t RESERVED_5[92];
11033   struct {                                         /* offset: 0x184, array step: 0x8 */
11034     __IO uint32_t JRSMVBAR;                          /**< Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register, array offset: 0x184, array step: 0x8 */
11035          uint8_t RESERVED_0[4];
11036   } JRNSMVBAR[4];
11037        uint8_t RESERVED_6[124];
11038   __IO uint32_t PBSL;                              /**< Peak Bandwidth Smoothing Limit Register, offset: 0x220 */
11039        uint8_t RESERVED_7[28];
11040   struct {                                         /* offset: 0x240, array step: 0x10 */
11041     __I  uint32_t DMA_AIDL_MAP_MS;                   /**< DMA0_AIDL_MAP_MS, array offset: 0x240, array step: 0x10 */
11042     __I  uint32_t DMA_AIDL_MAP_LS;                   /**< DMA0_AIDL_MAP_LS, array offset: 0x244, array step: 0x10 */
11043     __I  uint32_t DMA_AIDM_MAP_MS;                   /**< DMA0_AIDM_MAP_MS, array offset: 0x248, array step: 0x10 */
11044     __I  uint32_t DMA_AIDM_MAP_LS;                   /**< DMA0_AIDM_MAP_LS, array offset: 0x24C, array step: 0x10 */
11045   } AID_CNTS[1];
11046   __I  uint32_t DMA0_AID_ENB;                      /**< DMA0 AXI ID Enable Register, offset: 0x250 */
11047        uint8_t RESERVED_8[12];
11048   __IO uint64_t DMA0_ARD_TC;                       /**< DMA0 AXI Read Timing Check Register, offset: 0x260 */
11049        uint8_t RESERVED_9[4];
11050   __IO uint32_t DMA0_ARD_LAT;                      /**< DMA0 Read Timing Check Latency Register, offset: 0x26C */
11051   __IO uint64_t DMA0_AWR_TC;                       /**< DMA0 AXI Write Timing Check Register, offset: 0x270 */
11052        uint8_t RESERVED_10[4];
11053   __IO uint32_t DMA0_AWR_LAT;                      /**< DMA0 Write Timing Check Latency Register, offset: 0x27C */
11054        uint8_t RESERVED_11[128];
11055   __IO uint8_t MPPKR[64];                          /**< Manufacturing Protection Private Key Register, array offset: 0x300, array step: 0x1 */
11056        uint8_t RESERVED_12[64];
11057   __IO uint8_t MPMR[32];                           /**< Manufacturing Protection Message Register, array offset: 0x380, array step: 0x1 */
11058        uint8_t RESERVED_13[32];
11059   __I  uint8_t MPTESTR[32];                        /**< Manufacturing Protection Test Register, array offset: 0x3C0, array step: 0x1 */
11060        uint8_t RESERVED_14[24];
11061   __I  uint32_t MPECC;                             /**< Manufacturing Protection ECC Register, offset: 0x3F8 */
11062        uint8_t RESERVED_15[4];
11063   __IO uint32_t JDKEKR[8];                         /**< Job Descriptor Key Encryption Key Register, array offset: 0x400, array step: 0x4 */
11064   __IO uint32_t TDKEKR[8];                         /**< Trusted Descriptor Key Encryption Key Register, array offset: 0x420, array step: 0x4 */
11065   __IO uint32_t TDSKR[8];                          /**< Trusted Descriptor Signing Key Register, array offset: 0x440, array step: 0x4 */
11066        uint8_t RESERVED_16[128];
11067   __IO uint64_t SKNR;                              /**< Secure Key Nonce Register, offset: 0x4E0 */
11068        uint8_t RESERVED_17[36];
11069   __I  uint32_t DMA_STA;                           /**< DMA Status Register, offset: 0x50C */
11070   __I  uint32_t DMA_X_AID_7_4_MAP;                 /**< DMA_X_AID_7_4_MAP, offset: 0x510 */
11071   __I  uint32_t DMA_X_AID_3_0_MAP;                 /**< DMA_X_AID_3_0_MAP, offset: 0x514 */
11072   __I  uint32_t DMA_X_AID_15_12_MAP;               /**< DMA_X_AID_15_12_MAP, offset: 0x518 */
11073   __I  uint32_t DMA_X_AID_11_8_MAP;                /**< DMA_X_AID_11_8_MAP, offset: 0x51C */
11074        uint8_t RESERVED_18[4];
11075   __I  uint32_t DMA_X_AID_15_0_EN;                 /**< DMA_X AXI ID Map Enable Register, offset: 0x524 */
11076        uint8_t RESERVED_19[8];
11077   __IO uint32_t DMA_X_ARTC_CTL;                    /**< DMA_X AXI Read Timing Check Control Register, offset: 0x530 */
11078   __IO uint32_t DMA_X_ARTC_LC;                     /**< DMA_X AXI Read Timing Check Late Count Register, offset: 0x534 */
11079   __IO uint32_t DMA_X_ARTC_SC;                     /**< DMA_X AXI Read Timing Check Sample Count Register, offset: 0x538 */
11080   __IO uint32_t DMA_X_ARTC_LAT;                    /**< DMA_X Read Timing Check Latency Register, offset: 0x53C */
11081   __IO uint32_t DMA_X_AWTC_CTL;                    /**< DMA_X AXI Write Timing Check Control Register, offset: 0x540 */
11082   __IO uint32_t DMA_X_AWTC_LC;                     /**< DMA_X AXI Write Timing Check Late Count Register, offset: 0x544 */
11083   __IO uint32_t DMA_X_AWTC_SC;                     /**< DMA_X AXI Write Timing Check Sample Count Register, offset: 0x548 */
11084   __IO uint32_t DMA_X_AWTC_LAT;                    /**< DMA_X Write Timing Check Latency Register, offset: 0x54C */
11085        uint8_t RESERVED_20[176];
11086   __IO uint32_t RTMCTL;                            /**< RNG TRNG Miscellaneous Control Register, offset: 0x600 */
11087   __IO uint32_t RTSCMISC;                          /**< RNG TRNG Statistical Check Miscellaneous Register, offset: 0x604 */
11088   __IO uint32_t RTPKRRNG;                          /**< RNG TRNG Poker Range Register, offset: 0x608 */
11089   union {                                          /* offset: 0x60C */
11090     __IO uint32_t RTPKRMAX;                          /**< RNG TRNG Poker Maximum Limit Register, offset: 0x60C */
11091     __I  uint32_t RTPKRSQ;                           /**< RNG TRNG Poker Square Calculation Result Register, offset: 0x60C */
11092   };
11093   __IO uint32_t RTSDCTL;                           /**< RNG TRNG Seed Control Register, offset: 0x610 */
11094   union {                                          /* offset: 0x614 */
11095     __IO uint32_t RTSBLIM;                           /**< RNG TRNG Sparse Bit Limit Register, offset: 0x614 */
11096     __I  uint32_t RTTOTSAM;                          /**< RNG TRNG Total Samples Register, offset: 0x614 */
11097   };
11098   __IO uint32_t RTFRQMIN;                          /**< RNG TRNG Frequency Count Minimum Limit Register, offset: 0x618 */
11099   union {                                          /* offset: 0x61C */
11100     struct {                                         /* offset: 0x61C */
11101       __I  uint32_t RTFRQCNT;                          /**< RNG TRNG Frequency Count Register, offset: 0x61C */
11102       __I  uint32_t RTSCMC;                            /**< RNG TRNG Statistical Check Monobit Count Register, offset: 0x620 */
11103       __I  uint32_t RTSCR1C;                           /**< RNG TRNG Statistical Check Run Length 1 Count Register, offset: 0x624 */
11104       __I  uint32_t RTSCR2C;                           /**< RNG TRNG Statistical Check Run Length 2 Count Register, offset: 0x628 */
11105       __I  uint32_t RTSCR3C;                           /**< RNG TRNG Statistical Check Run Length 3 Count Register, offset: 0x62C */
11106       __I  uint32_t RTSCR4C;                           /**< RNG TRNG Statistical Check Run Length 4 Count Register, offset: 0x630 */
11107       __I  uint32_t RTSCR5C;                           /**< RNG TRNG Statistical Check Run Length 5 Count Register, offset: 0x634 */
11108       __I  uint32_t RTSCR6PC;                          /**< RNG TRNG Statistical Check Run Length 6+ Count Register, offset: 0x638 */
11109     } COUNT;
11110     struct {                                         /* offset: 0x61C */
11111       __IO uint32_t RTFRQMAX;                          /**< RNG TRNG Frequency Count Maximum Limit Register, offset: 0x61C */
11112       __IO uint32_t RTSCML;                            /**< RNG TRNG Statistical Check Monobit Limit Register, offset: 0x620 */
11113       __IO uint32_t RTSCR1L;                           /**< RNG TRNG Statistical Check Run Length 1 Limit Register, offset: 0x624 */
11114       __IO uint32_t RTSCR2L;                           /**< RNG TRNG Statistical Check Run Length 2 Limit Register, offset: 0x628 */
11115       __IO uint32_t RTSCR3L;                           /**< RNG TRNG Statistical Check Run Length 3 Limit Register, offset: 0x62C */
11116       __IO uint32_t RTSCR4L;                           /**< RNG TRNG Statistical Check Run Length 4 Limit Register, offset: 0x630 */
11117       __IO uint32_t RTSCR5L;                           /**< RNG TRNG Statistical Check Run Length 5 Limit Register, offset: 0x634 */
11118       __IO uint32_t RTSCR6PL;                          /**< RNG TRNG Statistical Check Run Length 6+ Limit Register, offset: 0x638 */
11119     } LIMIT;
11120   };
11121   __I  uint32_t RTSTATUS;                          /**< RNG TRNG Status Register, offset: 0x63C */
11122   __I  uint32_t RTENT[16];                         /**< RNG TRNG Entropy Read Register, array offset: 0x640, array step: 0x4 */
11123   __I  uint32_t RTPKRCNT10;                        /**< RNG TRNG Statistical Check Poker Count 1 and 0 Register, offset: 0x680 */
11124   __I  uint32_t RTPKRCNT32;                        /**< RNG TRNG Statistical Check Poker Count 3 and 2 Register, offset: 0x684 */
11125   __I  uint32_t RTPKRCNT54;                        /**< RNG TRNG Statistical Check Poker Count 5 and 4 Register, offset: 0x688 */
11126   __I  uint32_t RTPKRCNT76;                        /**< RNG TRNG Statistical Check Poker Count 7 and 6 Register, offset: 0x68C */
11127   __I  uint32_t RTPKRCNT98;                        /**< RNG TRNG Statistical Check Poker Count 9 and 8 Register, offset: 0x690 */
11128   __I  uint32_t RTPKRCNTBA;                        /**< RNG TRNG Statistical Check Poker Count B and A Register, offset: 0x694 */
11129   __I  uint32_t RTPKRCNTDC;                        /**< RNG TRNG Statistical Check Poker Count D and C Register, offset: 0x698 */
11130   __I  uint32_t RTPKRCNTFE;                        /**< RNG TRNG Statistical Check Poker Count F and E Register, offset: 0x69C */
11131        uint8_t RESERVED_21[32];
11132   __I  uint32_t RDSTA;                             /**< RNG DRNG Status Register, offset: 0x6C0 */
11133        uint8_t RESERVED_22[12];
11134   __I  uint32_t RDINT0;                            /**< RNG DRNG State Handle 0 Reseed Interval Register, offset: 0x6D0 */
11135   __I  uint32_t RDINT1;                            /**< RNG DRNG State Handle 1 Reseed Interval Register, offset: 0x6D4 */
11136        uint8_t RESERVED_23[8];
11137   __IO uint32_t RDHCNTL;                           /**< RNG DRNG Hash Control Register, offset: 0x6E0 */
11138   __I  uint32_t RDHDIG;                            /**< RNG DRNG Hash Digest Register, offset: 0x6E4 */
11139   __O  uint32_t RDHBUF;                            /**< RNG DRNG Hash Buffer Register, offset: 0x6E8 */
11140        uint8_t RESERVED_24[788];
11141   struct {                                         /* offset: 0xA00, array step: 0x10 */
11142     __I  uint32_t PX_SDID_PG0;                       /**< Partition 0 SDID register..Partition 15 SDID register, array offset: 0xA00, array step: 0x10 */
11143     __IO uint32_t PX_SMAPR_PG0;                      /**< Secure Memory Access Permissions register, array offset: 0xA04, array step: 0x10 */
11144     __IO uint32_t PX_SMAG2_PG0;                      /**< Secure Memory Access Group Registers, array offset: 0xA08, array step: 0x10 */
11145     __IO uint32_t PX_SMAG1_PG0;                      /**< Secure Memory Access Group Registers, array offset: 0xA0C, array step: 0x10 */
11146   } PX_PG0[16];
11147   __IO uint32_t REIS;                              /**< Recoverable Error Interrupt Status, offset: 0xB00 */
11148   __IO uint32_t REIE;                              /**< Recoverable Error Interrupt Enable, offset: 0xB04 */
11149   __I  uint32_t REIF;                              /**< Recoverable Error Interrupt Force, offset: 0xB08 */
11150   __IO uint32_t REIH;                              /**< Recoverable Error Interrupt Halt, offset: 0xB0C */
11151        uint8_t RESERVED_25[192];
11152   __IO uint32_t SMWPJRR[4];                        /**< Secure Memory Write Protect Job Ring Register, array offset: 0xBD0, array step: 0x4 */
11153        uint8_t RESERVED_26[4];
11154   __O  uint32_t SMCR_PG0;                          /**< Secure Memory Command Register, offset: 0xBE4 */
11155        uint8_t RESERVED_27[4];
11156   __I  uint32_t SMCSR_PG0;                         /**< Secure Memory Command Status Register, offset: 0xBEC */
11157        uint8_t RESERVED_28[8];
11158   __I  uint32_t CAAMVID_MS_TRAD;                   /**< CAAM Version ID Register, most-significant half, offset: 0xBF8 */
11159   __I  uint32_t CAAMVID_LS_TRAD;                   /**< CAAM Version ID Register, least-significant half, offset: 0xBFC */
11160   struct {                                         /* offset: 0xC00, array step: 0x20 */
11161     __I  uint64_t HT_JD_ADDR;                        /**< Holding Tank 0 Job Descriptor Address, array offset: 0xC00, array step: 0x20 */
11162     __I  uint64_t HT_SD_ADDR;                        /**< Holding Tank 0 Shared Descriptor Address, array offset: 0xC08, array step: 0x20 */
11163     __I  uint32_t HT_JQ_CTRL_MS;                     /**< Holding Tank 0 Job Queue Control, most-significant half, array offset: 0xC10, array step: 0x20 */
11164     __I  uint32_t HT_JQ_CTRL_LS;                     /**< Holding Tank 0 Job Queue Control, least-significant half, array offset: 0xC14, array step: 0x20 */
11165          uint8_t RESERVED_0[4];
11166     __I  uint32_t HT_STATUS;                         /**< Holding Tank Status, array offset: 0xC1C, array step: 0x20 */
11167   } HTA[1];
11168        uint8_t RESERVED_29[4];
11169   __IO uint32_t JQ_DEBUG_SEL;                      /**< Job Queue Debug Select Register, offset: 0xC24 */
11170        uint8_t RESERVED_30[404];
11171   __I  uint32_t JRJIDU_LS;                         /**< Job Ring Job IDs in Use Register, least-significant half, offset: 0xDBC */
11172   __I  uint32_t JRJDJIFBC;                         /**< Job Ring Job-Done Job ID FIFO BC, offset: 0xDC0 */
11173   __I  uint32_t JRJDJIF;                           /**< Job Ring Job-Done Job ID FIFO, offset: 0xDC4 */
11174        uint8_t RESERVED_31[28];
11175   __I  uint32_t JRJDS1;                            /**< Job Ring Job-Done Source 1, offset: 0xDE4 */
11176        uint8_t RESERVED_32[24];
11177   __I  uint64_t JRJDDA[1];                         /**< Job Ring Job-Done Descriptor Address 0 Register, array offset: 0xE00, array step: 0x8 */
11178        uint8_t RESERVED_33[408];
11179   __I  uint32_t CRNR_MS;                           /**< CHA Revision Number Register, most-significant half, offset: 0xFA0 */
11180   __I  uint32_t CRNR_LS;                           /**< CHA Revision Number Register, least-significant half, offset: 0xFA4 */
11181   __I  uint32_t CTPR_MS;                           /**< Compile Time Parameters Register, most-significant half, offset: 0xFA8 */
11182   __I  uint32_t CTPR_LS;                           /**< Compile Time Parameters Register, least-significant half, offset: 0xFAC */
11183        uint8_t RESERVED_34[4];
11184   __I  uint32_t SMSTA;                             /**< Secure Memory Status Register, offset: 0xFB4 */
11185        uint8_t RESERVED_35[4];
11186   __I  uint32_t SMPO;                              /**< Secure Memory Partition Owners Register, offset: 0xFBC */
11187   __I  uint64_t FAR;                               /**< Fault Address Register, offset: 0xFC0 */
11188   __I  uint32_t FADID;                             /**< Fault Address DID Register, offset: 0xFC8 */
11189   __I  uint32_t FADR;                              /**< Fault Address Detail Register, offset: 0xFCC */
11190        uint8_t RESERVED_36[4];
11191   __I  uint32_t CSTA;                              /**< CAAM Status Register, offset: 0xFD4 */
11192   __I  uint32_t SMVID_MS;                          /**< Secure Memory Version ID Register, most-significant half, offset: 0xFD8 */
11193   __I  uint32_t SMVID_LS;                          /**< Secure Memory Version ID Register, least-significant half, offset: 0xFDC */
11194   __I  uint32_t RVID;                              /**< RTIC Version ID Register, offset: 0xFE0 */
11195   __I  uint32_t CCBVID;                            /**< CHA Cluster Block Version ID Register, offset: 0xFE4 */
11196   __I  uint32_t CHAVID_MS;                         /**< CHA Version ID Register, most-significant half, offset: 0xFE8 */
11197   __I  uint32_t CHAVID_LS;                         /**< CHA Version ID Register, least-significant half, offset: 0xFEC */
11198   __I  uint32_t CHANUM_MS;                         /**< CHA Number Register, most-significant half, offset: 0xFF0 */
11199   __I  uint32_t CHANUM_LS;                         /**< CHA Number Register, least-significant half, offset: 0xFF4 */
11200   __I  uint32_t CAAMVID_MS;                        /**< CAAM Version ID Register, most-significant half, offset: 0xFF8 */
11201   __I  uint32_t CAAMVID_LS;                        /**< CAAM Version ID Register, least-significant half, offset: 0xFFC */
11202        uint8_t RESERVED_37[61440];
11203   struct {                                         /* offset: 0x10000, array step: 0x10000 */
11204     __IO uint64_t IRBAR_JR;                          /**< Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3, array offset: 0x10000, array step: 0x10000 */
11205          uint8_t RESERVED_0[4];
11206     __IO uint32_t IRSR_JR;                           /**< Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3, array offset: 0x1000C, array step: 0x10000 */
11207          uint8_t RESERVED_1[4];
11208     __IO uint32_t IRSAR_JR;                          /**< Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3, array offset: 0x10014, array step: 0x10000 */
11209          uint8_t RESERVED_2[4];
11210     __IO uint32_t IRJAR_JR;                          /**< Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3, array offset: 0x1001C, array step: 0x10000 */
11211     __IO uint64_t ORBAR_JR;                          /**< Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3, array offset: 0x10020, array step: 0x10000 */
11212          uint8_t RESERVED_3[4];
11213     __IO uint32_t ORSR_JR;                           /**< Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3, array offset: 0x1002C, array step: 0x10000 */
11214          uint8_t RESERVED_4[4];
11215     __IO uint32_t ORJRR_JR;                          /**< Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3, array offset: 0x10034, array step: 0x10000 */
11216          uint8_t RESERVED_5[4];
11217     __IO uint32_t ORSFR_JR;                          /**< Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3, array offset: 0x1003C, array step: 0x10000 */
11218          uint8_t RESERVED_6[4];
11219     __I  uint32_t JRSTAR_JR;                         /**< Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3, array offset: 0x10044, array step: 0x10000 */
11220          uint8_t RESERVED_7[4];
11221     __IO uint32_t JRINTR_JR;                         /**< Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3, array offset: 0x1004C, array step: 0x10000 */
11222     __IO uint32_t JRCFGR_JR_MS;                      /**< Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half, array offset: 0x10050, array step: 0x10000 */
11223     __IO uint32_t JRCFGR_JR_LS;                      /**< Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half, array offset: 0x10054, array step: 0x10000 */
11224          uint8_t RESERVED_8[4];
11225     __IO uint32_t IRRIR_JR;                          /**< Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3, array offset: 0x1005C, array step: 0x10000 */
11226          uint8_t RESERVED_9[4];
11227     __IO uint32_t ORWIR_JR;                          /**< Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3, array offset: 0x10064, array step: 0x10000 */
11228          uint8_t RESERVED_10[4];
11229     __O  uint32_t JRCR_JR;                           /**< Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3, array offset: 0x1006C, array step: 0x10000 */
11230          uint8_t RESERVED_11[1684];
11231     __I  uint32_t JRAAV;                             /**< Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register, array offset: 0x10704, array step: 0x10000 */
11232          uint8_t RESERVED_12[248];
11233     __I  uint64_t JRAAA[4];                          /**< Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register, array offset: 0x10800, array step: index*0x10000, index2*0x8 */
11234          uint8_t RESERVED_13[480];
11235     struct {                                         /* offset: 0x10A00, array step: index*0x10000, index2*0x10 */
11236       __I  uint32_t PX_SDID_JR;                        /**< Partition 0 SDID register..Partition 15 SDID register, array offset: 0x10A00, array step: index*0x10000, index2*0x10 */
11237       __IO uint32_t PX_SMAPR_JR;                       /**< Secure Memory Access Permissions register, array offset: 0x10A04, array step: index*0x10000, index2*0x10 */
11238       __IO uint32_t PX_SMAG2_JR;                       /**< Secure Memory Access Group Registers, array offset: 0x10A08, array step: index*0x10000, index2*0x10 */
11239       __IO uint32_t PX_SMAG1_JR;                       /**< Secure Memory Access Group Registers, array offset: 0x10A0C, array step: index*0x10000, index2*0x10 */
11240     } PX_JR[16];
11241          uint8_t RESERVED_14[228];
11242     __O  uint32_t SMCR_JR;                           /**< Secure Memory Command Register, array offset: 0x10BE4, array step: 0x10000 */
11243          uint8_t RESERVED_15[4];
11244     __I  uint32_t SMCSR_JR;                          /**< Secure Memory Command Status Register, array offset: 0x10BEC, array step: 0x10000 */
11245          uint8_t RESERVED_16[528];
11246     __I  uint32_t REIR0JR;                           /**< Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3, array offset: 0x10E00, array step: 0x10000 */
11247          uint8_t RESERVED_17[4];
11248     __I  uint64_t REIR2JR;                           /**< Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3, array offset: 0x10E08, array step: 0x10000 */
11249     __I  uint32_t REIR4JR;                           /**< Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3, array offset: 0x10E10, array step: 0x10000 */
11250     __I  uint32_t REIR5JR;                           /**< Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3, array offset: 0x10E14, array step: 0x10000 */
11251          uint8_t RESERVED_18[392];
11252     __I  uint32_t CRNR_MS_JR;                        /**< CHA Revision Number Register, most-significant half, array offset: 0x10FA0, array step: 0x10000 */
11253     __I  uint32_t CRNR_LS_JR;                        /**< CHA Revision Number Register, least-significant half, array offset: 0x10FA4, array step: 0x10000 */
11254     __I  uint32_t CTPR_MS_JR;                        /**< Compile Time Parameters Register, most-significant half, array offset: 0x10FA8, array step: 0x10000 */
11255     __I  uint32_t CTPR_LS_JR;                        /**< Compile Time Parameters Register, least-significant half, array offset: 0x10FAC, array step: 0x10000 */
11256          uint8_t RESERVED_19[4];
11257     __I  uint32_t SMSTA_JR;                          /**< Secure Memory Status Register, array offset: 0x10FB4, array step: 0x10000 */
11258          uint8_t RESERVED_20[4];
11259     __I  uint32_t SMPO_JR;                           /**< Secure Memory Partition Owners Register, array offset: 0x10FBC, array step: 0x10000 */
11260     __I  uint64_t FAR_JR;                            /**< Fault Address Register, array offset: 0x10FC0, array step: 0x10000 */
11261     __I  uint32_t FADID_JR;                          /**< Fault Address DID Register, array offset: 0x10FC8, array step: 0x10000 */
11262     __I  uint32_t FADR_JR;                           /**< Fault Address Detail Register, array offset: 0x10FCC, array step: 0x10000 */
11263          uint8_t RESERVED_21[4];
11264     __I  uint32_t CSTA_JR;                           /**< CAAM Status Register, array offset: 0x10FD4, array step: 0x10000 */
11265     __I  uint32_t SMVID_MS_JR;                       /**< Secure Memory Version ID Register, most-significant half, array offset: 0x10FD8, array step: 0x10000 */
11266     __I  uint32_t SMVID_LS_JR;                       /**< Secure Memory Version ID Register, least-significant half, array offset: 0x10FDC, array step: 0x10000 */
11267     __I  uint32_t RVID_JR;                           /**< RTIC Version ID Register, array offset: 0x10FE0, array step: 0x10000 */
11268     __I  uint32_t CCBVID_JR;                         /**< CHA Cluster Block Version ID Register, array offset: 0x10FE4, array step: 0x10000 */
11269     __I  uint32_t CHAVID_MS_JR;                      /**< CHA Version ID Register, most-significant half, array offset: 0x10FE8, array step: 0x10000 */
11270     __I  uint32_t CHAVID_LS_JR;                      /**< CHA Version ID Register, least-significant half, array offset: 0x10FEC, array step: 0x10000 */
11271     __I  uint32_t CHANUM_MS_JR;                      /**< CHA Number Register, most-significant half, array offset: 0x10FF0, array step: 0x10000 */
11272     __I  uint32_t CHANUM_LS_JR;                      /**< CHA Number Register, least-significant half, array offset: 0x10FF4, array step: 0x10000 */
11273     __I  uint32_t CAAMVID_MS_JR;                     /**< CAAM Version ID Register, most-significant half, array offset: 0x10FF8, array step: 0x10000 */
11274     __I  uint32_t CAAMVID_LS_JR;                     /**< CAAM Version ID Register, least-significant half, array offset: 0x10FFC, array step: 0x10000 */
11275          uint8_t RESERVED_22[61440];
11276   } JOBRING[4];
11277        uint8_t RESERVED_38[65540];
11278   __I  uint32_t RSTA;                              /**< RTIC Status Register, offset: 0x60004 */
11279        uint8_t RESERVED_39[4];
11280   __IO uint32_t RCMD;                              /**< RTIC Command Register, offset: 0x6000C */
11281        uint8_t RESERVED_40[4];
11282   __IO uint32_t RCTL;                              /**< RTIC Control Register, offset: 0x60014 */
11283        uint8_t RESERVED_41[4];
11284   __IO uint32_t RTHR;                              /**< RTIC Throttle Register, offset: 0x6001C */
11285        uint8_t RESERVED_42[8];
11286   __IO uint64_t RWDOG;                             /**< RTIC Watchdog Timer, offset: 0x60028 */
11287        uint8_t RESERVED_43[4];
11288   __IO uint32_t REND;                              /**< RTIC Endian Register, offset: 0x60034 */
11289        uint8_t RESERVED_44[200];
11290   struct {                                         /* offset: 0x60100, array step: index*0x20, index2*0x10 */
11291     __IO uint64_t RMA;                               /**< RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register, array offset: 0x60100, array step: index*0x20, index2*0x10 */
11292          uint8_t RESERVED_0[4];
11293     __IO uint32_t RML;                               /**< RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register, array offset: 0x6010C, array step: index*0x20, index2*0x10 */
11294   } RM[4][2];
11295        uint8_t RESERVED_45[128];
11296   __IO uint32_t RMD[4][2][32];                     /**< RTIC Memory Block A Big Endian Hash Result Word 0..RTIC Memory Block D Little Endian Hash Result Word 31, array offset: 0x60200, array step: index*0x100, index2*0x80, index3*0x4 */
11297        uint8_t RESERVED_46[2048];
11298   __I  uint32_t REIR0RTIC;                         /**< Recoverable Error Interrupt Record 0 for RTIC, offset: 0x60E00 */
11299        uint8_t RESERVED_47[4];
11300   __I  uint64_t REIR2RTIC;                         /**< Recoverable Error Interrupt Record 2 for RTIC, offset: 0x60E08 */
11301   __I  uint32_t REIR4RTIC;                         /**< Recoverable Error Interrupt Record 4 for RTIC, offset: 0x60E10 */
11302   __I  uint32_t REIR5RTIC;                         /**< Recoverable Error Interrupt Record 5 for RTIC, offset: 0x60E14 */
11303        uint8_t RESERVED_48[392];
11304   __I  uint32_t CRNR_MS_RTIC;                      /**< CHA Revision Number Register, most-significant half, offset: 0x60FA0 */
11305   __I  uint32_t CRNR_LS_RTIC;                      /**< CHA Revision Number Register, least-significant half, offset: 0x60FA4 */
11306   __I  uint32_t CTPR_MS_RTIC;                      /**< Compile Time Parameters Register, most-significant half, offset: 0x60FA8 */
11307   __I  uint32_t CTPR_LS_RTIC;                      /**< Compile Time Parameters Register, least-significant half, offset: 0x60FAC */
11308        uint8_t RESERVED_49[4];
11309   __I  uint32_t SMSTA_RTIC;                        /**< Secure Memory Status Register, offset: 0x60FB4 */
11310        uint8_t RESERVED_50[8];
11311   __I  uint64_t FAR_RTIC;                          /**< Fault Address Register, offset: 0x60FC0 */
11312   __I  uint32_t FADID_RTIC;                        /**< Fault Address DID Register, offset: 0x60FC8 */
11313   __I  uint32_t FADR_RTIC;                         /**< Fault Address Detail Register, offset: 0x60FCC */
11314        uint8_t RESERVED_51[4];
11315   __I  uint32_t CSTA_RTIC;                         /**< CAAM Status Register, offset: 0x60FD4 */
11316   __I  uint32_t SMVID_MS_RTIC;                     /**< Secure Memory Version ID Register, most-significant half, offset: 0x60FD8 */
11317   __I  uint32_t SMVID_LS_RTIC;                     /**< Secure Memory Version ID Register, least-significant half, offset: 0x60FDC */
11318   __I  uint32_t RVID_RTIC;                         /**< RTIC Version ID Register, offset: 0x60FE0 */
11319   __I  uint32_t CCBVID_RTIC;                       /**< CHA Cluster Block Version ID Register, offset: 0x60FE4 */
11320   __I  uint32_t CHAVID_MS_RTIC;                    /**< CHA Version ID Register, most-significant half, offset: 0x60FE8 */
11321   __I  uint32_t CHAVID_LS_RTIC;                    /**< CHA Version ID Register, least-significant half, offset: 0x60FEC */
11322   __I  uint32_t CHANUM_MS_RTIC;                    /**< CHA Number Register, most-significant half, offset: 0x60FF0 */
11323   __I  uint32_t CHANUM_LS_RTIC;                    /**< CHA Number Register, least-significant half, offset: 0x60FF4 */
11324   __I  uint32_t CAAMVID_MS_RTIC;                   /**< CAAM Version ID Register, most-significant half, offset: 0x60FF8 */
11325   __I  uint32_t CAAMVID_LS_RTIC;                   /**< CAAM Version ID Register, least-significant half, offset: 0x60FFC */
11326        uint8_t RESERVED_52[126976];
11327   struct {                                         /* offset: 0x80000, array step: 0xE3C */
11328          uint8_t RESERVED_0[4];
11329     union {                                          /* offset: 0x80004, array step: 0xE3C */
11330       __IO uint32_t CC1MR;                             /**< CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms, array offset: 0x80004, array step: 0xE3C */
11331       __IO uint32_t CC1MR_PK;                          /**< CCB 0 Class 1 Mode Register Format for Public Key Algorithms, array offset: 0x80004, array step: 0xE3C */
11332       __IO uint32_t CC1MR_RNG;                         /**< CCB 0 Class 1 Mode Register Format for RNG4, array offset: 0x80004, array step: 0xE3C */
11333     };
11334          uint8_t RESERVED_1[4];
11335     __IO uint32_t CC1KSR;                            /**< CCB 0 Class 1 Key Size Register, array offset: 0x8000C, array step: 0xE3C */
11336     __IO uint64_t CC1DSR;                            /**< CCB 0 Class 1 Data Size Register, array offset: 0x80010, array step: 0xE3C */
11337          uint8_t RESERVED_2[4];
11338     __IO uint32_t CC1ICVSR;                          /**< CCB 0 Class 1 ICV Size Register, array offset: 0x8001C, array step: 0xE3C */
11339          uint8_t RESERVED_3[20];
11340     __O  uint32_t CCCTRL;                            /**< CCB 0 CHA Control Register, array offset: 0x80034, array step: 0xE3C */
11341          uint8_t RESERVED_4[4];
11342     __IO uint32_t CICTL;                             /**< CCB 0 Interrupt Control Register, array offset: 0x8003C, array step: 0xE3C */
11343          uint8_t RESERVED_5[4];
11344     __O  uint32_t CCWR;                              /**< CCB 0 Clear Written Register, array offset: 0x80044, array step: 0xE3C */
11345     __I  uint32_t CCSTA_MS;                          /**< CCB 0 Status and Error Register, most-significant half, array offset: 0x80048, array step: 0xE3C */
11346     __I  uint32_t CCSTA_LS;                          /**< CCB 0 Status and Error Register, least-significant half, array offset: 0x8004C, array step: 0xE3C */
11347          uint8_t RESERVED_6[12];
11348     __IO uint32_t CC1AADSZR;                         /**< CCB 0 Class 1 AAD Size Register, array offset: 0x8005C, array step: 0xE3C */
11349          uint8_t RESERVED_7[4];
11350     __IO uint32_t CC1IVSZR;                          /**< CCB 0 Class 1 IV Size Register, array offset: 0x80064, array step: 0xE3C */
11351          uint8_t RESERVED_8[28];
11352     __IO uint32_t CPKASZR;                           /**< PKHA A Size Register, array offset: 0x80084, array step: 0xE3C */
11353          uint8_t RESERVED_9[4];
11354     __IO uint32_t CPKBSZR;                           /**< PKHA B Size Register, array offset: 0x8008C, array step: 0xE3C */
11355          uint8_t RESERVED_10[4];
11356     __IO uint32_t CPKNSZR;                           /**< PKHA N Size Register, array offset: 0x80094, array step: 0xE3C */
11357          uint8_t RESERVED_11[4];
11358     __IO uint32_t CPKESZR;                           /**< PKHA E Size Register, array offset: 0x8009C, array step: 0xE3C */
11359          uint8_t RESERVED_12[96];
11360     __IO uint32_t CC1CTXR[16];                       /**< CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15, array offset: 0x80100, array step: index*0xE3C, index2*0x4 */
11361          uint8_t RESERVED_13[192];
11362     __IO uint32_t CC1KR[8];                          /**< CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7, array offset: 0x80200, array step: index*0xE3C, index2*0x4 */
11363          uint8_t RESERVED_14[484];
11364     __IO uint32_t CC2MR;                             /**< CCB 0 Class 2 Mode Register, array offset: 0x80404, array step: 0xE3C */
11365          uint8_t RESERVED_15[4];
11366     __IO uint32_t CC2KSR;                            /**< CCB 0 Class 2 Key Size Register, array offset: 0x8040C, array step: 0xE3C */
11367     __IO uint64_t CC2DSR;                            /**< CCB 0 Class 2 Data Size Register, array offset: 0x80410, array step: 0xE3C */
11368          uint8_t RESERVED_16[4];
11369     __IO uint32_t CC2ICVSZR;                         /**< CCB 0 Class 2 ICV Size Register, array offset: 0x8041C, array step: 0xE3C */
11370          uint8_t RESERVED_17[224];
11371     __IO uint32_t CC2CTXR[18];                       /**< CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17, array offset: 0x80500, array step: index*0xE3C, index2*0x4 */
11372          uint8_t RESERVED_18[184];
11373     __IO uint32_t CC2KEYR[32];                       /**< CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31, array offset: 0x80600, array step: index*0xE3C, index2*0x4 */
11374          uint8_t RESERVED_19[320];
11375     __I  uint32_t CFIFOSTA;                          /**< CCB 0 FIFO Status Register, array offset: 0x807C0, array step: 0xE3C */
11376          uint8_t RESERVED_20[12];
11377     union {                                          /* offset: 0x807D0, array step: 0xE3C */
11378       __O  uint32_t CNFIFO;                            /**< CCB 0 iNformation FIFO When STYPE != 10b, array offset: 0x807D0, array step: 0xE3C */
11379       __O  uint32_t CNFIFO_2;                          /**< CCB 0 iNformation FIFO When STYPE == 10b, array offset: 0x807D0, array step: 0xE3C */
11380     };
11381          uint8_t RESERVED_21[12];
11382     __O  uint32_t CIFIFO;                            /**< CCB 0 Input Data FIFO, array offset: 0x807E0, array step: 0xE3C */
11383          uint8_t RESERVED_22[12];
11384     __I  uint64_t COFIFO;                            /**< CCB 0 Output Data FIFO, array offset: 0x807F0, array step: 0xE3C */
11385          uint8_t RESERVED_23[8];
11386     __IO uint32_t DJQCR_MS;                          /**< DECO0 Job Queue Control Register, most-significant half, array offset: 0x80800, array step: 0xE3C */
11387     __I  uint32_t DJQCR_LS;                          /**< DECO0 Job Queue Control Register, least-significant half, array offset: 0x80804, array step: 0xE3C */
11388     __I  uint64_t DDAR;                              /**< DECO0 Descriptor Address Register, array offset: 0x80808, array step: 0xE3C */
11389     __I  uint32_t DOPSTA_MS;                         /**< DECO0 Operation Status Register, most-significant half, array offset: 0x80810, array step: 0xE3C */
11390     __I  uint32_t DOPSTA_LS;                         /**< DECO0 Operation Status Register, least-significant half, array offset: 0x80814, array step: 0xE3C */
11391          uint8_t RESERVED_24[8];
11392     __I  uint32_t DPDIDSR;                           /**< DECO0 Primary DID Status Register, array offset: 0x80820, array step: 0xE3C */
11393     __I  uint32_t DODIDSR;                           /**< DECO0 Output DID Status Register, array offset: 0x80824, array step: 0xE3C */
11394          uint8_t RESERVED_25[24];
11395     struct {                                         /* offset: 0x80840, array step: index*0xE3C, index2*0x8 */
11396       __IO uint32_t DMTH_MS;                           /**< DECO0 Math Register 0_MS..DECO0 Math Register 3_MS, array offset: 0x80840, array step: index*0xE3C, index2*0x8 */
11397       __IO uint32_t DMTH_LS;                           /**< DECO0 Math Register 0_LS..DECO0 Math Register 3_LS, array offset: 0x80844, array step: index*0xE3C, index2*0x8 */
11398     } DDMTHB[4];
11399          uint8_t RESERVED_26[32];
11400     struct {                                         /* offset: 0x80880, array step: index*0xE3C, index2*0x10 */
11401       __IO uint32_t DGTR_0;                            /**< DECO0 Gather Table Register 0 Word 0, array offset: 0x80880, array step: index*0xE3C, index2*0x10 */
11402       __IO uint32_t DGTR_1;                            /**< DECO0 Gather Table Register 0 Word 1, array offset: 0x80884, array step: index*0xE3C, index2*0x10 */
11403       __IO uint32_t DGTR_2;                            /**< DECO0 Gather Table Register 0 Word 2, array offset: 0x80888, array step: index*0xE3C, index2*0x10 */
11404       __IO uint32_t DGTR_3;                            /**< DECO0 Gather Table Register 0 Word 3, array offset: 0x8088C, array step: index*0xE3C, index2*0x10 */
11405     } DDGTR[1];
11406          uint8_t RESERVED_27[112];
11407     struct {                                         /* offset: 0x80900, array step: index*0xE3C, index2*0x10 */
11408       __IO uint32_t DSTR_0;                            /**< DECO0 Scatter Table Register 0 Word 0, array offset: 0x80900, array step: index*0xE3C, index2*0x10 */
11409       __IO uint32_t DSTR_1;                            /**< DECO0 Scatter Table Register 0 Word 1, array offset: 0x80904, array step: index*0xE3C, index2*0x10 */
11410       __IO uint32_t DSTR_2;                            /**< DECO0 Scatter Table Register 0 Word 2, array offset: 0x80908, array step: index*0xE3C, index2*0x10 */
11411       __IO uint32_t DSTR_3;                            /**< DECO0 Scatter Table Register 0 Word 3, array offset: 0x8090C, array step: index*0xE3C, index2*0x10 */
11412     } DDSTR[1];
11413          uint8_t RESERVED_28[240];
11414     __IO uint32_t DDESB[64];                         /**< DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63, array offset: 0x80A00, array step: index*0xE3C, index2*0x4 */
11415          uint8_t RESERVED_29[768];
11416     __I  uint32_t DDJR;                              /**< DECO0 Debug Job Register, array offset: 0x80E00, array step: 0xE3C */
11417     __I  uint32_t DDDR;                              /**< DECO0 Debug DECO Register, array offset: 0x80E04, array step: 0xE3C */
11418     __I  uint64_t DDJP;                              /**< DECO0 Debug Job Pointer, array offset: 0x80E08, array step: 0xE3C */
11419     __I  uint64_t DSDP;                              /**< DECO0 Debug Shared Pointer, array offset: 0x80E10, array step: 0xE3C */
11420     __I  uint32_t DDDR_MS;                           /**< DECO0 Debug DID, most-significant half, array offset: 0x80E18, array step: 0xE3C */
11421     __I  uint32_t DDDR_LS;                           /**< DECO0 Debug DID, least-significant half, array offset: 0x80E1C, array step: 0xE3C */
11422     __IO uint32_t SOL;                               /**< Sequence Output Length Register, array offset: 0x80E20, array step: 0xE3C */
11423     __IO uint32_t VSOL;                              /**< Variable Sequence Output Length Register, array offset: 0x80E24, array step: 0xE3C */
11424     __IO uint32_t SIL;                               /**< Sequence Input Length Register, array offset: 0x80E28, array step: 0xE3C */
11425     __IO uint32_t VSIL;                              /**< Variable Sequence Input Length Register, array offset: 0x80E2C, array step: 0xE3C */
11426     __IO uint32_t DPOVRD;                            /**< Protocol Override Register, array offset: 0x80E30, array step: 0xE3C */
11427     __IO uint32_t UVSOL;                             /**< Variable Sequence Output Length Register; Upper 32 bits, array offset: 0x80E34, array step: 0xE3C */
11428     __IO uint32_t UVSIL;                             /**< Variable Sequence Input Length Register; Upper 32 bits, array offset: 0x80E38, array step: 0xE3C */
11429   } DC[1];
11430        uint8_t RESERVED_53[356];
11431   __I  uint32_t CRNR_MS_DC01;                      /**< CHA Revision Number Register, most-significant half, offset: 0x80FA0 */
11432   __I  uint32_t CRNR_LS_DC01;                      /**< CHA Revision Number Register, least-significant half, offset: 0x80FA4 */
11433   __I  uint32_t CTPR_MS_DC01;                      /**< Compile Time Parameters Register, most-significant half, offset: 0x80FA8 */
11434   __I  uint32_t CTPR_LS_DC01;                      /**< Compile Time Parameters Register, least-significant half, offset: 0x80FAC */
11435        uint8_t RESERVED_54[4];
11436   __I  uint32_t SMSTA_DC01;                        /**< Secure Memory Status Register, offset: 0x80FB4 */
11437        uint8_t RESERVED_55[8];
11438   __I  uint64_t FAR_DC01;                          /**< Fault Address Register, offset: 0x80FC0 */
11439   __I  uint32_t FADID_DC01;                        /**< Fault Address DID Register, offset: 0x80FC8 */
11440   __I  uint32_t FADR_DC01;                         /**< Fault Address Detail Register, offset: 0x80FCC */
11441        uint8_t RESERVED_56[4];
11442   __I  uint32_t CSTA_DC01;                         /**< CAAM Status Register, offset: 0x80FD4 */
11443   __I  uint32_t SMVID_MS_DC01;                     /**< Secure Memory Version ID Register, most-significant half, offset: 0x80FD8 */
11444   __I  uint32_t SMVID_LS_DC01;                     /**< Secure Memory Version ID Register, least-significant half, offset: 0x80FDC */
11445   __I  uint32_t RVID_DC01;                         /**< RTIC Version ID Register, offset: 0x80FE0 */
11446   __I  uint32_t CCBVID_DC01;                       /**< CHA Cluster Block Version ID Register, offset: 0x80FE4 */
11447   __I  uint32_t CHAVID_MS_DC01;                    /**< CHA Version ID Register, most-significant half, offset: 0x80FE8 */
11448   __I  uint32_t CHAVID_LS_DC01;                    /**< CHA Version ID Register, least-significant half, offset: 0x80FEC */
11449   __I  uint32_t CHANUM_MS_DC01;                    /**< CHA Number Register, most-significant half, offset: 0x80FF0 */
11450   __I  uint32_t CHANUM_LS_DC01;                    /**< CHA Number Register, least-significant half, offset: 0x80FF4 */
11451   __I  uint32_t CAAMVID_MS_DC01;                   /**< CAAM Version ID Register, most-significant half, offset: 0x80FF8 */
11452   __I  uint32_t CAAMVID_LS_DC01;                   /**< CAAM Version ID Register, least-significant half, offset: 0x80FFC */
11453 } CAAM_Type;
11454 
11455 /* ----------------------------------------------------------------------------
11456    -- CAAM Register Masks
11457    ---------------------------------------------------------------------------- */
11458 
11459 /*!
11460  * @addtogroup CAAM_Register_Masks CAAM Register Masks
11461  * @{
11462  */
11463 
11464 /*! @name MCFGR - Master Configuration Register */
11465 /*! @{ */
11466 
11467 #define CAAM_MCFGR_NORMAL_BURST_MASK             (0x1U)
11468 #define CAAM_MCFGR_NORMAL_BURST_SHIFT            (0U)
11469 /*! NORMAL_BURST
11470  *  0b0..Aligned 32 byte burst size target
11471  *  0b1..Aligned 64 byte burst size target
11472  */
11473 #define CAAM_MCFGR_NORMAL_BURST(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_NORMAL_BURST_SHIFT)) & CAAM_MCFGR_NORMAL_BURST_MASK)
11474 
11475 #define CAAM_MCFGR_LARGE_BURST_MASK              (0x4U)
11476 #define CAAM_MCFGR_LARGE_BURST_SHIFT             (2U)
11477 #define CAAM_MCFGR_LARGE_BURST(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_LARGE_BURST_SHIFT)) & CAAM_MCFGR_LARGE_BURST_MASK)
11478 
11479 #define CAAM_MCFGR_AXIPIPE_MASK                  (0xF0U)
11480 #define CAAM_MCFGR_AXIPIPE_SHIFT                 (4U)
11481 #define CAAM_MCFGR_AXIPIPE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_AXIPIPE_SHIFT)) & CAAM_MCFGR_AXIPIPE_MASK)
11482 
11483 #define CAAM_MCFGR_AWCACHE_MASK                  (0xF00U)
11484 #define CAAM_MCFGR_AWCACHE_SHIFT                 (8U)
11485 #define CAAM_MCFGR_AWCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_AWCACHE_SHIFT)) & CAAM_MCFGR_AWCACHE_MASK)
11486 
11487 #define CAAM_MCFGR_ARCACHE_MASK                  (0xF000U)
11488 #define CAAM_MCFGR_ARCACHE_SHIFT                 (12U)
11489 #define CAAM_MCFGR_ARCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_ARCACHE_SHIFT)) & CAAM_MCFGR_ARCACHE_MASK)
11490 
11491 #define CAAM_MCFGR_PS_MASK                       (0x10000U)
11492 #define CAAM_MCFGR_PS_SHIFT                      (16U)
11493 /*! PS
11494  *  0b0..Pointers fit in one 32-bit word (pointers are 32-bit addresses).
11495  *  0b1..Pointers require two 32-bit words (pointers are 36-bit addresses).
11496  */
11497 #define CAAM_MCFGR_PS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_PS_SHIFT)) & CAAM_MCFGR_PS_MASK)
11498 
11499 #define CAAM_MCFGR_DWT_MASK                      (0x80000U)
11500 #define CAAM_MCFGR_DWT_SHIFT                     (19U)
11501 #define CAAM_MCFGR_DWT(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_DWT_SHIFT)) & CAAM_MCFGR_DWT_MASK)
11502 
11503 #define CAAM_MCFGR_WRHD_MASK                     (0x8000000U)
11504 #define CAAM_MCFGR_WRHD_SHIFT                    (27U)
11505 #define CAAM_MCFGR_WRHD(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WRHD_SHIFT)) & CAAM_MCFGR_WRHD_MASK)
11506 
11507 #define CAAM_MCFGR_DMA_RST_MASK                  (0x10000000U)
11508 #define CAAM_MCFGR_DMA_RST_SHIFT                 (28U)
11509 #define CAAM_MCFGR_DMA_RST(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_DMA_RST_SHIFT)) & CAAM_MCFGR_DMA_RST_MASK)
11510 
11511 #define CAAM_MCFGR_WDF_MASK                      (0x20000000U)
11512 #define CAAM_MCFGR_WDF_SHIFT                     (29U)
11513 #define CAAM_MCFGR_WDF(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WDF_SHIFT)) & CAAM_MCFGR_WDF_MASK)
11514 
11515 #define CAAM_MCFGR_WDE_MASK                      (0x40000000U)
11516 #define CAAM_MCFGR_WDE_SHIFT                     (30U)
11517 #define CAAM_MCFGR_WDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WDE_SHIFT)) & CAAM_MCFGR_WDE_MASK)
11518 
11519 #define CAAM_MCFGR_SWRST_MASK                    (0x80000000U)
11520 #define CAAM_MCFGR_SWRST_SHIFT                   (31U)
11521 #define CAAM_MCFGR_SWRST(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_SWRST_SHIFT)) & CAAM_MCFGR_SWRST_MASK)
11522 /*! @} */
11523 
11524 /*! @name PAGE0_SDID - Page 0 SDID Register */
11525 /*! @{ */
11526 
11527 #define CAAM_PAGE0_SDID_SDID_MASK                (0x7FFFU)
11528 #define CAAM_PAGE0_SDID_SDID_SHIFT               (0U)
11529 #define CAAM_PAGE0_SDID_SDID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_PAGE0_SDID_SDID_SHIFT)) & CAAM_PAGE0_SDID_SDID_MASK)
11530 /*! @} */
11531 
11532 /*! @name SCFGR - Security Configuration Register */
11533 /*! @{ */
11534 
11535 #define CAAM_SCFGR_PRIBLOB_MASK                  (0x3U)
11536 #define CAAM_SCFGR_PRIBLOB_SHIFT                 (0U)
11537 /*! PRIBLOB
11538  *  0b00..Private secure boot software blobs
11539  *  0b01..Private provisioning type 1 blobs
11540  *  0b10..Private provisioning type 2 blobs
11541  *  0b11..Normal operation blobs
11542  */
11543 #define CAAM_SCFGR_PRIBLOB(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_PRIBLOB_SHIFT)) & CAAM_SCFGR_PRIBLOB_MASK)
11544 
11545 #define CAAM_SCFGR_RNGSH0_MASK                   (0x200U)
11546 #define CAAM_SCFGR_RNGSH0_SHIFT                  (9U)
11547 /*! RNGSH0
11548  *  0b0..When RNGSH0 is 0, RNG DRNG State Handle 0 can be instantiated in any mode. RNGSH0 is set to 0 only for testing.
11549  *  0b1..When RNGSH0 is 1, RNG DRNG State Handle 0 cannot be instantiated in deterministic (test) mode. RNGSHO
11550  *       should be set to 1 before the RNG is instantiated. If it is currently instantiated in a deterministic mode,
11551  *       it will be un-instantiated. Once this bit has been written to a 1, it cannot be changed to a 0 until the
11552  *       next power on reset.
11553  */
11554 #define CAAM_SCFGR_RNGSH0(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_RNGSH0_SHIFT)) & CAAM_SCFGR_RNGSH0_MASK)
11555 
11556 #define CAAM_SCFGR_LCK_TRNG_MASK                 (0x800U)
11557 #define CAAM_SCFGR_LCK_TRNG_SHIFT                (11U)
11558 #define CAAM_SCFGR_LCK_TRNG(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_LCK_TRNG_SHIFT)) & CAAM_SCFGR_LCK_TRNG_MASK)
11559 
11560 #define CAAM_SCFGR_VIRT_EN_MASK                  (0x8000U)
11561 #define CAAM_SCFGR_VIRT_EN_SHIFT                 (15U)
11562 /*! VIRT_EN
11563  *  0b0..Disable job ring virtualization
11564  *  0b1..Enable job ring virtualization
11565  */
11566 #define CAAM_SCFGR_VIRT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_VIRT_EN_SHIFT)) & CAAM_SCFGR_VIRT_EN_MASK)
11567 
11568 #define CAAM_SCFGR_MPMRL_MASK                    (0x4000000U)
11569 #define CAAM_SCFGR_MPMRL_SHIFT                   (26U)
11570 #define CAAM_SCFGR_MPMRL(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPMRL_SHIFT)) & CAAM_SCFGR_MPMRL_MASK)
11571 
11572 #define CAAM_SCFGR_MPPKRC_MASK                   (0x8000000U)
11573 #define CAAM_SCFGR_MPPKRC_SHIFT                  (27U)
11574 #define CAAM_SCFGR_MPPKRC(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPPKRC_SHIFT)) & CAAM_SCFGR_MPPKRC_MASK)
11575 
11576 #define CAAM_SCFGR_MPCURVE_MASK                  (0xF0000000U)
11577 #define CAAM_SCFGR_MPCURVE_SHIFT                 (28U)
11578 #define CAAM_SCFGR_MPCURVE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPCURVE_SHIFT)) & CAAM_SCFGR_MPCURVE_MASK)
11579 /*! @} */
11580 
11581 /*! @name JRDID_MS - Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half */
11582 /*! @{ */
11583 
11584 #define CAAM_JRDID_MS_PRIM_DID_MASK              (0xFU)
11585 #define CAAM_JRDID_MS_PRIM_DID_SHIFT             (0U)
11586 #define CAAM_JRDID_MS_PRIM_DID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_DID_SHIFT)) & CAAM_JRDID_MS_PRIM_DID_MASK)
11587 
11588 #define CAAM_JRDID_MS_PRIM_TZ_MASK               (0x10U)
11589 #define CAAM_JRDID_MS_PRIM_TZ_SHIFT              (4U)
11590 #define CAAM_JRDID_MS_PRIM_TZ(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_TZ_SHIFT)) & CAAM_JRDID_MS_PRIM_TZ_MASK)
11591 
11592 #define CAAM_JRDID_MS_SDID_MS_MASK               (0x7FE0U)
11593 #define CAAM_JRDID_MS_SDID_MS_SHIFT              (5U)
11594 #define CAAM_JRDID_MS_SDID_MS(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_SDID_MS_SHIFT)) & CAAM_JRDID_MS_SDID_MS_MASK)
11595 
11596 #define CAAM_JRDID_MS_TZ_OWN_MASK                (0x8000U)
11597 #define CAAM_JRDID_MS_TZ_OWN_SHIFT               (15U)
11598 #define CAAM_JRDID_MS_TZ_OWN(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_TZ_OWN_SHIFT)) & CAAM_JRDID_MS_TZ_OWN_MASK)
11599 
11600 #define CAAM_JRDID_MS_AMTD_MASK                  (0x10000U)
11601 #define CAAM_JRDID_MS_AMTD_SHIFT                 (16U)
11602 #define CAAM_JRDID_MS_AMTD(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_AMTD_SHIFT)) & CAAM_JRDID_MS_AMTD_MASK)
11603 
11604 #define CAAM_JRDID_MS_LAMTD_MASK                 (0x20000U)
11605 #define CAAM_JRDID_MS_LAMTD_SHIFT                (17U)
11606 #define CAAM_JRDID_MS_LAMTD(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_LAMTD_SHIFT)) & CAAM_JRDID_MS_LAMTD_MASK)
11607 
11608 #define CAAM_JRDID_MS_PRIM_ICID_MASK             (0x3FF80000U)
11609 #define CAAM_JRDID_MS_PRIM_ICID_SHIFT            (19U)
11610 #define CAAM_JRDID_MS_PRIM_ICID(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_ICID_SHIFT)) & CAAM_JRDID_MS_PRIM_ICID_MASK)
11611 
11612 #define CAAM_JRDID_MS_USE_OUT_MASK               (0x40000000U)
11613 #define CAAM_JRDID_MS_USE_OUT_SHIFT              (30U)
11614 #define CAAM_JRDID_MS_USE_OUT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_USE_OUT_SHIFT)) & CAAM_JRDID_MS_USE_OUT_MASK)
11615 
11616 #define CAAM_JRDID_MS_LDID_MASK                  (0x80000000U)
11617 #define CAAM_JRDID_MS_LDID_SHIFT                 (31U)
11618 #define CAAM_JRDID_MS_LDID(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_LDID_SHIFT)) & CAAM_JRDID_MS_LDID_MASK)
11619 /*! @} */
11620 
11621 /* The count of CAAM_JRDID_MS */
11622 #define CAAM_JRDID_MS_COUNT                      (4U)
11623 
11624 /*! @name JRDID_LS - Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half */
11625 /*! @{ */
11626 
11627 #define CAAM_JRDID_LS_OUT_DID_MASK               (0xFU)
11628 #define CAAM_JRDID_LS_OUT_DID_SHIFT              (0U)
11629 #define CAAM_JRDID_LS_OUT_DID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_LS_OUT_DID_SHIFT)) & CAAM_JRDID_LS_OUT_DID_MASK)
11630 
11631 #define CAAM_JRDID_LS_OUT_ICID_MASK              (0x3FF80000U)
11632 #define CAAM_JRDID_LS_OUT_ICID_SHIFT             (19U)
11633 #define CAAM_JRDID_LS_OUT_ICID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_LS_OUT_ICID_SHIFT)) & CAAM_JRDID_LS_OUT_ICID_MASK)
11634 /*! @} */
11635 
11636 /* The count of CAAM_JRDID_LS */
11637 #define CAAM_JRDID_LS_COUNT                      (4U)
11638 
11639 /*! @name DEBUGCTL - Debug Control Register */
11640 /*! @{ */
11641 
11642 #define CAAM_DEBUGCTL_STOP_MASK                  (0x10000U)
11643 #define CAAM_DEBUGCTL_STOP_SHIFT                 (16U)
11644 #define CAAM_DEBUGCTL_STOP(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DEBUGCTL_STOP_SHIFT)) & CAAM_DEBUGCTL_STOP_MASK)
11645 
11646 #define CAAM_DEBUGCTL_STOP_ACK_MASK              (0x20000U)
11647 #define CAAM_DEBUGCTL_STOP_ACK_SHIFT             (17U)
11648 #define CAAM_DEBUGCTL_STOP_ACK(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DEBUGCTL_STOP_ACK_SHIFT)) & CAAM_DEBUGCTL_STOP_ACK_MASK)
11649 /*! @} */
11650 
11651 /*! @name JRSTARTR - Job Ring Start Register */
11652 /*! @{ */
11653 
11654 #define CAAM_JRSTARTR_Start_JR0_MASK             (0x1U)
11655 #define CAAM_JRSTARTR_Start_JR0_SHIFT            (0U)
11656 /*! Start_JR0
11657  *  0b0..Stop Mode. The JR0DID register and the SMVBA register for Job Ring 0 can be written but the IRBAR, IRSR,
11658  *       IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 0 are NOT accessible. If Job Ring 0 is
11659  *       allocated to TrustZone SecureWorld (JR0DID[TZ]=1), the JR0DID and SMVBA register can be written only via a
11660  *       bus transaction that has ns=0.
11661  *  0b1..Start Mode. The JR0DID register and the SMVBA register for Job Ring 0 CANNOT be written but the IRBAR,
11662  *       IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 0 ARE accessible. If Job Ring 0 is
11663  *       allocated to TrustZone SecureWorld (JR0DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
11664  *       ORJRR, ORSFR and JRSTAR registers for Job Ring 0 can be written only via a bus transaction that has ns=0.
11665  */
11666 #define CAAM_JRSTARTR_Start_JR0(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR0_SHIFT)) & CAAM_JRSTARTR_Start_JR0_MASK)
11667 
11668 #define CAAM_JRSTARTR_Start_JR1_MASK             (0x2U)
11669 #define CAAM_JRSTARTR_Start_JR1_SHIFT            (1U)
11670 /*! Start_JR1
11671  *  0b0..Stop Mode. The JR1DID register and the SMVBA register for Job Ring 1 can be written but the IRBAR, IRSR,
11672  *       IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 1 are NOT accessible. If Job Ring 1 is
11673  *       allocated to TrustZone SecureWorld (JR1DID[TZ]=1), the JR1DID and SMVBA register can be written only via a
11674  *       bus transaction that has ns=0.
11675  *  0b1..Start Mode. The JR1DID register and the SMVBA register for Job Ring 1 CANNOT be written but the IRBAR,
11676  *       IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 1 ARE accessible. If Job Ring 1 is
11677  *       allocated to TrustZone SecureWorld (JR1DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
11678  *       ORJRR, ORSFR and JRSTAR registers for Job Ring 1 can be written only via a bus transaction that has ns=0.
11679  */
11680 #define CAAM_JRSTARTR_Start_JR1(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR1_SHIFT)) & CAAM_JRSTARTR_Start_JR1_MASK)
11681 
11682 #define CAAM_JRSTARTR_Start_JR2_MASK             (0x4U)
11683 #define CAAM_JRSTARTR_Start_JR2_SHIFT            (2U)
11684 /*! Start_JR2
11685  *  0b0..Stop Mode. The JR2DID register and the SMVBA register for Job Ring 2 can be written but the IRBAR, IRSR,
11686  *       IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 2 are NOT accessible. If Job Ring 2 is
11687  *       allocated to TrustZone SecureWorld (JR2DID[TZ]=1), the JR2DID and SMVBA register can be written only via a
11688  *       bus transaction that has ns=0.
11689  *  0b1..Start Mode. The JR2DID register and the SMVBA register for Job Ring 2 CANNOT be written but the IRBAR,
11690  *       IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 2 ARE accessible. If Job Ring 2 is
11691  *       allocated to TrustZone SecureWorld (JR2DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
11692  *       ORJRR, ORSFR and JRSTAR registers for Job Ring 2 can be written only via a bus transaction that has ns=0.
11693  */
11694 #define CAAM_JRSTARTR_Start_JR2(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR2_SHIFT)) & CAAM_JRSTARTR_Start_JR2_MASK)
11695 
11696 #define CAAM_JRSTARTR_Start_JR3_MASK             (0x8U)
11697 #define CAAM_JRSTARTR_Start_JR3_SHIFT            (3U)
11698 /*! Start_JR3
11699  *  0b0..Stop Mode. The JR3DID register and the SMVBA register for Job Ring 3 can be written but the IRBAR, IRSR,
11700  *       IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 3 are NOT accessible. If Job Ring 3 is
11701  *       allocated to TrustZone SecureWorld (JR3DID[TZ]=1), the JR3DID and SMVBA register can be written only via a
11702  *       bus transaction that has ns=0.
11703  *  0b1..Start Mode. The JR3DID register and the SMVBA register for Job Ring 3 CANNOT be written but the IRBAR,
11704  *       IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 3 ARE accessible. If Job Ring 3 is
11705  *       allocated to TrustZone SecureWorld (JR3DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
11706  *       ORJRR, ORSFR and JRSTAR registers for Job Ring 3 can be written only via a bus transaction that has ns=0.
11707  */
11708 #define CAAM_JRSTARTR_Start_JR3(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR3_SHIFT)) & CAAM_JRSTARTR_Start_JR3_MASK)
11709 /*! @} */
11710 
11711 /*! @name RTIC_OWN - RTIC OWN Register */
11712 /*! @{ */
11713 
11714 #define CAAM_RTIC_OWN_ROWN_DID_MASK              (0xFU)
11715 #define CAAM_RTIC_OWN_ROWN_DID_SHIFT             (0U)
11716 /*! ROWN_DID - RTIC Owner's DID */
11717 #define CAAM_RTIC_OWN_ROWN_DID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_ROWN_DID_SHIFT)) & CAAM_RTIC_OWN_ROWN_DID_MASK)
11718 
11719 #define CAAM_RTIC_OWN_ROWN_TZ_MASK               (0x10U)
11720 #define CAAM_RTIC_OWN_ROWN_TZ_SHIFT              (4U)
11721 #define CAAM_RTIC_OWN_ROWN_TZ(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_ROWN_TZ_SHIFT)) & CAAM_RTIC_OWN_ROWN_TZ_MASK)
11722 
11723 #define CAAM_RTIC_OWN_LCK_MASK                   (0x80000000U)
11724 #define CAAM_RTIC_OWN_LCK_SHIFT                  (31U)
11725 #define CAAM_RTIC_OWN_LCK(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_LCK_SHIFT)) & CAAM_RTIC_OWN_LCK_MASK)
11726 /*! @} */
11727 
11728 /*! @name RTIC_DID - RTIC DID Register for Block A..RTIC DID Register for Block D */
11729 /*! @{ */
11730 
11731 #define CAAM_RTIC_DID_RTIC_DID_MASK              (0xFU)
11732 #define CAAM_RTIC_DID_RTIC_DID_SHIFT             (0U)
11733 #define CAAM_RTIC_DID_RTIC_DID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_DID_SHIFT)) & CAAM_RTIC_DID_RTIC_DID_MASK)
11734 
11735 #define CAAM_RTIC_DID_RTIC_TZ_MASK               (0x10U)
11736 #define CAAM_RTIC_DID_RTIC_TZ_SHIFT              (4U)
11737 #define CAAM_RTIC_DID_RTIC_TZ(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_TZ_SHIFT)) & CAAM_RTIC_DID_RTIC_TZ_MASK)
11738 
11739 #define CAAM_RTIC_DID_RTIC_ICID_MASK             (0x3FF80000U)
11740 #define CAAM_RTIC_DID_RTIC_ICID_SHIFT            (19U)
11741 #define CAAM_RTIC_DID_RTIC_ICID(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_ICID_SHIFT)) & CAAM_RTIC_DID_RTIC_ICID_MASK)
11742 /*! @} */
11743 
11744 /* The count of CAAM_RTIC_DID */
11745 #define CAAM_RTIC_DID_COUNT                      (4U)
11746 
11747 /*! @name DECORSR - DECO Request Source Register */
11748 /*! @{ */
11749 
11750 #define CAAM_DECORSR_JR_MASK                     (0x3U)
11751 #define CAAM_DECORSR_JR_SHIFT                    (0U)
11752 #define CAAM_DECORSR_JR(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_DECORSR_JR_SHIFT)) & CAAM_DECORSR_JR_MASK)
11753 
11754 #define CAAM_DECORSR_VALID_MASK                  (0x80000000U)
11755 #define CAAM_DECORSR_VALID_SHIFT                 (31U)
11756 #define CAAM_DECORSR_VALID(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DECORSR_VALID_SHIFT)) & CAAM_DECORSR_VALID_MASK)
11757 /*! @} */
11758 
11759 /*! @name DECORR - DECO Request Register */
11760 /*! @{ */
11761 
11762 #define CAAM_DECORR_RQD0_MASK                    (0x1U)
11763 #define CAAM_DECORR_RQD0_SHIFT                   (0U)
11764 #define CAAM_DECORR_RQD0(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_DECORR_RQD0_SHIFT)) & CAAM_DECORR_RQD0_MASK)
11765 
11766 #define CAAM_DECORR_DEN0_MASK                    (0x10000U)
11767 #define CAAM_DECORR_DEN0_SHIFT                   (16U)
11768 #define CAAM_DECORR_DEN0(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_DECORR_DEN0_SHIFT)) & CAAM_DECORR_DEN0_MASK)
11769 /*! @} */
11770 
11771 /*! @name DECODID_MS - DECO0 DID Register - most significant half */
11772 /*! @{ */
11773 
11774 #define CAAM_DECODID_MS_DPRIM_DID_MASK           (0xFU)
11775 #define CAAM_DECODID_MS_DPRIM_DID_SHIFT          (0U)
11776 /*! DPRIM_DID - DECO Owner */
11777 #define CAAM_DECODID_MS_DPRIM_DID(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_DPRIM_DID_SHIFT)) & CAAM_DECODID_MS_DPRIM_DID_MASK)
11778 
11779 #define CAAM_DECODID_MS_D_NS_MASK                (0x10U)
11780 #define CAAM_DECODID_MS_D_NS_SHIFT               (4U)
11781 #define CAAM_DECODID_MS_D_NS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_D_NS_SHIFT)) & CAAM_DECODID_MS_D_NS_MASK)
11782 
11783 #define CAAM_DECODID_MS_LCK_MASK                 (0x80000000U)
11784 #define CAAM_DECODID_MS_LCK_SHIFT                (31U)
11785 #define CAAM_DECODID_MS_LCK(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_LCK_SHIFT)) & CAAM_DECODID_MS_LCK_MASK)
11786 /*! @} */
11787 
11788 /* The count of CAAM_DECODID_MS */
11789 #define CAAM_DECODID_MS_COUNT                    (1U)
11790 
11791 /*! @name DECODID_LS - DECO0 DID Register - least significant half */
11792 /*! @{ */
11793 
11794 #define CAAM_DECODID_LS_DSEQ_DID_MASK            (0xFU)
11795 #define CAAM_DECODID_LS_DSEQ_DID_SHIFT           (0U)
11796 #define CAAM_DECODID_LS_DSEQ_DID(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DSEQ_DID_SHIFT)) & CAAM_DECODID_LS_DSEQ_DID_MASK)
11797 
11798 #define CAAM_DECODID_LS_DSEQ_NS_MASK             (0x10U)
11799 #define CAAM_DECODID_LS_DSEQ_NS_SHIFT            (4U)
11800 #define CAAM_DECODID_LS_DSEQ_NS(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DSEQ_NS_SHIFT)) & CAAM_DECODID_LS_DSEQ_NS_MASK)
11801 
11802 #define CAAM_DECODID_LS_DNSEQ_DID_MASK           (0xF0000U)
11803 #define CAAM_DECODID_LS_DNSEQ_DID_SHIFT          (16U)
11804 #define CAAM_DECODID_LS_DNSEQ_DID(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DNSEQ_DID_SHIFT)) & CAAM_DECODID_LS_DNSEQ_DID_MASK)
11805 
11806 #define CAAM_DECODID_LS_DNONSEQ_NS_MASK          (0x100000U)
11807 #define CAAM_DECODID_LS_DNONSEQ_NS_SHIFT         (20U)
11808 #define CAAM_DECODID_LS_DNONSEQ_NS(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DNONSEQ_NS_SHIFT)) & CAAM_DECODID_LS_DNONSEQ_NS_MASK)
11809 /*! @} */
11810 
11811 /* The count of CAAM_DECODID_LS */
11812 #define CAAM_DECODID_LS_COUNT                    (1U)
11813 
11814 /*! @name DAR - DECO Availability Register */
11815 /*! @{ */
11816 
11817 #define CAAM_DAR_NYA0_MASK                       (0x1U)
11818 #define CAAM_DAR_NYA0_SHIFT                      (0U)
11819 #define CAAM_DAR_NYA0(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DAR_NYA0_SHIFT)) & CAAM_DAR_NYA0_MASK)
11820 /*! @} */
11821 
11822 /*! @name DRR - DECO Reset Register */
11823 /*! @{ */
11824 
11825 #define CAAM_DRR_RST0_MASK                       (0x1U)
11826 #define CAAM_DRR_RST0_SHIFT                      (0U)
11827 #define CAAM_DRR_RST0(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DRR_RST0_SHIFT)) & CAAM_DRR_RST0_MASK)
11828 /*! @} */
11829 
11830 /*! @name JRSMVBAR - Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register */
11831 /*! @{ */
11832 
11833 #define CAAM_JRSMVBAR_SMVBA_MASK                 (0xFFFFFFFFU)
11834 #define CAAM_JRSMVBAR_SMVBA_SHIFT                (0U)
11835 #define CAAM_JRSMVBAR_SMVBA(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_JRSMVBAR_SMVBA_SHIFT)) & CAAM_JRSMVBAR_SMVBA_MASK)
11836 /*! @} */
11837 
11838 /* The count of CAAM_JRSMVBAR */
11839 #define CAAM_JRSMVBAR_COUNT                      (4U)
11840 
11841 /*! @name PBSL - Peak Bandwidth Smoothing Limit Register */
11842 /*! @{ */
11843 
11844 #define CAAM_PBSL_PBSL_MASK                      (0x7FU)
11845 #define CAAM_PBSL_PBSL_SHIFT                     (0U)
11846 #define CAAM_PBSL_PBSL(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_PBSL_PBSL_SHIFT)) & CAAM_PBSL_PBSL_MASK)
11847 /*! @} */
11848 
11849 /*! @name DMA_AIDL_MAP_MS - DMA0_AIDL_MAP_MS */
11850 /*! @{ */
11851 
11852 #define CAAM_DMA_AIDL_MAP_MS_AID4_BID_MASK       (0xFFU)
11853 #define CAAM_DMA_AIDL_MAP_MS_AID4_BID_SHIFT      (0U)
11854 #define CAAM_DMA_AIDL_MAP_MS_AID4_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID4_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID4_BID_MASK)
11855 
11856 #define CAAM_DMA_AIDL_MAP_MS_AID5_BID_MASK       (0xFF00U)
11857 #define CAAM_DMA_AIDL_MAP_MS_AID5_BID_SHIFT      (8U)
11858 #define CAAM_DMA_AIDL_MAP_MS_AID5_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID5_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID5_BID_MASK)
11859 
11860 #define CAAM_DMA_AIDL_MAP_MS_AID6_BID_MASK       (0xFF0000U)
11861 #define CAAM_DMA_AIDL_MAP_MS_AID6_BID_SHIFT      (16U)
11862 #define CAAM_DMA_AIDL_MAP_MS_AID6_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID6_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID6_BID_MASK)
11863 
11864 #define CAAM_DMA_AIDL_MAP_MS_AID7_BID_MASK       (0xFF000000U)
11865 #define CAAM_DMA_AIDL_MAP_MS_AID7_BID_SHIFT      (24U)
11866 #define CAAM_DMA_AIDL_MAP_MS_AID7_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID7_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID7_BID_MASK)
11867 /*! @} */
11868 
11869 /* The count of CAAM_DMA_AIDL_MAP_MS */
11870 #define CAAM_DMA_AIDL_MAP_MS_COUNT               (1U)
11871 
11872 /*! @name DMA_AIDL_MAP_LS - DMA0_AIDL_MAP_LS */
11873 /*! @{ */
11874 
11875 #define CAAM_DMA_AIDL_MAP_LS_AID0_BID_MASK       (0xFFU)
11876 #define CAAM_DMA_AIDL_MAP_LS_AID0_BID_SHIFT      (0U)
11877 #define CAAM_DMA_AIDL_MAP_LS_AID0_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID0_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID0_BID_MASK)
11878 
11879 #define CAAM_DMA_AIDL_MAP_LS_AID1_BID_MASK       (0xFF00U)
11880 #define CAAM_DMA_AIDL_MAP_LS_AID1_BID_SHIFT      (8U)
11881 #define CAAM_DMA_AIDL_MAP_LS_AID1_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID1_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID1_BID_MASK)
11882 
11883 #define CAAM_DMA_AIDL_MAP_LS_AID2_BID_MASK       (0xFF0000U)
11884 #define CAAM_DMA_AIDL_MAP_LS_AID2_BID_SHIFT      (16U)
11885 #define CAAM_DMA_AIDL_MAP_LS_AID2_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID2_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID2_BID_MASK)
11886 
11887 #define CAAM_DMA_AIDL_MAP_LS_AID3_BID_MASK       (0xFF000000U)
11888 #define CAAM_DMA_AIDL_MAP_LS_AID3_BID_SHIFT      (24U)
11889 #define CAAM_DMA_AIDL_MAP_LS_AID3_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID3_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID3_BID_MASK)
11890 /*! @} */
11891 
11892 /* The count of CAAM_DMA_AIDL_MAP_LS */
11893 #define CAAM_DMA_AIDL_MAP_LS_COUNT               (1U)
11894 
11895 /*! @name DMA_AIDM_MAP_MS - DMA0_AIDM_MAP_MS */
11896 /*! @{ */
11897 
11898 #define CAAM_DMA_AIDM_MAP_MS_AID12_BID_MASK      (0xFFU)
11899 #define CAAM_DMA_AIDM_MAP_MS_AID12_BID_SHIFT     (0U)
11900 #define CAAM_DMA_AIDM_MAP_MS_AID12_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID12_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID12_BID_MASK)
11901 
11902 #define CAAM_DMA_AIDM_MAP_MS_AID13_BID_MASK      (0xFF00U)
11903 #define CAAM_DMA_AIDM_MAP_MS_AID13_BID_SHIFT     (8U)
11904 #define CAAM_DMA_AIDM_MAP_MS_AID13_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID13_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID13_BID_MASK)
11905 
11906 #define CAAM_DMA_AIDM_MAP_MS_AID14_BID_MASK      (0xFF0000U)
11907 #define CAAM_DMA_AIDM_MAP_MS_AID14_BID_SHIFT     (16U)
11908 #define CAAM_DMA_AIDM_MAP_MS_AID14_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID14_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID14_BID_MASK)
11909 
11910 #define CAAM_DMA_AIDM_MAP_MS_AID15_BID_MASK      (0xFF000000U)
11911 #define CAAM_DMA_AIDM_MAP_MS_AID15_BID_SHIFT     (24U)
11912 #define CAAM_DMA_AIDM_MAP_MS_AID15_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID15_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID15_BID_MASK)
11913 /*! @} */
11914 
11915 /* The count of CAAM_DMA_AIDM_MAP_MS */
11916 #define CAAM_DMA_AIDM_MAP_MS_COUNT               (1U)
11917 
11918 /*! @name DMA_AIDM_MAP_LS - DMA0_AIDM_MAP_LS */
11919 /*! @{ */
11920 
11921 #define CAAM_DMA_AIDM_MAP_LS_AID8_BID_MASK       (0xFFU)
11922 #define CAAM_DMA_AIDM_MAP_LS_AID8_BID_SHIFT      (0U)
11923 #define CAAM_DMA_AIDM_MAP_LS_AID8_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID8_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID8_BID_MASK)
11924 
11925 #define CAAM_DMA_AIDM_MAP_LS_AID9_BID_MASK       (0xFF00U)
11926 #define CAAM_DMA_AIDM_MAP_LS_AID9_BID_SHIFT      (8U)
11927 #define CAAM_DMA_AIDM_MAP_LS_AID9_BID(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID9_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID9_BID_MASK)
11928 
11929 #define CAAM_DMA_AIDM_MAP_LS_AID10_BID_MASK      (0xFF0000U)
11930 #define CAAM_DMA_AIDM_MAP_LS_AID10_BID_SHIFT     (16U)
11931 #define CAAM_DMA_AIDM_MAP_LS_AID10_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID10_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID10_BID_MASK)
11932 
11933 #define CAAM_DMA_AIDM_MAP_LS_AID11_BID_MASK      (0xFF000000U)
11934 #define CAAM_DMA_AIDM_MAP_LS_AID11_BID_SHIFT     (24U)
11935 #define CAAM_DMA_AIDM_MAP_LS_AID11_BID(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID11_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID11_BID_MASK)
11936 /*! @} */
11937 
11938 /* The count of CAAM_DMA_AIDM_MAP_LS */
11939 #define CAAM_DMA_AIDM_MAP_LS_COUNT               (1U)
11940 
11941 /*! @name DMA0_AID_ENB - DMA0 AXI ID Enable Register */
11942 /*! @{ */
11943 
11944 #define CAAM_DMA0_AID_ENB_AID0E_MASK             (0x1U)
11945 #define CAAM_DMA0_AID_ENB_AID0E_SHIFT            (0U)
11946 #define CAAM_DMA0_AID_ENB_AID0E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID0E_SHIFT)) & CAAM_DMA0_AID_ENB_AID0E_MASK)
11947 
11948 #define CAAM_DMA0_AID_ENB_AID1E_MASK             (0x2U)
11949 #define CAAM_DMA0_AID_ENB_AID1E_SHIFT            (1U)
11950 #define CAAM_DMA0_AID_ENB_AID1E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID1E_SHIFT)) & CAAM_DMA0_AID_ENB_AID1E_MASK)
11951 
11952 #define CAAM_DMA0_AID_ENB_AID2E_MASK             (0x4U)
11953 #define CAAM_DMA0_AID_ENB_AID2E_SHIFT            (2U)
11954 #define CAAM_DMA0_AID_ENB_AID2E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID2E_SHIFT)) & CAAM_DMA0_AID_ENB_AID2E_MASK)
11955 
11956 #define CAAM_DMA0_AID_ENB_AID3E_MASK             (0x8U)
11957 #define CAAM_DMA0_AID_ENB_AID3E_SHIFT            (3U)
11958 #define CAAM_DMA0_AID_ENB_AID3E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID3E_SHIFT)) & CAAM_DMA0_AID_ENB_AID3E_MASK)
11959 
11960 #define CAAM_DMA0_AID_ENB_AID4E_MASK             (0x10U)
11961 #define CAAM_DMA0_AID_ENB_AID4E_SHIFT            (4U)
11962 #define CAAM_DMA0_AID_ENB_AID4E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID4E_SHIFT)) & CAAM_DMA0_AID_ENB_AID4E_MASK)
11963 
11964 #define CAAM_DMA0_AID_ENB_AID5E_MASK             (0x20U)
11965 #define CAAM_DMA0_AID_ENB_AID5E_SHIFT            (5U)
11966 #define CAAM_DMA0_AID_ENB_AID5E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID5E_SHIFT)) & CAAM_DMA0_AID_ENB_AID5E_MASK)
11967 
11968 #define CAAM_DMA0_AID_ENB_AID6E_MASK             (0x40U)
11969 #define CAAM_DMA0_AID_ENB_AID6E_SHIFT            (6U)
11970 #define CAAM_DMA0_AID_ENB_AID6E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID6E_SHIFT)) & CAAM_DMA0_AID_ENB_AID6E_MASK)
11971 
11972 #define CAAM_DMA0_AID_ENB_AID7E_MASK             (0x80U)
11973 #define CAAM_DMA0_AID_ENB_AID7E_SHIFT            (7U)
11974 #define CAAM_DMA0_AID_ENB_AID7E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID7E_SHIFT)) & CAAM_DMA0_AID_ENB_AID7E_MASK)
11975 
11976 #define CAAM_DMA0_AID_ENB_AID8E_MASK             (0x100U)
11977 #define CAAM_DMA0_AID_ENB_AID8E_SHIFT            (8U)
11978 #define CAAM_DMA0_AID_ENB_AID8E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID8E_SHIFT)) & CAAM_DMA0_AID_ENB_AID8E_MASK)
11979 
11980 #define CAAM_DMA0_AID_ENB_AID9E_MASK             (0x200U)
11981 #define CAAM_DMA0_AID_ENB_AID9E_SHIFT            (9U)
11982 #define CAAM_DMA0_AID_ENB_AID9E(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID9E_SHIFT)) & CAAM_DMA0_AID_ENB_AID9E_MASK)
11983 
11984 #define CAAM_DMA0_AID_ENB_AID10E_MASK            (0x400U)
11985 #define CAAM_DMA0_AID_ENB_AID10E_SHIFT           (10U)
11986 #define CAAM_DMA0_AID_ENB_AID10E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID10E_SHIFT)) & CAAM_DMA0_AID_ENB_AID10E_MASK)
11987 
11988 #define CAAM_DMA0_AID_ENB_AID11E_MASK            (0x800U)
11989 #define CAAM_DMA0_AID_ENB_AID11E_SHIFT           (11U)
11990 #define CAAM_DMA0_AID_ENB_AID11E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID11E_SHIFT)) & CAAM_DMA0_AID_ENB_AID11E_MASK)
11991 
11992 #define CAAM_DMA0_AID_ENB_AID12E_MASK            (0x1000U)
11993 #define CAAM_DMA0_AID_ENB_AID12E_SHIFT           (12U)
11994 #define CAAM_DMA0_AID_ENB_AID12E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID12E_SHIFT)) & CAAM_DMA0_AID_ENB_AID12E_MASK)
11995 
11996 #define CAAM_DMA0_AID_ENB_AID13E_MASK            (0x2000U)
11997 #define CAAM_DMA0_AID_ENB_AID13E_SHIFT           (13U)
11998 #define CAAM_DMA0_AID_ENB_AID13E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID13E_SHIFT)) & CAAM_DMA0_AID_ENB_AID13E_MASK)
11999 
12000 #define CAAM_DMA0_AID_ENB_AID14E_MASK            (0x4000U)
12001 #define CAAM_DMA0_AID_ENB_AID14E_SHIFT           (14U)
12002 #define CAAM_DMA0_AID_ENB_AID14E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID14E_SHIFT)) & CAAM_DMA0_AID_ENB_AID14E_MASK)
12003 
12004 #define CAAM_DMA0_AID_ENB_AID15E_MASK            (0x8000U)
12005 #define CAAM_DMA0_AID_ENB_AID15E_SHIFT           (15U)
12006 #define CAAM_DMA0_AID_ENB_AID15E(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID15E_SHIFT)) & CAAM_DMA0_AID_ENB_AID15E_MASK)
12007 /*! @} */
12008 
12009 /*! @name DMA0_ARD_TC - DMA0 AXI Read Timing Check Register */
12010 /*! @{ */
12011 
12012 #define CAAM_DMA0_ARD_TC_ARSC_MASK               (0xFFFFFU)
12013 #define CAAM_DMA0_ARD_TC_ARSC_SHIFT              (0U)
12014 #define CAAM_DMA0_ARD_TC_ARSC(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARSC_SHIFT)) & CAAM_DMA0_ARD_TC_ARSC_MASK)
12015 
12016 #define CAAM_DMA0_ARD_TC_ARLC_MASK               (0xFFFFF000000U)
12017 #define CAAM_DMA0_ARD_TC_ARLC_SHIFT              (24U)
12018 #define CAAM_DMA0_ARD_TC_ARLC(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARLC_SHIFT)) & CAAM_DMA0_ARD_TC_ARLC_MASK)
12019 
12020 #define CAAM_DMA0_ARD_TC_ARL_MASK                (0xFFF000000000000U)
12021 #define CAAM_DMA0_ARD_TC_ARL_SHIFT               (48U)
12022 #define CAAM_DMA0_ARD_TC_ARL(x)                  (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARL_SHIFT)) & CAAM_DMA0_ARD_TC_ARL_MASK)
12023 
12024 #define CAAM_DMA0_ARD_TC_ARTL_MASK               (0x1000000000000000U)
12025 #define CAAM_DMA0_ARD_TC_ARTL_SHIFT              (60U)
12026 #define CAAM_DMA0_ARD_TC_ARTL(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTL_SHIFT)) & CAAM_DMA0_ARD_TC_ARTL_MASK)
12027 
12028 #define CAAM_DMA0_ARD_TC_ARTT_MASK               (0x2000000000000000U)
12029 #define CAAM_DMA0_ARD_TC_ARTT_SHIFT              (61U)
12030 #define CAAM_DMA0_ARD_TC_ARTT(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTT_SHIFT)) & CAAM_DMA0_ARD_TC_ARTT_MASK)
12031 
12032 #define CAAM_DMA0_ARD_TC_ARCT_MASK               (0x4000000000000000U)
12033 #define CAAM_DMA0_ARD_TC_ARCT_SHIFT              (62U)
12034 #define CAAM_DMA0_ARD_TC_ARCT(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARCT_SHIFT)) & CAAM_DMA0_ARD_TC_ARCT_MASK)
12035 
12036 #define CAAM_DMA0_ARD_TC_ARTCE_MASK              (0x8000000000000000U)
12037 #define CAAM_DMA0_ARD_TC_ARTCE_SHIFT             (63U)
12038 #define CAAM_DMA0_ARD_TC_ARTCE(x)                (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTCE_SHIFT)) & CAAM_DMA0_ARD_TC_ARTCE_MASK)
12039 /*! @} */
12040 
12041 /*! @name DMA0_ARD_LAT - DMA0 Read Timing Check Latency Register */
12042 /*! @{ */
12043 
12044 #define CAAM_DMA0_ARD_LAT_SARL_MASK              (0xFFFFFFFFU)
12045 #define CAAM_DMA0_ARD_LAT_SARL_SHIFT             (0U)
12046 #define CAAM_DMA0_ARD_LAT_SARL(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_ARD_LAT_SARL_SHIFT)) & CAAM_DMA0_ARD_LAT_SARL_MASK)
12047 /*! @} */
12048 
12049 /*! @name DMA0_AWR_TC - DMA0 AXI Write Timing Check Register */
12050 /*! @{ */
12051 
12052 #define CAAM_DMA0_AWR_TC_AWSC_MASK               (0xFFFFFU)
12053 #define CAAM_DMA0_AWR_TC_AWSC_SHIFT              (0U)
12054 #define CAAM_DMA0_AWR_TC_AWSC(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWSC_SHIFT)) & CAAM_DMA0_AWR_TC_AWSC_MASK)
12055 
12056 #define CAAM_DMA0_AWR_TC_AWLC_MASK               (0xFFFFF000000U)
12057 #define CAAM_DMA0_AWR_TC_AWLC_SHIFT              (24U)
12058 #define CAAM_DMA0_AWR_TC_AWLC(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWLC_SHIFT)) & CAAM_DMA0_AWR_TC_AWLC_MASK)
12059 
12060 #define CAAM_DMA0_AWR_TC_AWL_MASK                (0xFFF000000000000U)
12061 #define CAAM_DMA0_AWR_TC_AWL_SHIFT               (48U)
12062 #define CAAM_DMA0_AWR_TC_AWL(x)                  (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWL_SHIFT)) & CAAM_DMA0_AWR_TC_AWL_MASK)
12063 
12064 #define CAAM_DMA0_AWR_TC_AWTT_MASK               (0x2000000000000000U)
12065 #define CAAM_DMA0_AWR_TC_AWTT_SHIFT              (61U)
12066 #define CAAM_DMA0_AWR_TC_AWTT(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWTT_SHIFT)) & CAAM_DMA0_AWR_TC_AWTT_MASK)
12067 
12068 #define CAAM_DMA0_AWR_TC_AWCT_MASK               (0x4000000000000000U)
12069 #define CAAM_DMA0_AWR_TC_AWCT_SHIFT              (62U)
12070 #define CAAM_DMA0_AWR_TC_AWCT(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWCT_SHIFT)) & CAAM_DMA0_AWR_TC_AWCT_MASK)
12071 
12072 #define CAAM_DMA0_AWR_TC_AWTCE_MASK              (0x8000000000000000U)
12073 #define CAAM_DMA0_AWR_TC_AWTCE_SHIFT             (63U)
12074 #define CAAM_DMA0_AWR_TC_AWTCE(x)                (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWTCE_SHIFT)) & CAAM_DMA0_AWR_TC_AWTCE_MASK)
12075 /*! @} */
12076 
12077 /*! @name DMA0_AWR_LAT - DMA0 Write Timing Check Latency Register */
12078 /*! @{ */
12079 
12080 #define CAAM_DMA0_AWR_LAT_SAWL_MASK              (0xFFFFFFFFU)
12081 #define CAAM_DMA0_AWR_LAT_SAWL_SHIFT             (0U)
12082 #define CAAM_DMA0_AWR_LAT_SAWL(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AWR_LAT_SAWL_SHIFT)) & CAAM_DMA0_AWR_LAT_SAWL_MASK)
12083 /*! @} */
12084 
12085 /*! @name MPPKR - Manufacturing Protection Private Key Register */
12086 /*! @{ */
12087 
12088 #define CAAM_MPPKR_MPPrivK_MASK                  (0xFFU)
12089 #define CAAM_MPPKR_MPPrivK_SHIFT                 (0U)
12090 #define CAAM_MPPKR_MPPrivK(x)                    (((uint8_t)(((uint8_t)(x)) << CAAM_MPPKR_MPPrivK_SHIFT)) & CAAM_MPPKR_MPPrivK_MASK)
12091 /*! @} */
12092 
12093 /* The count of CAAM_MPPKR */
12094 #define CAAM_MPPKR_COUNT                         (64U)
12095 
12096 /*! @name MPMR - Manufacturing Protection Message Register */
12097 /*! @{ */
12098 
12099 #define CAAM_MPMR_MPMSG_MASK                     (0xFFU)
12100 #define CAAM_MPMR_MPMSG_SHIFT                    (0U)
12101 #define CAAM_MPMR_MPMSG(x)                       (((uint8_t)(((uint8_t)(x)) << CAAM_MPMR_MPMSG_SHIFT)) & CAAM_MPMR_MPMSG_MASK)
12102 /*! @} */
12103 
12104 /* The count of CAAM_MPMR */
12105 #define CAAM_MPMR_COUNT                          (32U)
12106 
12107 /*! @name MPTESTR - Manufacturing Protection Test Register */
12108 /*! @{ */
12109 
12110 #define CAAM_MPTESTR_TEST_VALUE_MASK             (0xFFU)
12111 #define CAAM_MPTESTR_TEST_VALUE_SHIFT            (0U)
12112 #define CAAM_MPTESTR_TEST_VALUE(x)               (((uint8_t)(((uint8_t)(x)) << CAAM_MPTESTR_TEST_VALUE_SHIFT)) & CAAM_MPTESTR_TEST_VALUE_MASK)
12113 /*! @} */
12114 
12115 /* The count of CAAM_MPTESTR */
12116 #define CAAM_MPTESTR_COUNT                       (32U)
12117 
12118 /*! @name MPECC - Manufacturing Protection ECC Register */
12119 /*! @{ */
12120 
12121 #define CAAM_MPECC_MP_SYNDROME_MASK              (0x1FF0000U)
12122 #define CAAM_MPECC_MP_SYNDROME_SHIFT             (16U)
12123 /*! MP_SYNDROME
12124  *  0b000000000..The MP Key in the SFP passes the ECC check.
12125  *  0b000000001-0b111111111..The MP Key in the SFP fails the ECC check, and this is the ECC failure syndrome.
12126  */
12127 #define CAAM_MPECC_MP_SYNDROME(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_MPECC_MP_SYNDROME_SHIFT)) & CAAM_MPECC_MP_SYNDROME_MASK)
12128 
12129 #define CAAM_MPECC_MP_ZERO_MASK                  (0x8000000U)
12130 #define CAAM_MPECC_MP_ZERO_SHIFT                 (27U)
12131 /*! MP_ZERO
12132  *  0b0..The MP Key in the SFP has a non-zero value.
12133  *  0b1..The MP Key in the SFP is all zeros (unprogrammed).
12134  */
12135 #define CAAM_MPECC_MP_ZERO(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_MPECC_MP_ZERO_SHIFT)) & CAAM_MPECC_MP_ZERO_MASK)
12136 /*! @} */
12137 
12138 /*! @name JDKEKR - Job Descriptor Key Encryption Key Register */
12139 /*! @{ */
12140 
12141 #define CAAM_JDKEKR_JDKEK_MASK                   (0xFFFFFFFFU)
12142 #define CAAM_JDKEKR_JDKEK_SHIFT                  (0U)
12143 #define CAAM_JDKEKR_JDKEK(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_JDKEKR_JDKEK_SHIFT)) & CAAM_JDKEKR_JDKEK_MASK)
12144 /*! @} */
12145 
12146 /* The count of CAAM_JDKEKR */
12147 #define CAAM_JDKEKR_COUNT                        (8U)
12148 
12149 /*! @name TDKEKR - Trusted Descriptor Key Encryption Key Register */
12150 /*! @{ */
12151 
12152 #define CAAM_TDKEKR_TDKEK_MASK                   (0xFFFFFFFFU)
12153 #define CAAM_TDKEKR_TDKEK_SHIFT                  (0U)
12154 #define CAAM_TDKEKR_TDKEK(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_TDKEKR_TDKEK_SHIFT)) & CAAM_TDKEKR_TDKEK_MASK)
12155 /*! @} */
12156 
12157 /* The count of CAAM_TDKEKR */
12158 #define CAAM_TDKEKR_COUNT                        (8U)
12159 
12160 /*! @name TDSKR - Trusted Descriptor Signing Key Register */
12161 /*! @{ */
12162 
12163 #define CAAM_TDSKR_TDSK_MASK                     (0xFFFFFFFFU)
12164 #define CAAM_TDSKR_TDSK_SHIFT                    (0U)
12165 #define CAAM_TDSKR_TDSK(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_TDSKR_TDSK_SHIFT)) & CAAM_TDSKR_TDSK_MASK)
12166 /*! @} */
12167 
12168 /* The count of CAAM_TDSKR */
12169 #define CAAM_TDSKR_COUNT                         (8U)
12170 
12171 /*! @name SKNR - Secure Key Nonce Register */
12172 /*! @{ */
12173 
12174 #define CAAM_SKNR_SK_NONCE_LS_MASK               (0xFFFFFFFFU)
12175 #define CAAM_SKNR_SK_NONCE_LS_SHIFT              (0U)
12176 #define CAAM_SKNR_SK_NONCE_LS(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_SKNR_SK_NONCE_LS_SHIFT)) & CAAM_SKNR_SK_NONCE_LS_MASK)
12177 
12178 #define CAAM_SKNR_SK_NONCE_MS_MASK               (0x7FFF00000000U)
12179 #define CAAM_SKNR_SK_NONCE_MS_SHIFT              (32U)
12180 #define CAAM_SKNR_SK_NONCE_MS(x)                 (((uint64_t)(((uint64_t)(x)) << CAAM_SKNR_SK_NONCE_MS_SHIFT)) & CAAM_SKNR_SK_NONCE_MS_MASK)
12181 /*! @} */
12182 
12183 /*! @name DMA_STA - DMA Status Register */
12184 /*! @{ */
12185 
12186 #define CAAM_DMA_STA_DMA0_ETIF_MASK              (0x1FU)
12187 #define CAAM_DMA_STA_DMA0_ETIF_SHIFT             (0U)
12188 #define CAAM_DMA_STA_DMA0_ETIF(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_ETIF_SHIFT)) & CAAM_DMA_STA_DMA0_ETIF_MASK)
12189 
12190 #define CAAM_DMA_STA_DMA0_ITIF_MASK              (0x20U)
12191 #define CAAM_DMA_STA_DMA0_ITIF_SHIFT             (5U)
12192 #define CAAM_DMA_STA_DMA0_ITIF(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_ITIF_SHIFT)) & CAAM_DMA_STA_DMA0_ITIF_MASK)
12193 
12194 #define CAAM_DMA_STA_DMA0_IDLE_MASK              (0x80U)
12195 #define CAAM_DMA_STA_DMA0_IDLE_SHIFT             (7U)
12196 #define CAAM_DMA_STA_DMA0_IDLE(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_IDLE_SHIFT)) & CAAM_DMA_STA_DMA0_IDLE_MASK)
12197 /*! @} */
12198 
12199 /*! @name DMA_X_AID_7_4_MAP - DMA_X_AID_7_4_MAP */
12200 /*! @{ */
12201 
12202 #define CAAM_DMA_X_AID_7_4_MAP_AID4_BID_MASK     (0xFFU)
12203 #define CAAM_DMA_X_AID_7_4_MAP_AID4_BID_SHIFT    (0U)
12204 #define CAAM_DMA_X_AID_7_4_MAP_AID4_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID4_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID4_BID_MASK)
12205 
12206 #define CAAM_DMA_X_AID_7_4_MAP_AID5_BID_MASK     (0xFF00U)
12207 #define CAAM_DMA_X_AID_7_4_MAP_AID5_BID_SHIFT    (8U)
12208 #define CAAM_DMA_X_AID_7_4_MAP_AID5_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID5_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID5_BID_MASK)
12209 
12210 #define CAAM_DMA_X_AID_7_4_MAP_AID6_BID_MASK     (0xFF0000U)
12211 #define CAAM_DMA_X_AID_7_4_MAP_AID6_BID_SHIFT    (16U)
12212 #define CAAM_DMA_X_AID_7_4_MAP_AID6_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID6_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID6_BID_MASK)
12213 
12214 #define CAAM_DMA_X_AID_7_4_MAP_AID7_BID_MASK     (0xFF000000U)
12215 #define CAAM_DMA_X_AID_7_4_MAP_AID7_BID_SHIFT    (24U)
12216 #define CAAM_DMA_X_AID_7_4_MAP_AID7_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID7_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID7_BID_MASK)
12217 /*! @} */
12218 
12219 /*! @name DMA_X_AID_3_0_MAP - DMA_X_AID_3_0_MAP */
12220 /*! @{ */
12221 
12222 #define CAAM_DMA_X_AID_3_0_MAP_AID0_BID_MASK     (0xFFU)
12223 #define CAAM_DMA_X_AID_3_0_MAP_AID0_BID_SHIFT    (0U)
12224 #define CAAM_DMA_X_AID_3_0_MAP_AID0_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID0_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID0_BID_MASK)
12225 
12226 #define CAAM_DMA_X_AID_3_0_MAP_AID1_BID_MASK     (0xFF00U)
12227 #define CAAM_DMA_X_AID_3_0_MAP_AID1_BID_SHIFT    (8U)
12228 #define CAAM_DMA_X_AID_3_0_MAP_AID1_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID1_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID1_BID_MASK)
12229 
12230 #define CAAM_DMA_X_AID_3_0_MAP_AID2_BID_MASK     (0xFF0000U)
12231 #define CAAM_DMA_X_AID_3_0_MAP_AID2_BID_SHIFT    (16U)
12232 #define CAAM_DMA_X_AID_3_0_MAP_AID2_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID2_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID2_BID_MASK)
12233 
12234 #define CAAM_DMA_X_AID_3_0_MAP_AID3_BID_MASK     (0xFF000000U)
12235 #define CAAM_DMA_X_AID_3_0_MAP_AID3_BID_SHIFT    (24U)
12236 #define CAAM_DMA_X_AID_3_0_MAP_AID3_BID(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID3_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID3_BID_MASK)
12237 /*! @} */
12238 
12239 /*! @name DMA_X_AID_15_12_MAP - DMA_X_AID_15_12_MAP */
12240 /*! @{ */
12241 
12242 #define CAAM_DMA_X_AID_15_12_MAP_AID12_BID_MASK  (0xFFU)
12243 #define CAAM_DMA_X_AID_15_12_MAP_AID12_BID_SHIFT (0U)
12244 #define CAAM_DMA_X_AID_15_12_MAP_AID12_BID(x)    (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID12_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID12_BID_MASK)
12245 
12246 #define CAAM_DMA_X_AID_15_12_MAP_AID13_BID_MASK  (0xFF00U)
12247 #define CAAM_DMA_X_AID_15_12_MAP_AID13_BID_SHIFT (8U)
12248 #define CAAM_DMA_X_AID_15_12_MAP_AID13_BID(x)    (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID13_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID13_BID_MASK)
12249 
12250 #define CAAM_DMA_X_AID_15_12_MAP_AID14_BID_MASK  (0xFF0000U)
12251 #define CAAM_DMA_X_AID_15_12_MAP_AID14_BID_SHIFT (16U)
12252 #define CAAM_DMA_X_AID_15_12_MAP_AID14_BID(x)    (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID14_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID14_BID_MASK)
12253 
12254 #define CAAM_DMA_X_AID_15_12_MAP_AID15_BID_MASK  (0xFF000000U)
12255 #define CAAM_DMA_X_AID_15_12_MAP_AID15_BID_SHIFT (24U)
12256 #define CAAM_DMA_X_AID_15_12_MAP_AID15_BID(x)    (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID15_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID15_BID_MASK)
12257 /*! @} */
12258 
12259 /*! @name DMA_X_AID_11_8_MAP - DMA_X_AID_11_8_MAP */
12260 /*! @{ */
12261 
12262 #define CAAM_DMA_X_AID_11_8_MAP_AID8_BID_MASK    (0xFFU)
12263 #define CAAM_DMA_X_AID_11_8_MAP_AID8_BID_SHIFT   (0U)
12264 #define CAAM_DMA_X_AID_11_8_MAP_AID8_BID(x)      (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID8_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID8_BID_MASK)
12265 
12266 #define CAAM_DMA_X_AID_11_8_MAP_AID9_BID_MASK    (0xFF00U)
12267 #define CAAM_DMA_X_AID_11_8_MAP_AID9_BID_SHIFT   (8U)
12268 #define CAAM_DMA_X_AID_11_8_MAP_AID9_BID(x)      (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID9_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID9_BID_MASK)
12269 
12270 #define CAAM_DMA_X_AID_11_8_MAP_AID10_BID_MASK   (0xFF0000U)
12271 #define CAAM_DMA_X_AID_11_8_MAP_AID10_BID_SHIFT  (16U)
12272 #define CAAM_DMA_X_AID_11_8_MAP_AID10_BID(x)     (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID10_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID10_BID_MASK)
12273 
12274 #define CAAM_DMA_X_AID_11_8_MAP_AID11_BID_MASK   (0xFF000000U)
12275 #define CAAM_DMA_X_AID_11_8_MAP_AID11_BID_SHIFT  (24U)
12276 #define CAAM_DMA_X_AID_11_8_MAP_AID11_BID(x)     (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID11_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID11_BID_MASK)
12277 /*! @} */
12278 
12279 /*! @name DMA_X_AID_15_0_EN - DMA_X AXI ID Map Enable Register */
12280 /*! @{ */
12281 
12282 #define CAAM_DMA_X_AID_15_0_EN_AID0E_MASK        (0x1U)
12283 #define CAAM_DMA_X_AID_15_0_EN_AID0E_SHIFT       (0U)
12284 #define CAAM_DMA_X_AID_15_0_EN_AID0E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID0E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID0E_MASK)
12285 
12286 #define CAAM_DMA_X_AID_15_0_EN_AID1E_MASK        (0x2U)
12287 #define CAAM_DMA_X_AID_15_0_EN_AID1E_SHIFT       (1U)
12288 #define CAAM_DMA_X_AID_15_0_EN_AID1E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID1E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID1E_MASK)
12289 
12290 #define CAAM_DMA_X_AID_15_0_EN_AID2E_MASK        (0x4U)
12291 #define CAAM_DMA_X_AID_15_0_EN_AID2E_SHIFT       (2U)
12292 #define CAAM_DMA_X_AID_15_0_EN_AID2E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID2E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID2E_MASK)
12293 
12294 #define CAAM_DMA_X_AID_15_0_EN_AID3E_MASK        (0x8U)
12295 #define CAAM_DMA_X_AID_15_0_EN_AID3E_SHIFT       (3U)
12296 #define CAAM_DMA_X_AID_15_0_EN_AID3E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID3E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID3E_MASK)
12297 
12298 #define CAAM_DMA_X_AID_15_0_EN_AID4E_MASK        (0x10U)
12299 #define CAAM_DMA_X_AID_15_0_EN_AID4E_SHIFT       (4U)
12300 #define CAAM_DMA_X_AID_15_0_EN_AID4E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID4E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID4E_MASK)
12301 
12302 #define CAAM_DMA_X_AID_15_0_EN_AID5E_MASK        (0x20U)
12303 #define CAAM_DMA_X_AID_15_0_EN_AID5E_SHIFT       (5U)
12304 #define CAAM_DMA_X_AID_15_0_EN_AID5E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID5E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID5E_MASK)
12305 
12306 #define CAAM_DMA_X_AID_15_0_EN_AID6E_MASK        (0x40U)
12307 #define CAAM_DMA_X_AID_15_0_EN_AID6E_SHIFT       (6U)
12308 #define CAAM_DMA_X_AID_15_0_EN_AID6E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID6E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID6E_MASK)
12309 
12310 #define CAAM_DMA_X_AID_15_0_EN_AID7E_MASK        (0x80U)
12311 #define CAAM_DMA_X_AID_15_0_EN_AID7E_SHIFT       (7U)
12312 #define CAAM_DMA_X_AID_15_0_EN_AID7E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID7E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID7E_MASK)
12313 
12314 #define CAAM_DMA_X_AID_15_0_EN_AID8E_MASK        (0x100U)
12315 #define CAAM_DMA_X_AID_15_0_EN_AID8E_SHIFT       (8U)
12316 #define CAAM_DMA_X_AID_15_0_EN_AID8E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID8E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID8E_MASK)
12317 
12318 #define CAAM_DMA_X_AID_15_0_EN_AID9E_MASK        (0x200U)
12319 #define CAAM_DMA_X_AID_15_0_EN_AID9E_SHIFT       (9U)
12320 #define CAAM_DMA_X_AID_15_0_EN_AID9E(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID9E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID9E_MASK)
12321 
12322 #define CAAM_DMA_X_AID_15_0_EN_AID10E_MASK       (0x400U)
12323 #define CAAM_DMA_X_AID_15_0_EN_AID10E_SHIFT      (10U)
12324 #define CAAM_DMA_X_AID_15_0_EN_AID10E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID10E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID10E_MASK)
12325 
12326 #define CAAM_DMA_X_AID_15_0_EN_AID11E_MASK       (0x800U)
12327 #define CAAM_DMA_X_AID_15_0_EN_AID11E_SHIFT      (11U)
12328 #define CAAM_DMA_X_AID_15_0_EN_AID11E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID11E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID11E_MASK)
12329 
12330 #define CAAM_DMA_X_AID_15_0_EN_AID12E_MASK       (0x1000U)
12331 #define CAAM_DMA_X_AID_15_0_EN_AID12E_SHIFT      (12U)
12332 #define CAAM_DMA_X_AID_15_0_EN_AID12E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID12E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID12E_MASK)
12333 
12334 #define CAAM_DMA_X_AID_15_0_EN_AID13E_MASK       (0x2000U)
12335 #define CAAM_DMA_X_AID_15_0_EN_AID13E_SHIFT      (13U)
12336 #define CAAM_DMA_X_AID_15_0_EN_AID13E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID13E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID13E_MASK)
12337 
12338 #define CAAM_DMA_X_AID_15_0_EN_AID14E_MASK       (0x4000U)
12339 #define CAAM_DMA_X_AID_15_0_EN_AID14E_SHIFT      (14U)
12340 #define CAAM_DMA_X_AID_15_0_EN_AID14E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID14E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID14E_MASK)
12341 
12342 #define CAAM_DMA_X_AID_15_0_EN_AID15E_MASK       (0x8000U)
12343 #define CAAM_DMA_X_AID_15_0_EN_AID15E_SHIFT      (15U)
12344 #define CAAM_DMA_X_AID_15_0_EN_AID15E(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID15E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID15E_MASK)
12345 /*! @} */
12346 
12347 /*! @name DMA_X_ARTC_CTL - DMA_X AXI Read Timing Check Control Register */
12348 /*! @{ */
12349 
12350 #define CAAM_DMA_X_ARTC_CTL_ART_MASK             (0xFFFU)
12351 #define CAAM_DMA_X_ARTC_CTL_ART_SHIFT            (0U)
12352 #define CAAM_DMA_X_ARTC_CTL_ART(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ART_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ART_MASK)
12353 
12354 #define CAAM_DMA_X_ARTC_CTL_ARL_MASK             (0xFFF0000U)
12355 #define CAAM_DMA_X_ARTC_CTL_ARL_SHIFT            (16U)
12356 #define CAAM_DMA_X_ARTC_CTL_ARL(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARL_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARL_MASK)
12357 
12358 #define CAAM_DMA_X_ARTC_CTL_ARTL_MASK            (0x10000000U)
12359 #define CAAM_DMA_X_ARTC_CTL_ARTL_SHIFT           (28U)
12360 #define CAAM_DMA_X_ARTC_CTL_ARTL(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTL_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTL_MASK)
12361 
12362 #define CAAM_DMA_X_ARTC_CTL_ARTT_MASK            (0x20000000U)
12363 #define CAAM_DMA_X_ARTC_CTL_ARTT_SHIFT           (29U)
12364 #define CAAM_DMA_X_ARTC_CTL_ARTT(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTT_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTT_MASK)
12365 
12366 #define CAAM_DMA_X_ARTC_CTL_ARCT_MASK            (0x40000000U)
12367 #define CAAM_DMA_X_ARTC_CTL_ARCT_SHIFT           (30U)
12368 #define CAAM_DMA_X_ARTC_CTL_ARCT(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARCT_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARCT_MASK)
12369 
12370 #define CAAM_DMA_X_ARTC_CTL_ARTCE_MASK           (0x80000000U)
12371 #define CAAM_DMA_X_ARTC_CTL_ARTCE_SHIFT          (31U)
12372 #define CAAM_DMA_X_ARTC_CTL_ARTCE(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTCE_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTCE_MASK)
12373 /*! @} */
12374 
12375 /*! @name DMA_X_ARTC_LC - DMA_X AXI Read Timing Check Late Count Register */
12376 /*! @{ */
12377 
12378 #define CAAM_DMA_X_ARTC_LC_ARLC_MASK             (0xFFFFFU)
12379 #define CAAM_DMA_X_ARTC_LC_ARLC_SHIFT            (0U)
12380 #define CAAM_DMA_X_ARTC_LC_ARLC(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_LC_ARLC_SHIFT)) & CAAM_DMA_X_ARTC_LC_ARLC_MASK)
12381 /*! @} */
12382 
12383 /*! @name DMA_X_ARTC_SC - DMA_X AXI Read Timing Check Sample Count Register */
12384 /*! @{ */
12385 
12386 #define CAAM_DMA_X_ARTC_SC_ARSC_MASK             (0xFFFFFU)
12387 #define CAAM_DMA_X_ARTC_SC_ARSC_SHIFT            (0U)
12388 #define CAAM_DMA_X_ARTC_SC_ARSC(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_SC_ARSC_SHIFT)) & CAAM_DMA_X_ARTC_SC_ARSC_MASK)
12389 /*! @} */
12390 
12391 /*! @name DMA_X_ARTC_LAT - DMA_X Read Timing Check Latency Register */
12392 /*! @{ */
12393 
12394 #define CAAM_DMA_X_ARTC_LAT_SARL_MASK            (0xFFFFFFFFU)
12395 #define CAAM_DMA_X_ARTC_LAT_SARL_SHIFT           (0U)
12396 #define CAAM_DMA_X_ARTC_LAT_SARL(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_LAT_SARL_SHIFT)) & CAAM_DMA_X_ARTC_LAT_SARL_MASK)
12397 /*! @} */
12398 
12399 /*! @name DMA_X_AWTC_CTL - DMA_X AXI Write Timing Check Control Register */
12400 /*! @{ */
12401 
12402 #define CAAM_DMA_X_AWTC_CTL_AWT_MASK             (0xFFFU)
12403 #define CAAM_DMA_X_AWTC_CTL_AWT_SHIFT            (0U)
12404 #define CAAM_DMA_X_AWTC_CTL_AWT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWT_MASK)
12405 
12406 #define CAAM_DMA_X_AWTC_CTL_AWL_MASK             (0xFFF0000U)
12407 #define CAAM_DMA_X_AWTC_CTL_AWL_SHIFT            (16U)
12408 #define CAAM_DMA_X_AWTC_CTL_AWL(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWL_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWL_MASK)
12409 
12410 #define CAAM_DMA_X_AWTC_CTL_AWTT_MASK            (0x20000000U)
12411 #define CAAM_DMA_X_AWTC_CTL_AWTT_SHIFT           (29U)
12412 #define CAAM_DMA_X_AWTC_CTL_AWTT(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWTT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWTT_MASK)
12413 
12414 #define CAAM_DMA_X_AWTC_CTL_AWCT_MASK            (0x40000000U)
12415 #define CAAM_DMA_X_AWTC_CTL_AWCT_SHIFT           (30U)
12416 #define CAAM_DMA_X_AWTC_CTL_AWCT(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWCT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWCT_MASK)
12417 
12418 #define CAAM_DMA_X_AWTC_CTL_AWTCE_MASK           (0x80000000U)
12419 #define CAAM_DMA_X_AWTC_CTL_AWTCE_SHIFT          (31U)
12420 #define CAAM_DMA_X_AWTC_CTL_AWTCE(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWTCE_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWTCE_MASK)
12421 /*! @} */
12422 
12423 /*! @name DMA_X_AWTC_LC - DMA_X AXI Write Timing Check Late Count Register */
12424 /*! @{ */
12425 
12426 #define CAAM_DMA_X_AWTC_LC_AWLC_MASK             (0xFFFFFU)
12427 #define CAAM_DMA_X_AWTC_LC_AWLC_SHIFT            (0U)
12428 #define CAAM_DMA_X_AWTC_LC_AWLC(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_LC_AWLC_SHIFT)) & CAAM_DMA_X_AWTC_LC_AWLC_MASK)
12429 /*! @} */
12430 
12431 /*! @name DMA_X_AWTC_SC - DMA_X AXI Write Timing Check Sample Count Register */
12432 /*! @{ */
12433 
12434 #define CAAM_DMA_X_AWTC_SC_AWSC_MASK             (0xFFFFFU)
12435 #define CAAM_DMA_X_AWTC_SC_AWSC_SHIFT            (0U)
12436 #define CAAM_DMA_X_AWTC_SC_AWSC(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_SC_AWSC_SHIFT)) & CAAM_DMA_X_AWTC_SC_AWSC_MASK)
12437 /*! @} */
12438 
12439 /*! @name DMA_X_AWTC_LAT - DMA_X Write Timing Check Latency Register */
12440 /*! @{ */
12441 
12442 #define CAAM_DMA_X_AWTC_LAT_SAWL_MASK            (0xFFFFFFFFU)
12443 #define CAAM_DMA_X_AWTC_LAT_SAWL_SHIFT           (0U)
12444 #define CAAM_DMA_X_AWTC_LAT_SAWL(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_LAT_SAWL_SHIFT)) & CAAM_DMA_X_AWTC_LAT_SAWL_MASK)
12445 /*! @} */
12446 
12447 /*! @name RTMCTL - RNG TRNG Miscellaneous Control Register */
12448 /*! @{ */
12449 
12450 #define CAAM_RTMCTL_SAMP_MODE_MASK               (0x3U)
12451 #define CAAM_RTMCTL_SAMP_MODE_SHIFT              (0U)
12452 /*! SAMP_MODE
12453  *  0b00..use Von Neumann data into both Entropy shifter and Statistical Checker
12454  *  0b01..use raw data into both Entropy shifter and Statistical Checker
12455  *  0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker
12456  *  0b11..undefined/reserved.
12457  */
12458 #define CAAM_RTMCTL_SAMP_MODE(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_SAMP_MODE_SHIFT)) & CAAM_RTMCTL_SAMP_MODE_MASK)
12459 
12460 #define CAAM_RTMCTL_OSC_DIV_MASK                 (0xCU)
12461 #define CAAM_RTMCTL_OSC_DIV_SHIFT                (2U)
12462 /*! OSC_DIV
12463  *  0b00..use ring oscillator with no divide
12464  *  0b01..use ring oscillator divided-by-2
12465  *  0b10..use ring oscillator divided-by-4
12466  *  0b11..use ring oscillator divided-by-8
12467  */
12468 #define CAAM_RTMCTL_OSC_DIV(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_OSC_DIV_SHIFT)) & CAAM_RTMCTL_OSC_DIV_MASK)
12469 
12470 #define CAAM_RTMCTL_CLK_OUT_EN_MASK              (0x10U)
12471 #define CAAM_RTMCTL_CLK_OUT_EN_SHIFT             (4U)
12472 #define CAAM_RTMCTL_CLK_OUT_EN(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_CLK_OUT_EN_SHIFT)) & CAAM_RTMCTL_CLK_OUT_EN_MASK)
12473 
12474 #define CAAM_RTMCTL_TRNG_ACC_MASK                (0x20U)
12475 #define CAAM_RTMCTL_TRNG_ACC_SHIFT               (5U)
12476 #define CAAM_RTMCTL_TRNG_ACC(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TRNG_ACC_SHIFT)) & CAAM_RTMCTL_TRNG_ACC_MASK)
12477 
12478 #define CAAM_RTMCTL_RST_DEF_MASK                 (0x40U)
12479 #define CAAM_RTMCTL_RST_DEF_SHIFT                (6U)
12480 #define CAAM_RTMCTL_RST_DEF(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_RST_DEF_SHIFT)) & CAAM_RTMCTL_RST_DEF_MASK)
12481 
12482 #define CAAM_RTMCTL_FORCE_SYSCLK_MASK            (0x80U)
12483 #define CAAM_RTMCTL_FORCE_SYSCLK_SHIFT           (7U)
12484 #define CAAM_RTMCTL_FORCE_SYSCLK(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FORCE_SYSCLK_SHIFT)) & CAAM_RTMCTL_FORCE_SYSCLK_MASK)
12485 
12486 #define CAAM_RTMCTL_FCT_FAIL_MASK                (0x100U)
12487 #define CAAM_RTMCTL_FCT_FAIL_SHIFT               (8U)
12488 #define CAAM_RTMCTL_FCT_FAIL(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FCT_FAIL_SHIFT)) & CAAM_RTMCTL_FCT_FAIL_MASK)
12489 
12490 #define CAAM_RTMCTL_FCT_VAL_MASK                 (0x200U)
12491 #define CAAM_RTMCTL_FCT_VAL_SHIFT                (9U)
12492 #define CAAM_RTMCTL_FCT_VAL(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FCT_VAL_SHIFT)) & CAAM_RTMCTL_FCT_VAL_MASK)
12493 
12494 #define CAAM_RTMCTL_ENT_VAL_MASK                 (0x400U)
12495 #define CAAM_RTMCTL_ENT_VAL_SHIFT                (10U)
12496 #define CAAM_RTMCTL_ENT_VAL(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_ENT_VAL_SHIFT)) & CAAM_RTMCTL_ENT_VAL_MASK)
12497 
12498 #define CAAM_RTMCTL_TST_OUT_MASK                 (0x800U)
12499 #define CAAM_RTMCTL_TST_OUT_SHIFT                (11U)
12500 #define CAAM_RTMCTL_TST_OUT(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TST_OUT_SHIFT)) & CAAM_RTMCTL_TST_OUT_MASK)
12501 
12502 #define CAAM_RTMCTL_ERR_MASK                     (0x1000U)
12503 #define CAAM_RTMCTL_ERR_SHIFT                    (12U)
12504 #define CAAM_RTMCTL_ERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_ERR_SHIFT)) & CAAM_RTMCTL_ERR_MASK)
12505 
12506 #define CAAM_RTMCTL_TSTOP_OK_MASK                (0x2000U)
12507 #define CAAM_RTMCTL_TSTOP_OK_SHIFT               (13U)
12508 #define CAAM_RTMCTL_TSTOP_OK(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TSTOP_OK_SHIFT)) & CAAM_RTMCTL_TSTOP_OK_MASK)
12509 
12510 #define CAAM_RTMCTL_PRGM_MASK                    (0x10000U)
12511 #define CAAM_RTMCTL_PRGM_SHIFT                   (16U)
12512 #define CAAM_RTMCTL_PRGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_PRGM_SHIFT)) & CAAM_RTMCTL_PRGM_MASK)
12513 /*! @} */
12514 
12515 /*! @name RTSCMISC - RNG TRNG Statistical Check Miscellaneous Register */
12516 /*! @{ */
12517 
12518 #define CAAM_RTSCMISC_LRUN_MAX_MASK              (0xFFU)
12519 #define CAAM_RTSCMISC_LRUN_MAX_SHIFT             (0U)
12520 #define CAAM_RTSCMISC_LRUN_MAX(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMISC_LRUN_MAX_SHIFT)) & CAAM_RTSCMISC_LRUN_MAX_MASK)
12521 
12522 #define CAAM_RTSCMISC_RTY_CNT_MASK               (0xF0000U)
12523 #define CAAM_RTSCMISC_RTY_CNT_SHIFT              (16U)
12524 #define CAAM_RTSCMISC_RTY_CNT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMISC_RTY_CNT_SHIFT)) & CAAM_RTSCMISC_RTY_CNT_MASK)
12525 /*! @} */
12526 
12527 /*! @name RTPKRRNG - RNG TRNG Poker Range Register */
12528 /*! @{ */
12529 
12530 #define CAAM_RTPKRRNG_PKR_RNG_MASK               (0xFFFFU)
12531 #define CAAM_RTPKRRNG_PKR_RNG_SHIFT              (0U)
12532 #define CAAM_RTPKRRNG_PKR_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRRNG_PKR_RNG_SHIFT)) & CAAM_RTPKRRNG_PKR_RNG_MASK)
12533 /*! @} */
12534 
12535 /*! @name RTPKRMAX - RNG TRNG Poker Maximum Limit Register */
12536 /*! @{ */
12537 
12538 #define CAAM_RTPKRMAX_PKR_MAX_MASK               (0xFFFFFFU)
12539 #define CAAM_RTPKRMAX_PKR_MAX_SHIFT              (0U)
12540 #define CAAM_RTPKRMAX_PKR_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRMAX_PKR_MAX_SHIFT)) & CAAM_RTPKRMAX_PKR_MAX_MASK)
12541 /*! @} */
12542 
12543 /*! @name RTPKRSQ - RNG TRNG Poker Square Calculation Result Register */
12544 /*! @{ */
12545 
12546 #define CAAM_RTPKRSQ_PKR_SQ_MASK                 (0xFFFFFFU)
12547 #define CAAM_RTPKRSQ_PKR_SQ_SHIFT                (0U)
12548 #define CAAM_RTPKRSQ_PKR_SQ(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRSQ_PKR_SQ_SHIFT)) & CAAM_RTPKRSQ_PKR_SQ_MASK)
12549 /*! @} */
12550 
12551 /*! @name RTSDCTL - RNG TRNG Seed Control Register */
12552 /*! @{ */
12553 
12554 #define CAAM_RTSDCTL_SAMP_SIZE_MASK              (0xFFFFU)
12555 #define CAAM_RTSDCTL_SAMP_SIZE_SHIFT             (0U)
12556 #define CAAM_RTSDCTL_SAMP_SIZE(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTSDCTL_SAMP_SIZE_SHIFT)) & CAAM_RTSDCTL_SAMP_SIZE_MASK)
12557 
12558 #define CAAM_RTSDCTL_ENT_DLY_MASK                (0xFFFF0000U)
12559 #define CAAM_RTSDCTL_ENT_DLY_SHIFT               (16U)
12560 #define CAAM_RTSDCTL_ENT_DLY(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTSDCTL_ENT_DLY_SHIFT)) & CAAM_RTSDCTL_ENT_DLY_MASK)
12561 /*! @} */
12562 
12563 /*! @name RTSBLIM - RNG TRNG Sparse Bit Limit Register */
12564 /*! @{ */
12565 
12566 #define CAAM_RTSBLIM_SB_LIM_MASK                 (0x3FFU)
12567 #define CAAM_RTSBLIM_SB_LIM_SHIFT                (0U)
12568 #define CAAM_RTSBLIM_SB_LIM(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTSBLIM_SB_LIM_SHIFT)) & CAAM_RTSBLIM_SB_LIM_MASK)
12569 /*! @} */
12570 
12571 /*! @name RTTOTSAM - RNG TRNG Total Samples Register */
12572 /*! @{ */
12573 
12574 #define CAAM_RTTOTSAM_TOT_SAM_MASK               (0xFFFFFU)
12575 #define CAAM_RTTOTSAM_TOT_SAM_SHIFT              (0U)
12576 #define CAAM_RTTOTSAM_TOT_SAM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTTOTSAM_TOT_SAM_SHIFT)) & CAAM_RTTOTSAM_TOT_SAM_MASK)
12577 /*! @} */
12578 
12579 /*! @name RTFRQMIN - RNG TRNG Frequency Count Minimum Limit Register */
12580 /*! @{ */
12581 
12582 #define CAAM_RTFRQMIN_FRQ_MIN_MASK               (0x3FFFFFU)
12583 #define CAAM_RTFRQMIN_FRQ_MIN_SHIFT              (0U)
12584 #define CAAM_RTFRQMIN_FRQ_MIN(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQMIN_FRQ_MIN_SHIFT)) & CAAM_RTFRQMIN_FRQ_MIN_MASK)
12585 /*! @} */
12586 
12587 /*! @name RTFRQCNT - RNG TRNG Frequency Count Register */
12588 /*! @{ */
12589 
12590 #define CAAM_RTFRQCNT_FRQ_CNT_MASK               (0x3FFFFFU)
12591 #define CAAM_RTFRQCNT_FRQ_CNT_SHIFT              (0U)
12592 #define CAAM_RTFRQCNT_FRQ_CNT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQCNT_FRQ_CNT_SHIFT)) & CAAM_RTFRQCNT_FRQ_CNT_MASK)
12593 /*! @} */
12594 
12595 /*! @name RTSCMC - RNG TRNG Statistical Check Monobit Count Register */
12596 /*! @{ */
12597 
12598 #define CAAM_RTSCMC_MONO_CNT_MASK                (0xFFFFU)
12599 #define CAAM_RTSCMC_MONO_CNT_SHIFT               (0U)
12600 #define CAAM_RTSCMC_MONO_CNT(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMC_MONO_CNT_SHIFT)) & CAAM_RTSCMC_MONO_CNT_MASK)
12601 /*! @} */
12602 
12603 /*! @name RTSCR1C - RNG TRNG Statistical Check Run Length 1 Count Register */
12604 /*! @{ */
12605 
12606 #define CAAM_RTSCR1C_R1_0_COUNT_MASK             (0x7FFFU)
12607 #define CAAM_RTSCR1C_R1_0_COUNT_SHIFT            (0U)
12608 #define CAAM_RTSCR1C_R1_0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1C_R1_0_COUNT_SHIFT)) & CAAM_RTSCR1C_R1_0_COUNT_MASK)
12609 
12610 #define CAAM_RTSCR1C_R1_1_COUNT_MASK             (0x7FFF0000U)
12611 #define CAAM_RTSCR1C_R1_1_COUNT_SHIFT            (16U)
12612 #define CAAM_RTSCR1C_R1_1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1C_R1_1_COUNT_SHIFT)) & CAAM_RTSCR1C_R1_1_COUNT_MASK)
12613 /*! @} */
12614 
12615 /*! @name RTSCR2C - RNG TRNG Statistical Check Run Length 2 Count Register */
12616 /*! @{ */
12617 
12618 #define CAAM_RTSCR2C_R2_0_COUNT_MASK             (0x3FFFU)
12619 #define CAAM_RTSCR2C_R2_0_COUNT_SHIFT            (0U)
12620 #define CAAM_RTSCR2C_R2_0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2C_R2_0_COUNT_SHIFT)) & CAAM_RTSCR2C_R2_0_COUNT_MASK)
12621 
12622 #define CAAM_RTSCR2C_R2_1_COUNT_MASK             (0x3FFF0000U)
12623 #define CAAM_RTSCR2C_R2_1_COUNT_SHIFT            (16U)
12624 #define CAAM_RTSCR2C_R2_1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2C_R2_1_COUNT_SHIFT)) & CAAM_RTSCR2C_R2_1_COUNT_MASK)
12625 /*! @} */
12626 
12627 /*! @name RTSCR3C - RNG TRNG Statistical Check Run Length 3 Count Register */
12628 /*! @{ */
12629 
12630 #define CAAM_RTSCR3C_R3_0_COUNT_MASK             (0x1FFFU)
12631 #define CAAM_RTSCR3C_R3_0_COUNT_SHIFT            (0U)
12632 #define CAAM_RTSCR3C_R3_0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3C_R3_0_COUNT_SHIFT)) & CAAM_RTSCR3C_R3_0_COUNT_MASK)
12633 
12634 #define CAAM_RTSCR3C_R3_1_COUNT_MASK             (0x1FFF0000U)
12635 #define CAAM_RTSCR3C_R3_1_COUNT_SHIFT            (16U)
12636 #define CAAM_RTSCR3C_R3_1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3C_R3_1_COUNT_SHIFT)) & CAAM_RTSCR3C_R3_1_COUNT_MASK)
12637 /*! @} */
12638 
12639 /*! @name RTSCR4C - RNG TRNG Statistical Check Run Length 4 Count Register */
12640 /*! @{ */
12641 
12642 #define CAAM_RTSCR4C_R4_0_COUNT_MASK             (0xFFFU)
12643 #define CAAM_RTSCR4C_R4_0_COUNT_SHIFT            (0U)
12644 #define CAAM_RTSCR4C_R4_0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4C_R4_0_COUNT_SHIFT)) & CAAM_RTSCR4C_R4_0_COUNT_MASK)
12645 
12646 #define CAAM_RTSCR4C_R4_1_COUNT_MASK             (0xFFF0000U)
12647 #define CAAM_RTSCR4C_R4_1_COUNT_SHIFT            (16U)
12648 #define CAAM_RTSCR4C_R4_1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4C_R4_1_COUNT_SHIFT)) & CAAM_RTSCR4C_R4_1_COUNT_MASK)
12649 /*! @} */
12650 
12651 /*! @name RTSCR5C - RNG TRNG Statistical Check Run Length 5 Count Register */
12652 /*! @{ */
12653 
12654 #define CAAM_RTSCR5C_R5_0_COUNT_MASK             (0x7FFU)
12655 #define CAAM_RTSCR5C_R5_0_COUNT_SHIFT            (0U)
12656 #define CAAM_RTSCR5C_R5_0_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5C_R5_0_COUNT_SHIFT)) & CAAM_RTSCR5C_R5_0_COUNT_MASK)
12657 
12658 #define CAAM_RTSCR5C_R5_1_COUNT_MASK             (0x7FF0000U)
12659 #define CAAM_RTSCR5C_R5_1_COUNT_SHIFT            (16U)
12660 #define CAAM_RTSCR5C_R5_1_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5C_R5_1_COUNT_SHIFT)) & CAAM_RTSCR5C_R5_1_COUNT_MASK)
12661 /*! @} */
12662 
12663 /*! @name RTSCR6PC - RNG TRNG Statistical Check Run Length 6+ Count Register */
12664 /*! @{ */
12665 
12666 #define CAAM_RTSCR6PC_R6P_0_COUNT_MASK           (0x7FFU)
12667 #define CAAM_RTSCR6PC_R6P_0_COUNT_SHIFT          (0U)
12668 #define CAAM_RTSCR6PC_R6P_0_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PC_R6P_0_COUNT_SHIFT)) & CAAM_RTSCR6PC_R6P_0_COUNT_MASK)
12669 
12670 #define CAAM_RTSCR6PC_R6P_1_COUNT_MASK           (0x7FF0000U)
12671 #define CAAM_RTSCR6PC_R6P_1_COUNT_SHIFT          (16U)
12672 #define CAAM_RTSCR6PC_R6P_1_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PC_R6P_1_COUNT_SHIFT)) & CAAM_RTSCR6PC_R6P_1_COUNT_MASK)
12673 /*! @} */
12674 
12675 /*! @name RTFRQMAX - RNG TRNG Frequency Count Maximum Limit Register */
12676 /*! @{ */
12677 
12678 #define CAAM_RTFRQMAX_FRQ_MAX_MASK               (0x3FFFFFU)
12679 #define CAAM_RTFRQMAX_FRQ_MAX_SHIFT              (0U)
12680 #define CAAM_RTFRQMAX_FRQ_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQMAX_FRQ_MAX_SHIFT)) & CAAM_RTFRQMAX_FRQ_MAX_MASK)
12681 /*! @} */
12682 
12683 /*! @name RTSCML - RNG TRNG Statistical Check Monobit Limit Register */
12684 /*! @{ */
12685 
12686 #define CAAM_RTSCML_MONO_MAX_MASK                (0xFFFFU)
12687 #define CAAM_RTSCML_MONO_MAX_SHIFT               (0U)
12688 #define CAAM_RTSCML_MONO_MAX(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCML_MONO_MAX_SHIFT)) & CAAM_RTSCML_MONO_MAX_MASK)
12689 
12690 #define CAAM_RTSCML_MONO_RNG_MASK                (0xFFFF0000U)
12691 #define CAAM_RTSCML_MONO_RNG_SHIFT               (16U)
12692 #define CAAM_RTSCML_MONO_RNG(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCML_MONO_RNG_SHIFT)) & CAAM_RTSCML_MONO_RNG_MASK)
12693 /*! @} */
12694 
12695 /*! @name RTSCR1L - RNG TRNG Statistical Check Run Length 1 Limit Register */
12696 /*! @{ */
12697 
12698 #define CAAM_RTSCR1L_RUN1_MAX_MASK               (0x7FFFU)
12699 #define CAAM_RTSCR1L_RUN1_MAX_SHIFT              (0U)
12700 #define CAAM_RTSCR1L_RUN1_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1L_RUN1_MAX_SHIFT)) & CAAM_RTSCR1L_RUN1_MAX_MASK)
12701 
12702 #define CAAM_RTSCR1L_RUN1_RNG_MASK               (0x7FFF0000U)
12703 #define CAAM_RTSCR1L_RUN1_RNG_SHIFT              (16U)
12704 #define CAAM_RTSCR1L_RUN1_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1L_RUN1_RNG_SHIFT)) & CAAM_RTSCR1L_RUN1_RNG_MASK)
12705 /*! @} */
12706 
12707 /*! @name RTSCR2L - RNG TRNG Statistical Check Run Length 2 Limit Register */
12708 /*! @{ */
12709 
12710 #define CAAM_RTSCR2L_RUN2_MAX_MASK               (0x3FFFU)
12711 #define CAAM_RTSCR2L_RUN2_MAX_SHIFT              (0U)
12712 #define CAAM_RTSCR2L_RUN2_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2L_RUN2_MAX_SHIFT)) & CAAM_RTSCR2L_RUN2_MAX_MASK)
12713 
12714 #define CAAM_RTSCR2L_RUN2_RNG_MASK               (0x3FFF0000U)
12715 #define CAAM_RTSCR2L_RUN2_RNG_SHIFT              (16U)
12716 #define CAAM_RTSCR2L_RUN2_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2L_RUN2_RNG_SHIFT)) & CAAM_RTSCR2L_RUN2_RNG_MASK)
12717 /*! @} */
12718 
12719 /*! @name RTSCR3L - RNG TRNG Statistical Check Run Length 3 Limit Register */
12720 /*! @{ */
12721 
12722 #define CAAM_RTSCR3L_RUN3_MAX_MASK               (0x1FFFU)
12723 #define CAAM_RTSCR3L_RUN3_MAX_SHIFT              (0U)
12724 #define CAAM_RTSCR3L_RUN3_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3L_RUN3_MAX_SHIFT)) & CAAM_RTSCR3L_RUN3_MAX_MASK)
12725 
12726 #define CAAM_RTSCR3L_RUN3_RNG_MASK               (0x1FFF0000U)
12727 #define CAAM_RTSCR3L_RUN3_RNG_SHIFT              (16U)
12728 #define CAAM_RTSCR3L_RUN3_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3L_RUN3_RNG_SHIFT)) & CAAM_RTSCR3L_RUN3_RNG_MASK)
12729 /*! @} */
12730 
12731 /*! @name RTSCR4L - RNG TRNG Statistical Check Run Length 4 Limit Register */
12732 /*! @{ */
12733 
12734 #define CAAM_RTSCR4L_RUN4_MAX_MASK               (0xFFFU)
12735 #define CAAM_RTSCR4L_RUN4_MAX_SHIFT              (0U)
12736 #define CAAM_RTSCR4L_RUN4_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4L_RUN4_MAX_SHIFT)) & CAAM_RTSCR4L_RUN4_MAX_MASK)
12737 
12738 #define CAAM_RTSCR4L_RUN4_RNG_MASK               (0xFFF0000U)
12739 #define CAAM_RTSCR4L_RUN4_RNG_SHIFT              (16U)
12740 #define CAAM_RTSCR4L_RUN4_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4L_RUN4_RNG_SHIFT)) & CAAM_RTSCR4L_RUN4_RNG_MASK)
12741 /*! @} */
12742 
12743 /*! @name RTSCR5L - RNG TRNG Statistical Check Run Length 5 Limit Register */
12744 /*! @{ */
12745 
12746 #define CAAM_RTSCR5L_RUN5_MAX_MASK               (0x7FFU)
12747 #define CAAM_RTSCR5L_RUN5_MAX_SHIFT              (0U)
12748 #define CAAM_RTSCR5L_RUN5_MAX(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5L_RUN5_MAX_SHIFT)) & CAAM_RTSCR5L_RUN5_MAX_MASK)
12749 
12750 #define CAAM_RTSCR5L_RUN5_RNG_MASK               (0x7FF0000U)
12751 #define CAAM_RTSCR5L_RUN5_RNG_SHIFT              (16U)
12752 #define CAAM_RTSCR5L_RUN5_RNG(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5L_RUN5_RNG_SHIFT)) & CAAM_RTSCR5L_RUN5_RNG_MASK)
12753 /*! @} */
12754 
12755 /*! @name RTSCR6PL - RNG TRNG Statistical Check Run Length 6+ Limit Register */
12756 /*! @{ */
12757 
12758 #define CAAM_RTSCR6PL_RUN6P_MAX_MASK             (0x7FFU)
12759 #define CAAM_RTSCR6PL_RUN6P_MAX_SHIFT            (0U)
12760 #define CAAM_RTSCR6PL_RUN6P_MAX(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PL_RUN6P_MAX_SHIFT)) & CAAM_RTSCR6PL_RUN6P_MAX_MASK)
12761 
12762 #define CAAM_RTSCR6PL_RUN6P_RNG_MASK             (0x7FF0000U)
12763 #define CAAM_RTSCR6PL_RUN6P_RNG_SHIFT            (16U)
12764 #define CAAM_RTSCR6PL_RUN6P_RNG(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PL_RUN6P_RNG_SHIFT)) & CAAM_RTSCR6PL_RUN6P_RNG_MASK)
12765 /*! @} */
12766 
12767 /*! @name RTSTATUS - RNG TRNG Status Register */
12768 /*! @{ */
12769 
12770 #define CAAM_RTSTATUS_F1BR0TF_MASK               (0x1U)
12771 #define CAAM_RTSTATUS_F1BR0TF_SHIFT              (0U)
12772 #define CAAM_RTSTATUS_F1BR0TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F1BR0TF_SHIFT)) & CAAM_RTSTATUS_F1BR0TF_MASK)
12773 
12774 #define CAAM_RTSTATUS_F1BR1TF_MASK               (0x2U)
12775 #define CAAM_RTSTATUS_F1BR1TF_SHIFT              (1U)
12776 #define CAAM_RTSTATUS_F1BR1TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F1BR1TF_SHIFT)) & CAAM_RTSTATUS_F1BR1TF_MASK)
12777 
12778 #define CAAM_RTSTATUS_F2BR0TF_MASK               (0x4U)
12779 #define CAAM_RTSTATUS_F2BR0TF_SHIFT              (2U)
12780 #define CAAM_RTSTATUS_F2BR0TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F2BR0TF_SHIFT)) & CAAM_RTSTATUS_F2BR0TF_MASK)
12781 
12782 #define CAAM_RTSTATUS_F2BR1TF_MASK               (0x8U)
12783 #define CAAM_RTSTATUS_F2BR1TF_SHIFT              (3U)
12784 #define CAAM_RTSTATUS_F2BR1TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F2BR1TF_SHIFT)) & CAAM_RTSTATUS_F2BR1TF_MASK)
12785 
12786 #define CAAM_RTSTATUS_F3BR01TF_MASK              (0x10U)
12787 #define CAAM_RTSTATUS_F3BR01TF_SHIFT             (4U)
12788 #define CAAM_RTSTATUS_F3BR01TF(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F3BR01TF_SHIFT)) & CAAM_RTSTATUS_F3BR01TF_MASK)
12789 
12790 #define CAAM_RTSTATUS_F3BR1TF_MASK               (0x20U)
12791 #define CAAM_RTSTATUS_F3BR1TF_SHIFT              (5U)
12792 #define CAAM_RTSTATUS_F3BR1TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F3BR1TF_SHIFT)) & CAAM_RTSTATUS_F3BR1TF_MASK)
12793 
12794 #define CAAM_RTSTATUS_F4BR0TF_MASK               (0x40U)
12795 #define CAAM_RTSTATUS_F4BR0TF_SHIFT              (6U)
12796 #define CAAM_RTSTATUS_F4BR0TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F4BR0TF_SHIFT)) & CAAM_RTSTATUS_F4BR0TF_MASK)
12797 
12798 #define CAAM_RTSTATUS_F4BR1TF_MASK               (0x80U)
12799 #define CAAM_RTSTATUS_F4BR1TF_SHIFT              (7U)
12800 #define CAAM_RTSTATUS_F4BR1TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F4BR1TF_SHIFT)) & CAAM_RTSTATUS_F4BR1TF_MASK)
12801 
12802 #define CAAM_RTSTATUS_F5BR0TF_MASK               (0x100U)
12803 #define CAAM_RTSTATUS_F5BR0TF_SHIFT              (8U)
12804 #define CAAM_RTSTATUS_F5BR0TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F5BR0TF_SHIFT)) & CAAM_RTSTATUS_F5BR0TF_MASK)
12805 
12806 #define CAAM_RTSTATUS_F5BR1TF_MASK               (0x200U)
12807 #define CAAM_RTSTATUS_F5BR1TF_SHIFT              (9U)
12808 #define CAAM_RTSTATUS_F5BR1TF(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F5BR1TF_SHIFT)) & CAAM_RTSTATUS_F5BR1TF_MASK)
12809 
12810 #define CAAM_RTSTATUS_F6PBR0TF_MASK              (0x400U)
12811 #define CAAM_RTSTATUS_F6PBR0TF_SHIFT             (10U)
12812 #define CAAM_RTSTATUS_F6PBR0TF(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F6PBR0TF_SHIFT)) & CAAM_RTSTATUS_F6PBR0TF_MASK)
12813 
12814 #define CAAM_RTSTATUS_F6PBR1TF_MASK              (0x800U)
12815 #define CAAM_RTSTATUS_F6PBR1TF_SHIFT             (11U)
12816 #define CAAM_RTSTATUS_F6PBR1TF(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F6PBR1TF_SHIFT)) & CAAM_RTSTATUS_F6PBR1TF_MASK)
12817 
12818 #define CAAM_RTSTATUS_FSBTF_MASK                 (0x1000U)
12819 #define CAAM_RTSTATUS_FSBTF_SHIFT                (12U)
12820 #define CAAM_RTSTATUS_FSBTF(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FSBTF_SHIFT)) & CAAM_RTSTATUS_FSBTF_MASK)
12821 
12822 #define CAAM_RTSTATUS_FLRTF_MASK                 (0x2000U)
12823 #define CAAM_RTSTATUS_FLRTF_SHIFT                (13U)
12824 #define CAAM_RTSTATUS_FLRTF(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FLRTF_SHIFT)) & CAAM_RTSTATUS_FLRTF_MASK)
12825 
12826 #define CAAM_RTSTATUS_FPTF_MASK                  (0x4000U)
12827 #define CAAM_RTSTATUS_FPTF_SHIFT                 (14U)
12828 #define CAAM_RTSTATUS_FPTF(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FPTF_SHIFT)) & CAAM_RTSTATUS_FPTF_MASK)
12829 
12830 #define CAAM_RTSTATUS_FMBTF_MASK                 (0x8000U)
12831 #define CAAM_RTSTATUS_FMBTF_SHIFT                (15U)
12832 #define CAAM_RTSTATUS_FMBTF(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FMBTF_SHIFT)) & CAAM_RTSTATUS_FMBTF_MASK)
12833 
12834 #define CAAM_RTSTATUS_RETRY_COUNT_MASK           (0xF0000U)
12835 #define CAAM_RTSTATUS_RETRY_COUNT_SHIFT          (16U)
12836 #define CAAM_RTSTATUS_RETRY_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_RETRY_COUNT_SHIFT)) & CAAM_RTSTATUS_RETRY_COUNT_MASK)
12837 /*! @} */
12838 
12839 /*! @name RTENT - RNG TRNG Entropy Read Register */
12840 /*! @{ */
12841 
12842 #define CAAM_RTENT_ENT_MASK                      (0xFFFFFFFFU)
12843 #define CAAM_RTENT_ENT_SHIFT                     (0U)
12844 #define CAAM_RTENT_ENT(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RTENT_ENT_SHIFT)) & CAAM_RTENT_ENT_MASK)
12845 /*! @} */
12846 
12847 /* The count of CAAM_RTENT */
12848 #define CAAM_RTENT_COUNT                         (16U)
12849 
12850 /*! @name RTPKRCNT10 - RNG TRNG Statistical Check Poker Count 1 and 0 Register */
12851 /*! @{ */
12852 
12853 #define CAAM_RTPKRCNT10_PKR_0_CNT_MASK           (0xFFFFU)
12854 #define CAAM_RTPKRCNT10_PKR_0_CNT_SHIFT          (0U)
12855 #define CAAM_RTPKRCNT10_PKR_0_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT10_PKR_0_CNT_SHIFT)) & CAAM_RTPKRCNT10_PKR_0_CNT_MASK)
12856 
12857 #define CAAM_RTPKRCNT10_PKR_1_CNT_MASK           (0xFFFF0000U)
12858 #define CAAM_RTPKRCNT10_PKR_1_CNT_SHIFT          (16U)
12859 #define CAAM_RTPKRCNT10_PKR_1_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT10_PKR_1_CNT_SHIFT)) & CAAM_RTPKRCNT10_PKR_1_CNT_MASK)
12860 /*! @} */
12861 
12862 /*! @name RTPKRCNT32 - RNG TRNG Statistical Check Poker Count 3 and 2 Register */
12863 /*! @{ */
12864 
12865 #define CAAM_RTPKRCNT32_PKR_2_CNT_MASK           (0xFFFFU)
12866 #define CAAM_RTPKRCNT32_PKR_2_CNT_SHIFT          (0U)
12867 #define CAAM_RTPKRCNT32_PKR_2_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT32_PKR_2_CNT_SHIFT)) & CAAM_RTPKRCNT32_PKR_2_CNT_MASK)
12868 
12869 #define CAAM_RTPKRCNT32_PKR_3_CNT_MASK           (0xFFFF0000U)
12870 #define CAAM_RTPKRCNT32_PKR_3_CNT_SHIFT          (16U)
12871 #define CAAM_RTPKRCNT32_PKR_3_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT32_PKR_3_CNT_SHIFT)) & CAAM_RTPKRCNT32_PKR_3_CNT_MASK)
12872 /*! @} */
12873 
12874 /*! @name RTPKRCNT54 - RNG TRNG Statistical Check Poker Count 5 and 4 Register */
12875 /*! @{ */
12876 
12877 #define CAAM_RTPKRCNT54_PKR_4_CNT_MASK           (0xFFFFU)
12878 #define CAAM_RTPKRCNT54_PKR_4_CNT_SHIFT          (0U)
12879 #define CAAM_RTPKRCNT54_PKR_4_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT54_PKR_4_CNT_SHIFT)) & CAAM_RTPKRCNT54_PKR_4_CNT_MASK)
12880 
12881 #define CAAM_RTPKRCNT54_PKR_5_CNT_MASK           (0xFFFF0000U)
12882 #define CAAM_RTPKRCNT54_PKR_5_CNT_SHIFT          (16U)
12883 #define CAAM_RTPKRCNT54_PKR_5_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT54_PKR_5_CNT_SHIFT)) & CAAM_RTPKRCNT54_PKR_5_CNT_MASK)
12884 /*! @} */
12885 
12886 /*! @name RTPKRCNT76 - RNG TRNG Statistical Check Poker Count 7 and 6 Register */
12887 /*! @{ */
12888 
12889 #define CAAM_RTPKRCNT76_PKR_6_CNT_MASK           (0xFFFFU)
12890 #define CAAM_RTPKRCNT76_PKR_6_CNT_SHIFT          (0U)
12891 #define CAAM_RTPKRCNT76_PKR_6_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT76_PKR_6_CNT_SHIFT)) & CAAM_RTPKRCNT76_PKR_6_CNT_MASK)
12892 
12893 #define CAAM_RTPKRCNT76_PKR_7_CNT_MASK           (0xFFFF0000U)
12894 #define CAAM_RTPKRCNT76_PKR_7_CNT_SHIFT          (16U)
12895 #define CAAM_RTPKRCNT76_PKR_7_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT76_PKR_7_CNT_SHIFT)) & CAAM_RTPKRCNT76_PKR_7_CNT_MASK)
12896 /*! @} */
12897 
12898 /*! @name RTPKRCNT98 - RNG TRNG Statistical Check Poker Count 9 and 8 Register */
12899 /*! @{ */
12900 
12901 #define CAAM_RTPKRCNT98_PKR_8_CNT_MASK           (0xFFFFU)
12902 #define CAAM_RTPKRCNT98_PKR_8_CNT_SHIFT          (0U)
12903 #define CAAM_RTPKRCNT98_PKR_8_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT98_PKR_8_CNT_SHIFT)) & CAAM_RTPKRCNT98_PKR_8_CNT_MASK)
12904 
12905 #define CAAM_RTPKRCNT98_PKR_9_CNT_MASK           (0xFFFF0000U)
12906 #define CAAM_RTPKRCNT98_PKR_9_CNT_SHIFT          (16U)
12907 #define CAAM_RTPKRCNT98_PKR_9_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT98_PKR_9_CNT_SHIFT)) & CAAM_RTPKRCNT98_PKR_9_CNT_MASK)
12908 /*! @} */
12909 
12910 /*! @name RTPKRCNTBA - RNG TRNG Statistical Check Poker Count B and A Register */
12911 /*! @{ */
12912 
12913 #define CAAM_RTPKRCNTBA_PKR_A_CNT_MASK           (0xFFFFU)
12914 #define CAAM_RTPKRCNTBA_PKR_A_CNT_SHIFT          (0U)
12915 #define CAAM_RTPKRCNTBA_PKR_A_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTBA_PKR_A_CNT_SHIFT)) & CAAM_RTPKRCNTBA_PKR_A_CNT_MASK)
12916 
12917 #define CAAM_RTPKRCNTBA_PKR_B_CNT_MASK           (0xFFFF0000U)
12918 #define CAAM_RTPKRCNTBA_PKR_B_CNT_SHIFT          (16U)
12919 #define CAAM_RTPKRCNTBA_PKR_B_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTBA_PKR_B_CNT_SHIFT)) & CAAM_RTPKRCNTBA_PKR_B_CNT_MASK)
12920 /*! @} */
12921 
12922 /*! @name RTPKRCNTDC - RNG TRNG Statistical Check Poker Count D and C Register */
12923 /*! @{ */
12924 
12925 #define CAAM_RTPKRCNTDC_PKR_C_CNT_MASK           (0xFFFFU)
12926 #define CAAM_RTPKRCNTDC_PKR_C_CNT_SHIFT          (0U)
12927 #define CAAM_RTPKRCNTDC_PKR_C_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTDC_PKR_C_CNT_SHIFT)) & CAAM_RTPKRCNTDC_PKR_C_CNT_MASK)
12928 
12929 #define CAAM_RTPKRCNTDC_PKR_D_CNT_MASK           (0xFFFF0000U)
12930 #define CAAM_RTPKRCNTDC_PKR_D_CNT_SHIFT          (16U)
12931 #define CAAM_RTPKRCNTDC_PKR_D_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTDC_PKR_D_CNT_SHIFT)) & CAAM_RTPKRCNTDC_PKR_D_CNT_MASK)
12932 /*! @} */
12933 
12934 /*! @name RTPKRCNTFE - RNG TRNG Statistical Check Poker Count F and E Register */
12935 /*! @{ */
12936 
12937 #define CAAM_RTPKRCNTFE_PKR_E_CNT_MASK           (0xFFFFU)
12938 #define CAAM_RTPKRCNTFE_PKR_E_CNT_SHIFT          (0U)
12939 #define CAAM_RTPKRCNTFE_PKR_E_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTFE_PKR_E_CNT_SHIFT)) & CAAM_RTPKRCNTFE_PKR_E_CNT_MASK)
12940 
12941 #define CAAM_RTPKRCNTFE_PKR_F_CNT_MASK           (0xFFFF0000U)
12942 #define CAAM_RTPKRCNTFE_PKR_F_CNT_SHIFT          (16U)
12943 #define CAAM_RTPKRCNTFE_PKR_F_CNT(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTFE_PKR_F_CNT_SHIFT)) & CAAM_RTPKRCNTFE_PKR_F_CNT_MASK)
12944 /*! @} */
12945 
12946 /*! @name RDSTA - RNG DRNG Status Register */
12947 /*! @{ */
12948 
12949 #define CAAM_RDSTA_IF0_MASK                      (0x1U)
12950 #define CAAM_RDSTA_IF0_SHIFT                     (0U)
12951 #define CAAM_RDSTA_IF0(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_IF0_SHIFT)) & CAAM_RDSTA_IF0_MASK)
12952 
12953 #define CAAM_RDSTA_IF1_MASK                      (0x2U)
12954 #define CAAM_RDSTA_IF1_SHIFT                     (1U)
12955 #define CAAM_RDSTA_IF1(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_IF1_SHIFT)) & CAAM_RDSTA_IF1_MASK)
12956 
12957 #define CAAM_RDSTA_PR0_MASK                      (0x10U)
12958 #define CAAM_RDSTA_PR0_SHIFT                     (4U)
12959 #define CAAM_RDSTA_PR0(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_PR0_SHIFT)) & CAAM_RDSTA_PR0_MASK)
12960 
12961 #define CAAM_RDSTA_PR1_MASK                      (0x20U)
12962 #define CAAM_RDSTA_PR1_SHIFT                     (5U)
12963 #define CAAM_RDSTA_PR1(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_PR1_SHIFT)) & CAAM_RDSTA_PR1_MASK)
12964 
12965 #define CAAM_RDSTA_TF0_MASK                      (0x100U)
12966 #define CAAM_RDSTA_TF0_SHIFT                     (8U)
12967 #define CAAM_RDSTA_TF0(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_TF0_SHIFT)) & CAAM_RDSTA_TF0_MASK)
12968 
12969 #define CAAM_RDSTA_TF1_MASK                      (0x200U)
12970 #define CAAM_RDSTA_TF1_SHIFT                     (9U)
12971 #define CAAM_RDSTA_TF1(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_TF1_SHIFT)) & CAAM_RDSTA_TF1_MASK)
12972 
12973 #define CAAM_RDSTA_ERRCODE_MASK                  (0xF0000U)
12974 #define CAAM_RDSTA_ERRCODE_SHIFT                 (16U)
12975 #define CAAM_RDSTA_ERRCODE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_ERRCODE_SHIFT)) & CAAM_RDSTA_ERRCODE_MASK)
12976 
12977 #define CAAM_RDSTA_CE_MASK                       (0x100000U)
12978 #define CAAM_RDSTA_CE_SHIFT                      (20U)
12979 #define CAAM_RDSTA_CE(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_CE_SHIFT)) & CAAM_RDSTA_CE_MASK)
12980 
12981 #define CAAM_RDSTA_SKVN_MASK                     (0x40000000U)
12982 #define CAAM_RDSTA_SKVN_SHIFT                    (30U)
12983 #define CAAM_RDSTA_SKVN(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_SKVN_SHIFT)) & CAAM_RDSTA_SKVN_MASK)
12984 
12985 #define CAAM_RDSTA_SKVT_MASK                     (0x80000000U)
12986 #define CAAM_RDSTA_SKVT_SHIFT                    (31U)
12987 #define CAAM_RDSTA_SKVT(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_SKVT_SHIFT)) & CAAM_RDSTA_SKVT_MASK)
12988 /*! @} */
12989 
12990 /*! @name RDINT0 - RNG DRNG State Handle 0 Reseed Interval Register */
12991 /*! @{ */
12992 
12993 #define CAAM_RDINT0_RESINT0_MASK                 (0xFFFFFFFFU)
12994 #define CAAM_RDINT0_RESINT0_SHIFT                (0U)
12995 #define CAAM_RDINT0_RESINT0(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RDINT0_RESINT0_SHIFT)) & CAAM_RDINT0_RESINT0_MASK)
12996 /*! @} */
12997 
12998 /*! @name RDINT1 - RNG DRNG State Handle 1 Reseed Interval Register */
12999 /*! @{ */
13000 
13001 #define CAAM_RDINT1_RESINT1_MASK                 (0xFFFFFFFFU)
13002 #define CAAM_RDINT1_RESINT1_SHIFT                (0U)
13003 #define CAAM_RDINT1_RESINT1(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RDINT1_RESINT1_SHIFT)) & CAAM_RDINT1_RESINT1_MASK)
13004 /*! @} */
13005 
13006 /*! @name RDHCNTL - RNG DRNG Hash Control Register */
13007 /*! @{ */
13008 
13009 #define CAAM_RDHCNTL_HD_MASK                     (0x1U)
13010 #define CAAM_RDHCNTL_HD_SHIFT                    (0U)
13011 #define CAAM_RDHCNTL_HD(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HD_SHIFT)) & CAAM_RDHCNTL_HD_MASK)
13012 
13013 #define CAAM_RDHCNTL_HB_MASK                     (0x2U)
13014 #define CAAM_RDHCNTL_HB_SHIFT                    (1U)
13015 #define CAAM_RDHCNTL_HB(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HB_SHIFT)) & CAAM_RDHCNTL_HB_MASK)
13016 
13017 #define CAAM_RDHCNTL_HI_MASK                     (0x4U)
13018 #define CAAM_RDHCNTL_HI_SHIFT                    (2U)
13019 #define CAAM_RDHCNTL_HI(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HI_SHIFT)) & CAAM_RDHCNTL_HI_MASK)
13020 
13021 #define CAAM_RDHCNTL_HTM_MASK                    (0x8U)
13022 #define CAAM_RDHCNTL_HTM_SHIFT                   (3U)
13023 #define CAAM_RDHCNTL_HTM(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HTM_SHIFT)) & CAAM_RDHCNTL_HTM_MASK)
13024 
13025 #define CAAM_RDHCNTL_HTC_MASK                    (0x10U)
13026 #define CAAM_RDHCNTL_HTC_SHIFT                   (4U)
13027 #define CAAM_RDHCNTL_HTC(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HTC_SHIFT)) & CAAM_RDHCNTL_HTC_MASK)
13028 /*! @} */
13029 
13030 /*! @name RDHDIG - RNG DRNG Hash Digest Register */
13031 /*! @{ */
13032 
13033 #define CAAM_RDHDIG_HASHMD_MASK                  (0xFFFFFFFFU)
13034 #define CAAM_RDHDIG_HASHMD_SHIFT                 (0U)
13035 #define CAAM_RDHDIG_HASHMD(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_RDHDIG_HASHMD_SHIFT)) & CAAM_RDHDIG_HASHMD_MASK)
13036 /*! @} */
13037 
13038 /*! @name RDHBUF - RNG DRNG Hash Buffer Register */
13039 /*! @{ */
13040 
13041 #define CAAM_RDHBUF_HASHBUF_MASK                 (0xFFFFFFFFU)
13042 #define CAAM_RDHBUF_HASHBUF_SHIFT                (0U)
13043 #define CAAM_RDHBUF_HASHBUF(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_RDHBUF_HASHBUF_SHIFT)) & CAAM_RDHBUF_HASHBUF_MASK)
13044 /*! @} */
13045 
13046 /*! @name PX_SDID_PG0 - Partition 0 SDID register..Partition 15 SDID register */
13047 /*! @{ */
13048 
13049 #define CAAM_PX_SDID_PG0_SDID_MASK               (0xFFFFU)
13050 #define CAAM_PX_SDID_PG0_SDID_SHIFT              (0U)
13051 #define CAAM_PX_SDID_PG0_SDID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDID_PG0_SDID_SHIFT)) & CAAM_PX_SDID_PG0_SDID_MASK)
13052 /*! @} */
13053 
13054 /* The count of CAAM_PX_SDID_PG0 */
13055 #define CAAM_PX_SDID_PG0_COUNT                   (16U)
13056 
13057 /*! @name PX_SMAPR_PG0 - Secure Memory Access Permissions register */
13058 /*! @{ */
13059 
13060 #define CAAM_PX_SMAPR_PG0_G1_READ_MASK           (0x1U)
13061 #define CAAM_PX_SMAPR_PG0_G1_READ_SHIFT          (0U)
13062 /*! G1_READ
13063  *  0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and
13064  *       key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a
13065  *       Trusted Descriptor and G1_TDO=1).
13066  *  0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
13067  *       G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0).
13068  */
13069 #define CAAM_PX_SMAPR_PG0_G1_READ(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_READ_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_READ_MASK)
13070 
13071 #define CAAM_PX_SMAPR_PG0_G1_WRITE_MASK          (0x2U)
13072 #define CAAM_PX_SMAPR_PG0_G1_WRITE_SHIFT         (1U)
13073 /*! G1_WRITE
13074  *  0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
13075  *       Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1).
13076  *  0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is
13077  *       not a Trusted Descriptor or if G1_TDO=0).
13078  */
13079 #define CAAM_PX_SMAPR_PG0_G1_WRITE(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_WRITE_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_WRITE_MASK)
13080 
13081 #define CAAM_PX_SMAPR_PG0_G1_TDO_MASK            (0x4U)
13082 #define CAAM_PX_SMAPR_PG0_G1_TDO_SHIFT           (2U)
13083 /*! G1_TDO
13084  *  0b0..Trusted Descriptors have the same access privileges as Job Descriptors
13085  *  0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
13086  *       or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB,
13087  *       G1_WRITE and G1_READ settings.
13088  */
13089 #define CAAM_PX_SMAPR_PG0_G1_TDO(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_TDO_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_TDO_MASK)
13090 
13091 #define CAAM_PX_SMAPR_PG0_G1_SMBLOB_MASK         (0x8U)
13092 #define CAAM_PX_SMAPR_PG0_G1_SMBLOB_SHIFT        (3U)
13093 /*! G1_SMBLOB
13094  *  0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1.
13095  *  0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings.
13096  */
13097 #define CAAM_PX_SMAPR_PG0_G1_SMBLOB(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_SMBLOB_MASK)
13098 
13099 #define CAAM_PX_SMAPR_PG0_G2_READ_MASK           (0x10U)
13100 #define CAAM_PX_SMAPR_PG0_G2_READ_SHIFT          (4U)
13101 /*! G2_READ
13102  *  0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and
13103  *       key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a
13104  *       Trusted Descriptor and G2_TDO=1).
13105  *  0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
13106  *       G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0).
13107  */
13108 #define CAAM_PX_SMAPR_PG0_G2_READ(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_READ_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_READ_MASK)
13109 
13110 #define CAAM_PX_SMAPR_PG0_G2_WRITE_MASK          (0x20U)
13111 #define CAAM_PX_SMAPR_PG0_G2_WRITE_SHIFT         (5U)
13112 /*! G2_WRITE
13113  *  0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
13114  *       Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1).
13115  *  0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is
13116  *       not a Trusted Descriptor or if G2_TDO=0).
13117  */
13118 #define CAAM_PX_SMAPR_PG0_G2_WRITE(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_WRITE_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_WRITE_MASK)
13119 
13120 #define CAAM_PX_SMAPR_PG0_G2_TDO_MASK            (0x40U)
13121 #define CAAM_PX_SMAPR_PG0_G2_TDO_SHIFT           (6U)
13122 /*! G2_TDO
13123  *  0b0..Trusted Descriptors have the same access privileges as Job Descriptors
13124  *  0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
13125  *       or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB,
13126  *       G2_WRITE and G2_READ settings.
13127  */
13128 #define CAAM_PX_SMAPR_PG0_G2_TDO(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_TDO_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_TDO_MASK)
13129 
13130 #define CAAM_PX_SMAPR_PG0_G2_SMBLOB_MASK         (0x80U)
13131 #define CAAM_PX_SMAPR_PG0_G2_SMBLOB_SHIFT        (7U)
13132 /*! G2_SMBLOB
13133  *  0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1.
13134  *  0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings.
13135  */
13136 #define CAAM_PX_SMAPR_PG0_G2_SMBLOB(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_SMBLOB_MASK)
13137 
13138 #define CAAM_PX_SMAPR_PG0_SMAG_LCK_MASK          (0x1000U)
13139 #define CAAM_PX_SMAPR_PG0_SMAG_LCK_SHIFT         (12U)
13140 /*! SMAG_LCK
13141  *  0b0..The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers.
13142  *  0b1..The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed
13143  *       until the partition is de-allocated or a POR occurs.
13144  */
13145 #define CAAM_PX_SMAPR_PG0_SMAG_LCK(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_SMAG_LCK_SHIFT)) & CAAM_PX_SMAPR_PG0_SMAG_LCK_MASK)
13146 
13147 #define CAAM_PX_SMAPR_PG0_SMAP_LCK_MASK          (0x2000U)
13148 #define CAAM_PX_SMAPR_PG0_SMAP_LCK_SHIFT         (13U)
13149 /*! SMAP_LCK
13150  *  0b0..The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register.
13151  *  0b1..The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP
13152  *       register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can
13153  *       still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0.
13154  */
13155 #define CAAM_PX_SMAPR_PG0_SMAP_LCK(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_SMAP_LCK_SHIFT)) & CAAM_PX_SMAPR_PG0_SMAP_LCK_MASK)
13156 
13157 #define CAAM_PX_SMAPR_PG0_PSP_MASK               (0x4000U)
13158 #define CAAM_PX_SMAPR_PG0_PSP_SHIFT              (14U)
13159 /*! PSP
13160  *  0b0..The partition and any of the pages allocated to the partition can be de-allocated.
13161  *  0b1..The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated.
13162  */
13163 #define CAAM_PX_SMAPR_PG0_PSP(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_PSP_SHIFT)) & CAAM_PX_SMAPR_PG0_PSP_MASK)
13164 
13165 #define CAAM_PX_SMAPR_PG0_CSP_MASK               (0x8000U)
13166 #define CAAM_PX_SMAPR_PG0_CSP_SHIFT              (15U)
13167 /*! CSP
13168  *  0b0..The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is
13169  *       released or a security alarm occurs.
13170  *  0b1..The pages allocated to the partition will be zeroized when they are individually de-allocated or the
13171  *       partition is released or a security alarm occurs.
13172  */
13173 #define CAAM_PX_SMAPR_PG0_CSP(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_CSP_SHIFT)) & CAAM_PX_SMAPR_PG0_CSP_MASK)
13174 
13175 #define CAAM_PX_SMAPR_PG0_PARTITION_KMOD_MASK    (0xFFFF0000U)
13176 #define CAAM_PX_SMAPR_PG0_PARTITION_KMOD_SHIFT   (16U)
13177 #define CAAM_PX_SMAPR_PG0_PARTITION_KMOD(x)      (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_PARTITION_KMOD_SHIFT)) & CAAM_PX_SMAPR_PG0_PARTITION_KMOD_MASK)
13178 /*! @} */
13179 
13180 /* The count of CAAM_PX_SMAPR_PG0 */
13181 #define CAAM_PX_SMAPR_PG0_COUNT                  (16U)
13182 
13183 /*! @name PX_SMAG2_PG0 - Secure Memory Access Group Registers */
13184 /*! @{ */
13185 
13186 #define CAAM_PX_SMAG2_PG0_Gx_ID00_MASK           (0x1U)
13187 #define CAAM_PX_SMAG2_PG0_Gx_ID00_SHIFT          (0U)
13188 #define CAAM_PX_SMAG2_PG0_Gx_ID00(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID00_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID00_MASK)
13189 
13190 #define CAAM_PX_SMAG2_PG0_Gx_ID01_MASK           (0x2U)
13191 #define CAAM_PX_SMAG2_PG0_Gx_ID01_SHIFT          (1U)
13192 #define CAAM_PX_SMAG2_PG0_Gx_ID01(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID01_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID01_MASK)
13193 
13194 #define CAAM_PX_SMAG2_PG0_Gx_ID02_MASK           (0x4U)
13195 #define CAAM_PX_SMAG2_PG0_Gx_ID02_SHIFT          (2U)
13196 #define CAAM_PX_SMAG2_PG0_Gx_ID02(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID02_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID02_MASK)
13197 
13198 #define CAAM_PX_SMAG2_PG0_Gx_ID03_MASK           (0x8U)
13199 #define CAAM_PX_SMAG2_PG0_Gx_ID03_SHIFT          (3U)
13200 #define CAAM_PX_SMAG2_PG0_Gx_ID03(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID03_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID03_MASK)
13201 
13202 #define CAAM_PX_SMAG2_PG0_Gx_ID04_MASK           (0x10U)
13203 #define CAAM_PX_SMAG2_PG0_Gx_ID04_SHIFT          (4U)
13204 #define CAAM_PX_SMAG2_PG0_Gx_ID04(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID04_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID04_MASK)
13205 
13206 #define CAAM_PX_SMAG2_PG0_Gx_ID05_MASK           (0x20U)
13207 #define CAAM_PX_SMAG2_PG0_Gx_ID05_SHIFT          (5U)
13208 #define CAAM_PX_SMAG2_PG0_Gx_ID05(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID05_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID05_MASK)
13209 
13210 #define CAAM_PX_SMAG2_PG0_Gx_ID06_MASK           (0x40U)
13211 #define CAAM_PX_SMAG2_PG0_Gx_ID06_SHIFT          (6U)
13212 #define CAAM_PX_SMAG2_PG0_Gx_ID06(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID06_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID06_MASK)
13213 
13214 #define CAAM_PX_SMAG2_PG0_Gx_ID07_MASK           (0x80U)
13215 #define CAAM_PX_SMAG2_PG0_Gx_ID07_SHIFT          (7U)
13216 #define CAAM_PX_SMAG2_PG0_Gx_ID07(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID07_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID07_MASK)
13217 
13218 #define CAAM_PX_SMAG2_PG0_Gx_ID08_MASK           (0x100U)
13219 #define CAAM_PX_SMAG2_PG0_Gx_ID08_SHIFT          (8U)
13220 #define CAAM_PX_SMAG2_PG0_Gx_ID08(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID08_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID08_MASK)
13221 
13222 #define CAAM_PX_SMAG2_PG0_Gx_ID09_MASK           (0x200U)
13223 #define CAAM_PX_SMAG2_PG0_Gx_ID09_SHIFT          (9U)
13224 #define CAAM_PX_SMAG2_PG0_Gx_ID09(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID09_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID09_MASK)
13225 
13226 #define CAAM_PX_SMAG2_PG0_Gx_ID10_MASK           (0x400U)
13227 #define CAAM_PX_SMAG2_PG0_Gx_ID10_SHIFT          (10U)
13228 #define CAAM_PX_SMAG2_PG0_Gx_ID10(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID10_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID10_MASK)
13229 
13230 #define CAAM_PX_SMAG2_PG0_Gx_ID11_MASK           (0x800U)
13231 #define CAAM_PX_SMAG2_PG0_Gx_ID11_SHIFT          (11U)
13232 #define CAAM_PX_SMAG2_PG0_Gx_ID11(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID11_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID11_MASK)
13233 
13234 #define CAAM_PX_SMAG2_PG0_Gx_ID12_MASK           (0x1000U)
13235 #define CAAM_PX_SMAG2_PG0_Gx_ID12_SHIFT          (12U)
13236 #define CAAM_PX_SMAG2_PG0_Gx_ID12(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID12_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID12_MASK)
13237 
13238 #define CAAM_PX_SMAG2_PG0_Gx_ID13_MASK           (0x2000U)
13239 #define CAAM_PX_SMAG2_PG0_Gx_ID13_SHIFT          (13U)
13240 #define CAAM_PX_SMAG2_PG0_Gx_ID13(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID13_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID13_MASK)
13241 
13242 #define CAAM_PX_SMAG2_PG0_Gx_ID14_MASK           (0x4000U)
13243 #define CAAM_PX_SMAG2_PG0_Gx_ID14_SHIFT          (14U)
13244 #define CAAM_PX_SMAG2_PG0_Gx_ID14(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID14_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID14_MASK)
13245 
13246 #define CAAM_PX_SMAG2_PG0_Gx_ID15_MASK           (0x8000U)
13247 #define CAAM_PX_SMAG2_PG0_Gx_ID15_SHIFT          (15U)
13248 #define CAAM_PX_SMAG2_PG0_Gx_ID15(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID15_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID15_MASK)
13249 
13250 #define CAAM_PX_SMAG2_PG0_Gx_ID16_MASK           (0x10000U)
13251 #define CAAM_PX_SMAG2_PG0_Gx_ID16_SHIFT          (16U)
13252 #define CAAM_PX_SMAG2_PG0_Gx_ID16(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID16_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID16_MASK)
13253 
13254 #define CAAM_PX_SMAG2_PG0_Gx_ID17_MASK           (0x20000U)
13255 #define CAAM_PX_SMAG2_PG0_Gx_ID17_SHIFT          (17U)
13256 #define CAAM_PX_SMAG2_PG0_Gx_ID17(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID17_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID17_MASK)
13257 
13258 #define CAAM_PX_SMAG2_PG0_Gx_ID18_MASK           (0x40000U)
13259 #define CAAM_PX_SMAG2_PG0_Gx_ID18_SHIFT          (18U)
13260 #define CAAM_PX_SMAG2_PG0_Gx_ID18(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID18_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID18_MASK)
13261 
13262 #define CAAM_PX_SMAG2_PG0_Gx_ID19_MASK           (0x80000U)
13263 #define CAAM_PX_SMAG2_PG0_Gx_ID19_SHIFT          (19U)
13264 #define CAAM_PX_SMAG2_PG0_Gx_ID19(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID19_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID19_MASK)
13265 
13266 #define CAAM_PX_SMAG2_PG0_Gx_ID20_MASK           (0x100000U)
13267 #define CAAM_PX_SMAG2_PG0_Gx_ID20_SHIFT          (20U)
13268 #define CAAM_PX_SMAG2_PG0_Gx_ID20(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID20_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID20_MASK)
13269 
13270 #define CAAM_PX_SMAG2_PG0_Gx_ID21_MASK           (0x200000U)
13271 #define CAAM_PX_SMAG2_PG0_Gx_ID21_SHIFT          (21U)
13272 #define CAAM_PX_SMAG2_PG0_Gx_ID21(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID21_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID21_MASK)
13273 
13274 #define CAAM_PX_SMAG2_PG0_Gx_ID22_MASK           (0x400000U)
13275 #define CAAM_PX_SMAG2_PG0_Gx_ID22_SHIFT          (22U)
13276 #define CAAM_PX_SMAG2_PG0_Gx_ID22(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID22_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID22_MASK)
13277 
13278 #define CAAM_PX_SMAG2_PG0_Gx_ID23_MASK           (0x800000U)
13279 #define CAAM_PX_SMAG2_PG0_Gx_ID23_SHIFT          (23U)
13280 #define CAAM_PX_SMAG2_PG0_Gx_ID23(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID23_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID23_MASK)
13281 
13282 #define CAAM_PX_SMAG2_PG0_Gx_ID24_MASK           (0x1000000U)
13283 #define CAAM_PX_SMAG2_PG0_Gx_ID24_SHIFT          (24U)
13284 #define CAAM_PX_SMAG2_PG0_Gx_ID24(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID24_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID24_MASK)
13285 
13286 #define CAAM_PX_SMAG2_PG0_Gx_ID25_MASK           (0x2000000U)
13287 #define CAAM_PX_SMAG2_PG0_Gx_ID25_SHIFT          (25U)
13288 #define CAAM_PX_SMAG2_PG0_Gx_ID25(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID25_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID25_MASK)
13289 
13290 #define CAAM_PX_SMAG2_PG0_Gx_ID26_MASK           (0x4000000U)
13291 #define CAAM_PX_SMAG2_PG0_Gx_ID26_SHIFT          (26U)
13292 #define CAAM_PX_SMAG2_PG0_Gx_ID26(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID26_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID26_MASK)
13293 
13294 #define CAAM_PX_SMAG2_PG0_Gx_ID27_MASK           (0x8000000U)
13295 #define CAAM_PX_SMAG2_PG0_Gx_ID27_SHIFT          (27U)
13296 #define CAAM_PX_SMAG2_PG0_Gx_ID27(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID27_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID27_MASK)
13297 
13298 #define CAAM_PX_SMAG2_PG0_Gx_ID28_MASK           (0x10000000U)
13299 #define CAAM_PX_SMAG2_PG0_Gx_ID28_SHIFT          (28U)
13300 #define CAAM_PX_SMAG2_PG0_Gx_ID28(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID28_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID28_MASK)
13301 
13302 #define CAAM_PX_SMAG2_PG0_Gx_ID29_MASK           (0x20000000U)
13303 #define CAAM_PX_SMAG2_PG0_Gx_ID29_SHIFT          (29U)
13304 #define CAAM_PX_SMAG2_PG0_Gx_ID29(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID29_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID29_MASK)
13305 
13306 #define CAAM_PX_SMAG2_PG0_Gx_ID30_MASK           (0x40000000U)
13307 #define CAAM_PX_SMAG2_PG0_Gx_ID30_SHIFT          (30U)
13308 #define CAAM_PX_SMAG2_PG0_Gx_ID30(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID30_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID30_MASK)
13309 
13310 #define CAAM_PX_SMAG2_PG0_Gx_ID31_MASK           (0x80000000U)
13311 #define CAAM_PX_SMAG2_PG0_Gx_ID31_SHIFT          (31U)
13312 #define CAAM_PX_SMAG2_PG0_Gx_ID31(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID31_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID31_MASK)
13313 /*! @} */
13314 
13315 /* The count of CAAM_PX_SMAG2_PG0 */
13316 #define CAAM_PX_SMAG2_PG0_COUNT                  (16U)
13317 
13318 /*! @name PX_SMAG1_PG0 - Secure Memory Access Group Registers */
13319 /*! @{ */
13320 
13321 #define CAAM_PX_SMAG1_PG0_Gx_ID00_MASK           (0x1U)
13322 #define CAAM_PX_SMAG1_PG0_Gx_ID00_SHIFT          (0U)
13323 #define CAAM_PX_SMAG1_PG0_Gx_ID00(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID00_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID00_MASK)
13324 
13325 #define CAAM_PX_SMAG1_PG0_Gx_ID01_MASK           (0x2U)
13326 #define CAAM_PX_SMAG1_PG0_Gx_ID01_SHIFT          (1U)
13327 #define CAAM_PX_SMAG1_PG0_Gx_ID01(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID01_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID01_MASK)
13328 
13329 #define CAAM_PX_SMAG1_PG0_Gx_ID02_MASK           (0x4U)
13330 #define CAAM_PX_SMAG1_PG0_Gx_ID02_SHIFT          (2U)
13331 #define CAAM_PX_SMAG1_PG0_Gx_ID02(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID02_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID02_MASK)
13332 
13333 #define CAAM_PX_SMAG1_PG0_Gx_ID03_MASK           (0x8U)
13334 #define CAAM_PX_SMAG1_PG0_Gx_ID03_SHIFT          (3U)
13335 #define CAAM_PX_SMAG1_PG0_Gx_ID03(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID03_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID03_MASK)
13336 
13337 #define CAAM_PX_SMAG1_PG0_Gx_ID04_MASK           (0x10U)
13338 #define CAAM_PX_SMAG1_PG0_Gx_ID04_SHIFT          (4U)
13339 #define CAAM_PX_SMAG1_PG0_Gx_ID04(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID04_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID04_MASK)
13340 
13341 #define CAAM_PX_SMAG1_PG0_Gx_ID05_MASK           (0x20U)
13342 #define CAAM_PX_SMAG1_PG0_Gx_ID05_SHIFT          (5U)
13343 #define CAAM_PX_SMAG1_PG0_Gx_ID05(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID05_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID05_MASK)
13344 
13345 #define CAAM_PX_SMAG1_PG0_Gx_ID06_MASK           (0x40U)
13346 #define CAAM_PX_SMAG1_PG0_Gx_ID06_SHIFT          (6U)
13347 #define CAAM_PX_SMAG1_PG0_Gx_ID06(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID06_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID06_MASK)
13348 
13349 #define CAAM_PX_SMAG1_PG0_Gx_ID07_MASK           (0x80U)
13350 #define CAAM_PX_SMAG1_PG0_Gx_ID07_SHIFT          (7U)
13351 #define CAAM_PX_SMAG1_PG0_Gx_ID07(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID07_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID07_MASK)
13352 
13353 #define CAAM_PX_SMAG1_PG0_Gx_ID08_MASK           (0x100U)
13354 #define CAAM_PX_SMAG1_PG0_Gx_ID08_SHIFT          (8U)
13355 #define CAAM_PX_SMAG1_PG0_Gx_ID08(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID08_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID08_MASK)
13356 
13357 #define CAAM_PX_SMAG1_PG0_Gx_ID09_MASK           (0x200U)
13358 #define CAAM_PX_SMAG1_PG0_Gx_ID09_SHIFT          (9U)
13359 #define CAAM_PX_SMAG1_PG0_Gx_ID09(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID09_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID09_MASK)
13360 
13361 #define CAAM_PX_SMAG1_PG0_Gx_ID10_MASK           (0x400U)
13362 #define CAAM_PX_SMAG1_PG0_Gx_ID10_SHIFT          (10U)
13363 #define CAAM_PX_SMAG1_PG0_Gx_ID10(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID10_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID10_MASK)
13364 
13365 #define CAAM_PX_SMAG1_PG0_Gx_ID11_MASK           (0x800U)
13366 #define CAAM_PX_SMAG1_PG0_Gx_ID11_SHIFT          (11U)
13367 #define CAAM_PX_SMAG1_PG0_Gx_ID11(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID11_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID11_MASK)
13368 
13369 #define CAAM_PX_SMAG1_PG0_Gx_ID12_MASK           (0x1000U)
13370 #define CAAM_PX_SMAG1_PG0_Gx_ID12_SHIFT          (12U)
13371 #define CAAM_PX_SMAG1_PG0_Gx_ID12(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID12_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID12_MASK)
13372 
13373 #define CAAM_PX_SMAG1_PG0_Gx_ID13_MASK           (0x2000U)
13374 #define CAAM_PX_SMAG1_PG0_Gx_ID13_SHIFT          (13U)
13375 #define CAAM_PX_SMAG1_PG0_Gx_ID13(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID13_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID13_MASK)
13376 
13377 #define CAAM_PX_SMAG1_PG0_Gx_ID14_MASK           (0x4000U)
13378 #define CAAM_PX_SMAG1_PG0_Gx_ID14_SHIFT          (14U)
13379 #define CAAM_PX_SMAG1_PG0_Gx_ID14(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID14_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID14_MASK)
13380 
13381 #define CAAM_PX_SMAG1_PG0_Gx_ID15_MASK           (0x8000U)
13382 #define CAAM_PX_SMAG1_PG0_Gx_ID15_SHIFT          (15U)
13383 #define CAAM_PX_SMAG1_PG0_Gx_ID15(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID15_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID15_MASK)
13384 
13385 #define CAAM_PX_SMAG1_PG0_Gx_ID16_MASK           (0x10000U)
13386 #define CAAM_PX_SMAG1_PG0_Gx_ID16_SHIFT          (16U)
13387 #define CAAM_PX_SMAG1_PG0_Gx_ID16(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID16_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID16_MASK)
13388 
13389 #define CAAM_PX_SMAG1_PG0_Gx_ID17_MASK           (0x20000U)
13390 #define CAAM_PX_SMAG1_PG0_Gx_ID17_SHIFT          (17U)
13391 #define CAAM_PX_SMAG1_PG0_Gx_ID17(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID17_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID17_MASK)
13392 
13393 #define CAAM_PX_SMAG1_PG0_Gx_ID18_MASK           (0x40000U)
13394 #define CAAM_PX_SMAG1_PG0_Gx_ID18_SHIFT          (18U)
13395 #define CAAM_PX_SMAG1_PG0_Gx_ID18(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID18_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID18_MASK)
13396 
13397 #define CAAM_PX_SMAG1_PG0_Gx_ID19_MASK           (0x80000U)
13398 #define CAAM_PX_SMAG1_PG0_Gx_ID19_SHIFT          (19U)
13399 #define CAAM_PX_SMAG1_PG0_Gx_ID19(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID19_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID19_MASK)
13400 
13401 #define CAAM_PX_SMAG1_PG0_Gx_ID20_MASK           (0x100000U)
13402 #define CAAM_PX_SMAG1_PG0_Gx_ID20_SHIFT          (20U)
13403 #define CAAM_PX_SMAG1_PG0_Gx_ID20(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID20_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID20_MASK)
13404 
13405 #define CAAM_PX_SMAG1_PG0_Gx_ID21_MASK           (0x200000U)
13406 #define CAAM_PX_SMAG1_PG0_Gx_ID21_SHIFT          (21U)
13407 #define CAAM_PX_SMAG1_PG0_Gx_ID21(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID21_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID21_MASK)
13408 
13409 #define CAAM_PX_SMAG1_PG0_Gx_ID22_MASK           (0x400000U)
13410 #define CAAM_PX_SMAG1_PG0_Gx_ID22_SHIFT          (22U)
13411 #define CAAM_PX_SMAG1_PG0_Gx_ID22(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID22_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID22_MASK)
13412 
13413 #define CAAM_PX_SMAG1_PG0_Gx_ID23_MASK           (0x800000U)
13414 #define CAAM_PX_SMAG1_PG0_Gx_ID23_SHIFT          (23U)
13415 #define CAAM_PX_SMAG1_PG0_Gx_ID23(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID23_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID23_MASK)
13416 
13417 #define CAAM_PX_SMAG1_PG0_Gx_ID24_MASK           (0x1000000U)
13418 #define CAAM_PX_SMAG1_PG0_Gx_ID24_SHIFT          (24U)
13419 #define CAAM_PX_SMAG1_PG0_Gx_ID24(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID24_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID24_MASK)
13420 
13421 #define CAAM_PX_SMAG1_PG0_Gx_ID25_MASK           (0x2000000U)
13422 #define CAAM_PX_SMAG1_PG0_Gx_ID25_SHIFT          (25U)
13423 #define CAAM_PX_SMAG1_PG0_Gx_ID25(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID25_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID25_MASK)
13424 
13425 #define CAAM_PX_SMAG1_PG0_Gx_ID26_MASK           (0x4000000U)
13426 #define CAAM_PX_SMAG1_PG0_Gx_ID26_SHIFT          (26U)
13427 #define CAAM_PX_SMAG1_PG0_Gx_ID26(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID26_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID26_MASK)
13428 
13429 #define CAAM_PX_SMAG1_PG0_Gx_ID27_MASK           (0x8000000U)
13430 #define CAAM_PX_SMAG1_PG0_Gx_ID27_SHIFT          (27U)
13431 #define CAAM_PX_SMAG1_PG0_Gx_ID27(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID27_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID27_MASK)
13432 
13433 #define CAAM_PX_SMAG1_PG0_Gx_ID28_MASK           (0x10000000U)
13434 #define CAAM_PX_SMAG1_PG0_Gx_ID28_SHIFT          (28U)
13435 #define CAAM_PX_SMAG1_PG0_Gx_ID28(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID28_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID28_MASK)
13436 
13437 #define CAAM_PX_SMAG1_PG0_Gx_ID29_MASK           (0x20000000U)
13438 #define CAAM_PX_SMAG1_PG0_Gx_ID29_SHIFT          (29U)
13439 #define CAAM_PX_SMAG1_PG0_Gx_ID29(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID29_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID29_MASK)
13440 
13441 #define CAAM_PX_SMAG1_PG0_Gx_ID30_MASK           (0x40000000U)
13442 #define CAAM_PX_SMAG1_PG0_Gx_ID30_SHIFT          (30U)
13443 #define CAAM_PX_SMAG1_PG0_Gx_ID30(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID30_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID30_MASK)
13444 
13445 #define CAAM_PX_SMAG1_PG0_Gx_ID31_MASK           (0x80000000U)
13446 #define CAAM_PX_SMAG1_PG0_Gx_ID31_SHIFT          (31U)
13447 #define CAAM_PX_SMAG1_PG0_Gx_ID31(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID31_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID31_MASK)
13448 /*! @} */
13449 
13450 /* The count of CAAM_PX_SMAG1_PG0 */
13451 #define CAAM_PX_SMAG1_PG0_COUNT                  (16U)
13452 
13453 /*! @name REIS - Recoverable Error Interrupt Status */
13454 /*! @{ */
13455 
13456 #define CAAM_REIS_CWDE_MASK                      (0x1U)
13457 #define CAAM_REIS_CWDE_SHIFT                     (0U)
13458 #define CAAM_REIS_CWDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_CWDE_SHIFT)) & CAAM_REIS_CWDE_MASK)
13459 
13460 #define CAAM_REIS_RBAE_MASK                      (0x10000U)
13461 #define CAAM_REIS_RBAE_SHIFT                     (16U)
13462 #define CAAM_REIS_RBAE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_RBAE_SHIFT)) & CAAM_REIS_RBAE_MASK)
13463 
13464 #define CAAM_REIS_JBAE0_MASK                     (0x1000000U)
13465 #define CAAM_REIS_JBAE0_SHIFT                    (24U)
13466 #define CAAM_REIS_JBAE0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE0_SHIFT)) & CAAM_REIS_JBAE0_MASK)
13467 
13468 #define CAAM_REIS_JBAE1_MASK                     (0x2000000U)
13469 #define CAAM_REIS_JBAE1_SHIFT                    (25U)
13470 #define CAAM_REIS_JBAE1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE1_SHIFT)) & CAAM_REIS_JBAE1_MASK)
13471 
13472 #define CAAM_REIS_JBAE2_MASK                     (0x4000000U)
13473 #define CAAM_REIS_JBAE2_SHIFT                    (26U)
13474 #define CAAM_REIS_JBAE2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE2_SHIFT)) & CAAM_REIS_JBAE2_MASK)
13475 
13476 #define CAAM_REIS_JBAE3_MASK                     (0x8000000U)
13477 #define CAAM_REIS_JBAE3_SHIFT                    (27U)
13478 #define CAAM_REIS_JBAE3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE3_SHIFT)) & CAAM_REIS_JBAE3_MASK)
13479 /*! @} */
13480 
13481 /*! @name REIE - Recoverable Error Interrupt Enable */
13482 /*! @{ */
13483 
13484 #define CAAM_REIE_CWDE_MASK                      (0x1U)
13485 #define CAAM_REIE_CWDE_SHIFT                     (0U)
13486 #define CAAM_REIE_CWDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_CWDE_SHIFT)) & CAAM_REIE_CWDE_MASK)
13487 
13488 #define CAAM_REIE_RBAE_MASK                      (0x10000U)
13489 #define CAAM_REIE_RBAE_SHIFT                     (16U)
13490 #define CAAM_REIE_RBAE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_RBAE_SHIFT)) & CAAM_REIE_RBAE_MASK)
13491 
13492 #define CAAM_REIE_JBAE0_MASK                     (0x1000000U)
13493 #define CAAM_REIE_JBAE0_SHIFT                    (24U)
13494 #define CAAM_REIE_JBAE0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE0_SHIFT)) & CAAM_REIE_JBAE0_MASK)
13495 
13496 #define CAAM_REIE_JBAE1_MASK                     (0x2000000U)
13497 #define CAAM_REIE_JBAE1_SHIFT                    (25U)
13498 #define CAAM_REIE_JBAE1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE1_SHIFT)) & CAAM_REIE_JBAE1_MASK)
13499 
13500 #define CAAM_REIE_JBAE2_MASK                     (0x4000000U)
13501 #define CAAM_REIE_JBAE2_SHIFT                    (26U)
13502 #define CAAM_REIE_JBAE2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE2_SHIFT)) & CAAM_REIE_JBAE2_MASK)
13503 
13504 #define CAAM_REIE_JBAE3_MASK                     (0x8000000U)
13505 #define CAAM_REIE_JBAE3_SHIFT                    (27U)
13506 #define CAAM_REIE_JBAE3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE3_SHIFT)) & CAAM_REIE_JBAE3_MASK)
13507 /*! @} */
13508 
13509 /*! @name REIF - Recoverable Error Interrupt Force */
13510 /*! @{ */
13511 
13512 #define CAAM_REIF_CWDE_MASK                      (0x1U)
13513 #define CAAM_REIF_CWDE_SHIFT                     (0U)
13514 #define CAAM_REIF_CWDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_CWDE_SHIFT)) & CAAM_REIF_CWDE_MASK)
13515 
13516 #define CAAM_REIF_RBAE_MASK                      (0x10000U)
13517 #define CAAM_REIF_RBAE_SHIFT                     (16U)
13518 #define CAAM_REIF_RBAE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_RBAE_SHIFT)) & CAAM_REIF_RBAE_MASK)
13519 
13520 #define CAAM_REIF_JBAE0_MASK                     (0x1000000U)
13521 #define CAAM_REIF_JBAE0_SHIFT                    (24U)
13522 #define CAAM_REIF_JBAE0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE0_SHIFT)) & CAAM_REIF_JBAE0_MASK)
13523 
13524 #define CAAM_REIF_JBAE1_MASK                     (0x2000000U)
13525 #define CAAM_REIF_JBAE1_SHIFT                    (25U)
13526 #define CAAM_REIF_JBAE1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE1_SHIFT)) & CAAM_REIF_JBAE1_MASK)
13527 
13528 #define CAAM_REIF_JBAE2_MASK                     (0x4000000U)
13529 #define CAAM_REIF_JBAE2_SHIFT                    (26U)
13530 #define CAAM_REIF_JBAE2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE2_SHIFT)) & CAAM_REIF_JBAE2_MASK)
13531 
13532 #define CAAM_REIF_JBAE3_MASK                     (0x8000000U)
13533 #define CAAM_REIF_JBAE3_SHIFT                    (27U)
13534 #define CAAM_REIF_JBAE3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE3_SHIFT)) & CAAM_REIF_JBAE3_MASK)
13535 /*! @} */
13536 
13537 /*! @name REIH - Recoverable Error Interrupt Halt */
13538 /*! @{ */
13539 
13540 #define CAAM_REIH_CWDE_MASK                      (0x1U)
13541 #define CAAM_REIH_CWDE_SHIFT                     (0U)
13542 /*! CWDE
13543  *  0b0..Don't halt CAAM if CAAM watchdog expired.
13544  *  0b1..Halt CAAM if CAAM watchdog expired..
13545  */
13546 #define CAAM_REIH_CWDE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_CWDE_SHIFT)) & CAAM_REIH_CWDE_MASK)
13547 
13548 #define CAAM_REIH_RBAE_MASK                      (0x10000U)
13549 #define CAAM_REIH_RBAE_SHIFT                     (16U)
13550 /*! RBAE
13551  *  0b0..Don't halt CAAM if RTIC-initiated job execution caused bus access error.
13552  *  0b1..Halt CAAM if RTIC-initiated job execution caused bus access error.
13553  */
13554 #define CAAM_REIH_RBAE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_RBAE_SHIFT)) & CAAM_REIH_RBAE_MASK)
13555 
13556 #define CAAM_REIH_JBAE0_MASK                     (0x1000000U)
13557 #define CAAM_REIH_JBAE0_SHIFT                    (24U)
13558 /*! JBAE0
13559  *  0b0..Don't halt CAAM if JR0-initiated job execution caused bus access error.
13560  *  0b1..Halt CAAM if JR0-initiated job execution caused bus access error.
13561  */
13562 #define CAAM_REIH_JBAE0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE0_SHIFT)) & CAAM_REIH_JBAE0_MASK)
13563 
13564 #define CAAM_REIH_JBAE1_MASK                     (0x2000000U)
13565 #define CAAM_REIH_JBAE1_SHIFT                    (25U)
13566 /*! JBAE1
13567  *  0b0..Don't halt CAAM if JR1-initiated job execution caused bus access error.
13568  *  0b1..Halt CAAM if JR1-initiated job execution caused bus access error.
13569  */
13570 #define CAAM_REIH_JBAE1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE1_SHIFT)) & CAAM_REIH_JBAE1_MASK)
13571 
13572 #define CAAM_REIH_JBAE2_MASK                     (0x4000000U)
13573 #define CAAM_REIH_JBAE2_SHIFT                    (26U)
13574 /*! JBAE2
13575  *  0b0..Don't halt CAAM if JR2-initiated job execution caused bus access error.
13576  *  0b1..Halt CAAM if JR2-initiated job execution caused bus access error.
13577  */
13578 #define CAAM_REIH_JBAE2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE2_SHIFT)) & CAAM_REIH_JBAE2_MASK)
13579 
13580 #define CAAM_REIH_JBAE3_MASK                     (0x8000000U)
13581 #define CAAM_REIH_JBAE3_SHIFT                    (27U)
13582 /*! JBAE3
13583  *  0b0..Don't halt CAAM if JR3-initiated job execution caused bus access error.
13584  *  0b1..Halt CAAM if JR3-initiated job execution caused bus access error.
13585  */
13586 #define CAAM_REIH_JBAE3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE3_SHIFT)) & CAAM_REIH_JBAE3_MASK)
13587 /*! @} */
13588 
13589 /*! @name SMWPJRR - Secure Memory Write Protect Job Ring Register */
13590 /*! @{ */
13591 
13592 #define CAAM_SMWPJRR_SMR_WP_JRa_MASK             (0x1U)
13593 #define CAAM_SMWPJRR_SMR_WP_JRa_SHIFT            (0U)
13594 #define CAAM_SMWPJRR_SMR_WP_JRa(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_SMWPJRR_SMR_WP_JRa_SHIFT)) & CAAM_SMWPJRR_SMR_WP_JRa_MASK)
13595 /*! @} */
13596 
13597 /* The count of CAAM_SMWPJRR */
13598 #define CAAM_SMWPJRR_COUNT                       (4U)
13599 
13600 /*! @name SMCR_PG0 - Secure Memory Command Register */
13601 /*! @{ */
13602 
13603 #define CAAM_SMCR_PG0_CMD_MASK                   (0xFU)
13604 #define CAAM_SMCR_PG0_CMD_SHIFT                  (0U)
13605 #define CAAM_SMCR_PG0_CMD(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_CMD_SHIFT)) & CAAM_SMCR_PG0_CMD_MASK)
13606 
13607 #define CAAM_SMCR_PG0_PRTN_MASK                  (0xF00U)
13608 #define CAAM_SMCR_PG0_PRTN_SHIFT                 (8U)
13609 #define CAAM_SMCR_PG0_PRTN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_PRTN_SHIFT)) & CAAM_SMCR_PG0_PRTN_MASK)
13610 
13611 #define CAAM_SMCR_PG0_PAGE_MASK                  (0xFFFF0000U)
13612 #define CAAM_SMCR_PG0_PAGE_SHIFT                 (16U)
13613 #define CAAM_SMCR_PG0_PAGE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_PAGE_SHIFT)) & CAAM_SMCR_PG0_PAGE_MASK)
13614 /*! @} */
13615 
13616 /*! @name SMCSR_PG0 - Secure Memory Command Status Register */
13617 /*! @{ */
13618 
13619 #define CAAM_SMCSR_PG0_PRTN_MASK                 (0xFU)
13620 #define CAAM_SMCSR_PG0_PRTN_SHIFT                (0U)
13621 #define CAAM_SMCSR_PG0_PRTN(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PRTN_SHIFT)) & CAAM_SMCSR_PG0_PRTN_MASK)
13622 
13623 #define CAAM_SMCSR_PG0_PO_MASK                   (0xC0U)
13624 #define CAAM_SMCSR_PG0_PO_SHIFT                  (6U)
13625 /*! PO
13626  *  0b00..Available; Unowned: The entity that issued the inquiry may allocate this page to a partition. No
13627  *        zeroization is needed since it has already been cleared, therefore no interrupt should be expected.
13628  *  0b01..Page does not exist in this version or is not initialized yet.
13629  *  0b10..Another entity owns the page. This page is unavailable to the issuer of the inquiry.
13630  *  0b11..Owned by the entity making the inquiry. The owner may de-allocate this page if its partition is not
13631  *        marked PSP. If the partition to which the page is allocated is designated as CSP, the page will be zeroized
13632  *        upon de-allocation.
13633  */
13634 #define CAAM_SMCSR_PG0_PO(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PO_SHIFT)) & CAAM_SMCSR_PG0_PO_MASK)
13635 
13636 #define CAAM_SMCSR_PG0_AERR_MASK                 (0x3000U)
13637 #define CAAM_SMCSR_PG0_AERR_SHIFT                (12U)
13638 #define CAAM_SMCSR_PG0_AERR(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_AERR_SHIFT)) & CAAM_SMCSR_PG0_AERR_MASK)
13639 
13640 #define CAAM_SMCSR_PG0_CERR_MASK                 (0xC000U)
13641 #define CAAM_SMCSR_PG0_CERR_SHIFT                (14U)
13642 /*! CERR
13643  *  0b00..No Error.
13644  *  0b01..Command has not yet completed.
13645  *  0b10..A security failure occurred.
13646  *  0b11..Command Overflow. Another command was issued by the same Job Ring owner before the owner's previous
13647  *        command completed. The additional command was ignored.
13648  */
13649 #define CAAM_SMCSR_PG0_CERR(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_CERR_SHIFT)) & CAAM_SMCSR_PG0_CERR_MASK)
13650 
13651 #define CAAM_SMCSR_PG0_PAGE_MASK                 (0xFFF0000U)
13652 #define CAAM_SMCSR_PG0_PAGE_SHIFT                (16U)
13653 #define CAAM_SMCSR_PG0_PAGE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PAGE_SHIFT)) & CAAM_SMCSR_PG0_PAGE_MASK)
13654 /*! @} */
13655 
13656 /*! @name CAAMVID_MS_TRAD - CAAM Version ID Register, most-significant half */
13657 /*! @{ */
13658 
13659 #define CAAM_CAAMVID_MS_TRAD_MIN_REV_MASK        (0xFFU)
13660 #define CAAM_CAAMVID_MS_TRAD_MIN_REV_SHIFT       (0U)
13661 #define CAAM_CAAMVID_MS_TRAD_MIN_REV(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_MIN_REV_SHIFT)) & CAAM_CAAMVID_MS_TRAD_MIN_REV_MASK)
13662 
13663 #define CAAM_CAAMVID_MS_TRAD_MAJ_REV_MASK        (0xFF00U)
13664 #define CAAM_CAAMVID_MS_TRAD_MAJ_REV_SHIFT       (8U)
13665 #define CAAM_CAAMVID_MS_TRAD_MAJ_REV(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_MAJ_REV_SHIFT)) & CAAM_CAAMVID_MS_TRAD_MAJ_REV_MASK)
13666 
13667 #define CAAM_CAAMVID_MS_TRAD_IP_ID_MASK          (0xFFFF0000U)
13668 #define CAAM_CAAMVID_MS_TRAD_IP_ID_SHIFT         (16U)
13669 #define CAAM_CAAMVID_MS_TRAD_IP_ID(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_IP_ID_SHIFT)) & CAAM_CAAMVID_MS_TRAD_IP_ID_MASK)
13670 /*! @} */
13671 
13672 /*! @name CAAMVID_LS_TRAD - CAAM Version ID Register, least-significant half */
13673 /*! @{ */
13674 
13675 #define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_MASK     (0xFFU)
13676 #define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_SHIFT    (0U)
13677 #define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_MASK)
13678 
13679 #define CAAM_CAAMVID_LS_TRAD_ECO_REV_MASK        (0xFF00U)
13680 #define CAAM_CAAMVID_LS_TRAD_ECO_REV_SHIFT       (8U)
13681 #define CAAM_CAAMVID_LS_TRAD_ECO_REV(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_ECO_REV_SHIFT)) & CAAM_CAAMVID_LS_TRAD_ECO_REV_MASK)
13682 
13683 #define CAAM_CAAMVID_LS_TRAD_INTG_OPT_MASK       (0xFF0000U)
13684 #define CAAM_CAAMVID_LS_TRAD_INTG_OPT_SHIFT      (16U)
13685 #define CAAM_CAAMVID_LS_TRAD_INTG_OPT(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_INTG_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_INTG_OPT_MASK)
13686 
13687 #define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_MASK    (0xFF000000U)
13688 #define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_SHIFT   (24U)
13689 #define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT(x)      (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_MASK)
13690 /*! @} */
13691 
13692 /*! @name HT_JD_ADDR - Holding Tank 0 Job Descriptor Address */
13693 /*! @{ */
13694 
13695 #define CAAM_HT_JD_ADDR_JD_ADDR_MASK             (0xFFFFFFFFFU)
13696 #define CAAM_HT_JD_ADDR_JD_ADDR_SHIFT            (0U)
13697 #define CAAM_HT_JD_ADDR_JD_ADDR(x)               (((uint64_t)(((uint64_t)(x)) << CAAM_HT_JD_ADDR_JD_ADDR_SHIFT)) & CAAM_HT_JD_ADDR_JD_ADDR_MASK)
13698 /*! @} */
13699 
13700 /* The count of CAAM_HT_JD_ADDR */
13701 #define CAAM_HT_JD_ADDR_COUNT                    (1U)
13702 
13703 /*! @name HT_SD_ADDR - Holding Tank 0 Shared Descriptor Address */
13704 /*! @{ */
13705 
13706 #define CAAM_HT_SD_ADDR_SD_ADDR_MASK             (0xFFFFFFFFFU)
13707 #define CAAM_HT_SD_ADDR_SD_ADDR_SHIFT            (0U)
13708 #define CAAM_HT_SD_ADDR_SD_ADDR(x)               (((uint64_t)(((uint64_t)(x)) << CAAM_HT_SD_ADDR_SD_ADDR_SHIFT)) & CAAM_HT_SD_ADDR_SD_ADDR_MASK)
13709 /*! @} */
13710 
13711 /* The count of CAAM_HT_SD_ADDR */
13712 #define CAAM_HT_SD_ADDR_COUNT                    (1U)
13713 
13714 /*! @name HT_JQ_CTRL_MS - Holding Tank 0 Job Queue Control, most-significant half */
13715 /*! @{ */
13716 
13717 #define CAAM_HT_JQ_CTRL_MS_ID_MASK               (0x7U)
13718 #define CAAM_HT_JQ_CTRL_MS_ID_SHIFT              (0U)
13719 #define CAAM_HT_JQ_CTRL_MS_ID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_ID_SHIFT)) & CAAM_HT_JQ_CTRL_MS_ID_MASK)
13720 
13721 #define CAAM_HT_JQ_CTRL_MS_SRC_MASK              (0x700U)
13722 #define CAAM_HT_JQ_CTRL_MS_SRC_SHIFT             (8U)
13723 /*! SRC
13724  *  0b000..Job Ring 0
13725  *  0b001..Job Ring 1
13726  *  0b010..Job Ring 2
13727  *  0b011..Job Ring 3
13728  *  0b100..RTIC
13729  *  0b101..Reserved
13730  *  0b110..Reserved
13731  *  0b111..Reserved
13732  */
13733 #define CAAM_HT_JQ_CTRL_MS_SRC(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SRC_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SRC_MASK)
13734 
13735 #define CAAM_HT_JQ_CTRL_MS_JDDS_MASK             (0x4000U)
13736 #define CAAM_HT_JQ_CTRL_MS_JDDS_SHIFT            (14U)
13737 /*! JDDS
13738  *  0b1..SEQ DID
13739  *  0b0..Non-SEQ DID
13740  */
13741 #define CAAM_HT_JQ_CTRL_MS_JDDS(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_JDDS_SHIFT)) & CAAM_HT_JQ_CTRL_MS_JDDS_MASK)
13742 
13743 #define CAAM_HT_JQ_CTRL_MS_AMTD_MASK             (0x8000U)
13744 #define CAAM_HT_JQ_CTRL_MS_AMTD_SHIFT            (15U)
13745 #define CAAM_HT_JQ_CTRL_MS_AMTD(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_AMTD_SHIFT)) & CAAM_HT_JQ_CTRL_MS_AMTD_MASK)
13746 
13747 #define CAAM_HT_JQ_CTRL_MS_SOB_MASK              (0x10000U)
13748 #define CAAM_HT_JQ_CTRL_MS_SOB_SHIFT             (16U)
13749 #define CAAM_HT_JQ_CTRL_MS_SOB(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SOB_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SOB_MASK)
13750 
13751 #define CAAM_HT_JQ_CTRL_MS_HT_ERROR_MASK         (0x60000U)
13752 #define CAAM_HT_JQ_CTRL_MS_HT_ERROR_SHIFT        (17U)
13753 /*! HT_ERROR
13754  *  0b00..No error
13755  *  0b01..Job Descriptor or Shared Descriptor length error
13756  *  0b10..AXI_error while reading a Job Ring Shared Descriptor or the remainder of a Job Ring Job Descriptor
13757  *  0b11..reserved
13758  */
13759 #define CAAM_HT_JQ_CTRL_MS_HT_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_HT_ERROR_SHIFT)) & CAAM_HT_JQ_CTRL_MS_HT_ERROR_MASK)
13760 
13761 #define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_MASK       (0x80000U)
13762 #define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_SHIFT      (19U)
13763 /*! DWORD_SWAP
13764  *  0b0..DWords are in the order most-significant word, least-significant word.
13765  *  0b1..DWords are in the order least-significant word, most-significant word.
13766  */
13767 #define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP(x)         (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_SHIFT)) & CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_MASK)
13768 
13769 #define CAAM_HT_JQ_CTRL_MS_SHR_FROM_MASK         (0x7C00000U)
13770 #define CAAM_HT_JQ_CTRL_MS_SHR_FROM_SHIFT        (22U)
13771 #define CAAM_HT_JQ_CTRL_MS_SHR_FROM(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SHR_FROM_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SHR_FROM_MASK)
13772 
13773 #define CAAM_HT_JQ_CTRL_MS_ILE_MASK              (0x8000000U)
13774 #define CAAM_HT_JQ_CTRL_MS_ILE_SHIFT             (27U)
13775 /*! ILE
13776  *  0b0..No byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
13777  *  0b1..Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
13778  */
13779 #define CAAM_HT_JQ_CTRL_MS_ILE(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_ILE_SHIFT)) & CAAM_HT_JQ_CTRL_MS_ILE_MASK)
13780 
13781 #define CAAM_HT_JQ_CTRL_MS_FOUR_MASK             (0x10000000U)
13782 #define CAAM_HT_JQ_CTRL_MS_FOUR_SHIFT            (28U)
13783 #define CAAM_HT_JQ_CTRL_MS_FOUR(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_FOUR_SHIFT)) & CAAM_HT_JQ_CTRL_MS_FOUR_MASK)
13784 
13785 #define CAAM_HT_JQ_CTRL_MS_WHL_MASK              (0x20000000U)
13786 #define CAAM_HT_JQ_CTRL_MS_WHL_SHIFT             (29U)
13787 #define CAAM_HT_JQ_CTRL_MS_WHL(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_WHL_SHIFT)) & CAAM_HT_JQ_CTRL_MS_WHL_MASK)
13788 /*! @} */
13789 
13790 /* The count of CAAM_HT_JQ_CTRL_MS */
13791 #define CAAM_HT_JQ_CTRL_MS_COUNT                 (1U)
13792 
13793 /*! @name HT_JQ_CTRL_LS - Holding Tank 0 Job Queue Control, least-significant half */
13794 /*! @{ */
13795 
13796 #define CAAM_HT_JQ_CTRL_LS_PRIM_DID_MASK         (0xFU)
13797 #define CAAM_HT_JQ_CTRL_LS_PRIM_DID_SHIFT        (0U)
13798 #define CAAM_HT_JQ_CTRL_LS_PRIM_DID(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_DID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_DID_MASK)
13799 
13800 #define CAAM_HT_JQ_CTRL_LS_PRIM_TZ_MASK          (0x10U)
13801 #define CAAM_HT_JQ_CTRL_LS_PRIM_TZ_SHIFT         (4U)
13802 /*! PRIM_TZ
13803  *  0b0..TrustZone NonSecureWorld
13804  *  0b1..TrustZone SecureWorld
13805  */
13806 #define CAAM_HT_JQ_CTRL_LS_PRIM_TZ(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_TZ_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_TZ_MASK)
13807 
13808 #define CAAM_HT_JQ_CTRL_LS_PRIM_ICID_MASK        (0xFFE0U)
13809 #define CAAM_HT_JQ_CTRL_LS_PRIM_ICID_SHIFT       (5U)
13810 #define CAAM_HT_JQ_CTRL_LS_PRIM_ICID(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_ICID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_ICID_MASK)
13811 
13812 #define CAAM_HT_JQ_CTRL_LS_OUT_DID_MASK          (0xF0000U)
13813 #define CAAM_HT_JQ_CTRL_LS_OUT_DID_SHIFT         (16U)
13814 #define CAAM_HT_JQ_CTRL_LS_OUT_DID(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_OUT_DID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_OUT_DID_MASK)
13815 
13816 #define CAAM_HT_JQ_CTRL_LS_OUT_ICID_MASK         (0xFFE00000U)
13817 #define CAAM_HT_JQ_CTRL_LS_OUT_ICID_SHIFT        (21U)
13818 #define CAAM_HT_JQ_CTRL_LS_OUT_ICID(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_OUT_ICID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_OUT_ICID_MASK)
13819 /*! @} */
13820 
13821 /* The count of CAAM_HT_JQ_CTRL_LS */
13822 #define CAAM_HT_JQ_CTRL_LS_COUNT                 (1U)
13823 
13824 /*! @name HT_STATUS - Holding Tank Status */
13825 /*! @{ */
13826 
13827 #define CAAM_HT_STATUS_PEND_0_MASK               (0x1U)
13828 #define CAAM_HT_STATUS_PEND_0_SHIFT              (0U)
13829 #define CAAM_HT_STATUS_PEND_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_PEND_0_SHIFT)) & CAAM_HT_STATUS_PEND_0_MASK)
13830 
13831 #define CAAM_HT_STATUS_IN_USE_MASK               (0x40000000U)
13832 #define CAAM_HT_STATUS_IN_USE_SHIFT              (30U)
13833 #define CAAM_HT_STATUS_IN_USE(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_IN_USE_SHIFT)) & CAAM_HT_STATUS_IN_USE_MASK)
13834 
13835 #define CAAM_HT_STATUS_BC_MASK                   (0x80000000U)
13836 #define CAAM_HT_STATUS_BC_SHIFT                  (31U)
13837 #define CAAM_HT_STATUS_BC(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_BC_SHIFT)) & CAAM_HT_STATUS_BC_MASK)
13838 /*! @} */
13839 
13840 /* The count of CAAM_HT_STATUS */
13841 #define CAAM_HT_STATUS_COUNT                     (1U)
13842 
13843 /*! @name JQ_DEBUG_SEL - Job Queue Debug Select Register */
13844 /*! @{ */
13845 
13846 #define CAAM_JQ_DEBUG_SEL_HT_SEL_MASK            (0x1U)
13847 #define CAAM_JQ_DEBUG_SEL_HT_SEL_SHIFT           (0U)
13848 #define CAAM_JQ_DEBUG_SEL_HT_SEL(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_JQ_DEBUG_SEL_HT_SEL_SHIFT)) & CAAM_JQ_DEBUG_SEL_HT_SEL_MASK)
13849 
13850 #define CAAM_JQ_DEBUG_SEL_JOB_ID_MASK            (0x70000U)
13851 #define CAAM_JQ_DEBUG_SEL_JOB_ID_SHIFT           (16U)
13852 #define CAAM_JQ_DEBUG_SEL_JOB_ID(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_JQ_DEBUG_SEL_JOB_ID_SHIFT)) & CAAM_JQ_DEBUG_SEL_JOB_ID_MASK)
13853 /*! @} */
13854 
13855 /*! @name JRJIDU_LS - Job Ring Job IDs in Use Register, least-significant half */
13856 /*! @{ */
13857 
13858 #define CAAM_JRJIDU_LS_JID00_MASK                (0x1U)
13859 #define CAAM_JRJIDU_LS_JID00_SHIFT               (0U)
13860 #define CAAM_JRJIDU_LS_JID00(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID00_SHIFT)) & CAAM_JRJIDU_LS_JID00_MASK)
13861 
13862 #define CAAM_JRJIDU_LS_JID01_MASK                (0x2U)
13863 #define CAAM_JRJIDU_LS_JID01_SHIFT               (1U)
13864 #define CAAM_JRJIDU_LS_JID01(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID01_SHIFT)) & CAAM_JRJIDU_LS_JID01_MASK)
13865 
13866 #define CAAM_JRJIDU_LS_JID02_MASK                (0x4U)
13867 #define CAAM_JRJIDU_LS_JID02_SHIFT               (2U)
13868 #define CAAM_JRJIDU_LS_JID02(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID02_SHIFT)) & CAAM_JRJIDU_LS_JID02_MASK)
13869 
13870 #define CAAM_JRJIDU_LS_JID03_MASK                (0x8U)
13871 #define CAAM_JRJIDU_LS_JID03_SHIFT               (3U)
13872 #define CAAM_JRJIDU_LS_JID03(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID03_SHIFT)) & CAAM_JRJIDU_LS_JID03_MASK)
13873 /*! @} */
13874 
13875 /*! @name JRJDJIFBC - Job Ring Job-Done Job ID FIFO BC */
13876 /*! @{ */
13877 
13878 #define CAAM_JRJDJIFBC_BC_MASK                   (0x80000000U)
13879 #define CAAM_JRJDJIFBC_BC_SHIFT                  (31U)
13880 #define CAAM_JRJDJIFBC_BC(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDJIFBC_BC_SHIFT)) & CAAM_JRJDJIFBC_BC_MASK)
13881 /*! @} */
13882 
13883 /*! @name JRJDJIF - Job Ring Job-Done Job ID FIFO */
13884 /*! @{ */
13885 
13886 #define CAAM_JRJDJIF_JOB_ID_ENTRY_MASK           (0x7U)
13887 #define CAAM_JRJDJIF_JOB_ID_ENTRY_SHIFT          (0U)
13888 #define CAAM_JRJDJIF_JOB_ID_ENTRY(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDJIF_JOB_ID_ENTRY_SHIFT)) & CAAM_JRJDJIF_JOB_ID_ENTRY_MASK)
13889 /*! @} */
13890 
13891 /*! @name JRJDS1 - Job Ring Job-Done Source 1 */
13892 /*! @{ */
13893 
13894 #define CAAM_JRJDS1_SRC_MASK                     (0x3U)
13895 #define CAAM_JRJDS1_SRC_SHIFT                    (0U)
13896 #define CAAM_JRJDS1_SRC(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDS1_SRC_SHIFT)) & CAAM_JRJDS1_SRC_MASK)
13897 
13898 #define CAAM_JRJDS1_VALID_MASK                   (0x80000000U)
13899 #define CAAM_JRJDS1_VALID_SHIFT                  (31U)
13900 #define CAAM_JRJDS1_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDS1_VALID_SHIFT)) & CAAM_JRJDS1_VALID_MASK)
13901 /*! @} */
13902 
13903 /*! @name JRJDDA - Job Ring Job-Done Descriptor Address 0 Register */
13904 /*! @{ */
13905 
13906 #define CAAM_JRJDDA_JD_ADDR_MASK                 (0xFFFFFFFFFU)
13907 #define CAAM_JRJDDA_JD_ADDR_SHIFT                (0U)
13908 #define CAAM_JRJDDA_JD_ADDR(x)                   (((uint64_t)(((uint64_t)(x)) << CAAM_JRJDDA_JD_ADDR_SHIFT)) & CAAM_JRJDDA_JD_ADDR_MASK)
13909 /*! @} */
13910 
13911 /* The count of CAAM_JRJDDA */
13912 #define CAAM_JRJDDA_COUNT                        (1U)
13913 
13914 /*! @name CRNR_MS - CHA Revision Number Register, most-significant half */
13915 /*! @{ */
13916 
13917 #define CAAM_CRNR_MS_CRCRN_MASK                  (0xFU)
13918 #define CAAM_CRNR_MS_CRCRN_SHIFT                 (0U)
13919 #define CAAM_CRNR_MS_CRCRN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_CRCRN_SHIFT)) & CAAM_CRNR_MS_CRCRN_MASK)
13920 
13921 #define CAAM_CRNR_MS_SNW9RN_MASK                 (0xF0U)
13922 #define CAAM_CRNR_MS_SNW9RN_SHIFT                (4U)
13923 #define CAAM_CRNR_MS_SNW9RN(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_SNW9RN_SHIFT)) & CAAM_CRNR_MS_SNW9RN_MASK)
13924 
13925 #define CAAM_CRNR_MS_ZERN_MASK                   (0xF00U)
13926 #define CAAM_CRNR_MS_ZERN_SHIFT                  (8U)
13927 #define CAAM_CRNR_MS_ZERN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_ZERN_SHIFT)) & CAAM_CRNR_MS_ZERN_MASK)
13928 
13929 #define CAAM_CRNR_MS_ZARN_MASK                   (0xF000U)
13930 #define CAAM_CRNR_MS_ZARN_SHIFT                  (12U)
13931 #define CAAM_CRNR_MS_ZARN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_ZARN_SHIFT)) & CAAM_CRNR_MS_ZARN_MASK)
13932 
13933 #define CAAM_CRNR_MS_DECORN_MASK                 (0xF000000U)
13934 #define CAAM_CRNR_MS_DECORN_SHIFT                (24U)
13935 #define CAAM_CRNR_MS_DECORN(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_DECORN_SHIFT)) & CAAM_CRNR_MS_DECORN_MASK)
13936 
13937 #define CAAM_CRNR_MS_JRRN_MASK                   (0xF0000000U)
13938 #define CAAM_CRNR_MS_JRRN_SHIFT                  (28U)
13939 #define CAAM_CRNR_MS_JRRN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_JRRN_SHIFT)) & CAAM_CRNR_MS_JRRN_MASK)
13940 /*! @} */
13941 
13942 /*! @name CRNR_LS - CHA Revision Number Register, least-significant half */
13943 /*! @{ */
13944 
13945 #define CAAM_CRNR_LS_AESRN_MASK                  (0xFU)
13946 #define CAAM_CRNR_LS_AESRN_SHIFT                 (0U)
13947 #define CAAM_CRNR_LS_AESRN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_AESRN_SHIFT)) & CAAM_CRNR_LS_AESRN_MASK)
13948 
13949 #define CAAM_CRNR_LS_DESRN_MASK                  (0xF0U)
13950 #define CAAM_CRNR_LS_DESRN_SHIFT                 (4U)
13951 #define CAAM_CRNR_LS_DESRN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_DESRN_SHIFT)) & CAAM_CRNR_LS_DESRN_MASK)
13952 
13953 #define CAAM_CRNR_LS_MDRN_MASK                   (0xF000U)
13954 #define CAAM_CRNR_LS_MDRN_SHIFT                  (12U)
13955 #define CAAM_CRNR_LS_MDRN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_MDRN_SHIFT)) & CAAM_CRNR_LS_MDRN_MASK)
13956 
13957 #define CAAM_CRNR_LS_RNGRN_MASK                  (0xF0000U)
13958 #define CAAM_CRNR_LS_RNGRN_SHIFT                 (16U)
13959 #define CAAM_CRNR_LS_RNGRN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_RNGRN_SHIFT)) & CAAM_CRNR_LS_RNGRN_MASK)
13960 
13961 #define CAAM_CRNR_LS_SNW8RN_MASK                 (0xF00000U)
13962 #define CAAM_CRNR_LS_SNW8RN_SHIFT                (20U)
13963 #define CAAM_CRNR_LS_SNW8RN(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_SNW8RN_SHIFT)) & CAAM_CRNR_LS_SNW8RN_MASK)
13964 
13965 #define CAAM_CRNR_LS_KASRN_MASK                  (0xF000000U)
13966 #define CAAM_CRNR_LS_KASRN_SHIFT                 (24U)
13967 #define CAAM_CRNR_LS_KASRN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_KASRN_SHIFT)) & CAAM_CRNR_LS_KASRN_MASK)
13968 
13969 #define CAAM_CRNR_LS_PKRN_MASK                   (0xF0000000U)
13970 #define CAAM_CRNR_LS_PKRN_SHIFT                  (28U)
13971 /*! PKRN
13972  *  0b0000..PKHA-SDv1
13973  *  0b0001..PKHA-SDv2
13974  *  0b0010..PKHA-SDv3
13975  *  0b0011..PKHA-SDv4
13976  */
13977 #define CAAM_CRNR_LS_PKRN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_PKRN_SHIFT)) & CAAM_CRNR_LS_PKRN_MASK)
13978 /*! @} */
13979 
13980 /*! @name CTPR_MS - Compile Time Parameters Register, most-significant half */
13981 /*! @{ */
13982 
13983 #define CAAM_CTPR_MS_VIRT_EN_INCL_MASK           (0x1U)
13984 #define CAAM_CTPR_MS_VIRT_EN_INCL_SHIFT          (0U)
13985 #define CAAM_CTPR_MS_VIRT_EN_INCL(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_VIRT_EN_INCL_SHIFT)) & CAAM_CTPR_MS_VIRT_EN_INCL_MASK)
13986 
13987 #define CAAM_CTPR_MS_VIRT_EN_POR_VALUE_MASK      (0x2U)
13988 #define CAAM_CTPR_MS_VIRT_EN_POR_VALUE_SHIFT     (1U)
13989 #define CAAM_CTPR_MS_VIRT_EN_POR_VALUE(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_VIRT_EN_POR_VALUE_SHIFT)) & CAAM_CTPR_MS_VIRT_EN_POR_VALUE_MASK)
13990 
13991 #define CAAM_CTPR_MS_REG_PG_SIZE_MASK            (0x10U)
13992 #define CAAM_CTPR_MS_REG_PG_SIZE_SHIFT           (4U)
13993 #define CAAM_CTPR_MS_REG_PG_SIZE(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_REG_PG_SIZE_SHIFT)) & CAAM_CTPR_MS_REG_PG_SIZE_MASK)
13994 
13995 #define CAAM_CTPR_MS_RNG_I_MASK                  (0x700U)
13996 #define CAAM_CTPR_MS_RNG_I_SHIFT                 (8U)
13997 #define CAAM_CTPR_MS_RNG_I(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_RNG_I_SHIFT)) & CAAM_CTPR_MS_RNG_I_MASK)
13998 
13999 #define CAAM_CTPR_MS_AI_INCL_MASK                (0x800U)
14000 #define CAAM_CTPR_MS_AI_INCL_SHIFT               (11U)
14001 #define CAAM_CTPR_MS_AI_INCL(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AI_INCL_SHIFT)) & CAAM_CTPR_MS_AI_INCL_MASK)
14002 
14003 #define CAAM_CTPR_MS_DPAA2_MASK                  (0x2000U)
14004 #define CAAM_CTPR_MS_DPAA2_SHIFT                 (13U)
14005 #define CAAM_CTPR_MS_DPAA2(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_DPAA2_SHIFT)) & CAAM_CTPR_MS_DPAA2_MASK)
14006 
14007 #define CAAM_CTPR_MS_IP_CLK_MASK                 (0x4000U)
14008 #define CAAM_CTPR_MS_IP_CLK_SHIFT                (14U)
14009 #define CAAM_CTPR_MS_IP_CLK(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_IP_CLK_SHIFT)) & CAAM_CTPR_MS_IP_CLK_MASK)
14010 
14011 #define CAAM_CTPR_MS_MCFG_BURST_MASK             (0x10000U)
14012 #define CAAM_CTPR_MS_MCFG_BURST_SHIFT            (16U)
14013 #define CAAM_CTPR_MS_MCFG_BURST(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_MCFG_BURST_SHIFT)) & CAAM_CTPR_MS_MCFG_BURST_MASK)
14014 
14015 #define CAAM_CTPR_MS_MCFG_PS_MASK                (0x20000U)
14016 #define CAAM_CTPR_MS_MCFG_PS_SHIFT               (17U)
14017 #define CAAM_CTPR_MS_MCFG_PS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_MCFG_PS_SHIFT)) & CAAM_CTPR_MS_MCFG_PS_MASK)
14018 
14019 #define CAAM_CTPR_MS_SG8_MASK                    (0x40000U)
14020 #define CAAM_CTPR_MS_SG8_SHIFT                   (18U)
14021 #define CAAM_CTPR_MS_SG8(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_SG8_SHIFT)) & CAAM_CTPR_MS_SG8_MASK)
14022 
14023 #define CAAM_CTPR_MS_PM_EVT_BUS_MASK             (0x80000U)
14024 #define CAAM_CTPR_MS_PM_EVT_BUS_SHIFT            (19U)
14025 #define CAAM_CTPR_MS_PM_EVT_BUS(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_PM_EVT_BUS_SHIFT)) & CAAM_CTPR_MS_PM_EVT_BUS_MASK)
14026 
14027 #define CAAM_CTPR_MS_DECO_WD_MASK                (0x100000U)
14028 #define CAAM_CTPR_MS_DECO_WD_SHIFT               (20U)
14029 #define CAAM_CTPR_MS_DECO_WD(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_DECO_WD_SHIFT)) & CAAM_CTPR_MS_DECO_WD_MASK)
14030 
14031 #define CAAM_CTPR_MS_PC_MASK                     (0x200000U)
14032 #define CAAM_CTPR_MS_PC_SHIFT                    (21U)
14033 #define CAAM_CTPR_MS_PC(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_PC_SHIFT)) & CAAM_CTPR_MS_PC_MASK)
14034 
14035 #define CAAM_CTPR_MS_C1C2_MASK                   (0x800000U)
14036 #define CAAM_CTPR_MS_C1C2_SHIFT                  (23U)
14037 #define CAAM_CTPR_MS_C1C2(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_C1C2_SHIFT)) & CAAM_CTPR_MS_C1C2_MASK)
14038 
14039 #define CAAM_CTPR_MS_ACC_CTL_MASK                (0x1000000U)
14040 #define CAAM_CTPR_MS_ACC_CTL_SHIFT               (24U)
14041 #define CAAM_CTPR_MS_ACC_CTL(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_ACC_CTL_SHIFT)) & CAAM_CTPR_MS_ACC_CTL_MASK)
14042 
14043 #define CAAM_CTPR_MS_QI_MASK                     (0x2000000U)
14044 #define CAAM_CTPR_MS_QI_SHIFT                    (25U)
14045 #define CAAM_CTPR_MS_QI(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_QI_SHIFT)) & CAAM_CTPR_MS_QI_MASK)
14046 
14047 #define CAAM_CTPR_MS_AXI_PRI_MASK                (0x4000000U)
14048 #define CAAM_CTPR_MS_AXI_PRI_SHIFT               (26U)
14049 #define CAAM_CTPR_MS_AXI_PRI(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_PRI_SHIFT)) & CAAM_CTPR_MS_AXI_PRI_MASK)
14050 
14051 #define CAAM_CTPR_MS_AXI_LIODN_MASK              (0x8000000U)
14052 #define CAAM_CTPR_MS_AXI_LIODN_SHIFT             (27U)
14053 #define CAAM_CTPR_MS_AXI_LIODN(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_LIODN_SHIFT)) & CAAM_CTPR_MS_AXI_LIODN_MASK)
14054 
14055 #define CAAM_CTPR_MS_AXI_PIPE_DEPTH_MASK         (0xF0000000U)
14056 #define CAAM_CTPR_MS_AXI_PIPE_DEPTH_SHIFT        (28U)
14057 #define CAAM_CTPR_MS_AXI_PIPE_DEPTH(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_PIPE_DEPTH_SHIFT)) & CAAM_CTPR_MS_AXI_PIPE_DEPTH_MASK)
14058 /*! @} */
14059 
14060 /*! @name CTPR_LS - Compile Time Parameters Register, least-significant half */
14061 /*! @{ */
14062 
14063 #define CAAM_CTPR_LS_KG_DS_MASK                  (0x1U)
14064 #define CAAM_CTPR_LS_KG_DS_SHIFT                 (0U)
14065 /*! KG_DS
14066  *  0b0..CAAM does not implement specialized support for Public Key Generation and Digital Signatures.
14067  *  0b1..CAAM implements specialized support for Public Key Generation and Digital Signatures.
14068  */
14069 #define CAAM_CTPR_LS_KG_DS(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_KG_DS_SHIFT)) & CAAM_CTPR_LS_KG_DS_MASK)
14070 
14071 #define CAAM_CTPR_LS_BLOB_MASK                   (0x2U)
14072 #define CAAM_CTPR_LS_BLOB_SHIFT                  (1U)
14073 /*! BLOB
14074  *  0b0..CAAM does not implement specialized support for encapsulating and decapsulating cryptographic blobs.
14075  *  0b1..CAAM implements specialized support for encapsulating and decapsulating cryptographic blobs.
14076  */
14077 #define CAAM_CTPR_LS_BLOB(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_BLOB_SHIFT)) & CAAM_CTPR_LS_BLOB_MASK)
14078 
14079 #define CAAM_CTPR_LS_WIFI_MASK                   (0x4U)
14080 #define CAAM_CTPR_LS_WIFI_SHIFT                  (2U)
14081 /*! WIFI
14082  *  0b0..CAAM does not implement specialized support for the WIFI protocol.
14083  *  0b1..CAAM implements specialized support for the WIFI protocol.
14084  */
14085 #define CAAM_CTPR_LS_WIFI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_WIFI_SHIFT)) & CAAM_CTPR_LS_WIFI_MASK)
14086 
14087 #define CAAM_CTPR_LS_WIMAX_MASK                  (0x8U)
14088 #define CAAM_CTPR_LS_WIMAX_SHIFT                 (3U)
14089 /*! WIMAX
14090  *  0b0..CAAM does not implement specialized support for the WIMAX protocol.
14091  *  0b1..CAAM implements specialized support for the WIMAX protocol.
14092  */
14093 #define CAAM_CTPR_LS_WIMAX(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_WIMAX_SHIFT)) & CAAM_CTPR_LS_WIMAX_MASK)
14094 
14095 #define CAAM_CTPR_LS_SRTP_MASK                   (0x10U)
14096 #define CAAM_CTPR_LS_SRTP_SHIFT                  (4U)
14097 /*! SRTP
14098  *  0b0..CAAM does not implement specialized support for the SRTP protocol.
14099  *  0b1..CAAM implements specialized support for the SRTP protocol.
14100  */
14101 #define CAAM_CTPR_LS_SRTP(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_SRTP_SHIFT)) & CAAM_CTPR_LS_SRTP_MASK)
14102 
14103 #define CAAM_CTPR_LS_IPSEC_MASK                  (0x20U)
14104 #define CAAM_CTPR_LS_IPSEC_SHIFT                 (5U)
14105 /*! IPSEC
14106  *  0b0..CAAM does not implement specialized support for the IPSEC protocol.
14107  *  0b1..CAAM implements specialized support for the IPSEC protocol.
14108  */
14109 #define CAAM_CTPR_LS_IPSEC(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_IPSEC_SHIFT)) & CAAM_CTPR_LS_IPSEC_MASK)
14110 
14111 #define CAAM_CTPR_LS_IKE_MASK                    (0x40U)
14112 #define CAAM_CTPR_LS_IKE_SHIFT                   (6U)
14113 /*! IKE
14114  *  0b0..CAAM does not implement specialized support for the IKE protocol.
14115  *  0b1..CAAM implements specialized support for the IKE protocol.
14116  */
14117 #define CAAM_CTPR_LS_IKE(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_IKE_SHIFT)) & CAAM_CTPR_LS_IKE_MASK)
14118 
14119 #define CAAM_CTPR_LS_SSL_TLS_MASK                (0x80U)
14120 #define CAAM_CTPR_LS_SSL_TLS_SHIFT               (7U)
14121 /*! SSL_TLS
14122  *  0b0..CAAM does not implement specialized support for the SSL and TLS protocols.
14123  *  0b1..CAAM implements specialized support for the SSL and TLS protocols.
14124  */
14125 #define CAAM_CTPR_LS_SSL_TLS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_SSL_TLS_SHIFT)) & CAAM_CTPR_LS_SSL_TLS_MASK)
14126 
14127 #define CAAM_CTPR_LS_TLS_PRF_MASK                (0x100U)
14128 #define CAAM_CTPR_LS_TLS_PRF_SHIFT               (8U)
14129 /*! TLS_PRF
14130  *  0b0..CAAM does not implement specialized support for the TLS protocol pseudo-random function.
14131  *  0b1..CAAM implements specialized support for the TLS protocol pseudo-random function.
14132  */
14133 #define CAAM_CTPR_LS_TLS_PRF(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_TLS_PRF_SHIFT)) & CAAM_CTPR_LS_TLS_PRF_MASK)
14134 
14135 #define CAAM_CTPR_LS_MACSEC_MASK                 (0x200U)
14136 #define CAAM_CTPR_LS_MACSEC_SHIFT                (9U)
14137 /*! MACSEC
14138  *  0b0..CAAM does not implement specialized support for the MACSEC protocol.
14139  *  0b1..CAAM implements specialized support for the MACSEC protocol.
14140  */
14141 #define CAAM_CTPR_LS_MACSEC(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_MACSEC_SHIFT)) & CAAM_CTPR_LS_MACSEC_MASK)
14142 
14143 #define CAAM_CTPR_LS_RSA_MASK                    (0x400U)
14144 #define CAAM_CTPR_LS_RSA_SHIFT                   (10U)
14145 /*! RSA
14146  *  0b0..CAAM does not implement specialized support for RSA encrypt and decrypt operations.
14147  *  0b1..CAAM implements specialized support for RSA encrypt and decrypt operations.
14148  */
14149 #define CAAM_CTPR_LS_RSA(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_RSA_SHIFT)) & CAAM_CTPR_LS_RSA_MASK)
14150 
14151 #define CAAM_CTPR_LS_P3G_LTE_MASK                (0x800U)
14152 #define CAAM_CTPR_LS_P3G_LTE_SHIFT               (11U)
14153 /*! P3G_LTE
14154  *  0b0..CAAM does not implement specialized support for 3G and LTE protocols.
14155  *  0b1..CAAM implements specialized support for 3G and LTE protocols.
14156  */
14157 #define CAAM_CTPR_LS_P3G_LTE(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_P3G_LTE_SHIFT)) & CAAM_CTPR_LS_P3G_LTE_MASK)
14158 
14159 #define CAAM_CTPR_LS_DBL_CRC_MASK                (0x1000U)
14160 #define CAAM_CTPR_LS_DBL_CRC_SHIFT               (12U)
14161 /*! DBL_CRC
14162  *  0b0..CAAM does not implement specialized support for Double CRC.
14163  *  0b1..CAAM implements specialized support for Double CRC.
14164  */
14165 #define CAAM_CTPR_LS_DBL_CRC(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_DBL_CRC_SHIFT)) & CAAM_CTPR_LS_DBL_CRC_MASK)
14166 
14167 #define CAAM_CTPR_LS_MAN_PROT_MASK               (0x2000U)
14168 #define CAAM_CTPR_LS_MAN_PROT_SHIFT              (13U)
14169 /*! MAN_PROT
14170  *  0b0..CAAM does not implement Manufacturing Protection functions.
14171  *  0b1..CAAM implements Manufacturing Protection functions.
14172  */
14173 #define CAAM_CTPR_LS_MAN_PROT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_MAN_PROT_SHIFT)) & CAAM_CTPR_LS_MAN_PROT_MASK)
14174 
14175 #define CAAM_CTPR_LS_DKP_MASK                    (0x4000U)
14176 #define CAAM_CTPR_LS_DKP_SHIFT                   (14U)
14177 /*! DKP
14178  *  0b0..CAAM does not implement the Derived Key Protocol.
14179  *  0b1..CAAM implements the Derived Key Protocol.
14180  */
14181 #define CAAM_CTPR_LS_DKP(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_DKP_SHIFT)) & CAAM_CTPR_LS_DKP_MASK)
14182 /*! @} */
14183 
14184 /*! @name SMSTA - Secure Memory Status Register */
14185 /*! @{ */
14186 
14187 #define CAAM_SMSTA_STATE_MASK                    (0xFU)
14188 #define CAAM_SMSTA_STATE_SHIFT                   (0U)
14189 /*! STATE
14190  *  0b0000..Reset State
14191  *  0b0001..Initialize State
14192  *  0b0010..Normal State
14193  *  0b0011..Fail State
14194  */
14195 #define CAAM_SMSTA_STATE(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_STATE_SHIFT)) & CAAM_SMSTA_STATE_MASK)
14196 
14197 #define CAAM_SMSTA_ACCERR_MASK                   (0xF0U)
14198 #define CAAM_SMSTA_ACCERR_SHIFT                  (4U)
14199 /*! ACCERR
14200  *  0b0000..No error occurred
14201  *  0b0001..A bus transaction attempted to access a page in Secure Memory, but the page was not allocated to any partition.
14202  *  0b0010..A bus transaction attempted to access a partition, but the transaction's TrustZone World, DID was not
14203  *          granted access to the partition in the partition's SMAG2/1JR registers.
14204  *  0b0011..A bus transaction attempted to read, but reads from this partition are not allowed.
14205  *  0b0100..A bus transaction attempted to write, but writes to this partition are not allowed.
14206  *  0b0110..A bus transaction attempted a non-key read, but the only reads permitted from this partition are key reads.
14207  *  0b1001..Secure Memory Blob import or export was attempted, but Secure Memory Blob access is not allowed for this partition.
14208  *  0b1010..A Descriptor attempted a Secure Memory Blob import or export, but not all of the pages referenced were from the same partition.
14209  *  0b1011..A memory access was directed to Secure Memory, but the specified address is not implemented in Secure
14210  *          Memory. The address was either outside the address range occupied by Secure Memory, or was within an
14211  *          unimplemented portion of the 4kbyte address block occupied by a 1Kbyte or 2Kbyte Secure Memory page.
14212  *  0b1100..A bus transaction was attempted, but the burst would have crossed a page boundary.
14213  *  0b1101..An attempt was made to access a page while it was still being initialized.
14214  */
14215 #define CAAM_SMSTA_ACCERR(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_ACCERR_SHIFT)) & CAAM_SMSTA_ACCERR_MASK)
14216 
14217 #define CAAM_SMSTA_DID_MASK                      (0xF00U)
14218 #define CAAM_SMSTA_DID_SHIFT                     (8U)
14219 #define CAAM_SMSTA_DID(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_DID_SHIFT)) & CAAM_SMSTA_DID_MASK)
14220 
14221 #define CAAM_SMSTA_NS_MASK                       (0x1000U)
14222 #define CAAM_SMSTA_NS_SHIFT                      (12U)
14223 #define CAAM_SMSTA_NS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_NS_SHIFT)) & CAAM_SMSTA_NS_MASK)
14224 
14225 #define CAAM_SMSTA_SMR_WP_MASK                   (0x8000U)
14226 #define CAAM_SMSTA_SMR_WP_SHIFT                  (15U)
14227 #define CAAM_SMSTA_SMR_WP(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_SMR_WP_SHIFT)) & CAAM_SMSTA_SMR_WP_MASK)
14228 
14229 #define CAAM_SMSTA_PAGE_MASK                     (0x7FF0000U)
14230 #define CAAM_SMSTA_PAGE_SHIFT                    (16U)
14231 #define CAAM_SMSTA_PAGE(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_PAGE_SHIFT)) & CAAM_SMSTA_PAGE_MASK)
14232 
14233 #define CAAM_SMSTA_PART_MASK                     (0xF0000000U)
14234 #define CAAM_SMSTA_PART_SHIFT                    (28U)
14235 #define CAAM_SMSTA_PART(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_PART_SHIFT)) & CAAM_SMSTA_PART_MASK)
14236 /*! @} */
14237 
14238 /*! @name SMPO - Secure Memory Partition Owners Register */
14239 /*! @{ */
14240 
14241 #define CAAM_SMPO_PO0_MASK                       (0x3U)
14242 #define CAAM_SMPO_PO0_SHIFT                      (0U)
14243 /*! PO0
14244  *  0b00..Available; Unowned. A Job Ring owner may claim partition 0 by writing to the appropriate SMAPJR register
14245  *        address alias. Note that the entire register will return all 0s if read by a entity that does not own
14246  *        the Job Ring associated with the SMPO address alias that was read.
14247  *  0b01..Partition 0 does not exist in this version
14248  *  0b10..Another entity owns partition 0. Partition 0 is unavailable to the reader. If the reader attempts to
14249  *        de-allocate partition 0 or write to the SMAPJR register or SMAGJR register for partition 0 or allocate a
14250  *        page to or de-allocate a page from partition 0 the command will be ignored. (Note that if a CSP partition is
14251  *        de-allocated, all entities (including the owner that de-allocated the partition) will see a 0b10 value
14252  *        for that partition until all its pages have been zeroized.)
14253  *  0b11..The entity that read the SMPO register owns partition 0. Ownership is claimed when the access
14254  *        permissions register (SMAPJR) of an available partition is first written.
14255  */
14256 #define CAAM_SMPO_PO0(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO0_SHIFT)) & CAAM_SMPO_PO0_MASK)
14257 
14258 #define CAAM_SMPO_PO1_MASK                       (0xCU)
14259 #define CAAM_SMPO_PO1_SHIFT                      (2U)
14260 #define CAAM_SMPO_PO1(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO1_SHIFT)) & CAAM_SMPO_PO1_MASK)
14261 
14262 #define CAAM_SMPO_PO2_MASK                       (0x30U)
14263 #define CAAM_SMPO_PO2_SHIFT                      (4U)
14264 #define CAAM_SMPO_PO2(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO2_SHIFT)) & CAAM_SMPO_PO2_MASK)
14265 
14266 #define CAAM_SMPO_PO3_MASK                       (0xC0U)
14267 #define CAAM_SMPO_PO3_SHIFT                      (6U)
14268 #define CAAM_SMPO_PO3(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO3_SHIFT)) & CAAM_SMPO_PO3_MASK)
14269 
14270 #define CAAM_SMPO_PO4_MASK                       (0x300U)
14271 #define CAAM_SMPO_PO4_SHIFT                      (8U)
14272 #define CAAM_SMPO_PO4(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO4_SHIFT)) & CAAM_SMPO_PO4_MASK)
14273 
14274 #define CAAM_SMPO_PO5_MASK                       (0xC00U)
14275 #define CAAM_SMPO_PO5_SHIFT                      (10U)
14276 #define CAAM_SMPO_PO5(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO5_SHIFT)) & CAAM_SMPO_PO5_MASK)
14277 
14278 #define CAAM_SMPO_PO6_MASK                       (0x3000U)
14279 #define CAAM_SMPO_PO6_SHIFT                      (12U)
14280 #define CAAM_SMPO_PO6(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO6_SHIFT)) & CAAM_SMPO_PO6_MASK)
14281 
14282 #define CAAM_SMPO_PO7_MASK                       (0xC000U)
14283 #define CAAM_SMPO_PO7_SHIFT                      (14U)
14284 #define CAAM_SMPO_PO7(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO7_SHIFT)) & CAAM_SMPO_PO7_MASK)
14285 
14286 #define CAAM_SMPO_PO8_MASK                       (0x30000U)
14287 #define CAAM_SMPO_PO8_SHIFT                      (16U)
14288 #define CAAM_SMPO_PO8(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO8_SHIFT)) & CAAM_SMPO_PO8_MASK)
14289 
14290 #define CAAM_SMPO_PO9_MASK                       (0xC0000U)
14291 #define CAAM_SMPO_PO9_SHIFT                      (18U)
14292 #define CAAM_SMPO_PO9(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO9_SHIFT)) & CAAM_SMPO_PO9_MASK)
14293 
14294 #define CAAM_SMPO_PO10_MASK                      (0x300000U)
14295 #define CAAM_SMPO_PO10_SHIFT                     (20U)
14296 #define CAAM_SMPO_PO10(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO10_SHIFT)) & CAAM_SMPO_PO10_MASK)
14297 
14298 #define CAAM_SMPO_PO11_MASK                      (0xC00000U)
14299 #define CAAM_SMPO_PO11_SHIFT                     (22U)
14300 #define CAAM_SMPO_PO11(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO11_SHIFT)) & CAAM_SMPO_PO11_MASK)
14301 
14302 #define CAAM_SMPO_PO12_MASK                      (0x3000000U)
14303 #define CAAM_SMPO_PO12_SHIFT                     (24U)
14304 #define CAAM_SMPO_PO12(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO12_SHIFT)) & CAAM_SMPO_PO12_MASK)
14305 
14306 #define CAAM_SMPO_PO13_MASK                      (0xC000000U)
14307 #define CAAM_SMPO_PO13_SHIFT                     (26U)
14308 #define CAAM_SMPO_PO13(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO13_SHIFT)) & CAAM_SMPO_PO13_MASK)
14309 
14310 #define CAAM_SMPO_PO14_MASK                      (0x30000000U)
14311 #define CAAM_SMPO_PO14_SHIFT                     (28U)
14312 #define CAAM_SMPO_PO14(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO14_SHIFT)) & CAAM_SMPO_PO14_MASK)
14313 
14314 #define CAAM_SMPO_PO15_MASK                      (0xC0000000U)
14315 #define CAAM_SMPO_PO15_SHIFT                     (30U)
14316 #define CAAM_SMPO_PO15(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO15_SHIFT)) & CAAM_SMPO_PO15_MASK)
14317 /*! @} */
14318 
14319 /*! @name FAR - Fault Address Register */
14320 /*! @{ */
14321 
14322 #define CAAM_FAR_FAR_MASK                        (0xFFFFFFFFFU)
14323 #define CAAM_FAR_FAR_SHIFT                       (0U)
14324 #define CAAM_FAR_FAR(x)                          (((uint64_t)(((uint64_t)(x)) << CAAM_FAR_FAR_SHIFT)) & CAAM_FAR_FAR_MASK)
14325 /*! @} */
14326 
14327 /*! @name FADID - Fault Address DID Register */
14328 /*! @{ */
14329 
14330 #define CAAM_FADID_FDID_MASK                     (0xFU)
14331 #define CAAM_FADID_FDID_SHIFT                    (0U)
14332 #define CAAM_FADID_FDID(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FDID_SHIFT)) & CAAM_FADID_FDID_MASK)
14333 
14334 #define CAAM_FADID_FNS_MASK                      (0x10U)
14335 #define CAAM_FADID_FNS_SHIFT                     (4U)
14336 #define CAAM_FADID_FNS(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FNS_SHIFT)) & CAAM_FADID_FNS_MASK)
14337 
14338 #define CAAM_FADID_FICID_MASK                    (0xFFE0U)
14339 #define CAAM_FADID_FICID_SHIFT                   (5U)
14340 #define CAAM_FADID_FICID(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FICID_SHIFT)) & CAAM_FADID_FICID_MASK)
14341 /*! @} */
14342 
14343 /*! @name FADR - Fault Address Detail Register */
14344 /*! @{ */
14345 
14346 #define CAAM_FADR_FSZ_MASK                       (0x7FU)
14347 #define CAAM_FADR_FSZ_SHIFT                      (0U)
14348 #define CAAM_FADR_FSZ(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FSZ_SHIFT)) & CAAM_FADR_FSZ_MASK)
14349 
14350 #define CAAM_FADR_TYP_MASK                       (0x80U)
14351 #define CAAM_FADR_TYP_SHIFT                      (7U)
14352 /*! TYP
14353  *  0b0..Read.
14354  *  0b1..Write.
14355  */
14356 #define CAAM_FADR_TYP(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_TYP_SHIFT)) & CAAM_FADR_TYP_MASK)
14357 
14358 #define CAAM_FADR_BLKID_MASK                     (0xF00U)
14359 #define CAAM_FADR_BLKID_SHIFT                    (8U)
14360 /*! BLKID
14361  *  0b0100..job queue controller Burst Buffer
14362  *  0b0101..One of the Job Rings (see JSRC field)
14363  *  0b1000..DECO0
14364  */
14365 #define CAAM_FADR_BLKID(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_BLKID_SHIFT)) & CAAM_FADR_BLKID_MASK)
14366 
14367 #define CAAM_FADR_JSRC_MASK                      (0x7000U)
14368 #define CAAM_FADR_JSRC_SHIFT                     (12U)
14369 /*! JSRC
14370  *  0b000..Job Ring 0
14371  *  0b001..Job Ring 1
14372  *  0b010..Job Ring 2
14373  *  0b011..Job Ring 3
14374  *  0b100..RTIC
14375  *  0b101..reserved
14376  *  0b110..reserved
14377  *  0b111..reserved
14378  */
14379 #define CAAM_FADR_JSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_JSRC_SHIFT)) & CAAM_FADR_JSRC_MASK)
14380 
14381 #define CAAM_FADR_DTYP_MASK                      (0x8000U)
14382 #define CAAM_FADR_DTYP_SHIFT                     (15U)
14383 /*! DTYP
14384  *  0b0..message data
14385  *  0b1..control data
14386  */
14387 #define CAAM_FADR_DTYP(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_DTYP_SHIFT)) & CAAM_FADR_DTYP_MASK)
14388 
14389 #define CAAM_FADR_FSZ_EXT_MASK                   (0x70000U)
14390 #define CAAM_FADR_FSZ_EXT_SHIFT                  (16U)
14391 #define CAAM_FADR_FSZ_EXT(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FSZ_EXT_SHIFT)) & CAAM_FADR_FSZ_EXT_MASK)
14392 
14393 #define CAAM_FADR_FKMOD_MASK                     (0x1000000U)
14394 #define CAAM_FADR_FKMOD_SHIFT                    (24U)
14395 /*! FKMOD
14396  *  0b0..CAAM DMA was not attempting to read the key modifier from Secure Memory at the time that the DMA error occurred.
14397  *  0b1..CAAM DMA was attempting to read the key modifier from Secure Memory at the time that the DMA error occurred.
14398  */
14399 #define CAAM_FADR_FKMOD(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FKMOD_SHIFT)) & CAAM_FADR_FKMOD_MASK)
14400 
14401 #define CAAM_FADR_FKEY_MASK                      (0x2000000U)
14402 #define CAAM_FADR_FKEY_SHIFT                     (25U)
14403 /*! FKEY
14404  *  0b0..CAAM DMA was not attempting to perform a key read from Secure Memory at the time of the DMA error.
14405  *  0b1..CAAM DMA was attempting to perform a key read from Secure Memory at the time of the DMA error.
14406  */
14407 #define CAAM_FADR_FKEY(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FKEY_SHIFT)) & CAAM_FADR_FKEY_MASK)
14408 
14409 #define CAAM_FADR_FTDSC_MASK                     (0x4000000U)
14410 #define CAAM_FADR_FTDSC_SHIFT                    (26U)
14411 /*! FTDSC
14412  *  0b0..CAAM DMA was not executing a Trusted Descriptor at the time of the DMA error.
14413  *  0b1..CAAM DMA was executing a Trusted Descriptor at the time of the DMA error.
14414  */
14415 #define CAAM_FADR_FTDSC(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FTDSC_SHIFT)) & CAAM_FADR_FTDSC_MASK)
14416 
14417 #define CAAM_FADR_FBNDG_MASK                     (0x8000000U)
14418 #define CAAM_FADR_FBNDG_SHIFT                    (27U)
14419 /*! FBNDG
14420  *  0b0..CAAM DMA was not reading access permissions from a Secure Memory partition at the time of the DMA error.
14421  *  0b1..CAAM DMA was reading access permissions from a Secure Memory partition at the time of the DMA error.
14422  */
14423 #define CAAM_FADR_FBNDG(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FBNDG_SHIFT)) & CAAM_FADR_FBNDG_MASK)
14424 
14425 #define CAAM_FADR_FNS_MASK                       (0x10000000U)
14426 #define CAAM_FADR_FNS_SHIFT                      (28U)
14427 /*! FNS
14428  *  0b0..CAAM DMA was asserting ns=0 at the time of the DMA error.
14429  *  0b1..CAAM DMA was asserting ns=1 at the time of the DMA error.
14430  */
14431 #define CAAM_FADR_FNS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FNS_SHIFT)) & CAAM_FADR_FNS_MASK)
14432 
14433 #define CAAM_FADR_FERR_MASK                      (0xC0000000U)
14434 #define CAAM_FADR_FERR_SHIFT                     (30U)
14435 /*! FERR
14436  *  0b00..OKAY - Normal Access
14437  *  0b01..Reserved
14438  *  0b10..SLVERR - Slave Error
14439  *  0b11..DECERR - Decode Error
14440  */
14441 #define CAAM_FADR_FERR(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FERR_SHIFT)) & CAAM_FADR_FERR_MASK)
14442 /*! @} */
14443 
14444 /*! @name CSTA - CAAM Status Register */
14445 /*! @{ */
14446 
14447 #define CAAM_CSTA_BSY_MASK                       (0x1U)
14448 #define CAAM_CSTA_BSY_SHIFT                      (0U)
14449 #define CAAM_CSTA_BSY(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_BSY_SHIFT)) & CAAM_CSTA_BSY_MASK)
14450 
14451 #define CAAM_CSTA_IDLE_MASK                      (0x2U)
14452 #define CAAM_CSTA_IDLE_SHIFT                     (1U)
14453 #define CAAM_CSTA_IDLE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_IDLE_SHIFT)) & CAAM_CSTA_IDLE_MASK)
14454 
14455 #define CAAM_CSTA_TRNG_IDLE_MASK                 (0x4U)
14456 #define CAAM_CSTA_TRNG_IDLE_SHIFT                (2U)
14457 #define CAAM_CSTA_TRNG_IDLE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_TRNG_IDLE_SHIFT)) & CAAM_CSTA_TRNG_IDLE_MASK)
14458 
14459 #define CAAM_CSTA_MOO_MASK                       (0x300U)
14460 #define CAAM_CSTA_MOO_SHIFT                      (8U)
14461 /*! MOO
14462  *  0b00..Non-Secure
14463  *  0b01..Secure
14464  *  0b10..Trusted
14465  *  0b11..Fail
14466  */
14467 #define CAAM_CSTA_MOO(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_MOO_SHIFT)) & CAAM_CSTA_MOO_MASK)
14468 
14469 #define CAAM_CSTA_PLEND_MASK                     (0x400U)
14470 #define CAAM_CSTA_PLEND_SHIFT                    (10U)
14471 /*! PLEND
14472  *  0b0..Platform default is Little Endian
14473  *  0b1..Platform default is Big Endian
14474  */
14475 #define CAAM_CSTA_PLEND(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_PLEND_SHIFT)) & CAAM_CSTA_PLEND_MASK)
14476 /*! @} */
14477 
14478 /*! @name SMVID_MS - Secure Memory Version ID Register, most-significant half */
14479 /*! @{ */
14480 
14481 #define CAAM_SMVID_MS_NPAG_MASK                  (0x3FFU)
14482 #define CAAM_SMVID_MS_NPAG_SHIFT                 (0U)
14483 #define CAAM_SMVID_MS_NPAG(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_NPAG_SHIFT)) & CAAM_SMVID_MS_NPAG_MASK)
14484 
14485 #define CAAM_SMVID_MS_NPRT_MASK                  (0xF000U)
14486 #define CAAM_SMVID_MS_NPRT_SHIFT                 (12U)
14487 #define CAAM_SMVID_MS_NPRT(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_NPRT_SHIFT)) & CAAM_SMVID_MS_NPRT_MASK)
14488 
14489 #define CAAM_SMVID_MS_MAX_NPAG_MASK              (0x3FF0000U)
14490 #define CAAM_SMVID_MS_MAX_NPAG_SHIFT             (16U)
14491 #define CAAM_SMVID_MS_MAX_NPAG(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_MAX_NPAG_SHIFT)) & CAAM_SMVID_MS_MAX_NPAG_MASK)
14492 /*! @} */
14493 
14494 /*! @name SMVID_LS - Secure Memory Version ID Register, least-significant half */
14495 /*! @{ */
14496 
14497 #define CAAM_SMVID_LS_SMNV_MASK                  (0xFFU)
14498 #define CAAM_SMVID_LS_SMNV_SHIFT                 (0U)
14499 #define CAAM_SMVID_LS_SMNV(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_SMNV_SHIFT)) & CAAM_SMVID_LS_SMNV_MASK)
14500 
14501 #define CAAM_SMVID_LS_SMJV_MASK                  (0xFF00U)
14502 #define CAAM_SMVID_LS_SMJV_SHIFT                 (8U)
14503 #define CAAM_SMVID_LS_SMJV(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_SMJV_SHIFT)) & CAAM_SMVID_LS_SMJV_MASK)
14504 
14505 #define CAAM_SMVID_LS_PSIZ_MASK                  (0x70000U)
14506 #define CAAM_SMVID_LS_PSIZ_SHIFT                 (16U)
14507 #define CAAM_SMVID_LS_PSIZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_PSIZ_SHIFT)) & CAAM_SMVID_LS_PSIZ_MASK)
14508 /*! @} */
14509 
14510 /*! @name RVID - RTIC Version ID Register */
14511 /*! @{ */
14512 
14513 #define CAAM_RVID_RMNV_MASK                      (0xFFU)
14514 #define CAAM_RVID_RMNV_SHIFT                     (0U)
14515 #define CAAM_RVID_RMNV(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_RMNV_SHIFT)) & CAAM_RVID_RMNV_MASK)
14516 
14517 #define CAAM_RVID_RMJV_MASK                      (0xFF00U)
14518 #define CAAM_RVID_RMJV_SHIFT                     (8U)
14519 #define CAAM_RVID_RMJV(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_RMJV_SHIFT)) & CAAM_RVID_RMJV_MASK)
14520 
14521 #define CAAM_RVID_SHA_256_MASK                   (0x20000U)
14522 #define CAAM_RVID_SHA_256_SHIFT                  (17U)
14523 /*! SHA_256
14524  *  0b0..RTIC cannot use the SHA-256 hashing algorithm.
14525  *  0b1..RTIC can use the SHA-256 hashing algorithm.
14526  */
14527 #define CAAM_RVID_SHA_256(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_SHA_256_SHIFT)) & CAAM_RVID_SHA_256_MASK)
14528 
14529 #define CAAM_RVID_SHA_512_MASK                   (0x80000U)
14530 #define CAAM_RVID_SHA_512_SHIFT                  (19U)
14531 /*! SHA_512
14532  *  0b0..RTIC cannot use the SHA-512 hashing algorithm.
14533  *  0b1..RTIC can use the SHA-512 hashing algorithm.
14534  */
14535 #define CAAM_RVID_SHA_512(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_SHA_512_SHIFT)) & CAAM_RVID_SHA_512_MASK)
14536 
14537 #define CAAM_RVID_MA_MASK                        (0x1000000U)
14538 #define CAAM_RVID_MA_SHIFT                       (24U)
14539 #define CAAM_RVID_MA(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MA_SHIFT)) & CAAM_RVID_MA_MASK)
14540 
14541 #define CAAM_RVID_MB_MASK                        (0x2000000U)
14542 #define CAAM_RVID_MB_SHIFT                       (25U)
14543 #define CAAM_RVID_MB(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MB_SHIFT)) & CAAM_RVID_MB_MASK)
14544 
14545 #define CAAM_RVID_MC_MASK                        (0x4000000U)
14546 #define CAAM_RVID_MC_SHIFT                       (26U)
14547 #define CAAM_RVID_MC(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MC_SHIFT)) & CAAM_RVID_MC_MASK)
14548 
14549 #define CAAM_RVID_MD_MASK                        (0x8000000U)
14550 #define CAAM_RVID_MD_SHIFT                       (27U)
14551 #define CAAM_RVID_MD(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MD_SHIFT)) & CAAM_RVID_MD_MASK)
14552 /*! @} */
14553 
14554 /*! @name CCBVID - CHA Cluster Block Version ID Register */
14555 /*! @{ */
14556 
14557 #define CAAM_CCBVID_AMNV_MASK                    (0xFFU)
14558 #define CAAM_CCBVID_AMNV_SHIFT                   (0U)
14559 #define CAAM_CCBVID_AMNV(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_AMNV_SHIFT)) & CAAM_CCBVID_AMNV_MASK)
14560 
14561 #define CAAM_CCBVID_AMJV_MASK                    (0xFF00U)
14562 #define CAAM_CCBVID_AMJV_SHIFT                   (8U)
14563 #define CAAM_CCBVID_AMJV(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_AMJV_SHIFT)) & CAAM_CCBVID_AMJV_MASK)
14564 
14565 #define CAAM_CCBVID_CAAM_ERA_MASK                (0xFF000000U)
14566 #define CAAM_CCBVID_CAAM_ERA_SHIFT               (24U)
14567 #define CAAM_CCBVID_CAAM_ERA(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_CAAM_ERA_SHIFT)) & CAAM_CCBVID_CAAM_ERA_MASK)
14568 /*! @} */
14569 
14570 /*! @name CHAVID_MS - CHA Version ID Register, most-significant half */
14571 /*! @{ */
14572 
14573 #define CAAM_CHAVID_MS_CRCVID_MASK               (0xFU)
14574 #define CAAM_CHAVID_MS_CRCVID_SHIFT              (0U)
14575 #define CAAM_CHAVID_MS_CRCVID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_CRCVID_SHIFT)) & CAAM_CHAVID_MS_CRCVID_MASK)
14576 
14577 #define CAAM_CHAVID_MS_SNW9VID_MASK              (0xF0U)
14578 #define CAAM_CHAVID_MS_SNW9VID_SHIFT             (4U)
14579 #define CAAM_CHAVID_MS_SNW9VID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_SNW9VID_SHIFT)) & CAAM_CHAVID_MS_SNW9VID_MASK)
14580 
14581 #define CAAM_CHAVID_MS_ZEVID_MASK                (0xF00U)
14582 #define CAAM_CHAVID_MS_ZEVID_SHIFT               (8U)
14583 #define CAAM_CHAVID_MS_ZEVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_ZEVID_SHIFT)) & CAAM_CHAVID_MS_ZEVID_MASK)
14584 
14585 #define CAAM_CHAVID_MS_ZAVID_MASK                (0xF000U)
14586 #define CAAM_CHAVID_MS_ZAVID_SHIFT               (12U)
14587 #define CAAM_CHAVID_MS_ZAVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_ZAVID_SHIFT)) & CAAM_CHAVID_MS_ZAVID_MASK)
14588 
14589 #define CAAM_CHAVID_MS_DECOVID_MASK              (0xF000000U)
14590 #define CAAM_CHAVID_MS_DECOVID_SHIFT             (24U)
14591 #define CAAM_CHAVID_MS_DECOVID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_DECOVID_SHIFT)) & CAAM_CHAVID_MS_DECOVID_MASK)
14592 
14593 #define CAAM_CHAVID_MS_JRVID_MASK                (0xF0000000U)
14594 #define CAAM_CHAVID_MS_JRVID_SHIFT               (28U)
14595 #define CAAM_CHAVID_MS_JRVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_JRVID_SHIFT)) & CAAM_CHAVID_MS_JRVID_MASK)
14596 /*! @} */
14597 
14598 /*! @name CHAVID_LS - CHA Version ID Register, least-significant half */
14599 /*! @{ */
14600 
14601 #define CAAM_CHAVID_LS_AESVID_MASK               (0xFU)
14602 #define CAAM_CHAVID_LS_AESVID_SHIFT              (0U)
14603 /*! AESVID
14604  *  0b0100..High-performance AESA, implementing ECB, CBC, CBC-CS2, CFB128, OFB, CTR, CCM, CMAC, XCBC-MAC, CBCXCBC, CTRXCBC, XTS, and GCM modes
14605  *  0b0011..Low-power AESA, implementing ECB, CBC, CBC-CS2, CFB128, OFB, CTR, CCM, CMAC, XCBC-MAC, and GCM modes
14606  */
14607 #define CAAM_CHAVID_LS_AESVID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_AESVID_SHIFT)) & CAAM_CHAVID_LS_AESVID_MASK)
14608 
14609 #define CAAM_CHAVID_LS_DESVID_MASK               (0xF0U)
14610 #define CAAM_CHAVID_LS_DESVID_SHIFT              (4U)
14611 #define CAAM_CHAVID_LS_DESVID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_DESVID_SHIFT)) & CAAM_CHAVID_LS_DESVID_MASK)
14612 
14613 #define CAAM_CHAVID_LS_MDVID_MASK                (0xF000U)
14614 #define CAAM_CHAVID_LS_MDVID_SHIFT               (12U)
14615 /*! MDVID
14616  *  0b0000..Low-power MDHA, with SHA-1, SHA-256, SHA 224, MD5 and HMAC
14617  *  0b0001..Low-power MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5 and HMAC
14618  *  0b0010..Medium-performance MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5, HMAC & SMAC
14619  *  0b0011..High-performance MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5, HMAC & SMAC
14620  */
14621 #define CAAM_CHAVID_LS_MDVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_MDVID_SHIFT)) & CAAM_CHAVID_LS_MDVID_MASK)
14622 
14623 #define CAAM_CHAVID_LS_RNGVID_MASK               (0xF0000U)
14624 #define CAAM_CHAVID_LS_RNGVID_SHIFT              (16U)
14625 /*! RNGVID
14626  *  0b0010..RNGB
14627  *  0b0100..RNG4
14628  */
14629 #define CAAM_CHAVID_LS_RNGVID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_RNGVID_SHIFT)) & CAAM_CHAVID_LS_RNGVID_MASK)
14630 
14631 #define CAAM_CHAVID_LS_SNW8VID_MASK              (0xF00000U)
14632 #define CAAM_CHAVID_LS_SNW8VID_SHIFT             (20U)
14633 #define CAAM_CHAVID_LS_SNW8VID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
14634 
14635 #define CAAM_CHAVID_LS_KASVID_MASK               (0xF000000U)
14636 #define CAAM_CHAVID_LS_KASVID_SHIFT              (24U)
14637 #define CAAM_CHAVID_LS_KASVID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_KASVID_SHIFT)) & CAAM_CHAVID_LS_KASVID_MASK)
14638 
14639 #define CAAM_CHAVID_LS_PKVID_MASK                (0xF0000000U)
14640 #define CAAM_CHAVID_LS_PKVID_SHIFT               (28U)
14641 /*! PKVID
14642  *  0b0000..PKHA-XT (32-bit); minimum modulus five bytes
14643  *  0b0001..PKHA-SD (32-bit)
14644  *  0b0010..PKHA-SD (64-bit)
14645  *  0b0011..PKHA-SD (128-bit)
14646  */
14647 #define CAAM_CHAVID_LS_PKVID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_PKVID_SHIFT)) & CAAM_CHAVID_LS_PKVID_MASK)
14648 /*! @} */
14649 
14650 /*! @name CHANUM_MS - CHA Number Register, most-significant half */
14651 /*! @{ */
14652 
14653 #define CAAM_CHANUM_MS_CRCNUM_MASK               (0xFU)
14654 #define CAAM_CHANUM_MS_CRCNUM_SHIFT              (0U)
14655 #define CAAM_CHANUM_MS_CRCNUM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_CRCNUM_SHIFT)) & CAAM_CHANUM_MS_CRCNUM_MASK)
14656 
14657 #define CAAM_CHANUM_MS_SNW9NUM_MASK              (0xF0U)
14658 #define CAAM_CHANUM_MS_SNW9NUM_SHIFT             (4U)
14659 #define CAAM_CHANUM_MS_SNW9NUM(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_SNW9NUM_SHIFT)) & CAAM_CHANUM_MS_SNW9NUM_MASK)
14660 
14661 #define CAAM_CHANUM_MS_ZENUM_MASK                (0xF00U)
14662 #define CAAM_CHANUM_MS_ZENUM_SHIFT               (8U)
14663 #define CAAM_CHANUM_MS_ZENUM(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_ZENUM_SHIFT)) & CAAM_CHANUM_MS_ZENUM_MASK)
14664 
14665 #define CAAM_CHANUM_MS_ZANUM_MASK                (0xF000U)
14666 #define CAAM_CHANUM_MS_ZANUM_SHIFT               (12U)
14667 #define CAAM_CHANUM_MS_ZANUM(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_ZANUM_SHIFT)) & CAAM_CHANUM_MS_ZANUM_MASK)
14668 
14669 #define CAAM_CHANUM_MS_DECONUM_MASK              (0xF000000U)
14670 #define CAAM_CHANUM_MS_DECONUM_SHIFT             (24U)
14671 #define CAAM_CHANUM_MS_DECONUM(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_DECONUM_SHIFT)) & CAAM_CHANUM_MS_DECONUM_MASK)
14672 
14673 #define CAAM_CHANUM_MS_JRNUM_MASK                (0xF0000000U)
14674 #define CAAM_CHANUM_MS_JRNUM_SHIFT               (28U)
14675 #define CAAM_CHANUM_MS_JRNUM(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_JRNUM_SHIFT)) & CAAM_CHANUM_MS_JRNUM_MASK)
14676 /*! @} */
14677 
14678 /*! @name CHANUM_LS - CHA Number Register, least-significant half */
14679 /*! @{ */
14680 
14681 #define CAAM_CHANUM_LS_AESNUM_MASK               (0xFU)
14682 #define CAAM_CHANUM_LS_AESNUM_SHIFT              (0U)
14683 #define CAAM_CHANUM_LS_AESNUM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_AESNUM_SHIFT)) & CAAM_CHANUM_LS_AESNUM_MASK)
14684 
14685 #define CAAM_CHANUM_LS_DESNUM_MASK               (0xF0U)
14686 #define CAAM_CHANUM_LS_DESNUM_SHIFT              (4U)
14687 #define CAAM_CHANUM_LS_DESNUM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_DESNUM_SHIFT)) & CAAM_CHANUM_LS_DESNUM_MASK)
14688 
14689 #define CAAM_CHANUM_LS_ARC4NUM_MASK              (0xF00U)
14690 #define CAAM_CHANUM_LS_ARC4NUM_SHIFT             (8U)
14691 #define CAAM_CHANUM_LS_ARC4NUM(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_ARC4NUM_SHIFT)) & CAAM_CHANUM_LS_ARC4NUM_MASK)
14692 
14693 #define CAAM_CHANUM_LS_MDNUM_MASK                (0xF000U)
14694 #define CAAM_CHANUM_LS_MDNUM_SHIFT               (12U)
14695 #define CAAM_CHANUM_LS_MDNUM(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_MDNUM_SHIFT)) & CAAM_CHANUM_LS_MDNUM_MASK)
14696 
14697 #define CAAM_CHANUM_LS_RNGNUM_MASK               (0xF0000U)
14698 #define CAAM_CHANUM_LS_RNGNUM_SHIFT              (16U)
14699 #define CAAM_CHANUM_LS_RNGNUM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_RNGNUM_SHIFT)) & CAAM_CHANUM_LS_RNGNUM_MASK)
14700 
14701 #define CAAM_CHANUM_LS_SNW8NUM_MASK              (0xF00000U)
14702 #define CAAM_CHANUM_LS_SNW8NUM_SHIFT             (20U)
14703 #define CAAM_CHANUM_LS_SNW8NUM(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_SNW8NUM_SHIFT)) & CAAM_CHANUM_LS_SNW8NUM_MASK)
14704 
14705 #define CAAM_CHANUM_LS_KASNUM_MASK               (0xF000000U)
14706 #define CAAM_CHANUM_LS_KASNUM_SHIFT              (24U)
14707 #define CAAM_CHANUM_LS_KASNUM(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_KASNUM_SHIFT)) & CAAM_CHANUM_LS_KASNUM_MASK)
14708 
14709 #define CAAM_CHANUM_LS_PKNUM_MASK                (0xF0000000U)
14710 #define CAAM_CHANUM_LS_PKNUM_SHIFT               (28U)
14711 #define CAAM_CHANUM_LS_PKNUM(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_PKNUM_SHIFT)) & CAAM_CHANUM_LS_PKNUM_MASK)
14712 /*! @} */
14713 
14714 /*! @name IRBAR_JR - Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3 */
14715 /*! @{ */
14716 
14717 #define CAAM_IRBAR_JR_IRBA_MASK                  (0xFFFFFFFFFU)
14718 #define CAAM_IRBAR_JR_IRBA_SHIFT                 (0U)
14719 #define CAAM_IRBAR_JR_IRBA(x)                    (((uint64_t)(((uint64_t)(x)) << CAAM_IRBAR_JR_IRBA_SHIFT)) & CAAM_IRBAR_JR_IRBA_MASK)
14720 /*! @} */
14721 
14722 /* The count of CAAM_IRBAR_JR */
14723 #define CAAM_IRBAR_JR_COUNT                      (4U)
14724 
14725 /*! @name IRSR_JR - Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3 */
14726 /*! @{ */
14727 
14728 #define CAAM_IRSR_JR_IRS_MASK                    (0x3FFU)
14729 #define CAAM_IRSR_JR_IRS_SHIFT                   (0U)
14730 #define CAAM_IRSR_JR_IRS(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_IRSR_JR_IRS_SHIFT)) & CAAM_IRSR_JR_IRS_MASK)
14731 /*! @} */
14732 
14733 /* The count of CAAM_IRSR_JR */
14734 #define CAAM_IRSR_JR_COUNT                       (4U)
14735 
14736 /*! @name IRSAR_JR - Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3 */
14737 /*! @{ */
14738 
14739 #define CAAM_IRSAR_JR_IRSA_MASK                  (0x3FFU)
14740 #define CAAM_IRSAR_JR_IRSA_SHIFT                 (0U)
14741 #define CAAM_IRSAR_JR_IRSA(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_IRSAR_JR_IRSA_SHIFT)) & CAAM_IRSAR_JR_IRSA_MASK)
14742 /*! @} */
14743 
14744 /* The count of CAAM_IRSAR_JR */
14745 #define CAAM_IRSAR_JR_COUNT                      (4U)
14746 
14747 /*! @name IRJAR_JR - Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3 */
14748 /*! @{ */
14749 
14750 #define CAAM_IRJAR_JR_IRJA_MASK                  (0x3FFU)
14751 #define CAAM_IRJAR_JR_IRJA_SHIFT                 (0U)
14752 #define CAAM_IRJAR_JR_IRJA(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_IRJAR_JR_IRJA_SHIFT)) & CAAM_IRJAR_JR_IRJA_MASK)
14753 /*! @} */
14754 
14755 /* The count of CAAM_IRJAR_JR */
14756 #define CAAM_IRJAR_JR_COUNT                      (4U)
14757 
14758 /*! @name ORBAR_JR - Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3 */
14759 /*! @{ */
14760 
14761 #define CAAM_ORBAR_JR_ORBA_MASK                  (0xFFFFFFFFFU)
14762 #define CAAM_ORBAR_JR_ORBA_SHIFT                 (0U)
14763 #define CAAM_ORBAR_JR_ORBA(x)                    (((uint64_t)(((uint64_t)(x)) << CAAM_ORBAR_JR_ORBA_SHIFT)) & CAAM_ORBAR_JR_ORBA_MASK)
14764 /*! @} */
14765 
14766 /* The count of CAAM_ORBAR_JR */
14767 #define CAAM_ORBAR_JR_COUNT                      (4U)
14768 
14769 /*! @name ORSR_JR - Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3 */
14770 /*! @{ */
14771 
14772 #define CAAM_ORSR_JR_ORS_MASK                    (0x3FFU)
14773 #define CAAM_ORSR_JR_ORS_SHIFT                   (0U)
14774 #define CAAM_ORSR_JR_ORS(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_ORSR_JR_ORS_SHIFT)) & CAAM_ORSR_JR_ORS_MASK)
14775 /*! @} */
14776 
14777 /* The count of CAAM_ORSR_JR */
14778 #define CAAM_ORSR_JR_COUNT                       (4U)
14779 
14780 /*! @name ORJRR_JR - Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3 */
14781 /*! @{ */
14782 
14783 #define CAAM_ORJRR_JR_ORJR_MASK                  (0x3FFU)
14784 #define CAAM_ORJRR_JR_ORJR_SHIFT                 (0U)
14785 #define CAAM_ORJRR_JR_ORJR(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_ORJRR_JR_ORJR_SHIFT)) & CAAM_ORJRR_JR_ORJR_MASK)
14786 /*! @} */
14787 
14788 /* The count of CAAM_ORJRR_JR */
14789 #define CAAM_ORJRR_JR_COUNT                      (4U)
14790 
14791 /*! @name ORSFR_JR - Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3 */
14792 /*! @{ */
14793 
14794 #define CAAM_ORSFR_JR_ORSF_MASK                  (0x3FFU)
14795 #define CAAM_ORSFR_JR_ORSF_SHIFT                 (0U)
14796 #define CAAM_ORSFR_JR_ORSF(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_ORSFR_JR_ORSF_SHIFT)) & CAAM_ORSFR_JR_ORSF_MASK)
14797 /*! @} */
14798 
14799 /* The count of CAAM_ORSFR_JR */
14800 #define CAAM_ORSFR_JR_COUNT                      (4U)
14801 
14802 /*! @name JRSTAR_JR - Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3 */
14803 /*! @{ */
14804 
14805 #define CAAM_JRSTAR_JR_SSED_MASK                 (0xFFFFFFFU)
14806 #define CAAM_JRSTAR_JR_SSED_SHIFT                (0U)
14807 #define CAAM_JRSTAR_JR_SSED(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTAR_JR_SSED_SHIFT)) & CAAM_JRSTAR_JR_SSED_MASK)
14808 
14809 #define CAAM_JRSTAR_JR_SSRC_MASK                 (0xF0000000U)
14810 #define CAAM_JRSTAR_JR_SSRC_SHIFT                (28U)
14811 /*! SSRC
14812  *  0b0000..No Status Source (No Error or Status Reported)
14813  *  0b0001..Reserved
14814  *  0b0010..CCB Status Source (CCB Error Reported)
14815  *  0b0011..Jump Halt User Status Source (User-Provided Status Reported)
14816  *  0b0100..DECO Status Source (DECO Error Reported)
14817  *  0b0101..Reserved
14818  *  0b0110..Job Ring Status Source (Job Ring Error Reported)
14819  *  0b0111..Jump Halt Condition Codes (Condition Code Status Reported)
14820  */
14821 #define CAAM_JRSTAR_JR_SSRC(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTAR_JR_SSRC_SHIFT)) & CAAM_JRSTAR_JR_SSRC_MASK)
14822 /*! @} */
14823 
14824 /* The count of CAAM_JRSTAR_JR */
14825 #define CAAM_JRSTAR_JR_COUNT                     (4U)
14826 
14827 /*! @name JRINTR_JR - Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3 */
14828 /*! @{ */
14829 
14830 #define CAAM_JRINTR_JR_JRI_MASK                  (0x1U)
14831 #define CAAM_JRINTR_JR_JRI_SHIFT                 (0U)
14832 #define CAAM_JRINTR_JR_JRI(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_JRI_SHIFT)) & CAAM_JRINTR_JR_JRI_MASK)
14833 
14834 #define CAAM_JRINTR_JR_JRE_MASK                  (0x2U)
14835 #define CAAM_JRINTR_JR_JRE_SHIFT                 (1U)
14836 #define CAAM_JRINTR_JR_JRE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_JRE_SHIFT)) & CAAM_JRINTR_JR_JRE_MASK)
14837 
14838 #define CAAM_JRINTR_JR_HALT_MASK                 (0xCU)
14839 #define CAAM_JRINTR_JR_HALT_SHIFT                (2U)
14840 #define CAAM_JRINTR_JR_HALT(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_HALT_SHIFT)) & CAAM_JRINTR_JR_HALT_MASK)
14841 
14842 #define CAAM_JRINTR_JR_ENTER_FAIL_MASK           (0x10U)
14843 #define CAAM_JRINTR_JR_ENTER_FAIL_SHIFT          (4U)
14844 #define CAAM_JRINTR_JR_ENTER_FAIL(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ENTER_FAIL_SHIFT)) & CAAM_JRINTR_JR_ENTER_FAIL_MASK)
14845 
14846 #define CAAM_JRINTR_JR_EXIT_FAIL_MASK            (0x20U)
14847 #define CAAM_JRINTR_JR_EXIT_FAIL_SHIFT           (5U)
14848 #define CAAM_JRINTR_JR_EXIT_FAIL(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_EXIT_FAIL_SHIFT)) & CAAM_JRINTR_JR_EXIT_FAIL_MASK)
14849 
14850 #define CAAM_JRINTR_JR_ERR_TYPE_MASK             (0x1F00U)
14851 #define CAAM_JRINTR_JR_ERR_TYPE_SHIFT            (8U)
14852 /*! ERR_TYPE
14853  *  0b00001..Error writing status to Output Ring
14854  *  0b00011..Bad input ring base address (not on a 4-byte boundary).
14855  *  0b00100..Bad output ring base address (not on a 4-byte boundary).
14856  *  0b00101..Invalid write to Input Ring Base Address Register or Input Ring Size Register. Can be written when
14857  *           there are no jobs in the input ring or when the Job Ring is halted. These are fatal and will likely
14858  *           result in not being able to get all jobs out into the output ring for processing by software. Resetting
14859  *           the job ring will almost certainly be necessary.
14860  *  0b00110..Invalid write to Output Ring Base Address Register or Output Ring Size Register. Can be written when
14861  *           there are no jobs in the output ring and no jobs from this queue are already processing in CAAM (in
14862  *           the holding tanks or DECOs), or when the Job Ring is halted.
14863  *  0b00111..Job Ring reset released before Job Ring is halted.
14864  *  0b01000..Removed too many jobs (ORJRR larger than ORSFR).
14865  *  0b01001..Added too many jobs (IRJAR larger than IRSAR).
14866  *  0b01010..Writing ORSF > ORS In these error cases the write is ignored, the interrupt is asserted (unless
14867  *           masked) and the error bit and error_type fields are set in the Job Ring Interrupt Status Register.
14868  *  0b01011..Writing IRSA > IRS
14869  *  0b01100..Writing ORWI > ORS in bytes
14870  *  0b01101..Writing IRRI > IRS in bytes
14871  *  0b01110..Writing IRSA when ring is active
14872  *  0b01111..Writing IRRI when ring is active
14873  *  0b10000..Writing ORSF when ring is active
14874  *  0b10001..Writing ORWI when ring is active
14875  */
14876 #define CAAM_JRINTR_JR_ERR_TYPE(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ERR_TYPE_SHIFT)) & CAAM_JRINTR_JR_ERR_TYPE_MASK)
14877 
14878 #define CAAM_JRINTR_JR_ERR_ORWI_MASK             (0x3FFF0000U)
14879 #define CAAM_JRINTR_JR_ERR_ORWI_SHIFT            (16U)
14880 #define CAAM_JRINTR_JR_ERR_ORWI(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ERR_ORWI_SHIFT)) & CAAM_JRINTR_JR_ERR_ORWI_MASK)
14881 /*! @} */
14882 
14883 /* The count of CAAM_JRINTR_JR */
14884 #define CAAM_JRINTR_JR_COUNT                     (4U)
14885 
14886 /*! @name JRCFGR_JR_MS - Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half */
14887 /*! @{ */
14888 
14889 #define CAAM_JRCFGR_JR_MS_MBSI_MASK              (0x1U)
14890 #define CAAM_JRCFGR_JR_MS_MBSI_SHIFT             (0U)
14891 #define CAAM_JRCFGR_JR_MS_MBSI(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MBSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MBSI_MASK)
14892 
14893 #define CAAM_JRCFGR_JR_MS_MHWSI_MASK             (0x2U)
14894 #define CAAM_JRCFGR_JR_MS_MHWSI_SHIFT            (1U)
14895 #define CAAM_JRCFGR_JR_MS_MHWSI(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MHWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MHWSI_MASK)
14896 
14897 #define CAAM_JRCFGR_JR_MS_MWSI_MASK              (0x4U)
14898 #define CAAM_JRCFGR_JR_MS_MWSI_SHIFT             (2U)
14899 #define CAAM_JRCFGR_JR_MS_MWSI(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MWSI_MASK)
14900 
14901 #define CAAM_JRCFGR_JR_MS_CBSI_MASK              (0x10U)
14902 #define CAAM_JRCFGR_JR_MS_CBSI_SHIFT             (4U)
14903 #define CAAM_JRCFGR_JR_MS_CBSI(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CBSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CBSI_MASK)
14904 
14905 #define CAAM_JRCFGR_JR_MS_CHWSI_MASK             (0x20U)
14906 #define CAAM_JRCFGR_JR_MS_CHWSI_SHIFT            (5U)
14907 #define CAAM_JRCFGR_JR_MS_CHWSI(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CHWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CHWSI_MASK)
14908 
14909 #define CAAM_JRCFGR_JR_MS_CWSI_MASK              (0x40U)
14910 #define CAAM_JRCFGR_JR_MS_CWSI_SHIFT             (6U)
14911 #define CAAM_JRCFGR_JR_MS_CWSI(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CWSI_MASK)
14912 
14913 #define CAAM_JRCFGR_JR_MS_MBSO_MASK              (0x100U)
14914 #define CAAM_JRCFGR_JR_MS_MBSO_SHIFT             (8U)
14915 #define CAAM_JRCFGR_JR_MS_MBSO(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MBSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MBSO_MASK)
14916 
14917 #define CAAM_JRCFGR_JR_MS_MHWSO_MASK             (0x200U)
14918 #define CAAM_JRCFGR_JR_MS_MHWSO_SHIFT            (9U)
14919 #define CAAM_JRCFGR_JR_MS_MHWSO(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MHWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MHWSO_MASK)
14920 
14921 #define CAAM_JRCFGR_JR_MS_MWSO_MASK              (0x400U)
14922 #define CAAM_JRCFGR_JR_MS_MWSO_SHIFT             (10U)
14923 #define CAAM_JRCFGR_JR_MS_MWSO(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MWSO_MASK)
14924 
14925 #define CAAM_JRCFGR_JR_MS_CBSO_MASK              (0x1000U)
14926 #define CAAM_JRCFGR_JR_MS_CBSO_SHIFT             (12U)
14927 #define CAAM_JRCFGR_JR_MS_CBSO(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CBSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CBSO_MASK)
14928 
14929 #define CAAM_JRCFGR_JR_MS_CHWSO_MASK             (0x2000U)
14930 #define CAAM_JRCFGR_JR_MS_CHWSO_SHIFT            (13U)
14931 #define CAAM_JRCFGR_JR_MS_CHWSO(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CHWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CHWSO_MASK)
14932 
14933 #define CAAM_JRCFGR_JR_MS_CWSO_MASK              (0x4000U)
14934 #define CAAM_JRCFGR_JR_MS_CWSO_SHIFT             (14U)
14935 #define CAAM_JRCFGR_JR_MS_CWSO(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CWSO_MASK)
14936 
14937 #define CAAM_JRCFGR_JR_MS_DMBS_MASK              (0x10000U)
14938 #define CAAM_JRCFGR_JR_MS_DMBS_SHIFT             (16U)
14939 #define CAAM_JRCFGR_JR_MS_DMBS(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_DMBS_SHIFT)) & CAAM_JRCFGR_JR_MS_DMBS_MASK)
14940 
14941 #define CAAM_JRCFGR_JR_MS_PEO_MASK               (0x20000U)
14942 #define CAAM_JRCFGR_JR_MS_PEO_SHIFT              (17U)
14943 #define CAAM_JRCFGR_JR_MS_PEO(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_PEO_SHIFT)) & CAAM_JRCFGR_JR_MS_PEO_MASK)
14944 
14945 #define CAAM_JRCFGR_JR_MS_DWSO_MASK              (0x40000U)
14946 #define CAAM_JRCFGR_JR_MS_DWSO_SHIFT             (18U)
14947 #define CAAM_JRCFGR_JR_MS_DWSO(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_DWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_DWSO_MASK)
14948 
14949 #define CAAM_JRCFGR_JR_MS_FAIL_MODE_MASK         (0x20000000U)
14950 #define CAAM_JRCFGR_JR_MS_FAIL_MODE_SHIFT        (29U)
14951 #define CAAM_JRCFGR_JR_MS_FAIL_MODE(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_FAIL_MODE_SHIFT)) & CAAM_JRCFGR_JR_MS_FAIL_MODE_MASK)
14952 
14953 #define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_MASK      (0x40000000U)
14954 #define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_SHIFT     (30U)
14955 #define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT(x)        (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_SHIFT)) & CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_MASK)
14956 /*! @} */
14957 
14958 /* The count of CAAM_JRCFGR_JR_MS */
14959 #define CAAM_JRCFGR_JR_MS_COUNT                  (4U)
14960 
14961 /*! @name JRCFGR_JR_LS - Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half */
14962 /*! @{ */
14963 
14964 #define CAAM_JRCFGR_JR_LS_IMSK_MASK              (0x1U)
14965 #define CAAM_JRCFGR_JR_LS_IMSK_SHIFT             (0U)
14966 /*! IMSK
14967  *  0b0..Interrupt enabled.
14968  *  0b1..Interrupt masked.
14969  */
14970 #define CAAM_JRCFGR_JR_LS_IMSK(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_IMSK_SHIFT)) & CAAM_JRCFGR_JR_LS_IMSK_MASK)
14971 
14972 #define CAAM_JRCFGR_JR_LS_ICEN_MASK              (0x2U)
14973 #define CAAM_JRCFGR_JR_LS_ICEN_SHIFT             (1U)
14974 /*! ICEN
14975  *  0b0..Interrupt coalescing is disabled. If the IMSK bit is cleared, an interrupt is asserted whenever a job is
14976  *       written to the output ring. ICDCT is ignored. Note that if software removes one or more jobs and clears
14977  *       the interrupt but the output rings slots full is still greater than 0 (ORSF > 0), then the interrupt will
14978  *       clear but reassert on the next clock cycle.
14979  *  0b1..Interrupt coalescing is enabled. If the IMSK bit is cleared, an interrupt is asserted whenever the
14980  *       threshold number of frames is reached (ICDCT) or when the threshold timer expires (ICTT). Note that if software
14981  *       removes one or more jobs and clears the interrupt but the interrupt coalescing threshold is still met
14982  *       (ORSF >= ICDCT), then the interrupt will clear but reassert on the next clock cycle.
14983  */
14984 #define CAAM_JRCFGR_JR_LS_ICEN(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICEN_SHIFT)) & CAAM_JRCFGR_JR_LS_ICEN_MASK)
14985 
14986 #define CAAM_JRCFGR_JR_LS_ICDCT_MASK             (0xFF00U)
14987 #define CAAM_JRCFGR_JR_LS_ICDCT_SHIFT            (8U)
14988 #define CAAM_JRCFGR_JR_LS_ICDCT(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICDCT_SHIFT)) & CAAM_JRCFGR_JR_LS_ICDCT_MASK)
14989 
14990 #define CAAM_JRCFGR_JR_LS_ICTT_MASK              (0xFFFF0000U)
14991 #define CAAM_JRCFGR_JR_LS_ICTT_SHIFT             (16U)
14992 #define CAAM_JRCFGR_JR_LS_ICTT(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICTT_SHIFT)) & CAAM_JRCFGR_JR_LS_ICTT_MASK)
14993 /*! @} */
14994 
14995 /* The count of CAAM_JRCFGR_JR_LS */
14996 #define CAAM_JRCFGR_JR_LS_COUNT                  (4U)
14997 
14998 /*! @name IRRIR_JR - Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3 */
14999 /*! @{ */
15000 
15001 #define CAAM_IRRIR_JR_IRRI_MASK                  (0x1FFFU)
15002 #define CAAM_IRRIR_JR_IRRI_SHIFT                 (0U)
15003 #define CAAM_IRRIR_JR_IRRI(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_IRRIR_JR_IRRI_SHIFT)) & CAAM_IRRIR_JR_IRRI_MASK)
15004 /*! @} */
15005 
15006 /* The count of CAAM_IRRIR_JR */
15007 #define CAAM_IRRIR_JR_COUNT                      (4U)
15008 
15009 /*! @name ORWIR_JR - Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3 */
15010 /*! @{ */
15011 
15012 #define CAAM_ORWIR_JR_ORWI_MASK                  (0x3FFFU)
15013 #define CAAM_ORWIR_JR_ORWI_SHIFT                 (0U)
15014 #define CAAM_ORWIR_JR_ORWI(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_ORWIR_JR_ORWI_SHIFT)) & CAAM_ORWIR_JR_ORWI_MASK)
15015 /*! @} */
15016 
15017 /* The count of CAAM_ORWIR_JR */
15018 #define CAAM_ORWIR_JR_COUNT                      (4U)
15019 
15020 /*! @name JRCR_JR - Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3 */
15021 /*! @{ */
15022 
15023 #define CAAM_JRCR_JR_RESET_MASK                  (0x1U)
15024 #define CAAM_JRCR_JR_RESET_SHIFT                 (0U)
15025 #define CAAM_JRCR_JR_RESET(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_JRCR_JR_RESET_SHIFT)) & CAAM_JRCR_JR_RESET_MASK)
15026 
15027 #define CAAM_JRCR_JR_PARK_MASK                   (0x2U)
15028 #define CAAM_JRCR_JR_PARK_SHIFT                  (1U)
15029 #define CAAM_JRCR_JR_PARK(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_JRCR_JR_PARK_SHIFT)) & CAAM_JRCR_JR_PARK_MASK)
15030 /*! @} */
15031 
15032 /* The count of CAAM_JRCR_JR */
15033 #define CAAM_JRCR_JR_COUNT                       (4U)
15034 
15035 /*! @name JRAAV - Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register */
15036 /*! @{ */
15037 
15038 #define CAAM_JRAAV_V0_MASK                       (0x1U)
15039 #define CAAM_JRAAV_V0_SHIFT                      (0U)
15040 #define CAAM_JRAAV_V0(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V0_SHIFT)) & CAAM_JRAAV_V0_MASK)
15041 
15042 #define CAAM_JRAAV_V1_MASK                       (0x2U)
15043 #define CAAM_JRAAV_V1_SHIFT                      (1U)
15044 #define CAAM_JRAAV_V1(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V1_SHIFT)) & CAAM_JRAAV_V1_MASK)
15045 
15046 #define CAAM_JRAAV_V2_MASK                       (0x4U)
15047 #define CAAM_JRAAV_V2_SHIFT                      (2U)
15048 #define CAAM_JRAAV_V2(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V2_SHIFT)) & CAAM_JRAAV_V2_MASK)
15049 
15050 #define CAAM_JRAAV_V3_MASK                       (0x8U)
15051 #define CAAM_JRAAV_V3_SHIFT                      (3U)
15052 #define CAAM_JRAAV_V3(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V3_SHIFT)) & CAAM_JRAAV_V3_MASK)
15053 
15054 #define CAAM_JRAAV_BC_MASK                       (0x80000000U)
15055 #define CAAM_JRAAV_BC_SHIFT                      (31U)
15056 #define CAAM_JRAAV_BC(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_BC_SHIFT)) & CAAM_JRAAV_BC_MASK)
15057 /*! @} */
15058 
15059 /* The count of CAAM_JRAAV */
15060 #define CAAM_JRAAV_COUNT                         (4U)
15061 
15062 /*! @name JRAAA - Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register */
15063 /*! @{ */
15064 
15065 #define CAAM_JRAAA_JD_ADDR_MASK                  (0xFFFFFFFFFU)
15066 #define CAAM_JRAAA_JD_ADDR_SHIFT                 (0U)
15067 #define CAAM_JRAAA_JD_ADDR(x)                    (((uint64_t)(((uint64_t)(x)) << CAAM_JRAAA_JD_ADDR_SHIFT)) & CAAM_JRAAA_JD_ADDR_MASK)
15068 /*! @} */
15069 
15070 /* The count of CAAM_JRAAA */
15071 #define CAAM_JRAAA_COUNT                         (4U)
15072 
15073 /* The count of CAAM_JRAAA */
15074 #define CAAM_JRAAA_COUNT2                        (4U)
15075 
15076 /*! @name PX_SDID_JR - Partition 0 SDID register..Partition 15 SDID register */
15077 /*! @{ */
15078 
15079 #define CAAM_PX_SDID_JR_SDID_MASK                (0xFFFFU)
15080 #define CAAM_PX_SDID_JR_SDID_SHIFT               (0U)
15081 #define CAAM_PX_SDID_JR_SDID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDID_JR_SDID_SHIFT)) & CAAM_PX_SDID_JR_SDID_MASK)
15082 /*! @} */
15083 
15084 /* The count of CAAM_PX_SDID_JR */
15085 #define CAAM_PX_SDID_JR_COUNT                    (4U)
15086 
15087 /* The count of CAAM_PX_SDID_JR */
15088 #define CAAM_PX_SDID_JR_COUNT2                   (16U)
15089 
15090 /*! @name PX_SMAPR_JR - Secure Memory Access Permissions register */
15091 /*! @{ */
15092 
15093 #define CAAM_PX_SMAPR_JR_G1_READ_MASK            (0x1U)
15094 #define CAAM_PX_SMAPR_JR_G1_READ_SHIFT           (0U)
15095 /*! G1_READ
15096  *  0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and
15097  *       key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a
15098  *       Trusted Descriptor and G1_TDO=1).
15099  *  0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
15100  *       G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0).
15101  */
15102 #define CAAM_PX_SMAPR_JR_G1_READ(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_READ_SHIFT)) & CAAM_PX_SMAPR_JR_G1_READ_MASK)
15103 
15104 #define CAAM_PX_SMAPR_JR_G1_WRITE_MASK           (0x2U)
15105 #define CAAM_PX_SMAPR_JR_G1_WRITE_SHIFT          (1U)
15106 /*! G1_WRITE
15107  *  0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
15108  *       Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1).
15109  *  0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is
15110  *       not a Trusted Descriptor or if G1_TDO=0).
15111  */
15112 #define CAAM_PX_SMAPR_JR_G1_WRITE(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_WRITE_SHIFT)) & CAAM_PX_SMAPR_JR_G1_WRITE_MASK)
15113 
15114 #define CAAM_PX_SMAPR_JR_G1_TDO_MASK             (0x4U)
15115 #define CAAM_PX_SMAPR_JR_G1_TDO_SHIFT            (2U)
15116 /*! G1_TDO
15117  *  0b0..Trusted Descriptors have the same access privileges as Job Descriptors
15118  *  0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
15119  *       or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB,
15120  *       G1_WRITE and G1_READ settings.
15121  */
15122 #define CAAM_PX_SMAPR_JR_G1_TDO(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_TDO_SHIFT)) & CAAM_PX_SMAPR_JR_G1_TDO_MASK)
15123 
15124 #define CAAM_PX_SMAPR_JR_G1_SMBLOB_MASK          (0x8U)
15125 #define CAAM_PX_SMAPR_JR_G1_SMBLOB_SHIFT         (3U)
15126 /*! G1_SMBLOB
15127  *  0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1.
15128  *  0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings.
15129  */
15130 #define CAAM_PX_SMAPR_JR_G1_SMBLOB(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_JR_G1_SMBLOB_MASK)
15131 
15132 #define CAAM_PX_SMAPR_JR_G2_READ_MASK            (0x10U)
15133 #define CAAM_PX_SMAPR_JR_G2_READ_SHIFT           (4U)
15134 /*! G2_READ
15135  *  0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and
15136  *       key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a
15137  *       Trusted Descriptor and G2_TDO=1).
15138  *  0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
15139  *       G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0).
15140  */
15141 #define CAAM_PX_SMAPR_JR_G2_READ(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_READ_SHIFT)) & CAAM_PX_SMAPR_JR_G2_READ_MASK)
15142 
15143 #define CAAM_PX_SMAPR_JR_G2_WRITE_MASK           (0x20U)
15144 #define CAAM_PX_SMAPR_JR_G2_WRITE_SHIFT          (5U)
15145 /*! G2_WRITE
15146  *  0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
15147  *       Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1).
15148  *  0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is
15149  *       not a Trusted Descriptor or if G2_TDO=0).
15150  */
15151 #define CAAM_PX_SMAPR_JR_G2_WRITE(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_WRITE_SHIFT)) & CAAM_PX_SMAPR_JR_G2_WRITE_MASK)
15152 
15153 #define CAAM_PX_SMAPR_JR_G2_TDO_MASK             (0x40U)
15154 #define CAAM_PX_SMAPR_JR_G2_TDO_SHIFT            (6U)
15155 /*! G2_TDO
15156  *  0b0..Trusted Descriptors have the same access privileges as Job Descriptors
15157  *  0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
15158  *       or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB,
15159  *       G2_WRITE and G2_READ settings.
15160  */
15161 #define CAAM_PX_SMAPR_JR_G2_TDO(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_TDO_SHIFT)) & CAAM_PX_SMAPR_JR_G2_TDO_MASK)
15162 
15163 #define CAAM_PX_SMAPR_JR_G2_SMBLOB_MASK          (0x80U)
15164 #define CAAM_PX_SMAPR_JR_G2_SMBLOB_SHIFT         (7U)
15165 /*! G2_SMBLOB
15166  *  0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1.
15167  *  0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings.
15168  */
15169 #define CAAM_PX_SMAPR_JR_G2_SMBLOB(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_JR_G2_SMBLOB_MASK)
15170 
15171 #define CAAM_PX_SMAPR_JR_SMAG_LCK_MASK           (0x1000U)
15172 #define CAAM_PX_SMAPR_JR_SMAG_LCK_SHIFT          (12U)
15173 /*! SMAG_LCK
15174  *  0b0..The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers.
15175  *  0b1..The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed
15176  *       until the partition is de-allocated or a POR occurs.
15177  */
15178 #define CAAM_PX_SMAPR_JR_SMAG_LCK(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_SMAG_LCK_SHIFT)) & CAAM_PX_SMAPR_JR_SMAG_LCK_MASK)
15179 
15180 #define CAAM_PX_SMAPR_JR_SMAP_LCK_MASK           (0x2000U)
15181 #define CAAM_PX_SMAPR_JR_SMAP_LCK_SHIFT          (13U)
15182 /*! SMAP_LCK
15183  *  0b0..The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register.
15184  *  0b1..The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP
15185  *       register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can
15186  *       still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0.
15187  */
15188 #define CAAM_PX_SMAPR_JR_SMAP_LCK(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_SMAP_LCK_SHIFT)) & CAAM_PX_SMAPR_JR_SMAP_LCK_MASK)
15189 
15190 #define CAAM_PX_SMAPR_JR_PSP_MASK                (0x4000U)
15191 #define CAAM_PX_SMAPR_JR_PSP_SHIFT               (14U)
15192 /*! PSP
15193  *  0b0..The partition and any of the pages allocated to the partition can be de-allocated.
15194  *  0b1..The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated.
15195  */
15196 #define CAAM_PX_SMAPR_JR_PSP(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_PSP_SHIFT)) & CAAM_PX_SMAPR_JR_PSP_MASK)
15197 
15198 #define CAAM_PX_SMAPR_JR_CSP_MASK                (0x8000U)
15199 #define CAAM_PX_SMAPR_JR_CSP_SHIFT               (15U)
15200 /*! CSP
15201  *  0b0..The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is
15202  *       released or a security alarm occurs.
15203  *  0b1..The pages allocated to the partition will be zeroized when they are individually de-allocated or the
15204  *       partition is released or a security alarm occurs.
15205  */
15206 #define CAAM_PX_SMAPR_JR_CSP(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_CSP_SHIFT)) & CAAM_PX_SMAPR_JR_CSP_MASK)
15207 
15208 #define CAAM_PX_SMAPR_JR_PARTITION_KMOD_MASK     (0xFFFF0000U)
15209 #define CAAM_PX_SMAPR_JR_PARTITION_KMOD_SHIFT    (16U)
15210 #define CAAM_PX_SMAPR_JR_PARTITION_KMOD(x)       (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_PARTITION_KMOD_SHIFT)) & CAAM_PX_SMAPR_JR_PARTITION_KMOD_MASK)
15211 /*! @} */
15212 
15213 /* The count of CAAM_PX_SMAPR_JR */
15214 #define CAAM_PX_SMAPR_JR_COUNT                   (4U)
15215 
15216 /* The count of CAAM_PX_SMAPR_JR */
15217 #define CAAM_PX_SMAPR_JR_COUNT2                  (16U)
15218 
15219 /*! @name PX_SMAG2_JR - Secure Memory Access Group Registers */
15220 /*! @{ */
15221 
15222 #define CAAM_PX_SMAG2_JR_Gx_ID00_MASK            (0x1U)
15223 #define CAAM_PX_SMAG2_JR_Gx_ID00_SHIFT           (0U)
15224 #define CAAM_PX_SMAG2_JR_Gx_ID00(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID00_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID00_MASK)
15225 
15226 #define CAAM_PX_SMAG2_JR_Gx_ID01_MASK            (0x2U)
15227 #define CAAM_PX_SMAG2_JR_Gx_ID01_SHIFT           (1U)
15228 #define CAAM_PX_SMAG2_JR_Gx_ID01(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID01_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID01_MASK)
15229 
15230 #define CAAM_PX_SMAG2_JR_Gx_ID02_MASK            (0x4U)
15231 #define CAAM_PX_SMAG2_JR_Gx_ID02_SHIFT           (2U)
15232 #define CAAM_PX_SMAG2_JR_Gx_ID02(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID02_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID02_MASK)
15233 
15234 #define CAAM_PX_SMAG2_JR_Gx_ID03_MASK            (0x8U)
15235 #define CAAM_PX_SMAG2_JR_Gx_ID03_SHIFT           (3U)
15236 #define CAAM_PX_SMAG2_JR_Gx_ID03(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID03_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID03_MASK)
15237 
15238 #define CAAM_PX_SMAG2_JR_Gx_ID04_MASK            (0x10U)
15239 #define CAAM_PX_SMAG2_JR_Gx_ID04_SHIFT           (4U)
15240 #define CAAM_PX_SMAG2_JR_Gx_ID04(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID04_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID04_MASK)
15241 
15242 #define CAAM_PX_SMAG2_JR_Gx_ID05_MASK            (0x20U)
15243 #define CAAM_PX_SMAG2_JR_Gx_ID05_SHIFT           (5U)
15244 #define CAAM_PX_SMAG2_JR_Gx_ID05(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID05_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID05_MASK)
15245 
15246 #define CAAM_PX_SMAG2_JR_Gx_ID06_MASK            (0x40U)
15247 #define CAAM_PX_SMAG2_JR_Gx_ID06_SHIFT           (6U)
15248 #define CAAM_PX_SMAG2_JR_Gx_ID06(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID06_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID06_MASK)
15249 
15250 #define CAAM_PX_SMAG2_JR_Gx_ID07_MASK            (0x80U)
15251 #define CAAM_PX_SMAG2_JR_Gx_ID07_SHIFT           (7U)
15252 #define CAAM_PX_SMAG2_JR_Gx_ID07(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID07_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID07_MASK)
15253 
15254 #define CAAM_PX_SMAG2_JR_Gx_ID08_MASK            (0x100U)
15255 #define CAAM_PX_SMAG2_JR_Gx_ID08_SHIFT           (8U)
15256 #define CAAM_PX_SMAG2_JR_Gx_ID08(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID08_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID08_MASK)
15257 
15258 #define CAAM_PX_SMAG2_JR_Gx_ID09_MASK            (0x200U)
15259 #define CAAM_PX_SMAG2_JR_Gx_ID09_SHIFT           (9U)
15260 #define CAAM_PX_SMAG2_JR_Gx_ID09(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID09_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID09_MASK)
15261 
15262 #define CAAM_PX_SMAG2_JR_Gx_ID10_MASK            (0x400U)
15263 #define CAAM_PX_SMAG2_JR_Gx_ID10_SHIFT           (10U)
15264 #define CAAM_PX_SMAG2_JR_Gx_ID10(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID10_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID10_MASK)
15265 
15266 #define CAAM_PX_SMAG2_JR_Gx_ID11_MASK            (0x800U)
15267 #define CAAM_PX_SMAG2_JR_Gx_ID11_SHIFT           (11U)
15268 #define CAAM_PX_SMAG2_JR_Gx_ID11(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID11_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID11_MASK)
15269 
15270 #define CAAM_PX_SMAG2_JR_Gx_ID12_MASK            (0x1000U)
15271 #define CAAM_PX_SMAG2_JR_Gx_ID12_SHIFT           (12U)
15272 #define CAAM_PX_SMAG2_JR_Gx_ID12(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID12_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID12_MASK)
15273 
15274 #define CAAM_PX_SMAG2_JR_Gx_ID13_MASK            (0x2000U)
15275 #define CAAM_PX_SMAG2_JR_Gx_ID13_SHIFT           (13U)
15276 #define CAAM_PX_SMAG2_JR_Gx_ID13(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID13_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID13_MASK)
15277 
15278 #define CAAM_PX_SMAG2_JR_Gx_ID14_MASK            (0x4000U)
15279 #define CAAM_PX_SMAG2_JR_Gx_ID14_SHIFT           (14U)
15280 #define CAAM_PX_SMAG2_JR_Gx_ID14(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID14_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID14_MASK)
15281 
15282 #define CAAM_PX_SMAG2_JR_Gx_ID15_MASK            (0x8000U)
15283 #define CAAM_PX_SMAG2_JR_Gx_ID15_SHIFT           (15U)
15284 #define CAAM_PX_SMAG2_JR_Gx_ID15(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID15_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID15_MASK)
15285 
15286 #define CAAM_PX_SMAG2_JR_Gx_ID16_MASK            (0x10000U)
15287 #define CAAM_PX_SMAG2_JR_Gx_ID16_SHIFT           (16U)
15288 #define CAAM_PX_SMAG2_JR_Gx_ID16(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID16_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID16_MASK)
15289 
15290 #define CAAM_PX_SMAG2_JR_Gx_ID17_MASK            (0x20000U)
15291 #define CAAM_PX_SMAG2_JR_Gx_ID17_SHIFT           (17U)
15292 #define CAAM_PX_SMAG2_JR_Gx_ID17(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID17_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID17_MASK)
15293 
15294 #define CAAM_PX_SMAG2_JR_Gx_ID18_MASK            (0x40000U)
15295 #define CAAM_PX_SMAG2_JR_Gx_ID18_SHIFT           (18U)
15296 #define CAAM_PX_SMAG2_JR_Gx_ID18(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID18_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID18_MASK)
15297 
15298 #define CAAM_PX_SMAG2_JR_Gx_ID19_MASK            (0x80000U)
15299 #define CAAM_PX_SMAG2_JR_Gx_ID19_SHIFT           (19U)
15300 #define CAAM_PX_SMAG2_JR_Gx_ID19(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID19_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID19_MASK)
15301 
15302 #define CAAM_PX_SMAG2_JR_Gx_ID20_MASK            (0x100000U)
15303 #define CAAM_PX_SMAG2_JR_Gx_ID20_SHIFT           (20U)
15304 #define CAAM_PX_SMAG2_JR_Gx_ID20(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID20_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID20_MASK)
15305 
15306 #define CAAM_PX_SMAG2_JR_Gx_ID21_MASK            (0x200000U)
15307 #define CAAM_PX_SMAG2_JR_Gx_ID21_SHIFT           (21U)
15308 #define CAAM_PX_SMAG2_JR_Gx_ID21(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID21_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID21_MASK)
15309 
15310 #define CAAM_PX_SMAG2_JR_Gx_ID22_MASK            (0x400000U)
15311 #define CAAM_PX_SMAG2_JR_Gx_ID22_SHIFT           (22U)
15312 #define CAAM_PX_SMAG2_JR_Gx_ID22(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID22_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID22_MASK)
15313 
15314 #define CAAM_PX_SMAG2_JR_Gx_ID23_MASK            (0x800000U)
15315 #define CAAM_PX_SMAG2_JR_Gx_ID23_SHIFT           (23U)
15316 #define CAAM_PX_SMAG2_JR_Gx_ID23(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID23_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID23_MASK)
15317 
15318 #define CAAM_PX_SMAG2_JR_Gx_ID24_MASK            (0x1000000U)
15319 #define CAAM_PX_SMAG2_JR_Gx_ID24_SHIFT           (24U)
15320 #define CAAM_PX_SMAG2_JR_Gx_ID24(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID24_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID24_MASK)
15321 
15322 #define CAAM_PX_SMAG2_JR_Gx_ID25_MASK            (0x2000000U)
15323 #define CAAM_PX_SMAG2_JR_Gx_ID25_SHIFT           (25U)
15324 #define CAAM_PX_SMAG2_JR_Gx_ID25(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID25_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID25_MASK)
15325 
15326 #define CAAM_PX_SMAG2_JR_Gx_ID26_MASK            (0x4000000U)
15327 #define CAAM_PX_SMAG2_JR_Gx_ID26_SHIFT           (26U)
15328 #define CAAM_PX_SMAG2_JR_Gx_ID26(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID26_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID26_MASK)
15329 
15330 #define CAAM_PX_SMAG2_JR_Gx_ID27_MASK            (0x8000000U)
15331 #define CAAM_PX_SMAG2_JR_Gx_ID27_SHIFT           (27U)
15332 #define CAAM_PX_SMAG2_JR_Gx_ID27(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID27_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID27_MASK)
15333 
15334 #define CAAM_PX_SMAG2_JR_Gx_ID28_MASK            (0x10000000U)
15335 #define CAAM_PX_SMAG2_JR_Gx_ID28_SHIFT           (28U)
15336 #define CAAM_PX_SMAG2_JR_Gx_ID28(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID28_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID28_MASK)
15337 
15338 #define CAAM_PX_SMAG2_JR_Gx_ID29_MASK            (0x20000000U)
15339 #define CAAM_PX_SMAG2_JR_Gx_ID29_SHIFT           (29U)
15340 #define CAAM_PX_SMAG2_JR_Gx_ID29(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID29_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID29_MASK)
15341 
15342 #define CAAM_PX_SMAG2_JR_Gx_ID30_MASK            (0x40000000U)
15343 #define CAAM_PX_SMAG2_JR_Gx_ID30_SHIFT           (30U)
15344 #define CAAM_PX_SMAG2_JR_Gx_ID30(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID30_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID30_MASK)
15345 
15346 #define CAAM_PX_SMAG2_JR_Gx_ID31_MASK            (0x80000000U)
15347 #define CAAM_PX_SMAG2_JR_Gx_ID31_SHIFT           (31U)
15348 #define CAAM_PX_SMAG2_JR_Gx_ID31(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID31_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID31_MASK)
15349 /*! @} */
15350 
15351 /* The count of CAAM_PX_SMAG2_JR */
15352 #define CAAM_PX_SMAG2_JR_COUNT                   (4U)
15353 
15354 /* The count of CAAM_PX_SMAG2_JR */
15355 #define CAAM_PX_SMAG2_JR_COUNT2                  (16U)
15356 
15357 /*! @name PX_SMAG1_JR - Secure Memory Access Group Registers */
15358 /*! @{ */
15359 
15360 #define CAAM_PX_SMAG1_JR_Gx_ID00_MASK            (0x1U)
15361 #define CAAM_PX_SMAG1_JR_Gx_ID00_SHIFT           (0U)
15362 #define CAAM_PX_SMAG1_JR_Gx_ID00(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID00_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID00_MASK)
15363 
15364 #define CAAM_PX_SMAG1_JR_Gx_ID01_MASK            (0x2U)
15365 #define CAAM_PX_SMAG1_JR_Gx_ID01_SHIFT           (1U)
15366 #define CAAM_PX_SMAG1_JR_Gx_ID01(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID01_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID01_MASK)
15367 
15368 #define CAAM_PX_SMAG1_JR_Gx_ID02_MASK            (0x4U)
15369 #define CAAM_PX_SMAG1_JR_Gx_ID02_SHIFT           (2U)
15370 #define CAAM_PX_SMAG1_JR_Gx_ID02(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID02_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID02_MASK)
15371 
15372 #define CAAM_PX_SMAG1_JR_Gx_ID03_MASK            (0x8U)
15373 #define CAAM_PX_SMAG1_JR_Gx_ID03_SHIFT           (3U)
15374 #define CAAM_PX_SMAG1_JR_Gx_ID03(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID03_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID03_MASK)
15375 
15376 #define CAAM_PX_SMAG1_JR_Gx_ID04_MASK            (0x10U)
15377 #define CAAM_PX_SMAG1_JR_Gx_ID04_SHIFT           (4U)
15378 #define CAAM_PX_SMAG1_JR_Gx_ID04(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID04_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID04_MASK)
15379 
15380 #define CAAM_PX_SMAG1_JR_Gx_ID05_MASK            (0x20U)
15381 #define CAAM_PX_SMAG1_JR_Gx_ID05_SHIFT           (5U)
15382 #define CAAM_PX_SMAG1_JR_Gx_ID05(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID05_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID05_MASK)
15383 
15384 #define CAAM_PX_SMAG1_JR_Gx_ID06_MASK            (0x40U)
15385 #define CAAM_PX_SMAG1_JR_Gx_ID06_SHIFT           (6U)
15386 #define CAAM_PX_SMAG1_JR_Gx_ID06(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID06_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID06_MASK)
15387 
15388 #define CAAM_PX_SMAG1_JR_Gx_ID07_MASK            (0x80U)
15389 #define CAAM_PX_SMAG1_JR_Gx_ID07_SHIFT           (7U)
15390 #define CAAM_PX_SMAG1_JR_Gx_ID07(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID07_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID07_MASK)
15391 
15392 #define CAAM_PX_SMAG1_JR_Gx_ID08_MASK            (0x100U)
15393 #define CAAM_PX_SMAG1_JR_Gx_ID08_SHIFT           (8U)
15394 #define CAAM_PX_SMAG1_JR_Gx_ID08(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID08_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID08_MASK)
15395 
15396 #define CAAM_PX_SMAG1_JR_Gx_ID09_MASK            (0x200U)
15397 #define CAAM_PX_SMAG1_JR_Gx_ID09_SHIFT           (9U)
15398 #define CAAM_PX_SMAG1_JR_Gx_ID09(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID09_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID09_MASK)
15399 
15400 #define CAAM_PX_SMAG1_JR_Gx_ID10_MASK            (0x400U)
15401 #define CAAM_PX_SMAG1_JR_Gx_ID10_SHIFT           (10U)
15402 #define CAAM_PX_SMAG1_JR_Gx_ID10(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID10_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID10_MASK)
15403 
15404 #define CAAM_PX_SMAG1_JR_Gx_ID11_MASK            (0x800U)
15405 #define CAAM_PX_SMAG1_JR_Gx_ID11_SHIFT           (11U)
15406 #define CAAM_PX_SMAG1_JR_Gx_ID11(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID11_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID11_MASK)
15407 
15408 #define CAAM_PX_SMAG1_JR_Gx_ID12_MASK            (0x1000U)
15409 #define CAAM_PX_SMAG1_JR_Gx_ID12_SHIFT           (12U)
15410 #define CAAM_PX_SMAG1_JR_Gx_ID12(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID12_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID12_MASK)
15411 
15412 #define CAAM_PX_SMAG1_JR_Gx_ID13_MASK            (0x2000U)
15413 #define CAAM_PX_SMAG1_JR_Gx_ID13_SHIFT           (13U)
15414 #define CAAM_PX_SMAG1_JR_Gx_ID13(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID13_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID13_MASK)
15415 
15416 #define CAAM_PX_SMAG1_JR_Gx_ID14_MASK            (0x4000U)
15417 #define CAAM_PX_SMAG1_JR_Gx_ID14_SHIFT           (14U)
15418 #define CAAM_PX_SMAG1_JR_Gx_ID14(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID14_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID14_MASK)
15419 
15420 #define CAAM_PX_SMAG1_JR_Gx_ID15_MASK            (0x8000U)
15421 #define CAAM_PX_SMAG1_JR_Gx_ID15_SHIFT           (15U)
15422 #define CAAM_PX_SMAG1_JR_Gx_ID15(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID15_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID15_MASK)
15423 
15424 #define CAAM_PX_SMAG1_JR_Gx_ID16_MASK            (0x10000U)
15425 #define CAAM_PX_SMAG1_JR_Gx_ID16_SHIFT           (16U)
15426 #define CAAM_PX_SMAG1_JR_Gx_ID16(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID16_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID16_MASK)
15427 
15428 #define CAAM_PX_SMAG1_JR_Gx_ID17_MASK            (0x20000U)
15429 #define CAAM_PX_SMAG1_JR_Gx_ID17_SHIFT           (17U)
15430 #define CAAM_PX_SMAG1_JR_Gx_ID17(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID17_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID17_MASK)
15431 
15432 #define CAAM_PX_SMAG1_JR_Gx_ID18_MASK            (0x40000U)
15433 #define CAAM_PX_SMAG1_JR_Gx_ID18_SHIFT           (18U)
15434 #define CAAM_PX_SMAG1_JR_Gx_ID18(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID18_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID18_MASK)
15435 
15436 #define CAAM_PX_SMAG1_JR_Gx_ID19_MASK            (0x80000U)
15437 #define CAAM_PX_SMAG1_JR_Gx_ID19_SHIFT           (19U)
15438 #define CAAM_PX_SMAG1_JR_Gx_ID19(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID19_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID19_MASK)
15439 
15440 #define CAAM_PX_SMAG1_JR_Gx_ID20_MASK            (0x100000U)
15441 #define CAAM_PX_SMAG1_JR_Gx_ID20_SHIFT           (20U)
15442 #define CAAM_PX_SMAG1_JR_Gx_ID20(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID20_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID20_MASK)
15443 
15444 #define CAAM_PX_SMAG1_JR_Gx_ID21_MASK            (0x200000U)
15445 #define CAAM_PX_SMAG1_JR_Gx_ID21_SHIFT           (21U)
15446 #define CAAM_PX_SMAG1_JR_Gx_ID21(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID21_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID21_MASK)
15447 
15448 #define CAAM_PX_SMAG1_JR_Gx_ID22_MASK            (0x400000U)
15449 #define CAAM_PX_SMAG1_JR_Gx_ID22_SHIFT           (22U)
15450 #define CAAM_PX_SMAG1_JR_Gx_ID22(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID22_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID22_MASK)
15451 
15452 #define CAAM_PX_SMAG1_JR_Gx_ID23_MASK            (0x800000U)
15453 #define CAAM_PX_SMAG1_JR_Gx_ID23_SHIFT           (23U)
15454 #define CAAM_PX_SMAG1_JR_Gx_ID23(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID23_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID23_MASK)
15455 
15456 #define CAAM_PX_SMAG1_JR_Gx_ID24_MASK            (0x1000000U)
15457 #define CAAM_PX_SMAG1_JR_Gx_ID24_SHIFT           (24U)
15458 #define CAAM_PX_SMAG1_JR_Gx_ID24(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID24_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID24_MASK)
15459 
15460 #define CAAM_PX_SMAG1_JR_Gx_ID25_MASK            (0x2000000U)
15461 #define CAAM_PX_SMAG1_JR_Gx_ID25_SHIFT           (25U)
15462 #define CAAM_PX_SMAG1_JR_Gx_ID25(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID25_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID25_MASK)
15463 
15464 #define CAAM_PX_SMAG1_JR_Gx_ID26_MASK            (0x4000000U)
15465 #define CAAM_PX_SMAG1_JR_Gx_ID26_SHIFT           (26U)
15466 #define CAAM_PX_SMAG1_JR_Gx_ID26(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID26_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID26_MASK)
15467 
15468 #define CAAM_PX_SMAG1_JR_Gx_ID27_MASK            (0x8000000U)
15469 #define CAAM_PX_SMAG1_JR_Gx_ID27_SHIFT           (27U)
15470 #define CAAM_PX_SMAG1_JR_Gx_ID27(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID27_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID27_MASK)
15471 
15472 #define CAAM_PX_SMAG1_JR_Gx_ID28_MASK            (0x10000000U)
15473 #define CAAM_PX_SMAG1_JR_Gx_ID28_SHIFT           (28U)
15474 #define CAAM_PX_SMAG1_JR_Gx_ID28(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID28_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID28_MASK)
15475 
15476 #define CAAM_PX_SMAG1_JR_Gx_ID29_MASK            (0x20000000U)
15477 #define CAAM_PX_SMAG1_JR_Gx_ID29_SHIFT           (29U)
15478 #define CAAM_PX_SMAG1_JR_Gx_ID29(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID29_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID29_MASK)
15479 
15480 #define CAAM_PX_SMAG1_JR_Gx_ID30_MASK            (0x40000000U)
15481 #define CAAM_PX_SMAG1_JR_Gx_ID30_SHIFT           (30U)
15482 #define CAAM_PX_SMAG1_JR_Gx_ID30(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID30_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID30_MASK)
15483 
15484 #define CAAM_PX_SMAG1_JR_Gx_ID31_MASK            (0x80000000U)
15485 #define CAAM_PX_SMAG1_JR_Gx_ID31_SHIFT           (31U)
15486 #define CAAM_PX_SMAG1_JR_Gx_ID31(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID31_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID31_MASK)
15487 /*! @} */
15488 
15489 /* The count of CAAM_PX_SMAG1_JR */
15490 #define CAAM_PX_SMAG1_JR_COUNT                   (4U)
15491 
15492 /* The count of CAAM_PX_SMAG1_JR */
15493 #define CAAM_PX_SMAG1_JR_COUNT2                  (16U)
15494 
15495 /*! @name SMCR_JR - Secure Memory Command Register */
15496 /*! @{ */
15497 
15498 #define CAAM_SMCR_JR_CMD_MASK                    (0xFU)
15499 #define CAAM_SMCR_JR_CMD_SHIFT                   (0U)
15500 #define CAAM_SMCR_JR_CMD(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_CMD_SHIFT)) & CAAM_SMCR_JR_CMD_MASK)
15501 
15502 #define CAAM_SMCR_JR_PRTN_MASK                   (0xF00U)
15503 #define CAAM_SMCR_JR_PRTN_SHIFT                  (8U)
15504 #define CAAM_SMCR_JR_PRTN(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_PRTN_SHIFT)) & CAAM_SMCR_JR_PRTN_MASK)
15505 
15506 #define CAAM_SMCR_JR_PAGE_MASK                   (0xFFFF0000U)
15507 #define CAAM_SMCR_JR_PAGE_SHIFT                  (16U)
15508 #define CAAM_SMCR_JR_PAGE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_PAGE_SHIFT)) & CAAM_SMCR_JR_PAGE_MASK)
15509 /*! @} */
15510 
15511 /* The count of CAAM_SMCR_JR */
15512 #define CAAM_SMCR_JR_COUNT                       (4U)
15513 
15514 /*! @name SMCSR_JR - Secure Memory Command Status Register */
15515 /*! @{ */
15516 
15517 #define CAAM_SMCSR_JR_PRTN_MASK                  (0xFU)
15518 #define CAAM_SMCSR_JR_PRTN_SHIFT                 (0U)
15519 #define CAAM_SMCSR_JR_PRTN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PRTN_SHIFT)) & CAAM_SMCSR_JR_PRTN_MASK)
15520 
15521 #define CAAM_SMCSR_JR_PO_MASK                    (0xC0U)
15522 #define CAAM_SMCSR_JR_PO_SHIFT                   (6U)
15523 /*! PO
15524  *  0b00..Available; Unowned: The entity that issued the inquiry may allocate this page to a partition. No
15525  *        zeroization is needed since it has already been cleared, therefore no interrupt should be expected.
15526  *  0b01..Page does not exist in this version or is not initialized yet.
15527  *  0b10..Another entity owns the page. This page is unavailable to the issuer of the inquiry.
15528  *  0b11..Owned by the entity making the inquiry. The owner may de-allocate this page if its partition is not
15529  *        marked PSP. If the partition to which the page is allocated is designated as CSP, the page will be zeroized
15530  *        upon de-allocation.
15531  */
15532 #define CAAM_SMCSR_JR_PO(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PO_SHIFT)) & CAAM_SMCSR_JR_PO_MASK)
15533 
15534 #define CAAM_SMCSR_JR_AERR_MASK                  (0x3000U)
15535 #define CAAM_SMCSR_JR_AERR_SHIFT                 (12U)
15536 #define CAAM_SMCSR_JR_AERR(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_AERR_SHIFT)) & CAAM_SMCSR_JR_AERR_MASK)
15537 
15538 #define CAAM_SMCSR_JR_CERR_MASK                  (0xC000U)
15539 #define CAAM_SMCSR_JR_CERR_SHIFT                 (14U)
15540 /*! CERR
15541  *  0b00..No Error.
15542  *  0b01..Command has not yet completed.
15543  *  0b10..A security failure occurred.
15544  *  0b11..Command Overflow. Another command was issued by the same Job Ring owner before the owner's previous
15545  *        command completed. The additional command was ignored.
15546  */
15547 #define CAAM_SMCSR_JR_CERR(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_CERR_SHIFT)) & CAAM_SMCSR_JR_CERR_MASK)
15548 
15549 #define CAAM_SMCSR_JR_PAGE_MASK                  (0xFFF0000U)
15550 #define CAAM_SMCSR_JR_PAGE_SHIFT                 (16U)
15551 #define CAAM_SMCSR_JR_PAGE(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PAGE_SHIFT)) & CAAM_SMCSR_JR_PAGE_MASK)
15552 /*! @} */
15553 
15554 /* The count of CAAM_SMCSR_JR */
15555 #define CAAM_SMCSR_JR_COUNT                      (4U)
15556 
15557 /*! @name REIR0JR - Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3 */
15558 /*! @{ */
15559 
15560 #define CAAM_REIR0JR_TYPE_MASK                   (0x3000000U)
15561 #define CAAM_REIR0JR_TYPE_SHIFT                  (24U)
15562 #define CAAM_REIR0JR_TYPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0JR_TYPE_SHIFT)) & CAAM_REIR0JR_TYPE_MASK)
15563 
15564 #define CAAM_REIR0JR_MISS_MASK                   (0x80000000U)
15565 #define CAAM_REIR0JR_MISS_SHIFT                  (31U)
15566 #define CAAM_REIR0JR_MISS(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0JR_MISS_SHIFT)) & CAAM_REIR0JR_MISS_MASK)
15567 /*! @} */
15568 
15569 /* The count of CAAM_REIR0JR */
15570 #define CAAM_REIR0JR_COUNT                       (4U)
15571 
15572 /*! @name REIR2JR - Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3 */
15573 /*! @{ */
15574 
15575 #define CAAM_REIR2JR_ADDR_MASK                   (0xFFFFFFFFFU)
15576 #define CAAM_REIR2JR_ADDR_SHIFT                  (0U)
15577 #define CAAM_REIR2JR_ADDR(x)                     (((uint64_t)(((uint64_t)(x)) << CAAM_REIR2JR_ADDR_SHIFT)) & CAAM_REIR2JR_ADDR_MASK)
15578 /*! @} */
15579 
15580 /* The count of CAAM_REIR2JR */
15581 #define CAAM_REIR2JR_COUNT                       (4U)
15582 
15583 /*! @name REIR4JR - Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3 */
15584 /*! @{ */
15585 
15586 #define CAAM_REIR4JR_ICID_MASK                   (0x7FFU)
15587 #define CAAM_REIR4JR_ICID_SHIFT                  (0U)
15588 #define CAAM_REIR4JR_ICID(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_ICID_SHIFT)) & CAAM_REIR4JR_ICID_MASK)
15589 
15590 #define CAAM_REIR4JR_DID_MASK                    (0x7800U)
15591 #define CAAM_REIR4JR_DID_SHIFT                   (11U)
15592 #define CAAM_REIR4JR_DID(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_DID_SHIFT)) & CAAM_REIR4JR_DID_MASK)
15593 
15594 #define CAAM_REIR4JR_AXCACHE_MASK                (0xF0000U)
15595 #define CAAM_REIR4JR_AXCACHE_SHIFT               (16U)
15596 #define CAAM_REIR4JR_AXCACHE(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_AXCACHE_SHIFT)) & CAAM_REIR4JR_AXCACHE_MASK)
15597 
15598 #define CAAM_REIR4JR_AXPROT_MASK                 (0x700000U)
15599 #define CAAM_REIR4JR_AXPROT_SHIFT                (20U)
15600 #define CAAM_REIR4JR_AXPROT(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_AXPROT_SHIFT)) & CAAM_REIR4JR_AXPROT_MASK)
15601 
15602 #define CAAM_REIR4JR_RWB_MASK                    (0x800000U)
15603 #define CAAM_REIR4JR_RWB_SHIFT                   (23U)
15604 #define CAAM_REIR4JR_RWB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_RWB_SHIFT)) & CAAM_REIR4JR_RWB_MASK)
15605 
15606 #define CAAM_REIR4JR_ERR_MASK                    (0x30000000U)
15607 #define CAAM_REIR4JR_ERR_SHIFT                   (28U)
15608 #define CAAM_REIR4JR_ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_ERR_SHIFT)) & CAAM_REIR4JR_ERR_MASK)
15609 
15610 #define CAAM_REIR4JR_MIX_MASK                    (0xC0000000U)
15611 #define CAAM_REIR4JR_MIX_SHIFT                   (30U)
15612 #define CAAM_REIR4JR_MIX(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_MIX_SHIFT)) & CAAM_REIR4JR_MIX_MASK)
15613 /*! @} */
15614 
15615 /* The count of CAAM_REIR4JR */
15616 #define CAAM_REIR4JR_COUNT                       (4U)
15617 
15618 /*! @name REIR5JR - Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3 */
15619 /*! @{ */
15620 
15621 #define CAAM_REIR5JR_BID_MASK                    (0xF0000U)
15622 #define CAAM_REIR5JR_BID_SHIFT                   (16U)
15623 #define CAAM_REIR5JR_BID(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_BID_SHIFT)) & CAAM_REIR5JR_BID_MASK)
15624 
15625 #define CAAM_REIR5JR_BNDG_MASK                   (0x2000000U)
15626 #define CAAM_REIR5JR_BNDG_SHIFT                  (25U)
15627 #define CAAM_REIR5JR_BNDG(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_BNDG_SHIFT)) & CAAM_REIR5JR_BNDG_MASK)
15628 
15629 #define CAAM_REIR5JR_TDSC_MASK                   (0x4000000U)
15630 #define CAAM_REIR5JR_TDSC_SHIFT                  (26U)
15631 #define CAAM_REIR5JR_TDSC(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_TDSC_SHIFT)) & CAAM_REIR5JR_TDSC_MASK)
15632 
15633 #define CAAM_REIR5JR_KMOD_MASK                   (0x8000000U)
15634 #define CAAM_REIR5JR_KMOD_SHIFT                  (27U)
15635 #define CAAM_REIR5JR_KMOD(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_KMOD_SHIFT)) & CAAM_REIR5JR_KMOD_MASK)
15636 
15637 #define CAAM_REIR5JR_KEY_MASK                    (0x10000000U)
15638 #define CAAM_REIR5JR_KEY_SHIFT                   (28U)
15639 #define CAAM_REIR5JR_KEY(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_KEY_SHIFT)) & CAAM_REIR5JR_KEY_MASK)
15640 
15641 #define CAAM_REIR5JR_SMA_MASK                    (0x20000000U)
15642 #define CAAM_REIR5JR_SMA_SHIFT                   (29U)
15643 #define CAAM_REIR5JR_SMA(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_SMA_SHIFT)) & CAAM_REIR5JR_SMA_MASK)
15644 /*! @} */
15645 
15646 /* The count of CAAM_REIR5JR */
15647 #define CAAM_REIR5JR_COUNT                       (4U)
15648 
15649 /*! @name RSTA - RTIC Status Register */
15650 /*! @{ */
15651 
15652 #define CAAM_RSTA_BSY_MASK                       (0x1U)
15653 #define CAAM_RSTA_BSY_SHIFT                      (0U)
15654 /*! BSY
15655  *  0b0..RTIC Idle.
15656  *  0b1..RTIC Busy.
15657  */
15658 #define CAAM_RSTA_BSY(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_BSY_SHIFT)) & CAAM_RSTA_BSY_MASK)
15659 
15660 #define CAAM_RSTA_HD_MASK                        (0x2U)
15661 #define CAAM_RSTA_HD_SHIFT                       (1U)
15662 /*! HD
15663  *  0b0..Boot authentication disabled
15664  *  0b1..Authenticate code/generate reference hash value. This bit cannot be modified during run-time checking mode.
15665  */
15666 #define CAAM_RSTA_HD(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HD_SHIFT)) & CAAM_RSTA_HD_MASK)
15667 
15668 #define CAAM_RSTA_SV_MASK                        (0x4U)
15669 #define CAAM_RSTA_SV_SHIFT                       (2U)
15670 /*! SV
15671  *  0b0..Memory block contents authenticated.
15672  *  0b1..Memory block hash doesn't match reference value.
15673  */
15674 #define CAAM_RSTA_SV(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_SV_SHIFT)) & CAAM_RSTA_SV_MASK)
15675 
15676 #define CAAM_RSTA_HE_MASK                        (0x8U)
15677 #define CAAM_RSTA_HE_SHIFT                       (3U)
15678 /*! HE
15679  *  0b0..Memory block contents authenticated.
15680  *  0b1..Memory block hash doesn't match reference value.
15681  */
15682 #define CAAM_RSTA_HE(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HE_SHIFT)) & CAAM_RSTA_HE_MASK)
15683 
15684 #define CAAM_RSTA_MIS_MASK                       (0xF0U)
15685 #define CAAM_RSTA_MIS_SHIFT                      (4U)
15686 /*! MIS
15687  *  0b0000..Memory Block X is valid or state unknown
15688  *  0b0001..Memory Block X has been corrupted
15689  */
15690 #define CAAM_RSTA_MIS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_MIS_SHIFT)) & CAAM_RSTA_MIS_MASK)
15691 
15692 #define CAAM_RSTA_AE_MASK                        (0xF00U)
15693 #define CAAM_RSTA_AE_SHIFT                       (8U)
15694 /*! AE
15695  *  0b0000..All reads by RTIC were valid.
15696  *  0b0001..An illegal address was accessed by the RTIC
15697  */
15698 #define CAAM_RSTA_AE(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_AE_SHIFT)) & CAAM_RSTA_AE_MASK)
15699 
15700 #define CAAM_RSTA_WE_MASK                        (0x10000U)
15701 #define CAAM_RSTA_WE_SHIFT                       (16U)
15702 /*! WE
15703  *  0b0..No RTIC Watchdog timer error has occurred.
15704  *  0b1..RTIC Watchdog timer has expired prior to completing a round of hashing.
15705  */
15706 #define CAAM_RSTA_WE(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_WE_SHIFT)) & CAAM_RSTA_WE_MASK)
15707 
15708 #define CAAM_RSTA_ABH_MASK                       (0x20000U)
15709 #define CAAM_RSTA_ABH_SHIFT                      (17U)
15710 #define CAAM_RSTA_ABH(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_ABH_SHIFT)) & CAAM_RSTA_ABH_MASK)
15711 
15712 #define CAAM_RSTA_HOD_MASK                       (0x40000U)
15713 #define CAAM_RSTA_HOD_SHIFT                      (18U)
15714 #define CAAM_RSTA_HOD(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HOD_SHIFT)) & CAAM_RSTA_HOD_MASK)
15715 
15716 #define CAAM_RSTA_RTD_MASK                       (0x80000U)
15717 #define CAAM_RSTA_RTD_SHIFT                      (19U)
15718 #define CAAM_RSTA_RTD(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_RTD_SHIFT)) & CAAM_RSTA_RTD_MASK)
15719 
15720 #define CAAM_RSTA_CS_MASK                        (0x6000000U)
15721 #define CAAM_RSTA_CS_SHIFT                       (25U)
15722 /*! CS
15723  *  0b00..Idle State
15724  *  0b01..Single Hash State
15725  *  0b10..Run-time State
15726  *  0b11..Error State
15727  */
15728 #define CAAM_RSTA_CS(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_CS_SHIFT)) & CAAM_RSTA_CS_MASK)
15729 /*! @} */
15730 
15731 /*! @name RCMD - RTIC Command Register */
15732 /*! @{ */
15733 
15734 #define CAAM_RCMD_CINT_MASK                      (0x1U)
15735 #define CAAM_RCMD_CINT_SHIFT                     (0U)
15736 /*! CINT
15737  *  0b0..Do not clear interrupt
15738  *  0b1..Clear interrupt. This bit cannot be modified during run-time checking mode
15739  */
15740 #define CAAM_RCMD_CINT(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_CINT_SHIFT)) & CAAM_RCMD_CINT_MASK)
15741 
15742 #define CAAM_RCMD_HO_MASK                        (0x2U)
15743 #define CAAM_RCMD_HO_SHIFT                       (1U)
15744 /*! HO
15745  *  0b0..Boot authentication disabled
15746  *  0b1..Authenticate code/generate reference hash value. This bit cannot be modified during run-time checking mode.
15747  */
15748 #define CAAM_RCMD_HO(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_HO_SHIFT)) & CAAM_RCMD_HO_MASK)
15749 
15750 #define CAAM_RCMD_RTC_MASK                       (0x4U)
15751 #define CAAM_RCMD_RTC_SHIFT                      (2U)
15752 /*! RTC
15753  *  0b0..Run-time checking disabled
15754  *  0b1..Verify run-time memory blocks continually
15755  */
15756 #define CAAM_RCMD_RTC(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_RTC_SHIFT)) & CAAM_RCMD_RTC_MASK)
15757 
15758 #define CAAM_RCMD_RTD_MASK                       (0x8U)
15759 #define CAAM_RCMD_RTD_SHIFT                      (3U)
15760 /*! RTD
15761  *  0b0..Allow Run Time Mode
15762  *  0b1..Prevent Run Time Mode
15763  */
15764 #define CAAM_RCMD_RTD(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_RTD_SHIFT)) & CAAM_RCMD_RTD_MASK)
15765 /*! @} */
15766 
15767 /*! @name RCTL - RTIC Control Register */
15768 /*! @{ */
15769 
15770 #define CAAM_RCTL_IE_MASK                        (0x1U)
15771 #define CAAM_RCTL_IE_SHIFT                       (0U)
15772 /*! IE
15773  *  0b0..Interrupts disabled
15774  *  0b1..Interrupts enabled
15775  */
15776 #define CAAM_RCTL_IE(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_IE_SHIFT)) & CAAM_RCTL_IE_MASK)
15777 
15778 #define CAAM_RCTL_RREQS_MASK                     (0xEU)
15779 #define CAAM_RCTL_RREQS_SHIFT                    (1U)
15780 #define CAAM_RCTL_RREQS(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RREQS_SHIFT)) & CAAM_RCTL_RREQS_MASK)
15781 
15782 #define CAAM_RCTL_HOME_MASK                      (0xF0U)
15783 #define CAAM_RCTL_HOME_SHIFT                     (4U)
15784 #define CAAM_RCTL_HOME(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_HOME_SHIFT)) & CAAM_RCTL_HOME_MASK)
15785 
15786 #define CAAM_RCTL_RTME_MASK                      (0xF00U)
15787 #define CAAM_RCTL_RTME_SHIFT                     (8U)
15788 #define CAAM_RCTL_RTME(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RTME_SHIFT)) & CAAM_RCTL_RTME_MASK)
15789 
15790 #define CAAM_RCTL_RTMU_MASK                      (0xF000U)
15791 #define CAAM_RCTL_RTMU_SHIFT                     (12U)
15792 #define CAAM_RCTL_RTMU(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RTMU_SHIFT)) & CAAM_RCTL_RTMU_MASK)
15793 
15794 #define CAAM_RCTL_RALG_MASK                      (0xF0000U)
15795 #define CAAM_RCTL_RALG_SHIFT                     (16U)
15796 #define CAAM_RCTL_RALG(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RALG_SHIFT)) & CAAM_RCTL_RALG_MASK)
15797 
15798 #define CAAM_RCTL_RIDLE_MASK                     (0x100000U)
15799 #define CAAM_RCTL_RIDLE_SHIFT                    (20U)
15800 #define CAAM_RCTL_RIDLE(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RIDLE_SHIFT)) & CAAM_RCTL_RIDLE_MASK)
15801 /*! @} */
15802 
15803 /*! @name RTHR - RTIC Throttle Register */
15804 /*! @{ */
15805 
15806 #define CAAM_RTHR_RTHR_MASK                      (0xFFFFU)
15807 #define CAAM_RTHR_RTHR_SHIFT                     (0U)
15808 #define CAAM_RTHR_RTHR(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_RTHR_RTHR_SHIFT)) & CAAM_RTHR_RTHR_MASK)
15809 /*! @} */
15810 
15811 /*! @name RWDOG - RTIC Watchdog Timer */
15812 /*! @{ */
15813 
15814 #define CAAM_RWDOG_RWDOG_MASK                    (0xFFFFFFFFU)
15815 #define CAAM_RWDOG_RWDOG_SHIFT                   (0U)
15816 #define CAAM_RWDOG_RWDOG(x)                      (((uint64_t)(((uint64_t)(x)) << CAAM_RWDOG_RWDOG_SHIFT)) & CAAM_RWDOG_RWDOG_MASK)
15817 /*! @} */
15818 
15819 /*! @name REND - RTIC Endian Register */
15820 /*! @{ */
15821 
15822 #define CAAM_REND_REPO_MASK                      (0xFU)
15823 #define CAAM_REND_REPO_SHIFT                     (0U)
15824 /*! REPO
15825  *  0bxxx1..Byte Swap Memory Block A
15826  *  0bxx1x..Byte Swap Memory Block B
15827  *  0bx1xx..Byte Swap Memory Block C
15828  *  0b1xxx..Byte Swap Memory Block D
15829  */
15830 #define CAAM_REND_REPO(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REND_REPO_SHIFT)) & CAAM_REND_REPO_MASK)
15831 
15832 #define CAAM_REND_RBS_MASK                       (0xF0U)
15833 #define CAAM_REND_RBS_SHIFT                      (4U)
15834 /*! RBS
15835  *  0bxxx1..Byte Swap Memory Block A
15836  *  0bxx1x..Byte Swap Memory Block B
15837  *  0bx1xx..Byte Swap Memory Block C
15838  *  0b1xxx..Byte Swap Memory Block D
15839  */
15840 #define CAAM_REND_RBS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RBS_SHIFT)) & CAAM_REND_RBS_MASK)
15841 
15842 #define CAAM_REND_RHWS_MASK                      (0xF00U)
15843 #define CAAM_REND_RHWS_SHIFT                     (8U)
15844 /*! RHWS
15845  *  0bxxx1..Half-Word Swap Memory Block A
15846  *  0bxx1x..Half-Word Swap Memory Block B
15847  *  0bx1xx..Half-Word Swap Memory Block C
15848  *  0b1xxx..Half-Word Swap Memory Block D
15849  */
15850 #define CAAM_REND_RHWS(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RHWS_SHIFT)) & CAAM_REND_RHWS_MASK)
15851 
15852 #define CAAM_REND_RWS_MASK                       (0xF000U)
15853 #define CAAM_REND_RWS_SHIFT                      (12U)
15854 /*! RWS
15855  *  0bxxx1..Word Swap Memory Block A
15856  *  0bxx1x..Word Swap Memory Block B
15857  *  0bx1xx..Word Swap Memory Block C
15858  *  0b1xxx..Word Swap Memory Block D
15859  */
15860 #define CAAM_REND_RWS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RWS_SHIFT)) & CAAM_REND_RWS_MASK)
15861 /*! @} */
15862 
15863 /*! @name RMA - RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register */
15864 /*! @{ */
15865 
15866 #define CAAM_RMA_MEMBLKADDR_MASK                 (0xFFFFFFFFFU)
15867 #define CAAM_RMA_MEMBLKADDR_SHIFT                (0U)
15868 #define CAAM_RMA_MEMBLKADDR(x)                   (((uint64_t)(((uint64_t)(x)) << CAAM_RMA_MEMBLKADDR_SHIFT)) & CAAM_RMA_MEMBLKADDR_MASK)
15869 /*! @} */
15870 
15871 /* The count of CAAM_RMA */
15872 #define CAAM_RMA_COUNT                           (4U)
15873 
15874 /* The count of CAAM_RMA */
15875 #define CAAM_RMA_COUNT2                          (2U)
15876 
15877 /*! @name RML - RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register */
15878 /*! @{ */
15879 
15880 #define CAAM_RML_MEMBLKLEN_MASK                  (0xFFFFFFFFU)
15881 #define CAAM_RML_MEMBLKLEN_SHIFT                 (0U)
15882 #define CAAM_RML_MEMBLKLEN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_RML_MEMBLKLEN_SHIFT)) & CAAM_RML_MEMBLKLEN_MASK)
15883 /*! @} */
15884 
15885 /* The count of CAAM_RML */
15886 #define CAAM_RML_COUNT                           (4U)
15887 
15888 /* The count of CAAM_RML */
15889 #define CAAM_RML_COUNT2                          (2U)
15890 
15891 /*! @name RMD - RTIC Memory Block A Big Endian Hash Result Word 0..RTIC Memory Block D Little Endian Hash Result Word 31 */
15892 /*! @{ */
15893 
15894 #define CAAM_RMD_RTIC_Hash_Result_MASK           (0xFFFFFFFFU)
15895 #define CAAM_RMD_RTIC_Hash_Result_SHIFT          (0U)
15896 #define CAAM_RMD_RTIC_Hash_Result(x)             (((uint32_t)(((uint32_t)(x)) << CAAM_RMD_RTIC_Hash_Result_SHIFT)) & CAAM_RMD_RTIC_Hash_Result_MASK)
15897 /*! @} */
15898 
15899 /* The count of CAAM_RMD */
15900 #define CAAM_RMD_COUNT                           (4U)
15901 
15902 /* The count of CAAM_RMD */
15903 #define CAAM_RMD_COUNT2                          (2U)
15904 
15905 /* The count of CAAM_RMD */
15906 #define CAAM_RMD_COUNT3                          (32U)
15907 
15908 /*! @name REIR0RTIC - Recoverable Error Interrupt Record 0 for RTIC */
15909 /*! @{ */
15910 
15911 #define CAAM_REIR0RTIC_TYPE_MASK                 (0x3000000U)
15912 #define CAAM_REIR0RTIC_TYPE_SHIFT                (24U)
15913 #define CAAM_REIR0RTIC_TYPE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0RTIC_TYPE_SHIFT)) & CAAM_REIR0RTIC_TYPE_MASK)
15914 
15915 #define CAAM_REIR0RTIC_MISS_MASK                 (0x80000000U)
15916 #define CAAM_REIR0RTIC_MISS_SHIFT                (31U)
15917 #define CAAM_REIR0RTIC_MISS(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0RTIC_MISS_SHIFT)) & CAAM_REIR0RTIC_MISS_MASK)
15918 /*! @} */
15919 
15920 /*! @name REIR2RTIC - Recoverable Error Interrupt Record 2 for RTIC */
15921 /*! @{ */
15922 
15923 #define CAAM_REIR2RTIC_ADDR_MASK                 (0xFFFFFFFFFFFFFFFFU)
15924 #define CAAM_REIR2RTIC_ADDR_SHIFT                (0U)
15925 #define CAAM_REIR2RTIC_ADDR(x)                   (((uint64_t)(((uint64_t)(x)) << CAAM_REIR2RTIC_ADDR_SHIFT)) & CAAM_REIR2RTIC_ADDR_MASK)
15926 /*! @} */
15927 
15928 /*! @name REIR4RTIC - Recoverable Error Interrupt Record 4 for RTIC */
15929 /*! @{ */
15930 
15931 #define CAAM_REIR4RTIC_ICID_MASK                 (0x7FFU)
15932 #define CAAM_REIR4RTIC_ICID_SHIFT                (0U)
15933 #define CAAM_REIR4RTIC_ICID(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_ICID_SHIFT)) & CAAM_REIR4RTIC_ICID_MASK)
15934 
15935 #define CAAM_REIR4RTIC_DID_MASK                  (0x7800U)
15936 #define CAAM_REIR4RTIC_DID_SHIFT                 (11U)
15937 #define CAAM_REIR4RTIC_DID(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_DID_SHIFT)) & CAAM_REIR4RTIC_DID_MASK)
15938 
15939 #define CAAM_REIR4RTIC_AXCACHE_MASK              (0xF0000U)
15940 #define CAAM_REIR4RTIC_AXCACHE_SHIFT             (16U)
15941 #define CAAM_REIR4RTIC_AXCACHE(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_AXCACHE_SHIFT)) & CAAM_REIR4RTIC_AXCACHE_MASK)
15942 
15943 #define CAAM_REIR4RTIC_AXPROT_MASK               (0x700000U)
15944 #define CAAM_REIR4RTIC_AXPROT_SHIFT              (20U)
15945 #define CAAM_REIR4RTIC_AXPROT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_AXPROT_SHIFT)) & CAAM_REIR4RTIC_AXPROT_MASK)
15946 
15947 #define CAAM_REIR4RTIC_RWB_MASK                  (0x800000U)
15948 #define CAAM_REIR4RTIC_RWB_SHIFT                 (23U)
15949 #define CAAM_REIR4RTIC_RWB(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_RWB_SHIFT)) & CAAM_REIR4RTIC_RWB_MASK)
15950 
15951 #define CAAM_REIR4RTIC_ERR_MASK                  (0x30000000U)
15952 #define CAAM_REIR4RTIC_ERR_SHIFT                 (28U)
15953 #define CAAM_REIR4RTIC_ERR(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_ERR_SHIFT)) & CAAM_REIR4RTIC_ERR_MASK)
15954 
15955 #define CAAM_REIR4RTIC_MIX_MASK                  (0xC0000000U)
15956 #define CAAM_REIR4RTIC_MIX_SHIFT                 (30U)
15957 #define CAAM_REIR4RTIC_MIX(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_MIX_SHIFT)) & CAAM_REIR4RTIC_MIX_MASK)
15958 /*! @} */
15959 
15960 /*! @name REIR5RTIC - Recoverable Error Interrupt Record 5 for RTIC */
15961 /*! @{ */
15962 
15963 #define CAAM_REIR5RTIC_BID_MASK                  (0xF0000U)
15964 #define CAAM_REIR5RTIC_BID_SHIFT                 (16U)
15965 #define CAAM_REIR5RTIC_BID(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_BID_SHIFT)) & CAAM_REIR5RTIC_BID_MASK)
15966 
15967 #define CAAM_REIR5RTIC_SAFE_MASK                 (0x1000000U)
15968 #define CAAM_REIR5RTIC_SAFE_SHIFT                (24U)
15969 #define CAAM_REIR5RTIC_SAFE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_SAFE_SHIFT)) & CAAM_REIR5RTIC_SAFE_MASK)
15970 
15971 #define CAAM_REIR5RTIC_SMA_MASK                  (0x2000000U)
15972 #define CAAM_REIR5RTIC_SMA_SHIFT                 (25U)
15973 #define CAAM_REIR5RTIC_SMA(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_SMA_SHIFT)) & CAAM_REIR5RTIC_SMA_MASK)
15974 /*! @} */
15975 
15976 /*! @name CC1MR - CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms */
15977 /*! @{ */
15978 
15979 #define CAAM_CC1MR_ENC_MASK                      (0x1U)
15980 #define CAAM_CC1MR_ENC_SHIFT                     (0U)
15981 /*! ENC
15982  *  0b0..Decrypt.
15983  *  0b1..Encrypt.
15984  */
15985 #define CAAM_CC1MR_ENC(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ENC_SHIFT)) & CAAM_CC1MR_ENC_MASK)
15986 
15987 #define CAAM_CC1MR_ICV_TEST_MASK                 (0x2U)
15988 #define CAAM_CC1MR_ICV_TEST_SHIFT                (1U)
15989 #define CAAM_CC1MR_ICV_TEST(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ICV_TEST_SHIFT)) & CAAM_CC1MR_ICV_TEST_MASK)
15990 
15991 #define CAAM_CC1MR_AS_MASK                       (0xCU)
15992 #define CAAM_CC1MR_AS_SHIFT                      (2U)
15993 /*! AS
15994  *  0b00..Update
15995  *  0b01..Initialize
15996  *  0b10..Finalize
15997  *  0b11..Initialize/Finalize
15998  */
15999 #define CAAM_CC1MR_AS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_AS_SHIFT)) & CAAM_CC1MR_AS_MASK)
16000 
16001 #define CAAM_CC1MR_AAI_MASK                      (0x1FF0U)
16002 #define CAAM_CC1MR_AAI_SHIFT                     (4U)
16003 #define CAAM_CC1MR_AAI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_AAI_SHIFT)) & CAAM_CC1MR_AAI_MASK)
16004 
16005 #define CAAM_CC1MR_ALG_MASK                      (0xFF0000U)
16006 #define CAAM_CC1MR_ALG_SHIFT                     (16U)
16007 /*! ALG
16008  *  0b00010000..AES
16009  *  0b00100000..DES
16010  *  0b00100001..3DES
16011  *  0b01010000..RNG
16012  */
16013 #define CAAM_CC1MR_ALG(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ALG_SHIFT)) & CAAM_CC1MR_ALG_MASK)
16014 /*! @} */
16015 
16016 /* The count of CAAM_CC1MR */
16017 #define CAAM_CC1MR_COUNT                         (1U)
16018 
16019 /*! @name CC1MR_PK - CCB 0 Class 1 Mode Register Format for Public Key Algorithms */
16020 /*! @{ */
16021 
16022 #define CAAM_CC1MR_PK_PKHA_MODE_LS_MASK          (0xFFFU)
16023 #define CAAM_CC1MR_PK_PKHA_MODE_LS_SHIFT         (0U)
16024 #define CAAM_CC1MR_PK_PKHA_MODE_LS(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_PK_PKHA_MODE_LS_SHIFT)) & CAAM_CC1MR_PK_PKHA_MODE_LS_MASK)
16025 
16026 #define CAAM_CC1MR_PK_PKHA_MODE_MS_MASK          (0xF0000U)
16027 #define CAAM_CC1MR_PK_PKHA_MODE_MS_SHIFT         (16U)
16028 #define CAAM_CC1MR_PK_PKHA_MODE_MS(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_PK_PKHA_MODE_MS_SHIFT)) & CAAM_CC1MR_PK_PKHA_MODE_MS_MASK)
16029 /*! @} */
16030 
16031 /* The count of CAAM_CC1MR_PK */
16032 #define CAAM_CC1MR_PK_COUNT                      (1U)
16033 
16034 /*! @name CC1MR_RNG - CCB 0 Class 1 Mode Register Format for RNG4 */
16035 /*! @{ */
16036 
16037 #define CAAM_CC1MR_RNG_TST_MASK                  (0x1U)
16038 #define CAAM_CC1MR_RNG_TST_SHIFT                 (0U)
16039 #define CAAM_CC1MR_RNG_TST(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_TST_SHIFT)) & CAAM_CC1MR_RNG_TST_MASK)
16040 
16041 #define CAAM_CC1MR_RNG_PR_MASK                   (0x2U)
16042 #define CAAM_CC1MR_RNG_PR_SHIFT                  (1U)
16043 #define CAAM_CC1MR_RNG_PR(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_PR_SHIFT)) & CAAM_CC1MR_RNG_PR_MASK)
16044 
16045 #define CAAM_CC1MR_RNG_AS_MASK                   (0xCU)
16046 #define CAAM_CC1MR_RNG_AS_SHIFT                  (2U)
16047 #define CAAM_CC1MR_RNG_AS(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_AS_SHIFT)) & CAAM_CC1MR_RNG_AS_MASK)
16048 
16049 #define CAAM_CC1MR_RNG_SH_MASK                   (0x30U)
16050 #define CAAM_CC1MR_RNG_SH_SHIFT                  (4U)
16051 /*! SH
16052  *  0b00..State Handle 0
16053  *  0b01..State Handle 1
16054  *  0b10..Reserved
16055  *  0b11..Reserved
16056  */
16057 #define CAAM_CC1MR_RNG_SH(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_SH_SHIFT)) & CAAM_CC1MR_RNG_SH_MASK)
16058 
16059 #define CAAM_CC1MR_RNG_NZB_MASK                  (0x100U)
16060 #define CAAM_CC1MR_RNG_NZB_SHIFT                 (8U)
16061 /*! NZB
16062  *  0b0..Generate random data with all-zero bytes permitted.
16063  *  0b1..Generate random data without any all-zero bytes.
16064  */
16065 #define CAAM_CC1MR_RNG_NZB(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_NZB_SHIFT)) & CAAM_CC1MR_RNG_NZB_MASK)
16066 
16067 #define CAAM_CC1MR_RNG_OBP_MASK                  (0x200U)
16068 #define CAAM_CC1MR_RNG_OBP_SHIFT                 (9U)
16069 /*! OBP
16070  *  0b0..No odd byte parity.
16071  *  0b1..Generate random data with odd byte parity.
16072  */
16073 #define CAAM_CC1MR_RNG_OBP(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_OBP_SHIFT)) & CAAM_CC1MR_RNG_OBP_MASK)
16074 
16075 #define CAAM_CC1MR_RNG_PS_MASK                   (0x400U)
16076 #define CAAM_CC1MR_RNG_PS_SHIFT                  (10U)
16077 /*! PS
16078  *  0b0..No personalization string is included.
16079  *  0b1..A personalization string is included.
16080  */
16081 #define CAAM_CC1MR_RNG_PS(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_PS_SHIFT)) & CAAM_CC1MR_RNG_PS_MASK)
16082 
16083 #define CAAM_CC1MR_RNG_AI_MASK                   (0x800U)
16084 #define CAAM_CC1MR_RNG_AI_SHIFT                  (11U)
16085 /*! AI
16086  *  0b0..No additional entropy input has been provided.
16087  *  0b1..Additional entropy input has been provided.
16088  */
16089 #define CAAM_CC1MR_RNG_AI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_AI_SHIFT)) & CAAM_CC1MR_RNG_AI_MASK)
16090 
16091 #define CAAM_CC1MR_RNG_SK_MASK                   (0x1000U)
16092 #define CAAM_CC1MR_RNG_SK_SHIFT                  (12U)
16093 /*! SK
16094  *  0b0..The destination for the RNG data is specified by the FIFO STORE command.
16095  *  0b1..The RNG data will go to the JDKEKR, TDKEKR and DSKR.
16096  */
16097 #define CAAM_CC1MR_RNG_SK(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_SK_SHIFT)) & CAAM_CC1MR_RNG_SK_MASK)
16098 
16099 #define CAAM_CC1MR_RNG_ALG_MASK                  (0xFF0000U)
16100 #define CAAM_CC1MR_RNG_ALG_SHIFT                 (16U)
16101 /*! ALG
16102  *  0b01010000..RNG
16103  */
16104 #define CAAM_CC1MR_RNG_ALG(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_ALG_SHIFT)) & CAAM_CC1MR_RNG_ALG_MASK)
16105 /*! @} */
16106 
16107 /* The count of CAAM_CC1MR_RNG */
16108 #define CAAM_CC1MR_RNG_COUNT                     (1U)
16109 
16110 /*! @name CC1KSR - CCB 0 Class 1 Key Size Register */
16111 /*! @{ */
16112 
16113 #define CAAM_CC1KSR_C1KS_MASK                    (0x7FU)
16114 #define CAAM_CC1KSR_C1KS_SHIFT                   (0U)
16115 #define CAAM_CC1KSR_C1KS(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CC1KSR_C1KS_SHIFT)) & CAAM_CC1KSR_C1KS_MASK)
16116 /*! @} */
16117 
16118 /* The count of CAAM_CC1KSR */
16119 #define CAAM_CC1KSR_COUNT                        (1U)
16120 
16121 /*! @name CC1DSR - CCB 0 Class 1 Data Size Register */
16122 /*! @{ */
16123 
16124 #define CAAM_CC1DSR_C1DS_MASK                    (0xFFFFFFFFU)
16125 #define CAAM_CC1DSR_C1DS_SHIFT                   (0U)
16126 #define CAAM_CC1DSR_C1DS(x)                      (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_C1DS_SHIFT)) & CAAM_CC1DSR_C1DS_MASK)
16127 
16128 #define CAAM_CC1DSR_C1CY_MASK                    (0x100000000U)
16129 #define CAAM_CC1DSR_C1CY_SHIFT                   (32U)
16130 /*! C1CY
16131  *  0b0..No carry out of the C1 Data Size Reg.
16132  *  0b1..There was a carry out of the C1 Data Size Reg.
16133  */
16134 #define CAAM_CC1DSR_C1CY(x)                      (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_C1CY_SHIFT)) & CAAM_CC1DSR_C1CY_MASK)
16135 
16136 #define CAAM_CC1DSR_NUMBITS_MASK                 (0xE000000000000000U)
16137 #define CAAM_CC1DSR_NUMBITS_SHIFT                (61U)
16138 #define CAAM_CC1DSR_NUMBITS(x)                   (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_NUMBITS_SHIFT)) & CAAM_CC1DSR_NUMBITS_MASK)
16139 /*! @} */
16140 
16141 /* The count of CAAM_CC1DSR */
16142 #define CAAM_CC1DSR_COUNT                        (1U)
16143 
16144 /*! @name CC1ICVSR - CCB 0 Class 1 ICV Size Register */
16145 /*! @{ */
16146 
16147 #define CAAM_CC1ICVSR_C1ICVS_MASK                (0x1FU)
16148 #define CAAM_CC1ICVSR_C1ICVS_SHIFT               (0U)
16149 #define CAAM_CC1ICVSR_C1ICVS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CC1ICVSR_C1ICVS_SHIFT)) & CAAM_CC1ICVSR_C1ICVS_MASK)
16150 /*! @} */
16151 
16152 /* The count of CAAM_CC1ICVSR */
16153 #define CAAM_CC1ICVSR_COUNT                      (1U)
16154 
16155 /*! @name CCCTRL - CCB 0 CHA Control Register */
16156 /*! @{ */
16157 
16158 #define CAAM_CCCTRL_CCB_MASK                     (0x1U)
16159 #define CAAM_CCCTRL_CCB_SHIFT                    (0U)
16160 /*! CCB
16161  *  0b0..Do Not Reset
16162  *  0b1..Reset CCB
16163  */
16164 #define CAAM_CCCTRL_CCB(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_CCB_SHIFT)) & CAAM_CCCTRL_CCB_MASK)
16165 
16166 #define CAAM_CCCTRL_AES_MASK                     (0x2U)
16167 #define CAAM_CCCTRL_AES_SHIFT                    (1U)
16168 /*! AES
16169  *  0b0..Do Not Reset
16170  *  0b1..Reset AES Accelerator
16171  */
16172 #define CAAM_CCCTRL_AES(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_AES_SHIFT)) & CAAM_CCCTRL_AES_MASK)
16173 
16174 #define CAAM_CCCTRL_DES_MASK                     (0x4U)
16175 #define CAAM_CCCTRL_DES_SHIFT                    (2U)
16176 /*! DES
16177  *  0b0..Do Not Reset
16178  *  0b1..Reset DES Accelerator
16179  */
16180 #define CAAM_CCCTRL_DES(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_DES_SHIFT)) & CAAM_CCCTRL_DES_MASK)
16181 
16182 #define CAAM_CCCTRL_PK_MASK                      (0x40U)
16183 #define CAAM_CCCTRL_PK_SHIFT                     (6U)
16184 /*! PK
16185  *  0b0..Do Not Reset
16186  *  0b1..Reset Public Key Hardware Accelerator
16187  */
16188 #define CAAM_CCCTRL_PK(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_PK_SHIFT)) & CAAM_CCCTRL_PK_MASK)
16189 
16190 #define CAAM_CCCTRL_MD_MASK                      (0x80U)
16191 #define CAAM_CCCTRL_MD_SHIFT                     (7U)
16192 /*! MD
16193  *  0b0..Do Not Reset
16194  *  0b1..Reset Message Digest Hardware Accelerator
16195  */
16196 #define CAAM_CCCTRL_MD(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_MD_SHIFT)) & CAAM_CCCTRL_MD_MASK)
16197 
16198 #define CAAM_CCCTRL_CRC_MASK                     (0x100U)
16199 #define CAAM_CCCTRL_CRC_SHIFT                    (8U)
16200 /*! CRC
16201  *  0b0..Do Not Reset
16202  *  0b1..Reset CRC Accelerator
16203  */
16204 #define CAAM_CCCTRL_CRC(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_CRC_SHIFT)) & CAAM_CCCTRL_CRC_MASK)
16205 
16206 #define CAAM_CCCTRL_RNG_MASK                     (0x200U)
16207 #define CAAM_CCCTRL_RNG_SHIFT                    (9U)
16208 /*! RNG
16209  *  0b0..Do Not Reset
16210  *  0b1..Reset Random Number Generator Block.
16211  */
16212 #define CAAM_CCCTRL_RNG(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_RNG_SHIFT)) & CAAM_CCCTRL_RNG_MASK)
16213 
16214 #define CAAM_CCCTRL_UA0_MASK                     (0x10000U)
16215 #define CAAM_CCCTRL_UA0_SHIFT                    (16U)
16216 /*! UA0
16217  *  0b0..Don't unload the PKHA A0 Memory.
16218  *  0b1..Unload the PKHA A0 Memory into OFIFO.
16219  */
16220 #define CAAM_CCCTRL_UA0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA0_SHIFT)) & CAAM_CCCTRL_UA0_MASK)
16221 
16222 #define CAAM_CCCTRL_UA1_MASK                     (0x20000U)
16223 #define CAAM_CCCTRL_UA1_SHIFT                    (17U)
16224 /*! UA1
16225  *  0b0..Don't unload the PKHA A1 Memory.
16226  *  0b1..Unload the PKHA A1 Memory into OFIFO.
16227  */
16228 #define CAAM_CCCTRL_UA1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA1_SHIFT)) & CAAM_CCCTRL_UA1_MASK)
16229 
16230 #define CAAM_CCCTRL_UA2_MASK                     (0x40000U)
16231 #define CAAM_CCCTRL_UA2_SHIFT                    (18U)
16232 /*! UA2
16233  *  0b0..Don't unload the PKHA A2 Memory.
16234  *  0b1..Unload the PKHA A2 Memory into OFIFO.
16235  */
16236 #define CAAM_CCCTRL_UA2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA2_SHIFT)) & CAAM_CCCTRL_UA2_MASK)
16237 
16238 #define CAAM_CCCTRL_UA3_MASK                     (0x80000U)
16239 #define CAAM_CCCTRL_UA3_SHIFT                    (19U)
16240 /*! UA3
16241  *  0b0..Don't unload the PKHA A3 Memory.
16242  *  0b1..Unload the PKHA A3 Memory into OFIFO.
16243  */
16244 #define CAAM_CCCTRL_UA3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA3_SHIFT)) & CAAM_CCCTRL_UA3_MASK)
16245 
16246 #define CAAM_CCCTRL_UB0_MASK                     (0x100000U)
16247 #define CAAM_CCCTRL_UB0_SHIFT                    (20U)
16248 /*! UB0
16249  *  0b0..Don't unload the PKHA B0 Memory.
16250  *  0b1..Unload the PKHA B0 Memory into OFIFO.
16251  */
16252 #define CAAM_CCCTRL_UB0(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB0_SHIFT)) & CAAM_CCCTRL_UB0_MASK)
16253 
16254 #define CAAM_CCCTRL_UB1_MASK                     (0x200000U)
16255 #define CAAM_CCCTRL_UB1_SHIFT                    (21U)
16256 /*! UB1
16257  *  0b0..Don't unload the PKHA B1 Memory.
16258  *  0b1..Unload the PKHA B1 Memory into OFIFO.
16259  */
16260 #define CAAM_CCCTRL_UB1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB1_SHIFT)) & CAAM_CCCTRL_UB1_MASK)
16261 
16262 #define CAAM_CCCTRL_UB2_MASK                     (0x400000U)
16263 #define CAAM_CCCTRL_UB2_SHIFT                    (22U)
16264 /*! UB2
16265  *  0b0..Don't unload the PKHA B2 Memory.
16266  *  0b1..Unload the PKHA B2 Memory into OFIFO.
16267  */
16268 #define CAAM_CCCTRL_UB2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB2_SHIFT)) & CAAM_CCCTRL_UB2_MASK)
16269 
16270 #define CAAM_CCCTRL_UB3_MASK                     (0x800000U)
16271 #define CAAM_CCCTRL_UB3_SHIFT                    (23U)
16272 /*! UB3
16273  *  0b0..Don't unload the PKHA B3 Memory.
16274  *  0b1..Unload the PKHA B3 Memory into OFIFO.
16275  */
16276 #define CAAM_CCCTRL_UB3(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB3_SHIFT)) & CAAM_CCCTRL_UB3_MASK)
16277 
16278 #define CAAM_CCCTRL_UN_MASK                      (0x1000000U)
16279 #define CAAM_CCCTRL_UN_SHIFT                     (24U)
16280 /*! UN
16281  *  0b0..Don't unload the PKHA N Memory.
16282  *  0b1..Unload the PKHA N Memory into OFIFO.
16283  */
16284 #define CAAM_CCCTRL_UN(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UN_SHIFT)) & CAAM_CCCTRL_UN_MASK)
16285 
16286 #define CAAM_CCCTRL_UA_MASK                      (0x4000000U)
16287 #define CAAM_CCCTRL_UA_SHIFT                     (26U)
16288 /*! UA
16289  *  0b0..Don't unload the PKHA A Memory.
16290  *  0b1..Unload the PKHA A Memory into OFIFO.
16291  */
16292 #define CAAM_CCCTRL_UA(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA_SHIFT)) & CAAM_CCCTRL_UA_MASK)
16293 
16294 #define CAAM_CCCTRL_UB_MASK                      (0x8000000U)
16295 #define CAAM_CCCTRL_UB_SHIFT                     (27U)
16296 /*! UB
16297  *  0b0..Don't unload the PKHA B Memory.
16298  *  0b1..Unload the PKHA B Memory into OFIFO.
16299  */
16300 #define CAAM_CCCTRL_UB(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB_SHIFT)) & CAAM_CCCTRL_UB_MASK)
16301 /*! @} */
16302 
16303 /* The count of CAAM_CCCTRL */
16304 #define CAAM_CCCTRL_COUNT                        (1U)
16305 
16306 /*! @name CICTL - CCB 0 Interrupt Control Register */
16307 /*! @{ */
16308 
16309 #define CAAM_CICTL_ADI_MASK                      (0x2U)
16310 #define CAAM_CICTL_ADI_SHIFT                     (1U)
16311 #define CAAM_CICTL_ADI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_ADI_SHIFT)) & CAAM_CICTL_ADI_MASK)
16312 
16313 #define CAAM_CICTL_DDI_MASK                      (0x4U)
16314 #define CAAM_CICTL_DDI_SHIFT                     (2U)
16315 #define CAAM_CICTL_DDI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_DDI_SHIFT)) & CAAM_CICTL_DDI_MASK)
16316 
16317 #define CAAM_CICTL_PDI_MASK                      (0x40U)
16318 #define CAAM_CICTL_PDI_SHIFT                     (6U)
16319 #define CAAM_CICTL_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_PDI_SHIFT)) & CAAM_CICTL_PDI_MASK)
16320 
16321 #define CAAM_CICTL_MDI_MASK                      (0x80U)
16322 #define CAAM_CICTL_MDI_SHIFT                     (7U)
16323 #define CAAM_CICTL_MDI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_MDI_SHIFT)) & CAAM_CICTL_MDI_MASK)
16324 
16325 #define CAAM_CICTL_CDI_MASK                      (0x100U)
16326 #define CAAM_CICTL_CDI_SHIFT                     (8U)
16327 #define CAAM_CICTL_CDI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_CDI_SHIFT)) & CAAM_CICTL_CDI_MASK)
16328 
16329 #define CAAM_CICTL_RNDI_MASK                     (0x200U)
16330 #define CAAM_CICTL_RNDI_SHIFT                    (9U)
16331 #define CAAM_CICTL_RNDI(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_RNDI_SHIFT)) & CAAM_CICTL_RNDI_MASK)
16332 
16333 #define CAAM_CICTL_AEI_MASK                      (0x20000U)
16334 #define CAAM_CICTL_AEI_SHIFT                     (17U)
16335 /*! AEI
16336  *  0b0..No AESA error detected
16337  *  0b1..AESA error detected
16338  */
16339 #define CAAM_CICTL_AEI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_AEI_SHIFT)) & CAAM_CICTL_AEI_MASK)
16340 
16341 #define CAAM_CICTL_DEI_MASK                      (0x40000U)
16342 #define CAAM_CICTL_DEI_SHIFT                     (18U)
16343 /*! DEI
16344  *  0b0..No DESA error detected
16345  *  0b1..DESA error detected
16346  */
16347 #define CAAM_CICTL_DEI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_DEI_SHIFT)) & CAAM_CICTL_DEI_MASK)
16348 
16349 #define CAAM_CICTL_PEI_MASK                      (0x400000U)
16350 #define CAAM_CICTL_PEI_SHIFT                     (22U)
16351 /*! PEI
16352  *  0b0..No PKHA error detected
16353  *  0b1..PKHA error detected
16354  */
16355 #define CAAM_CICTL_PEI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_PEI_SHIFT)) & CAAM_CICTL_PEI_MASK)
16356 
16357 #define CAAM_CICTL_MEI_MASK                      (0x800000U)
16358 #define CAAM_CICTL_MEI_SHIFT                     (23U)
16359 /*! MEI
16360  *  0b0..No MDHA error detected
16361  *  0b1..MDHA error detected
16362  */
16363 #define CAAM_CICTL_MEI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_MEI_SHIFT)) & CAAM_CICTL_MEI_MASK)
16364 
16365 #define CAAM_CICTL_CEI_MASK                      (0x1000000U)
16366 #define CAAM_CICTL_CEI_SHIFT                     (24U)
16367 /*! CEI
16368  *  0b0..No CRCA error detected
16369  *  0b1..CRCA error detected
16370  */
16371 #define CAAM_CICTL_CEI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_CEI_SHIFT)) & CAAM_CICTL_CEI_MASK)
16372 
16373 #define CAAM_CICTL_RNEI_MASK                     (0x2000000U)
16374 #define CAAM_CICTL_RNEI_SHIFT                    (25U)
16375 /*! RNEI
16376  *  0b0..No RNG error detected
16377  *  0b1..RNG error detected
16378  */
16379 #define CAAM_CICTL_RNEI(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_RNEI_SHIFT)) & CAAM_CICTL_RNEI_MASK)
16380 /*! @} */
16381 
16382 /* The count of CAAM_CICTL */
16383 #define CAAM_CICTL_COUNT                         (1U)
16384 
16385 /*! @name CCWR - CCB 0 Clear Written Register */
16386 /*! @{ */
16387 
16388 #define CAAM_CCWR_C1M_MASK                       (0x1U)
16389 #define CAAM_CCWR_C1M_SHIFT                      (0U)
16390 /*! C1M
16391  *  0b0..Don't clear the Class 1 Mode Register.
16392  *  0b1..Clear the Class 1 Mode Register.
16393  */
16394 #define CAAM_CCWR_C1M(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1M_SHIFT)) & CAAM_CCWR_C1M_MASK)
16395 
16396 #define CAAM_CCWR_C1DS_MASK                      (0x4U)
16397 #define CAAM_CCWR_C1DS_SHIFT                     (2U)
16398 /*! C1DS
16399  *  0b0..Don't clear the Class 1 Data Size Register.
16400  *  0b1..Clear the Class 1 Data Size Register.
16401  */
16402 #define CAAM_CCWR_C1DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1DS_SHIFT)) & CAAM_CCWR_C1DS_MASK)
16403 
16404 #define CAAM_CCWR_C1ICV_MASK                     (0x8U)
16405 #define CAAM_CCWR_C1ICV_SHIFT                    (3U)
16406 /*! C1ICV
16407  *  0b0..Don't clear the Class 1 ICV Size Register.
16408  *  0b1..Clear the Class 1 ICV Size Register.
16409  */
16410 #define CAAM_CCWR_C1ICV(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1ICV_SHIFT)) & CAAM_CCWR_C1ICV_MASK)
16411 
16412 #define CAAM_CCWR_C1C_MASK                       (0x20U)
16413 #define CAAM_CCWR_C1C_SHIFT                      (5U)
16414 /*! C1C
16415  *  0b0..Don't clear the Class 1 Context Register.
16416  *  0b1..Clear the Class 1 Context Register.
16417  */
16418 #define CAAM_CCWR_C1C(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1C_SHIFT)) & CAAM_CCWR_C1C_MASK)
16419 
16420 #define CAAM_CCWR_C1K_MASK                       (0x40U)
16421 #define CAAM_CCWR_C1K_SHIFT                      (6U)
16422 /*! C1K
16423  *  0b0..Don't clear the Class 1 Key Register.
16424  *  0b1..Clear the Class 1 Key Register.
16425  */
16426 #define CAAM_CCWR_C1K(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1K_SHIFT)) & CAAM_CCWR_C1K_MASK)
16427 
16428 #define CAAM_CCWR_CPKA_MASK                      (0x1000U)
16429 #define CAAM_CCWR_CPKA_SHIFT                     (12U)
16430 /*! CPKA
16431  *  0b0..Don't clear the PKHA A Size Register.
16432  *  0b1..Clear the PKHA A Size Register.
16433  */
16434 #define CAAM_CCWR_CPKA(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKA_SHIFT)) & CAAM_CCWR_CPKA_MASK)
16435 
16436 #define CAAM_CCWR_CPKB_MASK                      (0x2000U)
16437 #define CAAM_CCWR_CPKB_SHIFT                     (13U)
16438 /*! CPKB
16439  *  0b0..Don't clear the PKHA B Size Register.
16440  *  0b1..Clear the PKHA B Size Register.
16441  */
16442 #define CAAM_CCWR_CPKB(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKB_SHIFT)) & CAAM_CCWR_CPKB_MASK)
16443 
16444 #define CAAM_CCWR_CPKN_MASK                      (0x4000U)
16445 #define CAAM_CCWR_CPKN_SHIFT                     (14U)
16446 /*! CPKN
16447  *  0b0..Don't clear the PKHA N Size Register.
16448  *  0b1..Clear the PKHA N Size Register.
16449  */
16450 #define CAAM_CCWR_CPKN(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKN_SHIFT)) & CAAM_CCWR_CPKN_MASK)
16451 
16452 #define CAAM_CCWR_CPKE_MASK                      (0x8000U)
16453 #define CAAM_CCWR_CPKE_SHIFT                     (15U)
16454 /*! CPKE
16455  *  0b0..Don't clear the PKHA E Size Register..
16456  *  0b1..Clear the PKHA E Size Register.
16457  */
16458 #define CAAM_CCWR_CPKE(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKE_SHIFT)) & CAAM_CCWR_CPKE_MASK)
16459 
16460 #define CAAM_CCWR_C2M_MASK                       (0x10000U)
16461 #define CAAM_CCWR_C2M_SHIFT                      (16U)
16462 /*! C2M
16463  *  0b0..Don't clear the Class 2 Mode Register.
16464  *  0b1..Clear the Class 2 Mode Register.
16465  */
16466 #define CAAM_CCWR_C2M(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2M_SHIFT)) & CAAM_CCWR_C2M_MASK)
16467 
16468 #define CAAM_CCWR_C2DS_MASK                      (0x40000U)
16469 #define CAAM_CCWR_C2DS_SHIFT                     (18U)
16470 /*! C2DS
16471  *  0b0..Don't clear the Class 2 Data Size Register.
16472  *  0b1..Clear the Class 2 Data Size Register.
16473  */
16474 #define CAAM_CCWR_C2DS(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2DS_SHIFT)) & CAAM_CCWR_C2DS_MASK)
16475 
16476 #define CAAM_CCWR_C2C_MASK                       (0x200000U)
16477 #define CAAM_CCWR_C2C_SHIFT                      (21U)
16478 /*! C2C
16479  *  0b0..Don't clear the Class 2 Context Register.
16480  *  0b1..Clear the Class 2 Context Register.
16481  */
16482 #define CAAM_CCWR_C2C(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2C_SHIFT)) & CAAM_CCWR_C2C_MASK)
16483 
16484 #define CAAM_CCWR_C2K_MASK                       (0x400000U)
16485 #define CAAM_CCWR_C2K_SHIFT                      (22U)
16486 /*! C2K
16487  *  0b0..Don't clear the Class 2 Key Register.
16488  *  0b1..Clear the Class 2 Key Register.
16489  */
16490 #define CAAM_CCWR_C2K(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2K_SHIFT)) & CAAM_CCWR_C2K_MASK)
16491 
16492 #define CAAM_CCWR_CDS_MASK                       (0x2000000U)
16493 #define CAAM_CCWR_CDS_SHIFT                      (25U)
16494 /*! CDS
16495  *  0b0..Don't clear the shared descriptor signal.
16496  *  0b1..Clear the shared descriptor signal.
16497  */
16498 #define CAAM_CCWR_CDS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CDS_SHIFT)) & CAAM_CCWR_CDS_MASK)
16499 
16500 #define CAAM_CCWR_C2D_MASK                       (0x4000000U)
16501 #define CAAM_CCWR_C2D_SHIFT                      (26U)
16502 /*! C2D
16503  *  0b0..Don't clear the Class 2 done interrrupt.
16504  *  0b1..Clear the Class 2 done interrrupt.
16505  */
16506 #define CAAM_CCWR_C2D(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2D_SHIFT)) & CAAM_CCWR_C2D_MASK)
16507 
16508 #define CAAM_CCWR_C1D_MASK                       (0x8000000U)
16509 #define CAAM_CCWR_C1D_SHIFT                      (27U)
16510 /*! C1D
16511  *  0b0..Don't clear the Class 1 done interrrupt.
16512  *  0b1..Clear the Class 1 done interrrupt.
16513  */
16514 #define CAAM_CCWR_C1D(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1D_SHIFT)) & CAAM_CCWR_C1D_MASK)
16515 
16516 #define CAAM_CCWR_C2RST_MASK                     (0x10000000U)
16517 #define CAAM_CCWR_C2RST_SHIFT                    (28U)
16518 /*! C2RST
16519  *  0b0..Don't reset the Class 2 CHA.
16520  *  0b1..Reset the Class 2 CHA.
16521  */
16522 #define CAAM_CCWR_C2RST(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2RST_SHIFT)) & CAAM_CCWR_C2RST_MASK)
16523 
16524 #define CAAM_CCWR_C1RST_MASK                     (0x20000000U)
16525 #define CAAM_CCWR_C1RST_SHIFT                    (29U)
16526 /*! C1RST
16527  *  0b0..Don't reset the Class 1 CHA.
16528  *  0b1..Reset the Class 1 CHA.
16529  */
16530 #define CAAM_CCWR_C1RST(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1RST_SHIFT)) & CAAM_CCWR_C1RST_MASK)
16531 
16532 #define CAAM_CCWR_COF_MASK                       (0x40000000U)
16533 #define CAAM_CCWR_COF_SHIFT                      (30U)
16534 /*! COF
16535  *  0b0..Don't clear the OFIFO.
16536  *  0b1..Clear the OFIFO.
16537  */
16538 #define CAAM_CCWR_COF(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_COF_SHIFT)) & CAAM_CCWR_COF_MASK)
16539 
16540 #define CAAM_CCWR_CIF_MASK                       (0x80000000U)
16541 #define CAAM_CCWR_CIF_SHIFT                      (31U)
16542 /*! CIF
16543  *  0b0..Don't clear the IFIFO.
16544  *  0b1..Clear the IFIFO.
16545  */
16546 #define CAAM_CCWR_CIF(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CIF_SHIFT)) & CAAM_CCWR_CIF_MASK)
16547 /*! @} */
16548 
16549 /* The count of CAAM_CCWR */
16550 #define CAAM_CCWR_COUNT                          (1U)
16551 
16552 /*! @name CCSTA_MS - CCB 0 Status and Error Register, most-significant half */
16553 /*! @{ */
16554 
16555 #define CAAM_CCSTA_MS_ERRID1_MASK                (0xFU)
16556 #define CAAM_CCSTA_MS_ERRID1_SHIFT               (0U)
16557 /*! ERRID1
16558  *  0b0001..Mode Error
16559  *  0b0010..Data Size Error, including PKHA N Memory Size Error
16560  *  0b0011..Key Size Error, including PKHA E Memory Size Error
16561  *  0b0100..PKHA A Memory Size Error
16562  *  0b0101..PKHA B Memory Size Error
16563  *  0b0110..Data Arrived out of Sequence Error
16564  *  0b0111..PKHA Divide by Zero Error
16565  *  0b1000..PKHA Modulus Even Error
16566  *  0b1001..DES Key Parity Error
16567  *  0b1010..ICV Check Failed
16568  *  0b1011..Internal Hardware Failure
16569  *  0b1100..CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and
16570  *          AAD provided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.)
16571  *  0b1101..Class 1 CHA is not reset
16572  *  0b1110..Invalid CHA combination was selected
16573  *  0b1111..Invalid CHA Selected
16574  */
16575 #define CAAM_CCSTA_MS_ERRID1(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_ERRID1_SHIFT)) & CAAM_CCSTA_MS_ERRID1_MASK)
16576 
16577 #define CAAM_CCSTA_MS_CL1_MASK                   (0xF000U)
16578 #define CAAM_CCSTA_MS_CL1_SHIFT                  (12U)
16579 /*! CL1
16580  *  0b0001..AES
16581  *  0b0010..DES
16582  *  0b0101..RNG
16583  *  0b1000..Public Key
16584  */
16585 #define CAAM_CCSTA_MS_CL1(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_CL1_SHIFT)) & CAAM_CCSTA_MS_CL1_MASK)
16586 
16587 #define CAAM_CCSTA_MS_ERRID2_MASK                (0xF0000U)
16588 #define CAAM_CCSTA_MS_ERRID2_SHIFT               (16U)
16589 /*! ERRID2
16590  *  0b0001..Mode Error
16591  *  0b0010..Data Size Error
16592  *  0b0011..Key Size Error
16593  *  0b0110..Data Arrived out of Sequence Error
16594  *  0b1010..ICV Check Failed
16595  *  0b1011..Internal Hardware Failure
16596  *  0b1110..Invalid CHA combination was selected.
16597  *  0b1111..Invalid CHA Selected
16598  */
16599 #define CAAM_CCSTA_MS_ERRID2(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_ERRID2_SHIFT)) & CAAM_CCSTA_MS_ERRID2_MASK)
16600 
16601 #define CAAM_CCSTA_MS_CL2_MASK                   (0xF0000000U)
16602 #define CAAM_CCSTA_MS_CL2_SHIFT                  (28U)
16603 /*! CL2
16604  *  0b0100..MD5, SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 and SHA-512/224, SHA-512/256
16605  *  0b1001..CRC
16606  */
16607 #define CAAM_CCSTA_MS_CL2(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_CL2_SHIFT)) & CAAM_CCSTA_MS_CL2_MASK)
16608 /*! @} */
16609 
16610 /* The count of CAAM_CCSTA_MS */
16611 #define CAAM_CCSTA_MS_COUNT                      (1U)
16612 
16613 /*! @name CCSTA_LS - CCB 0 Status and Error Register, least-significant half */
16614 /*! @{ */
16615 
16616 #define CAAM_CCSTA_LS_AB_MASK                    (0x2U)
16617 #define CAAM_CCSTA_LS_AB_SHIFT                   (1U)
16618 /*! AB
16619  *  0b0..AESA Idle
16620  *  0b1..AESA Busy
16621  */
16622 #define CAAM_CCSTA_LS_AB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_AB_SHIFT)) & CAAM_CCSTA_LS_AB_MASK)
16623 
16624 #define CAAM_CCSTA_LS_DB_MASK                    (0x4U)
16625 #define CAAM_CCSTA_LS_DB_SHIFT                   (2U)
16626 /*! DB
16627  *  0b0..DESA Idle
16628  *  0b1..DESA Busy
16629  */
16630 #define CAAM_CCSTA_LS_DB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_DB_SHIFT)) & CAAM_CCSTA_LS_DB_MASK)
16631 
16632 #define CAAM_CCSTA_LS_PB_MASK                    (0x40U)
16633 #define CAAM_CCSTA_LS_PB_SHIFT                   (6U)
16634 /*! PB
16635  *  0b0..PKHA Idle
16636  *  0b1..PKHA Busy
16637  */
16638 #define CAAM_CCSTA_LS_PB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PB_SHIFT)) & CAAM_CCSTA_LS_PB_MASK)
16639 
16640 #define CAAM_CCSTA_LS_MB_MASK                    (0x80U)
16641 #define CAAM_CCSTA_LS_MB_SHIFT                   (7U)
16642 /*! MB
16643  *  0b0..MDHA Idle
16644  *  0b1..MDHA Busy
16645  */
16646 #define CAAM_CCSTA_LS_MB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_MB_SHIFT)) & CAAM_CCSTA_LS_MB_MASK)
16647 
16648 #define CAAM_CCSTA_LS_CB_MASK                    (0x100U)
16649 #define CAAM_CCSTA_LS_CB_SHIFT                   (8U)
16650 /*! CB
16651  *  0b0..CRCA Idle
16652  *  0b1..CRCA Busy
16653  */
16654 #define CAAM_CCSTA_LS_CB(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_CB_SHIFT)) & CAAM_CCSTA_LS_CB_MASK)
16655 
16656 #define CAAM_CCSTA_LS_RNB_MASK                   (0x200U)
16657 #define CAAM_CCSTA_LS_RNB_SHIFT                  (9U)
16658 /*! RNB
16659  *  0b0..RNG Idle
16660  *  0b1..RNG Busy
16661  */
16662 #define CAAM_CCSTA_LS_RNB(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_RNB_SHIFT)) & CAAM_CCSTA_LS_RNB_MASK)
16663 
16664 #define CAAM_CCSTA_LS_PDI_MASK                   (0x10000U)
16665 #define CAAM_CCSTA_LS_PDI_SHIFT                  (16U)
16666 /*! PDI
16667  *  0b0..Not Done
16668  *  0b1..Done Interrupt
16669  */
16670 #define CAAM_CCSTA_LS_PDI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PDI_SHIFT)) & CAAM_CCSTA_LS_PDI_MASK)
16671 
16672 #define CAAM_CCSTA_LS_SDI_MASK                   (0x20000U)
16673 #define CAAM_CCSTA_LS_SDI_SHIFT                  (17U)
16674 /*! SDI
16675  *  0b0..Not Done
16676  *  0b1..Done Interrupt
16677  */
16678 #define CAAM_CCSTA_LS_SDI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_SDI_SHIFT)) & CAAM_CCSTA_LS_SDI_MASK)
16679 
16680 #define CAAM_CCSTA_LS_PEI_MASK                   (0x100000U)
16681 #define CAAM_CCSTA_LS_PEI_SHIFT                  (20U)
16682 /*! PEI
16683  *  0b0..No Error
16684  *  0b1..Error Interrupt
16685  */
16686 #define CAAM_CCSTA_LS_PEI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PEI_SHIFT)) & CAAM_CCSTA_LS_PEI_MASK)
16687 
16688 #define CAAM_CCSTA_LS_SEI_MASK                   (0x200000U)
16689 #define CAAM_CCSTA_LS_SEI_SHIFT                  (21U)
16690 /*! SEI
16691  *  0b0..No Error
16692  *  0b1..Error Interrupt
16693  */
16694 #define CAAM_CCSTA_LS_SEI(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_SEI_SHIFT)) & CAAM_CCSTA_LS_SEI_MASK)
16695 
16696 #define CAAM_CCSTA_LS_PRM_MASK                   (0x10000000U)
16697 #define CAAM_CCSTA_LS_PRM_SHIFT                  (28U)
16698 /*! PRM
16699  *  0b0..The given number is NOT prime.
16700  *  0b1..The given number is probably prime.
16701  */
16702 #define CAAM_CCSTA_LS_PRM(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PRM_SHIFT)) & CAAM_CCSTA_LS_PRM_MASK)
16703 
16704 #define CAAM_CCSTA_LS_GCD_MASK                   (0x20000000U)
16705 #define CAAM_CCSTA_LS_GCD_SHIFT                  (29U)
16706 /*! GCD
16707  *  0b0..The greatest common divisor of two numbers is NOT one.
16708  *  0b1..The greatest common divisor of two numbers is one.
16709  */
16710 #define CAAM_CCSTA_LS_GCD(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_GCD_SHIFT)) & CAAM_CCSTA_LS_GCD_MASK)
16711 
16712 #define CAAM_CCSTA_LS_PIZ_MASK                   (0x40000000U)
16713 #define CAAM_CCSTA_LS_PIZ_SHIFT                  (30U)
16714 /*! PIZ
16715  *  0b0..The result of a Public Key operation is not zero.
16716  *  0b1..The result of a Public Key operation is zero.
16717  */
16718 #define CAAM_CCSTA_LS_PIZ(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PIZ_SHIFT)) & CAAM_CCSTA_LS_PIZ_MASK)
16719 /*! @} */
16720 
16721 /* The count of CAAM_CCSTA_LS */
16722 #define CAAM_CCSTA_LS_COUNT                      (1U)
16723 
16724 /*! @name CC1AADSZR - CCB 0 Class 1 AAD Size Register */
16725 /*! @{ */
16726 
16727 #define CAAM_CC1AADSZR_AASZ_MASK                 (0xFU)
16728 #define CAAM_CC1AADSZR_AASZ_SHIFT                (0U)
16729 #define CAAM_CC1AADSZR_AASZ(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CC1AADSZR_AASZ_SHIFT)) & CAAM_CC1AADSZR_AASZ_MASK)
16730 /*! @} */
16731 
16732 /* The count of CAAM_CC1AADSZR */
16733 #define CAAM_CC1AADSZR_COUNT                     (1U)
16734 
16735 /*! @name CC1IVSZR - CCB 0 Class 1 IV Size Register */
16736 /*! @{ */
16737 
16738 #define CAAM_CC1IVSZR_IVSZ_MASK                  (0xFU)
16739 #define CAAM_CC1IVSZR_IVSZ_SHIFT                 (0U)
16740 #define CAAM_CC1IVSZR_IVSZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1IVSZR_IVSZ_SHIFT)) & CAAM_CC1IVSZR_IVSZ_MASK)
16741 /*! @} */
16742 
16743 /* The count of CAAM_CC1IVSZR */
16744 #define CAAM_CC1IVSZR_COUNT                      (1U)
16745 
16746 /*! @name CPKASZR - PKHA A Size Register */
16747 /*! @{ */
16748 
16749 #define CAAM_CPKASZR_PKASZ_MASK                  (0x3FFU)
16750 #define CAAM_CPKASZR_PKASZ_SHIFT                 (0U)
16751 #define CAAM_CPKASZR_PKASZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CPKASZR_PKASZ_SHIFT)) & CAAM_CPKASZR_PKASZ_MASK)
16752 /*! @} */
16753 
16754 /* The count of CAAM_CPKASZR */
16755 #define CAAM_CPKASZR_COUNT                       (1U)
16756 
16757 /*! @name CPKBSZR - PKHA B Size Register */
16758 /*! @{ */
16759 
16760 #define CAAM_CPKBSZR_PKBSZ_MASK                  (0x3FFU)
16761 #define CAAM_CPKBSZR_PKBSZ_SHIFT                 (0U)
16762 #define CAAM_CPKBSZR_PKBSZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CPKBSZR_PKBSZ_SHIFT)) & CAAM_CPKBSZR_PKBSZ_MASK)
16763 /*! @} */
16764 
16765 /* The count of CAAM_CPKBSZR */
16766 #define CAAM_CPKBSZR_COUNT                       (1U)
16767 
16768 /*! @name CPKNSZR - PKHA N Size Register */
16769 /*! @{ */
16770 
16771 #define CAAM_CPKNSZR_PKNSZ_MASK                  (0x3FFU)
16772 #define CAAM_CPKNSZR_PKNSZ_SHIFT                 (0U)
16773 #define CAAM_CPKNSZR_PKNSZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CPKNSZR_PKNSZ_SHIFT)) & CAAM_CPKNSZR_PKNSZ_MASK)
16774 /*! @} */
16775 
16776 /* The count of CAAM_CPKNSZR */
16777 #define CAAM_CPKNSZR_COUNT                       (1U)
16778 
16779 /*! @name CPKESZR - PKHA E Size Register */
16780 /*! @{ */
16781 
16782 #define CAAM_CPKESZR_PKESZ_MASK                  (0x3FFU)
16783 #define CAAM_CPKESZR_PKESZ_SHIFT                 (0U)
16784 #define CAAM_CPKESZR_PKESZ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CPKESZR_PKESZ_SHIFT)) & CAAM_CPKESZR_PKESZ_MASK)
16785 /*! @} */
16786 
16787 /* The count of CAAM_CPKESZR */
16788 #define CAAM_CPKESZR_COUNT                       (1U)
16789 
16790 /*! @name CC1CTXR - CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15 */
16791 /*! @{ */
16792 
16793 #define CAAM_CC1CTXR_C1CTX_MASK                  (0xFFFFFFFFU)
16794 #define CAAM_CC1CTXR_C1CTX_SHIFT                 (0U)
16795 #define CAAM_CC1CTXR_C1CTX(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC1CTXR_C1CTX_SHIFT)) & CAAM_CC1CTXR_C1CTX_MASK)
16796 /*! @} */
16797 
16798 /* The count of CAAM_CC1CTXR */
16799 #define CAAM_CC1CTXR_COUNT                       (1U)
16800 
16801 /* The count of CAAM_CC1CTXR */
16802 #define CAAM_CC1CTXR_COUNT2                      (16U)
16803 
16804 /*! @name CC1KR - CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7 */
16805 /*! @{ */
16806 
16807 #define CAAM_CC1KR_C1KEY_MASK                    (0xFFFFFFFFU)
16808 #define CAAM_CC1KR_C1KEY_SHIFT                   (0U)
16809 #define CAAM_CC1KR_C1KEY(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CC1KR_C1KEY_SHIFT)) & CAAM_CC1KR_C1KEY_MASK)
16810 /*! @} */
16811 
16812 /* The count of CAAM_CC1KR */
16813 #define CAAM_CC1KR_COUNT                         (1U)
16814 
16815 /* The count of CAAM_CC1KR */
16816 #define CAAM_CC1KR_COUNT2                        (8U)
16817 
16818 /*! @name CC2MR - CCB 0 Class 2 Mode Register */
16819 /*! @{ */
16820 
16821 #define CAAM_CC2MR_AP_MASK                       (0x1U)
16822 #define CAAM_CC2MR_AP_SHIFT                      (0U)
16823 /*! AP
16824  *  0b0..Authenticate
16825  *  0b1..Protect
16826  */
16827 #define CAAM_CC2MR_AP(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AP_SHIFT)) & CAAM_CC2MR_AP_MASK)
16828 
16829 #define CAAM_CC2MR_ICV_MASK                      (0x2U)
16830 #define CAAM_CC2MR_ICV_SHIFT                     (1U)
16831 /*! ICV
16832  *  0b0..Don't compare the calculated ICV against a received ICV.
16833  *  0b1..Compare the calculated ICV against a received ICV.
16834  */
16835 #define CAAM_CC2MR_ICV(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_ICV_SHIFT)) & CAAM_CC2MR_ICV_MASK)
16836 
16837 #define CAAM_CC2MR_AS_MASK                       (0xCU)
16838 #define CAAM_CC2MR_AS_SHIFT                      (2U)
16839 /*! AS
16840  *  0b00..Update.
16841  *  0b01..Initialize.
16842  *  0b10..Finalize.
16843  *  0b11..Initialize/Finalize.
16844  */
16845 #define CAAM_CC2MR_AS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AS_SHIFT)) & CAAM_CC2MR_AS_MASK)
16846 
16847 #define CAAM_CC2MR_AAI_MASK                      (0x1FF0U)
16848 #define CAAM_CC2MR_AAI_SHIFT                     (4U)
16849 #define CAAM_CC2MR_AAI(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AAI_SHIFT)) & CAAM_CC2MR_AAI_MASK)
16850 
16851 #define CAAM_CC2MR_ALG_MASK                      (0xFF0000U)
16852 #define CAAM_CC2MR_ALG_SHIFT                     (16U)
16853 /*! ALG
16854  *  0b01000000..MD5
16855  *  0b01000001..SHA-1
16856  *  0b01000010..SHA-224
16857  *  0b01000011..SHA-256
16858  *  0b01000100..SHA-384
16859  *  0b01000101..SHA-512
16860  *  0b01000110..SHA-512/224
16861  *  0b01000111..SHA-512/256
16862  *  0b10010000..CRC
16863  */
16864 #define CAAM_CC2MR_ALG(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_ALG_SHIFT)) & CAAM_CC2MR_ALG_MASK)
16865 /*! @} */
16866 
16867 /* The count of CAAM_CC2MR */
16868 #define CAAM_CC2MR_COUNT                         (1U)
16869 
16870 /*! @name CC2KSR - CCB 0 Class 2 Key Size Register */
16871 /*! @{ */
16872 
16873 #define CAAM_CC2KSR_C2KS_MASK                    (0xFFU)
16874 #define CAAM_CC2KSR_C2KS_SHIFT                   (0U)
16875 #define CAAM_CC2KSR_C2KS(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CC2KSR_C2KS_SHIFT)) & CAAM_CC2KSR_C2KS_MASK)
16876 /*! @} */
16877 
16878 /* The count of CAAM_CC2KSR */
16879 #define CAAM_CC2KSR_COUNT                        (1U)
16880 
16881 /*! @name CC2DSR - CCB 0 Class 2 Data Size Register */
16882 /*! @{ */
16883 
16884 #define CAAM_CC2DSR_C2DS_MASK                    (0xFFFFFFFFU)
16885 #define CAAM_CC2DSR_C2DS_SHIFT                   (0U)
16886 #define CAAM_CC2DSR_C2DS(x)                      (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_C2DS_SHIFT)) & CAAM_CC2DSR_C2DS_MASK)
16887 
16888 #define CAAM_CC2DSR_C2CY_MASK                    (0x100000000U)
16889 #define CAAM_CC2DSR_C2CY_SHIFT                   (32U)
16890 /*! C2CY
16891  *  0b0..A write to the Class 2 Data Size Register did not cause a carry.
16892  *  0b1..A write to the Class 2 Data Size Register caused a carry.
16893  */
16894 #define CAAM_CC2DSR_C2CY(x)                      (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_C2CY_SHIFT)) & CAAM_CC2DSR_C2CY_MASK)
16895 
16896 #define CAAM_CC2DSR_NUMBITS_MASK                 (0xE000000000000000U)
16897 #define CAAM_CC2DSR_NUMBITS_SHIFT                (61U)
16898 #define CAAM_CC2DSR_NUMBITS(x)                   (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_NUMBITS_SHIFT)) & CAAM_CC2DSR_NUMBITS_MASK)
16899 /*! @} */
16900 
16901 /* The count of CAAM_CC2DSR */
16902 #define CAAM_CC2DSR_COUNT                        (1U)
16903 
16904 /*! @name CC2ICVSZR - CCB 0 Class 2 ICV Size Register */
16905 /*! @{ */
16906 
16907 #define CAAM_CC2ICVSZR_ICVSZ_MASK                (0xFU)
16908 #define CAAM_CC2ICVSZR_ICVSZ_SHIFT               (0U)
16909 #define CAAM_CC2ICVSZR_ICVSZ(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_CC2ICVSZR_ICVSZ_SHIFT)) & CAAM_CC2ICVSZR_ICVSZ_MASK)
16910 /*! @} */
16911 
16912 /* The count of CAAM_CC2ICVSZR */
16913 #define CAAM_CC2ICVSZR_COUNT                     (1U)
16914 
16915 /*! @name CC2CTXR - CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17 */
16916 /*! @{ */
16917 
16918 #define CAAM_CC2CTXR_C2CTXR_MASK                 (0xFFFFFFFFU)
16919 #define CAAM_CC2CTXR_C2CTXR_SHIFT                (0U)
16920 #define CAAM_CC2CTXR_C2CTXR(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CC2CTXR_C2CTXR_SHIFT)) & CAAM_CC2CTXR_C2CTXR_MASK)
16921 /*! @} */
16922 
16923 /* The count of CAAM_CC2CTXR */
16924 #define CAAM_CC2CTXR_COUNT                       (1U)
16925 
16926 /* The count of CAAM_CC2CTXR */
16927 #define CAAM_CC2CTXR_COUNT2                      (18U)
16928 
16929 /*! @name CC2KEYR - CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31 */
16930 /*! @{ */
16931 
16932 #define CAAM_CC2KEYR_C2KEY_MASK                  (0xFFFFFFFFU)
16933 #define CAAM_CC2KEYR_C2KEY_SHIFT                 (0U)
16934 #define CAAM_CC2KEYR_C2KEY(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CC2KEYR_C2KEY_SHIFT)) & CAAM_CC2KEYR_C2KEY_MASK)
16935 /*! @} */
16936 
16937 /* The count of CAAM_CC2KEYR */
16938 #define CAAM_CC2KEYR_COUNT                       (1U)
16939 
16940 /* The count of CAAM_CC2KEYR */
16941 #define CAAM_CC2KEYR_COUNT2                      (32U)
16942 
16943 /*! @name CFIFOSTA - CCB 0 FIFO Status Register */
16944 /*! @{ */
16945 
16946 #define CAAM_CFIFOSTA_DECOOQHEAD_MASK            (0xFFU)
16947 #define CAAM_CFIFOSTA_DECOOQHEAD_SHIFT           (0U)
16948 #define CAAM_CFIFOSTA_DECOOQHEAD(x)              (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_DECOOQHEAD_SHIFT)) & CAAM_CFIFOSTA_DECOOQHEAD_MASK)
16949 
16950 #define CAAM_CFIFOSTA_DMAOQHEAD_MASK             (0xFF00U)
16951 #define CAAM_CFIFOSTA_DMAOQHEAD_SHIFT            (8U)
16952 #define CAAM_CFIFOSTA_DMAOQHEAD(x)               (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_DMAOQHEAD_SHIFT)) & CAAM_CFIFOSTA_DMAOQHEAD_MASK)
16953 
16954 #define CAAM_CFIFOSTA_C2IQHEAD_MASK              (0xFF0000U)
16955 #define CAAM_CFIFOSTA_C2IQHEAD_SHIFT             (16U)
16956 #define CAAM_CFIFOSTA_C2IQHEAD(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_C2IQHEAD_SHIFT)) & CAAM_CFIFOSTA_C2IQHEAD_MASK)
16957 
16958 #define CAAM_CFIFOSTA_C1IQHEAD_MASK              (0xFF000000U)
16959 #define CAAM_CFIFOSTA_C1IQHEAD_SHIFT             (24U)
16960 #define CAAM_CFIFOSTA_C1IQHEAD(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_C1IQHEAD_SHIFT)) & CAAM_CFIFOSTA_C1IQHEAD_MASK)
16961 /*! @} */
16962 
16963 /* The count of CAAM_CFIFOSTA */
16964 #define CAAM_CFIFOSTA_COUNT                      (1U)
16965 
16966 /*! @name CNFIFO - CCB 0 iNformation FIFO When STYPE != 10b */
16967 /*! @{ */
16968 
16969 #define CAAM_CNFIFO_DL_MASK                      (0xFFFU)
16970 #define CAAM_CNFIFO_DL_SHIFT                     (0U)
16971 #define CAAM_CNFIFO_DL(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DL_SHIFT)) & CAAM_CNFIFO_DL_MASK)
16972 
16973 #define CAAM_CNFIFO_AST_MASK                     (0x4000U)
16974 #define CAAM_CNFIFO_AST_SHIFT                    (14U)
16975 #define CAAM_CNFIFO_AST(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_AST_SHIFT)) & CAAM_CNFIFO_AST_MASK)
16976 
16977 #define CAAM_CNFIFO_OC_MASK                      (0x8000U)
16978 #define CAAM_CNFIFO_OC_SHIFT                     (15U)
16979 /*! OC
16980  *  0b0..Allow the final word to be popped from the Output Data FIFO.
16981  *  0b1..Don't pop the final word from the Output Data FIFO.
16982  */
16983 #define CAAM_CNFIFO_OC(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_OC_SHIFT)) & CAAM_CNFIFO_OC_MASK)
16984 
16985 #define CAAM_CNFIFO_PTYPE_MASK                   (0x70000U)
16986 #define CAAM_CNFIFO_PTYPE_SHIFT                  (16U)
16987 #define CAAM_CNFIFO_PTYPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_PTYPE_SHIFT)) & CAAM_CNFIFO_PTYPE_MASK)
16988 
16989 #define CAAM_CNFIFO_BND_MASK                     (0x80000U)
16990 #define CAAM_CNFIFO_BND_SHIFT                    (19U)
16991 /*! BND
16992  *  0b0..Don't pad.
16993  *  0b1..Pad to the next 16-byte boundary.
16994  */
16995 #define CAAM_CNFIFO_BND(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_BND_SHIFT)) & CAAM_CNFIFO_BND_MASK)
16996 
16997 #define CAAM_CNFIFO_DTYPE_MASK                   (0xF00000U)
16998 #define CAAM_CNFIFO_DTYPE_SHIFT                  (20U)
16999 #define CAAM_CNFIFO_DTYPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DTYPE_SHIFT)) & CAAM_CNFIFO_DTYPE_MASK)
17000 
17001 #define CAAM_CNFIFO_STYPE_MASK                   (0x3000000U)
17002 #define CAAM_CNFIFO_STYPE_SHIFT                  (24U)
17003 #define CAAM_CNFIFO_STYPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_STYPE_SHIFT)) & CAAM_CNFIFO_STYPE_MASK)
17004 
17005 #define CAAM_CNFIFO_FC1_MASK                     (0x4000000U)
17006 #define CAAM_CNFIFO_FC1_SHIFT                    (26U)
17007 /*! FC1
17008  *  0b0..Don't flush Class 1 data.
17009  *  0b1..Flush Class 1 data.
17010  */
17011 #define CAAM_CNFIFO_FC1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_FC1_SHIFT)) & CAAM_CNFIFO_FC1_MASK)
17012 
17013 #define CAAM_CNFIFO_FC2_MASK                     (0x8000000U)
17014 #define CAAM_CNFIFO_FC2_SHIFT                    (27U)
17015 /*! FC2
17016  *  0b0..Don't flush Class 2 data.
17017  *  0b1..Flush Class 2 data.
17018  */
17019 #define CAAM_CNFIFO_FC2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_FC2_SHIFT)) & CAAM_CNFIFO_FC2_MASK)
17020 
17021 #define CAAM_CNFIFO_LC1_MASK                     (0x10000000U)
17022 #define CAAM_CNFIFO_LC1_SHIFT                    (28U)
17023 /*! LC1
17024  *  0b0..This is not the last Class 1 data.
17025  *  0b1..This is the last Class 1 data.
17026  */
17027 #define CAAM_CNFIFO_LC1(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_LC1_SHIFT)) & CAAM_CNFIFO_LC1_MASK)
17028 
17029 #define CAAM_CNFIFO_LC2_MASK                     (0x20000000U)
17030 #define CAAM_CNFIFO_LC2_SHIFT                    (29U)
17031 /*! LC2
17032  *  0b0..This is not the last Class 2 data.
17033  *  0b1..This is the last Class 2 data.
17034  */
17035 #define CAAM_CNFIFO_LC2(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_LC2_SHIFT)) & CAAM_CNFIFO_LC2_MASK)
17036 
17037 #define CAAM_CNFIFO_DEST_MASK                    (0xC0000000U)
17038 #define CAAM_CNFIFO_DEST_SHIFT                   (30U)
17039 /*! DEST
17040  *  0b00..DECO Alignment Block. If DTYPE == Eh, data sent to the DECO Alignment Block is dropped. This is used to
17041  *        skip over input data. An error is generated if a DTYPE other than Eh (drop) or Fh (message) is used with
17042  *        the DECO Alignment Block destination.
17043  *  0b01..Class 1.
17044  *  0b10..Class 2.
17045  *  0b11..Both Class 1 and Class 2.
17046  */
17047 #define CAAM_CNFIFO_DEST(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DEST_SHIFT)) & CAAM_CNFIFO_DEST_MASK)
17048 /*! @} */
17049 
17050 /* The count of CAAM_CNFIFO */
17051 #define CAAM_CNFIFO_COUNT                        (1U)
17052 
17053 /*! @name CNFIFO_2 - CCB 0 iNformation FIFO When STYPE == 10b */
17054 /*! @{ */
17055 
17056 #define CAAM_CNFIFO_2_PL_MASK                    (0x7FU)
17057 #define CAAM_CNFIFO_2_PL_SHIFT                   (0U)
17058 #define CAAM_CNFIFO_2_PL(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PL_SHIFT)) & CAAM_CNFIFO_2_PL_MASK)
17059 
17060 #define CAAM_CNFIFO_2_PS_MASK                    (0x400U)
17061 #define CAAM_CNFIFO_2_PS_SHIFT                   (10U)
17062 /*! PS
17063  *  0b0..C2 CHA snoops pad data from padding block.
17064  *  0b1..C2 CHA snoops pad data from OFIFO.
17065  */
17066 #define CAAM_CNFIFO_2_PS(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PS_SHIFT)) & CAAM_CNFIFO_2_PS_MASK)
17067 
17068 #define CAAM_CNFIFO_2_BM_MASK                    (0x800U)
17069 #define CAAM_CNFIFO_2_BM_SHIFT                   (11U)
17070 /*! BM
17071  *  0b0..When padding, pad to power-of-2 boundary.
17072  *  0b1..When padding, pad to power-of-2 boundary minus 1 byte.
17073  */
17074 #define CAAM_CNFIFO_2_BM(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_BM_SHIFT)) & CAAM_CNFIFO_2_BM_MASK)
17075 
17076 #define CAAM_CNFIFO_2_PR_MASK                    (0x8000U)
17077 #define CAAM_CNFIFO_2_PR_SHIFT                   (15U)
17078 /*! PR
17079  *  0b0..No prediction resistance.
17080  *  0b1..Prediction resistance.
17081  */
17082 #define CAAM_CNFIFO_2_PR(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PR_SHIFT)) & CAAM_CNFIFO_2_PR_MASK)
17083 
17084 #define CAAM_CNFIFO_2_PTYPE_MASK                 (0x70000U)
17085 #define CAAM_CNFIFO_2_PTYPE_SHIFT                (16U)
17086 /*! PTYPE
17087  *  0b000..All Zero.
17088  *  0b001..Random with nonzero bytes.
17089  *  0b010..Incremented (starting with 01h), followed by a byte containing the value N-1, i.e., if N==1, a single byte is output with value 0h.
17090  *  0b011..Random.
17091  *  0b100..All Zero with last byte containing the number of 0 bytes, i.e., if N==1, a single byte is output with value 0h.
17092  *  0b101..Random with nonzero bytes with last byte 0.
17093  *  0b110..N bytes of padding all containing the value N-1.
17094  *  0b111..Random with nonzero bytes, with the last byte containing the value N-1.
17095  */
17096 #define CAAM_CNFIFO_2_PTYPE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PTYPE_SHIFT)) & CAAM_CNFIFO_2_PTYPE_MASK)
17097 
17098 #define CAAM_CNFIFO_2_BND_MASK                   (0x80000U)
17099 #define CAAM_CNFIFO_2_BND_SHIFT                  (19U)
17100 /*! BND
17101  *  0b0..Don't add boundary padding.
17102  *  0b1..Add boundary padding.
17103  */
17104 #define CAAM_CNFIFO_2_BND(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_BND_SHIFT)) & CAAM_CNFIFO_2_BND_MASK)
17105 
17106 #define CAAM_CNFIFO_2_DTYPE_MASK                 (0xF00000U)
17107 #define CAAM_CNFIFO_2_DTYPE_SHIFT                (20U)
17108 #define CAAM_CNFIFO_2_DTYPE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_DTYPE_SHIFT)) & CAAM_CNFIFO_2_DTYPE_MASK)
17109 
17110 #define CAAM_CNFIFO_2_STYPE_MASK                 (0x3000000U)
17111 #define CAAM_CNFIFO_2_STYPE_SHIFT                (24U)
17112 #define CAAM_CNFIFO_2_STYPE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_STYPE_SHIFT)) & CAAM_CNFIFO_2_STYPE_MASK)
17113 
17114 #define CAAM_CNFIFO_2_FC1_MASK                   (0x4000000U)
17115 #define CAAM_CNFIFO_2_FC1_SHIFT                  (26U)
17116 /*! FC1
17117  *  0b0..Don't flush the Class 1 data.
17118  *  0b1..Flush the Class 1 data.
17119  */
17120 #define CAAM_CNFIFO_2_FC1(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_FC1_SHIFT)) & CAAM_CNFIFO_2_FC1_MASK)
17121 
17122 #define CAAM_CNFIFO_2_FC2_MASK                   (0x8000000U)
17123 #define CAAM_CNFIFO_2_FC2_SHIFT                  (27U)
17124 /*! FC2
17125  *  0b0..Don't flush the Class 2 data.
17126  *  0b1..Flush the Class 2 data.
17127  */
17128 #define CAAM_CNFIFO_2_FC2(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_FC2_SHIFT)) & CAAM_CNFIFO_2_FC2_MASK)
17129 
17130 #define CAAM_CNFIFO_2_LC1_MASK                   (0x10000000U)
17131 #define CAAM_CNFIFO_2_LC1_SHIFT                  (28U)
17132 /*! LC1
17133  *  0b0..This is not the last Class 1 data.
17134  *  0b1..This is the last Class 1 data.
17135  */
17136 #define CAAM_CNFIFO_2_LC1(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_LC1_SHIFT)) & CAAM_CNFIFO_2_LC1_MASK)
17137 
17138 #define CAAM_CNFIFO_2_LC2_MASK                   (0x20000000U)
17139 #define CAAM_CNFIFO_2_LC2_SHIFT                  (29U)
17140 /*! LC2
17141  *  0b0..This is not the last Class 2 data.
17142  *  0b1..This is the last Class 2 data.
17143  */
17144 #define CAAM_CNFIFO_2_LC2(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_LC2_SHIFT)) & CAAM_CNFIFO_2_LC2_MASK)
17145 
17146 #define CAAM_CNFIFO_2_DEST_MASK                  (0xC0000000U)
17147 #define CAAM_CNFIFO_2_DEST_SHIFT                 (30U)
17148 /*! DEST
17149  *  0b00..DECO Alignment Block. If DTYPE is Eh, data sent to the DECO Alignment Block is dropped. This is used to
17150  *        skip over input data. An error is generated if a DTYPE other than Eh (drop) or Fh (message) is used with
17151  *        the DECO Alignment Block destination.
17152  *  0b01..Class 1.
17153  *  0b10..Class 2.
17154  *  0b11..Both Class 1 and Class 2.
17155  */
17156 #define CAAM_CNFIFO_2_DEST(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_DEST_SHIFT)) & CAAM_CNFIFO_2_DEST_MASK)
17157 /*! @} */
17158 
17159 /* The count of CAAM_CNFIFO_2 */
17160 #define CAAM_CNFIFO_2_COUNT                      (1U)
17161 
17162 /*! @name CIFIFO - CCB 0 Input Data FIFO */
17163 /*! @{ */
17164 
17165 #define CAAM_CIFIFO_IFIFO_MASK                   (0xFFFFFFFFU)
17166 #define CAAM_CIFIFO_IFIFO_SHIFT                  (0U)
17167 #define CAAM_CIFIFO_IFIFO(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_CIFIFO_IFIFO_SHIFT)) & CAAM_CIFIFO_IFIFO_MASK)
17168 /*! @} */
17169 
17170 /* The count of CAAM_CIFIFO */
17171 #define CAAM_CIFIFO_COUNT                        (1U)
17172 
17173 /*! @name COFIFO - CCB 0 Output Data FIFO */
17174 /*! @{ */
17175 
17176 #define CAAM_COFIFO_OFIFO_MASK                   (0xFFFFFFFFFFFFFFFFU)
17177 #define CAAM_COFIFO_OFIFO_SHIFT                  (0U)
17178 #define CAAM_COFIFO_OFIFO(x)                     (((uint64_t)(((uint64_t)(x)) << CAAM_COFIFO_OFIFO_SHIFT)) & CAAM_COFIFO_OFIFO_MASK)
17179 /*! @} */
17180 
17181 /* The count of CAAM_COFIFO */
17182 #define CAAM_COFIFO_COUNT                        (1U)
17183 
17184 /*! @name DJQCR_MS - DECO0 Job Queue Control Register, most-significant half */
17185 /*! @{ */
17186 
17187 #define CAAM_DJQCR_MS_ID_MASK                    (0x7U)
17188 #define CAAM_DJQCR_MS_ID_SHIFT                   (0U)
17189 #define CAAM_DJQCR_MS_ID(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_ID_SHIFT)) & CAAM_DJQCR_MS_ID_MASK)
17190 
17191 #define CAAM_DJQCR_MS_SRC_MASK                   (0x700U)
17192 #define CAAM_DJQCR_MS_SRC_SHIFT                  (8U)
17193 /*! SRC
17194  *  0b000..Job Ring 0
17195  *  0b001..Job Ring 1
17196  *  0b010..Job Ring 2
17197  *  0b011..Job Ring 3
17198  *  0b100..RTIC
17199  *  0b101..Reserved
17200  *  0b110..Reserved
17201  *  0b111..Reserved
17202  */
17203 #define CAAM_DJQCR_MS_SRC(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SRC_SHIFT)) & CAAM_DJQCR_MS_SRC_MASK)
17204 
17205 #define CAAM_DJQCR_MS_AMTD_MASK                  (0x8000U)
17206 #define CAAM_DJQCR_MS_AMTD_SHIFT                 (15U)
17207 /*! AMTD
17208  *  0b0..The Allowed Make Trusted Descriptor bit was NOT set.
17209  *  0b1..The Allowed Make Trusted Descriptor bit was set.
17210  */
17211 #define CAAM_DJQCR_MS_AMTD(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_AMTD_SHIFT)) & CAAM_DJQCR_MS_AMTD_MASK)
17212 
17213 #define CAAM_DJQCR_MS_SOB_MASK                   (0x10000U)
17214 #define CAAM_DJQCR_MS_SOB_SHIFT                  (16U)
17215 /*! SOB
17216  *  0b0..Shared Descriptor has NOT been loaded.
17217  *  0b1..Shared Descriptor HAS been loaded.
17218  */
17219 #define CAAM_DJQCR_MS_SOB(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SOB_SHIFT)) & CAAM_DJQCR_MS_SOB_MASK)
17220 
17221 #define CAAM_DJQCR_MS_DWS_MASK                   (0x80000U)
17222 #define CAAM_DJQCR_MS_DWS_SHIFT                  (19U)
17223 /*! DWS
17224  *  0b0..Double Word Swap is NOT set.
17225  *  0b1..Double Word Swap is set.
17226  */
17227 #define CAAM_DJQCR_MS_DWS(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_DWS_SHIFT)) & CAAM_DJQCR_MS_DWS_MASK)
17228 
17229 #define CAAM_DJQCR_MS_SHR_FROM_MASK              (0x7000000U)
17230 #define CAAM_DJQCR_MS_SHR_FROM_SHIFT             (24U)
17231 #define CAAM_DJQCR_MS_SHR_FROM(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SHR_FROM_SHIFT)) & CAAM_DJQCR_MS_SHR_FROM_MASK)
17232 
17233 #define CAAM_DJQCR_MS_ILE_MASK                   (0x8000000U)
17234 #define CAAM_DJQCR_MS_ILE_SHIFT                  (27U)
17235 /*! ILE
17236  *  0b0..No byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
17237  *  0b1..Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
17238  */
17239 #define CAAM_DJQCR_MS_ILE(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_ILE_SHIFT)) & CAAM_DJQCR_MS_ILE_MASK)
17240 
17241 #define CAAM_DJQCR_MS_FOUR_MASK                  (0x10000000U)
17242 #define CAAM_DJQCR_MS_FOUR_SHIFT                 (28U)
17243 /*! FOUR
17244  *  0b0..DECO has not been given at least four words of the descriptor.
17245  *  0b1..DECO has been given at least four words of the descriptor.
17246  */
17247 #define CAAM_DJQCR_MS_FOUR(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_FOUR_SHIFT)) & CAAM_DJQCR_MS_FOUR_MASK)
17248 
17249 #define CAAM_DJQCR_MS_WHL_MASK                   (0x20000000U)
17250 #define CAAM_DJQCR_MS_WHL_SHIFT                  (29U)
17251 /*! WHL
17252  *  0b0..DECO has not been given the whole descriptor.
17253  *  0b1..DECO has been given the whole descriptor.
17254  */
17255 #define CAAM_DJQCR_MS_WHL(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_WHL_SHIFT)) & CAAM_DJQCR_MS_WHL_MASK)
17256 
17257 #define CAAM_DJQCR_MS_SING_MASK                  (0x40000000U)
17258 #define CAAM_DJQCR_MS_SING_SHIFT                 (30U)
17259 /*! SING
17260  *  0b0..Do not tell DECO to execute the descriptor in single-step mode.
17261  *  0b1..Tell DECO to execute the descriptor in single-step mode.
17262  */
17263 #define CAAM_DJQCR_MS_SING(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SING_SHIFT)) & CAAM_DJQCR_MS_SING_MASK)
17264 
17265 #define CAAM_DJQCR_MS_STEP_MASK                  (0x80000000U)
17266 #define CAAM_DJQCR_MS_STEP_SHIFT                 (31U)
17267 /*! STEP
17268  *  0b0..DECO has not been told to execute the next command in the descriptor.
17269  *  0b1..DECO has been told to execute the next command in the descriptor.
17270  */
17271 #define CAAM_DJQCR_MS_STEP(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_STEP_SHIFT)) & CAAM_DJQCR_MS_STEP_MASK)
17272 /*! @} */
17273 
17274 /* The count of CAAM_DJQCR_MS */
17275 #define CAAM_DJQCR_MS_COUNT                      (1U)
17276 
17277 /*! @name DJQCR_LS - DECO0 Job Queue Control Register, least-significant half */
17278 /*! @{ */
17279 
17280 #define CAAM_DJQCR_LS_CMD_MASK                   (0xFFFFFFFFU)
17281 #define CAAM_DJQCR_LS_CMD_SHIFT                  (0U)
17282 #define CAAM_DJQCR_LS_CMD(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_LS_CMD_SHIFT)) & CAAM_DJQCR_LS_CMD_MASK)
17283 /*! @} */
17284 
17285 /* The count of CAAM_DJQCR_LS */
17286 #define CAAM_DJQCR_LS_COUNT                      (1U)
17287 
17288 /*! @name DDAR - DECO0 Descriptor Address Register */
17289 /*! @{ */
17290 
17291 #define CAAM_DDAR_DPTR_MASK                      (0xFFFFFFFFFU)
17292 #define CAAM_DDAR_DPTR_SHIFT                     (0U)
17293 #define CAAM_DDAR_DPTR(x)                        (((uint64_t)(((uint64_t)(x)) << CAAM_DDAR_DPTR_SHIFT)) & CAAM_DDAR_DPTR_MASK)
17294 /*! @} */
17295 
17296 /* The count of CAAM_DDAR */
17297 #define CAAM_DDAR_COUNT                          (1U)
17298 
17299 /*! @name DOPSTA_MS - DECO0 Operation Status Register, most-significant half */
17300 /*! @{ */
17301 
17302 #define CAAM_DOPSTA_MS_STATUS_MASK               (0xFFU)
17303 #define CAAM_DOPSTA_MS_STATUS_SHIFT              (0U)
17304 #define CAAM_DOPSTA_MS_STATUS(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_STATUS_SHIFT)) & CAAM_DOPSTA_MS_STATUS_MASK)
17305 
17306 #define CAAM_DOPSTA_MS_COMMAND_INDEX_MASK        (0x7F00U)
17307 #define CAAM_DOPSTA_MS_COMMAND_INDEX_SHIFT       (8U)
17308 #define CAAM_DOPSTA_MS_COMMAND_INDEX(x)          (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_COMMAND_INDEX_SHIFT)) & CAAM_DOPSTA_MS_COMMAND_INDEX_MASK)
17309 
17310 #define CAAM_DOPSTA_MS_NLJ_MASK                  (0x8000000U)
17311 #define CAAM_DOPSTA_MS_NLJ_SHIFT                 (27U)
17312 /*! NLJ
17313  *  0b0..The original job descriptor running in this DECO has not caused another job descriptor to be executed.
17314  *  0b1..The original job descriptor running in this DECO has caused another job descriptor to be executed.
17315  */
17316 #define CAAM_DOPSTA_MS_NLJ(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_NLJ_SHIFT)) & CAAM_DOPSTA_MS_NLJ_MASK)
17317 
17318 #define CAAM_DOPSTA_MS_STATUS_TYPE_MASK          (0xF0000000U)
17319 #define CAAM_DOPSTA_MS_STATUS_TYPE_SHIFT         (28U)
17320 /*! STATUS_TYPE
17321  *  0b0000..no error
17322  *  0b0001..DMA error
17323  *  0b0010..CCB error
17324  *  0b0011..Jump Halt User Status
17325  *  0b0100..DECO error
17326  *  0b0101, 0b0110..Reserved
17327  *  0b0111..Jump Halt Condition Code
17328  */
17329 #define CAAM_DOPSTA_MS_STATUS_TYPE(x)            (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_STATUS_TYPE_SHIFT)) & CAAM_DOPSTA_MS_STATUS_TYPE_MASK)
17330 /*! @} */
17331 
17332 /* The count of CAAM_DOPSTA_MS */
17333 #define CAAM_DOPSTA_MS_COUNT                     (1U)
17334 
17335 /*! @name DOPSTA_LS - DECO0 Operation Status Register, least-significant half */
17336 /*! @{ */
17337 
17338 #define CAAM_DOPSTA_LS_OUT_CT_MASK               (0xFFFFFFFFU)
17339 #define CAAM_DOPSTA_LS_OUT_CT_SHIFT              (0U)
17340 #define CAAM_DOPSTA_LS_OUT_CT(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_LS_OUT_CT_SHIFT)) & CAAM_DOPSTA_LS_OUT_CT_MASK)
17341 /*! @} */
17342 
17343 /* The count of CAAM_DOPSTA_LS */
17344 #define CAAM_DOPSTA_LS_COUNT                     (1U)
17345 
17346 /*! @name DPDIDSR - DECO0 Primary DID Status Register */
17347 /*! @{ */
17348 
17349 #define CAAM_DPDIDSR_PRIM_DID_MASK               (0xFU)
17350 #define CAAM_DPDIDSR_PRIM_DID_SHIFT              (0U)
17351 #define CAAM_DPDIDSR_PRIM_DID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DPDIDSR_PRIM_DID_SHIFT)) & CAAM_DPDIDSR_PRIM_DID_MASK)
17352 
17353 #define CAAM_DPDIDSR_PRIM_ICID_MASK              (0x3FF80000U)
17354 #define CAAM_DPDIDSR_PRIM_ICID_SHIFT             (19U)
17355 #define CAAM_DPDIDSR_PRIM_ICID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DPDIDSR_PRIM_ICID_SHIFT)) & CAAM_DPDIDSR_PRIM_ICID_MASK)
17356 /*! @} */
17357 
17358 /* The count of CAAM_DPDIDSR */
17359 #define CAAM_DPDIDSR_COUNT                       (1U)
17360 
17361 /*! @name DODIDSR - DECO0 Output DID Status Register */
17362 /*! @{ */
17363 
17364 #define CAAM_DODIDSR_OUT_DID_MASK                (0xFU)
17365 #define CAAM_DODIDSR_OUT_DID_SHIFT               (0U)
17366 #define CAAM_DODIDSR_OUT_DID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DODIDSR_OUT_DID_SHIFT)) & CAAM_DODIDSR_OUT_DID_MASK)
17367 
17368 #define CAAM_DODIDSR_OUT_ICID_MASK               (0x3FF80000U)
17369 #define CAAM_DODIDSR_OUT_ICID_SHIFT              (19U)
17370 #define CAAM_DODIDSR_OUT_ICID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DODIDSR_OUT_ICID_SHIFT)) & CAAM_DODIDSR_OUT_ICID_MASK)
17371 /*! @} */
17372 
17373 /* The count of CAAM_DODIDSR */
17374 #define CAAM_DODIDSR_COUNT                       (1U)
17375 
17376 /*! @name DMTH_MS - DECO0 Math Register 0_MS..DECO0 Math Register 3_MS */
17377 /*! @{ */
17378 
17379 #define CAAM_DMTH_MS_MATH_MS_MASK                (0xFFFFFFFFU)
17380 #define CAAM_DMTH_MS_MATH_MS_SHIFT               (0U)
17381 #define CAAM_DMTH_MS_MATH_MS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DMTH_MS_MATH_MS_SHIFT)) & CAAM_DMTH_MS_MATH_MS_MASK)
17382 /*! @} */
17383 
17384 /* The count of CAAM_DMTH_MS */
17385 #define CAAM_DMTH_MS_COUNT                       (1U)
17386 
17387 /* The count of CAAM_DMTH_MS */
17388 #define CAAM_DMTH_MS_COUNT2                      (4U)
17389 
17390 /*! @name DMTH_LS - DECO0 Math Register 0_LS..DECO0 Math Register 3_LS */
17391 /*! @{ */
17392 
17393 #define CAAM_DMTH_LS_MATH_LS_MASK                (0xFFFFFFFFU)
17394 #define CAAM_DMTH_LS_MATH_LS_SHIFT               (0U)
17395 #define CAAM_DMTH_LS_MATH_LS(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DMTH_LS_MATH_LS_SHIFT)) & CAAM_DMTH_LS_MATH_LS_MASK)
17396 /*! @} */
17397 
17398 /* The count of CAAM_DMTH_LS */
17399 #define CAAM_DMTH_LS_COUNT                       (1U)
17400 
17401 /* The count of CAAM_DMTH_LS */
17402 #define CAAM_DMTH_LS_COUNT2                      (4U)
17403 
17404 /*! @name DGTR_0 - DECO0 Gather Table Register 0 Word 0 */
17405 /*! @{ */
17406 
17407 #define CAAM_DGTR_0_ADDRESS_POINTER_MASK         (0xFU)
17408 #define CAAM_DGTR_0_ADDRESS_POINTER_SHIFT        (0U)
17409 /*! ADDRESS_POINTER - most-significant bits of memory address pointed to by table entry */
17410 #define CAAM_DGTR_0_ADDRESS_POINTER(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_0_ADDRESS_POINTER_SHIFT)) & CAAM_DGTR_0_ADDRESS_POINTER_MASK)
17411 /*! @} */
17412 
17413 /* The count of CAAM_DGTR_0 */
17414 #define CAAM_DGTR_0_COUNT                        (1U)
17415 
17416 /* The count of CAAM_DGTR_0 */
17417 #define CAAM_DGTR_0_COUNT2                       (1U)
17418 
17419 /*! @name DGTR_1 - DECO0 Gather Table Register 0 Word 1 */
17420 /*! @{ */
17421 
17422 #define CAAM_DGTR_1_ADDRESS_POINTER_MASK         (0xFFFFFFFFU)
17423 #define CAAM_DGTR_1_ADDRESS_POINTER_SHIFT        (0U)
17424 #define CAAM_DGTR_1_ADDRESS_POINTER(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_1_ADDRESS_POINTER_SHIFT)) & CAAM_DGTR_1_ADDRESS_POINTER_MASK)
17425 /*! @} */
17426 
17427 /* The count of CAAM_DGTR_1 */
17428 #define CAAM_DGTR_1_COUNT                        (1U)
17429 
17430 /* The count of CAAM_DGTR_1 */
17431 #define CAAM_DGTR_1_COUNT2                       (1U)
17432 
17433 /*! @name DGTR_2 - DECO0 Gather Table Register 0 Word 2 */
17434 /*! @{ */
17435 
17436 #define CAAM_DGTR_2_Length_MASK                  (0x3FFFFFFFU)
17437 #define CAAM_DGTR_2_Length_SHIFT                 (0U)
17438 #define CAAM_DGTR_2_Length(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_Length_SHIFT)) & CAAM_DGTR_2_Length_MASK)
17439 
17440 #define CAAM_DGTR_2_F_MASK                       (0x40000000U)
17441 #define CAAM_DGTR_2_F_SHIFT                      (30U)
17442 /*! F
17443  *  0b0..This is not the last entry of the SGT.
17444  *  0b1..This is the last entry of the SGT.
17445  */
17446 #define CAAM_DGTR_2_F(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_F_SHIFT)) & CAAM_DGTR_2_F_MASK)
17447 
17448 #define CAAM_DGTR_2_E_MASK                       (0x80000000U)
17449 #define CAAM_DGTR_2_E_SHIFT                      (31U)
17450 /*! E
17451  *  0b0..Address Pointer points to a memory buffer.
17452  *  0b1..Address Pointer points to a Scatter/Gather Table Entry.
17453  */
17454 #define CAAM_DGTR_2_E(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_E_SHIFT)) & CAAM_DGTR_2_E_MASK)
17455 /*! @} */
17456 
17457 /* The count of CAAM_DGTR_2 */
17458 #define CAAM_DGTR_2_COUNT                        (1U)
17459 
17460 /* The count of CAAM_DGTR_2 */
17461 #define CAAM_DGTR_2_COUNT2                       (1U)
17462 
17463 /*! @name DGTR_3 - DECO0 Gather Table Register 0 Word 3 */
17464 /*! @{ */
17465 
17466 #define CAAM_DGTR_3_Offset_MASK                  (0x1FFFU)
17467 #define CAAM_DGTR_3_Offset_SHIFT                 (0U)
17468 #define CAAM_DGTR_3_Offset(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_3_Offset_SHIFT)) & CAAM_DGTR_3_Offset_MASK)
17469 /*! @} */
17470 
17471 /* The count of CAAM_DGTR_3 */
17472 #define CAAM_DGTR_3_COUNT                        (1U)
17473 
17474 /* The count of CAAM_DGTR_3 */
17475 #define CAAM_DGTR_3_COUNT2                       (1U)
17476 
17477 /*! @name DSTR_0 - DECO0 Scatter Table Register 0 Word 0 */
17478 /*! @{ */
17479 
17480 #define CAAM_DSTR_0_ADDRESS_POINTER_MASK         (0xFU)
17481 #define CAAM_DSTR_0_ADDRESS_POINTER_SHIFT        (0U)
17482 /*! ADDRESS_POINTER - most-significant bits of memory address pointed to by table entry */
17483 #define CAAM_DSTR_0_ADDRESS_POINTER(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_0_ADDRESS_POINTER_SHIFT)) & CAAM_DSTR_0_ADDRESS_POINTER_MASK)
17484 /*! @} */
17485 
17486 /* The count of CAAM_DSTR_0 */
17487 #define CAAM_DSTR_0_COUNT                        (1U)
17488 
17489 /* The count of CAAM_DSTR_0 */
17490 #define CAAM_DSTR_0_COUNT2                       (1U)
17491 
17492 /*! @name DSTR_1 - DECO0 Scatter Table Register 0 Word 1 */
17493 /*! @{ */
17494 
17495 #define CAAM_DSTR_1_ADDRESS_POINTER_MASK         (0xFFFFFFFFU)
17496 #define CAAM_DSTR_1_ADDRESS_POINTER_SHIFT        (0U)
17497 #define CAAM_DSTR_1_ADDRESS_POINTER(x)           (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_1_ADDRESS_POINTER_SHIFT)) & CAAM_DSTR_1_ADDRESS_POINTER_MASK)
17498 /*! @} */
17499 
17500 /* The count of CAAM_DSTR_1 */
17501 #define CAAM_DSTR_1_COUNT                        (1U)
17502 
17503 /* The count of CAAM_DSTR_1 */
17504 #define CAAM_DSTR_1_COUNT2                       (1U)
17505 
17506 /*! @name DSTR_2 - DECO0 Scatter Table Register 0 Word 2 */
17507 /*! @{ */
17508 
17509 #define CAAM_DSTR_2_Length_MASK                  (0x3FFFFFFFU)
17510 #define CAAM_DSTR_2_Length_SHIFT                 (0U)
17511 #define CAAM_DSTR_2_Length(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_Length_SHIFT)) & CAAM_DSTR_2_Length_MASK)
17512 
17513 #define CAAM_DSTR_2_F_MASK                       (0x40000000U)
17514 #define CAAM_DSTR_2_F_SHIFT                      (30U)
17515 /*! F
17516  *  0b0..This is not the last entry of the SGT.
17517  *  0b1..This is the last entry of the SGT.
17518  */
17519 #define CAAM_DSTR_2_F(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_F_SHIFT)) & CAAM_DSTR_2_F_MASK)
17520 
17521 #define CAAM_DSTR_2_E_MASK                       (0x80000000U)
17522 #define CAAM_DSTR_2_E_SHIFT                      (31U)
17523 /*! E
17524  *  0b0..Address Pointer points to a memory buffer.
17525  *  0b1..Address Pointer points to a Scatter/Gather Table Entry.
17526  */
17527 #define CAAM_DSTR_2_E(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_E_SHIFT)) & CAAM_DSTR_2_E_MASK)
17528 /*! @} */
17529 
17530 /* The count of CAAM_DSTR_2 */
17531 #define CAAM_DSTR_2_COUNT                        (1U)
17532 
17533 /* The count of CAAM_DSTR_2 */
17534 #define CAAM_DSTR_2_COUNT2                       (1U)
17535 
17536 /*! @name DSTR_3 - DECO0 Scatter Table Register 0 Word 3 */
17537 /*! @{ */
17538 
17539 #define CAAM_DSTR_3_Offset_MASK                  (0x1FFFU)
17540 #define CAAM_DSTR_3_Offset_SHIFT                 (0U)
17541 #define CAAM_DSTR_3_Offset(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_3_Offset_SHIFT)) & CAAM_DSTR_3_Offset_MASK)
17542 /*! @} */
17543 
17544 /* The count of CAAM_DSTR_3 */
17545 #define CAAM_DSTR_3_COUNT                        (1U)
17546 
17547 /* The count of CAAM_DSTR_3 */
17548 #define CAAM_DSTR_3_COUNT2                       (1U)
17549 
17550 /*! @name DDESB - DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63 */
17551 /*! @{ */
17552 
17553 #define CAAM_DDESB_DESBW_MASK                    (0xFFFFFFFFU)
17554 #define CAAM_DDESB_DESBW_SHIFT                   (0U)
17555 #define CAAM_DDESB_DESBW(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_DDESB_DESBW_SHIFT)) & CAAM_DDESB_DESBW_MASK)
17556 /*! @} */
17557 
17558 /* The count of CAAM_DDESB */
17559 #define CAAM_DDESB_COUNT                         (1U)
17560 
17561 /* The count of CAAM_DDESB */
17562 #define CAAM_DDESB_COUNT2                        (64U)
17563 
17564 /*! @name DDJR - DECO0 Debug Job Register */
17565 /*! @{ */
17566 
17567 #define CAAM_DDJR_ID_MASK                        (0x7U)
17568 #define CAAM_DDJR_ID_SHIFT                       (0U)
17569 #define CAAM_DDJR_ID(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_ID_SHIFT)) & CAAM_DDJR_ID_MASK)
17570 
17571 #define CAAM_DDJR_SRC_MASK                       (0x700U)
17572 #define CAAM_DDJR_SRC_SHIFT                      (8U)
17573 /*! SRC
17574  *  0b000..Job Ring 0
17575  *  0b001..Job Ring 1
17576  *  0b010..Job Ring 2
17577  *  0b011..Job Ring 3
17578  *  0b100..RTIC
17579  *  0b101, 0b110, 0b111..Reserved
17580  */
17581 #define CAAM_DDJR_SRC(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SRC_SHIFT)) & CAAM_DDJR_SRC_MASK)
17582 
17583 #define CAAM_DDJR_JDDS_MASK                      (0x4000U)
17584 #define CAAM_DDJR_JDDS_SHIFT                     (14U)
17585 /*! JDDS
17586  *  0b1..SEQ DID
17587  *  0b0..Non-SEQ DID
17588  */
17589 #define CAAM_DDJR_JDDS(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_JDDS_SHIFT)) & CAAM_DDJR_JDDS_MASK)
17590 
17591 #define CAAM_DDJR_AMTD_MASK                      (0x8000U)
17592 #define CAAM_DDJR_AMTD_SHIFT                     (15U)
17593 /*! AMTD
17594  *  0b0..The Allowed Make Trusted Descriptor bit was NOT set.
17595  *  0b1..The Allowed Make Trusted Descriptor bit was set.
17596  */
17597 #define CAAM_DDJR_AMTD(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_AMTD_SHIFT)) & CAAM_DDJR_AMTD_MASK)
17598 
17599 #define CAAM_DDJR_GSD_MASK                       (0x10000U)
17600 #define CAAM_DDJR_GSD_SHIFT                      (16U)
17601 /*! GSD
17602  *  0b0..Shared Descriptor was NOT obtained from another DECO.
17603  *  0b1..Shared Descriptor was obtained from another DECO.
17604  */
17605 #define CAAM_DDJR_GSD(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_GSD_SHIFT)) & CAAM_DDJR_GSD_MASK)
17606 
17607 #define CAAM_DDJR_DWS_MASK                       (0x80000U)
17608 #define CAAM_DDJR_DWS_SHIFT                      (19U)
17609 /*! DWS
17610  *  0b0..Double Word Swap is NOT set.
17611  *  0b1..Double Word Swap is set.
17612  */
17613 #define CAAM_DDJR_DWS(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_DWS_SHIFT)) & CAAM_DDJR_DWS_MASK)
17614 
17615 #define CAAM_DDJR_SHR_FROM_MASK                  (0x7000000U)
17616 #define CAAM_DDJR_SHR_FROM_SHIFT                 (24U)
17617 #define CAAM_DDJR_SHR_FROM(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SHR_FROM_SHIFT)) & CAAM_DDJR_SHR_FROM_MASK)
17618 
17619 #define CAAM_DDJR_ILE_MASK                       (0x8000000U)
17620 #define CAAM_DDJR_ILE_SHIFT                      (27U)
17621 /*! ILE
17622  *  0b0..No byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
17623  *  0b1..Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
17624  */
17625 #define CAAM_DDJR_ILE(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_ILE_SHIFT)) & CAAM_DDJR_ILE_MASK)
17626 
17627 #define CAAM_DDJR_FOUR_MASK                      (0x10000000U)
17628 #define CAAM_DDJR_FOUR_SHIFT                     (28U)
17629 /*! FOUR
17630  *  0b0..DECO has not been given at least four words of the descriptor.
17631  *  0b1..DECO has been given at least four words of the descriptor.
17632  */
17633 #define CAAM_DDJR_FOUR(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_FOUR_SHIFT)) & CAAM_DDJR_FOUR_MASK)
17634 
17635 #define CAAM_DDJR_WHL_MASK                       (0x20000000U)
17636 #define CAAM_DDJR_WHL_SHIFT                      (29U)
17637 /*! WHL
17638  *  0b0..DECO has not been given the whole descriptor.
17639  *  0b1..DECO has been given the whole descriptor.
17640  */
17641 #define CAAM_DDJR_WHL(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_WHL_SHIFT)) & CAAM_DDJR_WHL_MASK)
17642 
17643 #define CAAM_DDJR_SING_MASK                      (0x40000000U)
17644 #define CAAM_DDJR_SING_SHIFT                     (30U)
17645 /*! SING
17646  *  0b0..DECO has not been told to execute the descriptor in single-step mode.
17647  *  0b1..DECO has been told to execute the descriptor in single-step mode.
17648  */
17649 #define CAAM_DDJR_SING(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SING_SHIFT)) & CAAM_DDJR_SING_MASK)
17650 
17651 #define CAAM_DDJR_STEP_MASK                      (0x80000000U)
17652 #define CAAM_DDJR_STEP_SHIFT                     (31U)
17653 /*! STEP
17654  *  0b0..DECO has not been told to execute the next command in the descriptor.
17655  *  0b1..DECO has been told to execute the next command in the descriptor.
17656  */
17657 #define CAAM_DDJR_STEP(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_STEP_SHIFT)) & CAAM_DDJR_STEP_MASK)
17658 /*! @} */
17659 
17660 /* The count of CAAM_DDJR */
17661 #define CAAM_DDJR_COUNT                          (1U)
17662 
17663 /*! @name DDDR - DECO0 Debug DECO Register */
17664 /*! @{ */
17665 
17666 #define CAAM_DDDR_CT_MASK                        (0x1U)
17667 #define CAAM_DDDR_CT_SHIFT                       (0U)
17668 /*! CT
17669  *  0b0..This DECO is NOTcurrently generating the signature of a Trusted Descriptor.
17670  *  0b1..This DECO is currently generating the signature of a Trusted Descriptor.
17671  */
17672 #define CAAM_DDDR_CT(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CT_SHIFT)) & CAAM_DDDR_CT_MASK)
17673 
17674 #define CAAM_DDDR_BRB_MASK                       (0x2U)
17675 #define CAAM_DDDR_BRB_SHIFT                      (1U)
17676 /*! BRB
17677  *  0b0..The READ machine in the Burster is not busy.
17678  *  0b1..The READ machine in the Burster is busy.
17679  */
17680 #define CAAM_DDDR_BRB(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_BRB_SHIFT)) & CAAM_DDDR_BRB_MASK)
17681 
17682 #define CAAM_DDDR_BWB_MASK                       (0x4U)
17683 #define CAAM_DDDR_BWB_SHIFT                      (2U)
17684 /*! BWB
17685  *  0b0..The WRITE machine in the Burster is not busy.
17686  *  0b1..The WRITE machine in the Burster is busy.
17687  */
17688 #define CAAM_DDDR_BWB(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_BWB_SHIFT)) & CAAM_DDDR_BWB_MASK)
17689 
17690 #define CAAM_DDDR_NC_MASK                        (0x8U)
17691 #define CAAM_DDDR_NC_SHIFT                       (3U)
17692 /*! NC
17693  *  0b0..This DECO is currently executing a command.
17694  *  0b1..This DECO is not currently executing a command.
17695  */
17696 #define CAAM_DDDR_NC(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NC_SHIFT)) & CAAM_DDDR_NC_MASK)
17697 
17698 #define CAAM_DDDR_CSA_MASK                       (0x10U)
17699 #define CAAM_DDDR_CSA_SHIFT                      (4U)
17700 #define CAAM_DDDR_CSA(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CSA_SHIFT)) & CAAM_DDDR_CSA_MASK)
17701 
17702 #define CAAM_DDDR_CMD_STAGE_MASK                 (0xE0U)
17703 #define CAAM_DDDR_CMD_STAGE_SHIFT                (5U)
17704 #define CAAM_DDDR_CMD_STAGE(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CMD_STAGE_SHIFT)) & CAAM_DDDR_CMD_STAGE_MASK)
17705 
17706 #define CAAM_DDDR_CMD_INDEX_MASK                 (0x3F00U)
17707 #define CAAM_DDDR_CMD_INDEX_SHIFT                (8U)
17708 #define CAAM_DDDR_CMD_INDEX(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CMD_INDEX_SHIFT)) & CAAM_DDDR_CMD_INDEX_MASK)
17709 
17710 #define CAAM_DDDR_NLJ_MASK                       (0x4000U)
17711 #define CAAM_DDDR_NLJ_SHIFT                      (14U)
17712 /*! NLJ
17713  *  0b0..The original job descriptor running in this DECO has not caused another job descriptor to be executed.
17714  *  0b1..The original job descriptor running in this DECO has caused another job descriptor to be executed.
17715  */
17716 #define CAAM_DDDR_NLJ(x)                         (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NLJ_SHIFT)) & CAAM_DDDR_NLJ_MASK)
17717 
17718 #define CAAM_DDDR_PTCL_RUN_MASK                  (0x8000U)
17719 #define CAAM_DDDR_PTCL_RUN_SHIFT                 (15U)
17720 /*! PTCL_RUN
17721  *  0b0..No protocol is running in this DECO.
17722  *  0b1..A protocol is running in this DECO.
17723  */
17724 #define CAAM_DDDR_PTCL_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PTCL_RUN_SHIFT)) & CAAM_DDDR_PTCL_RUN_MASK)
17725 
17726 #define CAAM_DDDR_PDB_STALL_MASK                 (0x30000U)
17727 #define CAAM_DDDR_PDB_STALL_SHIFT                (16U)
17728 #define CAAM_DDDR_PDB_STALL(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PDB_STALL_SHIFT)) & CAAM_DDDR_PDB_STALL_MASK)
17729 
17730 #define CAAM_DDDR_PDB_WB_ST_MASK                 (0xC0000U)
17731 #define CAAM_DDDR_PDB_WB_ST_SHIFT                (18U)
17732 #define CAAM_DDDR_PDB_WB_ST(x)                   (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PDB_WB_ST_SHIFT)) & CAAM_DDDR_PDB_WB_ST_MASK)
17733 
17734 #define CAAM_DDDR_DECO_STATE_MASK                (0xF00000U)
17735 #define CAAM_DDDR_DECO_STATE_SHIFT               (20U)
17736 #define CAAM_DDDR_DECO_STATE(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_DECO_STATE_SHIFT)) & CAAM_DDDR_DECO_STATE_MASK)
17737 
17738 #define CAAM_DDDR_NSEQLSEL_MASK                  (0x3000000U)
17739 #define CAAM_DDDR_NSEQLSEL_SHIFT                 (24U)
17740 /*! NSEQLSEL
17741  *  0b01..SEQ DID
17742  *  0b10..Non-SEQ DID
17743  *  0b11..Trusted DID
17744  */
17745 #define CAAM_DDDR_NSEQLSEL(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NSEQLSEL_SHIFT)) & CAAM_DDDR_NSEQLSEL_MASK)
17746 
17747 #define CAAM_DDDR_SEQLSEL_MASK                   (0xC000000U)
17748 #define CAAM_DDDR_SEQLSEL_SHIFT                  (26U)
17749 /*! SEQLSEL
17750  *  0b01..SEQ DID
17751  *  0b10..Non-SEQ DID
17752  *  0b11..Trusted DID
17753  */
17754 #define CAAM_DDDR_SEQLSEL(x)                     (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_SEQLSEL_SHIFT)) & CAAM_DDDR_SEQLSEL_MASK)
17755 
17756 #define CAAM_DDDR_TRCT_MASK                      (0x30000000U)
17757 #define CAAM_DDDR_TRCT_SHIFT                     (28U)
17758 #define CAAM_DDDR_TRCT(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_TRCT_SHIFT)) & CAAM_DDDR_TRCT_MASK)
17759 
17760 #define CAAM_DDDR_SD_MASK                        (0x40000000U)
17761 #define CAAM_DDDR_SD_SHIFT                       (30U)
17762 /*! SD
17763  *  0b0..This DECO has not received a shared descriptor from another DECO.
17764  *  0b1..This DECO has received a shared descriptor from another DECO.
17765  */
17766 #define CAAM_DDDR_SD(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_SD_SHIFT)) & CAAM_DDDR_SD_MASK)
17767 
17768 #define CAAM_DDDR_VALID_MASK                     (0x80000000U)
17769 #define CAAM_DDDR_VALID_SHIFT                    (31U)
17770 /*! VALID
17771  *  0b0..No descriptor is currently running in this DECO.
17772  *  0b1..There is currently a descriptor running in this DECO.
17773  */
17774 #define CAAM_DDDR_VALID(x)                       (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_VALID_SHIFT)) & CAAM_DDDR_VALID_MASK)
17775 /*! @} */
17776 
17777 /* The count of CAAM_DDDR */
17778 #define CAAM_DDDR_COUNT                          (1U)
17779 
17780 /*! @name DDJP - DECO0 Debug Job Pointer */
17781 /*! @{ */
17782 
17783 #define CAAM_DDJP_JDPTR_MASK                     (0xFFFFFFFFFU)
17784 #define CAAM_DDJP_JDPTR_SHIFT                    (0U)
17785 #define CAAM_DDJP_JDPTR(x)                       (((uint64_t)(((uint64_t)(x)) << CAAM_DDJP_JDPTR_SHIFT)) & CAAM_DDJP_JDPTR_MASK)
17786 /*! @} */
17787 
17788 /* The count of CAAM_DDJP */
17789 #define CAAM_DDJP_COUNT                          (1U)
17790 
17791 /*! @name DSDP - DECO0 Debug Shared Pointer */
17792 /*! @{ */
17793 
17794 #define CAAM_DSDP_SDPTR_MASK                     (0xFFFFFFFFFU)
17795 #define CAAM_DSDP_SDPTR_SHIFT                    (0U)
17796 #define CAAM_DSDP_SDPTR(x)                       (((uint64_t)(((uint64_t)(x)) << CAAM_DSDP_SDPTR_SHIFT)) & CAAM_DSDP_SDPTR_MASK)
17797 /*! @} */
17798 
17799 /* The count of CAAM_DSDP */
17800 #define CAAM_DSDP_COUNT                          (1U)
17801 
17802 /*! @name DDDR_MS - DECO0 Debug DID, most-significant half */
17803 /*! @{ */
17804 
17805 #define CAAM_DDDR_MS_PRIM_DID_MASK               (0xFU)
17806 #define CAAM_DDDR_MS_PRIM_DID_SHIFT              (0U)
17807 #define CAAM_DDDR_MS_PRIM_DID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_DID_SHIFT)) & CAAM_DDDR_MS_PRIM_DID_MASK)
17808 
17809 #define CAAM_DDDR_MS_PRIM_TZ_MASK                (0x10U)
17810 #define CAAM_DDDR_MS_PRIM_TZ_SHIFT               (4U)
17811 /*! PRIM_TZ
17812  *  0b0..TrustZone NonSecureWorld
17813  *  0b1..TrustZone SecureWorld
17814  */
17815 #define CAAM_DDDR_MS_PRIM_TZ(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_TZ_SHIFT)) & CAAM_DDDR_MS_PRIM_TZ_MASK)
17816 
17817 #define CAAM_DDDR_MS_PRIM_ICID_MASK              (0xFFE0U)
17818 #define CAAM_DDDR_MS_PRIM_ICID_SHIFT             (5U)
17819 #define CAAM_DDDR_MS_PRIM_ICID(x)                (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_ICID_SHIFT)) & CAAM_DDDR_MS_PRIM_ICID_MASK)
17820 
17821 #define CAAM_DDDR_MS_OUT_DID_MASK                (0xF0000U)
17822 #define CAAM_DDDR_MS_OUT_DID_SHIFT               (16U)
17823 #define CAAM_DDDR_MS_OUT_DID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_OUT_DID_SHIFT)) & CAAM_DDDR_MS_OUT_DID_MASK)
17824 
17825 #define CAAM_DDDR_MS_OUT_ICID_MASK               (0xFFE00000U)
17826 #define CAAM_DDDR_MS_OUT_ICID_SHIFT              (21U)
17827 #define CAAM_DDDR_MS_OUT_ICID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_OUT_ICID_SHIFT)) & CAAM_DDDR_MS_OUT_ICID_MASK)
17828 /*! @} */
17829 
17830 /* The count of CAAM_DDDR_MS */
17831 #define CAAM_DDDR_MS_COUNT                       (1U)
17832 
17833 /*! @name DDDR_LS - DECO0 Debug DID, least-significant half */
17834 /*! @{ */
17835 
17836 #define CAAM_DDDR_LS_OUT_DID_MASK                (0xFU)
17837 #define CAAM_DDDR_LS_OUT_DID_SHIFT               (0U)
17838 #define CAAM_DDDR_LS_OUT_DID(x)                  (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_LS_OUT_DID_SHIFT)) & CAAM_DDDR_LS_OUT_DID_MASK)
17839 
17840 #define CAAM_DDDR_LS_OUT_ICID_MASK               (0x3FF80000U)
17841 #define CAAM_DDDR_LS_OUT_ICID_SHIFT              (19U)
17842 #define CAAM_DDDR_LS_OUT_ICID(x)                 (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_LS_OUT_ICID_SHIFT)) & CAAM_DDDR_LS_OUT_ICID_MASK)
17843 /*! @} */
17844 
17845 /* The count of CAAM_DDDR_LS */
17846 #define CAAM_DDDR_LS_COUNT                       (1U)
17847 
17848 /*! @name SOL - Sequence Output Length Register */
17849 /*! @{ */
17850 
17851 #define CAAM_SOL_SOL_MASK                        (0xFFFFFFFFU)
17852 #define CAAM_SOL_SOL_SHIFT                       (0U)
17853 #define CAAM_SOL_SOL(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_SOL_SOL_SHIFT)) & CAAM_SOL_SOL_MASK)
17854 /*! @} */
17855 
17856 /* The count of CAAM_SOL */
17857 #define CAAM_SOL_COUNT                           (1U)
17858 
17859 /*! @name VSOL - Variable Sequence Output Length Register */
17860 /*! @{ */
17861 
17862 #define CAAM_VSOL_VSOL_MASK                      (0xFFFFFFFFU)
17863 #define CAAM_VSOL_VSOL_SHIFT                     (0U)
17864 #define CAAM_VSOL_VSOL(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_VSOL_VSOL_SHIFT)) & CAAM_VSOL_VSOL_MASK)
17865 /*! @} */
17866 
17867 /* The count of CAAM_VSOL */
17868 #define CAAM_VSOL_COUNT                          (1U)
17869 
17870 /*! @name SIL - Sequence Input Length Register */
17871 /*! @{ */
17872 
17873 #define CAAM_SIL_SIL_MASK                        (0xFFFFFFFFU)
17874 #define CAAM_SIL_SIL_SHIFT                       (0U)
17875 #define CAAM_SIL_SIL(x)                          (((uint32_t)(((uint32_t)(x)) << CAAM_SIL_SIL_SHIFT)) & CAAM_SIL_SIL_MASK)
17876 /*! @} */
17877 
17878 /* The count of CAAM_SIL */
17879 #define CAAM_SIL_COUNT                           (1U)
17880 
17881 /*! @name VSIL - Variable Sequence Input Length Register */
17882 /*! @{ */
17883 
17884 #define CAAM_VSIL_VSIL_MASK                      (0xFFFFFFFFU)
17885 #define CAAM_VSIL_VSIL_SHIFT                     (0U)
17886 #define CAAM_VSIL_VSIL(x)                        (((uint32_t)(((uint32_t)(x)) << CAAM_VSIL_VSIL_SHIFT)) & CAAM_VSIL_VSIL_MASK)
17887 /*! @} */
17888 
17889 /* The count of CAAM_VSIL */
17890 #define CAAM_VSIL_COUNT                          (1U)
17891 
17892 /*! @name DPOVRD - Protocol Override Register */
17893 /*! @{ */
17894 
17895 #define CAAM_DPOVRD_DPOVRD_MASK                  (0xFFFFFFFFU)
17896 #define CAAM_DPOVRD_DPOVRD_SHIFT                 (0U)
17897 #define CAAM_DPOVRD_DPOVRD(x)                    (((uint32_t)(((uint32_t)(x)) << CAAM_DPOVRD_DPOVRD_SHIFT)) & CAAM_DPOVRD_DPOVRD_MASK)
17898 /*! @} */
17899 
17900 /* The count of CAAM_DPOVRD */
17901 #define CAAM_DPOVRD_COUNT                        (1U)
17902 
17903 /*! @name UVSOL - Variable Sequence Output Length Register; Upper 32 bits */
17904 /*! @{ */
17905 
17906 #define CAAM_UVSOL_UVSOL_MASK                    (0xFFFFFFFFU)
17907 #define CAAM_UVSOL_UVSOL_SHIFT                   (0U)
17908 #define CAAM_UVSOL_UVSOL(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_UVSOL_UVSOL_SHIFT)) & CAAM_UVSOL_UVSOL_MASK)
17909 /*! @} */
17910 
17911 /* The count of CAAM_UVSOL */
17912 #define CAAM_UVSOL_COUNT                         (1U)
17913 
17914 /*! @name UVSIL - Variable Sequence Input Length Register; Upper 32 bits */
17915 /*! @{ */
17916 
17917 #define CAAM_UVSIL_UVSIL_MASK                    (0xFFFFFFFFU)
17918 #define CAAM_UVSIL_UVSIL_SHIFT                   (0U)
17919 #define CAAM_UVSIL_UVSIL(x)                      (((uint32_t)(((uint32_t)(x)) << CAAM_UVSIL_UVSIL_SHIFT)) & CAAM_UVSIL_UVSIL_MASK)
17920 /*! @} */
17921 
17922 /* The count of CAAM_UVSIL */
17923 #define CAAM_UVSIL_COUNT                         (1U)
17924 
17925 
17926 /*!
17927  * @}
17928  */ /* end of group CAAM_Register_Masks */
17929 
17930 
17931 /* CAAM - Peripheral instance base addresses */
17932 /** Peripheral CAAM base address */
17933 #define CAAM_BASE                                (0x40440000u)
17934 /** Peripheral CAAM base pointer */
17935 #define CAAM                                     ((CAAM_Type *)CAAM_BASE)
17936 /** Array initializer of CAAM peripheral base addresses */
17937 #define CAAM_BASE_ADDRS                          { CAAM_BASE }
17938 /** Array initializer of CAAM peripheral base pointers */
17939 #define CAAM_BASE_PTRS                           { CAAM }
17940 
17941 /*!
17942  * @}
17943  */ /* end of group CAAM_Peripheral_Access_Layer */
17944 
17945 
17946 /* ----------------------------------------------------------------------------
17947    -- CAN Peripheral Access Layer
17948    ---------------------------------------------------------------------------- */
17949 
17950 /*!
17951  * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
17952  * @{
17953  */
17954 
17955 /** CAN - Register Layout Typedef */
17956 typedef struct {
17957   __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
17958   __IO uint32_t CTRL1;                             /**< Control 1 Register, offset: 0x4 */
17959   __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
17960        uint8_t RESERVED_0[4];
17961   __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
17962   __IO uint32_t RX14MASK;                          /**< Rx 14 Mask Register, offset: 0x14 */
17963   __IO uint32_t RX15MASK;                          /**< Rx 15 Mask Register, offset: 0x18 */
17964   __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
17965   __IO uint32_t ESR1;                              /**< Error and Status 1 Register, offset: 0x20 */
17966   __IO uint32_t IMASK2;                            /**< Interrupt Masks 2 Register, offset: 0x24 */
17967   __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 Register, offset: 0x28 */
17968   __IO uint32_t IFLAG2;                            /**< Interrupt Flags 2 Register, offset: 0x2C */
17969   __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 Register, offset: 0x30 */
17970   __IO uint32_t CTRL2;                             /**< Control 2 Register, offset: 0x34 */
17971   __I  uint32_t ESR2;                              /**< Error and Status 2 Register, offset: 0x38 */
17972        uint8_t RESERVED_1[8];
17973   __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
17974   __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask Register, offset: 0x48 */
17975   __I  uint32_t RXFIR;                             /**< Rx FIFO Information Register, offset: 0x4C */
17976   __IO uint32_t CBT;                               /**< CAN Bit Timing Register, offset: 0x50 */
17977        uint8_t RESERVED_2[44];
17978   union {                                          /* offset: 0x80 */
17979     struct {                                         /* offset: 0x80, array step: 0x10 */
17980       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
17981       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
17982       __IO uint32_t WORD[2];                           /**< Message Buffer 0 WORD_8B Register..Message Buffer 63 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */
17983     } MB_8B[64];
17984     struct {                                         /* offset: 0x80 */
17985       struct {                                         /* offset: 0x80, array step: 0x18 */
17986         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18 */
17987         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18 */
17988         __IO uint32_t WORD[4];                           /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */
17989       } MB_16B_L[21];
17990            uint8_t RESERVED_0[8];
17991       struct {                                         /* offset: 0x280, array step: 0x18 */
17992         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x280, array step: 0x18 */
17993         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x284, array step: 0x18 */
17994         __IO uint32_t WORD[4];                           /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x288, array step: index*0x18, index2*0x4 */
17995       } MB_16B_H[21];
17996     } MB_16B;
17997     struct {                                         /* offset: 0x80 */
17998       struct {                                         /* offset: 0x80, array step: 0x28 */
17999         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28 */
18000         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28 */
18001         __IO uint32_t WORD[8];                           /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */
18002       } MB_32B_L[12];
18003            uint8_t RESERVED_0[32];
18004       struct {                                         /* offset: 0x280, array step: 0x28 */
18005         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x280, array step: 0x28 */
18006         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x284, array step: 0x28 */
18007         __IO uint32_t WORD[8];                           /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x288, array step: index*0x28, index2*0x4 */
18008       } MB_32B_H[12];
18009     } MB_32B;
18010     struct {                                         /* offset: 0x80 */
18011       struct {                                         /* offset: 0x80, array step: 0x48 */
18012         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48 */
18013         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48 */
18014         __IO uint32_t WORD[16];                          /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */
18015       } MB_64B_L[7];
18016            uint8_t RESERVED_0[8];
18017       struct {                                         /* offset: 0x280, array step: 0x48 */
18018         __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x280, array step: 0x48 */
18019         __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x284, array step: 0x48 */
18020         __IO uint32_t WORD[16];                          /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x288, array step: index*0x48, index2*0x4 */
18021       } MB_64B_H[7];
18022     } MB_64B;
18023     struct {                                         /* offset: 0x80, array step: 0x10 */
18024       __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
18025       __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
18026       __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
18027       __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
18028     } MB[64];
18029   };
18030        uint8_t RESERVED_3[1024];
18031   __IO uint32_t RXIMR[64];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
18032        uint8_t RESERVED_4[352];
18033   __IO uint32_t MECR;                              /**< Memory Error Control Register, offset: 0xAE0 */
18034   __IO uint32_t ERRIAR;                            /**< Error Injection Address Register, offset: 0xAE4 */
18035   __IO uint32_t ERRIDPR;                           /**< Error Injection Data Pattern Register, offset: 0xAE8 */
18036   __IO uint32_t ERRIPPR;                           /**< Error Injection Parity Pattern Register, offset: 0xAEC */
18037   __I  uint32_t RERRAR;                            /**< Error Report Address Register, offset: 0xAF0 */
18038   __I  uint32_t RERRDR;                            /**< Error Report Data Register, offset: 0xAF4 */
18039   __I  uint32_t RERRSYNR;                          /**< Error Report Syndrome Register, offset: 0xAF8 */
18040   __IO uint32_t ERRSR;                             /**< Error Status Register, offset: 0xAFC */
18041        uint8_t RESERVED_5[256];
18042   __IO uint32_t FDCTRL;                            /**< CAN FD Control Register, offset: 0xC00 */
18043   __IO uint32_t FDCBT;                             /**< CAN FD Bit Timing Register, offset: 0xC04 */
18044   __I  uint32_t FDCRC;                             /**< CAN FD CRC Register, offset: 0xC08 */
18045 } CAN_Type;
18046 
18047 /* ----------------------------------------------------------------------------
18048    -- CAN Register Masks
18049    ---------------------------------------------------------------------------- */
18050 
18051 /*!
18052  * @addtogroup CAN_Register_Masks CAN Register Masks
18053  * @{
18054  */
18055 
18056 /*! @name MCR - Module Configuration Register */
18057 /*! @{ */
18058 
18059 #define CAN_MCR_MAXMB_MASK                       (0x7FU)
18060 #define CAN_MCR_MAXMB_SHIFT                      (0U)
18061 /*! MAXMB - Number Of The Last Message Buffer */
18062 #define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
18063 
18064 #define CAN_MCR_IDAM_MASK                        (0x300U)
18065 #define CAN_MCR_IDAM_SHIFT                       (8U)
18066 /*! IDAM - ID Acceptance Mode
18067  *  0b00..Format A: One full ID (standard and extended) per ID filter table element.
18068  *  0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
18069  *  0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
18070  *  0b11..Format D: All frames rejected.
18071  */
18072 #define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
18073 
18074 #define CAN_MCR_FDEN_MASK                        (0x800U)
18075 #define CAN_MCR_FDEN_SHIFT                       (11U)
18076 /*! FDEN - CAN FD operation enable
18077  *  0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
18078  *  0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
18079  */
18080 #define CAN_MCR_FDEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
18081 
18082 #define CAN_MCR_AEN_MASK                         (0x1000U)
18083 #define CAN_MCR_AEN_SHIFT                        (12U)
18084 /*! AEN - Abort Enable
18085  *  0b0..Abort disabled.
18086  *  0b1..Abort enabled.
18087  */
18088 #define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
18089 
18090 #define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
18091 #define CAN_MCR_LPRIOEN_SHIFT                    (13U)
18092 /*! LPRIOEN - Local Priority Enable
18093  *  0b0..Local Priority disabled.
18094  *  0b1..Local Priority enabled.
18095  */
18096 #define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
18097 
18098 #define CAN_MCR_DMA_MASK                         (0x8000U)
18099 #define CAN_MCR_DMA_SHIFT                        (15U)
18100 /*! DMA - DMA Enable
18101  *  0b0..DMA feature for RX FIFO disabled.
18102  *  0b1..DMA feature for RX FIFO enabled.
18103  */
18104 #define CAN_MCR_DMA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
18105 
18106 #define CAN_MCR_IRMQ_MASK                        (0x10000U)
18107 #define CAN_MCR_IRMQ_SHIFT                       (16U)
18108 /*! IRMQ - Individual Rx Masking And Queue Enable
18109  *  0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy
18110  *       applications, the reading of C/S word locks the MB even if it is EMPTY.
18111  *  0b1..Individual Rx masking and queue feature are enabled.
18112  */
18113 #define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
18114 
18115 #define CAN_MCR_SRXDIS_MASK                      (0x20000U)
18116 #define CAN_MCR_SRXDIS_SHIFT                     (17U)
18117 /*! SRXDIS - Self Reception Disable
18118  *  0b0..Self-reception enabled.
18119  *  0b1..Self-reception disabled.
18120  */
18121 #define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
18122 
18123 #define CAN_MCR_DOZE_MASK                        (0x40000U)
18124 #define CAN_MCR_DOZE_SHIFT                       (18U)
18125 /*! DOZE - Doze Mode Enable
18126  *  0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
18127  *  0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
18128  */
18129 #define CAN_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
18130 
18131 #define CAN_MCR_WAKSRC_MASK                      (0x80000U)
18132 #define CAN_MCR_WAKSRC_SHIFT                     (19U)
18133 /*! WAKSRC - Wake Up Source
18134  *  0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
18135  *  0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
18136  */
18137 #define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
18138 
18139 #define CAN_MCR_LPMACK_MASK                      (0x100000U)
18140 #define CAN_MCR_LPMACK_SHIFT                     (20U)
18141 /*! LPMACK - Low-Power Mode Acknowledge
18142  *  0b0..FlexCAN is not in a low-power mode.
18143  *  0b1..FlexCAN is in a low-power mode.
18144  */
18145 #define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
18146 
18147 #define CAN_MCR_WRNEN_MASK                       (0x200000U)
18148 #define CAN_MCR_WRNEN_SHIFT                      (21U)
18149 /*! WRNEN - Warning Interrupt Enable
18150  *  0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
18151  *  0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
18152  */
18153 #define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
18154 
18155 #define CAN_MCR_SLFWAK_MASK                      (0x400000U)
18156 #define CAN_MCR_SLFWAK_SHIFT                     (22U)
18157 /*! SLFWAK - Self Wake Up
18158  *  0b0..FlexCAN Self Wake Up feature is disabled.
18159  *  0b1..FlexCAN Self Wake Up feature is enabled.
18160  */
18161 #define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
18162 
18163 #define CAN_MCR_SUPV_MASK                        (0x800000U)
18164 #define CAN_MCR_SUPV_SHIFT                       (23U)
18165 /*! SUPV - Supervisor Mode
18166  *  0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses.
18167  *  0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access
18168  *       behaves as though the access was done to an unimplemented register location.
18169  */
18170 #define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
18171 
18172 #define CAN_MCR_FRZACK_MASK                      (0x1000000U)
18173 #define CAN_MCR_FRZACK_SHIFT                     (24U)
18174 /*! FRZACK - Freeze Mode Acknowledge
18175  *  0b0..FlexCAN not in Freeze mode, prescaler running.
18176  *  0b1..FlexCAN in Freeze mode, prescaler stopped.
18177  */
18178 #define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
18179 
18180 #define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
18181 #define CAN_MCR_SOFTRST_SHIFT                    (25U)
18182 /*! SOFTRST - Soft Reset
18183  *  0b0..No reset request.
18184  *  0b1..Resets the registers affected by soft reset.
18185  */
18186 #define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
18187 
18188 #define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
18189 #define CAN_MCR_WAKMSK_SHIFT                     (26U)
18190 /*! WAKMSK - Wake Up Interrupt Mask
18191  *  0b0..Wake Up interrupt is disabled.
18192  *  0b1..Wake Up interrupt is enabled.
18193  */
18194 #define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
18195 
18196 #define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
18197 #define CAN_MCR_NOTRDY_SHIFT                     (27U)
18198 /*! NOTRDY - FlexCAN Not Ready
18199  *  0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode.
18200  *  0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.
18201  */
18202 #define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
18203 
18204 #define CAN_MCR_HALT_MASK                        (0x10000000U)
18205 #define CAN_MCR_HALT_SHIFT                       (28U)
18206 /*! HALT - Halt FlexCAN
18207  *  0b0..No Freeze mode request.
18208  *  0b1..Enters Freeze mode if the FRZ bit is asserted.
18209  */
18210 #define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
18211 
18212 #define CAN_MCR_RFEN_MASK                        (0x20000000U)
18213 #define CAN_MCR_RFEN_SHIFT                       (29U)
18214 /*! RFEN - Rx FIFO Enable
18215  *  0b0..Rx FIFO not enabled.
18216  *  0b1..Rx FIFO enabled.
18217  */
18218 #define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
18219 
18220 #define CAN_MCR_FRZ_MASK                         (0x40000000U)
18221 #define CAN_MCR_FRZ_SHIFT                        (30U)
18222 /*! FRZ - Freeze Enable
18223  *  0b0..Not enabled to enter Freeze mode.
18224  *  0b1..Enabled to enter Freeze mode.
18225  */
18226 #define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
18227 
18228 #define CAN_MCR_MDIS_MASK                        (0x80000000U)
18229 #define CAN_MCR_MDIS_SHIFT                       (31U)
18230 /*! MDIS - Module Disable
18231  *  0b0..Enable the FlexCAN module.
18232  *  0b1..Disable the FlexCAN module.
18233  */
18234 #define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
18235 /*! @} */
18236 
18237 /*! @name CTRL1 - Control 1 Register */
18238 /*! @{ */
18239 
18240 #define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
18241 #define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
18242 /*! PROPSEG - Propagation Segment */
18243 #define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
18244 
18245 #define CAN_CTRL1_LOM_MASK                       (0x8U)
18246 #define CAN_CTRL1_LOM_SHIFT                      (3U)
18247 /*! LOM - Listen-Only Mode
18248  *  0b0..Listen-Only mode is deactivated.
18249  *  0b1..FlexCAN module operates in Listen-Only mode.
18250  */
18251 #define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
18252 
18253 #define CAN_CTRL1_LBUF_MASK                      (0x10U)
18254 #define CAN_CTRL1_LBUF_SHIFT                     (4U)
18255 /*! LBUF - Lowest Buffer Transmitted First
18256  *  0b0..Buffer with highest priority is transmitted first.
18257  *  0b1..Lowest number buffer is transmitted first.
18258  */
18259 #define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
18260 
18261 #define CAN_CTRL1_TSYN_MASK                      (0x20U)
18262 #define CAN_CTRL1_TSYN_SHIFT                     (5U)
18263 /*! TSYN - Timer Sync
18264  *  0b0..Timer sync feature disabled
18265  *  0b1..Timer sync feature enabled
18266  */
18267 #define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
18268 
18269 #define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
18270 #define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
18271 /*! BOFFREC - Bus Off Recovery
18272  *  0b0..Automatic recovering from Bus Off state enabled.
18273  *  0b1..Automatic recovering from Bus Off state disabled.
18274  */
18275 #define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
18276 
18277 #define CAN_CTRL1_SMP_MASK                       (0x80U)
18278 #define CAN_CTRL1_SMP_SHIFT                      (7U)
18279 /*! SMP - CAN Bit Sampling
18280  *  0b0..Just one sample is used to determine the bit value.
18281  *  0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
18282  *       preceding samples; a majority rule is used.
18283  */
18284 #define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
18285 
18286 #define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
18287 #define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
18288 /*! RWRNMSK - Rx Warning Interrupt Mask
18289  *  0b0..Rx Warning interrupt disabled.
18290  *  0b1..Rx Warning interrupt enabled.
18291  */
18292 #define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
18293 
18294 #define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
18295 #define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
18296 /*! TWRNMSK - Tx Warning Interrupt Mask
18297  *  0b0..Tx Warning interrupt disabled.
18298  *  0b1..Tx Warning interrupt enabled.
18299  */
18300 #define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
18301 
18302 #define CAN_CTRL1_LPB_MASK                       (0x1000U)
18303 #define CAN_CTRL1_LPB_SHIFT                      (12U)
18304 /*! LPB - Loop Back Mode
18305  *  0b0..Loop Back disabled.
18306  *  0b1..Loop Back enabled.
18307  */
18308 #define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
18309 
18310 #define CAN_CTRL1_CLKSRC_MASK                    (0x2000U)
18311 #define CAN_CTRL1_CLKSRC_SHIFT                   (13U)
18312 /*! CLKSRC - CAN Engine Clock Source
18313  *  0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
18314  *  0b1..The CAN engine clock source is the peripheral clock.
18315  */
18316 #define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
18317 
18318 #define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
18319 #define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
18320 /*! ERRMSK - Error Interrupt Mask
18321  *  0b0..Error interrupt disabled.
18322  *  0b1..Error interrupt enabled.
18323  */
18324 #define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
18325 
18326 #define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
18327 #define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
18328 /*! BOFFMSK - Bus Off Interrupt Mask
18329  *  0b0..Bus Off interrupt disabled.
18330  *  0b1..Bus Off interrupt enabled.
18331  */
18332 #define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
18333 
18334 #define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
18335 #define CAN_CTRL1_PSEG2_SHIFT                    (16U)
18336 /*! PSEG2 - Phase Segment 2 */
18337 #define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
18338 
18339 #define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
18340 #define CAN_CTRL1_PSEG1_SHIFT                    (19U)
18341 /*! PSEG1 - Phase Segment 1 */
18342 #define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
18343 
18344 #define CAN_CTRL1_RJW_MASK                       (0xC00000U)
18345 #define CAN_CTRL1_RJW_SHIFT                      (22U)
18346 /*! RJW - Resync Jump Width */
18347 #define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
18348 
18349 #define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
18350 #define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
18351 /*! PRESDIV - Prescaler Division Factor */
18352 #define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
18353 /*! @} */
18354 
18355 /*! @name TIMER - Free Running Timer */
18356 /*! @{ */
18357 
18358 #define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
18359 #define CAN_TIMER_TIMER_SHIFT                    (0U)
18360 /*! TIMER - Timer Value */
18361 #define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
18362 /*! @} */
18363 
18364 /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
18365 /*! @{ */
18366 
18367 #define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
18368 #define CAN_RXMGMASK_MG_SHIFT                    (0U)
18369 /*! MG - Rx Mailboxes Global Mask Bits */
18370 #define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
18371 /*! @} */
18372 
18373 /*! @name RX14MASK - Rx 14 Mask Register */
18374 /*! @{ */
18375 
18376 #define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
18377 #define CAN_RX14MASK_RX14M_SHIFT                 (0U)
18378 /*! RX14M - Rx Buffer 14 Mask Bits */
18379 #define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
18380 /*! @} */
18381 
18382 /*! @name RX15MASK - Rx 15 Mask Register */
18383 /*! @{ */
18384 
18385 #define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
18386 #define CAN_RX15MASK_RX15M_SHIFT                 (0U)
18387 /*! RX15M - Rx Buffer 15 Mask Bits */
18388 #define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
18389 /*! @} */
18390 
18391 /*! @name ECR - Error Counter */
18392 /*! @{ */
18393 
18394 #define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
18395 #define CAN_ECR_TXERRCNT_SHIFT                   (0U)
18396 /*! TXERRCNT - Transmit Error Counter */
18397 #define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
18398 
18399 #define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
18400 #define CAN_ECR_RXERRCNT_SHIFT                   (8U)
18401 /*! RXERRCNT - Receive Error Counter */
18402 #define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
18403 
18404 #define CAN_ECR_TXERRCNT_FAST_MASK               (0xFF0000U)
18405 #define CAN_ECR_TXERRCNT_FAST_SHIFT              (16U)
18406 /*! TXERRCNT_FAST - Transmit Error Counter for fast bits */
18407 #define CAN_ECR_TXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
18408 
18409 #define CAN_ECR_RXERRCNT_FAST_MASK               (0xFF000000U)
18410 #define CAN_ECR_RXERRCNT_FAST_SHIFT              (24U)
18411 /*! RXERRCNT_FAST - Receive Error Counter for fast bits */
18412 #define CAN_ECR_RXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
18413 /*! @} */
18414 
18415 /*! @name ESR1 - Error and Status 1 Register */
18416 /*! @{ */
18417 
18418 #define CAN_ESR1_WAKINT_MASK                     (0x1U)
18419 #define CAN_ESR1_WAKINT_SHIFT                    (0U)
18420 /*! WAKINT - Wake-Up Interrupt
18421  *  0b0..No such occurrence.
18422  *  0b1..Indicates a recessive to dominant transition was received on the CAN bus.
18423  */
18424 #define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
18425 
18426 #define CAN_ESR1_ERRINT_MASK                     (0x2U)
18427 #define CAN_ESR1_ERRINT_SHIFT                    (1U)
18428 /*! ERRINT - Error Interrupt
18429  *  0b0..No such occurrence.
18430  *  0b1..Indicates setting of any error bit in the Error and Status register.
18431  */
18432 #define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
18433 
18434 #define CAN_ESR1_BOFFINT_MASK                    (0x4U)
18435 #define CAN_ESR1_BOFFINT_SHIFT                   (2U)
18436 /*! BOFFINT - Bus Off Interrupt
18437  *  0b0..No such occurrence.
18438  *  0b1..FlexCAN module entered Bus Off state.
18439  */
18440 #define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
18441 
18442 #define CAN_ESR1_RX_MASK                         (0x8U)
18443 #define CAN_ESR1_RX_SHIFT                        (3U)
18444 /*! RX - FlexCAN In Reception
18445  *  0b0..FlexCAN is not receiving a message.
18446  *  0b1..FlexCAN is receiving a message.
18447  */
18448 #define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
18449 
18450 #define CAN_ESR1_FLTCONF_MASK                    (0x30U)
18451 #define CAN_ESR1_FLTCONF_SHIFT                   (4U)
18452 /*! FLTCONF - Fault Confinement State
18453  *  0b00..Error Active
18454  *  0b01..Error Passive
18455  *  0b1x..Bus Off
18456  */
18457 #define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
18458 
18459 #define CAN_ESR1_TX_MASK                         (0x40U)
18460 #define CAN_ESR1_TX_SHIFT                        (6U)
18461 /*! TX - FlexCAN In Transmission
18462  *  0b0..FlexCAN is not transmitting a message.
18463  *  0b1..FlexCAN is transmitting a message.
18464  */
18465 #define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
18466 
18467 #define CAN_ESR1_IDLE_MASK                       (0x80U)
18468 #define CAN_ESR1_IDLE_SHIFT                      (7U)
18469 /*! IDLE - IDLE
18470  *  0b0..No such occurrence.
18471  *  0b1..CAN bus is now IDLE.
18472  */
18473 #define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
18474 
18475 #define CAN_ESR1_RXWRN_MASK                      (0x100U)
18476 #define CAN_ESR1_RXWRN_SHIFT                     (8U)
18477 /*! RXWRN - Rx Error Warning
18478  *  0b0..No such occurrence.
18479  *  0b1..RXERRCNT is greater than or equal to 96.
18480  */
18481 #define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
18482 
18483 #define CAN_ESR1_TXWRN_MASK                      (0x200U)
18484 #define CAN_ESR1_TXWRN_SHIFT                     (9U)
18485 /*! TXWRN - TX Error Warning
18486  *  0b0..No such occurrence.
18487  *  0b1..TXERRCNT is greater than or equal to 96.
18488  */
18489 #define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
18490 
18491 #define CAN_ESR1_STFERR_MASK                     (0x400U)
18492 #define CAN_ESR1_STFERR_SHIFT                    (10U)
18493 /*! STFERR - Stuffing Error
18494  *  0b0..No such occurrence.
18495  *  0b1..A stuffing error occurred since last read of this register.
18496  */
18497 #define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
18498 
18499 #define CAN_ESR1_FRMERR_MASK                     (0x800U)
18500 #define CAN_ESR1_FRMERR_SHIFT                    (11U)
18501 /*! FRMERR - Form Error
18502  *  0b0..No such occurrence.
18503  *  0b1..A Form Error occurred since last read of this register.
18504  */
18505 #define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
18506 
18507 #define CAN_ESR1_CRCERR_MASK                     (0x1000U)
18508 #define CAN_ESR1_CRCERR_SHIFT                    (12U)
18509 /*! CRCERR - Cyclic Redundancy Check Error
18510  *  0b0..No such occurrence.
18511  *  0b1..A CRC error occurred since last read of this register.
18512  */
18513 #define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
18514 
18515 #define CAN_ESR1_ACKERR_MASK                     (0x2000U)
18516 #define CAN_ESR1_ACKERR_SHIFT                    (13U)
18517 /*! ACKERR - Acknowledge Error
18518  *  0b0..No such occurrence.
18519  *  0b1..An ACK error occurred since last read of this register.
18520  */
18521 #define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
18522 
18523 #define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
18524 #define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
18525 /*! BIT0ERR - Bit0 Error
18526  *  0b0..No such occurrence.
18527  *  0b1..At least one bit sent as dominant is received as recessive.
18528  */
18529 #define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
18530 
18531 #define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
18532 #define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
18533 /*! BIT1ERR - Bit1 Error
18534  *  0b0..No such occurrence.
18535  *  0b1..At least one bit sent as recessive is received as dominant.
18536  */
18537 #define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
18538 
18539 #define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
18540 #define CAN_ESR1_RWRNINT_SHIFT                   (16U)
18541 /*! RWRNINT - Rx Warning Interrupt Flag
18542  *  0b0..No such occurrence.
18543  *  0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
18544  */
18545 #define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
18546 
18547 #define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
18548 #define CAN_ESR1_TWRNINT_SHIFT                   (17U)
18549 /*! TWRNINT - Tx Warning Interrupt Flag
18550  *  0b0..No such occurrence.
18551  *  0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
18552  */
18553 #define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
18554 
18555 #define CAN_ESR1_SYNCH_MASK                      (0x40000U)
18556 #define CAN_ESR1_SYNCH_SHIFT                     (18U)
18557 /*! SYNCH - CAN Synchronization Status
18558  *  0b0..FlexCAN is not synchronized to the CAN bus.
18559  *  0b1..FlexCAN is synchronized to the CAN bus.
18560  */
18561 #define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
18562 
18563 #define CAN_ESR1_BOFFDONEINT_MASK                (0x80000U)
18564 #define CAN_ESR1_BOFFDONEINT_SHIFT               (19U)
18565 /*! BOFFDONEINT - Bus Off Done Interrupt
18566  *  0b0..No such occurrence.
18567  *  0b1..FlexCAN module has completed Bus Off process.
18568  */
18569 #define CAN_ESR1_BOFFDONEINT(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
18570 
18571 #define CAN_ESR1_ERRINT_FAST_MASK                (0x100000U)
18572 #define CAN_ESR1_ERRINT_FAST_SHIFT               (20U)
18573 /*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set
18574  *  0b0..No such occurrence.
18575  *  0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.
18576  */
18577 #define CAN_ESR1_ERRINT_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
18578 
18579 #define CAN_ESR1_ERROVR_MASK                     (0x200000U)
18580 #define CAN_ESR1_ERROVR_SHIFT                    (21U)
18581 /*! ERROVR - Error Overrun
18582  *  0b0..Overrun has not occurred.
18583  *  0b1..Overrun has occurred.
18584  */
18585 #define CAN_ESR1_ERROVR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
18586 
18587 #define CAN_ESR1_STFERR_FAST_MASK                (0x4000000U)
18588 #define CAN_ESR1_STFERR_FAST_SHIFT               (26U)
18589 /*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
18590  *  0b0..No such occurrence.
18591  *  0b1..A stuffing error occurred since last read of this register.
18592  */
18593 #define CAN_ESR1_STFERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
18594 
18595 #define CAN_ESR1_FRMERR_FAST_MASK                (0x8000000U)
18596 #define CAN_ESR1_FRMERR_FAST_SHIFT               (27U)
18597 /*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
18598  *  0b0..No such occurrence.
18599  *  0b1..A form error occurred since last read of this register.
18600  */
18601 #define CAN_ESR1_FRMERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
18602 
18603 #define CAN_ESR1_CRCERR_FAST_MASK                (0x10000000U)
18604 #define CAN_ESR1_CRCERR_FAST_SHIFT               (28U)
18605 /*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
18606  *  0b0..No such occurrence.
18607  *  0b1..A CRC error occurred since last read of this register.
18608  */
18609 #define CAN_ESR1_CRCERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
18610 
18611 #define CAN_ESR1_BIT0ERR_FAST_MASK               (0x40000000U)
18612 #define CAN_ESR1_BIT0ERR_FAST_SHIFT              (30U)
18613 /*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
18614  *  0b0..No such occurrence.
18615  *  0b1..At least one bit sent as dominant is received as recessive.
18616  */
18617 #define CAN_ESR1_BIT0ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
18618 
18619 #define CAN_ESR1_BIT1ERR_FAST_MASK               (0x80000000U)
18620 #define CAN_ESR1_BIT1ERR_FAST_SHIFT              (31U)
18621 /*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
18622  *  0b0..No such occurrence.
18623  *  0b1..At least one bit sent as recessive is received as dominant.
18624  */
18625 #define CAN_ESR1_BIT1ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
18626 /*! @} */
18627 
18628 /*! @name IMASK2 - Interrupt Masks 2 Register */
18629 /*! @{ */
18630 
18631 #define CAN_IMASK2_BUF63TO32M_MASK               (0xFFFFFFFFU)
18632 #define CAN_IMASK2_BUF63TO32M_SHIFT              (0U)
18633 /*! BUF63TO32M - Buffer MBi Mask */
18634 #define CAN_IMASK2_BUF63TO32M(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
18635 /*! @} */
18636 
18637 /*! @name IMASK1 - Interrupt Masks 1 Register */
18638 /*! @{ */
18639 
18640 #define CAN_IMASK1_BUF31TO0M_MASK                (0xFFFFFFFFU)
18641 #define CAN_IMASK1_BUF31TO0M_SHIFT               (0U)
18642 /*! BUF31TO0M - Buffer MBi Mask */
18643 #define CAN_IMASK1_BUF31TO0M(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
18644 /*! @} */
18645 
18646 /*! @name IFLAG2 - Interrupt Flags 2 Register */
18647 /*! @{ */
18648 
18649 #define CAN_IFLAG2_BUF63TO32I_MASK               (0xFFFFFFFFU)
18650 #define CAN_IFLAG2_BUF63TO32I_SHIFT              (0U)
18651 /*! BUF63TO32I - Buffer MBi Interrupt */
18652 #define CAN_IFLAG2_BUF63TO32I(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
18653 /*! @} */
18654 
18655 /*! @name IFLAG1 - Interrupt Flags 1 Register */
18656 /*! @{ */
18657 
18658 #define CAN_IFLAG1_BUF0I_MASK                    (0x1U)
18659 #define CAN_IFLAG1_BUF0I_SHIFT                   (0U)
18660 /*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit
18661  *  0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
18662  *  0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
18663  */
18664 #define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
18665 
18666 #define CAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)
18667 #define CAN_IFLAG1_BUF4TO1I_SHIFT                (1U)
18668 /*! BUF4TO1I - Buffer MBi Interrupt Or Reserved */
18669 #define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
18670 
18671 #define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
18672 #define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
18673 /*! BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO
18674  *  0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
18675  *  0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when
18676  *       MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
18677  */
18678 #define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
18679 
18680 #define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
18681 #define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
18682 /*! BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning
18683  *  0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
18684  *  0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
18685  */
18686 #define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
18687 
18688 #define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
18689 #define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
18690 /*! BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow
18691  *  0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
18692  *  0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
18693  */
18694 #define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
18695 
18696 #define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
18697 #define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
18698 /*! BUF31TO8I - Buffer MBi Interrupt */
18699 #define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
18700 /*! @} */
18701 
18702 /*! @name CTRL2 - Control 2 Register */
18703 /*! @{ */
18704 
18705 #define CAN_CTRL2_EDFLTDIS_MASK                  (0x800U)
18706 #define CAN_CTRL2_EDFLTDIS_SHIFT                 (11U)
18707 /*! EDFLTDIS - Edge Filter Disable
18708  *  0b0..Edge filter is enabled
18709  *  0b1..Edge filter is disabled
18710  */
18711 #define CAN_CTRL2_EDFLTDIS(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
18712 
18713 #define CAN_CTRL2_ISOCANFDEN_MASK                (0x1000U)
18714 #define CAN_CTRL2_ISOCANFDEN_SHIFT               (12U)
18715 /*! ISOCANFDEN - ISO CAN FD Enable
18716  *  0b0..FlexCAN operates using the non-ISO CAN FD protocol.
18717  *  0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).
18718  */
18719 #define CAN_CTRL2_ISOCANFDEN(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
18720 
18721 #define CAN_CTRL2_PREXCEN_MASK                   (0x4000U)
18722 #define CAN_CTRL2_PREXCEN_SHIFT                  (14U)
18723 /*! PREXCEN - Protocol Exception Enable
18724  *  0b0..Protocol exception is disabled.
18725  *  0b1..Protocol exception is enabled.
18726  */
18727 #define CAN_CTRL2_PREXCEN(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
18728 
18729 #define CAN_CTRL2_TIMER_SRC_MASK                 (0x8000U)
18730 #define CAN_CTRL2_TIMER_SRC_SHIFT                (15U)
18731 /*! TIMER_SRC - Timer Source
18732  *  0b0..The free running timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus.
18733  *  0b1..The free running timer is clocked by an external time tick. The period can be either adjusted to be equal
18734  *       to the baud rate on the CAN bus, or a different value as required. See the device-specific section for
18735  *       details about the external time tick.
18736  */
18737 #define CAN_CTRL2_TIMER_SRC(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)
18738 
18739 #define CAN_CTRL2_EACEN_MASK                     (0x10000U)
18740 #define CAN_CTRL2_EACEN_SHIFT                    (16U)
18741 /*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
18742  *  0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
18743  *  0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within
18744  *       the incoming frame. Mask bits do apply.
18745  */
18746 #define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
18747 
18748 #define CAN_CTRL2_RRS_MASK                       (0x20000U)
18749 #define CAN_CTRL2_RRS_SHIFT                      (17U)
18750 /*! RRS - Remote Request Storing
18751  *  0b0..Remote response frame is generated.
18752  *  0b1..Remote request frame is stored.
18753  */
18754 #define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
18755 
18756 #define CAN_CTRL2_MRP_MASK                       (0x40000U)
18757 #define CAN_CTRL2_MRP_SHIFT                      (18U)
18758 /*! MRP - Mailboxes Reception Priority
18759  *  0b0..Matching starts from Rx FIFO and continues on mailboxes.
18760  *  0b1..Matching starts from mailboxes and continues on Rx FIFO.
18761  */
18762 #define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
18763 
18764 #define CAN_CTRL2_TASD_MASK                      (0xF80000U)
18765 #define CAN_CTRL2_TASD_SHIFT                     (19U)
18766 /*! TASD - Tx Arbitration Start Delay */
18767 #define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
18768 
18769 #define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
18770 #define CAN_CTRL2_RFFN_SHIFT                     (24U)
18771 /*! RFFN - Number Of Rx FIFO Filters */
18772 #define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
18773 
18774 #define CAN_CTRL2_WRMFRZ_MASK                    (0x10000000U)
18775 #define CAN_CTRL2_WRMFRZ_SHIFT                   (28U)
18776 /*! WRMFRZ - Write-Access To Memory In Freeze Mode
18777  *  0b0..Maintain the write access restrictions.
18778  *  0b1..Enable unrestricted write access to FlexCAN memory.
18779  */
18780 #define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
18781 
18782 #define CAN_CTRL2_ECRWRE_MASK                    (0x20000000U)
18783 #define CAN_CTRL2_ECRWRE_SHIFT                   (29U)
18784 /*! ECRWRE - Error-correction Configuration Register Write Enable
18785  *  0b0..Disable update.
18786  *  0b1..Enable update.
18787  */
18788 #define CAN_CTRL2_ECRWRE(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK)
18789 
18790 #define CAN_CTRL2_BOFFDONEMSK_MASK               (0x40000000U)
18791 #define CAN_CTRL2_BOFFDONEMSK_SHIFT              (30U)
18792 /*! BOFFDONEMSK - Bus Off Done Interrupt Mask
18793  *  0b0..Bus off done interrupt disabled.
18794  *  0b1..Bus off done interrupt enabled.
18795  */
18796 #define CAN_CTRL2_BOFFDONEMSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
18797 
18798 #define CAN_CTRL2_ERRMSK_FAST_MASK               (0x80000000U)
18799 #define CAN_CTRL2_ERRMSK_FAST_SHIFT              (31U)
18800 /*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames
18801  *  0b0..ERRINT_FAST error interrupt disabled.
18802  *  0b1..ERRINT_FAST error interrupt enabled.
18803  */
18804 #define CAN_CTRL2_ERRMSK_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
18805 /*! @} */
18806 
18807 /*! @name ESR2 - Error and Status 2 Register */
18808 /*! @{ */
18809 
18810 #define CAN_ESR2_IMB_MASK                        (0x2000U)
18811 #define CAN_ESR2_IMB_SHIFT                       (13U)
18812 /*! IMB - Inactive Mailbox
18813  *  0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox.
18814  *  0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.
18815  */
18816 #define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
18817 
18818 #define CAN_ESR2_VPS_MASK                        (0x4000U)
18819 #define CAN_ESR2_VPS_SHIFT                       (14U)
18820 /*! VPS - Valid Priority Status
18821  *  0b0..Contents of IMB and LPTM are invalid.
18822  *  0b1..Contents of IMB and LPTM are valid.
18823  */
18824 #define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
18825 
18826 #define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
18827 #define CAN_ESR2_LPTM_SHIFT                      (16U)
18828 /*! LPTM - Lowest Priority Tx Mailbox */
18829 #define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
18830 /*! @} */
18831 
18832 /*! @name CRCR - CRC Register */
18833 /*! @{ */
18834 
18835 #define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
18836 #define CAN_CRCR_TXCRC_SHIFT                     (0U)
18837 /*! TXCRC - Transmitted CRC value */
18838 #define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
18839 
18840 #define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
18841 #define CAN_CRCR_MBCRC_SHIFT                     (16U)
18842 /*! MBCRC - CRC Mailbox */
18843 #define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
18844 /*! @} */
18845 
18846 /*! @name RXFGMASK - Rx FIFO Global Mask Register */
18847 /*! @{ */
18848 
18849 #define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
18850 #define CAN_RXFGMASK_FGM_SHIFT                   (0U)
18851 /*! FGM - Rx FIFO Global Mask Bits */
18852 #define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
18853 /*! @} */
18854 
18855 /*! @name RXFIR - Rx FIFO Information Register */
18856 /*! @{ */
18857 
18858 #define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
18859 #define CAN_RXFIR_IDHIT_SHIFT                    (0U)
18860 /*! IDHIT - Identifier Acceptance Filter Hit Indicator */
18861 #define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
18862 /*! @} */
18863 
18864 /*! @name CBT - CAN Bit Timing Register */
18865 /*! @{ */
18866 
18867 #define CAN_CBT_EPSEG2_MASK                      (0x1FU)
18868 #define CAN_CBT_EPSEG2_SHIFT                     (0U)
18869 /*! EPSEG2 - Extended Phase Segment 2 */
18870 #define CAN_CBT_EPSEG2(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
18871 
18872 #define CAN_CBT_EPSEG1_MASK                      (0x3E0U)
18873 #define CAN_CBT_EPSEG1_SHIFT                     (5U)
18874 /*! EPSEG1 - Extended Phase Segment 1 */
18875 #define CAN_CBT_EPSEG1(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
18876 
18877 #define CAN_CBT_EPROPSEG_MASK                    (0xFC00U)
18878 #define CAN_CBT_EPROPSEG_SHIFT                   (10U)
18879 /*! EPROPSEG - Extended Propagation Segment */
18880 #define CAN_CBT_EPROPSEG(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
18881 
18882 #define CAN_CBT_ERJW_MASK                        (0x1F0000U)
18883 #define CAN_CBT_ERJW_SHIFT                       (16U)
18884 /*! ERJW - Extended Resync Jump Width */
18885 #define CAN_CBT_ERJW(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
18886 
18887 #define CAN_CBT_EPRESDIV_MASK                    (0x7FE00000U)
18888 #define CAN_CBT_EPRESDIV_SHIFT                   (21U)
18889 /*! EPRESDIV - Extended Prescaler Division Factor */
18890 #define CAN_CBT_EPRESDIV(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
18891 
18892 #define CAN_CBT_BTF_MASK                         (0x80000000U)
18893 #define CAN_CBT_BTF_SHIFT                        (31U)
18894 /*! BTF - Bit Timing Format Enable
18895  *  0b0..Extended bit time definitions disabled.
18896  *  0b1..Extended bit time definitions enabled.
18897  */
18898 #define CAN_CBT_BTF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
18899 /*! @} */
18900 
18901 /* The count of CAN_CS */
18902 #define CAN_CS_COUNT_MB8B                        (64U)
18903 
18904 /* The count of CAN_ID */
18905 #define CAN_ID_COUNT_MB8B                        (64U)
18906 
18907 /* The count of CAN_WORD */
18908 #define CAN_WORD_COUNT_MB8B                      (64U)
18909 
18910 /* The count of CAN_WORD */
18911 #define CAN_WORD_COUNT_MB8B2                     (2U)
18912 
18913 /* The count of CAN_CS */
18914 #define CAN_CS_COUNT_MB16B_L                     (21U)
18915 
18916 /* The count of CAN_ID */
18917 #define CAN_ID_COUNT_MB16B_L                     (21U)
18918 
18919 /* The count of CAN_WORD */
18920 #define CAN_WORD_COUNT_MB16B_L                   (21U)
18921 
18922 /* The count of CAN_WORD */
18923 #define CAN_WORD_COUNT_MB16B_L2                  (4U)
18924 
18925 /* The count of CAN_CS */
18926 #define CAN_CS_COUNT_MB16B_H                     (21U)
18927 
18928 /* The count of CAN_ID */
18929 #define CAN_ID_COUNT_MB16B_H                     (21U)
18930 
18931 /* The count of CAN_WORD */
18932 #define CAN_WORD_COUNT_MB16B_H                   (21U)
18933 
18934 /* The count of CAN_WORD */
18935 #define CAN_WORD_COUNT_MB16B_H2                  (4U)
18936 
18937 /* The count of CAN_CS */
18938 #define CAN_CS_COUNT_MB32B_L                     (12U)
18939 
18940 /* The count of CAN_ID */
18941 #define CAN_ID_COUNT_MB32B_L                     (12U)
18942 
18943 /* The count of CAN_WORD */
18944 #define CAN_WORD_COUNT_MB32B_L                   (12U)
18945 
18946 /* The count of CAN_WORD */
18947 #define CAN_WORD_COUNT_MB32B_L2                  (8U)
18948 
18949 /* The count of CAN_CS */
18950 #define CAN_CS_COUNT_MB32B_H                     (12U)
18951 
18952 /* The count of CAN_ID */
18953 #define CAN_ID_COUNT_MB32B_H                     (12U)
18954 
18955 /* The count of CAN_WORD */
18956 #define CAN_WORD_COUNT_MB32B_H                   (12U)
18957 
18958 /* The count of CAN_WORD */
18959 #define CAN_WORD_COUNT_MB32B_H2                  (8U)
18960 
18961 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */
18962 /*! @{ */
18963 
18964 #define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
18965 #define CAN_CS_TIME_STAMP_SHIFT                  (0U)
18966 /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
18967  *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
18968  *    appears on the CAN bus.
18969  */
18970 #define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
18971 
18972 #define CAN_CS_DLC_MASK                          (0xF0000U)
18973 #define CAN_CS_DLC_SHIFT                         (16U)
18974 /*! DLC - Length of the data to be stored/transmitted. */
18975 #define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
18976 
18977 #define CAN_CS_RTR_MASK                          (0x100000U)
18978 #define CAN_CS_RTR_SHIFT                         (20U)
18979 /*! RTR - Remote Transmission Request. One/zero for remote/data frame. */
18980 #define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
18981 
18982 #define CAN_CS_IDE_MASK                          (0x200000U)
18983 #define CAN_CS_IDE_SHIFT                         (21U)
18984 /*! IDE - ID Extended. One/zero for extended/standard format frame. */
18985 #define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
18986 
18987 #define CAN_CS_SRR_MASK                          (0x400000U)
18988 #define CAN_CS_SRR_SHIFT                         (22U)
18989 /*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */
18990 #define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
18991 
18992 #define CAN_CS_CODE_MASK                         (0xF000000U)
18993 #define CAN_CS_CODE_SHIFT                        (24U)
18994 /*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
18995  *    the FlexCAN module itself, as part of the message buffer matching and arbitration process.
18996  */
18997 #define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
18998 
18999 #define CAN_CS_ESI_MASK                          (0x20000000U)
19000 #define CAN_CS_ESI_SHIFT                         (29U)
19001 /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */
19002 #define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
19003 
19004 #define CAN_CS_BRS_MASK                          (0x40000000U)
19005 #define CAN_CS_BRS_SHIFT                         (30U)
19006 /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */
19007 #define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
19008 
19009 #define CAN_CS_EDL_MASK                          (0x80000000U)
19010 #define CAN_CS_EDL_SHIFT                         (31U)
19011 /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
19012  *    The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
19013  */
19014 #define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
19015 /*! @} */
19016 
19017 /* The count of CAN_CS */
19018 #define CAN_CS_COUNT_MB64B_L                     (7U)
19019 
19020 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */
19021 /*! @{ */
19022 
19023 #define CAN_ID_EXT_MASK                          (0x3FFFFU)
19024 #define CAN_ID_EXT_SHIFT                         (0U)
19025 /*! EXT - Contains extended (LOW word) identifier of message buffer. */
19026 #define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
19027 
19028 #define CAN_ID_STD_MASK                          (0x1FFC0000U)
19029 #define CAN_ID_STD_SHIFT                         (18U)
19030 /*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */
19031 #define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
19032 
19033 #define CAN_ID_PRIO_MASK                         (0xE0000000U)
19034 #define CAN_ID_PRIO_SHIFT                        (29U)
19035 /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
19036  *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
19037  *    ID to define the transmission priority.
19038  */
19039 #define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
19040 /*! @} */
19041 
19042 /* The count of CAN_ID */
19043 #define CAN_ID_COUNT_MB64B_L                     (7U)
19044 
19045 /*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */
19046 /*! @{ */
19047 
19048 #define CAN_WORD_DATA_BYTE_3_MASK                (0xFFU)
19049 #define CAN_WORD_DATA_BYTE_3_SHIFT               (0U)
19050 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */
19051 #define CAN_WORD_DATA_BYTE_3(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
19052 
19053 #define CAN_WORD_DATA_BYTE_7_MASK                (0xFFU)
19054 #define CAN_WORD_DATA_BYTE_7_SHIFT               (0U)
19055 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */
19056 #define CAN_WORD_DATA_BYTE_7(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
19057 
19058 #define CAN_WORD_DATA_BYTE_11_MASK               (0xFFU)
19059 #define CAN_WORD_DATA_BYTE_11_SHIFT              (0U)
19060 /*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */
19061 #define CAN_WORD_DATA_BYTE_11(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
19062 
19063 #define CAN_WORD_DATA_BYTE_15_MASK               (0xFFU)
19064 #define CAN_WORD_DATA_BYTE_15_SHIFT              (0U)
19065 /*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */
19066 #define CAN_WORD_DATA_BYTE_15(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
19067 
19068 #define CAN_WORD_DATA_BYTE_19_MASK               (0xFFU)
19069 #define CAN_WORD_DATA_BYTE_19_SHIFT              (0U)
19070 /*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */
19071 #define CAN_WORD_DATA_BYTE_19(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
19072 
19073 #define CAN_WORD_DATA_BYTE_23_MASK               (0xFFU)
19074 #define CAN_WORD_DATA_BYTE_23_SHIFT              (0U)
19075 /*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */
19076 #define CAN_WORD_DATA_BYTE_23(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
19077 
19078 #define CAN_WORD_DATA_BYTE_27_MASK               (0xFFU)
19079 #define CAN_WORD_DATA_BYTE_27_SHIFT              (0U)
19080 /*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */
19081 #define CAN_WORD_DATA_BYTE_27(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
19082 
19083 #define CAN_WORD_DATA_BYTE_31_MASK               (0xFFU)
19084 #define CAN_WORD_DATA_BYTE_31_SHIFT              (0U)
19085 /*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */
19086 #define CAN_WORD_DATA_BYTE_31(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
19087 
19088 #define CAN_WORD_DATA_BYTE_35_MASK               (0xFFU)
19089 #define CAN_WORD_DATA_BYTE_35_SHIFT              (0U)
19090 /*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */
19091 #define CAN_WORD_DATA_BYTE_35(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
19092 
19093 #define CAN_WORD_DATA_BYTE_39_MASK               (0xFFU)
19094 #define CAN_WORD_DATA_BYTE_39_SHIFT              (0U)
19095 /*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */
19096 #define CAN_WORD_DATA_BYTE_39(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
19097 
19098 #define CAN_WORD_DATA_BYTE_43_MASK               (0xFFU)
19099 #define CAN_WORD_DATA_BYTE_43_SHIFT              (0U)
19100 /*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */
19101 #define CAN_WORD_DATA_BYTE_43(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
19102 
19103 #define CAN_WORD_DATA_BYTE_47_MASK               (0xFFU)
19104 #define CAN_WORD_DATA_BYTE_47_SHIFT              (0U)
19105 /*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */
19106 #define CAN_WORD_DATA_BYTE_47(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
19107 
19108 #define CAN_WORD_DATA_BYTE_51_MASK               (0xFFU)
19109 #define CAN_WORD_DATA_BYTE_51_SHIFT              (0U)
19110 /*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */
19111 #define CAN_WORD_DATA_BYTE_51(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
19112 
19113 #define CAN_WORD_DATA_BYTE_55_MASK               (0xFFU)
19114 #define CAN_WORD_DATA_BYTE_55_SHIFT              (0U)
19115 /*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */
19116 #define CAN_WORD_DATA_BYTE_55(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
19117 
19118 #define CAN_WORD_DATA_BYTE_59_MASK               (0xFFU)
19119 #define CAN_WORD_DATA_BYTE_59_SHIFT              (0U)
19120 /*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */
19121 #define CAN_WORD_DATA_BYTE_59(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
19122 
19123 #define CAN_WORD_DATA_BYTE_63_MASK               (0xFFU)
19124 #define CAN_WORD_DATA_BYTE_63_SHIFT              (0U)
19125 /*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */
19126 #define CAN_WORD_DATA_BYTE_63(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
19127 
19128 #define CAN_WORD_DATA_BYTE_2_MASK                (0xFF00U)
19129 #define CAN_WORD_DATA_BYTE_2_SHIFT               (8U)
19130 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */
19131 #define CAN_WORD_DATA_BYTE_2(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
19132 
19133 #define CAN_WORD_DATA_BYTE_6_MASK                (0xFF00U)
19134 #define CAN_WORD_DATA_BYTE_6_SHIFT               (8U)
19135 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */
19136 #define CAN_WORD_DATA_BYTE_6(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
19137 
19138 #define CAN_WORD_DATA_BYTE_10_MASK               (0xFF00U)
19139 #define CAN_WORD_DATA_BYTE_10_SHIFT              (8U)
19140 /*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */
19141 #define CAN_WORD_DATA_BYTE_10(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
19142 
19143 #define CAN_WORD_DATA_BYTE_14_MASK               (0xFF00U)
19144 #define CAN_WORD_DATA_BYTE_14_SHIFT              (8U)
19145 /*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */
19146 #define CAN_WORD_DATA_BYTE_14(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
19147 
19148 #define CAN_WORD_DATA_BYTE_18_MASK               (0xFF00U)
19149 #define CAN_WORD_DATA_BYTE_18_SHIFT              (8U)
19150 /*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */
19151 #define CAN_WORD_DATA_BYTE_18(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
19152 
19153 #define CAN_WORD_DATA_BYTE_22_MASK               (0xFF00U)
19154 #define CAN_WORD_DATA_BYTE_22_SHIFT              (8U)
19155 /*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */
19156 #define CAN_WORD_DATA_BYTE_22(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
19157 
19158 #define CAN_WORD_DATA_BYTE_26_MASK               (0xFF00U)
19159 #define CAN_WORD_DATA_BYTE_26_SHIFT              (8U)
19160 /*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */
19161 #define CAN_WORD_DATA_BYTE_26(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
19162 
19163 #define CAN_WORD_DATA_BYTE_30_MASK               (0xFF00U)
19164 #define CAN_WORD_DATA_BYTE_30_SHIFT              (8U)
19165 /*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */
19166 #define CAN_WORD_DATA_BYTE_30(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
19167 
19168 #define CAN_WORD_DATA_BYTE_34_MASK               (0xFF00U)
19169 #define CAN_WORD_DATA_BYTE_34_SHIFT              (8U)
19170 /*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */
19171 #define CAN_WORD_DATA_BYTE_34(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
19172 
19173 #define CAN_WORD_DATA_BYTE_38_MASK               (0xFF00U)
19174 #define CAN_WORD_DATA_BYTE_38_SHIFT              (8U)
19175 /*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */
19176 #define CAN_WORD_DATA_BYTE_38(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
19177 
19178 #define CAN_WORD_DATA_BYTE_42_MASK               (0xFF00U)
19179 #define CAN_WORD_DATA_BYTE_42_SHIFT              (8U)
19180 /*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */
19181 #define CAN_WORD_DATA_BYTE_42(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
19182 
19183 #define CAN_WORD_DATA_BYTE_46_MASK               (0xFF00U)
19184 #define CAN_WORD_DATA_BYTE_46_SHIFT              (8U)
19185 /*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */
19186 #define CAN_WORD_DATA_BYTE_46(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
19187 
19188 #define CAN_WORD_DATA_BYTE_50_MASK               (0xFF00U)
19189 #define CAN_WORD_DATA_BYTE_50_SHIFT              (8U)
19190 /*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */
19191 #define CAN_WORD_DATA_BYTE_50(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
19192 
19193 #define CAN_WORD_DATA_BYTE_54_MASK               (0xFF00U)
19194 #define CAN_WORD_DATA_BYTE_54_SHIFT              (8U)
19195 /*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */
19196 #define CAN_WORD_DATA_BYTE_54(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
19197 
19198 #define CAN_WORD_DATA_BYTE_58_MASK               (0xFF00U)
19199 #define CAN_WORD_DATA_BYTE_58_SHIFT              (8U)
19200 /*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */
19201 #define CAN_WORD_DATA_BYTE_58(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
19202 
19203 #define CAN_WORD_DATA_BYTE_62_MASK               (0xFF00U)
19204 #define CAN_WORD_DATA_BYTE_62_SHIFT              (8U)
19205 /*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */
19206 #define CAN_WORD_DATA_BYTE_62(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
19207 
19208 #define CAN_WORD_DATA_BYTE_1_MASK                (0xFF0000U)
19209 #define CAN_WORD_DATA_BYTE_1_SHIFT               (16U)
19210 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */
19211 #define CAN_WORD_DATA_BYTE_1(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
19212 
19213 #define CAN_WORD_DATA_BYTE_5_MASK                (0xFF0000U)
19214 #define CAN_WORD_DATA_BYTE_5_SHIFT               (16U)
19215 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */
19216 #define CAN_WORD_DATA_BYTE_5(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
19217 
19218 #define CAN_WORD_DATA_BYTE_9_MASK                (0xFF0000U)
19219 #define CAN_WORD_DATA_BYTE_9_SHIFT               (16U)
19220 /*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */
19221 #define CAN_WORD_DATA_BYTE_9(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
19222 
19223 #define CAN_WORD_DATA_BYTE_13_MASK               (0xFF0000U)
19224 #define CAN_WORD_DATA_BYTE_13_SHIFT              (16U)
19225 /*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */
19226 #define CAN_WORD_DATA_BYTE_13(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
19227 
19228 #define CAN_WORD_DATA_BYTE_17_MASK               (0xFF0000U)
19229 #define CAN_WORD_DATA_BYTE_17_SHIFT              (16U)
19230 /*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */
19231 #define CAN_WORD_DATA_BYTE_17(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
19232 
19233 #define CAN_WORD_DATA_BYTE_21_MASK               (0xFF0000U)
19234 #define CAN_WORD_DATA_BYTE_21_SHIFT              (16U)
19235 /*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */
19236 #define CAN_WORD_DATA_BYTE_21(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
19237 
19238 #define CAN_WORD_DATA_BYTE_25_MASK               (0xFF0000U)
19239 #define CAN_WORD_DATA_BYTE_25_SHIFT              (16U)
19240 /*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */
19241 #define CAN_WORD_DATA_BYTE_25(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
19242 
19243 #define CAN_WORD_DATA_BYTE_29_MASK               (0xFF0000U)
19244 #define CAN_WORD_DATA_BYTE_29_SHIFT              (16U)
19245 /*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */
19246 #define CAN_WORD_DATA_BYTE_29(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
19247 
19248 #define CAN_WORD_DATA_BYTE_33_MASK               (0xFF0000U)
19249 #define CAN_WORD_DATA_BYTE_33_SHIFT              (16U)
19250 /*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */
19251 #define CAN_WORD_DATA_BYTE_33(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
19252 
19253 #define CAN_WORD_DATA_BYTE_37_MASK               (0xFF0000U)
19254 #define CAN_WORD_DATA_BYTE_37_SHIFT              (16U)
19255 /*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */
19256 #define CAN_WORD_DATA_BYTE_37(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
19257 
19258 #define CAN_WORD_DATA_BYTE_41_MASK               (0xFF0000U)
19259 #define CAN_WORD_DATA_BYTE_41_SHIFT              (16U)
19260 /*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */
19261 #define CAN_WORD_DATA_BYTE_41(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
19262 
19263 #define CAN_WORD_DATA_BYTE_45_MASK               (0xFF0000U)
19264 #define CAN_WORD_DATA_BYTE_45_SHIFT              (16U)
19265 /*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */
19266 #define CAN_WORD_DATA_BYTE_45(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
19267 
19268 #define CAN_WORD_DATA_BYTE_49_MASK               (0xFF0000U)
19269 #define CAN_WORD_DATA_BYTE_49_SHIFT              (16U)
19270 /*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */
19271 #define CAN_WORD_DATA_BYTE_49(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
19272 
19273 #define CAN_WORD_DATA_BYTE_53_MASK               (0xFF0000U)
19274 #define CAN_WORD_DATA_BYTE_53_SHIFT              (16U)
19275 /*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */
19276 #define CAN_WORD_DATA_BYTE_53(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
19277 
19278 #define CAN_WORD_DATA_BYTE_57_MASK               (0xFF0000U)
19279 #define CAN_WORD_DATA_BYTE_57_SHIFT              (16U)
19280 /*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */
19281 #define CAN_WORD_DATA_BYTE_57(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
19282 
19283 #define CAN_WORD_DATA_BYTE_61_MASK               (0xFF0000U)
19284 #define CAN_WORD_DATA_BYTE_61_SHIFT              (16U)
19285 /*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */
19286 #define CAN_WORD_DATA_BYTE_61(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
19287 
19288 #define CAN_WORD_DATA_BYTE_0_MASK                (0xFF000000U)
19289 #define CAN_WORD_DATA_BYTE_0_SHIFT               (24U)
19290 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */
19291 #define CAN_WORD_DATA_BYTE_0(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
19292 
19293 #define CAN_WORD_DATA_BYTE_4_MASK                (0xFF000000U)
19294 #define CAN_WORD_DATA_BYTE_4_SHIFT               (24U)
19295 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */
19296 #define CAN_WORD_DATA_BYTE_4(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
19297 
19298 #define CAN_WORD_DATA_BYTE_8_MASK                (0xFF000000U)
19299 #define CAN_WORD_DATA_BYTE_8_SHIFT               (24U)
19300 /*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */
19301 #define CAN_WORD_DATA_BYTE_8(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
19302 
19303 #define CAN_WORD_DATA_BYTE_12_MASK               (0xFF000000U)
19304 #define CAN_WORD_DATA_BYTE_12_SHIFT              (24U)
19305 /*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */
19306 #define CAN_WORD_DATA_BYTE_12(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
19307 
19308 #define CAN_WORD_DATA_BYTE_16_MASK               (0xFF000000U)
19309 #define CAN_WORD_DATA_BYTE_16_SHIFT              (24U)
19310 /*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */
19311 #define CAN_WORD_DATA_BYTE_16(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
19312 
19313 #define CAN_WORD_DATA_BYTE_20_MASK               (0xFF000000U)
19314 #define CAN_WORD_DATA_BYTE_20_SHIFT              (24U)
19315 /*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */
19316 #define CAN_WORD_DATA_BYTE_20(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
19317 
19318 #define CAN_WORD_DATA_BYTE_24_MASK               (0xFF000000U)
19319 #define CAN_WORD_DATA_BYTE_24_SHIFT              (24U)
19320 /*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */
19321 #define CAN_WORD_DATA_BYTE_24(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
19322 
19323 #define CAN_WORD_DATA_BYTE_28_MASK               (0xFF000000U)
19324 #define CAN_WORD_DATA_BYTE_28_SHIFT              (24U)
19325 /*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */
19326 #define CAN_WORD_DATA_BYTE_28(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
19327 
19328 #define CAN_WORD_DATA_BYTE_32_MASK               (0xFF000000U)
19329 #define CAN_WORD_DATA_BYTE_32_SHIFT              (24U)
19330 /*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */
19331 #define CAN_WORD_DATA_BYTE_32(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
19332 
19333 #define CAN_WORD_DATA_BYTE_36_MASK               (0xFF000000U)
19334 #define CAN_WORD_DATA_BYTE_36_SHIFT              (24U)
19335 /*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */
19336 #define CAN_WORD_DATA_BYTE_36(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
19337 
19338 #define CAN_WORD_DATA_BYTE_40_MASK               (0xFF000000U)
19339 #define CAN_WORD_DATA_BYTE_40_SHIFT              (24U)
19340 /*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */
19341 #define CAN_WORD_DATA_BYTE_40(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
19342 
19343 #define CAN_WORD_DATA_BYTE_44_MASK               (0xFF000000U)
19344 #define CAN_WORD_DATA_BYTE_44_SHIFT              (24U)
19345 /*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */
19346 #define CAN_WORD_DATA_BYTE_44(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
19347 
19348 #define CAN_WORD_DATA_BYTE_48_MASK               (0xFF000000U)
19349 #define CAN_WORD_DATA_BYTE_48_SHIFT              (24U)
19350 /*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */
19351 #define CAN_WORD_DATA_BYTE_48(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
19352 
19353 #define CAN_WORD_DATA_BYTE_52_MASK               (0xFF000000U)
19354 #define CAN_WORD_DATA_BYTE_52_SHIFT              (24U)
19355 /*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */
19356 #define CAN_WORD_DATA_BYTE_52(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
19357 
19358 #define CAN_WORD_DATA_BYTE_56_MASK               (0xFF000000U)
19359 #define CAN_WORD_DATA_BYTE_56_SHIFT              (24U)
19360 /*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */
19361 #define CAN_WORD_DATA_BYTE_56(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
19362 
19363 #define CAN_WORD_DATA_BYTE_60_MASK               (0xFF000000U)
19364 #define CAN_WORD_DATA_BYTE_60_SHIFT              (24U)
19365 /*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */
19366 #define CAN_WORD_DATA_BYTE_60(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
19367 /*! @} */
19368 
19369 /* The count of CAN_WORD */
19370 #define CAN_WORD_COUNT_MB64B_L                   (7U)
19371 
19372 /* The count of CAN_WORD */
19373 #define CAN_WORD_COUNT_MB64B_L2                  (16U)
19374 
19375 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */
19376 /*! @{ */
19377 
19378 #define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
19379 #define CAN_CS_TIME_STAMP_SHIFT                  (0U)
19380 /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
19381  *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
19382  *    appears on the CAN bus.
19383  */
19384 #define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
19385 
19386 #define CAN_CS_DLC_MASK                          (0xF0000U)
19387 #define CAN_CS_DLC_SHIFT                         (16U)
19388 /*! DLC - Length of the data to be stored/transmitted. */
19389 #define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
19390 
19391 #define CAN_CS_RTR_MASK                          (0x100000U)
19392 #define CAN_CS_RTR_SHIFT                         (20U)
19393 /*! RTR - Remote Transmission Request. One/zero for remote/data frame. */
19394 #define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
19395 
19396 #define CAN_CS_IDE_MASK                          (0x200000U)
19397 #define CAN_CS_IDE_SHIFT                         (21U)
19398 /*! IDE - ID Extended. One/zero for extended/standard format frame. */
19399 #define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
19400 
19401 #define CAN_CS_SRR_MASK                          (0x400000U)
19402 #define CAN_CS_SRR_SHIFT                         (22U)
19403 /*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */
19404 #define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
19405 
19406 #define CAN_CS_CODE_MASK                         (0xF000000U)
19407 #define CAN_CS_CODE_SHIFT                        (24U)
19408 /*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
19409  *    the FlexCAN module itself, as part of the message buffer matching and arbitration process.
19410  */
19411 #define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
19412 
19413 #define CAN_CS_ESI_MASK                          (0x20000000U)
19414 #define CAN_CS_ESI_SHIFT                         (29U)
19415 /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */
19416 #define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
19417 
19418 #define CAN_CS_BRS_MASK                          (0x40000000U)
19419 #define CAN_CS_BRS_SHIFT                         (30U)
19420 /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */
19421 #define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
19422 
19423 #define CAN_CS_EDL_MASK                          (0x80000000U)
19424 #define CAN_CS_EDL_SHIFT                         (31U)
19425 /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
19426  *    The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
19427  */
19428 #define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
19429 /*! @} */
19430 
19431 /* The count of CAN_CS */
19432 #define CAN_CS_COUNT_MB64B_H                     (7U)
19433 
19434 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */
19435 /*! @{ */
19436 
19437 #define CAN_ID_EXT_MASK                          (0x3FFFFU)
19438 #define CAN_ID_EXT_SHIFT                         (0U)
19439 /*! EXT - Contains extended (LOW word) identifier of message buffer. */
19440 #define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
19441 
19442 #define CAN_ID_STD_MASK                          (0x1FFC0000U)
19443 #define CAN_ID_STD_SHIFT                         (18U)
19444 /*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */
19445 #define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
19446 
19447 #define CAN_ID_PRIO_MASK                         (0xE0000000U)
19448 #define CAN_ID_PRIO_SHIFT                        (29U)
19449 /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
19450  *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
19451  *    ID to define the transmission priority.
19452  */
19453 #define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
19454 /*! @} */
19455 
19456 /* The count of CAN_ID */
19457 #define CAN_ID_COUNT_MB64B_H                     (7U)
19458 
19459 /*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */
19460 /*! @{ */
19461 
19462 #define CAN_WORD_DATA_BYTE_3_MASK                (0xFFU)
19463 #define CAN_WORD_DATA_BYTE_3_SHIFT               (0U)
19464 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */
19465 #define CAN_WORD_DATA_BYTE_3(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
19466 
19467 #define CAN_WORD_DATA_BYTE_7_MASK                (0xFFU)
19468 #define CAN_WORD_DATA_BYTE_7_SHIFT               (0U)
19469 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */
19470 #define CAN_WORD_DATA_BYTE_7(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
19471 
19472 #define CAN_WORD_DATA_BYTE_11_MASK               (0xFFU)
19473 #define CAN_WORD_DATA_BYTE_11_SHIFT              (0U)
19474 /*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */
19475 #define CAN_WORD_DATA_BYTE_11(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
19476 
19477 #define CAN_WORD_DATA_BYTE_15_MASK               (0xFFU)
19478 #define CAN_WORD_DATA_BYTE_15_SHIFT              (0U)
19479 /*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */
19480 #define CAN_WORD_DATA_BYTE_15(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
19481 
19482 #define CAN_WORD_DATA_BYTE_19_MASK               (0xFFU)
19483 #define CAN_WORD_DATA_BYTE_19_SHIFT              (0U)
19484 /*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */
19485 #define CAN_WORD_DATA_BYTE_19(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
19486 
19487 #define CAN_WORD_DATA_BYTE_23_MASK               (0xFFU)
19488 #define CAN_WORD_DATA_BYTE_23_SHIFT              (0U)
19489 /*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */
19490 #define CAN_WORD_DATA_BYTE_23(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
19491 
19492 #define CAN_WORD_DATA_BYTE_27_MASK               (0xFFU)
19493 #define CAN_WORD_DATA_BYTE_27_SHIFT              (0U)
19494 /*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */
19495 #define CAN_WORD_DATA_BYTE_27(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
19496 
19497 #define CAN_WORD_DATA_BYTE_31_MASK               (0xFFU)
19498 #define CAN_WORD_DATA_BYTE_31_SHIFT              (0U)
19499 /*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */
19500 #define CAN_WORD_DATA_BYTE_31(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
19501 
19502 #define CAN_WORD_DATA_BYTE_35_MASK               (0xFFU)
19503 #define CAN_WORD_DATA_BYTE_35_SHIFT              (0U)
19504 /*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */
19505 #define CAN_WORD_DATA_BYTE_35(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
19506 
19507 #define CAN_WORD_DATA_BYTE_39_MASK               (0xFFU)
19508 #define CAN_WORD_DATA_BYTE_39_SHIFT              (0U)
19509 /*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */
19510 #define CAN_WORD_DATA_BYTE_39(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
19511 
19512 #define CAN_WORD_DATA_BYTE_43_MASK               (0xFFU)
19513 #define CAN_WORD_DATA_BYTE_43_SHIFT              (0U)
19514 /*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */
19515 #define CAN_WORD_DATA_BYTE_43(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
19516 
19517 #define CAN_WORD_DATA_BYTE_47_MASK               (0xFFU)
19518 #define CAN_WORD_DATA_BYTE_47_SHIFT              (0U)
19519 /*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */
19520 #define CAN_WORD_DATA_BYTE_47(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
19521 
19522 #define CAN_WORD_DATA_BYTE_51_MASK               (0xFFU)
19523 #define CAN_WORD_DATA_BYTE_51_SHIFT              (0U)
19524 /*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */
19525 #define CAN_WORD_DATA_BYTE_51(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
19526 
19527 #define CAN_WORD_DATA_BYTE_55_MASK               (0xFFU)
19528 #define CAN_WORD_DATA_BYTE_55_SHIFT              (0U)
19529 /*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */
19530 #define CAN_WORD_DATA_BYTE_55(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
19531 
19532 #define CAN_WORD_DATA_BYTE_59_MASK               (0xFFU)
19533 #define CAN_WORD_DATA_BYTE_59_SHIFT              (0U)
19534 /*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */
19535 #define CAN_WORD_DATA_BYTE_59(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
19536 
19537 #define CAN_WORD_DATA_BYTE_63_MASK               (0xFFU)
19538 #define CAN_WORD_DATA_BYTE_63_SHIFT              (0U)
19539 /*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */
19540 #define CAN_WORD_DATA_BYTE_63(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
19541 
19542 #define CAN_WORD_DATA_BYTE_2_MASK                (0xFF00U)
19543 #define CAN_WORD_DATA_BYTE_2_SHIFT               (8U)
19544 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */
19545 #define CAN_WORD_DATA_BYTE_2(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
19546 
19547 #define CAN_WORD_DATA_BYTE_6_MASK                (0xFF00U)
19548 #define CAN_WORD_DATA_BYTE_6_SHIFT               (8U)
19549 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */
19550 #define CAN_WORD_DATA_BYTE_6(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
19551 
19552 #define CAN_WORD_DATA_BYTE_10_MASK               (0xFF00U)
19553 #define CAN_WORD_DATA_BYTE_10_SHIFT              (8U)
19554 /*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */
19555 #define CAN_WORD_DATA_BYTE_10(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
19556 
19557 #define CAN_WORD_DATA_BYTE_14_MASK               (0xFF00U)
19558 #define CAN_WORD_DATA_BYTE_14_SHIFT              (8U)
19559 /*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */
19560 #define CAN_WORD_DATA_BYTE_14(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
19561 
19562 #define CAN_WORD_DATA_BYTE_18_MASK               (0xFF00U)
19563 #define CAN_WORD_DATA_BYTE_18_SHIFT              (8U)
19564 /*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */
19565 #define CAN_WORD_DATA_BYTE_18(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
19566 
19567 #define CAN_WORD_DATA_BYTE_22_MASK               (0xFF00U)
19568 #define CAN_WORD_DATA_BYTE_22_SHIFT              (8U)
19569 /*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */
19570 #define CAN_WORD_DATA_BYTE_22(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
19571 
19572 #define CAN_WORD_DATA_BYTE_26_MASK               (0xFF00U)
19573 #define CAN_WORD_DATA_BYTE_26_SHIFT              (8U)
19574 /*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */
19575 #define CAN_WORD_DATA_BYTE_26(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
19576 
19577 #define CAN_WORD_DATA_BYTE_30_MASK               (0xFF00U)
19578 #define CAN_WORD_DATA_BYTE_30_SHIFT              (8U)
19579 /*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */
19580 #define CAN_WORD_DATA_BYTE_30(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
19581 
19582 #define CAN_WORD_DATA_BYTE_34_MASK               (0xFF00U)
19583 #define CAN_WORD_DATA_BYTE_34_SHIFT              (8U)
19584 /*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */
19585 #define CAN_WORD_DATA_BYTE_34(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
19586 
19587 #define CAN_WORD_DATA_BYTE_38_MASK               (0xFF00U)
19588 #define CAN_WORD_DATA_BYTE_38_SHIFT              (8U)
19589 /*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */
19590 #define CAN_WORD_DATA_BYTE_38(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
19591 
19592 #define CAN_WORD_DATA_BYTE_42_MASK               (0xFF00U)
19593 #define CAN_WORD_DATA_BYTE_42_SHIFT              (8U)
19594 /*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */
19595 #define CAN_WORD_DATA_BYTE_42(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
19596 
19597 #define CAN_WORD_DATA_BYTE_46_MASK               (0xFF00U)
19598 #define CAN_WORD_DATA_BYTE_46_SHIFT              (8U)
19599 /*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */
19600 #define CAN_WORD_DATA_BYTE_46(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
19601 
19602 #define CAN_WORD_DATA_BYTE_50_MASK               (0xFF00U)
19603 #define CAN_WORD_DATA_BYTE_50_SHIFT              (8U)
19604 /*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */
19605 #define CAN_WORD_DATA_BYTE_50(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
19606 
19607 #define CAN_WORD_DATA_BYTE_54_MASK               (0xFF00U)
19608 #define CAN_WORD_DATA_BYTE_54_SHIFT              (8U)
19609 /*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */
19610 #define CAN_WORD_DATA_BYTE_54(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
19611 
19612 #define CAN_WORD_DATA_BYTE_58_MASK               (0xFF00U)
19613 #define CAN_WORD_DATA_BYTE_58_SHIFT              (8U)
19614 /*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */
19615 #define CAN_WORD_DATA_BYTE_58(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
19616 
19617 #define CAN_WORD_DATA_BYTE_62_MASK               (0xFF00U)
19618 #define CAN_WORD_DATA_BYTE_62_SHIFT              (8U)
19619 /*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */
19620 #define CAN_WORD_DATA_BYTE_62(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
19621 
19622 #define CAN_WORD_DATA_BYTE_1_MASK                (0xFF0000U)
19623 #define CAN_WORD_DATA_BYTE_1_SHIFT               (16U)
19624 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */
19625 #define CAN_WORD_DATA_BYTE_1(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
19626 
19627 #define CAN_WORD_DATA_BYTE_5_MASK                (0xFF0000U)
19628 #define CAN_WORD_DATA_BYTE_5_SHIFT               (16U)
19629 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */
19630 #define CAN_WORD_DATA_BYTE_5(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
19631 
19632 #define CAN_WORD_DATA_BYTE_9_MASK                (0xFF0000U)
19633 #define CAN_WORD_DATA_BYTE_9_SHIFT               (16U)
19634 /*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */
19635 #define CAN_WORD_DATA_BYTE_9(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
19636 
19637 #define CAN_WORD_DATA_BYTE_13_MASK               (0xFF0000U)
19638 #define CAN_WORD_DATA_BYTE_13_SHIFT              (16U)
19639 /*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */
19640 #define CAN_WORD_DATA_BYTE_13(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
19641 
19642 #define CAN_WORD_DATA_BYTE_17_MASK               (0xFF0000U)
19643 #define CAN_WORD_DATA_BYTE_17_SHIFT              (16U)
19644 /*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */
19645 #define CAN_WORD_DATA_BYTE_17(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
19646 
19647 #define CAN_WORD_DATA_BYTE_21_MASK               (0xFF0000U)
19648 #define CAN_WORD_DATA_BYTE_21_SHIFT              (16U)
19649 /*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */
19650 #define CAN_WORD_DATA_BYTE_21(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
19651 
19652 #define CAN_WORD_DATA_BYTE_25_MASK               (0xFF0000U)
19653 #define CAN_WORD_DATA_BYTE_25_SHIFT              (16U)
19654 /*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */
19655 #define CAN_WORD_DATA_BYTE_25(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
19656 
19657 #define CAN_WORD_DATA_BYTE_29_MASK               (0xFF0000U)
19658 #define CAN_WORD_DATA_BYTE_29_SHIFT              (16U)
19659 /*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */
19660 #define CAN_WORD_DATA_BYTE_29(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
19661 
19662 #define CAN_WORD_DATA_BYTE_33_MASK               (0xFF0000U)
19663 #define CAN_WORD_DATA_BYTE_33_SHIFT              (16U)
19664 /*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */
19665 #define CAN_WORD_DATA_BYTE_33(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
19666 
19667 #define CAN_WORD_DATA_BYTE_37_MASK               (0xFF0000U)
19668 #define CAN_WORD_DATA_BYTE_37_SHIFT              (16U)
19669 /*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */
19670 #define CAN_WORD_DATA_BYTE_37(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
19671 
19672 #define CAN_WORD_DATA_BYTE_41_MASK               (0xFF0000U)
19673 #define CAN_WORD_DATA_BYTE_41_SHIFT              (16U)
19674 /*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */
19675 #define CAN_WORD_DATA_BYTE_41(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
19676 
19677 #define CAN_WORD_DATA_BYTE_45_MASK               (0xFF0000U)
19678 #define CAN_WORD_DATA_BYTE_45_SHIFT              (16U)
19679 /*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */
19680 #define CAN_WORD_DATA_BYTE_45(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
19681 
19682 #define CAN_WORD_DATA_BYTE_49_MASK               (0xFF0000U)
19683 #define CAN_WORD_DATA_BYTE_49_SHIFT              (16U)
19684 /*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */
19685 #define CAN_WORD_DATA_BYTE_49(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
19686 
19687 #define CAN_WORD_DATA_BYTE_53_MASK               (0xFF0000U)
19688 #define CAN_WORD_DATA_BYTE_53_SHIFT              (16U)
19689 /*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */
19690 #define CAN_WORD_DATA_BYTE_53(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
19691 
19692 #define CAN_WORD_DATA_BYTE_57_MASK               (0xFF0000U)
19693 #define CAN_WORD_DATA_BYTE_57_SHIFT              (16U)
19694 /*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */
19695 #define CAN_WORD_DATA_BYTE_57(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
19696 
19697 #define CAN_WORD_DATA_BYTE_61_MASK               (0xFF0000U)
19698 #define CAN_WORD_DATA_BYTE_61_SHIFT              (16U)
19699 /*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */
19700 #define CAN_WORD_DATA_BYTE_61(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
19701 
19702 #define CAN_WORD_DATA_BYTE_0_MASK                (0xFF000000U)
19703 #define CAN_WORD_DATA_BYTE_0_SHIFT               (24U)
19704 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */
19705 #define CAN_WORD_DATA_BYTE_0(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
19706 
19707 #define CAN_WORD_DATA_BYTE_4_MASK                (0xFF000000U)
19708 #define CAN_WORD_DATA_BYTE_4_SHIFT               (24U)
19709 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */
19710 #define CAN_WORD_DATA_BYTE_4(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
19711 
19712 #define CAN_WORD_DATA_BYTE_8_MASK                (0xFF000000U)
19713 #define CAN_WORD_DATA_BYTE_8_SHIFT               (24U)
19714 /*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */
19715 #define CAN_WORD_DATA_BYTE_8(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
19716 
19717 #define CAN_WORD_DATA_BYTE_12_MASK               (0xFF000000U)
19718 #define CAN_WORD_DATA_BYTE_12_SHIFT              (24U)
19719 /*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */
19720 #define CAN_WORD_DATA_BYTE_12(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
19721 
19722 #define CAN_WORD_DATA_BYTE_16_MASK               (0xFF000000U)
19723 #define CAN_WORD_DATA_BYTE_16_SHIFT              (24U)
19724 /*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */
19725 #define CAN_WORD_DATA_BYTE_16(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
19726 
19727 #define CAN_WORD_DATA_BYTE_20_MASK               (0xFF000000U)
19728 #define CAN_WORD_DATA_BYTE_20_SHIFT              (24U)
19729 /*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */
19730 #define CAN_WORD_DATA_BYTE_20(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
19731 
19732 #define CAN_WORD_DATA_BYTE_24_MASK               (0xFF000000U)
19733 #define CAN_WORD_DATA_BYTE_24_SHIFT              (24U)
19734 /*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */
19735 #define CAN_WORD_DATA_BYTE_24(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
19736 
19737 #define CAN_WORD_DATA_BYTE_28_MASK               (0xFF000000U)
19738 #define CAN_WORD_DATA_BYTE_28_SHIFT              (24U)
19739 /*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */
19740 #define CAN_WORD_DATA_BYTE_28(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
19741 
19742 #define CAN_WORD_DATA_BYTE_32_MASK               (0xFF000000U)
19743 #define CAN_WORD_DATA_BYTE_32_SHIFT              (24U)
19744 /*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */
19745 #define CAN_WORD_DATA_BYTE_32(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
19746 
19747 #define CAN_WORD_DATA_BYTE_36_MASK               (0xFF000000U)
19748 #define CAN_WORD_DATA_BYTE_36_SHIFT              (24U)
19749 /*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */
19750 #define CAN_WORD_DATA_BYTE_36(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
19751 
19752 #define CAN_WORD_DATA_BYTE_40_MASK               (0xFF000000U)
19753 #define CAN_WORD_DATA_BYTE_40_SHIFT              (24U)
19754 /*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */
19755 #define CAN_WORD_DATA_BYTE_40(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
19756 
19757 #define CAN_WORD_DATA_BYTE_44_MASK               (0xFF000000U)
19758 #define CAN_WORD_DATA_BYTE_44_SHIFT              (24U)
19759 /*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */
19760 #define CAN_WORD_DATA_BYTE_44(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
19761 
19762 #define CAN_WORD_DATA_BYTE_48_MASK               (0xFF000000U)
19763 #define CAN_WORD_DATA_BYTE_48_SHIFT              (24U)
19764 /*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */
19765 #define CAN_WORD_DATA_BYTE_48(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
19766 
19767 #define CAN_WORD_DATA_BYTE_52_MASK               (0xFF000000U)
19768 #define CAN_WORD_DATA_BYTE_52_SHIFT              (24U)
19769 /*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */
19770 #define CAN_WORD_DATA_BYTE_52(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
19771 
19772 #define CAN_WORD_DATA_BYTE_56_MASK               (0xFF000000U)
19773 #define CAN_WORD_DATA_BYTE_56_SHIFT              (24U)
19774 /*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */
19775 #define CAN_WORD_DATA_BYTE_56(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
19776 
19777 #define CAN_WORD_DATA_BYTE_60_MASK               (0xFF000000U)
19778 #define CAN_WORD_DATA_BYTE_60_SHIFT              (24U)
19779 /*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */
19780 #define CAN_WORD_DATA_BYTE_60(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
19781 /*! @} */
19782 
19783 /* The count of CAN_WORD */
19784 #define CAN_WORD_COUNT_MB64B_H                   (7U)
19785 
19786 /* The count of CAN_WORD */
19787 #define CAN_WORD_COUNT_MB64B_H2                  (16U)
19788 
19789 /* The count of CAN_CS */
19790 #define CAN_CS_COUNT                             (64U)
19791 
19792 /* The count of CAN_ID */
19793 #define CAN_ID_COUNT                             (64U)
19794 
19795 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
19796 /*! @{ */
19797 
19798 #define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
19799 #define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
19800 /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */
19801 #define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
19802 
19803 #define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
19804 #define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
19805 /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */
19806 #define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
19807 
19808 #define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
19809 #define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
19810 /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */
19811 #define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
19812 
19813 #define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
19814 #define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
19815 /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */
19816 #define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
19817 /*! @} */
19818 
19819 /* The count of CAN_WORD0 */
19820 #define CAN_WORD0_COUNT                          (64U)
19821 
19822 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
19823 /*! @{ */
19824 
19825 #define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
19826 #define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
19827 /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */
19828 #define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
19829 
19830 #define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
19831 #define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
19832 /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */
19833 #define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
19834 
19835 #define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
19836 #define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
19837 /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */
19838 #define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
19839 
19840 #define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
19841 #define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
19842 /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */
19843 #define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
19844 /*! @} */
19845 
19846 /* The count of CAN_WORD1 */
19847 #define CAN_WORD1_COUNT                          (64U)
19848 
19849 /*! @name RXIMR - Rx Individual Mask Registers */
19850 /*! @{ */
19851 
19852 #define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
19853 #define CAN_RXIMR_MI_SHIFT                       (0U)
19854 /*! MI - Individual Mask Bits */
19855 #define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
19856 /*! @} */
19857 
19858 /* The count of CAN_RXIMR */
19859 #define CAN_RXIMR_COUNT                          (64U)
19860 
19861 /*! @name MECR - Memory Error Control Register */
19862 /*! @{ */
19863 
19864 #define CAN_MECR_NCEFAFRZ_MASK                   (0x80U)
19865 #define CAN_MECR_NCEFAFRZ_SHIFT                  (7U)
19866 /*! NCEFAFRZ - Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode
19867  *  0b0..Keep normal operation.
19868  *  0b1..Put FlexCAN in Freeze mode (see section "Freeze mode").
19869  */
19870 #define CAN_MECR_NCEFAFRZ(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK)
19871 
19872 #define CAN_MECR_ECCDIS_MASK                     (0x100U)
19873 #define CAN_MECR_ECCDIS_SHIFT                    (8U)
19874 /*! ECCDIS - Error Correction Disable
19875  *  0b0..Enable memory error correction.
19876  *  0b1..Disable memory error correction.
19877  */
19878 #define CAN_MECR_ECCDIS(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK)
19879 
19880 #define CAN_MECR_RERRDIS_MASK                    (0x200U)
19881 #define CAN_MECR_RERRDIS_SHIFT                   (9U)
19882 /*! RERRDIS - Error Report Disable
19883  *  0b0..Enable updates of the error report registers.
19884  *  0b1..Disable updates of the error report registers.
19885  */
19886 #define CAN_MECR_RERRDIS(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK)
19887 
19888 #define CAN_MECR_EXTERRIE_MASK                   (0x2000U)
19889 #define CAN_MECR_EXTERRIE_SHIFT                  (13U)
19890 /*! EXTERRIE - Extended Error Injection Enable
19891  *  0b0..Error injection is applied only to the 32-bit word.
19892  *  0b1..Error injection is applied to the 64-bit word.
19893  */
19894 #define CAN_MECR_EXTERRIE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK)
19895 
19896 #define CAN_MECR_FAERRIE_MASK                    (0x4000U)
19897 #define CAN_MECR_FAERRIE_SHIFT                   (14U)
19898 /*! FAERRIE - FlexCAN Access Error Injection Enable
19899  *  0b0..Injection is disabled.
19900  *  0b1..Injection is enabled.
19901  */
19902 #define CAN_MECR_FAERRIE(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK)
19903 
19904 #define CAN_MECR_HAERRIE_MASK                    (0x8000U)
19905 #define CAN_MECR_HAERRIE_SHIFT                   (15U)
19906 /*! HAERRIE - Host Access Error Injection Enable
19907  *  0b0..Injection is disabled.
19908  *  0b1..Injection is enabled.
19909  */
19910 #define CAN_MECR_HAERRIE(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK)
19911 
19912 #define CAN_MECR_CEI_MSK_MASK                    (0x10000U)
19913 #define CAN_MECR_CEI_MSK_SHIFT                   (16U)
19914 /*! CEI_MSK - Correctable Errors Interrupt Mask
19915  *  0b0..Interrupt is disabled.
19916  *  0b1..Interrupt is enabled.
19917  */
19918 #define CAN_MECR_CEI_MSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK)
19919 
19920 #define CAN_MECR_FANCEI_MSK_MASK                 (0x40000U)
19921 #define CAN_MECR_FANCEI_MSK_SHIFT                (18U)
19922 /*! FANCEI_MSK - FlexCAN Access With Non-Correctable Errors Interrupt Mask
19923  *  0b0..Interrupt is disabled.
19924  *  0b1..Interrupt is enabled.
19925  */
19926 #define CAN_MECR_FANCEI_MSK(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK)
19927 
19928 #define CAN_MECR_HANCEI_MSK_MASK                 (0x80000U)
19929 #define CAN_MECR_HANCEI_MSK_SHIFT                (19U)
19930 /*! HANCEI_MSK - Host Access With Non-Correctable Errors Interrupt Mask
19931  *  0b0..Interrupt is disabled.
19932  *  0b1..Interrupt is enabled.
19933  */
19934 #define CAN_MECR_HANCEI_MSK(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK)
19935 
19936 #define CAN_MECR_ECRWRDIS_MASK                   (0x80000000U)
19937 #define CAN_MECR_ECRWRDIS_SHIFT                  (31U)
19938 /*! ECRWRDIS - Error Configuration Register Write Disable
19939  *  0b0..Write is enabled.
19940  *  0b1..Write is disabled.
19941  */
19942 #define CAN_MECR_ECRWRDIS(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK)
19943 /*! @} */
19944 
19945 /*! @name ERRIAR - Error Injection Address Register */
19946 /*! @{ */
19947 
19948 #define CAN_ERRIAR_INJADDR_L_MASK                (0x3U)
19949 #define CAN_ERRIAR_INJADDR_L_SHIFT               (0U)
19950 /*! INJADDR_L - Error Injection Address Low */
19951 #define CAN_ERRIAR_INJADDR_L(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK)
19952 
19953 #define CAN_ERRIAR_INJADDR_H_MASK                (0x3FFCU)
19954 #define CAN_ERRIAR_INJADDR_H_SHIFT               (2U)
19955 /*! INJADDR_H - Error Injection Address High */
19956 #define CAN_ERRIAR_INJADDR_H(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK)
19957 /*! @} */
19958 
19959 /*! @name ERRIDPR - Error Injection Data Pattern Register */
19960 /*! @{ */
19961 
19962 #define CAN_ERRIDPR_DFLIP_MASK                   (0xFFFFFFFFU)
19963 #define CAN_ERRIDPR_DFLIP_SHIFT                  (0U)
19964 /*! DFLIP - Data flip pattern */
19965 #define CAN_ERRIDPR_DFLIP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK)
19966 /*! @} */
19967 
19968 /*! @name ERRIPPR - Error Injection Parity Pattern Register */
19969 /*! @{ */
19970 
19971 #define CAN_ERRIPPR_PFLIP0_MASK                  (0x1FU)
19972 #define CAN_ERRIPPR_PFLIP0_SHIFT                 (0U)
19973 /*! PFLIP0 - Parity Flip Pattern For Byte 0 (Least Significant) */
19974 #define CAN_ERRIPPR_PFLIP0(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK)
19975 
19976 #define CAN_ERRIPPR_PFLIP1_MASK                  (0x1F00U)
19977 #define CAN_ERRIPPR_PFLIP1_SHIFT                 (8U)
19978 /*! PFLIP1 - Parity Flip Pattern For Byte 1 */
19979 #define CAN_ERRIPPR_PFLIP1(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK)
19980 
19981 #define CAN_ERRIPPR_PFLIP2_MASK                  (0x1F0000U)
19982 #define CAN_ERRIPPR_PFLIP2_SHIFT                 (16U)
19983 /*! PFLIP2 - Parity Flip Pattern For Byte 2 */
19984 #define CAN_ERRIPPR_PFLIP2(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK)
19985 
19986 #define CAN_ERRIPPR_PFLIP3_MASK                  (0x1F000000U)
19987 #define CAN_ERRIPPR_PFLIP3_SHIFT                 (24U)
19988 /*! PFLIP3 - Parity Flip Pattern For Byte 3 (most significant) */
19989 #define CAN_ERRIPPR_PFLIP3(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK)
19990 /*! @} */
19991 
19992 /*! @name RERRAR - Error Report Address Register */
19993 /*! @{ */
19994 
19995 #define CAN_RERRAR_ERRADDR_MASK                  (0x3FFFU)
19996 #define CAN_RERRAR_ERRADDR_SHIFT                 (0U)
19997 /*! ERRADDR - Address Where Error Detected */
19998 #define CAN_RERRAR_ERRADDR(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK)
19999 
20000 #define CAN_RERRAR_SAID_MASK                     (0x70000U)
20001 #define CAN_RERRAR_SAID_SHIFT                    (16U)
20002 /*! SAID - SAID */
20003 #define CAN_RERRAR_SAID(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK)
20004 
20005 #define CAN_RERRAR_NCE_MASK                      (0x1000000U)
20006 #define CAN_RERRAR_NCE_SHIFT                     (24U)
20007 /*! NCE - Non-Correctable Error
20008  *  0b0..Reporting a correctable error
20009  *  0b1..Reporting a non-correctable error
20010  */
20011 #define CAN_RERRAR_NCE(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK)
20012 /*! @} */
20013 
20014 /*! @name RERRDR - Error Report Data Register */
20015 /*! @{ */
20016 
20017 #define CAN_RERRDR_RDATA_MASK                    (0xFFFFFFFFU)
20018 #define CAN_RERRDR_RDATA_SHIFT                   (0U)
20019 /*! RDATA - Raw data word read from memory with error */
20020 #define CAN_RERRDR_RDATA(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK)
20021 /*! @} */
20022 
20023 /*! @name RERRSYNR - Error Report Syndrome Register */
20024 /*! @{ */
20025 
20026 #define CAN_RERRSYNR_SYND0_MASK                  (0x1FU)
20027 #define CAN_RERRSYNR_SYND0_SHIFT                 (0U)
20028 /*! SYND0 - Error Syndrome For Byte 0 (least significant) */
20029 #define CAN_RERRSYNR_SYND0(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK)
20030 
20031 #define CAN_RERRSYNR_BE0_MASK                    (0x80U)
20032 #define CAN_RERRSYNR_BE0_SHIFT                   (7U)
20033 /*! BE0 - Byte Enabled For Byte 0 (least significant)
20034  *  0b0..The byte was not read.
20035  *  0b1..The byte was read.
20036  */
20037 #define CAN_RERRSYNR_BE0(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK)
20038 
20039 #define CAN_RERRSYNR_SYND1_MASK                  (0x1F00U)
20040 #define CAN_RERRSYNR_SYND1_SHIFT                 (8U)
20041 /*! SYND1 - Error Syndrome for Byte 1 */
20042 #define CAN_RERRSYNR_SYND1(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK)
20043 
20044 #define CAN_RERRSYNR_BE1_MASK                    (0x8000U)
20045 #define CAN_RERRSYNR_BE1_SHIFT                   (15U)
20046 /*! BE1 - Byte Enabled For Byte 1
20047  *  0b0..The byte was not read.
20048  *  0b1..The byte was read.
20049  */
20050 #define CAN_RERRSYNR_BE1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK)
20051 
20052 #define CAN_RERRSYNR_SYND2_MASK                  (0x1F0000U)
20053 #define CAN_RERRSYNR_SYND2_SHIFT                 (16U)
20054 /*! SYND2 - Error Syndrome For Byte 2 */
20055 #define CAN_RERRSYNR_SYND2(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK)
20056 
20057 #define CAN_RERRSYNR_BE2_MASK                    (0x800000U)
20058 #define CAN_RERRSYNR_BE2_SHIFT                   (23U)
20059 /*! BE2 - Byte Enabled For Byte 2
20060  *  0b0..The byte was not read.
20061  *  0b1..The byte was read.
20062  */
20063 #define CAN_RERRSYNR_BE2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK)
20064 
20065 #define CAN_RERRSYNR_SYND3_MASK                  (0x1F000000U)
20066 #define CAN_RERRSYNR_SYND3_SHIFT                 (24U)
20067 /*! SYND3 - Error Syndrome For Byte 3 (most significant) */
20068 #define CAN_RERRSYNR_SYND3(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK)
20069 
20070 #define CAN_RERRSYNR_BE3_MASK                    (0x80000000U)
20071 #define CAN_RERRSYNR_BE3_SHIFT                   (31U)
20072 /*! BE3 - Byte Enabled For Byte 3 (most significant)
20073  *  0b0..The byte was not read.
20074  *  0b1..The byte was read.
20075  */
20076 #define CAN_RERRSYNR_BE3(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK)
20077 /*! @} */
20078 
20079 /*! @name ERRSR - Error Status Register */
20080 /*! @{ */
20081 
20082 #define CAN_ERRSR_CEIOF_MASK                     (0x1U)
20083 #define CAN_ERRSR_CEIOF_SHIFT                    (0U)
20084 /*! CEIOF - Correctable Error Interrupt Overrun Flag
20085  *  0b0..No overrun on correctable errors
20086  *  0b1..Overrun on correctable errors
20087  */
20088 #define CAN_ERRSR_CEIOF(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK)
20089 
20090 #define CAN_ERRSR_FANCEIOF_MASK                  (0x4U)
20091 #define CAN_ERRSR_FANCEIOF_SHIFT                 (2U)
20092 /*! FANCEIOF - FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag
20093  *  0b0..No overrun on non-correctable errors in FlexCAN access
20094  *  0b1..Overrun on non-correctable errors in FlexCAN access
20095  */
20096 #define CAN_ERRSR_FANCEIOF(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK)
20097 
20098 #define CAN_ERRSR_HANCEIOF_MASK                  (0x8U)
20099 #define CAN_ERRSR_HANCEIOF_SHIFT                 (3U)
20100 /*! HANCEIOF - Host Access With Non-Correctable Error Interrupt Overrun Flag
20101  *  0b0..No overrun on non-correctable errors in host access
20102  *  0b1..Overrun on non-correctable errors in host access
20103  */
20104 #define CAN_ERRSR_HANCEIOF(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK)
20105 
20106 #define CAN_ERRSR_CEIF_MASK                      (0x10000U)
20107 #define CAN_ERRSR_CEIF_SHIFT                     (16U)
20108 /*! CEIF - Correctable Error Interrupt Flag
20109  *  0b0..No correctable errors were detected so far.
20110  *  0b1..A correctable error was detected.
20111  */
20112 #define CAN_ERRSR_CEIF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK)
20113 
20114 #define CAN_ERRSR_FANCEIF_MASK                   (0x40000U)
20115 #define CAN_ERRSR_FANCEIF_SHIFT                  (18U)
20116 /*! FANCEIF - FlexCAN Access With Non-Correctable Error Interrupt Flag
20117  *  0b0..No non-correctable errors were detected in FlexCAN accesses so far.
20118  *  0b1..A non-correctable error was detected in a FlexCAN access.
20119  */
20120 #define CAN_ERRSR_FANCEIF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK)
20121 
20122 #define CAN_ERRSR_HANCEIF_MASK                   (0x80000U)
20123 #define CAN_ERRSR_HANCEIF_SHIFT                  (19U)
20124 /*! HANCEIF - Host Access With Non-Correctable Error Interrupt Flag
20125  *  0b0..No non-correctable errors were detected in host accesses so far.
20126  *  0b1..A non-correctable error was detected in a host access.
20127  */
20128 #define CAN_ERRSR_HANCEIF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK)
20129 /*! @} */
20130 
20131 /*! @name FDCTRL - CAN FD Control Register */
20132 /*! @{ */
20133 
20134 #define CAN_FDCTRL_TDCVAL_MASK                   (0x3FU)
20135 #define CAN_FDCTRL_TDCVAL_SHIFT                  (0U)
20136 /*! TDCVAL - Transceiver Delay Compensation Value */
20137 #define CAN_FDCTRL_TDCVAL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
20138 
20139 #define CAN_FDCTRL_TDCOFF_MASK                   (0x1F00U)
20140 #define CAN_FDCTRL_TDCOFF_SHIFT                  (8U)
20141 /*! TDCOFF - Transceiver Delay Compensation Offset */
20142 #define CAN_FDCTRL_TDCOFF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
20143 
20144 #define CAN_FDCTRL_TDCFAIL_MASK                  (0x4000U)
20145 #define CAN_FDCTRL_TDCFAIL_SHIFT                 (14U)
20146 /*! TDCFAIL - Transceiver Delay Compensation Fail
20147  *  0b0..Measured loop delay is in range.
20148  *  0b1..Measured loop delay is out of range.
20149  */
20150 #define CAN_FDCTRL_TDCFAIL(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
20151 
20152 #define CAN_FDCTRL_TDCEN_MASK                    (0x8000U)
20153 #define CAN_FDCTRL_TDCEN_SHIFT                   (15U)
20154 /*! TDCEN - Transceiver Delay Compensation Enable
20155  *  0b0..TDC is disabled
20156  *  0b1..TDC is enabled
20157  */
20158 #define CAN_FDCTRL_TDCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
20159 
20160 #define CAN_FDCTRL_MBDSR0_MASK                   (0x30000U)
20161 #define CAN_FDCTRL_MBDSR0_SHIFT                  (16U)
20162 /*! MBDSR0 - Message Buffer Data Size for Region 0
20163  *  0b00..Selects 8 bytes per message buffer.
20164  *  0b01..Selects 16 bytes per message buffer.
20165  *  0b10..Selects 32 bytes per message buffer.
20166  *  0b11..Selects 64 bytes per message buffer.
20167  */
20168 #define CAN_FDCTRL_MBDSR0(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
20169 
20170 #define CAN_FDCTRL_MBDSR1_MASK                   (0x180000U)
20171 #define CAN_FDCTRL_MBDSR1_SHIFT                  (19U)
20172 /*! MBDSR1 - Message Buffer Data Size for Region 1
20173  *  0b00..Selects 8 bytes per message buffer.
20174  *  0b01..Selects 16 bytes per message buffer.
20175  *  0b10..Selects 32 bytes per message buffer.
20176  *  0b11..Selects 64 bytes per message buffer.
20177  */
20178 #define CAN_FDCTRL_MBDSR1(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
20179 
20180 #define CAN_FDCTRL_FDRATE_MASK                   (0x80000000U)
20181 #define CAN_FDCTRL_FDRATE_SHIFT                  (31U)
20182 /*! FDRATE - Bit Rate Switch Enable
20183  *  0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
20184  *  0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
20185  */
20186 #define CAN_FDCTRL_FDRATE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
20187 /*! @} */
20188 
20189 /*! @name FDCBT - CAN FD Bit Timing Register */
20190 /*! @{ */
20191 
20192 #define CAN_FDCBT_FPSEG2_MASK                    (0x7U)
20193 #define CAN_FDCBT_FPSEG2_SHIFT                   (0U)
20194 /*! FPSEG2 - Fast Phase Segment 2 */
20195 #define CAN_FDCBT_FPSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
20196 
20197 #define CAN_FDCBT_FPSEG1_MASK                    (0xE0U)
20198 #define CAN_FDCBT_FPSEG1_SHIFT                   (5U)
20199 /*! FPSEG1 - Fast Phase Segment 1 */
20200 #define CAN_FDCBT_FPSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
20201 
20202 #define CAN_FDCBT_FPROPSEG_MASK                  (0x7C00U)
20203 #define CAN_FDCBT_FPROPSEG_SHIFT                 (10U)
20204 /*! FPROPSEG - Fast Propagation Segment */
20205 #define CAN_FDCBT_FPROPSEG(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
20206 
20207 #define CAN_FDCBT_FRJW_MASK                      (0x70000U)
20208 #define CAN_FDCBT_FRJW_SHIFT                     (16U)
20209 /*! FRJW - Fast Resync Jump Width */
20210 #define CAN_FDCBT_FRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
20211 
20212 #define CAN_FDCBT_FPRESDIV_MASK                  (0x3FF00000U)
20213 #define CAN_FDCBT_FPRESDIV_SHIFT                 (20U)
20214 /*! FPRESDIV - Fast Prescaler Division Factor */
20215 #define CAN_FDCBT_FPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
20216 /*! @} */
20217 
20218 /*! @name FDCRC - CAN FD CRC Register */
20219 /*! @{ */
20220 
20221 #define CAN_FDCRC_FD_TXCRC_MASK                  (0x1FFFFFU)
20222 #define CAN_FDCRC_FD_TXCRC_SHIFT                 (0U)
20223 /*! FD_TXCRC - Extended Transmitted CRC value */
20224 #define CAN_FDCRC_FD_TXCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
20225 
20226 #define CAN_FDCRC_FD_MBCRC_MASK                  (0x7F000000U)
20227 #define CAN_FDCRC_FD_MBCRC_SHIFT                 (24U)
20228 /*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC */
20229 #define CAN_FDCRC_FD_MBCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
20230 /*! @} */
20231 
20232 
20233 /*!
20234  * @}
20235  */ /* end of group CAN_Register_Masks */
20236 
20237 
20238 /* CAN - Peripheral instance base addresses */
20239 /** Peripheral CAN1 base address */
20240 #define CAN1_BASE                                (0x400C4000u)
20241 /** Peripheral CAN1 base pointer */
20242 #define CAN1                                     ((CAN_Type *)CAN1_BASE)
20243 /** Peripheral CAN2 base address */
20244 #define CAN2_BASE                                (0x400C8000u)
20245 /** Peripheral CAN2 base pointer */
20246 #define CAN2                                     ((CAN_Type *)CAN2_BASE)
20247 /** Peripheral CAN3 base address */
20248 #define CAN3_BASE                                (0x40C3C000u)
20249 /** Peripheral CAN3 base pointer */
20250 #define CAN3                                     ((CAN_Type *)CAN3_BASE)
20251 /** Array initializer of CAN peripheral base addresses */
20252 #define CAN_BASE_ADDRS                           { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE }
20253 /** Array initializer of CAN peripheral base pointers */
20254 #define CAN_BASE_PTRS                            { (CAN_Type *)0u, CAN1, CAN2, CAN3 }
20255 /** Interrupt vectors for the CAN peripheral type */
20256 #define CAN_Rx_Warning_IRQS                      { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20257 #define CAN_Tx_Warning_IRQS                      { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20258 #define CAN_Wake_Up_IRQS                         { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20259 #define CAN_Error_IRQS                           { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20260 #define CAN_Bus_Off_IRQS                         { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20261 #define CAN_ORed_Message_buffer_IRQS             { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
20262 
20263 /*!
20264  * @}
20265  */ /* end of group CAN_Peripheral_Access_Layer */
20266 
20267 
20268 /* ----------------------------------------------------------------------------
20269    -- CAN_WRAPPER Peripheral Access Layer
20270    ---------------------------------------------------------------------------- */
20271 
20272 /*!
20273  * @addtogroup CAN_WRAPPER_Peripheral_Access_Layer CAN_WRAPPER Peripheral Access Layer
20274  * @{
20275  */
20276 
20277 /** CAN_WRAPPER - Register Layout Typedef */
20278 typedef struct {
20279        uint8_t RESERVED_0[2528];
20280   __IO uint32_t GFWR;                              /**< Glitch Filter Width Register, offset: 0x9E0 */
20281 } CAN_WRAPPER_Type;
20282 
20283 /* ----------------------------------------------------------------------------
20284    -- CAN_WRAPPER Register Masks
20285    ---------------------------------------------------------------------------- */
20286 
20287 /*!
20288  * @addtogroup CAN_WRAPPER_Register_Masks CAN_WRAPPER Register Masks
20289  * @{
20290  */
20291 
20292 /*! @name GFWR - Glitch Filter Width Register */
20293 /*! @{ */
20294 
20295 #define CAN_WRAPPER_GFWR_GFWR_MASK               (0xFFU)
20296 #define CAN_WRAPPER_GFWR_GFWR_SHIFT              (0U)
20297 /*! GFWR - Glitch Filter Width */
20298 #define CAN_WRAPPER_GFWR_GFWR(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WRAPPER_GFWR_GFWR_SHIFT)) & CAN_WRAPPER_GFWR_GFWR_MASK)
20299 /*! @} */
20300 
20301 
20302 /*!
20303  * @}
20304  */ /* end of group CAN_WRAPPER_Register_Masks */
20305 
20306 
20307 /* CAN_WRAPPER - Peripheral instance base addresses */
20308 /** Peripheral CAN1_WRAPPER base address */
20309 #define CAN1_WRAPPER_BASE                        (0x400C4000u)
20310 /** Peripheral CAN1_WRAPPER base pointer */
20311 #define CAN1_WRAPPER                             ((CAN_WRAPPER_Type *)CAN1_WRAPPER_BASE)
20312 /** Peripheral CAN2_WRAPPER base address */
20313 #define CAN2_WRAPPER_BASE                        (0x400C8000u)
20314 /** Peripheral CAN2_WRAPPER base pointer */
20315 #define CAN2_WRAPPER                             ((CAN_WRAPPER_Type *)CAN2_WRAPPER_BASE)
20316 /** Peripheral CAN3_WRAPPER base address */
20317 #define CAN3_WRAPPER_BASE                        (0x40C3C000u)
20318 /** Peripheral CAN3_WRAPPER base pointer */
20319 #define CAN3_WRAPPER                             ((CAN_WRAPPER_Type *)CAN3_WRAPPER_BASE)
20320 /** Array initializer of CAN_WRAPPER peripheral base addresses */
20321 #define CAN_WRAPPER_BASE_ADDRS                   { 0u, CAN1_WRAPPER_BASE, CAN2_WRAPPER_BASE, CAN3_WRAPPER_BASE }
20322 /** Array initializer of CAN_WRAPPER peripheral base pointers */
20323 #define CAN_WRAPPER_BASE_PTRS                    { (CAN_WRAPPER_Type *)0u, CAN1_WRAPPER, CAN2_WRAPPER, CAN3_WRAPPER }
20324 
20325 /*!
20326  * @}
20327  */ /* end of group CAN_WRAPPER_Peripheral_Access_Layer */
20328 
20329 
20330 /* ----------------------------------------------------------------------------
20331    -- CCM Peripheral Access Layer
20332    ---------------------------------------------------------------------------- */
20333 
20334 /*!
20335  * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
20336  * @{
20337  */
20338 
20339 /** CCM - Register Layout Typedef */
20340 typedef struct {
20341   struct {                                         /* offset: 0x0, array step: 0x80 */
20342     __IO uint32_t CONTROL;                           /**< Clock root control, array offset: 0x0, array step: 0x80 */
20343     __IO uint32_t CONTROL_SET;                       /**< Clock root control, array offset: 0x4, array step: 0x80 */
20344     __IO uint32_t CONTROL_CLR;                       /**< Clock root control, array offset: 0x8, array step: 0x80 */
20345     __IO uint32_t CONTROL_TOG;                       /**< Clock root control, array offset: 0xC, array step: 0x80 */
20346          uint8_t RESERVED_0[16];
20347     __I  uint32_t STATUS0;                           /**< Clock root working status, array offset: 0x20, array step: 0x80 */
20348     __I  uint32_t STATUS1;                           /**< Clock root low power status, array offset: 0x24, array step: 0x80 */
20349          uint8_t RESERVED_1[4];
20350     __I  uint32_t CONFIG;                            /**< Clock root configuration, array offset: 0x2C, array step: 0x80 */
20351     __IO uint32_t AUTHEN;                            /**< Clock root access control, array offset: 0x30, array step: 0x80 */
20352     __IO uint32_t AUTHEN_SET;                        /**< Clock root access control, array offset: 0x34, array step: 0x80 */
20353     __IO uint32_t AUTHEN_CLR;                        /**< Clock root access control, array offset: 0x38, array step: 0x80 */
20354     __IO uint32_t AUTHEN_TOG;                        /**< Clock root access control, array offset: 0x3C, array step: 0x80 */
20355     __IO uint32_t SETPOINT[16];                      /**< Setpoint setting, array offset: 0x40, array step: index*0x80, index2*0x4, valid indices: [0][0-15], [1][0-15], [2][0-15], [3][0-15], [4][0-15], [20][0-15], [21][0-15], [77][0-15], [78][0-15] */
20356   } CLOCK_ROOT[79];
20357        uint8_t RESERVED_0[6272];
20358   struct {                                         /* offset: 0x4000, array step: 0x80 */
20359     __IO uint32_t CONTROL;                           /**< Clock group control, array offset: 0x4000, array step: 0x80 */
20360     __IO uint32_t CONTROL_SET;                       /**< Clock group control, array offset: 0x4004, array step: 0x80 */
20361     __IO uint32_t CONTROL_CLR;                       /**< Clock group control, array offset: 0x4008, array step: 0x80 */
20362     __IO uint32_t CONTROL_TOG;                       /**< Clock group control, array offset: 0x400C, array step: 0x80 */
20363          uint8_t RESERVED_0[16];
20364     __IO uint32_t STATUS0;                           /**< Clock group working status, array offset: 0x4020, array step: 0x80 */
20365     __I  uint32_t STATUS1;                           /**< Clock group low power/extend status, array offset: 0x4024, array step: 0x80 */
20366          uint8_t RESERVED_1[4];
20367     __I  uint32_t CONFIG;                            /**< Clock group configuration, array offset: 0x402C, array step: 0x80 */
20368     __IO uint32_t AUTHEN;                            /**< Clock group access control, array offset: 0x4030, array step: 0x80 */
20369     __IO uint32_t AUTHEN_SET;                        /**< Clock group access control, array offset: 0x4034, array step: 0x80 */
20370     __IO uint32_t AUTHEN_CLR;                        /**< Clock group access control, array offset: 0x4038, array step: 0x80 */
20371     __IO uint32_t AUTHEN_TOG;                        /**< Clock group access control, array offset: 0x403C, array step: 0x80 */
20372     __IO uint32_t SETPOINT[16];                      /**< Setpoint setting, array offset: 0x4040, array step: index*0x80, index2*0x4 */
20373   } CLOCK_GROUP[2];
20374        uint8_t RESERVED_1[1792];
20375   struct {                                         /* offset: 0x4800, array step: 0x20 */
20376     __IO uint32_t GPR_SHARED;                        /**< General Purpose Register, array offset: 0x4800, array step: 0x20 */
20377     __IO uint32_t SET;                               /**< General Purpose Register, array offset: 0x4804, array step: 0x20 */
20378     __IO uint32_t CLR;                               /**< General Purpose Register, array offset: 0x4808, array step: 0x20 */
20379     __IO uint32_t TOG;                               /**< General Purpose Register, array offset: 0x480C, array step: 0x20 */
20380     __IO uint32_t AUTHEN;                            /**< GPR access control, array offset: 0x4810, array step: 0x20 */
20381     __IO uint32_t AUTHEN_SET;                        /**< GPR access control, array offset: 0x4814, array step: 0x20 */
20382     __IO uint32_t AUTHEN_CLR;                        /**< GPR access control, array offset: 0x4818, array step: 0x20 */
20383     __IO uint32_t AUTHEN_TOG;                        /**< GPR access control, array offset: 0x481C, array step: 0x20 */
20384   } GPR_SHARED[8];
20385        uint8_t RESERVED_2[800];
20386   __IO uint32_t GPR_PRIVATE1;                      /**< General Purpose Register, offset: 0x4C20 */
20387   __IO uint32_t GPR_PRIVATE1_SET;                  /**< General Purpose Register, offset: 0x4C24 */
20388   __IO uint32_t GPR_PRIVATE1_CLR;                  /**< General Purpose Register, offset: 0x4C28 */
20389   __IO uint32_t GPR_PRIVATE1_TOG;                  /**< General Purpose Register, offset: 0x4C2C */
20390   __IO uint32_t GPR_PRIVATE1_AUTHEN;               /**< GPR access control, offset: 0x4C30 */
20391   __IO uint32_t GPR_PRIVATE1_AUTHEN_SET;           /**< GPR access control, offset: 0x4C34 */
20392   __IO uint32_t GPR_PRIVATE1_AUTHEN_CLR;           /**< GPR access control, offset: 0x4C38 */
20393   __IO uint32_t GPR_PRIVATE1_AUTHEN_TOG;           /**< GPR access control, offset: 0x4C3C */
20394   __IO uint32_t GPR_PRIVATE2;                      /**< General Purpose Register, offset: 0x4C40 */
20395   __IO uint32_t GPR_PRIVATE2_SET;                  /**< General Purpose Register, offset: 0x4C44 */
20396   __IO uint32_t GPR_PRIVATE2_CLR;                  /**< General Purpose Register, offset: 0x4C48 */
20397   __IO uint32_t GPR_PRIVATE2_TOG;                  /**< General Purpose Register, offset: 0x4C4C */
20398   __IO uint32_t GPR_PRIVATE2_AUTHEN;               /**< GPR access control, offset: 0x4C50 */
20399   __IO uint32_t GPR_PRIVATE2_AUTHEN_SET;           /**< GPR access control, offset: 0x4C54 */
20400   __IO uint32_t GPR_PRIVATE2_AUTHEN_CLR;           /**< GPR access control, offset: 0x4C58 */
20401   __IO uint32_t GPR_PRIVATE2_AUTHEN_TOG;           /**< GPR access control, offset: 0x4C5C */
20402   __IO uint32_t GPR_PRIVATE3;                      /**< General Purpose Register, offset: 0x4C60 */
20403   __IO uint32_t GPR_PRIVATE3_SET;                  /**< General Purpose Register, offset: 0x4C64 */
20404   __IO uint32_t GPR_PRIVATE3_CLR;                  /**< General Purpose Register, offset: 0x4C68 */
20405   __IO uint32_t GPR_PRIVATE3_TOG;                  /**< General Purpose Register, offset: 0x4C6C */
20406   __IO uint32_t GPR_PRIVATE3_AUTHEN;               /**< GPR access control, offset: 0x4C70 */
20407   __IO uint32_t GPR_PRIVATE3_AUTHEN_SET;           /**< GPR access control, offset: 0x4C74 */
20408   __IO uint32_t GPR_PRIVATE3_AUTHEN_CLR;           /**< GPR access control, offset: 0x4C78 */
20409   __IO uint32_t GPR_PRIVATE3_AUTHEN_TOG;           /**< GPR access control, offset: 0x4C7C */
20410   __IO uint32_t GPR_PRIVATE4;                      /**< General Purpose Register, offset: 0x4C80 */
20411   __IO uint32_t GPR_PRIVATE4_SET;                  /**< General Purpose Register, offset: 0x4C84 */
20412   __IO uint32_t GPR_PRIVATE4_CLR;                  /**< General Purpose Register, offset: 0x4C88 */
20413   __IO uint32_t GPR_PRIVATE4_TOG;                  /**< General Purpose Register, offset: 0x4C8C */
20414   __IO uint32_t GPR_PRIVATE4_AUTHEN;               /**< GPR access control, offset: 0x4C90 */
20415   __IO uint32_t GPR_PRIVATE4_AUTHEN_SET;           /**< GPR access control, offset: 0x4C94 */
20416   __IO uint32_t GPR_PRIVATE4_AUTHEN_CLR;           /**< GPR access control, offset: 0x4C98 */
20417   __IO uint32_t GPR_PRIVATE4_AUTHEN_TOG;           /**< GPR access control, offset: 0x4C9C */
20418   __IO uint32_t GPR_PRIVATE5;                      /**< General Purpose Register, offset: 0x4CA0 */
20419   __IO uint32_t GPR_PRIVATE5_SET;                  /**< General Purpose Register, offset: 0x4CA4 */
20420   __IO uint32_t GPR_PRIVATE5_CLR;                  /**< General Purpose Register, offset: 0x4CA8 */
20421   __IO uint32_t GPR_PRIVATE5_TOG;                  /**< General Purpose Register, offset: 0x4CAC */
20422   __IO uint32_t GPR_PRIVATE5_AUTHEN;               /**< GPR access control, offset: 0x4CB0 */
20423   __IO uint32_t GPR_PRIVATE5_AUTHEN_SET;           /**< GPR access control, offset: 0x4CB4 */
20424   __IO uint32_t GPR_PRIVATE5_AUTHEN_CLR;           /**< GPR access control, offset: 0x4CB8 */
20425   __IO uint32_t GPR_PRIVATE5_AUTHEN_TOG;           /**< GPR access control, offset: 0x4CBC */
20426   __IO uint32_t GPR_PRIVATE6;                      /**< General Purpose Register, offset: 0x4CC0 */
20427   __IO uint32_t GPR_PRIVATE6_SET;                  /**< General Purpose Register, offset: 0x4CC4 */
20428   __IO uint32_t GPR_PRIVATE6_CLR;                  /**< General Purpose Register, offset: 0x4CC8 */
20429   __IO uint32_t GPR_PRIVATE6_TOG;                  /**< General Purpose Register, offset: 0x4CCC */
20430   __IO uint32_t GPR_PRIVATE6_AUTHEN;               /**< GPR access control, offset: 0x4CD0 */
20431   __IO uint32_t GPR_PRIVATE6_AUTHEN_SET;           /**< GPR access control, offset: 0x4CD4 */
20432   __IO uint32_t GPR_PRIVATE6_AUTHEN_CLR;           /**< GPR access control, offset: 0x4CD8 */
20433   __IO uint32_t GPR_PRIVATE6_AUTHEN_TOG;           /**< GPR access control, offset: 0x4CDC */
20434   __IO uint32_t GPR_PRIVATE7;                      /**< General Purpose Register, offset: 0x4CE0 */
20435   __IO uint32_t GPR_PRIVATE7_SET;                  /**< General Purpose Register, offset: 0x4CE4 */
20436   __IO uint32_t GPR_PRIVATE7_CLR;                  /**< General Purpose Register, offset: 0x4CE8 */
20437   __IO uint32_t GPR_PRIVATE7_TOG;                  /**< General Purpose Register, offset: 0x4CEC */
20438   __IO uint32_t GPR_PRIVATE7_AUTHEN;               /**< GPR access control, offset: 0x4CF0 */
20439   __IO uint32_t GPR_PRIVATE7_AUTHEN_SET;           /**< GPR access control, offset: 0x4CF4 */
20440   __IO uint32_t GPR_PRIVATE7_AUTHEN_CLR;           /**< GPR access control, offset: 0x4CF8 */
20441   __IO uint32_t GPR_PRIVATE7_AUTHEN_TOG;           /**< GPR access control, offset: 0x4CFC */
20442        uint8_t RESERVED_3[768];
20443   struct {                                         /* offset: 0x5000, array step: 0x20 */
20444     __IO uint32_t DIRECT;                            /**< Clock source direct control, array offset: 0x5000, array step: 0x20 */
20445     __IO uint32_t DOMAINr;                           /**< Clock source domain control, array offset: 0x5004, array step: 0x20, 'r' suffix has been added to avoid clash with DOMAIN symbol in math.h */
20446     __IO uint32_t SETPOINT;                          /**< Clock source Setpoint setting, array offset: 0x5008, array step: 0x20 */
20447          uint8_t RESERVED_0[4];
20448     __I  uint32_t STATUS0;                           /**< Clock source working status, array offset: 0x5010, array step: 0x20 */
20449     __I  uint32_t STATUS1;                           /**< Clock source low power status, array offset: 0x5014, array step: 0x20 */
20450     __I  uint32_t CONFIG;                            /**< Clock source configuration, array offset: 0x5018, array step: 0x20 */
20451     __IO uint32_t AUTHEN;                            /**< Clock source access control, array offset: 0x501C, array step: 0x20 */
20452   } OSCPLL[29];
20453        uint8_t RESERVED_4[3168];
20454   struct {                                         /* offset: 0x6000, array step: 0x20 */
20455     __IO uint32_t DIRECT;                            /**< LPCG direct control, array offset: 0x6000, array step: 0x20 */
20456     __IO uint32_t DOMAINr;                           /**< LPCG domain control, array offset: 0x6004, array step: 0x20, 'r' suffix has been added to avoid clash with DOMAIN symbol in math.h */
20457     __IO uint32_t SETPOINT;                          /**< LPCG Setpoint setting, array offset: 0x6008, array step: 0x20, valid indices: [2-12, 14-19, 24-40, 43-48] */
20458          uint8_t RESERVED_0[4];
20459     __I  uint32_t STATUS0;                           /**< LPCG working status, array offset: 0x6010, array step: 0x20 */
20460     __I  uint32_t STATUS1;                           /**< LPCG low power status, array offset: 0x6014, array step: 0x20 */
20461     __I  uint32_t CONFIG;                            /**< LPCG configuration, array offset: 0x6018, array step: 0x20 */
20462     __IO uint32_t AUTHEN;                            /**< LPCG access control, array offset: 0x601C, array step: 0x20 */
20463   } LPCG[138];
20464 } CCM_Type;
20465 
20466 /* ----------------------------------------------------------------------------
20467    -- CCM Register Masks
20468    ---------------------------------------------------------------------------- */
20469 
20470 /*!
20471  * @addtogroup CCM_Register_Masks CCM Register Masks
20472  * @{
20473  */
20474 
20475 /*! @name CLOCK_ROOT_CONTROL - Clock root control */
20476 /*! @{ */
20477 
20478 #define CCM_CLOCK_ROOT_CONTROL_DIV_MASK          (0xFFU)
20479 #define CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT         (0U)
20480 /*! DIV - Clock divider */
20481 #define CCM_CLOCK_ROOT_CONTROL_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_DIV_MASK)
20482 
20483 #define CCM_CLOCK_ROOT_CONTROL_MUX_MASK          (0x700U)
20484 #define CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT         (8U)
20485 /*! MUX - Clock multiplexer */
20486 #define CCM_CLOCK_ROOT_CONTROL_MUX(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_MUX_MASK)
20487 
20488 #define CCM_CLOCK_ROOT_CONTROL_OFF_MASK          (0x1000000U)
20489 #define CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT         (24U)
20490 /*! OFF - OFF
20491  *  0b0..Turn on clock
20492  *  0b1..Turn off clock
20493  */
20494 #define CCM_CLOCK_ROOT_CONTROL_OFF(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_OFF_MASK)
20495 /*! @} */
20496 
20497 /* The count of CCM_CLOCK_ROOT_CONTROL */
20498 #define CCM_CLOCK_ROOT_CONTROL_COUNT             (79U)
20499 
20500 /*! @name CLOCK_ROOT_CONTROL_SET - Clock root control */
20501 /*! @{ */
20502 
20503 #define CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK      (0xFFU)
20504 #define CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT     (0U)
20505 /*! DIV - Clock divider */
20506 #define CCM_CLOCK_ROOT_CONTROL_SET_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK)
20507 
20508 #define CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK      (0x700U)
20509 #define CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT     (8U)
20510 /*! MUX - Clock multiplexer */
20511 #define CCM_CLOCK_ROOT_CONTROL_SET_MUX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK)
20512 
20513 #define CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK      (0x1000000U)
20514 #define CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT     (24U)
20515 /*! OFF - OFF */
20516 #define CCM_CLOCK_ROOT_CONTROL_SET_OFF(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK)
20517 /*! @} */
20518 
20519 /* The count of CCM_CLOCK_ROOT_CONTROL_SET */
20520 #define CCM_CLOCK_ROOT_CONTROL_SET_COUNT         (79U)
20521 
20522 /*! @name CLOCK_ROOT_CONTROL_CLR - Clock root control */
20523 /*! @{ */
20524 
20525 #define CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK      (0xFFU)
20526 #define CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT     (0U)
20527 /*! DIV - Clock divider */
20528 #define CCM_CLOCK_ROOT_CONTROL_CLR_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK)
20529 
20530 #define CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK      (0x700U)
20531 #define CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT     (8U)
20532 /*! MUX - Clock multiplexer */
20533 #define CCM_CLOCK_ROOT_CONTROL_CLR_MUX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK)
20534 
20535 #define CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK      (0x1000000U)
20536 #define CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT     (24U)
20537 /*! OFF - OFF */
20538 #define CCM_CLOCK_ROOT_CONTROL_CLR_OFF(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK)
20539 /*! @} */
20540 
20541 /* The count of CCM_CLOCK_ROOT_CONTROL_CLR */
20542 #define CCM_CLOCK_ROOT_CONTROL_CLR_COUNT         (79U)
20543 
20544 /*! @name CLOCK_ROOT_CONTROL_TOG - Clock root control */
20545 /*! @{ */
20546 
20547 #define CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK      (0xFFU)
20548 #define CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT     (0U)
20549 /*! DIV - Clock divider */
20550 #define CCM_CLOCK_ROOT_CONTROL_TOG_DIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK)
20551 
20552 #define CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK      (0x700U)
20553 #define CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT     (8U)
20554 /*! MUX - Clock multiplexer */
20555 #define CCM_CLOCK_ROOT_CONTROL_TOG_MUX(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK)
20556 
20557 #define CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK      (0x1000000U)
20558 #define CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT     (24U)
20559 /*! OFF - OFF */
20560 #define CCM_CLOCK_ROOT_CONTROL_TOG_OFF(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK)
20561 /*! @} */
20562 
20563 /* The count of CCM_CLOCK_ROOT_CONTROL_TOG */
20564 #define CCM_CLOCK_ROOT_CONTROL_TOG_COUNT         (79U)
20565 
20566 /*! @name CLOCK_ROOT_STATUS0 - Clock root working status */
20567 /*! @{ */
20568 
20569 #define CCM_CLOCK_ROOT_STATUS0_DIV_MASK          (0xFFU)
20570 #define CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT         (0U)
20571 /*! DIV - Current clock root DIV setting */
20572 #define CCM_CLOCK_ROOT_STATUS0_DIV(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_DIV_MASK)
20573 
20574 #define CCM_CLOCK_ROOT_STATUS0_MUX_MASK          (0x700U)
20575 #define CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT         (8U)
20576 /*! MUX - Current clock root MUX setting */
20577 #define CCM_CLOCK_ROOT_STATUS0_MUX(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_MUX_MASK)
20578 
20579 #define CCM_CLOCK_ROOT_STATUS0_OFF_MASK          (0x1000000U)
20580 #define CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT         (24U)
20581 /*! OFF - Current clock root OFF setting
20582  *  0b0..Clock is running
20583  *  0b1..Clock is disabled/off
20584  */
20585 #define CCM_CLOCK_ROOT_STATUS0_OFF(x)            (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_OFF_MASK)
20586 
20587 #define CCM_CLOCK_ROOT_STATUS0_POWERDOWN_MASK    (0x8000000U)
20588 #define CCM_CLOCK_ROOT_STATUS0_POWERDOWN_SHIFT   (27U)
20589 /*! POWERDOWN - Current clock root POWERDOWN setting
20590  *  0b1..Clock root is Powered Down
20591  *  0b0..Clock root is running
20592  */
20593 #define CCM_CLOCK_ROOT_STATUS0_POWERDOWN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_POWERDOWN_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_POWERDOWN_MASK)
20594 
20595 #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK   (0x10000000U)
20596 #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT  (28U)
20597 /*! SLICE_BUSY - Internal updating in generation logic
20598  *  0b1..Clock generation logic is applying the new setting
20599  *  0b0..Clock generation logic is not busy
20600  */
20601 #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK)
20602 
20603 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK (0x20000000U)
20604 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT (29U)
20605 /*! UPDATE_FORWARD - Internal status synchronization to clock generation logic
20606  *  0b1..Synchronization in process
20607  *  0b0..Synchronization not in process
20608  */
20609 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK)
20610 
20611 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_MASK (0x40000000U)
20612 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_SHIFT (30U)
20613 /*! UPDATE_REVERSE - Internal status synchronization from clock generation logic
20614  *  0b1..Synchronization in process
20615  *  0b0..Synchronization not in process
20616  */
20617 #define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_MASK)
20618 
20619 #define CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK     (0x80000000U)
20620 #define CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT    (31U)
20621 /*! CHANGING - Internal updating in clock root
20622  *  0b1..Clock generation logic is updating currently
20623  *  0b0..Clock Status is not updating currently
20624  */
20625 #define CCM_CLOCK_ROOT_STATUS0_CHANGING(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK)
20626 /*! @} */
20627 
20628 /* The count of CCM_CLOCK_ROOT_STATUS0 */
20629 #define CCM_CLOCK_ROOT_STATUS0_COUNT             (79U)
20630 
20631 /*! @name CLOCK_ROOT_STATUS1 - Clock root low power status */
20632 /*! @{ */
20633 
20634 #define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_MASK (0xF0000U)
20635 #define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_SHIFT (16U)
20636 /*! TARGET_SETPOINT - Target Setpoint */
20637 #define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_MASK)
20638 
20639 #define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
20640 #define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
20641 /*! CURRENT_SETPOINT - Current Setpoint */
20642 #define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_MASK)
20643 
20644 #define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_MASK (0x1000000U)
20645 #define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_SHIFT (24U)
20646 /*! DOWN_REQUEST - Clock frequency decrease request
20647  *  0b1..Frequency decrease requested
20648  *  0b0..Frequency decrease not requested
20649  */
20650 #define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_MASK)
20651 
20652 #define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_MASK    (0x2000000U)
20653 #define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_SHIFT   (25U)
20654 /*! DOWN_DONE - Clock frequency decrease finish
20655  *  0b1..Frequency decrease completed
20656  *  0b0..Frequency decrease not completed
20657  */
20658 #define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_MASK)
20659 
20660 #define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_MASK   (0x4000000U)
20661 #define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_SHIFT  (26U)
20662 /*! UP_REQUEST - Clock frequency increase request
20663  *  0b1..Frequency increase requested
20664  *  0b0..Frequency increase not requested
20665  */
20666 #define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_MASK)
20667 
20668 #define CCM_CLOCK_ROOT_STATUS1_UP_DONE_MASK      (0x8000000U)
20669 #define CCM_CLOCK_ROOT_STATUS1_UP_DONE_SHIFT     (27U)
20670 /*! UP_DONE - Clock frequency increase finish
20671  *  0b1..Frequency increase completed
20672  *  0b0..Frequency increase not completed
20673  */
20674 #define CCM_CLOCK_ROOT_STATUS1_UP_DONE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_UP_DONE_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_UP_DONE_MASK)
20675 /*! @} */
20676 
20677 /* The count of CCM_CLOCK_ROOT_STATUS1 */
20678 #define CCM_CLOCK_ROOT_STATUS1_COUNT             (79U)
20679 
20680 /*! @name CLOCK_ROOT_CONFIG - Clock root configuration */
20681 /*! @{ */
20682 
20683 #define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK (0x10U)
20684 #define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
20685 /*! SETPOINT_PRESENT - Setpoint present
20686  *  0b1..Setpoint is implemented.
20687  *  0b0..Setpoint is not implemented.
20688  */
20689 #define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK)
20690 /*! @} */
20691 
20692 /* The count of CCM_CLOCK_ROOT_CONFIG */
20693 #define CCM_CLOCK_ROOT_CONFIG_COUNT              (79U)
20694 
20695 /*! @name CLOCK_ROOT_AUTHEN - Clock root access control */
20696 /*! @{ */
20697 
20698 #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK       (0x1U)
20699 #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT      (0U)
20700 /*! TZ_USER - User access
20701  *  0b1..Clock can be changed in user mode
20702  *  0b0..Clock cannot be changed in user mode
20703  */
20704 #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER(x)         (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK)
20705 
20706 #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK         (0x2U)
20707 #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT        (1U)
20708 /*! TZ_NS - Non-secure access
20709  *  0b0..Cannot be changed in Non-secure mode
20710  *  0b1..Can be changed in Non-secure mode
20711  */
20712 #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS(x)           (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK)
20713 
20714 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK       (0x10U)
20715 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT      (4U)
20716 /*! LOCK_TZ - Lock truszone setting
20717  *  0b0..Trustzone setting is not locked
20718  *  0b1..Trustzone setting is locked
20719  */
20720 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ(x)         (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK)
20721 
20722 #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK    (0xF00U)
20723 #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT   (8U)
20724 /*! WHITE_LIST - Whitelist
20725  *  0b0000..This domain is NOT allowed to change clock
20726  *  0b0001..This domain is allowed to change clock
20727  */
20728 #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK)
20729 
20730 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK     (0x1000U)
20731 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT    (12U)
20732 /*! LOCK_LIST - Lock Whitelist
20733  *  0b0..Whitelist is not locked
20734  *  0b1..Whitelist is locked
20735  */
20736 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK)
20737 
20738 #define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
20739 #define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_SHIFT  (16U)
20740 /*! DOMAIN_MODE - Low power and access control by domain
20741  *  0b1..Clock works in Domain Mode
20742  *  0b0..Clock does NOT work in Domain Mode
20743  */
20744 #define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK)
20745 
20746 #define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK (0x20000U)
20747 #define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_SHIFT (17U)
20748 /*! SETPOINT_MODE - Low power and access control by Setpoint
20749  *  0b1..Clock works in Setpoint Mode
20750  *  0b0..Clock does NOT work in Setpoint Mode
20751  */
20752 #define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK)
20753 
20754 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK     (0x100000U)
20755 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_SHIFT    (20U)
20756 /*! LOCK_MODE - Lock low power and access mode
20757  *  0b0..MODE is not locked
20758  *  0b1..MODE is locked
20759  */
20760 #define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK)
20761 /*! @} */
20762 
20763 /* The count of CCM_CLOCK_ROOT_AUTHEN */
20764 #define CCM_CLOCK_ROOT_AUTHEN_COUNT              (79U)
20765 
20766 /*! @name CLOCK_ROOT_AUTHEN_SET - Clock root access control */
20767 /*! @{ */
20768 
20769 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_MASK   (0x1U)
20770 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_SHIFT  (0U)
20771 /*! TZ_USER - User access */
20772 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_MASK)
20773 
20774 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_MASK     (0x2U)
20775 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_SHIFT    (1U)
20776 /*! TZ_NS - Non-secure access */
20777 #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_MASK)
20778 
20779 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
20780 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_SHIFT  (4U)
20781 /*! LOCK_TZ - Lock truszone setting */
20782 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_MASK)
20783 
20784 #define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
20785 #define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
20786 /*! WHITE_LIST - Whitelist */
20787 #define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_MASK)
20788 
20789 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
20790 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
20791 /*! LOCK_LIST - Lock Whitelist */
20792 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_MASK)
20793 
20794 #define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
20795 #define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
20796 /*! DOMAIN_MODE - Low power and access control by domain */
20797 #define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_MASK)
20798 
20799 #define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_MASK (0x20000U)
20800 #define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_SHIFT (17U)
20801 /*! SETPOINT_MODE - Low power and access control by Setpoint */
20802 #define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_MASK)
20803 
20804 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
20805 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
20806 /*! LOCK_MODE - Lock low power and access mode */
20807 #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_MASK)
20808 /*! @} */
20809 
20810 /* The count of CCM_CLOCK_ROOT_AUTHEN_SET */
20811 #define CCM_CLOCK_ROOT_AUTHEN_SET_COUNT          (79U)
20812 
20813 /*! @name CLOCK_ROOT_AUTHEN_CLR - Clock root access control */
20814 /*! @{ */
20815 
20816 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
20817 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_SHIFT  (0U)
20818 /*! TZ_USER - User access */
20819 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_MASK)
20820 
20821 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_MASK     (0x2U)
20822 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_SHIFT    (1U)
20823 /*! TZ_NS - Non-secure access */
20824 #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_MASK)
20825 
20826 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
20827 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_SHIFT  (4U)
20828 /*! LOCK_TZ - Lock truszone setting */
20829 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_MASK)
20830 
20831 #define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
20832 #define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
20833 /*! WHITE_LIST - Whitelist */
20834 #define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_MASK)
20835 
20836 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
20837 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
20838 /*! LOCK_LIST - Lock Whitelist */
20839 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_MASK)
20840 
20841 #define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
20842 #define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
20843 /*! DOMAIN_MODE - Low power and access control by domain */
20844 #define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_MASK)
20845 
20846 #define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_MASK (0x20000U)
20847 #define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_SHIFT (17U)
20848 /*! SETPOINT_MODE - Low power and access control by Setpoint */
20849 #define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_MASK)
20850 
20851 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
20852 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
20853 /*! LOCK_MODE - Lock low power and access mode */
20854 #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_MASK)
20855 /*! @} */
20856 
20857 /* The count of CCM_CLOCK_ROOT_AUTHEN_CLR */
20858 #define CCM_CLOCK_ROOT_AUTHEN_CLR_COUNT          (79U)
20859 
20860 /*! @name CLOCK_ROOT_AUTHEN_TOG - Clock root access control */
20861 /*! @{ */
20862 
20863 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
20864 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_SHIFT  (0U)
20865 /*! TZ_USER - User access */
20866 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_MASK)
20867 
20868 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_MASK     (0x2U)
20869 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_SHIFT    (1U)
20870 /*! TZ_NS - Non-secure access */
20871 #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_MASK)
20872 
20873 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
20874 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_SHIFT  (4U)
20875 /*! LOCK_TZ - Lock truszone setting */
20876 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_MASK)
20877 
20878 #define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
20879 #define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
20880 /*! WHITE_LIST - Whitelist */
20881 #define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_MASK)
20882 
20883 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
20884 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
20885 /*! LOCK_LIST - Lock Whitelist */
20886 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_MASK)
20887 
20888 #define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
20889 #define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
20890 /*! DOMAIN_MODE - Low power and access control by domain */
20891 #define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_MASK)
20892 
20893 #define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_MASK (0x20000U)
20894 #define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_SHIFT (17U)
20895 /*! SETPOINT_MODE - Low power and access control by Setpoint */
20896 #define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_MASK)
20897 
20898 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
20899 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
20900 /*! LOCK_MODE - Lock low power and access mode */
20901 #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_MASK)
20902 /*! @} */
20903 
20904 /* The count of CCM_CLOCK_ROOT_AUTHEN_TOG */
20905 #define CCM_CLOCK_ROOT_AUTHEN_TOG_COUNT          (79U)
20906 
20907 /*! @name CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT - Setpoint setting */
20908 /*! @{ */
20909 
20910 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_MASK (0xFFU)
20911 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_SHIFT (0U)
20912 /*! DIV - Clock divider */
20913 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_MASK)
20914 
20915 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_MASK (0x700U)
20916 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_SHIFT (8U)
20917 /*! MUX - Clock multiplexer */
20918 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_MASK)
20919 
20920 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_MASK (0x1000000U)
20921 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_SHIFT (24U)
20922 /*! OFF - OFF
20923  *  0b1..OFF
20924  *  0b0..ON
20925  */
20926 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_MASK)
20927 
20928 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_MASK (0xF0000000U)
20929 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_SHIFT (28U)
20930 /*! GRADE - Grade */
20931 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_MASK)
20932 /*! @} */
20933 
20934 /* The count of CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT */
20935 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_COUNT (79U)
20936 
20937 /* The count of CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT */
20938 #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_COUNT2 (16U)
20939 
20940 /*! @name CLOCK_GROUP_CONTROL - Clock group control */
20941 /*! @{ */
20942 
20943 #define CCM_CLOCK_GROUP_CONTROL_DIV0_MASK        (0xFU)
20944 #define CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT       (0U)
20945 /*! DIV0 - Clock divider0 */
20946 #define CCM_CLOCK_GROUP_CONTROL_DIV0(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_DIV0_MASK)
20947 
20948 #define CCM_CLOCK_GROUP_CONTROL_RSTDIV_MASK      (0xFF0000U)
20949 #define CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT     (16U)
20950 /*! RSTDIV - Clock group global restart count */
20951 #define CCM_CLOCK_GROUP_CONTROL_RSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_RSTDIV_MASK)
20952 
20953 #define CCM_CLOCK_GROUP_CONTROL_OFF_MASK         (0x1000000U)
20954 #define CCM_CLOCK_GROUP_CONTROL_OFF_SHIFT        (24U)
20955 /*! OFF - OFF
20956  *  0b0..Clock is running
20957  *  0b1..Turn off clock
20958  */
20959 #define CCM_CLOCK_GROUP_CONTROL_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_OFF_MASK)
20960 /*! @} */
20961 
20962 /* The count of CCM_CLOCK_GROUP_CONTROL */
20963 #define CCM_CLOCK_GROUP_CONTROL_COUNT            (2U)
20964 
20965 /*! @name CLOCK_GROUP_CONTROL_SET - Clock group control */
20966 /*! @{ */
20967 
20968 #define CCM_CLOCK_GROUP_CONTROL_SET_DIV0_MASK    (0xFU)
20969 #define CCM_CLOCK_GROUP_CONTROL_SET_DIV0_SHIFT   (0U)
20970 /*! DIV0 - Clock divider0 */
20971 #define CCM_CLOCK_GROUP_CONTROL_SET_DIV0(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_DIV0_MASK)
20972 
20973 #define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_MASK  (0xFF0000U)
20974 #define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_SHIFT (16U)
20975 /*! RSTDIV - Clock group global restart count */
20976 #define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_MASK)
20977 
20978 #define CCM_CLOCK_GROUP_CONTROL_SET_OFF_MASK     (0x1000000U)
20979 #define CCM_CLOCK_GROUP_CONTROL_SET_OFF_SHIFT    (24U)
20980 /*! OFF - OFF */
20981 #define CCM_CLOCK_GROUP_CONTROL_SET_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_OFF_MASK)
20982 /*! @} */
20983 
20984 /* The count of CCM_CLOCK_GROUP_CONTROL_SET */
20985 #define CCM_CLOCK_GROUP_CONTROL_SET_COUNT        (2U)
20986 
20987 /*! @name CLOCK_GROUP_CONTROL_CLR - Clock group control */
20988 /*! @{ */
20989 
20990 #define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_MASK    (0xFU)
20991 #define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_SHIFT   (0U)
20992 /*! DIV0 - Clock divider0 */
20993 #define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_MASK)
20994 
20995 #define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_MASK  (0xFF0000U)
20996 #define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_SHIFT (16U)
20997 /*! RSTDIV - Clock group global restart count */
20998 #define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_MASK)
20999 
21000 #define CCM_CLOCK_GROUP_CONTROL_CLR_OFF_MASK     (0x1000000U)
21001 #define CCM_CLOCK_GROUP_CONTROL_CLR_OFF_SHIFT    (24U)
21002 /*! OFF - OFF */
21003 #define CCM_CLOCK_GROUP_CONTROL_CLR_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_OFF_MASK)
21004 /*! @} */
21005 
21006 /* The count of CCM_CLOCK_GROUP_CONTROL_CLR */
21007 #define CCM_CLOCK_GROUP_CONTROL_CLR_COUNT        (2U)
21008 
21009 /*! @name CLOCK_GROUP_CONTROL_TOG - Clock group control */
21010 /*! @{ */
21011 
21012 #define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_MASK    (0xFU)
21013 #define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_SHIFT   (0U)
21014 /*! DIV0 - Clock divider0 */
21015 #define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_MASK)
21016 
21017 #define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_MASK  (0xFF0000U)
21018 #define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_SHIFT (16U)
21019 /*! RSTDIV - Clock group global restart count */
21020 #define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_MASK)
21021 
21022 #define CCM_CLOCK_GROUP_CONTROL_TOG_OFF_MASK     (0x1000000U)
21023 #define CCM_CLOCK_GROUP_CONTROL_TOG_OFF_SHIFT    (24U)
21024 /*! OFF - OFF */
21025 #define CCM_CLOCK_GROUP_CONTROL_TOG_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_OFF_MASK)
21026 /*! @} */
21027 
21028 /* The count of CCM_CLOCK_GROUP_CONTROL_TOG */
21029 #define CCM_CLOCK_GROUP_CONTROL_TOG_COUNT        (2U)
21030 
21031 /*! @name CLOCK_GROUP_STATUS0 - Clock group working status */
21032 /*! @{ */
21033 
21034 #define CCM_CLOCK_GROUP_STATUS0_DIV0_MASK        (0xFU)
21035 #define CCM_CLOCK_GROUP_STATUS0_DIV0_SHIFT       (0U)
21036 /*! DIV0 - Clock divider */
21037 #define CCM_CLOCK_GROUP_STATUS0_DIV0(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_DIV0_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_DIV0_MASK)
21038 
21039 #define CCM_CLOCK_GROUP_STATUS0_RSTDIV_MASK      (0xFF0000U)
21040 #define CCM_CLOCK_GROUP_STATUS0_RSTDIV_SHIFT     (16U)
21041 /*! RSTDIV - Clock divider */
21042 #define CCM_CLOCK_GROUP_STATUS0_RSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_RSTDIV_MASK)
21043 
21044 #define CCM_CLOCK_GROUP_STATUS0_OFF_MASK         (0x1000000U)
21045 #define CCM_CLOCK_GROUP_STATUS0_OFF_SHIFT        (24U)
21046 /*! OFF - OFF
21047  *  0b0..Clock is running.
21048  *  0b1..Turn off clock.
21049  */
21050 #define CCM_CLOCK_GROUP_STATUS0_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_OFF_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_OFF_MASK)
21051 
21052 #define CCM_CLOCK_GROUP_STATUS0_POWERDOWN_MASK   (0x8000000U)
21053 #define CCM_CLOCK_GROUP_STATUS0_POWERDOWN_SHIFT  (27U)
21054 /*! POWERDOWN - Current clock root POWERDOWN setting
21055  *  0b1..Clock root is Powered Down
21056  *  0b0..Clock root is running
21057  */
21058 #define CCM_CLOCK_GROUP_STATUS0_POWERDOWN(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_POWERDOWN_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_POWERDOWN_MASK)
21059 
21060 #define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_MASK  (0x10000000U)
21061 #define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_SHIFT (28U)
21062 /*! SLICE_BUSY - Internal updating in generation logic
21063  *  0b1..Clock generation logic is applying the new setting
21064  *  0b0..Clock generation logic is not busy
21065  */
21066 #define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_MASK)
21067 
21068 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_MASK (0x20000000U)
21069 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_SHIFT (29U)
21070 /*! UPDATE_FORWARD - Internal status synchronization to clock generation logic
21071  *  0b1..Synchronization in process
21072  *  0b0..Synchronization not in process
21073  */
21074 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_MASK)
21075 
21076 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_MASK (0x40000000U)
21077 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_SHIFT (30U)
21078 /*! UPDATE_REVERSE - Internal status synchronization from clock generation logic
21079  *  0b1..Synchronization in process
21080  *  0b0..Synchronization not in process
21081  */
21082 #define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_MASK)
21083 
21084 #define CCM_CLOCK_GROUP_STATUS0_CHANGING_MASK    (0x80000000U)
21085 #define CCM_CLOCK_GROUP_STATUS0_CHANGING_SHIFT   (31U)
21086 /*! CHANGING - Internal updating in clock group
21087  *  0b1..Clock root logic is updating currently
21088  *  0b0..Clock root is not updating currently
21089  */
21090 #define CCM_CLOCK_GROUP_STATUS0_CHANGING(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_CHANGING_MASK)
21091 /*! @} */
21092 
21093 /* The count of CCM_CLOCK_GROUP_STATUS0 */
21094 #define CCM_CLOCK_GROUP_STATUS0_COUNT            (2U)
21095 
21096 /*! @name CLOCK_GROUP_STATUS1 - Clock group low power/extend status */
21097 /*! @{ */
21098 
21099 #define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_MASK (0xF0000U)
21100 #define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_SHIFT (16U)
21101 /*! TARGET_SETPOINT - Next Setpoint to change to */
21102 #define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_MASK)
21103 
21104 #define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
21105 #define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
21106 /*! CURRENT_SETPOINT - Current Setpoint */
21107 #define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_MASK)
21108 
21109 #define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_MASK (0x1000000U)
21110 #define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_SHIFT (24U)
21111 /*! DOWN_REQUEST - Clock frequency decrease request
21112  *  0b1..Handshake signal with GPC status indicating frequency decrease is requested
21113  *  0b0..No handshake signal is not requested
21114  */
21115 #define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_MASK)
21116 
21117 #define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_MASK   (0x2000000U)
21118 #define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_SHIFT  (25U)
21119 /*! DOWN_DONE - Clock frequency decrease complete
21120  *  0b1..Handshake signal with GPC status indicating frequency decrease is complete
21121  *  0b0..Handshake signal with GPC status indicating frequency decrease is not complete
21122  */
21123 #define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_MASK)
21124 
21125 #define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_MASK  (0x4000000U)
21126 #define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_SHIFT (26U)
21127 /*! UP_REQUEST - Clock frequency increase request
21128  *  0b1..Handshake signal with GPC status indicating frequency increase is requested
21129  *  0b0..No handshake signal is not requested
21130  */
21131 #define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_MASK)
21132 
21133 #define CCM_CLOCK_GROUP_STATUS1_UP_DONE_MASK     (0x8000000U)
21134 #define CCM_CLOCK_GROUP_STATUS1_UP_DONE_SHIFT    (27U)
21135 /*! UP_DONE - Clock frequency increase complete
21136  *  0b1..Handshake signal with GPC status indicating frequency increase is complete
21137  *  0b0..Handshake signal with GPC status indicating frequency increase is not complete
21138  */
21139 #define CCM_CLOCK_GROUP_STATUS1_UP_DONE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_UP_DONE_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_UP_DONE_MASK)
21140 /*! @} */
21141 
21142 /* The count of CCM_CLOCK_GROUP_STATUS1 */
21143 #define CCM_CLOCK_GROUP_STATUS1_COUNT            (2U)
21144 
21145 /*! @name CLOCK_GROUP_CONFIG - Clock group configuration */
21146 /*! @{ */
21147 
21148 #define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_MASK (0x10U)
21149 #define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
21150 /*! SETPOINT_PRESENT - Setpoint present
21151  *  0b1..Setpoint is implemented.
21152  *  0b0..Setpoint is not implemented.
21153  */
21154 #define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_MASK)
21155 /*! @} */
21156 
21157 /* The count of CCM_CLOCK_GROUP_CONFIG */
21158 #define CCM_CLOCK_GROUP_CONFIG_COUNT             (2U)
21159 
21160 /*! @name CLOCK_GROUP_AUTHEN - Clock group access control */
21161 /*! @{ */
21162 
21163 #define CCM_CLOCK_GROUP_AUTHEN_TZ_USER_MASK      (0x1U)
21164 #define CCM_CLOCK_GROUP_AUTHEN_TZ_USER_SHIFT     (0U)
21165 /*! TZ_USER - User access
21166  *  0b1..Clock can be changed in user mode.
21167  *  0b0..Clock cannot be changed in user mode.
21168  */
21169 #define CCM_CLOCK_GROUP_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TZ_USER_MASK)
21170 
21171 #define CCM_CLOCK_GROUP_AUTHEN_TZ_NS_MASK        (0x2U)
21172 #define CCM_CLOCK_GROUP_AUTHEN_TZ_NS_SHIFT       (1U)
21173 /*! TZ_NS - Non-secure access
21174  *  0b0..Cannot be changed in Non-secure mode.
21175  *  0b1..Can be changed in Non-secure mode.
21176  */
21177 #define CCM_CLOCK_GROUP_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TZ_NS_MASK)
21178 
21179 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_MASK      (0x10U)
21180 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_SHIFT     (4U)
21181 /*! LOCK_TZ - Lock truszone setting
21182  *  0b0..Trustzone setting is not locked.
21183  *  0b1..Trustzone setting is locked.
21184  */
21185 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_MASK)
21186 
21187 #define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_MASK   (0xF00U)
21188 #define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_SHIFT  (8U)
21189 /*! WHITE_LIST - Whitelist */
21190 #define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_MASK)
21191 
21192 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_MASK    (0x1000U)
21193 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_SHIFT   (12U)
21194 /*! LOCK_LIST - Lock Whitelist
21195  *  0b0..Whitelist is not locked.
21196  *  0b1..Whitelist is locked.
21197  */
21198 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_MASK)
21199 
21200 #define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_MASK  (0x10000U)
21201 #define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_SHIFT (16U)
21202 /*! DOMAIN_MODE - Low power and access control by domain
21203  *  0b1..Clock works in Domain Mode.
21204  *  0b0..Clock does not work in Domain Mode.
21205  */
21206 #define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_MASK)
21207 
21208 #define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_MASK (0x20000U)
21209 #define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_SHIFT (17U)
21210 /*! SETPOINT_MODE - Low power and access control by Setpoint */
21211 #define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_MASK)
21212 
21213 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_MASK    (0x100000U)
21214 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_SHIFT   (20U)
21215 /*! LOCK_MODE - Lock low power and access mode
21216  *  0b0..MODE is not locked.
21217  *  0b1..MODE is locked.
21218  */
21219 #define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_MASK)
21220 /*! @} */
21221 
21222 /* The count of CCM_CLOCK_GROUP_AUTHEN */
21223 #define CCM_CLOCK_GROUP_AUTHEN_COUNT             (2U)
21224 
21225 /*! @name CLOCK_GROUP_AUTHEN_SET - Clock group access control */
21226 /*! @{ */
21227 
21228 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_MASK  (0x1U)
21229 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_SHIFT (0U)
21230 /*! TZ_USER - User access */
21231 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_MASK)
21232 
21233 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_MASK    (0x2U)
21234 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_SHIFT   (1U)
21235 /*! TZ_NS - Non-secure access */
21236 #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_MASK)
21237 
21238 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_MASK  (0x10U)
21239 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
21240 /*! LOCK_TZ - Lock truszone setting */
21241 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_MASK)
21242 
21243 #define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
21244 #define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
21245 /*! WHITE_LIST - Whitelist */
21246 #define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_MASK)
21247 
21248 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
21249 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
21250 /*! LOCK_LIST - Lock Whitelist */
21251 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_MASK)
21252 
21253 #define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
21254 #define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
21255 /*! DOMAIN_MODE - Low power and access control by domain */
21256 #define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_MASK)
21257 
21258 #define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_MASK (0x20000U)
21259 #define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_SHIFT (17U)
21260 /*! SETPOINT_MODE - Low power and access control by Setpoint */
21261 #define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_MASK)
21262 
21263 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
21264 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
21265 /*! LOCK_MODE - Lock low power and access mode */
21266 #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_MASK)
21267 /*! @} */
21268 
21269 /* The count of CCM_CLOCK_GROUP_AUTHEN_SET */
21270 #define CCM_CLOCK_GROUP_AUTHEN_SET_COUNT         (2U)
21271 
21272 /*! @name CLOCK_GROUP_AUTHEN_CLR - Clock group access control */
21273 /*! @{ */
21274 
21275 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_MASK  (0x1U)
21276 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_SHIFT (0U)
21277 /*! TZ_USER - User access */
21278 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_MASK)
21279 
21280 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_MASK    (0x2U)
21281 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
21282 /*! TZ_NS - Non-secure access */
21283 #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_MASK)
21284 
21285 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_MASK  (0x10U)
21286 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
21287 /*! LOCK_TZ - Lock truszone setting */
21288 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_MASK)
21289 
21290 #define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
21291 #define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
21292 /*! WHITE_LIST - Whitelist */
21293 #define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_MASK)
21294 
21295 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
21296 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
21297 /*! LOCK_LIST - Lock Whitelist */
21298 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_MASK)
21299 
21300 #define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
21301 #define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
21302 /*! DOMAIN_MODE - Low power and access control by domain */
21303 #define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_MASK)
21304 
21305 #define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_MASK (0x20000U)
21306 #define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_SHIFT (17U)
21307 /*! SETPOINT_MODE - Low power and access control by Setpoint */
21308 #define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_MASK)
21309 
21310 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
21311 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
21312 /*! LOCK_MODE - Lock low power and access mode */
21313 #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_MASK)
21314 /*! @} */
21315 
21316 /* The count of CCM_CLOCK_GROUP_AUTHEN_CLR */
21317 #define CCM_CLOCK_GROUP_AUTHEN_CLR_COUNT         (2U)
21318 
21319 /*! @name CLOCK_GROUP_AUTHEN_TOG - Clock group access control */
21320 /*! @{ */
21321 
21322 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_MASK  (0x1U)
21323 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_SHIFT (0U)
21324 /*! TZ_USER - User access */
21325 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_MASK)
21326 
21327 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_MASK    (0x2U)
21328 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
21329 /*! TZ_NS - Non-secure access */
21330 #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_MASK)
21331 
21332 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_MASK  (0x10U)
21333 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
21334 /*! LOCK_TZ - Lock truszone setting */
21335 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_MASK)
21336 
21337 #define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
21338 #define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
21339 /*! WHITE_LIST - Whitelist */
21340 #define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_MASK)
21341 
21342 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
21343 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
21344 /*! LOCK_LIST - Lock Whitelist */
21345 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_MASK)
21346 
21347 #define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
21348 #define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
21349 /*! DOMAIN_MODE - Low power and access control by domain */
21350 #define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_MASK)
21351 
21352 #define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_MASK (0x20000U)
21353 #define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_SHIFT (17U)
21354 /*! SETPOINT_MODE - Low power and access control by Setpoint */
21355 #define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_MASK)
21356 
21357 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
21358 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
21359 /*! LOCK_MODE - Lock low power and access mode */
21360 #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_MASK)
21361 /*! @} */
21362 
21363 /* The count of CCM_CLOCK_GROUP_AUTHEN_TOG */
21364 #define CCM_CLOCK_GROUP_AUTHEN_TOG_COUNT         (2U)
21365 
21366 /*! @name CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT - Setpoint setting */
21367 /*! @{ */
21368 
21369 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_MASK (0xFU)
21370 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_SHIFT (0U)
21371 /*! DIV0 - Clock divider
21372  *  0b0000..Direct output.
21373  *  0b0001..Divide by 2.
21374  *  0b0010..Divide by 3.
21375  *  0b0011..Divide by 4.
21376  *  0b1111..Divide by 16.
21377  */
21378 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_MASK)
21379 
21380 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_MASK (0xFF0000U)
21381 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_SHIFT (16U)
21382 /*! RSTDIV - Clock group global restart count */
21383 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_MASK)
21384 
21385 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_MASK (0x1000000U)
21386 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_SHIFT (24U)
21387 /*! OFF - OFF
21388  *  0b0..Clock is running.
21389  *  0b1..Turn off clock.
21390  */
21391 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_MASK)
21392 
21393 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_MASK (0xF0000000U)
21394 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_SHIFT (28U)
21395 /*! GRADE - Grade */
21396 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_MASK)
21397 /*! @} */
21398 
21399 /* The count of CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT */
21400 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT (2U)
21401 
21402 /* The count of CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT */
21403 #define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT2 (16U)
21404 
21405 /*! @name GPR_SHARED - General Purpose Register */
21406 /*! @{ */
21407 
21408 #define CCM_GPR_SHARED_GPR_MASK                  (0xFFFFFFFFU)
21409 #define CCM_GPR_SHARED_GPR_SHIFT                 (0U)
21410 /*! GPR - GP register */
21411 #define CCM_GPR_SHARED_GPR(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_GPR_SHIFT)) & CCM_GPR_SHARED_GPR_MASK)
21412 /*! @} */
21413 
21414 /* The count of CCM_GPR_SHARED */
21415 #define CCM_GPR_SHARED_COUNT                     (8U)
21416 
21417 /*! @name GPR_SHARED_SET - General Purpose Register */
21418 /*! @{ */
21419 
21420 #define CCM_GPR_SHARED_SET_GPR_MASK              (0xFFFFFFFFU)
21421 #define CCM_GPR_SHARED_SET_GPR_SHIFT             (0U)
21422 /*! GPR - GP register */
21423 #define CCM_GPR_SHARED_SET_GPR(x)                (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_SET_GPR_SHIFT)) & CCM_GPR_SHARED_SET_GPR_MASK)
21424 /*! @} */
21425 
21426 /* The count of CCM_GPR_SHARED_SET */
21427 #define CCM_GPR_SHARED_SET_COUNT                 (8U)
21428 
21429 /*! @name GPR_SHARED_CLR - General Purpose Register */
21430 /*! @{ */
21431 
21432 #define CCM_GPR_SHARED_CLR_GPR_MASK              (0xFFFFFFFFU)
21433 #define CCM_GPR_SHARED_CLR_GPR_SHIFT             (0U)
21434 /*! GPR - GP register */
21435 #define CCM_GPR_SHARED_CLR_GPR(x)                (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_CLR_GPR_SHIFT)) & CCM_GPR_SHARED_CLR_GPR_MASK)
21436 /*! @} */
21437 
21438 /* The count of CCM_GPR_SHARED_CLR */
21439 #define CCM_GPR_SHARED_CLR_COUNT                 (8U)
21440 
21441 /*! @name GPR_SHARED_TOG - General Purpose Register */
21442 /*! @{ */
21443 
21444 #define CCM_GPR_SHARED_TOG_GPR_MASK              (0xFFFFFFFFU)
21445 #define CCM_GPR_SHARED_TOG_GPR_SHIFT             (0U)
21446 /*! GPR - GP register */
21447 #define CCM_GPR_SHARED_TOG_GPR(x)                (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_TOG_GPR_SHIFT)) & CCM_GPR_SHARED_TOG_GPR_MASK)
21448 /*! @} */
21449 
21450 /* The count of CCM_GPR_SHARED_TOG */
21451 #define CCM_GPR_SHARED_TOG_COUNT                 (8U)
21452 
21453 /*! @name GPR_SHARED_AUTHEN - GPR access control */
21454 /*! @{ */
21455 
21456 #define CCM_GPR_SHARED_AUTHEN_TZ_USER_MASK       (0x1U)
21457 #define CCM_GPR_SHARED_AUTHEN_TZ_USER_SHIFT      (0U)
21458 /*! TZ_USER - User access
21459  *  0b1..Clock can be changed in user mode.
21460  *  0b0..Clock cannot be changed in user mode.
21461  */
21462 #define CCM_GPR_SHARED_AUTHEN_TZ_USER(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TZ_USER_MASK)
21463 
21464 #define CCM_GPR_SHARED_AUTHEN_TZ_NS_MASK         (0x2U)
21465 #define CCM_GPR_SHARED_AUTHEN_TZ_NS_SHIFT        (1U)
21466 /*! TZ_NS - Non-secure access
21467  *  0b0..Cannot be changed in Non-secure mode.
21468  *  0b1..Can be changed in Non-secure mode.
21469  */
21470 #define CCM_GPR_SHARED_AUTHEN_TZ_NS(x)           (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TZ_NS_MASK)
21471 
21472 #define CCM_GPR_SHARED_AUTHEN_LOCK_TZ_MASK       (0x10U)
21473 #define CCM_GPR_SHARED_AUTHEN_LOCK_TZ_SHIFT      (4U)
21474 /*! LOCK_TZ - Lock truszone setting
21475  *  0b0..Trustzone setting is not locked.
21476  *  0b1..Trustzone setting is locked.
21477  */
21478 #define CCM_GPR_SHARED_AUTHEN_LOCK_TZ(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_TZ_MASK)
21479 
21480 #define CCM_GPR_SHARED_AUTHEN_WHITE_LIST_MASK    (0xF00U)
21481 #define CCM_GPR_SHARED_AUTHEN_WHITE_LIST_SHIFT   (8U)
21482 /*! WHITE_LIST - Whitelist
21483  *  0b0000..This domain is NOT allowed to change clock.
21484  *  0b0001..This domain is allowed to change clock.
21485  */
21486 #define CCM_GPR_SHARED_AUTHEN_WHITE_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_WHITE_LIST_MASK)
21487 
21488 #define CCM_GPR_SHARED_AUTHEN_LOCK_LIST_MASK     (0x1000U)
21489 #define CCM_GPR_SHARED_AUTHEN_LOCK_LIST_SHIFT    (12U)
21490 /*! LOCK_LIST - Lock Whitelist
21491  *  0b0..Whitelist is not locked.
21492  *  0b1..Whitelist is locked.
21493  */
21494 #define CCM_GPR_SHARED_AUTHEN_LOCK_LIST(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_LIST_MASK)
21495 
21496 #define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_MASK   (0x10000U)
21497 #define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_SHIFT  (16U)
21498 /*! DOMAIN_MODE - Low power and access control by domain
21499  *  0b1..Clock works in Domain Mode.
21500  *  0b0..Clock does NOT work in Domain Mode.
21501  */
21502 #define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_MASK)
21503 
21504 #define CCM_GPR_SHARED_AUTHEN_LOCK_MODE_MASK     (0x100000U)
21505 #define CCM_GPR_SHARED_AUTHEN_LOCK_MODE_SHIFT    (20U)
21506 /*! LOCK_MODE - Lock low power and access mode
21507  *  0b0..MODE is not locked.
21508  *  0b1..MODE is locked.
21509  */
21510 #define CCM_GPR_SHARED_AUTHEN_LOCK_MODE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_MODE_MASK)
21511 /*! @} */
21512 
21513 /* The count of CCM_GPR_SHARED_AUTHEN */
21514 #define CCM_GPR_SHARED_AUTHEN_COUNT              (8U)
21515 
21516 /*! @name GPR_SHARED_AUTHEN_SET - GPR access control */
21517 /*! @{ */
21518 
21519 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_MASK   (0x1U)
21520 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_SHIFT  (0U)
21521 /*! TZ_USER - User access */
21522 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_MASK)
21523 
21524 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_MASK     (0x2U)
21525 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_SHIFT    (1U)
21526 /*! TZ_NS - Non-secure access */
21527 #define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_MASK)
21528 
21529 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_MASK   (0x10U)
21530 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_SHIFT  (4U)
21531 /*! LOCK_TZ - Lock truszone setting */
21532 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_MASK)
21533 
21534 #define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
21535 #define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
21536 /*! WHITE_LIST - Whitelist */
21537 #define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_MASK)
21538 
21539 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
21540 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
21541 /*! LOCK_LIST - Lock Whitelist */
21542 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_MASK)
21543 
21544 #define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
21545 #define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
21546 /*! DOMAIN_MODE - Low power and access control by domain */
21547 #define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_MASK)
21548 
21549 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
21550 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
21551 /*! LOCK_MODE - Lock low power and access mode */
21552 #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_MASK)
21553 /*! @} */
21554 
21555 /* The count of CCM_GPR_SHARED_AUTHEN_SET */
21556 #define CCM_GPR_SHARED_AUTHEN_SET_COUNT          (8U)
21557 
21558 /*! @name GPR_SHARED_AUTHEN_CLR - GPR access control */
21559 /*! @{ */
21560 
21561 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_MASK   (0x1U)
21562 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_SHIFT  (0U)
21563 /*! TZ_USER - User access */
21564 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_MASK)
21565 
21566 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_MASK     (0x2U)
21567 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_SHIFT    (1U)
21568 /*! TZ_NS - Non-secure access */
21569 #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_MASK)
21570 
21571 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_MASK   (0x10U)
21572 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_SHIFT  (4U)
21573 /*! LOCK_TZ - Lock truszone setting */
21574 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_MASK)
21575 
21576 #define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
21577 #define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
21578 /*! WHITE_LIST - Whitelist */
21579 #define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_MASK)
21580 
21581 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
21582 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
21583 /*! LOCK_LIST - Lock Whitelist */
21584 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_MASK)
21585 
21586 #define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
21587 #define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
21588 /*! DOMAIN_MODE - Low power and access control by domain */
21589 #define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_MASK)
21590 
21591 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
21592 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
21593 /*! LOCK_MODE - Lock low power and access mode */
21594 #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_MASK)
21595 /*! @} */
21596 
21597 /* The count of CCM_GPR_SHARED_AUTHEN_CLR */
21598 #define CCM_GPR_SHARED_AUTHEN_CLR_COUNT          (8U)
21599 
21600 /*! @name GPR_SHARED_AUTHEN_TOG - GPR access control */
21601 /*! @{ */
21602 
21603 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_MASK   (0x1U)
21604 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_SHIFT  (0U)
21605 /*! TZ_USER - User access */
21606 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_MASK)
21607 
21608 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_MASK     (0x2U)
21609 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_SHIFT    (1U)
21610 /*! TZ_NS - Non-secure access */
21611 #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_MASK)
21612 
21613 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_MASK   (0x10U)
21614 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_SHIFT  (4U)
21615 /*! LOCK_TZ - Lock truszone setting */
21616 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_MASK)
21617 
21618 #define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
21619 #define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
21620 /*! WHITE_LIST - Whitelist */
21621 #define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_MASK)
21622 
21623 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
21624 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
21625 /*! LOCK_LIST - Lock Whitelist */
21626 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_MASK)
21627 
21628 #define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
21629 #define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
21630 /*! DOMAIN_MODE - Low power and access control by domain */
21631 #define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_MASK)
21632 
21633 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
21634 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
21635 /*! LOCK_MODE - Lock low power and access mode */
21636 #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_MASK)
21637 /*! @} */
21638 
21639 /* The count of CCM_GPR_SHARED_AUTHEN_TOG */
21640 #define CCM_GPR_SHARED_AUTHEN_TOG_COUNT          (8U)
21641 
21642 /*! @name GPR_PRIVATE1 - General Purpose Register */
21643 /*! @{ */
21644 
21645 #define CCM_GPR_PRIVATE1_GPR_MASK                (0xFFFFFFFFU)
21646 #define CCM_GPR_PRIVATE1_GPR_SHIFT               (0U)
21647 /*! GPR - GP register */
21648 #define CCM_GPR_PRIVATE1_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_GPR_SHIFT)) & CCM_GPR_PRIVATE1_GPR_MASK)
21649 /*! @} */
21650 
21651 /*! @name GPR_PRIVATE1_SET - General Purpose Register */
21652 /*! @{ */
21653 
21654 #define CCM_GPR_PRIVATE1_SET_GPR_MASK            (0xFFFFFFFFU)
21655 #define CCM_GPR_PRIVATE1_SET_GPR_SHIFT           (0U)
21656 /*! GPR - GP register */
21657 #define CCM_GPR_PRIVATE1_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE1_SET_GPR_MASK)
21658 /*! @} */
21659 
21660 /*! @name GPR_PRIVATE1_CLR - General Purpose Register */
21661 /*! @{ */
21662 
21663 #define CCM_GPR_PRIVATE1_CLR_GPR_MASK            (0xFFFFFFFFU)
21664 #define CCM_GPR_PRIVATE1_CLR_GPR_SHIFT           (0U)
21665 /*! GPR - GP register */
21666 #define CCM_GPR_PRIVATE1_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE1_CLR_GPR_MASK)
21667 /*! @} */
21668 
21669 /*! @name GPR_PRIVATE1_TOG - General Purpose Register */
21670 /*! @{ */
21671 
21672 #define CCM_GPR_PRIVATE1_TOG_GPR_MASK            (0xFFFFFFFFU)
21673 #define CCM_GPR_PRIVATE1_TOG_GPR_SHIFT           (0U)
21674 /*! GPR - GP register */
21675 #define CCM_GPR_PRIVATE1_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE1_TOG_GPR_MASK)
21676 /*! @} */
21677 
21678 /*! @name GPR_PRIVATE1_AUTHEN - GPR access control */
21679 /*! @{ */
21680 
21681 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_MASK     (0x1U)
21682 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_SHIFT    (0U)
21683 /*! TZ_USER - User access
21684  *  0b1..Clock can be changed in user mode.
21685  *  0b0..Clock cannot be changed in user mode.
21686  */
21687 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_MASK)
21688 
21689 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_MASK       (0x2U)
21690 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_SHIFT      (1U)
21691 /*! TZ_NS - Non-secure access
21692  *  0b0..Cannot be changed in Non-secure mode.
21693  *  0b1..Can be changed in Non-secure mode.
21694  */
21695 #define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_MASK)
21696 
21697 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_MASK     (0x10U)
21698 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_SHIFT    (4U)
21699 /*! LOCK_TZ - Lock truszone setting
21700  *  0b0..Trustzone setting is not locked.
21701  *  0b1..Trustzone setting is locked.
21702  */
21703 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_MASK)
21704 
21705 #define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_MASK  (0xF00U)
21706 #define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_SHIFT (8U)
21707 /*! WHITE_LIST - Whitelist
21708  *  0b0000..This domain is NOT allowed to change clock.
21709  *  0b0001..This domain is allowed to change clock.
21710  */
21711 #define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_MASK)
21712 
21713 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_MASK   (0x1000U)
21714 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_SHIFT  (12U)
21715 /*! LOCK_LIST - Lock Whitelist
21716  *  0b0..Whitelist is not locked.
21717  *  0b1..Whitelist is locked.
21718  */
21719 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_MASK)
21720 
21721 #define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
21722 #define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_SHIFT (16U)
21723 /*! DOMAIN_MODE - Low power and access control by Domain
21724  *  0b1..Clock works in Domain Mode.
21725  *  0b0..Clock does NOT work in Domain Mode.
21726  */
21727 #define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_MASK)
21728 
21729 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_MASK   (0x100000U)
21730 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_SHIFT  (20U)
21731 /*! LOCK_MODE - Lock low power and access mode
21732  *  0b0..MODE is not locked.
21733  *  0b1..MODE is locked.
21734  */
21735 #define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_MASK)
21736 /*! @} */
21737 
21738 /*! @name GPR_PRIVATE1_AUTHEN_SET - GPR access control */
21739 /*! @{ */
21740 
21741 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_MASK (0x1U)
21742 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_SHIFT (0U)
21743 /*! TZ_USER - User access */
21744 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_MASK)
21745 
21746 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_MASK   (0x2U)
21747 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_SHIFT  (1U)
21748 /*! TZ_NS - Non-secure access */
21749 #define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_MASK)
21750 
21751 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
21752 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
21753 /*! LOCK_TZ - Lock truszone setting */
21754 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_MASK)
21755 
21756 #define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
21757 #define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
21758 /*! WHITE_LIST - Whitelist */
21759 #define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_MASK)
21760 
21761 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
21762 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
21763 /*! LOCK_LIST - Lock Whitelist */
21764 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_MASK)
21765 
21766 #define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
21767 #define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
21768 /*! DOMAIN_MODE - Low power and access control by Domain */
21769 #define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_MASK)
21770 
21771 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
21772 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
21773 /*! LOCK_MODE - Lock low power and access mode */
21774 #define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_MASK)
21775 /*! @} */
21776 
21777 /*! @name GPR_PRIVATE1_AUTHEN_CLR - GPR access control */
21778 /*! @{ */
21779 
21780 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_MASK (0x1U)
21781 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_SHIFT (0U)
21782 /*! TZ_USER - User access */
21783 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_MASK)
21784 
21785 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
21786 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
21787 /*! TZ_NS - Non-secure access */
21788 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_MASK)
21789 
21790 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
21791 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
21792 /*! LOCK_TZ - Lock truszone setting */
21793 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_MASK)
21794 
21795 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
21796 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
21797 /*! WHITE_LIST - Whitelist */
21798 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_MASK)
21799 
21800 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
21801 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
21802 /*! LOCK_LIST - Lock Whitelist */
21803 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_MASK)
21804 
21805 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
21806 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
21807 /*! DOMAIN_MODE - Low power and access control by Domain */
21808 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_MASK)
21809 
21810 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
21811 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
21812 /*! LOCK_MODE - Lock low power and access mode */
21813 #define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_MASK)
21814 /*! @} */
21815 
21816 /*! @name GPR_PRIVATE1_AUTHEN_TOG - GPR access control */
21817 /*! @{ */
21818 
21819 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_MASK (0x1U)
21820 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_SHIFT (0U)
21821 /*! TZ_USER - User access */
21822 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_MASK)
21823 
21824 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
21825 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
21826 /*! TZ_NS - Non-secure access */
21827 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_MASK)
21828 
21829 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
21830 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
21831 /*! LOCK_TZ - Lock truszone setting */
21832 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_MASK)
21833 
21834 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
21835 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
21836 /*! WHITE_LIST - Whitelist */
21837 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_MASK)
21838 
21839 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
21840 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
21841 /*! LOCK_LIST - Lock Whitelist */
21842 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_MASK)
21843 
21844 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
21845 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
21846 /*! DOMAIN_MODE - Low power and access control by Domain */
21847 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_MASK)
21848 
21849 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
21850 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
21851 /*! LOCK_MODE - Lock low power and access mode */
21852 #define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_MASK)
21853 /*! @} */
21854 
21855 /*! @name GPR_PRIVATE2 - General Purpose Register */
21856 /*! @{ */
21857 
21858 #define CCM_GPR_PRIVATE2_GPR_MASK                (0xFFFFFFFFU)
21859 #define CCM_GPR_PRIVATE2_GPR_SHIFT               (0U)
21860 /*! GPR - GP register */
21861 #define CCM_GPR_PRIVATE2_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_GPR_SHIFT)) & CCM_GPR_PRIVATE2_GPR_MASK)
21862 /*! @} */
21863 
21864 /*! @name GPR_PRIVATE2_SET - General Purpose Register */
21865 /*! @{ */
21866 
21867 #define CCM_GPR_PRIVATE2_SET_GPR_MASK            (0xFFFFFFFFU)
21868 #define CCM_GPR_PRIVATE2_SET_GPR_SHIFT           (0U)
21869 /*! GPR - GP register */
21870 #define CCM_GPR_PRIVATE2_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE2_SET_GPR_MASK)
21871 /*! @} */
21872 
21873 /*! @name GPR_PRIVATE2_CLR - General Purpose Register */
21874 /*! @{ */
21875 
21876 #define CCM_GPR_PRIVATE2_CLR_GPR_MASK            (0xFFFFFFFFU)
21877 #define CCM_GPR_PRIVATE2_CLR_GPR_SHIFT           (0U)
21878 /*! GPR - GP register */
21879 #define CCM_GPR_PRIVATE2_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE2_CLR_GPR_MASK)
21880 /*! @} */
21881 
21882 /*! @name GPR_PRIVATE2_TOG - General Purpose Register */
21883 /*! @{ */
21884 
21885 #define CCM_GPR_PRIVATE2_TOG_GPR_MASK            (0xFFFFFFFFU)
21886 #define CCM_GPR_PRIVATE2_TOG_GPR_SHIFT           (0U)
21887 /*! GPR - GP register */
21888 #define CCM_GPR_PRIVATE2_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE2_TOG_GPR_MASK)
21889 /*! @} */
21890 
21891 /*! @name GPR_PRIVATE2_AUTHEN - GPR access control */
21892 /*! @{ */
21893 
21894 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_MASK     (0x1U)
21895 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_SHIFT    (0U)
21896 /*! TZ_USER - User access
21897  *  0b1..Clock can be changed in user mode.
21898  *  0b0..Clock cannot be changed in user mode.
21899  */
21900 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_MASK)
21901 
21902 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_MASK       (0x2U)
21903 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_SHIFT      (1U)
21904 /*! TZ_NS - Non-secure access
21905  *  0b0..Cannot be changed in Non-secure mode.
21906  *  0b1..Can be changed in Non-secure mode.
21907  */
21908 #define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_MASK)
21909 
21910 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_MASK     (0x10U)
21911 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_SHIFT    (4U)
21912 /*! LOCK_TZ - Lock truszone setting
21913  *  0b0..Trustzone setting is not locked.
21914  *  0b1..Trustzone setting is locked.
21915  */
21916 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_MASK)
21917 
21918 #define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_MASK  (0xF00U)
21919 #define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_SHIFT (8U)
21920 /*! WHITE_LIST - Whitelist
21921  *  0b0000..This domain is NOT allowed to change clock.
21922  *  0b0001..This domain is allowed to change clock.
21923  */
21924 #define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_MASK)
21925 
21926 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_MASK   (0x1000U)
21927 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_SHIFT  (12U)
21928 /*! LOCK_LIST - Lock Whitelist
21929  *  0b0..Whitelist is not locked.
21930  *  0b1..Whitelist is locked.
21931  */
21932 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_MASK)
21933 
21934 #define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
21935 #define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_SHIFT (16U)
21936 /*! DOMAIN_MODE - Low power and access control by Domain
21937  *  0b1..Clock works in Domain Mode.
21938  *  0b0..Clock does NOT work in Domain Mode.
21939  */
21940 #define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_MASK)
21941 
21942 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_MASK   (0x100000U)
21943 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_SHIFT  (20U)
21944 /*! LOCK_MODE - Lock low power and access mode
21945  *  0b0..MODE is not locked.
21946  *  0b1..MODE is locked.
21947  */
21948 #define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_MASK)
21949 /*! @} */
21950 
21951 /*! @name GPR_PRIVATE2_AUTHEN_SET - GPR access control */
21952 /*! @{ */
21953 
21954 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_MASK (0x1U)
21955 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_SHIFT (0U)
21956 /*! TZ_USER - User access */
21957 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_MASK)
21958 
21959 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_MASK   (0x2U)
21960 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_SHIFT  (1U)
21961 /*! TZ_NS - Non-secure access */
21962 #define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_MASK)
21963 
21964 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
21965 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
21966 /*! LOCK_TZ - Lock truszone setting */
21967 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_MASK)
21968 
21969 #define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
21970 #define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
21971 /*! WHITE_LIST - Whitelist */
21972 #define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_MASK)
21973 
21974 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
21975 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
21976 /*! LOCK_LIST - Lock Whitelist */
21977 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_MASK)
21978 
21979 #define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
21980 #define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
21981 /*! DOMAIN_MODE - Low power and access control by Domain */
21982 #define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_MASK)
21983 
21984 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
21985 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
21986 /*! LOCK_MODE - Lock low power and access mode */
21987 #define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_MASK)
21988 /*! @} */
21989 
21990 /*! @name GPR_PRIVATE2_AUTHEN_CLR - GPR access control */
21991 /*! @{ */
21992 
21993 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_MASK (0x1U)
21994 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_SHIFT (0U)
21995 /*! TZ_USER - User access */
21996 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_MASK)
21997 
21998 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
21999 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
22000 /*! TZ_NS - Non-secure access */
22001 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_MASK)
22002 
22003 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22004 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22005 /*! LOCK_TZ - Lock truszone setting */
22006 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_MASK)
22007 
22008 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22009 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22010 /*! WHITE_LIST - Whitelist */
22011 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_MASK)
22012 
22013 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22014 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22015 /*! LOCK_LIST - Lock Whitelist */
22016 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_MASK)
22017 
22018 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22019 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22020 /*! DOMAIN_MODE - Low power and access control by Domain */
22021 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_MASK)
22022 
22023 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22024 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22025 /*! LOCK_MODE - Lock low power and access mode */
22026 #define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_MASK)
22027 /*! @} */
22028 
22029 /*! @name GPR_PRIVATE2_AUTHEN_TOG - GPR access control */
22030 /*! @{ */
22031 
22032 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22033 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22034 /*! TZ_USER - User access */
22035 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_MASK)
22036 
22037 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
22038 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
22039 /*! TZ_NS - Non-secure access */
22040 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_MASK)
22041 
22042 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22043 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22044 /*! LOCK_TZ - Lock truszone setting */
22045 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_MASK)
22046 
22047 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22048 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22049 /*! WHITE_LIST - Whitelist */
22050 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_MASK)
22051 
22052 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22053 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22054 /*! LOCK_LIST - Lock Whitelist */
22055 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_MASK)
22056 
22057 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22058 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22059 /*! DOMAIN_MODE - Low power and access control by Domain */
22060 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_MASK)
22061 
22062 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22063 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22064 /*! LOCK_MODE - Lock low power and access mode */
22065 #define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_MASK)
22066 /*! @} */
22067 
22068 /*! @name GPR_PRIVATE3 - General Purpose Register */
22069 /*! @{ */
22070 
22071 #define CCM_GPR_PRIVATE3_GPR_MASK                (0xFFFFFFFFU)
22072 #define CCM_GPR_PRIVATE3_GPR_SHIFT               (0U)
22073 /*! GPR - GP register */
22074 #define CCM_GPR_PRIVATE3_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_GPR_SHIFT)) & CCM_GPR_PRIVATE3_GPR_MASK)
22075 /*! @} */
22076 
22077 /*! @name GPR_PRIVATE3_SET - General Purpose Register */
22078 /*! @{ */
22079 
22080 #define CCM_GPR_PRIVATE3_SET_GPR_MASK            (0xFFFFFFFFU)
22081 #define CCM_GPR_PRIVATE3_SET_GPR_SHIFT           (0U)
22082 /*! GPR - GP register */
22083 #define CCM_GPR_PRIVATE3_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE3_SET_GPR_MASK)
22084 /*! @} */
22085 
22086 /*! @name GPR_PRIVATE3_CLR - General Purpose Register */
22087 /*! @{ */
22088 
22089 #define CCM_GPR_PRIVATE3_CLR_GPR_MASK            (0xFFFFFFFFU)
22090 #define CCM_GPR_PRIVATE3_CLR_GPR_SHIFT           (0U)
22091 /*! GPR - GP register */
22092 #define CCM_GPR_PRIVATE3_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE3_CLR_GPR_MASK)
22093 /*! @} */
22094 
22095 /*! @name GPR_PRIVATE3_TOG - General Purpose Register */
22096 /*! @{ */
22097 
22098 #define CCM_GPR_PRIVATE3_TOG_GPR_MASK            (0xFFFFFFFFU)
22099 #define CCM_GPR_PRIVATE3_TOG_GPR_SHIFT           (0U)
22100 /*! GPR - GP register */
22101 #define CCM_GPR_PRIVATE3_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE3_TOG_GPR_MASK)
22102 /*! @} */
22103 
22104 /*! @name GPR_PRIVATE3_AUTHEN - GPR access control */
22105 /*! @{ */
22106 
22107 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_MASK     (0x1U)
22108 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_SHIFT    (0U)
22109 /*! TZ_USER - User access
22110  *  0b1..Clock can be changed in user mode.
22111  *  0b0..Clock cannot be changed in user mode.
22112  */
22113 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_MASK)
22114 
22115 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_MASK       (0x2U)
22116 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_SHIFT      (1U)
22117 /*! TZ_NS - Non-secure access
22118  *  0b0..Cannot be changed in Non-secure mode.
22119  *  0b1..Can be changed in Non-secure mode.
22120  */
22121 #define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_MASK)
22122 
22123 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_MASK     (0x10U)
22124 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_SHIFT    (4U)
22125 /*! LOCK_TZ - Lock truszone setting
22126  *  0b0..Trustzone setting is not locked.
22127  *  0b1..Trustzone setting is locked.
22128  */
22129 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_MASK)
22130 
22131 #define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_MASK  (0xF00U)
22132 #define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_SHIFT (8U)
22133 /*! WHITE_LIST - Whitelist
22134  *  0b0000..This domain is NOT allowed to change clock.
22135  *  0b0001..This domain is allowed to change clock.
22136  */
22137 #define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_MASK)
22138 
22139 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_MASK   (0x1000U)
22140 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_SHIFT  (12U)
22141 /*! LOCK_LIST - Lock Whitelist
22142  *  0b0..Whitelist is not locked.
22143  *  0b1..Whitelist is locked.
22144  */
22145 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_MASK)
22146 
22147 #define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22148 #define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22149 /*! DOMAIN_MODE - Low power and access control by Domain
22150  *  0b1..Clock works in Domain Mode.
22151  *  0b0..Clock does NOT work in Domain Mode.
22152  */
22153 #define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_MASK)
22154 
22155 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_MASK   (0x100000U)
22156 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_SHIFT  (20U)
22157 /*! LOCK_MODE - Lock low power and access mode
22158  *  0b0..MODE is not locked.
22159  *  0b1..MODE is locked.
22160  */
22161 #define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_MASK)
22162 /*! @} */
22163 
22164 /*! @name GPR_PRIVATE3_AUTHEN_SET - GPR access control */
22165 /*! @{ */
22166 
22167 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_MASK (0x1U)
22168 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_SHIFT (0U)
22169 /*! TZ_USER - User access */
22170 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_MASK)
22171 
22172 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_MASK   (0x2U)
22173 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_SHIFT  (1U)
22174 /*! TZ_NS - Non-secure access */
22175 #define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_MASK)
22176 
22177 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
22178 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
22179 /*! LOCK_TZ - Lock truszone setting */
22180 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_MASK)
22181 
22182 #define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22183 #define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22184 /*! WHITE_LIST - Whitelist */
22185 #define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_MASK)
22186 
22187 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22188 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22189 /*! LOCK_LIST - Lock Whitelist */
22190 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_MASK)
22191 
22192 #define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22193 #define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22194 /*! DOMAIN_MODE - Low power and access control by Domain */
22195 #define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_MASK)
22196 
22197 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22198 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22199 /*! LOCK_MODE - Lock low power and access mode */
22200 #define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_MASK)
22201 /*! @} */
22202 
22203 /*! @name GPR_PRIVATE3_AUTHEN_CLR - GPR access control */
22204 /*! @{ */
22205 
22206 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22207 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22208 /*! TZ_USER - User access */
22209 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_MASK)
22210 
22211 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
22212 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
22213 /*! TZ_NS - Non-secure access */
22214 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_MASK)
22215 
22216 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22217 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22218 /*! LOCK_TZ - Lock truszone setting */
22219 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_MASK)
22220 
22221 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22222 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22223 /*! WHITE_LIST - Whitelist */
22224 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_MASK)
22225 
22226 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22227 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22228 /*! LOCK_LIST - Lock Whitelist */
22229 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_MASK)
22230 
22231 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22232 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22233 /*! DOMAIN_MODE - Low power and access control by Domain */
22234 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_MASK)
22235 
22236 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22237 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22238 /*! LOCK_MODE - Lock low power and access mode */
22239 #define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_MASK)
22240 /*! @} */
22241 
22242 /*! @name GPR_PRIVATE3_AUTHEN_TOG - GPR access control */
22243 /*! @{ */
22244 
22245 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22246 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22247 /*! TZ_USER - User access */
22248 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_MASK)
22249 
22250 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
22251 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
22252 /*! TZ_NS - Non-secure access */
22253 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_MASK)
22254 
22255 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22256 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22257 /*! LOCK_TZ - Lock truszone setting */
22258 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_MASK)
22259 
22260 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22261 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22262 /*! WHITE_LIST - Whitelist */
22263 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_MASK)
22264 
22265 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22266 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22267 /*! LOCK_LIST - Lock Whitelist */
22268 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_MASK)
22269 
22270 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22271 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22272 /*! DOMAIN_MODE - Low power and access control by Domain */
22273 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_MASK)
22274 
22275 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22276 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22277 /*! LOCK_MODE - Lock low power and access mode */
22278 #define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_MASK)
22279 /*! @} */
22280 
22281 /*! @name GPR_PRIVATE4 - General Purpose Register */
22282 /*! @{ */
22283 
22284 #define CCM_GPR_PRIVATE4_GPR_MASK                (0xFFFFFFFFU)
22285 #define CCM_GPR_PRIVATE4_GPR_SHIFT               (0U)
22286 /*! GPR - GP register */
22287 #define CCM_GPR_PRIVATE4_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_GPR_SHIFT)) & CCM_GPR_PRIVATE4_GPR_MASK)
22288 /*! @} */
22289 
22290 /*! @name GPR_PRIVATE4_SET - General Purpose Register */
22291 /*! @{ */
22292 
22293 #define CCM_GPR_PRIVATE4_SET_GPR_MASK            (0xFFFFFFFFU)
22294 #define CCM_GPR_PRIVATE4_SET_GPR_SHIFT           (0U)
22295 /*! GPR - GP register */
22296 #define CCM_GPR_PRIVATE4_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE4_SET_GPR_MASK)
22297 /*! @} */
22298 
22299 /*! @name GPR_PRIVATE4_CLR - General Purpose Register */
22300 /*! @{ */
22301 
22302 #define CCM_GPR_PRIVATE4_CLR_GPR_MASK            (0xFFFFFFFFU)
22303 #define CCM_GPR_PRIVATE4_CLR_GPR_SHIFT           (0U)
22304 /*! GPR - GP register */
22305 #define CCM_GPR_PRIVATE4_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE4_CLR_GPR_MASK)
22306 /*! @} */
22307 
22308 /*! @name GPR_PRIVATE4_TOG - General Purpose Register */
22309 /*! @{ */
22310 
22311 #define CCM_GPR_PRIVATE4_TOG_GPR_MASK            (0xFFFFFFFFU)
22312 #define CCM_GPR_PRIVATE4_TOG_GPR_SHIFT           (0U)
22313 /*! GPR - GP register */
22314 #define CCM_GPR_PRIVATE4_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE4_TOG_GPR_MASK)
22315 /*! @} */
22316 
22317 /*! @name GPR_PRIVATE4_AUTHEN - GPR access control */
22318 /*! @{ */
22319 
22320 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_MASK     (0x1U)
22321 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_SHIFT    (0U)
22322 /*! TZ_USER - User access
22323  *  0b1..Clock can be changed in user mode.
22324  *  0b0..Clock cannot be changed in user mode.
22325  */
22326 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_MASK)
22327 
22328 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_MASK       (0x2U)
22329 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_SHIFT      (1U)
22330 /*! TZ_NS - Non-secure access
22331  *  0b0..Cannot be changed in Non-secure mode.
22332  *  0b1..Can be changed in Non-secure mode.
22333  */
22334 #define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_MASK)
22335 
22336 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_MASK     (0x10U)
22337 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_SHIFT    (4U)
22338 /*! LOCK_TZ - Lock truszone setting
22339  *  0b0..Trustzone setting is not locked.
22340  *  0b1..Trustzone setting is locked.
22341  */
22342 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_MASK)
22343 
22344 #define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_MASK  (0xF00U)
22345 #define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_SHIFT (8U)
22346 /*! WHITE_LIST - Whitelist
22347  *  0b0000..This domain is NOT allowed to change clock.
22348  *  0b0001..This domain is allowed to change clock.
22349  */
22350 #define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_MASK)
22351 
22352 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_MASK   (0x1000U)
22353 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_SHIFT  (12U)
22354 /*! LOCK_LIST - Lock Whitelist
22355  *  0b0..Whitelist is not locked.
22356  *  0b1..Whitelist is locked.
22357  */
22358 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_MASK)
22359 
22360 #define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22361 #define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22362 /*! DOMAIN_MODE - Low power and access control by Domain
22363  *  0b1..Clock works in Domain Mode.
22364  *  0b0..Clock does NOT work in Domain Mode.
22365  */
22366 #define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_MASK)
22367 
22368 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_MASK   (0x100000U)
22369 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_SHIFT  (20U)
22370 /*! LOCK_MODE - Lock low power and access mode
22371  *  0b0..MODE is not locked.
22372  *  0b1..MODE is locked.
22373  */
22374 #define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_MASK)
22375 /*! @} */
22376 
22377 /*! @name GPR_PRIVATE4_AUTHEN_SET - GPR access control */
22378 /*! @{ */
22379 
22380 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_MASK (0x1U)
22381 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_SHIFT (0U)
22382 /*! TZ_USER - User access */
22383 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_MASK)
22384 
22385 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_MASK   (0x2U)
22386 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_SHIFT  (1U)
22387 /*! TZ_NS - Non-secure access */
22388 #define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_MASK)
22389 
22390 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
22391 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
22392 /*! LOCK_TZ - Lock truszone setting */
22393 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_MASK)
22394 
22395 #define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22396 #define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22397 /*! WHITE_LIST - Whitelist */
22398 #define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_MASK)
22399 
22400 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22401 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22402 /*! LOCK_LIST - Lock Whitelist */
22403 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_MASK)
22404 
22405 #define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22406 #define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22407 /*! DOMAIN_MODE - Low power and access control by Domain */
22408 #define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_MASK)
22409 
22410 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22411 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22412 /*! LOCK_MODE - Lock low power and access mode */
22413 #define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_MASK)
22414 /*! @} */
22415 
22416 /*! @name GPR_PRIVATE4_AUTHEN_CLR - GPR access control */
22417 /*! @{ */
22418 
22419 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22420 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22421 /*! TZ_USER - User access */
22422 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_MASK)
22423 
22424 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
22425 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
22426 /*! TZ_NS - Non-secure access */
22427 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_MASK)
22428 
22429 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22430 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22431 /*! LOCK_TZ - Lock truszone setting */
22432 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_MASK)
22433 
22434 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22435 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22436 /*! WHITE_LIST - Whitelist */
22437 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_MASK)
22438 
22439 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22440 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22441 /*! LOCK_LIST - Lock Whitelist */
22442 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_MASK)
22443 
22444 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22445 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22446 /*! DOMAIN_MODE - Low power and access control by Domain */
22447 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_MASK)
22448 
22449 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22450 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22451 /*! LOCK_MODE - Lock low power and access mode */
22452 #define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_MASK)
22453 /*! @} */
22454 
22455 /*! @name GPR_PRIVATE4_AUTHEN_TOG - GPR access control */
22456 /*! @{ */
22457 
22458 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22459 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22460 /*! TZ_USER - User access */
22461 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_MASK)
22462 
22463 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
22464 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
22465 /*! TZ_NS - Non-secure access */
22466 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_MASK)
22467 
22468 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22469 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22470 /*! LOCK_TZ - Lock truszone setting */
22471 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_MASK)
22472 
22473 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22474 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22475 /*! WHITE_LIST - Whitelist */
22476 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_MASK)
22477 
22478 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22479 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22480 /*! LOCK_LIST - Lock Whitelist */
22481 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_MASK)
22482 
22483 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22484 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22485 /*! DOMAIN_MODE - Low power and access control by Domain */
22486 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_MASK)
22487 
22488 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22489 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22490 /*! LOCK_MODE - Lock low power and access mode */
22491 #define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_MASK)
22492 /*! @} */
22493 
22494 /*! @name GPR_PRIVATE5 - General Purpose Register */
22495 /*! @{ */
22496 
22497 #define CCM_GPR_PRIVATE5_GPR_MASK                (0xFFFFFFFFU)
22498 #define CCM_GPR_PRIVATE5_GPR_SHIFT               (0U)
22499 /*! GPR - GP register */
22500 #define CCM_GPR_PRIVATE5_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_GPR_SHIFT)) & CCM_GPR_PRIVATE5_GPR_MASK)
22501 /*! @} */
22502 
22503 /*! @name GPR_PRIVATE5_SET - General Purpose Register */
22504 /*! @{ */
22505 
22506 #define CCM_GPR_PRIVATE5_SET_GPR_MASK            (0xFFFFFFFFU)
22507 #define CCM_GPR_PRIVATE5_SET_GPR_SHIFT           (0U)
22508 /*! GPR - GP register */
22509 #define CCM_GPR_PRIVATE5_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE5_SET_GPR_MASK)
22510 /*! @} */
22511 
22512 /*! @name GPR_PRIVATE5_CLR - General Purpose Register */
22513 /*! @{ */
22514 
22515 #define CCM_GPR_PRIVATE5_CLR_GPR_MASK            (0xFFFFFFFFU)
22516 #define CCM_GPR_PRIVATE5_CLR_GPR_SHIFT           (0U)
22517 /*! GPR - GP register */
22518 #define CCM_GPR_PRIVATE5_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE5_CLR_GPR_MASK)
22519 /*! @} */
22520 
22521 /*! @name GPR_PRIVATE5_TOG - General Purpose Register */
22522 /*! @{ */
22523 
22524 #define CCM_GPR_PRIVATE5_TOG_GPR_MASK            (0xFFFFFFFFU)
22525 #define CCM_GPR_PRIVATE5_TOG_GPR_SHIFT           (0U)
22526 /*! GPR - GP register */
22527 #define CCM_GPR_PRIVATE5_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE5_TOG_GPR_MASK)
22528 /*! @} */
22529 
22530 /*! @name GPR_PRIVATE5_AUTHEN - GPR access control */
22531 /*! @{ */
22532 
22533 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_MASK     (0x1U)
22534 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_SHIFT    (0U)
22535 /*! TZ_USER - User access
22536  *  0b1..Clock can be changed in user mode.
22537  *  0b0..Clock cannot be changed in user mode.
22538  */
22539 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_MASK)
22540 
22541 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_MASK       (0x2U)
22542 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_SHIFT      (1U)
22543 /*! TZ_NS - Non-secure access
22544  *  0b0..Cannot be changed in Non-secure mode.
22545  *  0b1..Can be changed in Non-secure mode.
22546  */
22547 #define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_MASK)
22548 
22549 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_MASK     (0x10U)
22550 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_SHIFT    (4U)
22551 /*! LOCK_TZ - Lock truszone setting
22552  *  0b0..Trustzone setting is not locked.
22553  *  0b1..Trustzone setting is locked.
22554  */
22555 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_MASK)
22556 
22557 #define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_MASK  (0xF00U)
22558 #define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_SHIFT (8U)
22559 /*! WHITE_LIST - Whitelist
22560  *  0b0000..This domain is NOT allowed to change clock.
22561  *  0b0001..This domain is allowed to change clock.
22562  */
22563 #define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_MASK)
22564 
22565 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_MASK   (0x1000U)
22566 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_SHIFT  (12U)
22567 /*! LOCK_LIST - Lock Whitelist
22568  *  0b0..Whitelist is not locked.
22569  *  0b1..Whitelist is locked.
22570  */
22571 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_MASK)
22572 
22573 #define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22574 #define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22575 /*! DOMAIN_MODE - Low power and access control by Domain
22576  *  0b1..Clock works in Domain Mode.
22577  *  0b0..Clock does NOT work in Domain Mode.
22578  */
22579 #define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_MASK)
22580 
22581 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_MASK   (0x100000U)
22582 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_SHIFT  (20U)
22583 /*! LOCK_MODE - Lock low power and access mode
22584  *  0b0..MODE is not locked.
22585  *  0b1..MODE is locked.
22586  */
22587 #define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_MASK)
22588 /*! @} */
22589 
22590 /*! @name GPR_PRIVATE5_AUTHEN_SET - GPR access control */
22591 /*! @{ */
22592 
22593 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_MASK (0x1U)
22594 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_SHIFT (0U)
22595 /*! TZ_USER - User access */
22596 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_MASK)
22597 
22598 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_MASK   (0x2U)
22599 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_SHIFT  (1U)
22600 /*! TZ_NS - Non-secure access */
22601 #define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_MASK)
22602 
22603 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
22604 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
22605 /*! LOCK_TZ - Lock truszone setting */
22606 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_MASK)
22607 
22608 #define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22609 #define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22610 /*! WHITE_LIST - Whitelist */
22611 #define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_MASK)
22612 
22613 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22614 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22615 /*! LOCK_LIST - Lock Whitelist */
22616 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_MASK)
22617 
22618 #define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22619 #define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22620 /*! DOMAIN_MODE - Low power and access control by Domain */
22621 #define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_MASK)
22622 
22623 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22624 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22625 /*! LOCK_MODE - Lock low power and access mode */
22626 #define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_MASK)
22627 /*! @} */
22628 
22629 /*! @name GPR_PRIVATE5_AUTHEN_CLR - GPR access control */
22630 /*! @{ */
22631 
22632 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22633 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22634 /*! TZ_USER - User access */
22635 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_MASK)
22636 
22637 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
22638 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
22639 /*! TZ_NS - Non-secure access */
22640 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_MASK)
22641 
22642 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22643 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22644 /*! LOCK_TZ - Lock truszone setting */
22645 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_MASK)
22646 
22647 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22648 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22649 /*! WHITE_LIST - Whitelist */
22650 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_MASK)
22651 
22652 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22653 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22654 /*! LOCK_LIST - Lock Whitelist */
22655 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_MASK)
22656 
22657 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22658 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22659 /*! DOMAIN_MODE - Low power and access control by Domain */
22660 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_MASK)
22661 
22662 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22663 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22664 /*! LOCK_MODE - Lock low power and access mode */
22665 #define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_MASK)
22666 /*! @} */
22667 
22668 /*! @name GPR_PRIVATE5_AUTHEN_TOG - GPR access control */
22669 /*! @{ */
22670 
22671 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22672 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22673 /*! TZ_USER - User access */
22674 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_MASK)
22675 
22676 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
22677 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
22678 /*! TZ_NS - Non-secure access */
22679 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_MASK)
22680 
22681 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22682 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22683 /*! LOCK_TZ - Lock truszone setting */
22684 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_MASK)
22685 
22686 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22687 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22688 /*! WHITE_LIST - Whitelist */
22689 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_MASK)
22690 
22691 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22692 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22693 /*! LOCK_LIST - Lock Whitelist */
22694 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_MASK)
22695 
22696 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22697 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22698 /*! DOMAIN_MODE - Low power and access control by Domain */
22699 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_MASK)
22700 
22701 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22702 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22703 /*! LOCK_MODE - Lock low power and access mode */
22704 #define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_MASK)
22705 /*! @} */
22706 
22707 /*! @name GPR_PRIVATE6 - General Purpose Register */
22708 /*! @{ */
22709 
22710 #define CCM_GPR_PRIVATE6_GPR_MASK                (0xFFFFFFFFU)
22711 #define CCM_GPR_PRIVATE6_GPR_SHIFT               (0U)
22712 /*! GPR - GP register */
22713 #define CCM_GPR_PRIVATE6_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_GPR_SHIFT)) & CCM_GPR_PRIVATE6_GPR_MASK)
22714 /*! @} */
22715 
22716 /*! @name GPR_PRIVATE6_SET - General Purpose Register */
22717 /*! @{ */
22718 
22719 #define CCM_GPR_PRIVATE6_SET_GPR_MASK            (0xFFFFFFFFU)
22720 #define CCM_GPR_PRIVATE6_SET_GPR_SHIFT           (0U)
22721 /*! GPR - GP register */
22722 #define CCM_GPR_PRIVATE6_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE6_SET_GPR_MASK)
22723 /*! @} */
22724 
22725 /*! @name GPR_PRIVATE6_CLR - General Purpose Register */
22726 /*! @{ */
22727 
22728 #define CCM_GPR_PRIVATE6_CLR_GPR_MASK            (0xFFFFFFFFU)
22729 #define CCM_GPR_PRIVATE6_CLR_GPR_SHIFT           (0U)
22730 /*! GPR - GP register */
22731 #define CCM_GPR_PRIVATE6_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE6_CLR_GPR_MASK)
22732 /*! @} */
22733 
22734 /*! @name GPR_PRIVATE6_TOG - General Purpose Register */
22735 /*! @{ */
22736 
22737 #define CCM_GPR_PRIVATE6_TOG_GPR_MASK            (0xFFFFFFFFU)
22738 #define CCM_GPR_PRIVATE6_TOG_GPR_SHIFT           (0U)
22739 /*! GPR - GP register */
22740 #define CCM_GPR_PRIVATE6_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE6_TOG_GPR_MASK)
22741 /*! @} */
22742 
22743 /*! @name GPR_PRIVATE6_AUTHEN - GPR access control */
22744 /*! @{ */
22745 
22746 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_MASK     (0x1U)
22747 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_SHIFT    (0U)
22748 /*! TZ_USER - User access
22749  *  0b1..Clock can be changed in user mode.
22750  *  0b0..Clock cannot be changed in user mode.
22751  */
22752 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_MASK)
22753 
22754 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_MASK       (0x2U)
22755 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_SHIFT      (1U)
22756 /*! TZ_NS - Non-secure access
22757  *  0b0..Cannot be changed in Non-secure mode.
22758  *  0b1..Can be changed in Non-secure mode.
22759  */
22760 #define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_MASK)
22761 
22762 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_MASK     (0x10U)
22763 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_SHIFT    (4U)
22764 /*! LOCK_TZ - Lock truszone setting
22765  *  0b0..Trustzone setting is not locked.
22766  *  0b1..Trustzone setting is locked.
22767  */
22768 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_MASK)
22769 
22770 #define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_MASK  (0xF00U)
22771 #define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_SHIFT (8U)
22772 /*! WHITE_LIST - Whitelist
22773  *  0b0000..This domain is NOT allowed to change clock.
22774  *  0b0001..This domain is allowed to change clock.
22775  */
22776 #define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_MASK)
22777 
22778 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_MASK   (0x1000U)
22779 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_SHIFT  (12U)
22780 /*! LOCK_LIST - Lock Whitelist
22781  *  0b0..Whitelist is not locked.
22782  *  0b1..Whitelist is locked.
22783  */
22784 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_MASK)
22785 
22786 #define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
22787 #define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_SHIFT (16U)
22788 /*! DOMAIN_MODE - Low power and access control by Domain
22789  *  0b1..Clock works in Domain Mode.
22790  *  0b0..Clock does NOT work in Domain Mode.
22791  */
22792 #define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_MASK)
22793 
22794 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_MASK   (0x100000U)
22795 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_SHIFT  (20U)
22796 /*! LOCK_MODE - Lock low power and access mode
22797  *  0b0..MODE is not locked.
22798  *  0b1..MODE is locked.
22799  */
22800 #define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_MASK)
22801 /*! @} */
22802 
22803 /*! @name GPR_PRIVATE6_AUTHEN_SET - GPR access control */
22804 /*! @{ */
22805 
22806 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_MASK (0x1U)
22807 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_SHIFT (0U)
22808 /*! TZ_USER - User access */
22809 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_MASK)
22810 
22811 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_MASK   (0x2U)
22812 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_SHIFT  (1U)
22813 /*! TZ_NS - Non-secure access */
22814 #define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_MASK)
22815 
22816 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
22817 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
22818 /*! LOCK_TZ - Lock truszone setting */
22819 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_MASK)
22820 
22821 #define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
22822 #define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
22823 /*! WHITE_LIST - Whitelist */
22824 #define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_MASK)
22825 
22826 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
22827 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
22828 /*! LOCK_LIST - Lock Whitelist */
22829 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_MASK)
22830 
22831 #define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
22832 #define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
22833 /*! DOMAIN_MODE - Low power and access control by Domain */
22834 #define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_MASK)
22835 
22836 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
22837 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
22838 /*! LOCK_MODE - Lock low power and access mode */
22839 #define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_MASK)
22840 /*! @} */
22841 
22842 /*! @name GPR_PRIVATE6_AUTHEN_CLR - GPR access control */
22843 /*! @{ */
22844 
22845 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_MASK (0x1U)
22846 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_SHIFT (0U)
22847 /*! TZ_USER - User access */
22848 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_MASK)
22849 
22850 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
22851 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
22852 /*! TZ_NS - Non-secure access */
22853 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_MASK)
22854 
22855 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
22856 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
22857 /*! LOCK_TZ - Lock truszone setting */
22858 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_MASK)
22859 
22860 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
22861 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
22862 /*! WHITE_LIST - Whitelist */
22863 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_MASK)
22864 
22865 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
22866 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
22867 /*! LOCK_LIST - Lock Whitelist */
22868 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_MASK)
22869 
22870 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
22871 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
22872 /*! DOMAIN_MODE - Low power and access control by Domain */
22873 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_MASK)
22874 
22875 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
22876 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
22877 /*! LOCK_MODE - Lock low power and access mode */
22878 #define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_MASK)
22879 /*! @} */
22880 
22881 /*! @name GPR_PRIVATE6_AUTHEN_TOG - GPR access control */
22882 /*! @{ */
22883 
22884 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_MASK (0x1U)
22885 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_SHIFT (0U)
22886 /*! TZ_USER - User access */
22887 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_MASK)
22888 
22889 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
22890 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
22891 /*! TZ_NS - Non-secure access */
22892 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_MASK)
22893 
22894 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
22895 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
22896 /*! LOCK_TZ - Lock truszone setting */
22897 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_MASK)
22898 
22899 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
22900 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
22901 /*! WHITE_LIST - Whitelist */
22902 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_MASK)
22903 
22904 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
22905 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
22906 /*! LOCK_LIST - Lock Whitelist */
22907 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_MASK)
22908 
22909 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
22910 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
22911 /*! DOMAIN_MODE - Low power and access control by Domain */
22912 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_MASK)
22913 
22914 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
22915 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
22916 /*! LOCK_MODE - Lock low power and access mode */
22917 #define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_MASK)
22918 /*! @} */
22919 
22920 /*! @name GPR_PRIVATE7 - General Purpose Register */
22921 /*! @{ */
22922 
22923 #define CCM_GPR_PRIVATE7_GPR_MASK                (0xFFFFFFFFU)
22924 #define CCM_GPR_PRIVATE7_GPR_SHIFT               (0U)
22925 /*! GPR - GP register */
22926 #define CCM_GPR_PRIVATE7_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_GPR_SHIFT)) & CCM_GPR_PRIVATE7_GPR_MASK)
22927 /*! @} */
22928 
22929 /*! @name GPR_PRIVATE7_SET - General Purpose Register */
22930 /*! @{ */
22931 
22932 #define CCM_GPR_PRIVATE7_SET_GPR_MASK            (0xFFFFFFFFU)
22933 #define CCM_GPR_PRIVATE7_SET_GPR_SHIFT           (0U)
22934 /*! GPR - GP register */
22935 #define CCM_GPR_PRIVATE7_SET_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE7_SET_GPR_MASK)
22936 /*! @} */
22937 
22938 /*! @name GPR_PRIVATE7_CLR - General Purpose Register */
22939 /*! @{ */
22940 
22941 #define CCM_GPR_PRIVATE7_CLR_GPR_MASK            (0xFFFFFFFFU)
22942 #define CCM_GPR_PRIVATE7_CLR_GPR_SHIFT           (0U)
22943 /*! GPR - GP register */
22944 #define CCM_GPR_PRIVATE7_CLR_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE7_CLR_GPR_MASK)
22945 /*! @} */
22946 
22947 /*! @name GPR_PRIVATE7_TOG - General Purpose Register */
22948 /*! @{ */
22949 
22950 #define CCM_GPR_PRIVATE7_TOG_GPR_MASK            (0xFFFFFFFFU)
22951 #define CCM_GPR_PRIVATE7_TOG_GPR_SHIFT           (0U)
22952 /*! GPR - GP register */
22953 #define CCM_GPR_PRIVATE7_TOG_GPR(x)              (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE7_TOG_GPR_MASK)
22954 /*! @} */
22955 
22956 /*! @name GPR_PRIVATE7_AUTHEN - GPR access control */
22957 /*! @{ */
22958 
22959 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_MASK     (0x1U)
22960 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_SHIFT    (0U)
22961 /*! TZ_USER - User access
22962  *  0b1..Clock can be changed in user mode.
22963  *  0b0..Clock cannot be changed in user mode.
22964  */
22965 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_MASK)
22966 
22967 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_MASK       (0x2U)
22968 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_SHIFT      (1U)
22969 /*! TZ_NS - Non-secure access
22970  *  0b0..Cannot be changed in Non-secure mode.
22971  *  0b1..Can be changed in Non-secure mode.
22972  */
22973 #define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS(x)         (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_MASK)
22974 
22975 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_MASK     (0x10U)
22976 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_SHIFT    (4U)
22977 /*! LOCK_TZ - Lock truszone setting
22978  *  0b0..Trustzone setting is not locked.
22979  *  0b1..Trustzone setting is locked.
22980  */
22981 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ(x)       (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_MASK)
22982 
22983 #define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_MASK  (0xF00U)
22984 #define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_SHIFT (8U)
22985 /*! WHITE_LIST - Whitelist
22986  *  0b0000..This domain is NOT allowed to change clock.
22987  *  0b0001..This domain is allowed to change clock.
22988  */
22989 #define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_MASK)
22990 
22991 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_MASK   (0x1000U)
22992 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_SHIFT  (12U)
22993 /*! LOCK_LIST - Lock Whitelist
22994  *  0b0..Whitelist is not locked.
22995  *  0b1..Whitelist is locked.
22996  */
22997 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_MASK)
22998 
22999 #define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
23000 #define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_SHIFT (16U)
23001 /*! DOMAIN_MODE - Low power and access control by Domain
23002  *  0b1..Clock works in Domain Mode.
23003  *  0b0..Clock does NOT work in Domain Mode.
23004  */
23005 #define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_MASK)
23006 
23007 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_MASK   (0x100000U)
23008 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_SHIFT  (20U)
23009 /*! LOCK_MODE - Lock low power and access mode
23010  *  0b0..MODE is not locked.
23011  *  0b1..MODE is locked.
23012  */
23013 #define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_MASK)
23014 /*! @} */
23015 
23016 /*! @name GPR_PRIVATE7_AUTHEN_SET - GPR access control */
23017 /*! @{ */
23018 
23019 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_MASK (0x1U)
23020 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_SHIFT (0U)
23021 /*! TZ_USER - User access */
23022 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_MASK)
23023 
23024 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_MASK   (0x2U)
23025 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_SHIFT  (1U)
23026 /*! TZ_NS - Non-secure access */
23027 #define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_MASK)
23028 
23029 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
23030 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
23031 /*! LOCK_TZ - Lock truszone setting */
23032 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_MASK)
23033 
23034 #define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
23035 #define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
23036 /*! WHITE_LIST - Whitelist */
23037 #define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_MASK)
23038 
23039 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
23040 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
23041 /*! LOCK_LIST - Lock Whitelist */
23042 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_MASK)
23043 
23044 #define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
23045 #define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
23046 /*! DOMAIN_MODE - Low power and access control by Domain */
23047 #define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_MASK)
23048 
23049 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
23050 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
23051 /*! LOCK_MODE - Lock low power and access mode */
23052 #define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_MASK)
23053 /*! @} */
23054 
23055 /*! @name GPR_PRIVATE7_AUTHEN_CLR - GPR access control */
23056 /*! @{ */
23057 
23058 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_MASK (0x1U)
23059 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_SHIFT (0U)
23060 /*! TZ_USER - User access */
23061 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_MASK)
23062 
23063 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_MASK   (0x2U)
23064 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_SHIFT  (1U)
23065 /*! TZ_NS - Non-secure access */
23066 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_MASK)
23067 
23068 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
23069 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
23070 /*! LOCK_TZ - Lock truszone setting */
23071 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_MASK)
23072 
23073 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
23074 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
23075 /*! WHITE_LIST - Whitelist */
23076 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_MASK)
23077 
23078 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
23079 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
23080 /*! LOCK_LIST - Lock Whitelist */
23081 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_MASK)
23082 
23083 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
23084 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
23085 /*! DOMAIN_MODE - Low power and access control by Domain */
23086 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_MASK)
23087 
23088 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
23089 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
23090 /*! LOCK_MODE - Lock low power and access mode */
23091 #define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_MASK)
23092 /*! @} */
23093 
23094 /*! @name GPR_PRIVATE7_AUTHEN_TOG - GPR access control */
23095 /*! @{ */
23096 
23097 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_MASK (0x1U)
23098 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_SHIFT (0U)
23099 /*! TZ_USER - User access */
23100 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_MASK)
23101 
23102 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_MASK   (0x2U)
23103 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_SHIFT  (1U)
23104 /*! TZ_NS - Non-secure access */
23105 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS(x)     (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_MASK)
23106 
23107 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
23108 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
23109 /*! LOCK_TZ - Lock truszone setting */
23110 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ(x)   (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_MASK)
23111 
23112 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
23113 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
23114 /*! WHITE_LIST - Whitelist */
23115 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_MASK)
23116 
23117 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
23118 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
23119 /*! LOCK_LIST - Lock Whitelist */
23120 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_MASK)
23121 
23122 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
23123 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
23124 /*! DOMAIN_MODE - Low power and access control by Domain */
23125 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_MASK)
23126 
23127 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
23128 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
23129 /*! LOCK_MODE - Lock low power and access mode */
23130 #define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_MASK)
23131 /*! @} */
23132 
23133 /*! @name OSCPLL_DIRECT - Clock source direct control */
23134 /*! @{ */
23135 
23136 #define CCM_OSCPLL_DIRECT_ON_MASK                (0x1U)
23137 #define CCM_OSCPLL_DIRECT_ON_SHIFT               (0U)
23138 /*! ON - turn on clock source
23139  *  0b0..OSCPLL is OFF
23140  *  0b1..OSCPLL is ON
23141  */
23142 #define CCM_OSCPLL_DIRECT_ON(x)                  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DIRECT_ON_SHIFT)) & CCM_OSCPLL_DIRECT_ON_MASK)
23143 /*! @} */
23144 
23145 /* The count of CCM_OSCPLL_DIRECT */
23146 #define CCM_OSCPLL_DIRECT_COUNT                  (29U)
23147 
23148 /*! @name OSCPLL_DOMAIN - Clock source domain control */
23149 /*! @{ */
23150 
23151 #define CCM_OSCPLL_DOMAIN_LEVEL_MASK             (0x7U)
23152 #define CCM_OSCPLL_DOMAIN_LEVEL_SHIFT            (0U)
23153 /*! LEVEL - Current dependence level
23154  *  0b000..This clock source is not needed in any mode, and can be turned off
23155  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23156  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23157  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23158  *  0b100..This clock source is always on in any mode (including SUSPEND)
23159  *  0b101, 0b110, 0b111..Reserved
23160  */
23161 #define CCM_OSCPLL_DOMAIN_LEVEL(x)               (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL_MASK)
23162 
23163 #define CCM_OSCPLL_DOMAIN_LEVEL0_MASK            (0x70000U)
23164 #define CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT           (16U)
23165 /*! LEVEL0 - Dependence level
23166  *  0b000..This clock source is not needed in any mode, and can be turned off
23167  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23168  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23169  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23170  *  0b100..This clock source is always on in any mode (including SUSPEND)
23171  *  0b101, 0b110, 0b111..Reserved
23172  */
23173 #define CCM_OSCPLL_DOMAIN_LEVEL0(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL0_MASK)
23174 
23175 #define CCM_OSCPLL_DOMAIN_LEVEL1_MASK            (0x700000U)
23176 #define CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT           (20U)
23177 /*! LEVEL1 - Depend level
23178  *  0b000..This clock source is not needed in any mode, and can be turned off
23179  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23180  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23181  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23182  *  0b100..This clock source is always on in any mode (including SUSPEND)
23183  *  0b101, 0b110, 0b111..Reserved
23184  */
23185 #define CCM_OSCPLL_DOMAIN_LEVEL1(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL1_MASK)
23186 
23187 #define CCM_OSCPLL_DOMAIN_LEVEL2_MASK            (0x7000000U)
23188 #define CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT           (24U)
23189 /*! LEVEL2 - Depend level
23190  *  0b000..This clock source is not needed in any mode, and can be turned off
23191  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23192  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23193  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23194  *  0b100..This clock source is always on in any mode (including SUSPEND)
23195  *  0b101, 0b110, 0b111..Reserved
23196  */
23197 #define CCM_OSCPLL_DOMAIN_LEVEL2(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL2_MASK)
23198 
23199 #define CCM_OSCPLL_DOMAIN_LEVEL3_MASK            (0x70000000U)
23200 #define CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT           (28U)
23201 /*! LEVEL3 - Depend level
23202  *  0b000..This clock source is not needed in any mode, and can be turned off
23203  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23204  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23205  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23206  *  0b100..This clock source is always on in any mode (including SUSPEND)
23207  *  0b101, 0b110, 0b111..Reserved
23208  */
23209 #define CCM_OSCPLL_DOMAIN_LEVEL3(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL3_MASK)
23210 /*! @} */
23211 
23212 /* The count of CCM_OSCPLL_DOMAIN */
23213 #define CCM_OSCPLL_DOMAIN_COUNT                  (29U)
23214 
23215 /*! @name OSCPLL_SETPOINT - Clock source Setpoint setting */
23216 /*! @{ */
23217 
23218 #define CCM_OSCPLL_SETPOINT_SETPOINT_MASK        (0xFFFFU)
23219 #define CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT       (0U)
23220 /*! SETPOINT - Setpoint */
23221 #define CCM_OSCPLL_SETPOINT_SETPOINT(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT)) & CCM_OSCPLL_SETPOINT_SETPOINT_MASK)
23222 
23223 #define CCM_OSCPLL_SETPOINT_STANDBY_MASK         (0xFFFF0000U)
23224 #define CCM_OSCPLL_SETPOINT_STANDBY_SHIFT        (16U)
23225 /*! STANDBY - Standby */
23226 #define CCM_OSCPLL_SETPOINT_STANDBY(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_STANDBY_SHIFT)) & CCM_OSCPLL_SETPOINT_STANDBY_MASK)
23227 /*! @} */
23228 
23229 /* The count of CCM_OSCPLL_SETPOINT */
23230 #define CCM_OSCPLL_SETPOINT_COUNT                (29U)
23231 
23232 /*! @name OSCPLL_STATUS0 - Clock source working status */
23233 /*! @{ */
23234 
23235 #define CCM_OSCPLL_STATUS0_ON_MASK               (0x1U)
23236 #define CCM_OSCPLL_STATUS0_ON_SHIFT              (0U)
23237 /*! ON - Clock source current state
23238  *  0b0..Clock source is OFF
23239  *  0b1..Clock source is ON
23240  */
23241 #define CCM_OSCPLL_STATUS0_ON(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ON_SHIFT)) & CCM_OSCPLL_STATUS0_ON_MASK)
23242 
23243 #define CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK     (0x10U)
23244 #define CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT    (4U)
23245 /*! STATUS_EARLY - Clock source active
23246  *  0b1..Clock source is active
23247  *  0b0..Clock source is not active
23248  */
23249 #define CCM_OSCPLL_STATUS0_STATUS_EARLY(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK)
23250 
23251 #define CCM_OSCPLL_STATUS0_STATUS_LATE_MASK      (0x20U)
23252 #define CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT     (5U)
23253 /*! STATUS_LATE - Clock source ready
23254  *  0b1..Clock source is ready to use
23255  *  0b0..Clock source is not ready to use
23256  */
23257 #define CCM_OSCPLL_STATUS0_STATUS_LATE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_LATE_MASK)
23258 
23259 #define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK    (0xF00U)
23260 #define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT   (8U)
23261 /*! ACTIVE_DOMAIN - Domains that own this clock source
23262  *  0b0000..Clock not owned by any domain
23263  *  0b0001..Clock owned by Domain0
23264  *  0b0010..Clock owned by Domain1
23265  *  0b0011..Clock owned by Domain0 and Domain1
23266  *  0b0100..Clock owned by Domain2
23267  *  0b0101..Clock owned by Domain0 and Domain2
23268  *  0b0110..Clock owned by Domain1 and Domain2
23269  *  0b0111..Clock owned by Domain0, Domain1 and Domain 2
23270  *  0b1000..Clock owned by Domain3
23271  *  0b1001..Clock owned by Domain0 and Domain3
23272  *  0b1010..Clock owned by Domain1 and Domain3
23273  *  0b1011..Clock owned by Domain2 and Domain3
23274  *  0b1100..Clock owned by Domain0, Domain 1, and Domain3
23275  *  0b1101..Clock owned by Domain0, Domain 2, and Domain3
23276  *  0b1110..Clock owned by Domain1, Domain 2, and Domain3
23277  *  0b1111..Clock owned by all domains
23278  */
23279 #define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK)
23280 
23281 #define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK    (0xF000U)
23282 #define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT   (12U)
23283 /*! DOMAIN_ENABLE - Enable status from each domain
23284  *  0b0000..No domain request
23285  *  0b0001..Request from Domain0
23286  *  0b0010..Request from Domain1
23287  *  0b0011..Request from Domain0 and Domain1
23288  *  0b0100..Request from Domain2
23289  *  0b0101..Request from Domain0 and Domain2
23290  *  0b0110..Request from Domain1 and Domain2
23291  *  0b0111..Request from Domain0, Domain1 and Domain 2
23292  *  0b1000..Request from Domain3
23293  *  0b1001..Request from Domain0 and Domain3
23294  *  0b1010..Request from Domain1 and Domain3
23295  *  0b1011..Request from Domain2 and Domain3
23296  *  0b1100..Request from Domain0, Domain 1, and Domain3
23297  *  0b1101..Request from Domain0, Domain 2, and Domain3
23298  *  0b1110..Request from Domain1, Domain 2, and Domain3
23299  *  0b1111..Request from all domains
23300  */
23301 #define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK)
23302 
23303 #define CCM_OSCPLL_STATUS0_IN_USE_MASK           (0x10000000U)
23304 #define CCM_OSCPLL_STATUS0_IN_USE_SHIFT          (28U)
23305 /*! IN_USE - In use
23306  *  0b1..Clock source is being used by clock roots
23307  *  0b0..Clock source is not being used by clock roots
23308  */
23309 #define CCM_OSCPLL_STATUS0_IN_USE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_IN_USE_SHIFT)) & CCM_OSCPLL_STATUS0_IN_USE_MASK)
23310 /*! @} */
23311 
23312 /* The count of CCM_OSCPLL_STATUS0 */
23313 #define CCM_OSCPLL_STATUS0_COUNT                 (29U)
23314 
23315 /*! @name OSCPLL_STATUS1 - Clock source low power status */
23316 /*! @{ */
23317 
23318 #define CCM_OSCPLL_STATUS1_CPU0_MODE_MASK        (0x3U)
23319 #define CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT       (0U)
23320 /*! CPU0_MODE - Domain0 Low Power Mode
23321  *  0b00..Run
23322  *  0b01..Wait
23323  *  0b10..Stop
23324  *  0b11..Suspend
23325  */
23326 #define CCM_OSCPLL_STATUS1_CPU0_MODE(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_MASK)
23327 
23328 #define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK (0x4U)
23329 #define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U)
23330 /*! CPU0_MODE_REQUEST - Domain0 request enter Low Power Mode
23331  *  0b1..Request from domain to enter Low Power Mode
23332  *  0b0..No request
23333  */
23334 #define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK)
23335 
23336 #define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK   (0x8U)
23337 #define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT  (3U)
23338 /*! CPU0_MODE_DONE - Domain0 Low Power Mode task done
23339  *  0b1..Clock is gated-off
23340  *  0b0..Clock is not gated
23341  */
23342 #define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK)
23343 
23344 #define CCM_OSCPLL_STATUS1_CPU1_MODE_MASK        (0x30U)
23345 #define CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT       (4U)
23346 /*! CPU1_MODE - Domain1 Low Power Mode
23347  *  0b00..Run
23348  *  0b01..Wait
23349  *  0b10..Stop
23350  *  0b11..Suspend
23351  */
23352 #define CCM_OSCPLL_STATUS1_CPU1_MODE(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_MASK)
23353 
23354 #define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK (0x40U)
23355 #define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U)
23356 /*! CPU1_MODE_REQUEST - Domain1 request enter Low Power Mode
23357  *  0b1..Request from domain to enter Low Power Mode
23358  *  0b0..No request
23359  */
23360 #define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK)
23361 
23362 #define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK   (0x80U)
23363 #define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT  (7U)
23364 /*! CPU1_MODE_DONE - Domain1 Low Power Mode task done
23365  *  0b1..Clock is gated-off
23366  *  0b0..Clock is not gated
23367  */
23368 #define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK)
23369 
23370 #define CCM_OSCPLL_STATUS1_CPU2_MODE_MASK        (0x300U)
23371 #define CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT       (8U)
23372 /*! CPU2_MODE - Domain2 Low Power Mode
23373  *  0b00..Run
23374  *  0b01..Wait
23375  *  0b10..Stop
23376  *  0b11..Suspend
23377  */
23378 #define CCM_OSCPLL_STATUS1_CPU2_MODE(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_MASK)
23379 
23380 #define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK (0x400U)
23381 #define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U)
23382 /*! CPU2_MODE_REQUEST - Domain2 request enter Low Power Mode
23383  *  0b1..Request from domain to enter Low Power Mode
23384  *  0b0..No request
23385  */
23386 #define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK)
23387 
23388 #define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK   (0x800U)
23389 #define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT  (11U)
23390 /*! CPU2_MODE_DONE - Domain2 Low Power Mode task done
23391  *  0b1..Clock is gated-off
23392  *  0b0..Clock is not gated
23393  */
23394 #define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK)
23395 
23396 #define CCM_OSCPLL_STATUS1_CPU3_MODE_MASK        (0x3000U)
23397 #define CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT       (12U)
23398 /*! CPU3_MODE - Domain3 Low Power Mode
23399  *  0b00..Run
23400  *  0b01..Wait
23401  *  0b10..Stop
23402  *  0b11..Suspend
23403  */
23404 #define CCM_OSCPLL_STATUS1_CPU3_MODE(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_MASK)
23405 
23406 #define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK (0x4000U)
23407 #define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U)
23408 /*! CPU3_MODE_REQUEST - Domain3 request enter Low Power Mode
23409  *  0b1..Request from domain to enter Low Power Mode
23410  *  0b0..No request
23411  */
23412 #define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK)
23413 
23414 #define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK   (0x8000U)
23415 #define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT  (15U)
23416 /*! CPU3_MODE_DONE - Domain3 Low Power Mode task done
23417  *  0b1..Clock is gated-off
23418  *  0b0..Clock is not gated
23419  */
23420 #define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK)
23421 
23422 #define CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK  (0xF0000U)
23423 #define CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT (16U)
23424 /*! TARGET_SETPOINT - Next Setpoint to change to */
23425 #define CCM_OSCPLL_STATUS1_TARGET_SETPOINT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK)
23426 
23427 #define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
23428 #define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
23429 /*! CURRENT_SETPOINT - Current Setpoint */
23430 #define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT(x)   (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK)
23431 
23432 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U)
23433 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U)
23434 /*! SETPOINT_OFF_REQUEST - Clock gate turn off request from GPC Setpoint
23435  *  0b1..Clock gate requested to be turned off
23436  *  0b0..No request
23437  */
23438 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK)
23439 
23440 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK (0x2000000U)
23441 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U)
23442 /*! SETPOINT_OFF_DONE - Clock source turn off finish from GPC Setpoint
23443  *  0b1..Clock source is turned off
23444  *  0b0..Clock source is not turned off
23445  */
23446 #define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK)
23447 
23448 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U)
23449 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U)
23450 /*! SETPOINT_ON_REQUEST - Clock gate turn on request from GPC Setpoint
23451  *  0b1..Clock gate requested to be turned on
23452  *  0b0..No request
23453  */
23454 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK)
23455 
23456 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK (0x8000000U)
23457 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT (27U)
23458 /*! SETPOINT_ON_DONE - Clock gate turn on finish from GPC Setpoint
23459  *  0b1..Request to turn on clock gate
23460  *  0b0..No request
23461  */
23462 #define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK)
23463 
23464 #define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK (0x10000000U)
23465 #define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT (28U)
23466 /*! STANDBY_IN_REQUEST - Clock gate turn off request from GPC standby
23467  *  0b1..Clock gate requested to be turned off
23468  *  0b0..No request
23469  */
23470 #define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK)
23471 
23472 #define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK  (0x20000000U)
23473 #define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT (29U)
23474 /*! STANDBY_IN_DONE - Clock source turn off finish from GPC standby
23475  *  0b1..Clock source is turned off
23476  *  0b0..Clock source is not turned off
23477  */
23478 #define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK)
23479 
23480 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK (0x40000000U)
23481 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT (30U)
23482 /*! STANDBY_OUT_DONE - Clock gate turn on finish from GPC standby
23483  *  0b1..Request to turn on Clock gate is complete
23484  *  0b0..Request to turn on Clock gate is not complete
23485  */
23486 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE(x)   (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK)
23487 
23488 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK (0x80000000U)
23489 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT (31U)
23490 /*! STANDBY_OUT_REQUEST - Clock gate turn on request from GPC standby
23491  *  0b1..Clock gate requested to be turned on
23492  *  0b0..No request
23493  */
23494 #define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK)
23495 /*! @} */
23496 
23497 /* The count of CCM_OSCPLL_STATUS1 */
23498 #define CCM_OSCPLL_STATUS1_COUNT                 (29U)
23499 
23500 /*! @name OSCPLL_CONFIG - Clock source configuration */
23501 /*! @{ */
23502 
23503 #define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK  (0x2U)
23504 #define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT (1U)
23505 /*! AUTOMODE_PRESENT - Automode Present
23506  *  0b1..Present
23507  *  0b0..Not present
23508  */
23509 #define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK)
23510 
23511 #define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK  (0x10U)
23512 #define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
23513 /*! SETPOINT_PRESENT - Setpoint present
23514  *  0b1..Setpoint is implemented.
23515  *  0b0..Setpoint is not implemented.
23516  */
23517 #define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK)
23518 /*! @} */
23519 
23520 /* The count of CCM_OSCPLL_CONFIG */
23521 #define CCM_OSCPLL_CONFIG_COUNT                  (29U)
23522 
23523 /*! @name OSCPLL_AUTHEN - Clock source access control */
23524 /*! @{ */
23525 
23526 #define CCM_OSCPLL_AUTHEN_TZ_USER_MASK           (0x1U)
23527 #define CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT          (0U)
23528 /*! TZ_USER - User access
23529  *  0b1..Clock can be changed in user mode.
23530  *  0b0..Clock cannot be changed in user mode.
23531  */
23532 #define CCM_OSCPLL_AUTHEN_TZ_USER(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_USER_MASK)
23533 
23534 #define CCM_OSCPLL_AUTHEN_TZ_NS_MASK             (0x2U)
23535 #define CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT            (1U)
23536 /*! TZ_NS - Non-secure access
23537  *  0b0..Cannot be changed in Non-secure mode.
23538  *  0b1..Can be changed in Non-secure mode.
23539  */
23540 #define CCM_OSCPLL_AUTHEN_TZ_NS(x)               (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_NS_MASK)
23541 
23542 #define CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK           (0x10U)
23543 #define CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT          (4U)
23544 /*! LOCK_TZ - lock truszone setting
23545  *  0b0..Trustzone setting is not locked.
23546  *  0b1..Trustzone setting is locked.
23547  */
23548 #define CCM_OSCPLL_AUTHEN_LOCK_TZ(x)             (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK)
23549 
23550 #define CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK        (0xF00U)
23551 #define CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT       (8U)
23552 /*! WHITE_LIST - Whitelist */
23553 #define CCM_OSCPLL_AUTHEN_WHITE_LIST(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK)
23554 
23555 #define CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK         (0x1000U)
23556 #define CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT        (12U)
23557 /*! LOCK_LIST - Lock Whitelist
23558  *  0b0..Whitelist is not locked.
23559  *  0b1..Whitelist is locked.
23560  */
23561 #define CCM_OSCPLL_AUTHEN_LOCK_LIST(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK)
23562 
23563 #define CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK       (0x10000U)
23564 #define CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT      (16U)
23565 /*! DOMAIN_MODE - Low power and access control by domain
23566  *  0b1..Clock works in Domain Mode.
23567  *  0b0..Clock does not work in Domain Mode.
23568  */
23569 #define CCM_OSCPLL_AUTHEN_DOMAIN_MODE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK)
23570 
23571 #define CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK     (0x20000U)
23572 #define CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT    (17U)
23573 /*! SETPOINT_MODE - LPCG works in Setpoint controlled Mode. */
23574 #define CCM_OSCPLL_AUTHEN_SETPOINT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK)
23575 
23576 #define CCM_OSCPLL_AUTHEN_CPULPM_MASK            (0x40000U)
23577 #define CCM_OSCPLL_AUTHEN_CPULPM_SHIFT           (18U)
23578 /*! CPULPM - CPU Low Power Mode
23579  *  0b1..PLL functions in Low Power Mode
23580  *  0b0..PLL does not function in Low power Mode
23581  */
23582 #define CCM_OSCPLL_AUTHEN_CPULPM(x)              (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_CPULPM_SHIFT)) & CCM_OSCPLL_AUTHEN_CPULPM_MASK)
23583 
23584 #define CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK         (0x100000U)
23585 #define CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT        (20U)
23586 /*! LOCK_MODE - Lock low power and access mode
23587  *  0b0..MODE is not locked.
23588  *  0b1..MODE is locked.
23589  */
23590 #define CCM_OSCPLL_AUTHEN_LOCK_MODE(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK)
23591 /*! @} */
23592 
23593 /* The count of CCM_OSCPLL_AUTHEN */
23594 #define CCM_OSCPLL_AUTHEN_COUNT                  (29U)
23595 
23596 /*! @name LPCG_DIRECT - LPCG direct control */
23597 /*! @{ */
23598 
23599 #define CCM_LPCG_DIRECT_ON_MASK                  (0x1U)
23600 #define CCM_LPCG_DIRECT_ON_SHIFT                 (0U)
23601 /*! ON - LPCG on
23602  *  0b0..LPCG is OFF.
23603  *  0b1..LPCG is ON.
23604  */
23605 #define CCM_LPCG_DIRECT_ON(x)                    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_ON_SHIFT)) & CCM_LPCG_DIRECT_ON_MASK)
23606 /*! @} */
23607 
23608 /* The count of CCM_LPCG_DIRECT */
23609 #define CCM_LPCG_DIRECT_COUNT                    (138U)
23610 
23611 /*! @name LPCG_DOMAIN - LPCG domain control */
23612 /*! @{ */
23613 
23614 #define CCM_LPCG_DOMAIN_LEVEL_MASK               (0x7U)
23615 #define CCM_LPCG_DOMAIN_LEVEL_SHIFT              (0U)
23616 /*! LEVEL - Current dependence level
23617  *  0b000..This clock source is not needed in any mode, and can be turned off
23618  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23619  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23620  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23621  *  0b100..This clock source is always on in any mode (including SUSPEND)
23622  *  0b101, 0b110, 0b111..Reserved
23623  */
23624 #define CCM_LPCG_DOMAIN_LEVEL(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL_MASK)
23625 
23626 #define CCM_LPCG_DOMAIN_LEVEL0_MASK              (0x70000U)
23627 #define CCM_LPCG_DOMAIN_LEVEL0_SHIFT             (16U)
23628 /*! LEVEL0 - Depend level
23629  *  0b000..This clock source is not needed in any mode, and can be turned off
23630  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23631  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23632  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23633  *  0b100..This clock source is always on in any mode (including SUSPEND)
23634  *  0b101, 0b110, 0b111..Reserved
23635  */
23636 #define CCM_LPCG_DOMAIN_LEVEL0(x)                (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL0_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL0_MASK)
23637 
23638 #define CCM_LPCG_DOMAIN_LEVEL1_MASK              (0x700000U)
23639 #define CCM_LPCG_DOMAIN_LEVEL1_SHIFT             (20U)
23640 /*! LEVEL1 - Depend level
23641  *  0b000..This clock source is not needed in any mode, and can be turned off
23642  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23643  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23644  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23645  *  0b100..This clock source is always on in any mode (including SUSPEND)
23646  *  0b101, 0b110, 0b111..Reserved
23647  */
23648 #define CCM_LPCG_DOMAIN_LEVEL1(x)                (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL1_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL1_MASK)
23649 
23650 #define CCM_LPCG_DOMAIN_LEVEL2_MASK              (0x7000000U)
23651 #define CCM_LPCG_DOMAIN_LEVEL2_SHIFT             (24U)
23652 /*! LEVEL2 - Depend level
23653  *  0b000..This clock source is not needed in any mode, and can be turned off
23654  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23655  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23656  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23657  *  0b100..This clock source is always on in any mode (including SUSPEND)
23658  *  0b101, 0b110, 0b111..Reserved
23659  */
23660 #define CCM_LPCG_DOMAIN_LEVEL2(x)                (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL2_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL2_MASK)
23661 
23662 #define CCM_LPCG_DOMAIN_LEVEL3_MASK              (0x70000000U)
23663 #define CCM_LPCG_DOMAIN_LEVEL3_SHIFT             (28U)
23664 /*! LEVEL3 - Depend level
23665  *  0b000..This clock source is not needed in any mode, and can be turned off
23666  *  0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
23667  *  0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
23668  *  0b011..This clock source is needed in RUN, WAIT and STOP mode
23669  *  0b100..This clock source is always on in any mode (including SUSPEND)
23670  *  0b101, 0b110, 0b111..Reserved
23671  */
23672 #define CCM_LPCG_DOMAIN_LEVEL3(x)                (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL3_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL3_MASK)
23673 /*! @} */
23674 
23675 /* The count of CCM_LPCG_DOMAIN */
23676 #define CCM_LPCG_DOMAIN_COUNT                    (138U)
23677 
23678 /*! @name LPCG_SETPOINT - LPCG Setpoint setting */
23679 /*! @{ */
23680 
23681 #define CCM_LPCG_SETPOINT_SETPOINT_MASK          (0xFFFFU)
23682 #define CCM_LPCG_SETPOINT_SETPOINT_SHIFT         (0U)
23683 /*! SETPOINT - Setpoints */
23684 #define CCM_LPCG_SETPOINT_SETPOINT(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_SETPOINT_SETPOINT_SHIFT)) & CCM_LPCG_SETPOINT_SETPOINT_MASK)
23685 
23686 #define CCM_LPCG_SETPOINT_STANDBY_MASK           (0xFFFF0000U)
23687 #define CCM_LPCG_SETPOINT_STANDBY_SHIFT          (16U)
23688 /*! STANDBY - Standby */
23689 #define CCM_LPCG_SETPOINT_STANDBY(x)             (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_SETPOINT_STANDBY_SHIFT)) & CCM_LPCG_SETPOINT_STANDBY_MASK)
23690 /*! @} */
23691 
23692 /* The count of CCM_LPCG_SETPOINT */
23693 #define CCM_LPCG_SETPOINT_COUNT                  (138U)
23694 
23695 /*! @name LPCG_STATUS0 - LPCG working status */
23696 /*! @{ */
23697 
23698 #define CCM_LPCG_STATUS0_ON_MASK                 (0x1U)
23699 #define CCM_LPCG_STATUS0_ON_SHIFT                (0U)
23700 /*! ON - LPCG current state
23701  *  0b0..LPCG is OFF.
23702  *  0b1..LPCG is ON.
23703  */
23704 #define CCM_LPCG_STATUS0_ON(x)                   (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ON_SHIFT)) & CCM_LPCG_STATUS0_ON_MASK)
23705 
23706 #define CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK      (0xF00U)
23707 #define CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT     (8U)
23708 /*! ACTIVE_DOMAIN - Domains that own this clock gate
23709  *  0b0000..Clock not owned by any domain
23710  *  0b0001..Clock owned by Domain0
23711  *  0b0010..Clock owned by Domain1
23712  *  0b0011..Clock owned by Domain0 and Domain1
23713  *  0b0100..Clock owned by Domain2
23714  *  0b0101..Clock owned by Domain0 and Domain2
23715  *  0b0110..Clock owned by Domain1 and Domain2
23716  *  0b0111..Clock owned by Domain0, Domain1 and Domain 2
23717  *  0b1000..Clock owned by Domain3
23718  *  0b1001..Clock owned by Domain0 and Domain3
23719  *  0b1010..Clock owned by Domain1 and Domain3
23720  *  0b1011..Clock owned by Domain2 and Domain3
23721  *  0b1100..Clock owned by Domain0, Domain 1, and Domain3
23722  *  0b1101..Clock owned by Domain0, Domain 2, and Domain3
23723  *  0b1110..Clock owned by Domain1, Domain 2, and Domain3
23724  *  0b1111..Clock owned by all domains
23725  */
23726 #define CCM_LPCG_STATUS0_ACTIVE_DOMAIN(x)        (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK)
23727 
23728 #define CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK      (0xF000U)
23729 #define CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT     (12U)
23730 /*! DOMAIN_ENABLE - Enable status from each domain
23731  *  0b0000..No domain request
23732  *  0b0001..Request from Domain0
23733  *  0b0010..Request from Domain1
23734  *  0b0011..Request from Domain0 and Domain1
23735  *  0b0100..Request from Domain2
23736  *  0b0101..Request from Domain0 and Domain2
23737  *  0b0110..Request from Domain1 and Domain2
23738  *  0b0111..Request from Domain0, Domain1 and Domain 2
23739  *  0b1000..Request from Domain3
23740  *  0b1001..Request from Domain0 and Domain3
23741  *  0b1010..Request from Domain1 and Domain3
23742  *  0b1011..Request from Domain2 and Domain3
23743  *  0b1100..Request from Domain0, Domain 1, and Domain3
23744  *  0b1101..Request from Domain0, Domain 2, and Domain3
23745  *  0b1110..Request from Domain1, Domain 2, and Domain3
23746  *  0b1111..Request from all domains
23747  */
23748 #define CCM_LPCG_STATUS0_DOMAIN_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK)
23749 /*! @} */
23750 
23751 /* The count of CCM_LPCG_STATUS0 */
23752 #define CCM_LPCG_STATUS0_COUNT                   (138U)
23753 
23754 /*! @name LPCG_STATUS1 - LPCG low power status */
23755 /*! @{ */
23756 
23757 #define CCM_LPCG_STATUS1_CPU0_MODE_MASK          (0x3U)
23758 #define CCM_LPCG_STATUS1_CPU0_MODE_SHIFT         (0U)
23759 /*! CPU0_MODE - Domain0 Low Power Mode
23760  *  0b00..Run
23761  *  0b01..Wait
23762  *  0b10..Stop
23763  *  0b11..Suspend
23764  */
23765 #define CCM_LPCG_STATUS1_CPU0_MODE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
23766 
23767 #define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK  (0x4U)
23768 #define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U)
23769 /*! CPU0_MODE_REQUEST - Domain0 request enter Low Power Mode
23770  *  0b1..Request from domain to enter Low Power Mode
23771  *  0b0..No request
23772  */
23773 #define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK)
23774 
23775 #define CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK     (0x8U)
23776 #define CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT    (3U)
23777 /*! CPU0_MODE_DONE - Domain0 Low Power Mode task done
23778  *  0b1..Clock is gated-off
23779  *  0b0..Clock is not gated
23780  */
23781 #define CCM_LPCG_STATUS1_CPU0_MODE_DONE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK)
23782 
23783 #define CCM_LPCG_STATUS1_CPU1_MODE_MASK          (0x30U)
23784 #define CCM_LPCG_STATUS1_CPU1_MODE_SHIFT         (4U)
23785 /*! CPU1_MODE - Domain1 Low Power Mode
23786  *  0b00..Run
23787  *  0b01..Wait
23788  *  0b10..Stop
23789  *  0b11..Suspend
23790  */
23791 #define CCM_LPCG_STATUS1_CPU1_MODE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_MASK)
23792 
23793 #define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK  (0x40U)
23794 #define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U)
23795 /*! CPU1_MODE_REQUEST - Domain1 request enter Low Power Mode
23796  *  0b1..Request from domain to enter Low Power Mode
23797  *  0b0..No request
23798  */
23799 #define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK)
23800 
23801 #define CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK     (0x80U)
23802 #define CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT    (7U)
23803 /*! CPU1_MODE_DONE - Domain1 Low Power Mode task done
23804  *  0b1..Clock is gated-off
23805  *  0b0..Clock is not gated
23806  */
23807 #define CCM_LPCG_STATUS1_CPU1_MODE_DONE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK)
23808 
23809 #define CCM_LPCG_STATUS1_CPU2_MODE_MASK          (0x300U)
23810 #define CCM_LPCG_STATUS1_CPU2_MODE_SHIFT         (8U)
23811 /*! CPU2_MODE - Domain2 Low Power Mode
23812  *  0b00..Run
23813  *  0b01..Wait
23814  *  0b10..Stop
23815  *  0b11..Suspend
23816  */
23817 #define CCM_LPCG_STATUS1_CPU2_MODE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_MASK)
23818 
23819 #define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK  (0x400U)
23820 #define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U)
23821 /*! CPU2_MODE_REQUEST - Domain2 request enter Low Power Mode
23822  *  0b1..Request from domain to enter Low Power Mode
23823  *  0b0..No request
23824  */
23825 #define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK)
23826 
23827 #define CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK     (0x800U)
23828 #define CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT    (11U)
23829 /*! CPU2_MODE_DONE - Domain2 Low Power Mode task done
23830  *  0b1..Clock is gated-off
23831  *  0b0..Clock is not gated
23832  */
23833 #define CCM_LPCG_STATUS1_CPU2_MODE_DONE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK)
23834 
23835 #define CCM_LPCG_STATUS1_CPU3_MODE_MASK          (0x3000U)
23836 #define CCM_LPCG_STATUS1_CPU3_MODE_SHIFT         (12U)
23837 /*! CPU3_MODE - Domain3 Low Power Mode
23838  *  0b00..Run
23839  *  0b01..Wait
23840  *  0b10..Stop
23841  *  0b11..Suspend
23842  */
23843 #define CCM_LPCG_STATUS1_CPU3_MODE(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_MASK)
23844 
23845 #define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK  (0x4000U)
23846 #define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U)
23847 /*! CPU3_MODE_REQUEST - Domain3 request enter Low Power Mode
23848  *  0b1..Request from domain to enter Low Power Mode
23849  *  0b0..No request
23850  */
23851 #define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST(x)    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK)
23852 
23853 #define CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK     (0x8000U)
23854 #define CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT    (15U)
23855 /*! CPU3_MODE_DONE - Domain3 Low Power Mode task done
23856  *  0b1..Clock is gated-off
23857  *  0b0..Clock is not gated
23858  */
23859 #define CCM_LPCG_STATUS1_CPU3_MODE_DONE(x)       (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK)
23860 
23861 #define CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK    (0xF0000U)
23862 #define CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT   (16U)
23863 /*! TARGET_SETPOINT - Next Setpoint to change to */
23864 #define CCM_LPCG_STATUS1_TARGET_SETPOINT(x)      (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK)
23865 
23866 #define CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK   (0xF00000U)
23867 #define CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT  (20U)
23868 /*! CURRENT_SETPOINT - Current Setpoint */
23869 #define CCM_LPCG_STATUS1_CURRENT_SETPOINT(x)     (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK)
23870 
23871 #define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U)
23872 #define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U)
23873 /*! SETPOINT_OFF_REQUEST - Clock gate turn off request from GPC Setpoint
23874  *  0b1..Clock gate requested to be turned off
23875  *  0b0..No request
23876  */
23877 #define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK)
23878 
23879 #define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK  (0x2000000U)
23880 #define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U)
23881 /*! SETPOINT_OFF_DONE - Clock gate turn off finish from GPC Setpoint
23882  *  0b1..Clock gate is turned off
23883  *  0b0..Clock gate is not turned off
23884  */
23885 #define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK)
23886 
23887 #define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U)
23888 #define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U)
23889 /*! SETPOINT_ON_REQUEST - Clock gate turn on request from GPC Setpoint
23890  *  0b1..Clock gate requested to be turned on
23891  *  0b0..No request
23892  */
23893 #define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK)
23894 
23895 #define CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK   (0x8000000U)
23896 #define CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT  (27U)
23897 /*! SETPOINT_ON_DONE - Clock gate turn on finish from GPC Setpoint
23898  *  0b1..Clock gate is turned on
23899  *  0b0..Clock gate is not turned on
23900  */
23901 #define CCM_LPCG_STATUS1_SETPOINT_ON_DONE(x)     (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK)
23902 /*! @} */
23903 
23904 /* The count of CCM_LPCG_STATUS1 */
23905 #define CCM_LPCG_STATUS1_COUNT                   (138U)
23906 
23907 /*! @name LPCG_CONFIG - LPCG configuration */
23908 /*! @{ */
23909 
23910 #define CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK    (0x10U)
23911 #define CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT   (4U)
23912 /*! SETPOINT_PRESENT - Setpoint present
23913  *  0b1..Setpoint is implemented.
23914  *  0b0..Setpoint is not implemented.
23915  */
23916 #define CCM_LPCG_CONFIG_SETPOINT_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK)
23917 /*! @} */
23918 
23919 /* The count of CCM_LPCG_CONFIG */
23920 #define CCM_LPCG_CONFIG_COUNT                    (138U)
23921 
23922 /*! @name LPCG_AUTHEN - LPCG access control */
23923 /*! @{ */
23924 
23925 #define CCM_LPCG_AUTHEN_TZ_USER_MASK             (0x1U)
23926 #define CCM_LPCG_AUTHEN_TZ_USER_SHIFT            (0U)
23927 /*! TZ_USER - User access
23928  *  0b1..LPCG can be changed in user mode.
23929  *  0b0..LPCG cannot be changed in user mode.
23930  */
23931 #define CCM_LPCG_AUTHEN_TZ_USER(x)               (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_USER_SHIFT)) & CCM_LPCG_AUTHEN_TZ_USER_MASK)
23932 
23933 #define CCM_LPCG_AUTHEN_TZ_NS_MASK               (0x2U)
23934 #define CCM_LPCG_AUTHEN_TZ_NS_SHIFT              (1U)
23935 /*! TZ_NS - Non-secure access
23936  *  0b0..Cannot be changed in Non-secure mode.
23937  *  0b1..Can be changed in Non-secure mode.
23938  */
23939 #define CCM_LPCG_AUTHEN_TZ_NS(x)                 (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_NS_SHIFT)) & CCM_LPCG_AUTHEN_TZ_NS_MASK)
23940 
23941 #define CCM_LPCG_AUTHEN_LOCK_TZ_MASK             (0x10U)
23942 #define CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT            (4U)
23943 /*! LOCK_TZ - lock truszone setting
23944  *  0b0..Trustzone setting is not locked.
23945  *  0b1..Trustzone setting is locked.
23946  */
23947 #define CCM_LPCG_AUTHEN_LOCK_TZ(x)               (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_TZ_MASK)
23948 
23949 #define CCM_LPCG_AUTHEN_WHITE_LIST_MASK          (0xF00U)
23950 #define CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT         (8U)
23951 /*! WHITE_LIST - Whitelist */
23952 #define CCM_LPCG_AUTHEN_WHITE_LIST(x)            (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT)) & CCM_LPCG_AUTHEN_WHITE_LIST_MASK)
23953 
23954 #define CCM_LPCG_AUTHEN_LOCK_LIST_MASK           (0x1000U)
23955 #define CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT          (12U)
23956 /*! LOCK_LIST - Lock Whitelist
23957  *  0b0..Whitelist is not locked.
23958  *  0b1..Whitelist is locked.
23959  */
23960 #define CCM_LPCG_AUTHEN_LOCK_LIST(x)             (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_LIST_MASK)
23961 
23962 #define CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK         (0x10000U)
23963 #define CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT        (16U)
23964 /*! DOMAIN_MODE - Low power and access control by domain
23965  *  0b1..Clock works in Domain Mode
23966  *  0b0..Clock does not work in Domain Mode
23967  */
23968 #define CCM_LPCG_AUTHEN_DOMAIN_MODE(x)           (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK)
23969 
23970 #define CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK       (0x20000U)
23971 #define CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT      (17U)
23972 /*! SETPOINT_MODE - Low power and access control by Setpoint
23973  *  0b1..LPCG is functioning in Setpoint controlled Mode
23974  *  0b0..LPCG is not functioning in Setpoint controlled Mode
23975  */
23976 #define CCM_LPCG_AUTHEN_SETPOINT_MODE(x)         (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK)
23977 
23978 #define CCM_LPCG_AUTHEN_CPULPM_MASK              (0x40000U)
23979 #define CCM_LPCG_AUTHEN_CPULPM_SHIFT             (18U)
23980 /*! CPULPM - CPU Low Power Mode
23981  *  0b1..LPCG is functioning in Low Power Mode
23982  *  0b0..LPCG is not functioning in Low power Mode
23983  */
23984 #define CCM_LPCG_AUTHEN_CPULPM(x)                (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_CPULPM_SHIFT)) & CCM_LPCG_AUTHEN_CPULPM_MASK)
23985 
23986 #define CCM_LPCG_AUTHEN_LOCK_MODE_MASK           (0x100000U)
23987 #define CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT          (20U)
23988 /*! LOCK_MODE - Lock low power and access mode
23989  *  0b0..MODE is not locked.
23990  *  0b1..MODE is locked.
23991  */
23992 #define CCM_LPCG_AUTHEN_LOCK_MODE(x)             (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_MODE_MASK)
23993 /*! @} */
23994 
23995 /* The count of CCM_LPCG_AUTHEN */
23996 #define CCM_LPCG_AUTHEN_COUNT                    (138U)
23997 
23998 
23999 /*!
24000  * @}
24001  */ /* end of group CCM_Register_Masks */
24002 
24003 
24004 /* CCM - Peripheral instance base addresses */
24005 /** Peripheral CCM base address */
24006 #define CCM_BASE                                 (0x40CC0000u)
24007 /** Peripheral CCM base pointer */
24008 #define CCM                                      ((CCM_Type *)CCM_BASE)
24009 /** Array initializer of CCM peripheral base addresses */
24010 #define CCM_BASE_ADDRS                           { CCM_BASE }
24011 /** Array initializer of CCM peripheral base pointers */
24012 #define CCM_BASE_PTRS                            { CCM }
24013 
24014 /*!
24015  * @}
24016  */ /* end of group CCM_Peripheral_Access_Layer */
24017 
24018 
24019 /* ----------------------------------------------------------------------------
24020    -- CCM_OBS Peripheral Access Layer
24021    ---------------------------------------------------------------------------- */
24022 
24023 /*!
24024  * @addtogroup CCM_OBS_Peripheral_Access_Layer CCM_OBS Peripheral Access Layer
24025  * @{
24026  */
24027 
24028 /** CCM_OBS - Register Layout Typedef */
24029 typedef struct {
24030   struct {                                         /* offset: 0x0, array step: 0x80 */
24031     __IO uint32_t CONTROL;                           /**< Observe control, array offset: 0x0, array step: 0x80 */
24032     __IO uint32_t CONTROL_SET;                       /**< Observe control, array offset: 0x4, array step: 0x80 */
24033     __IO uint32_t CONTROL_CLR;                       /**< Observe control, array offset: 0x8, array step: 0x80 */
24034     __IO uint32_t CONTROL_TOG;                       /**< Observe control, array offset: 0xC, array step: 0x80 */
24035          uint8_t RESERVED_0[16];
24036     __I  uint32_t STATUS0;                           /**< Observe status, array offset: 0x20, array step: 0x80 */
24037          uint8_t RESERVED_1[12];
24038     __IO uint32_t AUTHEN;                            /**< Observe access control, array offset: 0x30, array step: 0x80 */
24039     __IO uint32_t AUTHEN_SET;                        /**< Observe access control, array offset: 0x34, array step: 0x80 */
24040     __IO uint32_t AUTHEN_CLR;                        /**< Observe access control, array offset: 0x38, array step: 0x80 */
24041     __IO uint32_t AUTHEN_TOG;                        /**< Observe access control, array offset: 0x3C, array step: 0x80 */
24042     __I  uint32_t FREQUENCY_CURRENT;                 /**< Current frequency detected, array offset: 0x40, array step: 0x80 */
24043     __I  uint32_t FREQUENCY_MIN;                     /**< Minimum frequency detected, array offset: 0x44, array step: 0x80 */
24044     __I  uint32_t FREQUENCY_MAX;                     /**< Maximum frequency detected, array offset: 0x48, array step: 0x80 */
24045          uint8_t RESERVED_2[52];
24046   } OBSERVE[6];
24047 } CCM_OBS_Type;
24048 
24049 /* ----------------------------------------------------------------------------
24050    -- CCM_OBS Register Masks
24051    ---------------------------------------------------------------------------- */
24052 
24053 /*!
24054  * @addtogroup CCM_OBS_Register_Masks CCM_OBS Register Masks
24055  * @{
24056  */
24057 
24058 /*! @name OBSERVE_CONTROL - Observe control */
24059 /*! @{ */
24060 
24061 #define CCM_OBS_OBSERVE_CONTROL_SELECT_MASK      (0x1FFU)
24062 #define CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT     (0U)
24063 /*! SELECT - Observe signal selector */
24064 #define CCM_OBS_OBSERVE_CONTROL_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SELECT_MASK)
24065 
24066 #define CCM_OBS_OBSERVE_CONTROL_RAW_MASK         (0x1000U)
24067 #define CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT        (12U)
24068 /*! RAW - Observe raw signal
24069  *  0b0..Select divided signal.
24070  *  0b1..Select raw signal.
24071  */
24072 #define CCM_OBS_OBSERVE_CONTROL_RAW(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RAW_MASK)
24073 
24074 #define CCM_OBS_OBSERVE_CONTROL_INV_MASK         (0x2000U)
24075 #define CCM_OBS_OBSERVE_CONTROL_INV_SHIFT        (13U)
24076 /*! INV - Invert
24077  *  0b0..Clock phase remain same.
24078  *  0b1..Invert clock phase before measurement or send to IO.
24079  */
24080 #define CCM_OBS_OBSERVE_CONTROL_INV(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_INV_MASK)
24081 
24082 #define CCM_OBS_OBSERVE_CONTROL_RESET_MASK       (0x8000U)
24083 #define CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT      (15U)
24084 /*! RESET - Reset observe divider
24085  *  0b0..No reset
24086  *  0b1..Reset observe divider
24087  */
24088 #define CCM_OBS_OBSERVE_CONTROL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RESET_MASK)
24089 
24090 #define CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK      (0xFF0000U)
24091 #define CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT     (16U)
24092 /*! DIVIDE - Divider for observe signal */
24093 #define CCM_OBS_OBSERVE_CONTROL_DIVIDE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK)
24094 
24095 #define CCM_OBS_OBSERVE_CONTROL_OFF_MASK         (0x1000000U)
24096 #define CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT        (24U)
24097 /*! OFF - Turn off
24098  *  0b0..observe slice is on
24099  *  0b1..observe slice is off
24100  */
24101 #define CCM_OBS_OBSERVE_CONTROL_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_OFF_MASK)
24102 /*! @} */
24103 
24104 /* The count of CCM_OBS_OBSERVE_CONTROL */
24105 #define CCM_OBS_OBSERVE_CONTROL_COUNT            (6U)
24106 
24107 /*! @name OBSERVE_CONTROL_SET - Observe control */
24108 /*! @{ */
24109 
24110 #define CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK  (0x1FFU)
24111 #define CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT (0U)
24112 /*! SELECT - Observe signal selector */
24113 #define CCM_OBS_OBSERVE_CONTROL_SET_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK)
24114 
24115 #define CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK     (0x1000U)
24116 #define CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT    (12U)
24117 /*! RAW - Observe raw signal */
24118 #define CCM_OBS_OBSERVE_CONTROL_SET_RAW(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK)
24119 
24120 #define CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK     (0x2000U)
24121 #define CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT    (13U)
24122 /*! INV - Invert */
24123 #define CCM_OBS_OBSERVE_CONTROL_SET_INV(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK)
24124 
24125 #define CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK   (0x8000U)
24126 #define CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT  (15U)
24127 /*! RESET - Reset observe divider */
24128 #define CCM_OBS_OBSERVE_CONTROL_SET_RESET(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK)
24129 
24130 #define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK  (0xFF0000U)
24131 #define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT (16U)
24132 /*! DIVIDE - Divider for observe signal */
24133 #define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK)
24134 
24135 #define CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK     (0x1000000U)
24136 #define CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT    (24U)
24137 /*! OFF - Turn off */
24138 #define CCM_OBS_OBSERVE_CONTROL_SET_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK)
24139 /*! @} */
24140 
24141 /* The count of CCM_OBS_OBSERVE_CONTROL_SET */
24142 #define CCM_OBS_OBSERVE_CONTROL_SET_COUNT        (6U)
24143 
24144 /*! @name OBSERVE_CONTROL_CLR - Observe control */
24145 /*! @{ */
24146 
24147 #define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK  (0x1FFU)
24148 #define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT (0U)
24149 /*! SELECT - Observe signal selector */
24150 #define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK)
24151 
24152 #define CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK     (0x1000U)
24153 #define CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT    (12U)
24154 /*! RAW - Observe raw signal */
24155 #define CCM_OBS_OBSERVE_CONTROL_CLR_RAW(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK)
24156 
24157 #define CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK     (0x2000U)
24158 #define CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT    (13U)
24159 /*! INV - Invert */
24160 #define CCM_OBS_OBSERVE_CONTROL_CLR_INV(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK)
24161 
24162 #define CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK   (0x8000U)
24163 #define CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT  (15U)
24164 /*! RESET - Reset observe divider */
24165 #define CCM_OBS_OBSERVE_CONTROL_CLR_RESET(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK)
24166 
24167 #define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK  (0xFF0000U)
24168 #define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT (16U)
24169 /*! DIVIDE - Divider for observe signal */
24170 #define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK)
24171 
24172 #define CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK     (0x1000000U)
24173 #define CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT    (24U)
24174 /*! OFF - Turn off */
24175 #define CCM_OBS_OBSERVE_CONTROL_CLR_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK)
24176 /*! @} */
24177 
24178 /* The count of CCM_OBS_OBSERVE_CONTROL_CLR */
24179 #define CCM_OBS_OBSERVE_CONTROL_CLR_COUNT        (6U)
24180 
24181 /*! @name OBSERVE_CONTROL_TOG - Observe control */
24182 /*! @{ */
24183 
24184 #define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK  (0x1FFU)
24185 #define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT (0U)
24186 /*! SELECT - Observe signal selector */
24187 #define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK)
24188 
24189 #define CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK     (0x1000U)
24190 #define CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT    (12U)
24191 /*! RAW - Observe raw signal */
24192 #define CCM_OBS_OBSERVE_CONTROL_TOG_RAW(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK)
24193 
24194 #define CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK     (0x2000U)
24195 #define CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT    (13U)
24196 /*! INV - Invert */
24197 #define CCM_OBS_OBSERVE_CONTROL_TOG_INV(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK)
24198 
24199 #define CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK   (0x8000U)
24200 #define CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT  (15U)
24201 /*! RESET - Reset observe divider */
24202 #define CCM_OBS_OBSERVE_CONTROL_TOG_RESET(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK)
24203 
24204 #define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK  (0xFF0000U)
24205 #define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT (16U)
24206 /*! DIVIDE - Divider for observe signal */
24207 #define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK)
24208 
24209 #define CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK     (0x1000000U)
24210 #define CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT    (24U)
24211 /*! OFF - Turn off */
24212 #define CCM_OBS_OBSERVE_CONTROL_TOG_OFF(x)       (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK)
24213 /*! @} */
24214 
24215 /* The count of CCM_OBS_OBSERVE_CONTROL_TOG */
24216 #define CCM_OBS_OBSERVE_CONTROL_TOG_COUNT        (6U)
24217 
24218 /*! @name OBSERVE_STATUS0 - Observe status */
24219 /*! @{ */
24220 
24221 #define CCM_OBS_OBSERVE_STATUS0_SELECT_MASK      (0x1FFU)
24222 #define CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT     (0U)
24223 /*! SELECT - Select value */
24224 #define CCM_OBS_OBSERVE_STATUS0_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_SELECT_MASK)
24225 
24226 #define CCM_OBS_OBSERVE_STATUS0_RAW_MASK         (0x1000U)
24227 #define CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT        (12U)
24228 /*! RAW - Observe raw signal
24229  *  0b0..Divided signal is selected
24230  *  0b1..Raw signal is selected
24231  */
24232 #define CCM_OBS_OBSERVE_STATUS0_RAW(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RAW_MASK)
24233 
24234 #define CCM_OBS_OBSERVE_STATUS0_INV_MASK         (0x2000U)
24235 #define CCM_OBS_OBSERVE_STATUS0_INV_SHIFT        (13U)
24236 /*! INV - Polarity of the observe target
24237  *  0b1..Polarity of the observe target is inverted
24238  *  0b0..Polarity is not inverted
24239  */
24240 #define CCM_OBS_OBSERVE_STATUS0_INV(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_INV_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_INV_MASK)
24241 
24242 #define CCM_OBS_OBSERVE_STATUS0_RESET_MASK       (0x8000U)
24243 #define CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT      (15U)
24244 /*! RESET - Reset state
24245  *  0b1..Observe divider is in reset state
24246  *  0b0..Observe divider is not in reset state
24247  */
24248 #define CCM_OBS_OBSERVE_STATUS0_RESET(x)         (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RESET_MASK)
24249 
24250 #define CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK      (0xFF0000U)
24251 #define CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT     (16U)
24252 /*! DIVIDE - Divide value status. The clock will be divided by DIVIDE + 1. */
24253 #define CCM_OBS_OBSERVE_STATUS0_DIVIDE(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK)
24254 
24255 #define CCM_OBS_OBSERVE_STATUS0_OFF_MASK         (0x1000000U)
24256 #define CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT        (24U)
24257 /*! OFF - Turn off slice
24258  *  0b0..observe slice is on
24259  *  0b1..observe slice is off
24260  */
24261 #define CCM_OBS_OBSERVE_STATUS0_OFF(x)           (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_OFF_MASK)
24262 /*! @} */
24263 
24264 /* The count of CCM_OBS_OBSERVE_STATUS0 */
24265 #define CCM_OBS_OBSERVE_STATUS0_COUNT            (6U)
24266 
24267 /*! @name OBSERVE_AUTHEN - Observe access control */
24268 /*! @{ */
24269 
24270 #define CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK      (0x1U)
24271 #define CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT     (0U)
24272 /*! TZ_USER - User access
24273  *  0b1..Clock can be changed in user mode.
24274  *  0b0..Clock cannot be changed in user mode.
24275  */
24276 #define CCM_OBS_OBSERVE_AUTHEN_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK)
24277 
24278 #define CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK        (0x2U)
24279 #define CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT       (1U)
24280 /*! TZ_NS - Non-secure access
24281  *  0b0..Cannot be changed in Non-secure mode.
24282  *  0b1..Can be changed in Non-secure mode.
24283  */
24284 #define CCM_OBS_OBSERVE_AUTHEN_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK)
24285 
24286 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK      (0x10U)
24287 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT     (4U)
24288 /*! LOCK_TZ - Lock truszone setting
24289  *  0b0..Trustzone setting is not locked.
24290  *  0b1..Trustzone setting is locked.
24291  */
24292 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ(x)        (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK)
24293 
24294 #define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK   (0xF00U)
24295 #define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT  (8U)
24296 /*! WHITE_LIST - White list
24297  *  0b1111..All domain can change.
24298  *  0b0010..Domain 1 can change.
24299  *  0b0011..Domain 0 and domain 1 can change.
24300  *  0b0000..No domain can change.
24301  *  0b0100..Domain 2 can change.
24302  *  0b0001..Domain 0 can change.
24303  */
24304 #define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK)
24305 
24306 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK    (0x1000U)
24307 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT   (12U)
24308 /*! LOCK_LIST - Lock white list
24309  *  0b0..White list is not locked.
24310  *  0b1..White list is locked.
24311  */
24312 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK)
24313 
24314 #define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK  (0x10000U)
24315 #define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT (16U)
24316 /*! DOMAIN_MODE - Low power and access control by domain
24317  *  0b1..Clock works in domain mode.
24318  *  0b0..Clock does not work in domain mode.
24319  */
24320 #define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK)
24321 
24322 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK    (0x100000U)
24323 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT   (20U)
24324 /*! LOCK_MODE - Lock low power and access mode
24325  *  0b0..MODE is not locked.
24326  *  0b1..MODE is locked.
24327  */
24328 #define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK)
24329 /*! @} */
24330 
24331 /* The count of CCM_OBS_OBSERVE_AUTHEN */
24332 #define CCM_OBS_OBSERVE_AUTHEN_COUNT             (6U)
24333 
24334 /*! @name OBSERVE_AUTHEN_SET - Observe access control */
24335 /*! @{ */
24336 
24337 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK  (0x1U)
24338 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT (0U)
24339 /*! TZ_USER - User access */
24340 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK)
24341 
24342 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK    (0x2U)
24343 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT   (1U)
24344 /*! TZ_NS - Non-secure access */
24345 #define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK)
24346 
24347 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK  (0x10U)
24348 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
24349 /*! LOCK_TZ - Lock truszone setting */
24350 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK)
24351 
24352 #define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
24353 #define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
24354 /*! WHITE_LIST - White list */
24355 #define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK)
24356 
24357 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
24358 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
24359 /*! LOCK_LIST - Lock white list */
24360 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK)
24361 
24362 #define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
24363 #define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
24364 /*! DOMAIN_MODE - Low power and access control by domain */
24365 #define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK)
24366 
24367 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
24368 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
24369 /*! LOCK_MODE - Lock low power and access mode */
24370 #define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK)
24371 /*! @} */
24372 
24373 /* The count of CCM_OBS_OBSERVE_AUTHEN_SET */
24374 #define CCM_OBS_OBSERVE_AUTHEN_SET_COUNT         (6U)
24375 
24376 /*! @name OBSERVE_AUTHEN_CLR - Observe access control */
24377 /*! @{ */
24378 
24379 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK  (0x1U)
24380 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT (0U)
24381 /*! TZ_USER - User access */
24382 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK)
24383 
24384 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK    (0x2U)
24385 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT   (1U)
24386 /*! TZ_NS - Non-secure access */
24387 #define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK)
24388 
24389 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK  (0x10U)
24390 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
24391 /*! LOCK_TZ - Lock truszone setting */
24392 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK)
24393 
24394 #define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
24395 #define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
24396 /*! WHITE_LIST - White list */
24397 #define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK)
24398 
24399 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
24400 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
24401 /*! LOCK_LIST - Lock white list */
24402 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK)
24403 
24404 #define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
24405 #define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
24406 /*! DOMAIN_MODE - Low power and access control by domain */
24407 #define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK)
24408 
24409 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
24410 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
24411 /*! LOCK_MODE - Lock low power and access mode */
24412 #define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK)
24413 /*! @} */
24414 
24415 /* The count of CCM_OBS_OBSERVE_AUTHEN_CLR */
24416 #define CCM_OBS_OBSERVE_AUTHEN_CLR_COUNT         (6U)
24417 
24418 /*! @name OBSERVE_AUTHEN_TOG - Observe access control */
24419 /*! @{ */
24420 
24421 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK  (0x1U)
24422 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT (0U)
24423 /*! TZ_USER - User access */
24424 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK)
24425 
24426 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK    (0x2U)
24427 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT   (1U)
24428 /*! TZ_NS - Non-secure access */
24429 #define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS(x)      (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK)
24430 
24431 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK  (0x10U)
24432 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
24433 /*! LOCK_TZ - Lock truszone setting */
24434 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ(x)    (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK)
24435 
24436 #define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
24437 #define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
24438 /*! WHITE_LIST - White list */
24439 #define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK)
24440 
24441 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
24442 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
24443 /*! LOCK_LIST - Lock white list */
24444 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK)
24445 
24446 #define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
24447 #define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
24448 /*! DOMAIN_MODE - Low power and access control by domain */
24449 #define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK)
24450 
24451 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
24452 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
24453 /*! LOCK_MODE - Lock low power and access mode */
24454 #define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE(x)  (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK)
24455 /*! @} */
24456 
24457 /* The count of CCM_OBS_OBSERVE_AUTHEN_TOG */
24458 #define CCM_OBS_OBSERVE_AUTHEN_TOG_COUNT         (6U)
24459 
24460 /*! @name OBSERVE_FREQUENCY_CURRENT - Current frequency detected */
24461 /*! @{ */
24462 
24463 #define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK (0xFFFFFFFFU)
24464 #define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT (0U)
24465 /*! FREQUENCY - Frequency */
24466 #define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK)
24467 /*! @} */
24468 
24469 /* The count of CCM_OBS_OBSERVE_FREQUENCY_CURRENT */
24470 #define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_COUNT  (6U)
24471 
24472 /*! @name OBSERVE_FREQUENCY_MIN - Minimum frequency detected */
24473 /*! @{ */
24474 
24475 #define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK (0xFFFFFFFFU)
24476 #define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT (0U)
24477 /*! FREQUENCY - Frequency */
24478 #define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK)
24479 /*! @} */
24480 
24481 /* The count of CCM_OBS_OBSERVE_FREQUENCY_MIN */
24482 #define CCM_OBS_OBSERVE_FREQUENCY_MIN_COUNT      (6U)
24483 
24484 /*! @name OBSERVE_FREQUENCY_MAX - Maximum frequency detected */
24485 /*! @{ */
24486 
24487 #define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK (0xFFFFFFFFU)
24488 #define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT (0U)
24489 /*! FREQUENCY - Frequency */
24490 #define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK)
24491 /*! @} */
24492 
24493 /* The count of CCM_OBS_OBSERVE_FREQUENCY_MAX */
24494 #define CCM_OBS_OBSERVE_FREQUENCY_MAX_COUNT      (6U)
24495 
24496 
24497 /*!
24498  * @}
24499  */ /* end of group CCM_OBS_Register_Masks */
24500 
24501 
24502 /* CCM_OBS - Peripheral instance base addresses */
24503 /** Peripheral CCM_OBS base address */
24504 #define CCM_OBS_BASE                             (0x40150000u)
24505 /** Peripheral CCM_OBS base pointer */
24506 #define CCM_OBS                                  ((CCM_OBS_Type *)CCM_OBS_BASE)
24507 /** Array initializer of CCM_OBS peripheral base addresses */
24508 #define CCM_OBS_BASE_ADDRS                       { CCM_OBS_BASE }
24509 /** Array initializer of CCM_OBS peripheral base pointers */
24510 #define CCM_OBS_BASE_PTRS                        { CCM_OBS }
24511 
24512 /*!
24513  * @}
24514  */ /* end of group CCM_OBS_Peripheral_Access_Layer */
24515 
24516 
24517 /* ----------------------------------------------------------------------------
24518    -- CDOG Peripheral Access Layer
24519    ---------------------------------------------------------------------------- */
24520 
24521 /*!
24522  * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer
24523  * @{
24524  */
24525 
24526 /** CDOG - Register Layout Typedef */
24527 typedef struct {
24528   __IO uint32_t CONTROL;                           /**< Control, offset: 0x0 */
24529   __IO uint32_t RELOAD;                            /**< Instruction Timer reload, offset: 0x4 */
24530   __IO uint32_t INSTRUCTION_TIMER;                 /**< Instruction Timer, offset: 0x8 */
24531   __O  uint32_t SECURE_COUNTER;                    /**< Secure Counter, offset: 0xC */
24532   __I  uint32_t STATUS;                            /**< Status 1, offset: 0x10 */
24533   __I  uint32_t STATUS2;                           /**< Status 2, offset: 0x14 */
24534   __IO uint32_t FLAGS;                             /**< Flags, offset: 0x18 */
24535   __IO uint32_t PERSISTENT;                        /**< Persistent Data Storage, offset: 0x1C */
24536   __O  uint32_t START;                             /**< START Command, offset: 0x20 */
24537   __O  uint32_t STOP;                              /**< STOP Command, offset: 0x24 */
24538   __O  uint32_t RESTART;                           /**< RESTART Command, offset: 0x28 */
24539   __O  uint32_t ADD;                               /**< ADD Command, offset: 0x2C */
24540   __O  uint32_t ADD1;                              /**< ADD1 Command, offset: 0x30 */
24541   __O  uint32_t ADD16;                             /**< ADD16 Command, offset: 0x34 */
24542   __O  uint32_t ADD256;                            /**< ADD256 Command, offset: 0x38 */
24543   __O  uint32_t SUB;                               /**< SUB Command, offset: 0x3C */
24544   __O  uint32_t SUB1;                              /**< SUB1 Command, offset: 0x40 */
24545   __O  uint32_t SUB16;                             /**< SUB16 Command, offset: 0x44 */
24546   __O  uint32_t SUB256;                            /**< SUB256 Command, offset: 0x48 */
24547 } CDOG_Type;
24548 
24549 /* ----------------------------------------------------------------------------
24550    -- CDOG Register Masks
24551    ---------------------------------------------------------------------------- */
24552 
24553 /*!
24554  * @addtogroup CDOG_Register_Masks CDOG Register Masks
24555  * @{
24556  */
24557 
24558 /*! @name CONTROL - Control */
24559 /*! @{ */
24560 
24561 #define CDOG_CONTROL_LOCK_CTRL_MASK              (0x3U)
24562 #define CDOG_CONTROL_LOCK_CTRL_SHIFT             (0U)
24563 /*! LOCK_CTRL - Lock control
24564  *  0b01..Locked
24565  *  0b10..Unlocked
24566  */
24567 #define CDOG_CONTROL_LOCK_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK)
24568 
24569 #define CDOG_CONTROL_TIMEOUT_CTRL_MASK           (0x1CU)
24570 #define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT          (2U)
24571 /*! TIMEOUT_CTRL - TIMEOUT fault control
24572  *  0b100..Disable both reset and interrupt
24573  *  0b001..Enable reset
24574  *  0b010..Enable interrupt
24575  */
24576 #define CDOG_CONTROL_TIMEOUT_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK)
24577 
24578 #define CDOG_CONTROL_MISCOMPARE_CTRL_MASK        (0xE0U)
24579 #define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT       (5U)
24580 /*! MISCOMPARE_CTRL - MISCOMPARE fault control
24581  *  0b100..Disable both reset and interrupt
24582  *  0b001..Enable reset
24583  *  0b010..Enable interrupt
24584  */
24585 #define CDOG_CONTROL_MISCOMPARE_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK)
24586 
24587 #define CDOG_CONTROL_SEQUENCE_CTRL_MASK          (0x700U)
24588 #define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT         (8U)
24589 /*! SEQUENCE_CTRL - SEQUENCE fault control
24590  *  0b001..Enable reset
24591  *  0b010..Enable interrupt
24592  *  0b100..Disable both reset and interrupt
24593  */
24594 #define CDOG_CONTROL_SEQUENCE_CTRL(x)            (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK)
24595 
24596 #define CDOG_CONTROL_CONTROL_CTRL_MASK           (0x3800U)
24597 #define CDOG_CONTROL_CONTROL_CTRL_SHIFT          (11U)
24598 /*! CONTROL_CTRL - CONTROL fault control
24599  *  0b001..Enable reset
24600  *  0b100..Disable reset
24601  */
24602 #define CDOG_CONTROL_CONTROL_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_CONTROL_CTRL_SHIFT)) & CDOG_CONTROL_CONTROL_CTRL_MASK)
24603 
24604 #define CDOG_CONTROL_STATE_CTRL_MASK             (0x1C000U)
24605 #define CDOG_CONTROL_STATE_CTRL_SHIFT            (14U)
24606 /*! STATE_CTRL - STATE fault control
24607  *  0b001..Enable reset
24608  *  0b010..Enable interrupt
24609  *  0b100..Disable both reset and interrupt
24610  */
24611 #define CDOG_CONTROL_STATE_CTRL(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK)
24612 
24613 #define CDOG_CONTROL_ADDRESS_CTRL_MASK           (0xE0000U)
24614 #define CDOG_CONTROL_ADDRESS_CTRL_SHIFT          (17U)
24615 /*! ADDRESS_CTRL - ADDRESS fault control
24616  *  0b001..Enable reset
24617  *  0b010..Enable interrupt
24618  *  0b100..Disable both reset and interrupt
24619  */
24620 #define CDOG_CONTROL_ADDRESS_CTRL(x)             (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK)
24621 
24622 #define CDOG_CONTROL_IRQ_PAUSE_MASK              (0x30000000U)
24623 #define CDOG_CONTROL_IRQ_PAUSE_SHIFT             (28U)
24624 /*! IRQ_PAUSE - IRQ pause control
24625  *  0b01..Keep the timer running
24626  *  0b10..Stop the timer
24627  */
24628 #define CDOG_CONTROL_IRQ_PAUSE(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK)
24629 
24630 #define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK        (0xC0000000U)
24631 #define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT       (30U)
24632 /*! DEBUG_HALT_CTRL - DEBUG_HALT control
24633  *  0b01..Keep the timer running
24634  *  0b10..Stop the timer
24635  */
24636 #define CDOG_CONTROL_DEBUG_HALT_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK)
24637 /*! @} */
24638 
24639 /*! @name RELOAD - Instruction Timer reload */
24640 /*! @{ */
24641 
24642 #define CDOG_RELOAD_RLOAD_MASK                   (0xFFFFFFFFU)
24643 #define CDOG_RELOAD_RLOAD_SHIFT                  (0U)
24644 /*! RLOAD - Instruction Timer reload value */
24645 #define CDOG_RELOAD_RLOAD(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK)
24646 /*! @} */
24647 
24648 /*! @name INSTRUCTION_TIMER - Instruction Timer */
24649 /*! @{ */
24650 
24651 #define CDOG_INSTRUCTION_TIMER_INSTIM_MASK       (0xFFFFFFFFU)
24652 #define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT      (0U)
24653 /*! INSTIM - Current value of the Instruction Timer */
24654 #define CDOG_INSTRUCTION_TIMER_INSTIM(x)         (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK)
24655 /*! @} */
24656 
24657 /*! @name SECURE_COUNTER - Secure Counter */
24658 /*! @{ */
24659 
24660 #define CDOG_SECURE_COUNTER_SECCNT_MASK          (0xFFFFFFFFU)
24661 #define CDOG_SECURE_COUNTER_SECCNT_SHIFT         (0U)
24662 /*! SECCNT - Secure Counter */
24663 #define CDOG_SECURE_COUNTER_SECCNT(x)            (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK)
24664 /*! @} */
24665 
24666 /*! @name STATUS - Status 1 */
24667 /*! @{ */
24668 
24669 #define CDOG_STATUS_NUMTOF_MASK                  (0xFFU)
24670 #define CDOG_STATUS_NUMTOF_SHIFT                 (0U)
24671 /*! NUMTOF - Number of TIMEOUT faults since the last POR */
24672 #define CDOG_STATUS_NUMTOF(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK)
24673 
24674 #define CDOG_STATUS_NUMMISCOMPF_MASK             (0xFF00U)
24675 #define CDOG_STATUS_NUMMISCOMPF_SHIFT            (8U)
24676 /*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR */
24677 #define CDOG_STATUS_NUMMISCOMPF(x)               (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK)
24678 
24679 #define CDOG_STATUS_NUMILSEQF_MASK               (0xFF0000U)
24680 #define CDOG_STATUS_NUMILSEQF_SHIFT              (16U)
24681 /*! NUMILSEQF - Number of SEQUENCE faults since the last POR */
24682 #define CDOG_STATUS_NUMILSEQF(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK)
24683 
24684 #define CDOG_STATUS_CURST_MASK                   (0xF0000000U)
24685 #define CDOG_STATUS_CURST_SHIFT                  (28U)
24686 /*! CURST - Current State */
24687 #define CDOG_STATUS_CURST(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK)
24688 /*! @} */
24689 
24690 /*! @name STATUS2 - Status 2 */
24691 /*! @{ */
24692 
24693 #define CDOG_STATUS2_NUMCNTF_MASK                (0xFFU)
24694 #define CDOG_STATUS2_NUMCNTF_SHIFT               (0U)
24695 /*! NUMCNTF - Number of CONTROL faults since the last POR */
24696 #define CDOG_STATUS2_NUMCNTF(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK)
24697 
24698 #define CDOG_STATUS2_NUMILLSTF_MASK              (0xFF00U)
24699 #define CDOG_STATUS2_NUMILLSTF_SHIFT             (8U)
24700 /*! NUMILLSTF - Number of STATE faults since the last POR */
24701 #define CDOG_STATUS2_NUMILLSTF(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK)
24702 
24703 #define CDOG_STATUS2_NUMILLA_MASK                (0xFF0000U)
24704 #define CDOG_STATUS2_NUMILLA_SHIFT               (16U)
24705 /*! NUMILLA - Number of ADDRESS faults since the last POR */
24706 #define CDOG_STATUS2_NUMILLA(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK)
24707 /*! @} */
24708 
24709 /*! @name FLAGS - Flags */
24710 /*! @{ */
24711 
24712 #define CDOG_FLAGS_TO_FLAG_MASK                  (0x1U)
24713 #define CDOG_FLAGS_TO_FLAG_SHIFT                 (0U)
24714 /*! TO_FLAG - TIMEOUT fault flag
24715  *  0b0..A TIMEOUT fault has not occurred
24716  *  0b1..A TIMEOUT fault has occurred
24717  */
24718 #define CDOG_FLAGS_TO_FLAG(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK)
24719 
24720 #define CDOG_FLAGS_MISCOM_FLAG_MASK              (0x2U)
24721 #define CDOG_FLAGS_MISCOM_FLAG_SHIFT             (1U)
24722 /*! MISCOM_FLAG - MISCOMPARE fault flag
24723  *  0b0..A MISCOMPARE fault has not occurred
24724  *  0b1..A MISCOMPARE fault has occurred
24725  */
24726 #define CDOG_FLAGS_MISCOM_FLAG(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK)
24727 
24728 #define CDOG_FLAGS_SEQ_FLAG_MASK                 (0x4U)
24729 #define CDOG_FLAGS_SEQ_FLAG_SHIFT                (2U)
24730 /*! SEQ_FLAG - SEQUENCE fault flag
24731  *  0b0..A SEQUENCE fault has not occurred
24732  *  0b1..A SEQUENCE fault has occurred
24733  */
24734 #define CDOG_FLAGS_SEQ_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK)
24735 
24736 #define CDOG_FLAGS_CNT_FLAG_MASK                 (0x8U)
24737 #define CDOG_FLAGS_CNT_FLAG_SHIFT                (3U)
24738 /*! CNT_FLAG - CONTROL fault flag
24739  *  0b0..A CONTROL fault has not occurred
24740  *  0b1..A CONTROL fault has occurred
24741  */
24742 #define CDOG_FLAGS_CNT_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK)
24743 
24744 #define CDOG_FLAGS_STATE_FLAG_MASK               (0x10U)
24745 #define CDOG_FLAGS_STATE_FLAG_SHIFT              (4U)
24746 /*! STATE_FLAG - STATE fault flag
24747  *  0b0..A STATE fault has not occurred
24748  *  0b1..A STATE fault has occurred
24749  */
24750 #define CDOG_FLAGS_STATE_FLAG(x)                 (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK)
24751 
24752 #define CDOG_FLAGS_ADDR_FLAG_MASK                (0x20U)
24753 #define CDOG_FLAGS_ADDR_FLAG_SHIFT               (5U)
24754 /*! ADDR_FLAG - ADDRESS fault flag
24755  *  0b0..An ADDRESS fault has not occurred
24756  *  0b1..An ADDRESS fault has occurred
24757  */
24758 #define CDOG_FLAGS_ADDR_FLAG(x)                  (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK)
24759 
24760 #define CDOG_FLAGS_POR_FLAG_MASK                 (0x10000U)
24761 #define CDOG_FLAGS_POR_FLAG_SHIFT                (16U)
24762 /*! POR_FLAG - Power-on reset flag
24763  *  0b0..A Power-on reset event has not occurred
24764  *  0b1..A Power-on reset event has occurred
24765  */
24766 #define CDOG_FLAGS_POR_FLAG(x)                   (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK)
24767 /*! @} */
24768 
24769 /*! @name PERSISTENT - Persistent Data Storage */
24770 /*! @{ */
24771 
24772 #define CDOG_PERSISTENT_PERSIS_MASK              (0xFFFFFFFFU)
24773 #define CDOG_PERSISTENT_PERSIS_SHIFT             (0U)
24774 /*! PERSIS - Persistent Storage */
24775 #define CDOG_PERSISTENT_PERSIS(x)                (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK)
24776 /*! @} */
24777 
24778 /*! @name START - START Command */
24779 /*! @{ */
24780 
24781 #define CDOG_START_STRT_MASK                     (0xFFFFFFFFU)
24782 #define CDOG_START_STRT_SHIFT                    (0U)
24783 /*! STRT - Start command */
24784 #define CDOG_START_STRT(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK)
24785 /*! @} */
24786 
24787 /*! @name STOP - STOP Command */
24788 /*! @{ */
24789 
24790 #define CDOG_STOP_STP_MASK                       (0xFFFFFFFFU)
24791 #define CDOG_STOP_STP_SHIFT                      (0U)
24792 /*! STP - Stop command */
24793 #define CDOG_STOP_STP(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK)
24794 /*! @} */
24795 
24796 /*! @name RESTART - RESTART Command */
24797 /*! @{ */
24798 
24799 #define CDOG_RESTART_RSTRT_MASK                  (0xFFFFFFFFU)
24800 #define CDOG_RESTART_RSTRT_SHIFT                 (0U)
24801 /*! RSTRT - Restart command */
24802 #define CDOG_RESTART_RSTRT(x)                    (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK)
24803 /*! @} */
24804 
24805 /*! @name ADD - ADD Command */
24806 /*! @{ */
24807 
24808 #define CDOG_ADD_AD_MASK                         (0xFFFFFFFFU)
24809 #define CDOG_ADD_AD_SHIFT                        (0U)
24810 /*! AD - ADD Write Value */
24811 #define CDOG_ADD_AD(x)                           (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK)
24812 /*! @} */
24813 
24814 /*! @name ADD1 - ADD1 Command */
24815 /*! @{ */
24816 
24817 #define CDOG_ADD1_AD1_MASK                       (0xFFFFFFFFU)
24818 #define CDOG_ADD1_AD1_SHIFT                      (0U)
24819 /*! AD1 - ADD 1 */
24820 #define CDOG_ADD1_AD1(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK)
24821 /*! @} */
24822 
24823 /*! @name ADD16 - ADD16 Command */
24824 /*! @{ */
24825 
24826 #define CDOG_ADD16_AD16_MASK                     (0xFFFFFFFFU)
24827 #define CDOG_ADD16_AD16_SHIFT                    (0U)
24828 /*! AD16 - ADD 16 */
24829 #define CDOG_ADD16_AD16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK)
24830 /*! @} */
24831 
24832 /*! @name ADD256 - ADD256 Command */
24833 /*! @{ */
24834 
24835 #define CDOG_ADD256_AD256_MASK                   (0xFFFFFFFFU)
24836 #define CDOG_ADD256_AD256_SHIFT                  (0U)
24837 /*! AD256 - ADD 256 */
24838 #define CDOG_ADD256_AD256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK)
24839 /*! @} */
24840 
24841 /*! @name SUB - SUB Command */
24842 /*! @{ */
24843 
24844 #define CDOG_SUB_S0B_MASK                        (0xFFFFFFFFU)
24845 #define CDOG_SUB_S0B_SHIFT                       (0U)
24846 /*! S0B - Subtract Write Value */
24847 #define CDOG_SUB_S0B(x)                          (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
24848 /*! @} */
24849 
24850 /*! @name SUB1 - SUB1 Command */
24851 /*! @{ */
24852 
24853 #define CDOG_SUB1_S1B_MASK                       (0xFFFFFFFFU)
24854 #define CDOG_SUB1_S1B_SHIFT                      (0U)
24855 /*! S1B - Subtract 1 */
24856 #define CDOG_SUB1_S1B(x)                         (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK)
24857 /*! @} */
24858 
24859 /*! @name SUB16 - SUB16 Command */
24860 /*! @{ */
24861 
24862 #define CDOG_SUB16_SB16_MASK                     (0xFFFFFFFFU)
24863 #define CDOG_SUB16_SB16_SHIFT                    (0U)
24864 /*! SB16 - Subtract 16 */
24865 #define CDOG_SUB16_SB16(x)                       (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK)
24866 /*! @} */
24867 
24868 /*! @name SUB256 - SUB256 Command */
24869 /*! @{ */
24870 
24871 #define CDOG_SUB256_SB256_MASK                   (0xFFFFFFFFU)
24872 #define CDOG_SUB256_SB256_SHIFT                  (0U)
24873 /*! SB256 - Subtract 256 */
24874 #define CDOG_SUB256_SB256(x)                     (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK)
24875 /*! @} */
24876 
24877 
24878 /*!
24879  * @}
24880  */ /* end of group CDOG_Register_Masks */
24881 
24882 
24883 /* CDOG - Peripheral instance base addresses */
24884 /** Peripheral CDOG base address */
24885 #define CDOG_BASE                                (0x41900000u)
24886 /** Peripheral CDOG base pointer */
24887 #define CDOG                                     ((CDOG_Type *)CDOG_BASE)
24888 /** Array initializer of CDOG peripheral base addresses */
24889 #define CDOG_BASE_ADDRS                          { CDOG_BASE }
24890 /** Array initializer of CDOG peripheral base pointers */
24891 #define CDOG_BASE_PTRS                           { CDOG }
24892 /** Interrupt vectors for the CDOG peripheral type */
24893 #define CDOG_IRQS                                { CDOG_IRQn }
24894 
24895 /*!
24896  * @}
24897  */ /* end of group CDOG_Peripheral_Access_Layer */
24898 
24899 
24900 /* ----------------------------------------------------------------------------
24901    -- CMP Peripheral Access Layer
24902    ---------------------------------------------------------------------------- */
24903 
24904 /*!
24905  * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
24906  * @{
24907  */
24908 
24909 /** CMP - Register Layout Typedef */
24910 typedef struct {
24911   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
24912   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
24913   __IO uint32_t C0;                                /**< CMP Control Register 0, offset: 0x8 */
24914   __IO uint32_t C1;                                /**< CMP Control Register 1, offset: 0xC */
24915   __IO uint32_t C2;                                /**< CMP Control Register 2, offset: 0x10 */
24916   __IO uint32_t C3;                                /**< CMP Control Register 3, offset: 0x14 */
24917 } CMP_Type;
24918 
24919 /* ----------------------------------------------------------------------------
24920    -- CMP Register Masks
24921    ---------------------------------------------------------------------------- */
24922 
24923 /*!
24924  * @addtogroup CMP_Register_Masks CMP Register Masks
24925  * @{
24926  */
24927 
24928 /*! @name VERID - Version ID Register */
24929 /*! @{ */
24930 
24931 #define CMP_VERID_FEATURE_MASK                   (0xFFFFU)
24932 #define CMP_VERID_FEATURE_SHIFT                  (0U)
24933 /*! FEATURE - Feature Specification Number. This read only filed returns the feature set number. */
24934 #define CMP_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)
24935 
24936 #define CMP_VERID_MINOR_MASK                     (0xFF0000U)
24937 #define CMP_VERID_MINOR_SHIFT                    (16U)
24938 /*! MINOR - Minor Version Number. This read only field returns the minor version number for the module specification. */
24939 #define CMP_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)
24940 
24941 #define CMP_VERID_MAJOR_MASK                     (0xFF000000U)
24942 #define CMP_VERID_MAJOR_SHIFT                    (24U)
24943 /*! MAJOR - Major Version Number. This read only field returns the major version number for the module specification. */
24944 #define CMP_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)
24945 /*! @} */
24946 
24947 /*! @name PARAM - Parameter Register */
24948 /*! @{ */
24949 
24950 #define CMP_PARAM_PARAM_MASK                     (0xFFFFFFFFU)
24951 #define CMP_PARAM_PARAM_SHIFT                    (0U)
24952 /*! PARAM - Parameter Registers. This read only filed returns the feature parameters implemented along with the Version ID register. */
24953 #define CMP_PARAM_PARAM(x)                       (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)
24954 /*! @} */
24955 
24956 /*! @name C0 - CMP Control Register 0 */
24957 /*! @{ */
24958 
24959 #define CMP_C0_HYSTCTR_MASK                      (0x3U)
24960 #define CMP_C0_HYSTCTR_SHIFT                     (0U)
24961 /*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level
24962  *  0b00..The hard block output has level 0 hysteresis internally.
24963  *  0b01..The hard block output has level 1 hysteresis internally.
24964  *  0b10..The hard block output has level 2 hysteresis internally.
24965  *  0b11..The hard block output has level 3 hysteresis internally.
24966  */
24967 #define CMP_C0_HYSTCTR(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK)
24968 
24969 #define CMP_C0_FILTER_CNT_MASK                   (0x70U)
24970 #define CMP_C0_FILTER_CNT_SHIFT                  (4U)
24971 /*! FILTER_CNT - Filter Sample Count
24972  *  0b000..Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA.
24973  *  0b001..1 consecutive sample must agree (comparator output is simply sampled).
24974  *  0b010..2 consecutive samples must agree.
24975  *  0b011..3 consecutive samples must agree.
24976  *  0b100..4 consecutive samples must agree.
24977  *  0b101..5 consecutive samples must agree.
24978  *  0b110..6 consecutive samples must agree.
24979  *  0b111..7 consecutive samples must agree.
24980  */
24981 #define CMP_C0_FILTER_CNT(x)                     (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK)
24982 
24983 #define CMP_C0_EN_MASK                           (0x100U)
24984 #define CMP_C0_EN_SHIFT                          (8U)
24985 /*! EN - Comparator Module Enable
24986  *  0b0..Analog Comparator is disabled.
24987  *  0b1..Analog Comparator is enabled.
24988  */
24989 #define CMP_C0_EN(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK)
24990 
24991 #define CMP_C0_OPE_MASK                          (0x200U)
24992 #define CMP_C0_OPE_SHIFT                         (9U)
24993 /*! OPE - Comparator Output Pin Enable
24994  *  0b0..When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin.
24995  *  0b1..When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin.
24996  */
24997 #define CMP_C0_OPE(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK)
24998 
24999 #define CMP_C0_COS_MASK                          (0x400U)
25000 #define CMP_C0_COS_SHIFT                         (10U)
25001 /*! COS - Comparator Output Select
25002  *  0b0..Set CMPO to equal COUT (filtered comparator output).
25003  *  0b1..Set CMPO to equal COUTA (unfiltered comparator output).
25004  */
25005 #define CMP_C0_COS(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK)
25006 
25007 #define CMP_C0_INVT_MASK                         (0x800U)
25008 #define CMP_C0_INVT_SHIFT                        (11U)
25009 /*! INVT - Comparator invert
25010  *  0b0..Does not invert the comparator output.
25011  *  0b1..Inverts the comparator output.
25012  */
25013 #define CMP_C0_INVT(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK)
25014 
25015 #define CMP_C0_PMODE_MASK                        (0x1000U)
25016 #define CMP_C0_PMODE_SHIFT                       (12U)
25017 /*! PMODE - Power Mode Select
25018  *  0b0..Low Speed (LS) comparison mode is selected.
25019  *  0b1..High Speed (HS) comparison mode is selected.
25020  */
25021 #define CMP_C0_PMODE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK)
25022 
25023 #define CMP_C0_WE_MASK                           (0x4000U)
25024 #define CMP_C0_WE_SHIFT                          (14U)
25025 /*! WE - Windowing Enable
25026  *  0b0..Windowing mode is not selected.
25027  *  0b1..Windowing mode is selected.
25028  */
25029 #define CMP_C0_WE(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK)
25030 
25031 #define CMP_C0_SE_MASK                           (0x8000U)
25032 #define CMP_C0_SE_SHIFT                          (15U)
25033 /*! SE - Sample Enable
25034  *  0b0..Sampling mode is not selected.
25035  *  0b1..Sampling mode is selected.
25036  */
25037 #define CMP_C0_SE(x)                             (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK)
25038 
25039 #define CMP_C0_FPR_MASK                          (0xFF0000U)
25040 #define CMP_C0_FPR_SHIFT                         (16U)
25041 /*! FPR - Filter Sample Period */
25042 #define CMP_C0_FPR(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK)
25043 
25044 #define CMP_C0_COUT_MASK                         (0x1000000U)
25045 #define CMP_C0_COUT_SHIFT                        (24U)
25046 /*! COUT - Analog Comparator Output */
25047 #define CMP_C0_COUT(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK)
25048 
25049 #define CMP_C0_CFF_MASK                          (0x2000000U)
25050 #define CMP_C0_CFF_SHIFT                         (25U)
25051 /*! CFF - Analog Comparator Flag Falling
25052  *  0b0..A falling edge has not been detected on COUT.
25053  *  0b1..A falling edge on COUT has occurred.
25054  */
25055 #define CMP_C0_CFF(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK)
25056 
25057 #define CMP_C0_CFR_MASK                          (0x4000000U)
25058 #define CMP_C0_CFR_SHIFT                         (26U)
25059 /*! CFR - Analog Comparator Flag Rising
25060  *  0b0..A rising edge has not been detected on COUT.
25061  *  0b1..A rising edge on COUT has occurred.
25062  */
25063 #define CMP_C0_CFR(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
25064 
25065 #define CMP_C0_IEF_MASK                          (0x8000000U)
25066 #define CMP_C0_IEF_SHIFT                         (27U)
25067 /*! IEF - Comparator Interrupt Enable Falling
25068  *  0b0..Interrupt is disabled.
25069  *  0b1..Interrupt is enabled.
25070  */
25071 #define CMP_C0_IEF(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK)
25072 
25073 #define CMP_C0_IER_MASK                          (0x10000000U)
25074 #define CMP_C0_IER_SHIFT                         (28U)
25075 /*! IER - Comparator Interrupt Enable Rising
25076  *  0b0..Interrupt is disabled.
25077  *  0b1..Interrupt is enabled.
25078  */
25079 #define CMP_C0_IER(x)                            (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK)
25080 
25081 #define CMP_C0_DMAEN_MASK                        (0x40000000U)
25082 #define CMP_C0_DMAEN_SHIFT                       (30U)
25083 /*! DMAEN - DMA Enable
25084  *  0b0..DMA is disabled.
25085  *  0b1..DMA is enabled.
25086  */
25087 #define CMP_C0_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK)
25088 
25089 #define CMP_C0_LINKEN_MASK                       (0x80000000U)
25090 #define CMP_C0_LINKEN_SHIFT                      (31U)
25091 /*! LINKEN - CMP to DAC link enable.
25092  *  0b0..CMP to DAC link is disabled
25093  *  0b1..CMP to DAC link is enabled.
25094  */
25095 #define CMP_C0_LINKEN(x)                         (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK)
25096 /*! @} */
25097 
25098 /*! @name C1 - CMP Control Register 1 */
25099 /*! @{ */
25100 
25101 #define CMP_C1_VOSEL_MASK                        (0xFFU)
25102 #define CMP_C1_VOSEL_SHIFT                       (0U)
25103 /*! VOSEL - DAC Output Voltage Select */
25104 #define CMP_C1_VOSEL(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK)
25105 
25106 #define CMP_C1_DMODE_MASK                        (0x100U)
25107 #define CMP_C1_DMODE_SHIFT                       (8U)
25108 /*! DMODE - DAC Mode Selection
25109  *  0b0..DAC is selected to work in low speed and low power mode.
25110  *  0b1..DAC is selected to work in high speed high power mode.
25111  */
25112 #define CMP_C1_DMODE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK)
25113 
25114 #define CMP_C1_VRSEL_MASK                        (0x200U)
25115 #define CMP_C1_VRSEL_SHIFT                       (9U)
25116 /*! VRSEL - Supply Voltage Reference Source Select
25117  *  0b0..Vin1 is selected as resistor ladder network supply reference Vin. Vin1 is from internal PMC.
25118  *  0b1..Vin2 is selected as resistor ladder network supply reference Vin. Vin2 is from PAD.
25119  */
25120 #define CMP_C1_VRSEL(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK)
25121 
25122 #define CMP_C1_DACEN_MASK                        (0x400U)
25123 #define CMP_C1_DACEN_SHIFT                       (10U)
25124 /*! DACEN - DAC Enable
25125  *  0b0..DAC is disabled.
25126  *  0b1..DAC is enabled.
25127  */
25128 #define CMP_C1_DACEN(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK)
25129 
25130 #define CMP_C1_CHN0_MASK                         (0x10000U)
25131 #define CMP_C1_CHN0_SHIFT                        (16U)
25132 /*! CHN0 - Channel 0 input enable */
25133 #define CMP_C1_CHN0(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK)
25134 
25135 #define CMP_C1_CHN1_MASK                         (0x20000U)
25136 #define CMP_C1_CHN1_SHIFT                        (17U)
25137 /*! CHN1 - Channel 1 input enable */
25138 #define CMP_C1_CHN1(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK)
25139 
25140 #define CMP_C1_CHN2_MASK                         (0x40000U)
25141 #define CMP_C1_CHN2_SHIFT                        (18U)
25142 /*! CHN2 - Channel 2 input enable */
25143 #define CMP_C1_CHN2(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK)
25144 
25145 #define CMP_C1_CHN3_MASK                         (0x80000U)
25146 #define CMP_C1_CHN3_SHIFT                        (19U)
25147 /*! CHN3 - Channel 3 input enable */
25148 #define CMP_C1_CHN3(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK)
25149 
25150 #define CMP_C1_CHN4_MASK                         (0x100000U)
25151 #define CMP_C1_CHN4_SHIFT                        (20U)
25152 /*! CHN4 - Channel 4 input enable */
25153 #define CMP_C1_CHN4(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK)
25154 
25155 #define CMP_C1_CHN5_MASK                         (0x200000U)
25156 #define CMP_C1_CHN5_SHIFT                        (21U)
25157 /*! CHN5 - Channel 5 input enable */
25158 #define CMP_C1_CHN5(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK)
25159 
25160 #define CMP_C1_MSEL_MASK                         (0x7000000U)
25161 #define CMP_C1_MSEL_SHIFT                        (24U)
25162 /*! MSEL - Minus Input MUX Control
25163  *  0b000..Internal Negative Input 0 for Minus Channel -- Internal Minus Input
25164  *  0b001..External Input 1 for Minus Channel -- Reference Input 0
25165  *  0b010..External Input 2 for Minus Channel -- Reference Input 1
25166  *  0b011..External Input 3 for Minus Channel -- Reference Input 2
25167  *  0b100..External Input 4 for Minus Channel -- Reference Input 3
25168  *  0b101..External Input 5 for Minus Channel -- Reference Input 4
25169  *  0b110..External Input 6 for Minus Channel -- Reference Input 5
25170  *  0b111..Internal 8b DAC output
25171  */
25172 #define CMP_C1_MSEL(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK)
25173 
25174 #define CMP_C1_PSEL_MASK                         (0x70000000U)
25175 #define CMP_C1_PSEL_SHIFT                        (28U)
25176 /*! PSEL - Plus Input MUX Control
25177  *  0b000..Internal Positive Input 0 for Plus Channel -- Internal Plus Input
25178  *  0b001..External Input 1 for Plus Channel -- Reference Input 0
25179  *  0b010..External Input 2 for Plus Channel -- Reference Input 1
25180  *  0b011..External Input 3 for Plus Channel -- Reference Input 2
25181  *  0b100..External Input 4 for Plus Channel -- Reference Input 3
25182  *  0b101..External Input 5 for Plus Channel -- Reference Input 4
25183  *  0b110..External Input 6 for Plus Channel -- Reference Input 5
25184  *  0b111..Internal 8b DAC output
25185  */
25186 #define CMP_C1_PSEL(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK)
25187 /*! @} */
25188 
25189 /*! @name C2 - CMP Control Register 2 */
25190 /*! @{ */
25191 
25192 #define CMP_C2_ACOn_MASK                         (0x3FU)
25193 #define CMP_C2_ACOn_SHIFT                        (0U)
25194 /*! ACOn - ACOn */
25195 #define CMP_C2_ACOn(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK)
25196 
25197 #define CMP_C2_INITMOD_MASK                      (0x3F00U)
25198 #define CMP_C2_INITMOD_SHIFT                     (8U)
25199 /*! INITMOD - Comparator and DAC initialization delay modulus. */
25200 #define CMP_C2_INITMOD(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK)
25201 
25202 #define CMP_C2_NSAM_MASK                         (0xC000U)
25203 #define CMP_C2_NSAM_SHIFT                        (14U)
25204 /*! NSAM - Number of sample clocks
25205  *  0b00..The comparison result is sampled as soon as the active channel is scanned in one round-robin clock.
25206  *  0b01..The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock.
25207  *  0b10..The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock.
25208  *  0b11..The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock.
25209  */
25210 #define CMP_C2_NSAM(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK)
25211 
25212 #define CMP_C2_CH0F_MASK                         (0x10000U)
25213 #define CMP_C2_CH0F_SHIFT                        (16U)
25214 /*! CH0F - CH0F */
25215 #define CMP_C2_CH0F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK)
25216 
25217 #define CMP_C2_CH1F_MASK                         (0x20000U)
25218 #define CMP_C2_CH1F_SHIFT                        (17U)
25219 /*! CH1F - CH1F */
25220 #define CMP_C2_CH1F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK)
25221 
25222 #define CMP_C2_CH2F_MASK                         (0x40000U)
25223 #define CMP_C2_CH2F_SHIFT                        (18U)
25224 /*! CH2F - CH2F */
25225 #define CMP_C2_CH2F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK)
25226 
25227 #define CMP_C2_CH3F_MASK                         (0x80000U)
25228 #define CMP_C2_CH3F_SHIFT                        (19U)
25229 /*! CH3F - CH3F */
25230 #define CMP_C2_CH3F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK)
25231 
25232 #define CMP_C2_CH4F_MASK                         (0x100000U)
25233 #define CMP_C2_CH4F_SHIFT                        (20U)
25234 /*! CH4F - CH4F */
25235 #define CMP_C2_CH4F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK)
25236 
25237 #define CMP_C2_CH5F_MASK                         (0x200000U)
25238 #define CMP_C2_CH5F_SHIFT                        (21U)
25239 /*! CH5F - CH5F */
25240 #define CMP_C2_CH5F(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK)
25241 
25242 #define CMP_C2_FXMXCH_MASK                       (0xE000000U)
25243 #define CMP_C2_FXMXCH_SHIFT                      (25U)
25244 /*! FXMXCH - Fixed channel selection
25245  *  0b000..External Reference Input 0 is selected as the fixed reference input for the fixed mux port.
25246  *  0b001..External Reference Input 1 is selected as the fixed reference input for the fixed mux port.
25247  *  0b010..External Reference Input 2 is selected as the fixed reference input for the fixed mux port.
25248  *  0b011..External Reference Input 3 is selected as the fixed reference input for the fixed mux port.
25249  *  0b100..External Reference Input 4 is selected as the fixed reference input for the fixed mux port.
25250  *  0b101..External Reference Input 5 is selected as the fixed reference input for the fixed mux port.
25251  *  0b110..Reserved.
25252  *  0b111..The 8bit DAC is selected as the fixed reference input for the fixed mux port.
25253  */
25254 #define CMP_C2_FXMXCH(x)                         (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK)
25255 
25256 #define CMP_C2_FXMP_MASK                         (0x20000000U)
25257 #define CMP_C2_FXMP_SHIFT                        (29U)
25258 /*! FXMP - Fixed MUX Port
25259  *  0b0..The Plus port is fixed. Only the inputs to the Minus port are swept in each round.
25260  *  0b1..The Minus port is fixed. Only the inputs to the Plus port are swept in each round.
25261  */
25262 #define CMP_C2_FXMP(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK)
25263 
25264 #define CMP_C2_RRIE_MASK                         (0x40000000U)
25265 #define CMP_C2_RRIE_SHIFT                        (30U)
25266 /*! RRIE - Round-Robin interrupt enable
25267  *  0b0..The round-robin interrupt is disabled.
25268  *  0b1..The round-robin interrupt is enabled when a comparison result changes from the last sample.
25269  */
25270 #define CMP_C2_RRIE(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK)
25271 /*! @} */
25272 
25273 /*! @name C3 - CMP Control Register 3 */
25274 /*! @{ */
25275 
25276 #define CMP_C3_ACPH2TC_MASK                      (0x70U)
25277 #define CMP_C3_ACPH2TC_SHIFT                     (4U)
25278 /*! ACPH2TC - Analog Comparator Phase2 Timing Control.
25279  *  0b000..Phase2 active time in one sampling period equals to T
25280  *  0b001..Phase2 active time in one sampling period equals to 2*T
25281  *  0b010..Phase2 active time in one sampling period equals to 4*T
25282  *  0b011..Phase2 active time in one sampling period equals to 8*T
25283  *  0b100..Phase2 active time in one sampling period equals to 16*T
25284  *  0b101..Phase2 active time in one sampling period equals to 32*T
25285  *  0b110..Phase2 active time in one sampling period equals to 64*T
25286  *  0b111..Phase2 active time in one sampling period equals to 16*T
25287  */
25288 #define CMP_C3_ACPH2TC(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK)
25289 
25290 #define CMP_C3_ACPH1TC_MASK                      (0x700U)
25291 #define CMP_C3_ACPH1TC_SHIFT                     (8U)
25292 /*! ACPH1TC - Analog Comparator Phase1 Timing Control.
25293  *  0b000..Phase1 active time in one sampling period equals to T
25294  *  0b001..Phase1 active time in one sampling period equals to 2*T
25295  *  0b010..Phase1 active time in one sampling period equals to 4*T
25296  *  0b011..Phase1 active time in one sampling period equals to 8*T
25297  *  0b100..Phase1 active time in one sampling period equals to T
25298  *  0b101..Phase1 active time in one sampling period equals to T
25299  *  0b110..Phase1 active time in one sampling period equals to T
25300  *  0b111..Phase1 active time in one sampling period equals to 0
25301  */
25302 #define CMP_C3_ACPH1TC(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK)
25303 
25304 #define CMP_C3_ACSAT_MASK                        (0x7000U)
25305 #define CMP_C3_ACSAT_SHIFT                       (12U)
25306 /*! ACSAT - Analog Comparator Sampling Time control.
25307  *  0b000..The sampling time equals to T
25308  *  0b001..The sampling time equasl to 2*T
25309  *  0b010..The sampling time equasl to 4*T
25310  *  0b011..The sampling time equasl to 8*T
25311  *  0b100..The sampling time equasl to 16*T
25312  *  0b101..The sampling time equasl to 32*T
25313  *  0b110..The sampling time equasl to 64*T
25314  *  0b111..The sampling time equasl to 256*T
25315  */
25316 #define CMP_C3_ACSAT(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK)
25317 
25318 #define CMP_C3_DMCS_MASK                         (0x10000U)
25319 #define CMP_C3_DMCS_SHIFT                        (16U)
25320 /*! DMCS - Discrete Mode Clock Selection
25321  *  0b0..Slow clock is selected for the timing generation.
25322  *  0b1..Fast clock is selected for the timing generation.
25323  */
25324 #define CMP_C3_DMCS(x)                           (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK)
25325 
25326 #define CMP_C3_RDIVE_MASK                        (0x100000U)
25327 #define CMP_C3_RDIVE_SHIFT                       (20U)
25328 /*! RDIVE - Resistor Divider Enable
25329  *  0b0..The resistor is not enabled even when either NCHEN or PCHEN is set to1 but the actual input is in the range of 0 - 1.8v.
25330  *  0b1..The resistor is enabled because the inputs are above 1.8v.
25331  */
25332 #define CMP_C3_RDIVE(x)                          (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK)
25333 
25334 #define CMP_C3_NCHCTEN_MASK                      (0x1000000U)
25335 #define CMP_C3_NCHCTEN_SHIFT                     (24U)
25336 /*! NCHCTEN - Negative Channel Continuous Mode Enable.
25337  *  0b0..Negative channel is in Discrete Mode and special timing needs to be configured.
25338  *  0b1..Negative channel is in Continuous Mode and no special timing is requried.
25339  */
25340 #define CMP_C3_NCHCTEN(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK)
25341 
25342 #define CMP_C3_PCHCTEN_MASK                      (0x10000000U)
25343 #define CMP_C3_PCHCTEN_SHIFT                     (28U)
25344 /*! PCHCTEN - Positive Channel Continuous Mode Enable.
25345  *  0b0..Positive channel is in Discrete Mode and special timing needs to be configured.
25346  *  0b1..Positive channel is in Continuous Mode and no special timing is requried.
25347  */
25348 #define CMP_C3_PCHCTEN(x)                        (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK)
25349 /*! @} */
25350 
25351 
25352 /*!
25353  * @}
25354  */ /* end of group CMP_Register_Masks */
25355 
25356 
25357 /* CMP - Peripheral instance base addresses */
25358 /** Peripheral CMP1 base address */
25359 #define CMP1_BASE                                (0x401A4000u)
25360 /** Peripheral CMP1 base pointer */
25361 #define CMP1                                     ((CMP_Type *)CMP1_BASE)
25362 /** Peripheral CMP2 base address */
25363 #define CMP2_BASE                                (0x401A8000u)
25364 /** Peripheral CMP2 base pointer */
25365 #define CMP2                                     ((CMP_Type *)CMP2_BASE)
25366 /** Peripheral CMP3 base address */
25367 #define CMP3_BASE                                (0x401AC000u)
25368 /** Peripheral CMP3 base pointer */
25369 #define CMP3                                     ((CMP_Type *)CMP3_BASE)
25370 /** Peripheral CMP4 base address */
25371 #define CMP4_BASE                                (0x401B0000u)
25372 /** Peripheral CMP4 base pointer */
25373 #define CMP4                                     ((CMP_Type *)CMP4_BASE)
25374 /** Array initializer of CMP peripheral base addresses */
25375 #define CMP_BASE_ADDRS                           { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
25376 /** Array initializer of CMP peripheral base pointers */
25377 #define CMP_BASE_PTRS                            { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
25378 /** Interrupt vectors for the CMP peripheral type */
25379 #define CMP_IRQS                                 { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
25380 
25381 /*!
25382  * @}
25383  */ /* end of group CMP_Peripheral_Access_Layer */
25384 
25385 
25386 /* ----------------------------------------------------------------------------
25387    -- CSI Peripheral Access Layer
25388    ---------------------------------------------------------------------------- */
25389 
25390 /*!
25391  * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer
25392  * @{
25393  */
25394 
25395 /** CSI - Register Layout Typedef */
25396 typedef struct {
25397   __IO uint32_t CR1;                               /**< CSI Control Register 1, offset: 0x0 */
25398   __IO uint32_t CR2;                               /**< CSI Control Register 2, offset: 0x4 */
25399   __IO uint32_t CR3;                               /**< CSI Control Register 3, offset: 0x8 */
25400   __I  uint32_t STATFIFO;                          /**< CSI Statistic FIFO Register, offset: 0xC */
25401   __I  uint32_t RFIFO;                             /**< CSI RX FIFO Register, offset: 0x10 */
25402   __IO uint32_t RXCNT;                             /**< CSI RX Count Register, offset: 0x14 */
25403   __IO uint32_t SR;                                /**< CSI Status Register, offset: 0x18 */
25404        uint8_t RESERVED_0[4];
25405   __IO uint32_t DMASA_STATFIFO;                    /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */
25406   __IO uint32_t DMATS_STATFIFO;                    /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */
25407   __IO uint32_t DMASA_FB1;                         /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */
25408   __IO uint32_t DMASA_FB2;                         /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */
25409   __IO uint32_t FBUF_PARA;                         /**< CSI Frame Buffer Parameter Register, offset: 0x30 */
25410   __IO uint32_t IMAG_PARA;                         /**< CSI Image Parameter Register, offset: 0x34 */
25411        uint8_t RESERVED_1[16];
25412   __IO uint32_t CR18;                              /**< CSI Control Register 18, offset: 0x48 */
25413   __IO uint32_t CR19;                              /**< CSI Control Register 19, offset: 0x4C */
25414   __IO uint32_t CR20;                              /**< CSI Control Register 20, offset: 0x50 */
25415   __IO uint32_t CR[256];                           /**< CSI Control Register, array offset: 0x54, array step: 0x4 */
25416 } CSI_Type;
25417 
25418 /* ----------------------------------------------------------------------------
25419    -- CSI Register Masks
25420    ---------------------------------------------------------------------------- */
25421 
25422 /*!
25423  * @addtogroup CSI_Register_Masks CSI Register Masks
25424  * @{
25425  */
25426 
25427 /*! @name CR1 - CSI Control Register 1 */
25428 /*! @{ */
25429 
25430 #define CSI_CR1_PIXEL_BIT_MASK                   (0x1U)
25431 #define CSI_CR1_PIXEL_BIT_SHIFT                  (0U)
25432 /*! PIXEL_BIT
25433  *  0b0..8-bit data for each pixel
25434  *  0b1..10-bit data for each pixel
25435  */
25436 #define CSI_CR1_PIXEL_BIT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PIXEL_BIT_SHIFT)) & CSI_CR1_PIXEL_BIT_MASK)
25437 
25438 #define CSI_CR1_REDGE_MASK                       (0x2U)
25439 #define CSI_CR1_REDGE_SHIFT                      (1U)
25440 /*! REDGE
25441  *  0b0..Pixel data is latched at the falling edge of CSI_PIXCLK
25442  *  0b1..Pixel data is latched at the rising edge of CSI_PIXCLK
25443  */
25444 #define CSI_CR1_REDGE(x)                         (((uint32_t)(((uint32_t)(x)) << CSI_CR1_REDGE_SHIFT)) & CSI_CR1_REDGE_MASK)
25445 
25446 #define CSI_CR1_INV_PCLK_MASK                    (0x4U)
25447 #define CSI_CR1_INV_PCLK_SHIFT                   (2U)
25448 /*! INV_PCLK
25449  *  0b0..CSI_PIXCLK is directly applied to internal circuitry
25450  *  0b1..CSI_PIXCLK is inverted before applied to internal circuitry
25451  */
25452 #define CSI_CR1_INV_PCLK(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_PCLK_SHIFT)) & CSI_CR1_INV_PCLK_MASK)
25453 
25454 #define CSI_CR1_INV_DATA_MASK                    (0x8U)
25455 #define CSI_CR1_INV_DATA_SHIFT                   (3U)
25456 /*! INV_DATA
25457  *  0b0..CSI_D[7:0] data lines are directly applied to internal circuitry
25458  *  0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry
25459  */
25460 #define CSI_CR1_INV_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_DATA_SHIFT)) & CSI_CR1_INV_DATA_MASK)
25461 
25462 #define CSI_CR1_GCLK_MODE_MASK                   (0x10U)
25463 #define CSI_CR1_GCLK_MODE_SHIFT                  (4U)
25464 /*! GCLK_MODE
25465  *  0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored.
25466  *  0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
25467  */
25468 #define CSI_CR1_GCLK_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_GCLK_MODE_SHIFT)) & CSI_CR1_GCLK_MODE_MASK)
25469 
25470 #define CSI_CR1_CLR_RXFIFO_MASK                  (0x20U)
25471 #define CSI_CR1_CLR_RXFIFO_SHIFT                 (5U)
25472 #define CSI_CR1_CLR_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_RXFIFO_SHIFT)) & CSI_CR1_CLR_RXFIFO_MASK)
25473 
25474 #define CSI_CR1_CLR_STATFIFO_MASK                (0x40U)
25475 #define CSI_CR1_CLR_STATFIFO_SHIFT               (6U)
25476 #define CSI_CR1_CLR_STATFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_STATFIFO_SHIFT)) & CSI_CR1_CLR_STATFIFO_MASK)
25477 
25478 #define CSI_CR1_PACK_DIR_MASK                    (0x80U)
25479 #define CSI_CR1_PACK_DIR_SHIFT                   (7U)
25480 /*! PACK_DIR
25481  *  0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For
25482  *       stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO.
25483  *  0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For
25484  *       stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
25485  */
25486 #define CSI_CR1_PACK_DIR(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PACK_DIR_SHIFT)) & CSI_CR1_PACK_DIR_MASK)
25487 
25488 #define CSI_CR1_FCC_MASK                         (0x100U)
25489 #define CSI_CR1_FCC_SHIFT                        (8U)
25490 /*! FCC
25491  *  0b0..Asynchronous FIFO clear is selected.
25492  *  0b1..Synchronous FIFO clear is selected.
25493  */
25494 #define CSI_CR1_FCC(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FCC_SHIFT)) & CSI_CR1_FCC_MASK)
25495 
25496 #define CSI_CR1_CCIR_EN_MASK                     (0x400U)
25497 #define CSI_CR1_CCIR_EN_SHIFT                    (10U)
25498 /*! CCIR_EN
25499  *  0b0..Traditional interface is selected.
25500  *  0b1..BT.656 interface is selected.
25501  */
25502 #define CSI_CR1_CCIR_EN(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CCIR_EN_SHIFT)) & CSI_CR1_CCIR_EN_MASK)
25503 
25504 #define CSI_CR1_HSYNC_POL_MASK                   (0x800U)
25505 #define CSI_CR1_HSYNC_POL_SHIFT                  (11U)
25506 /*! HSYNC_POL
25507  *  0b0..HSYNC is active low
25508  *  0b1..HSYNC is active high
25509  */
25510 #define CSI_CR1_HSYNC_POL(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HSYNC_POL_SHIFT)) & CSI_CR1_HSYNC_POL_MASK)
25511 
25512 #define CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK      (0x1000U)
25513 #define CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT     (12U)
25514 /*! HISTOGRAM_CALC_DONE_IE
25515  *  0b0..Histogram done interrupt disable
25516  *  0b1..Histogram done interrupt enable
25517  */
25518 #define CSI_CR1_HISTOGRAM_CALC_DONE_IE(x)        (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT)) & CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK)
25519 
25520 #define CSI_CR1_SOF_INTEN_MASK                   (0x10000U)
25521 #define CSI_CR1_SOF_INTEN_SHIFT                  (16U)
25522 /*! SOF_INTEN
25523  *  0b0..SOF interrupt disable
25524  *  0b1..SOF interrupt enable
25525  */
25526 #define CSI_CR1_SOF_INTEN(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_INTEN_SHIFT)) & CSI_CR1_SOF_INTEN_MASK)
25527 
25528 #define CSI_CR1_SOF_POL_MASK                     (0x20000U)
25529 #define CSI_CR1_SOF_POL_SHIFT                    (17U)
25530 /*! SOF_POL
25531  *  0b0..SOF interrupt is generated on SOF falling edge
25532  *  0b1..SOF interrupt is generated on SOF rising edge
25533  */
25534 #define CSI_CR1_SOF_POL(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_POL_SHIFT)) & CSI_CR1_SOF_POL_MASK)
25535 
25536 #define CSI_CR1_RXFF_INTEN_MASK                  (0x40000U)
25537 #define CSI_CR1_RXFF_INTEN_SHIFT                 (18U)
25538 /*! RXFF_INTEN
25539  *  0b0..RxFIFO full interrupt disable
25540  *  0b1..RxFIFO full interrupt enable
25541  */
25542 #define CSI_CR1_RXFF_INTEN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RXFF_INTEN_SHIFT)) & CSI_CR1_RXFF_INTEN_MASK)
25543 
25544 #define CSI_CR1_FB1_DMA_DONE_INTEN_MASK          (0x80000U)
25545 #define CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT         (19U)
25546 /*! FB1_DMA_DONE_INTEN
25547  *  0b0..Frame Buffer1 DMA Transfer Done interrupt disable
25548  *  0b1..Frame Buffer1 DMA Transfer Done interrupt enable
25549  */
25550 #define CSI_CR1_FB1_DMA_DONE_INTEN(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB1_DMA_DONE_INTEN_MASK)
25551 
25552 #define CSI_CR1_FB2_DMA_DONE_INTEN_MASK          (0x100000U)
25553 #define CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT         (20U)
25554 /*! FB2_DMA_DONE_INTEN
25555  *  0b0..Frame Buffer2 DMA Transfer Done interrupt disable
25556  *  0b1..Frame Buffer2 DMA Transfer Done interrupt enable
25557  */
25558 #define CSI_CR1_FB2_DMA_DONE_INTEN(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB2_DMA_DONE_INTEN_MASK)
25559 
25560 #define CSI_CR1_STATFF_INTEN_MASK                (0x200000U)
25561 #define CSI_CR1_STATFF_INTEN_SHIFT               (21U)
25562 /*! STATFF_INTEN
25563  *  0b0..STATFIFO full interrupt disable
25564  *  0b1..STATFIFO full interrupt enable
25565  */
25566 #define CSI_CR1_STATFF_INTEN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR1_STATFF_INTEN_SHIFT)) & CSI_CR1_STATFF_INTEN_MASK)
25567 
25568 #define CSI_CR1_SFF_DMA_DONE_INTEN_MASK          (0x400000U)
25569 #define CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT         (22U)
25570 /*! SFF_DMA_DONE_INTEN
25571  *  0b0..STATFIFO DMA Transfer Done interrupt disable
25572  *  0b1..STATFIFO DMA Transfer Done interrupt enable
25573  */
25574 #define CSI_CR1_SFF_DMA_DONE_INTEN(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_SFF_DMA_DONE_INTEN_MASK)
25575 
25576 #define CSI_CR1_RF_OR_INTEN_MASK                 (0x1000000U)
25577 #define CSI_CR1_RF_OR_INTEN_SHIFT                (24U)
25578 /*! RF_OR_INTEN
25579  *  0b0..RxFIFO overrun interrupt is disabled
25580  *  0b1..RxFIFO overrun interrupt is enabled
25581  */
25582 #define CSI_CR1_RF_OR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RF_OR_INTEN_SHIFT)) & CSI_CR1_RF_OR_INTEN_MASK)
25583 
25584 #define CSI_CR1_SF_OR_INTEN_MASK                 (0x2000000U)
25585 #define CSI_CR1_SF_OR_INTEN_SHIFT                (25U)
25586 /*! SF_OR_INTEN
25587  *  0b0..STATFIFO overrun interrupt is disabled
25588  *  0b1..STATFIFO overrun interrupt is enabled
25589  */
25590 #define CSI_CR1_SF_OR_INTEN(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SF_OR_INTEN_SHIFT)) & CSI_CR1_SF_OR_INTEN_MASK)
25591 
25592 #define CSI_CR1_COF_INT_EN_MASK                  (0x4000000U)
25593 #define CSI_CR1_COF_INT_EN_SHIFT                 (26U)
25594 /*! COF_INT_EN
25595  *  0b0..COF interrupt is disabled
25596  *  0b1..COF interrupt is enabled
25597  */
25598 #define CSI_CR1_COF_INT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_COF_INT_EN_SHIFT)) & CSI_CR1_COF_INT_EN_MASK)
25599 
25600 #define CSI_CR1_VIDEO_MODE_MASK                  (0x8000000U)
25601 #define CSI_CR1_VIDEO_MODE_SHIFT                 (27U)
25602 /*! VIDEO_MODE
25603  *  0b0..Progressive mode is selected
25604  *  0b1..Interlace mode is selected
25605  */
25606 #define CSI_CR1_VIDEO_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_VIDEO_MODE_SHIFT)) & CSI_CR1_VIDEO_MODE_MASK)
25607 
25608 #define CSI_CR1_EOF_INT_EN_MASK                  (0x20000000U)
25609 #define CSI_CR1_EOF_INT_EN_SHIFT                 (29U)
25610 /*! EOF_INT_EN
25611  *  0b0..EOF interrupt is disabled.
25612  *  0b1..EOF interrupt is generated when RX count value is reached.
25613  */
25614 #define CSI_CR1_EOF_INT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EOF_INT_EN_SHIFT)) & CSI_CR1_EOF_INT_EN_MASK)
25615 
25616 #define CSI_CR1_EXT_VSYNC_MASK                   (0x40000000U)
25617 #define CSI_CR1_EXT_VSYNC_SHIFT                  (30U)
25618 /*! EXT_VSYNC
25619  *  0b0..Internal VSYNC mode
25620  *  0b1..External VSYNC mode
25621  */
25622 #define CSI_CR1_EXT_VSYNC(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EXT_VSYNC_SHIFT)) & CSI_CR1_EXT_VSYNC_MASK)
25623 
25624 #define CSI_CR1_SWAP16_EN_MASK                   (0x80000000U)
25625 #define CSI_CR1_SWAP16_EN_SHIFT                  (31U)
25626 /*! SWAP16_EN
25627  *  0b0..Disable swapping
25628  *  0b1..Enable swapping
25629  */
25630 #define CSI_CR1_SWAP16_EN(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SWAP16_EN_SHIFT)) & CSI_CR1_SWAP16_EN_MASK)
25631 /*! @} */
25632 
25633 /*! @name CR2 - CSI Control Register 2 */
25634 /*! @{ */
25635 
25636 #define CSI_CR2_HSC_MASK                         (0xFFU)
25637 #define CSI_CR2_HSC_SHIFT                        (0U)
25638 /*! HSC
25639  *  0b00000000-0b11111111..Number of pixels to skip minus 1
25640  */
25641 #define CSI_CR2_HSC(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_HSC_SHIFT)) & CSI_CR2_HSC_MASK)
25642 
25643 #define CSI_CR2_VSC_MASK                         (0xFF00U)
25644 #define CSI_CR2_VSC_SHIFT                        (8U)
25645 /*! VSC
25646  *  0b00000000-0b11111111..Number of rows to skip minus 1
25647  */
25648 #define CSI_CR2_VSC(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_VSC_SHIFT)) & CSI_CR2_VSC_MASK)
25649 
25650 #define CSI_CR2_LVRM_MASK                        (0x70000U)
25651 #define CSI_CR2_LVRM_SHIFT                       (16U)
25652 /*! LVRM
25653  *  0b000..512 x 384
25654  *  0b001..448 x 336
25655  *  0b010..384 x 288
25656  *  0b011..384 x 256
25657  *  0b100..320 x 240
25658  *  0b101..288 x 216
25659  *  0b110..400 x 300
25660  */
25661 #define CSI_CR2_LVRM(x)                          (((uint32_t)(((uint32_t)(x)) << CSI_CR2_LVRM_SHIFT)) & CSI_CR2_LVRM_MASK)
25662 
25663 #define CSI_CR2_BTS_MASK                         (0x180000U)
25664 #define CSI_CR2_BTS_SHIFT                        (19U)
25665 /*! BTS
25666  *  0b00..GR
25667  *  0b01..RG
25668  *  0b10..BG
25669  *  0b11..GB
25670  */
25671 #define CSI_CR2_BTS(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_BTS_SHIFT)) & CSI_CR2_BTS_MASK)
25672 
25673 #define CSI_CR2_SCE_MASK                         (0x800000U)
25674 #define CSI_CR2_SCE_SHIFT                        (23U)
25675 /*! SCE
25676  *  0b0..Skip count disable
25677  *  0b1..Skip count enable
25678  */
25679 #define CSI_CR2_SCE(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_SCE_SHIFT)) & CSI_CR2_SCE_MASK)
25680 
25681 #define CSI_CR2_AFS_MASK                         (0x3000000U)
25682 #define CSI_CR2_AFS_SHIFT                        (24U)
25683 /*! AFS
25684  *  0b00..Abs Diff on consecutive green pixels
25685  *  0b01..Abs Diff on every third green pixels
25686  *  0b1x..Abs Diff on every four green pixels
25687  */
25688 #define CSI_CR2_AFS(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_AFS_SHIFT)) & CSI_CR2_AFS_MASK)
25689 
25690 #define CSI_CR2_DRM_MASK                         (0x4000000U)
25691 #define CSI_CR2_DRM_SHIFT                        (26U)
25692 /*! DRM
25693  *  0b0..Stats grid of 8 x 6
25694  *  0b1..Stats grid of 8 x 12
25695  */
25696 #define CSI_CR2_DRM(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DRM_SHIFT)) & CSI_CR2_DRM_MASK)
25697 
25698 #define CSI_CR2_DMA_BURST_TYPE_SFF_MASK          (0x30000000U)
25699 #define CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT         (28U)
25700 /*! DMA_BURST_TYPE_SFF
25701  *  0bx0..INCR8
25702  *  0b01..INCR4
25703  *  0b11..INCR16
25704  */
25705 #define CSI_CR2_DMA_BURST_TYPE_SFF(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_SFF_MASK)
25706 
25707 #define CSI_CR2_DMA_BURST_TYPE_RFF_MASK          (0xC0000000U)
25708 #define CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT         (30U)
25709 /*! DMA_BURST_TYPE_RFF
25710  *  0bx0..INCR8
25711  *  0b01..INCR4
25712  *  0b11..INCR16
25713  */
25714 #define CSI_CR2_DMA_BURST_TYPE_RFF(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_RFF_MASK)
25715 /*! @} */
25716 
25717 /*! @name CR3 - CSI Control Register 3 */
25718 /*! @{ */
25719 
25720 #define CSI_CR3_ECC_AUTO_EN_MASK                 (0x1U)
25721 #define CSI_CR3_ECC_AUTO_EN_SHIFT                (0U)
25722 /*! ECC_AUTO_EN
25723  *  0b0..Auto Error correction is disabled.
25724  *  0b1..Auto Error correction is enabled.
25725  */
25726 #define CSI_CR3_ECC_AUTO_EN(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_AUTO_EN_SHIFT)) & CSI_CR3_ECC_AUTO_EN_MASK)
25727 
25728 #define CSI_CR3_ECC_INT_EN_MASK                  (0x2U)
25729 #define CSI_CR3_ECC_INT_EN_SHIFT                 (1U)
25730 /*! ECC_INT_EN
25731  *  0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set.
25732  *  0b1..Interrupt is generated when error is detected.
25733  */
25734 #define CSI_CR3_ECC_INT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_INT_EN_SHIFT)) & CSI_CR3_ECC_INT_EN_MASK)
25735 
25736 #define CSI_CR3_ZERO_PACK_EN_MASK                (0x4U)
25737 #define CSI_CR3_ZERO_PACK_EN_SHIFT               (2U)
25738 /*! ZERO_PACK_EN
25739  *  0b0..Zero packing disabled
25740  *  0b1..Zero packing enabled
25741  */
25742 #define CSI_CR3_ZERO_PACK_EN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ZERO_PACK_EN_SHIFT)) & CSI_CR3_ZERO_PACK_EN_MASK)
25743 
25744 #define CSI_CR3_SENSOR_16BITS_MASK               (0x8U)
25745 #define CSI_CR3_SENSOR_16BITS_SHIFT              (3U)
25746 /*! SENSOR_16BITS
25747  *  0b0..Only one 8-bit sensor is connected.
25748  *  0b1..One 16-bit sensor is connected.
25749  */
25750 #define CSI_CR3_SENSOR_16BITS(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR3_SENSOR_16BITS_SHIFT)) & CSI_CR3_SENSOR_16BITS_MASK)
25751 
25752 #define CSI_CR3_RxFF_LEVEL_MASK                  (0x70U)
25753 #define CSI_CR3_RxFF_LEVEL_SHIFT                 (4U)
25754 /*! RxFF_LEVEL
25755  *  0b000..4 Double words
25756  *  0b001..8 Double words
25757  *  0b010..16 Double words
25758  *  0b011..24 Double words
25759  *  0b100..32 Double words
25760  *  0b101..48 Double words
25761  *  0b110..64 Double words
25762  *  0b111..96 Double words
25763  */
25764 #define CSI_CR3_RxFF_LEVEL(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR3_RxFF_LEVEL_SHIFT)) & CSI_CR3_RxFF_LEVEL_MASK)
25765 
25766 #define CSI_CR3_HRESP_ERR_EN_MASK                (0x80U)
25767 #define CSI_CR3_HRESP_ERR_EN_SHIFT               (7U)
25768 /*! HRESP_ERR_EN
25769  *  0b0..Disable hresponse error interrupt
25770  *  0b1..Enable hresponse error interrupt
25771  */
25772 #define CSI_CR3_HRESP_ERR_EN(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR3_HRESP_ERR_EN_SHIFT)) & CSI_CR3_HRESP_ERR_EN_MASK)
25773 
25774 #define CSI_CR3_STATFF_LEVEL_MASK                (0x700U)
25775 #define CSI_CR3_STATFF_LEVEL_SHIFT               (8U)
25776 /*! STATFF_LEVEL
25777  *  0b000..4 Double words
25778  *  0b001..8 Double words
25779  *  0b010..12 Double words
25780  *  0b011..16 Double words
25781  *  0b100..24 Double words
25782  *  0b101..32 Double words
25783  *  0b110..48 Double words
25784  *  0b111..64 Double words
25785  */
25786 #define CSI_CR3_STATFF_LEVEL(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR3_STATFF_LEVEL_SHIFT)) & CSI_CR3_STATFF_LEVEL_MASK)
25787 
25788 #define CSI_CR3_DMA_REQ_EN_SFF_MASK              (0x800U)
25789 #define CSI_CR3_DMA_REQ_EN_SFF_SHIFT             (11U)
25790 /*! DMA_REQ_EN_SFF
25791  *  0b0..Disable the dma request
25792  *  0b1..Enable the dma request
25793  */
25794 #define CSI_CR3_DMA_REQ_EN_SFF(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_SFF_MASK)
25795 
25796 #define CSI_CR3_DMA_REQ_EN_RFF_MASK              (0x1000U)
25797 #define CSI_CR3_DMA_REQ_EN_RFF_SHIFT             (12U)
25798 /*! DMA_REQ_EN_RFF
25799  *  0b0..Disable the dma request
25800  *  0b1..Enable the dma request
25801  */
25802 #define CSI_CR3_DMA_REQ_EN_RFF(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_RFF_MASK)
25803 
25804 #define CSI_CR3_DMA_REFLASH_SFF_MASK             (0x2000U)
25805 #define CSI_CR3_DMA_REFLASH_SFF_SHIFT            (13U)
25806 /*! DMA_REFLASH_SFF
25807  *  0b0..No reflashing
25808  *  0b1..Reflash the embedded DMA controller
25809  */
25810 #define CSI_CR3_DMA_REFLASH_SFF(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CR3_DMA_REFLASH_SFF_MASK)
25811 
25812 #define CSI_CR3_DMA_REFLASH_RFF_MASK             (0x4000U)
25813 #define CSI_CR3_DMA_REFLASH_RFF_SHIFT            (14U)
25814 /*! DMA_REFLASH_RFF
25815  *  0b0..No reflashing
25816  *  0b1..Reflash the embedded DMA controller
25817  */
25818 #define CSI_CR3_DMA_REFLASH_RFF(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CR3_DMA_REFLASH_RFF_MASK)
25819 
25820 #define CSI_CR3_FRMCNT_RST_MASK                  (0x8000U)
25821 #define CSI_CR3_FRMCNT_RST_SHIFT                 (15U)
25822 /*! FRMCNT_RST
25823  *  0b0..Do not reset
25824  *  0b1..Reset frame counter immediately
25825  */
25826 #define CSI_CR3_FRMCNT_RST(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_RST_SHIFT)) & CSI_CR3_FRMCNT_RST_MASK)
25827 
25828 #define CSI_CR3_FRMCNT_MASK                      (0xFFFF0000U)
25829 #define CSI_CR3_FRMCNT_SHIFT                     (16U)
25830 #define CSI_CR3_FRMCNT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_SHIFT)) & CSI_CR3_FRMCNT_MASK)
25831 /*! @} */
25832 
25833 /*! @name STATFIFO - CSI Statistic FIFO Register */
25834 /*! @{ */
25835 
25836 #define CSI_STATFIFO_STAT_MASK                   (0xFFFFFFFFU)
25837 #define CSI_STATFIFO_STAT_SHIFT                  (0U)
25838 #define CSI_STATFIFO_STAT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_STATFIFO_STAT_SHIFT)) & CSI_STATFIFO_STAT_MASK)
25839 /*! @} */
25840 
25841 /*! @name RFIFO - CSI RX FIFO Register */
25842 /*! @{ */
25843 
25844 #define CSI_RFIFO_IMAGE_MASK                     (0xFFFFFFFFU)
25845 #define CSI_RFIFO_IMAGE_SHIFT                    (0U)
25846 #define CSI_RFIFO_IMAGE(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_RFIFO_IMAGE_SHIFT)) & CSI_RFIFO_IMAGE_MASK)
25847 /*! @} */
25848 
25849 /*! @name RXCNT - CSI RX Count Register */
25850 /*! @{ */
25851 
25852 #define CSI_RXCNT_RXCNT_MASK                     (0x3FFFFFU)
25853 #define CSI_RXCNT_RXCNT_SHIFT                    (0U)
25854 #define CSI_RXCNT_RXCNT(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_RXCNT_RXCNT_SHIFT)) & CSI_RXCNT_RXCNT_MASK)
25855 /*! @} */
25856 
25857 /*! @name SR - CSI Status Register */
25858 /*! @{ */
25859 
25860 #define CSI_SR_DRDY_MASK                         (0x1U)
25861 #define CSI_SR_DRDY_SHIFT                        (0U)
25862 /*! DRDY
25863  *  0b0..No data (word) is ready
25864  *  0b1..At least 1 datum (word) is ready in RXFIFO.
25865  */
25866 #define CSI_SR_DRDY(x)                           (((uint32_t)(((uint32_t)(x)) << CSI_SR_DRDY_SHIFT)) & CSI_SR_DRDY_MASK)
25867 
25868 #define CSI_SR_ECC_INT_MASK                      (0x2U)
25869 #define CSI_SR_ECC_INT_SHIFT                     (1U)
25870 /*! ECC_INT
25871  *  0b0..No error detected
25872  *  0b1..Error is detected in BT.656 coding
25873  */
25874 #define CSI_SR_ECC_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_ECC_INT_SHIFT)) & CSI_SR_ECC_INT_MASK)
25875 
25876 #define CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK      (0x4U)
25877 #define CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT     (2U)
25878 /*! HISTOGRAM_CALC_DONE_INT
25879  *  0b0..Histogram calculation is not finished
25880  *  0b1..Histogram calculation is done and driver can access the PIXEL_COUNTERS(CSI_CSICR21~CSI_CSICR276) to get the gray level
25881  */
25882 #define CSI_SR_HISTOGRAM_CALC_DONE_INT(x)        (((uint32_t)(((uint32_t)(x)) << CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT)) & CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK)
25883 
25884 #define CSI_SR_HRESP_ERR_INT_MASK                (0x80U)
25885 #define CSI_SR_HRESP_ERR_INT_SHIFT               (7U)
25886 /*! HRESP_ERR_INT
25887  *  0b0..No hresponse error.
25888  *  0b1..Hresponse error is detected.
25889  */
25890 #define CSI_SR_HRESP_ERR_INT(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_SR_HRESP_ERR_INT_SHIFT)) & CSI_SR_HRESP_ERR_INT_MASK)
25891 
25892 #define CSI_SR_COF_INT_MASK                      (0x2000U)
25893 #define CSI_SR_COF_INT_SHIFT                     (13U)
25894 /*! COF_INT
25895  *  0b0..Video field has no change.
25896  *  0b1..Change of video field is detected.
25897  */
25898 #define CSI_SR_COF_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_COF_INT_SHIFT)) & CSI_SR_COF_INT_MASK)
25899 
25900 #define CSI_SR_F1_INT_MASK                       (0x4000U)
25901 #define CSI_SR_F1_INT_SHIFT                      (14U)
25902 /*! F1_INT
25903  *  0b0..Field 1 of video is not detected.
25904  *  0b1..Field 1 of video is about to start.
25905  */
25906 #define CSI_SR_F1_INT(x)                         (((uint32_t)(((uint32_t)(x)) << CSI_SR_F1_INT_SHIFT)) & CSI_SR_F1_INT_MASK)
25907 
25908 #define CSI_SR_F2_INT_MASK                       (0x8000U)
25909 #define CSI_SR_F2_INT_SHIFT                      (15U)
25910 /*! F2_INT
25911  *  0b0..Field 2 of video is not detected
25912  *  0b1..Field 2 of video is about to start
25913  */
25914 #define CSI_SR_F2_INT(x)                         (((uint32_t)(((uint32_t)(x)) << CSI_SR_F2_INT_SHIFT)) & CSI_SR_F2_INT_MASK)
25915 
25916 #define CSI_SR_SOF_INT_MASK                      (0x10000U)
25917 #define CSI_SR_SOF_INT_SHIFT                     (16U)
25918 /*! SOF_INT
25919  *  0b0..SOF is not detected.
25920  *  0b1..SOF is detected.
25921  */
25922 #define CSI_SR_SOF_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_SOF_INT_SHIFT)) & CSI_SR_SOF_INT_MASK)
25923 
25924 #define CSI_SR_EOF_INT_MASK                      (0x20000U)
25925 #define CSI_SR_EOF_INT_SHIFT                     (17U)
25926 /*! EOF_INT
25927  *  0b0..EOF is not detected.
25928  *  0b1..EOF is detected.
25929  */
25930 #define CSI_SR_EOF_INT(x)                        (((uint32_t)(((uint32_t)(x)) << CSI_SR_EOF_INT_SHIFT)) & CSI_SR_EOF_INT_MASK)
25931 
25932 #define CSI_SR_RxFF_INT_MASK                     (0x40000U)
25933 #define CSI_SR_RxFF_INT_SHIFT                    (18U)
25934 /*! RxFF_INT
25935  *  0b0..RxFIFO is not full.
25936  *  0b1..RxFIFO is full.
25937  */
25938 #define CSI_SR_RxFF_INT(x)                       (((uint32_t)(((uint32_t)(x)) << CSI_SR_RxFF_INT_SHIFT)) & CSI_SR_RxFF_INT_MASK)
25939 
25940 #define CSI_SR_DMA_TSF_DONE_FB1_MASK             (0x80000U)
25941 #define CSI_SR_DMA_TSF_DONE_FB1_SHIFT            (19U)
25942 /*! DMA_TSF_DONE_FB1
25943  *  0b0..DMA transfer is not completed.
25944  *  0b1..DMA transfer is completed.
25945  */
25946 #define CSI_SR_DMA_TSF_DONE_FB1(x)               (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB1_MASK)
25947 
25948 #define CSI_SR_DMA_TSF_DONE_FB2_MASK             (0x100000U)
25949 #define CSI_SR_DMA_TSF_DONE_FB2_SHIFT            (20U)
25950 /*! DMA_TSF_DONE_FB2
25951  *  0b0..DMA transfer is not completed.
25952  *  0b1..DMA transfer is completed.
25953  */
25954 #define CSI_SR_DMA_TSF_DONE_FB2(x)               (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB2_MASK)
25955 
25956 #define CSI_SR_STATFF_INT_MASK                   (0x200000U)
25957 #define CSI_SR_STATFF_INT_SHIFT                  (21U)
25958 /*! STATFF_INT
25959  *  0b0..STATFIFO is not full.
25960  *  0b1..STATFIFO is full.
25961  */
25962 #define CSI_SR_STATFF_INT(x)                     (((uint32_t)(((uint32_t)(x)) << CSI_SR_STATFF_INT_SHIFT)) & CSI_SR_STATFF_INT_MASK)
25963 
25964 #define CSI_SR_DMA_TSF_DONE_SFF_MASK             (0x400000U)
25965 #define CSI_SR_DMA_TSF_DONE_SFF_SHIFT            (22U)
25966 /*! DMA_TSF_DONE_SFF
25967  *  0b0..DMA transfer is not completed.
25968  *  0b1..DMA transfer is completed.
25969  */
25970 #define CSI_SR_DMA_TSF_DONE_SFF(x)               (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_SR_DMA_TSF_DONE_SFF_MASK)
25971 
25972 #define CSI_SR_RF_OR_INT_MASK                    (0x1000000U)
25973 #define CSI_SR_RF_OR_INT_SHIFT                   (24U)
25974 /*! RF_OR_INT
25975  *  0b0..RXFIFO has not overflowed.
25976  *  0b1..RXFIFO has overflowed.
25977  */
25978 #define CSI_SR_RF_OR_INT(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_SR_RF_OR_INT_SHIFT)) & CSI_SR_RF_OR_INT_MASK)
25979 
25980 #define CSI_SR_SF_OR_INT_MASK                    (0x2000000U)
25981 #define CSI_SR_SF_OR_INT_SHIFT                   (25U)
25982 /*! SF_OR_INT
25983  *  0b0..STATFIFO has not overflowed.
25984  *  0b1..STATFIFO has overflowed.
25985  */
25986 #define CSI_SR_SF_OR_INT(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_SR_SF_OR_INT_SHIFT)) & CSI_SR_SF_OR_INT_MASK)
25987 
25988 #define CSI_SR_DMA_FIELD1_DONE_MASK              (0x4000000U)
25989 #define CSI_SR_DMA_FIELD1_DONE_SHIFT             (26U)
25990 #define CSI_SR_DMA_FIELD1_DONE(x)                (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD1_DONE_SHIFT)) & CSI_SR_DMA_FIELD1_DONE_MASK)
25991 
25992 #define CSI_SR_DMA_FIELD0_DONE_MASK              (0x8000000U)
25993 #define CSI_SR_DMA_FIELD0_DONE_SHIFT             (27U)
25994 #define CSI_SR_DMA_FIELD0_DONE(x)                (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD0_DONE_SHIFT)) & CSI_SR_DMA_FIELD0_DONE_MASK)
25995 
25996 #define CSI_SR_BASEADDR_CHHANGE_ERROR_MASK       (0x10000000U)
25997 #define CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT      (28U)
25998 #define CSI_SR_BASEADDR_CHHANGE_ERROR(x)         (((uint32_t)(((uint32_t)(x)) << CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_SR_BASEADDR_CHHANGE_ERROR_MASK)
25999 /*! @} */
26000 
26001 /*! @name DMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */
26002 /*! @{ */
26003 
26004 #define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
26005 #define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
26006 #define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
26007 /*! @} */
26008 
26009 /*! @name DMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */
26010 /*! @{ */
26011 
26012 #define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
26013 #define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
26014 #define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x)   (((uint32_t)(((uint32_t)(x)) << CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
26015 /*! @} */
26016 
26017 /*! @name DMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */
26018 /*! @{ */
26019 
26020 #define CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK    (0xFFFFFFFCU)
26021 #define CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT   (2U)
26022 #define CSI_DMASA_FB1_DMA_START_ADDR_FB1(x)      (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK)
26023 /*! @} */
26024 
26025 /*! @name DMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */
26026 /*! @{ */
26027 
26028 #define CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK    (0xFFFFFFFCU)
26029 #define CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT   (2U)
26030 #define CSI_DMASA_FB2_DMA_START_ADDR_FB2(x)      (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK)
26031 /*! @} */
26032 
26033 /*! @name FBUF_PARA - CSI Frame Buffer Parameter Register */
26034 /*! @{ */
26035 
26036 #define CSI_FBUF_PARA_FBUF_STRIDE_MASK           (0xFFFFU)
26037 #define CSI_FBUF_PARA_FBUF_STRIDE_SHIFT          (0U)
26038 #define CSI_FBUF_PARA_FBUF_STRIDE(x)             (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_FBUF_PARA_FBUF_STRIDE_MASK)
26039 
26040 #define CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK    (0xFFFF0000U)
26041 #define CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT   (16U)
26042 #define CSI_FBUF_PARA_DEINTERLACE_STRIDE(x)      (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK)
26043 /*! @} */
26044 
26045 /*! @name IMAG_PARA - CSI Image Parameter Register */
26046 /*! @{ */
26047 
26048 #define CSI_IMAG_PARA_IMAGE_HEIGHT_MASK          (0xFFFFU)
26049 #define CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT         (0U)
26050 #define CSI_IMAG_PARA_IMAGE_HEIGHT(x)            (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_IMAG_PARA_IMAGE_HEIGHT_MASK)
26051 
26052 #define CSI_IMAG_PARA_IMAGE_WIDTH_MASK           (0xFFFF0000U)
26053 #define CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT          (16U)
26054 #define CSI_IMAG_PARA_IMAGE_WIDTH(x)             (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_IMAG_PARA_IMAGE_WIDTH_MASK)
26055 /*! @} */
26056 
26057 /*! @name CR18 - CSI Control Register 18 */
26058 /*! @{ */
26059 
26060 #define CSI_CR18_NTSC_EN_MASK                    (0x1U)
26061 #define CSI_CR18_NTSC_EN_SHIFT                   (0U)
26062 /*! NTSC_EN
26063  *  0b0..PAL
26064  *  0b1..NTSC
26065  */
26066 #define CSI_CR18_NTSC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR18_NTSC_EN_SHIFT)) & CSI_CR18_NTSC_EN_MASK)
26067 
26068 #define CSI_CR18_TVDECODER_IN_EN_MASK            (0x2U)
26069 #define CSI_CR18_TVDECODER_IN_EN_SHIFT           (1U)
26070 #define CSI_CR18_TVDECODER_IN_EN(x)              (((uint32_t)(((uint32_t)(x)) << CSI_CR18_TVDECODER_IN_EN_SHIFT)) & CSI_CR18_TVDECODER_IN_EN_MASK)
26071 
26072 #define CSI_CR18_DEINTERLACE_EN_MASK             (0x4U)
26073 #define CSI_CR18_DEINTERLACE_EN_SHIFT            (2U)
26074 /*! DEINTERLACE_EN
26075  *  0b0..Deinterlace disabled
26076  *  0b1..Deinterlace enabled
26077  */
26078 #define CSI_CR18_DEINTERLACE_EN(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DEINTERLACE_EN_SHIFT)) & CSI_CR18_DEINTERLACE_EN_MASK)
26079 
26080 #define CSI_CR18_PARALLEL24_EN_MASK              (0x8U)
26081 #define CSI_CR18_PARALLEL24_EN_SHIFT             (3U)
26082 /*! PARALLEL24_EN
26083  *  0b0..Input is disabled
26084  *  0b1..Input is enabled
26085  */
26086 #define CSI_CR18_PARALLEL24_EN(x)                (((uint32_t)(((uint32_t)(x)) << CSI_CR18_PARALLEL24_EN_SHIFT)) & CSI_CR18_PARALLEL24_EN_MASK)
26087 
26088 #define CSI_CR18_BASEADDR_SWITCH_EN_MASK         (0x10U)
26089 #define CSI_CR18_BASEADDR_SWITCH_EN_SHIFT        (4U)
26090 #define CSI_CR18_BASEADDR_SWITCH_EN(x)           (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_EN_MASK)
26091 
26092 #define CSI_CR18_BASEADDR_SWITCH_SEL_MASK        (0x20U)
26093 #define CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT       (5U)
26094 /*! BASEADDR_SWITCH_SEL
26095  *  0b0..Switching base address at the edge of the vsync
26096  *  0b1..Switching base address at the edge of the first data of each frame
26097  */
26098 #define CSI_CR18_BASEADDR_SWITCH_SEL(x)          (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_SEL_MASK)
26099 
26100 #define CSI_CR18_FIELD0_DONE_IE_MASK             (0x40U)
26101 #define CSI_CR18_FIELD0_DONE_IE_SHIFT            (6U)
26102 /*! FIELD0_DONE_IE
26103  *  0b0..Interrupt disabled
26104  *  0b1..Interrupt enabled
26105  */
26106 #define CSI_CR18_FIELD0_DONE_IE(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR18_FIELD0_DONE_IE_SHIFT)) & CSI_CR18_FIELD0_DONE_IE_MASK)
26107 
26108 #define CSI_CR18_DMA_FIELD1_DONE_IE_MASK         (0x80U)
26109 #define CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT        (7U)
26110 /*! DMA_FIELD1_DONE_IE
26111  *  0b0..Interrupt disabled
26112  *  0b1..Interrupt enabled
26113  */
26114 #define CSI_CR18_DMA_FIELD1_DONE_IE(x)           (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CR18_DMA_FIELD1_DONE_IE_MASK)
26115 
26116 #define CSI_CR18_LAST_DMA_REQ_SEL_MASK           (0x100U)
26117 #define CSI_CR18_LAST_DMA_REQ_SEL_SHIFT          (8U)
26118 /*! LAST_DMA_REQ_SEL
26119  *  0b0..fifo_full_level
26120  *  0b1..hburst_length
26121  */
26122 #define CSI_CR18_LAST_DMA_REQ_SEL(x)             (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CR18_LAST_DMA_REQ_SEL_MASK)
26123 
26124 #define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK   (0x200U)
26125 #define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT  (9U)
26126 /*! BASEADDR_CHANGE_ERROR_IE
26127  *  0b0..Interrupt disabled
26128  *  0b1..Interrupt enabled
26129  */
26130 #define CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x)     (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK)
26131 
26132 #define CSI_CR18_RGB888A_FORMAT_SEL_MASK         (0x400U)
26133 #define CSI_CR18_RGB888A_FORMAT_SEL_SHIFT        (10U)
26134 /*! RGB888A_FORMAT_SEL
26135  *  0b0..{8'h0, data[23:0]}
26136  *  0b1..{data[23:0], 8'h0}
26137  */
26138 #define CSI_CR18_RGB888A_FORMAT_SEL(x)           (((uint32_t)(((uint32_t)(x)) << CSI_CR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CR18_RGB888A_FORMAT_SEL_MASK)
26139 
26140 #define CSI_CR18_AHB_HPROT_MASK                  (0xF000U)
26141 #define CSI_CR18_AHB_HPROT_SHIFT                 (12U)
26142 #define CSI_CR18_AHB_HPROT(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR18_AHB_HPROT_SHIFT)) & CSI_CR18_AHB_HPROT_MASK)
26143 
26144 #define CSI_CR18_MASK_OPTION_MASK                (0xC0000U)
26145 #define CSI_CR18_MASK_OPTION_SHIFT               (18U)
26146 /*! MASK_OPTION
26147  *  0b00..Writing to memory (OCRAM or external DDR) from first completely frame, when using this option, the CSI_ENABLE should be 1.
26148  *  0b01..Writing to memory when CSI_ENABLE is 1.
26149  *  0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1.
26150  *  0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.
26151  */
26152 #define CSI_CR18_MASK_OPTION(x)                  (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MASK_OPTION_SHIFT)) & CSI_CR18_MASK_OPTION_MASK)
26153 
26154 #define CSI_CR18_MIPI_DOUBLE_CMPNT_MASK          (0x100000U)
26155 #define CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT         (20U)
26156 /*! MIPI_DOUBLE_CMPNT
26157  *  0b0..Single component per clock cycle (half pixel per clock cycle)
26158  *  0b1..Double component per clock cycle (a pixel per clock cycle)
26159  */
26160 #define CSI_CR18_MIPI_DOUBLE_CMPNT(x)            (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT)) & CSI_CR18_MIPI_DOUBLE_CMPNT_MASK)
26161 
26162 #define CSI_CR18_MIPI_YU_SWAP_MASK               (0x200000U)
26163 #define CSI_CR18_MIPI_YU_SWAP_SHIFT              (21U)
26164 /*! MIPI_YU_SWAP - It only works in MIPI CSI YUV422 double component mode. */
26165 #define CSI_CR18_MIPI_YU_SWAP(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_YU_SWAP_SHIFT)) & CSI_CR18_MIPI_YU_SWAP_MASK)
26166 
26167 #define CSI_CR18_DATA_FROM_MIPI_MASK             (0x400000U)
26168 #define CSI_CR18_DATA_FROM_MIPI_SHIFT            (22U)
26169 /*! DATA_FROM_MIPI
26170  *  0b0..Data from parallel sensor
26171  *  0b1..Data from MIPI
26172  */
26173 #define CSI_CR18_DATA_FROM_MIPI(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DATA_FROM_MIPI_SHIFT)) & CSI_CR18_DATA_FROM_MIPI_MASK)
26174 
26175 #define CSI_CR18_LINE_STRIDE_EN_MASK             (0x1000000U)
26176 #define CSI_CR18_LINE_STRIDE_EN_SHIFT            (24U)
26177 #define CSI_CR18_LINE_STRIDE_EN(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LINE_STRIDE_EN_SHIFT)) & CSI_CR18_LINE_STRIDE_EN_MASK)
26178 
26179 #define CSI_CR18_MIPI_DATA_FORMAT_MASK           (0x7E000000U)
26180 #define CSI_CR18_MIPI_DATA_FORMAT_SHIFT          (25U)
26181 /*! MIPI_DATA_FORMAT - Image Data Format */
26182 #define CSI_CR18_MIPI_DATA_FORMAT(x)             (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_DATA_FORMAT_SHIFT)) & CSI_CR18_MIPI_DATA_FORMAT_MASK)
26183 
26184 #define CSI_CR18_CSI_ENABLE_MASK                 (0x80000000U)
26185 #define CSI_CR18_CSI_ENABLE_SHIFT                (31U)
26186 #define CSI_CR18_CSI_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << CSI_CR18_CSI_ENABLE_SHIFT)) & CSI_CR18_CSI_ENABLE_MASK)
26187 /*! @} */
26188 
26189 /*! @name CR19 - CSI Control Register 19 */
26190 /*! @{ */
26191 
26192 #define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)
26193 #define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)
26194 #define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)
26195 /*! @} */
26196 
26197 /*! @name CR20 - CSI Control Register 20 */
26198 /*! @{ */
26199 
26200 #define CSI_CR20_THRESHOLD_MASK                  (0xFFU)
26201 #define CSI_CR20_THRESHOLD_SHIFT                 (0U)
26202 #define CSI_CR20_THRESHOLD(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR20_THRESHOLD_SHIFT)) & CSI_CR20_THRESHOLD_MASK)
26203 
26204 #define CSI_CR20_BINARY_EN_MASK                  (0x100U)
26205 #define CSI_CR20_BINARY_EN_SHIFT                 (8U)
26206 /*! BINARY_EN
26207  *  0b0..Output is Y8 format(8 bits each pixel)
26208  *  0b1..Output is Y1 format(1 bit each pixel)
26209  */
26210 #define CSI_CR20_BINARY_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR20_BINARY_EN_SHIFT)) & CSI_CR20_BINARY_EN_MASK)
26211 
26212 #define CSI_CR20_QR_DATA_FORMAT_MASK             (0xE00U)
26213 #define CSI_CR20_QR_DATA_FORMAT_SHIFT            (9U)
26214 /*! QR_DATA_FORMAT
26215  *  0b000..YU YV one cycle per 1 pixel input
26216  *  0b001..UY VY one cycle per1 pixel input
26217  *  0b010..Y U Y V two cycles per 1 pixel input
26218  *  0b011..U Y V Y two cycles per 1 pixel input
26219  *  0b100..YUV one cycle per 1 pixel input
26220  *  0b101..Y U V three cycles per 1 pixel input
26221  */
26222 #define CSI_CR20_QR_DATA_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << CSI_CR20_QR_DATA_FORMAT_SHIFT)) & CSI_CR20_QR_DATA_FORMAT_MASK)
26223 
26224 #define CSI_CR20_BIG_END_MASK                    (0x1000U)
26225 #define CSI_CR20_BIG_END_SHIFT                   (12U)
26226 /*! BIG_END
26227  *  0b0..The newest (most recent) data will be assigned the lowest position when store to memory.
26228  *  0b1..The newest (most recent) data will be assigned the highest position when store to memory.
26229  */
26230 #define CSI_CR20_BIG_END(x)                      (((uint32_t)(((uint32_t)(x)) << CSI_CR20_BIG_END_SHIFT)) & CSI_CR20_BIG_END_MASK)
26231 
26232 #define CSI_CR20_10BIT_NEW_EN_MASK               (0x20000000U)
26233 #define CSI_CR20_10BIT_NEW_EN_SHIFT              (29U)
26234 /*! 10BIT_NEW_EN
26235  *  0b0..When input 8bits data, it will use the data[9:2]
26236  *  0b1..If input is 10bits data, it will use the data[7:0] (optional)
26237  */
26238 #define CSI_CR20_10BIT_NEW_EN(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR20_10BIT_NEW_EN_SHIFT)) & CSI_CR20_10BIT_NEW_EN_MASK)
26239 
26240 #define CSI_CR20_HISTOGRAM_EN_MASK               (0x40000000U)
26241 #define CSI_CR20_HISTOGRAM_EN_SHIFT              (30U)
26242 /*! HISTOGRAM_EN
26243  *  0b0..Histogram disable
26244  *  0b1..Histogram enable
26245  */
26246 #define CSI_CR20_HISTOGRAM_EN(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR20_HISTOGRAM_EN_SHIFT)) & CSI_CR20_HISTOGRAM_EN_MASK)
26247 
26248 #define CSI_CR20_QRCODE_EN_MASK                  (0x80000000U)
26249 #define CSI_CR20_QRCODE_EN_SHIFT                 (31U)
26250 /*! QRCODE_EN
26251  *  0b0..Normal mode
26252  *  0b1..Gray scale mode
26253  */
26254 #define CSI_CR20_QRCODE_EN(x)                    (((uint32_t)(((uint32_t)(x)) << CSI_CR20_QRCODE_EN_SHIFT)) & CSI_CR20_QRCODE_EN_MASK)
26255 /*! @} */
26256 
26257 /*! @name CR - CSI Control Register */
26258 /*! @{ */
26259 
26260 #define CSI_CR_PIXEL_COUNTERS_MASK               (0xFFFFFFU)
26261 #define CSI_CR_PIXEL_COUNTERS_SHIFT              (0U)
26262 #define CSI_CR_PIXEL_COUNTERS(x)                 (((uint32_t)(((uint32_t)(x)) << CSI_CR_PIXEL_COUNTERS_SHIFT)) & CSI_CR_PIXEL_COUNTERS_MASK)
26263 /*! @} */
26264 
26265 /* The count of CSI_CR */
26266 #define CSI_CR_COUNT                             (256U)
26267 
26268 
26269 /*!
26270  * @}
26271  */ /* end of group CSI_Register_Masks */
26272 
26273 
26274 /* CSI - Peripheral instance base addresses */
26275 /** Peripheral CSI base address */
26276 #define CSI_BASE                                 (0x40800000u)
26277 /** Peripheral CSI base pointer */
26278 #define CSI                                      ((CSI_Type *)CSI_BASE)
26279 /** Array initializer of CSI peripheral base addresses */
26280 #define CSI_BASE_ADDRS                           { CSI_BASE }
26281 /** Array initializer of CSI peripheral base pointers */
26282 #define CSI_BASE_PTRS                            { CSI }
26283 /** Interrupt vectors for the CSI peripheral type */
26284 #define CSI_IRQS                                 { CSI_IRQn }
26285 /* Backward compatibility */
26286 #define CSI_CSICR1_PIXEL_BIT_MASK     CSI_CR1_PIXEL_BIT_MASK
26287 #define CSI_CSICR1_PIXEL_BIT_SHIFT     CSI_CR1_PIXEL_BIT_SHIFT
26288 #define CSI_CSICR1_PIXEL_BIT(x)     CSI_CR1_PIXEL_BIT(x)
26289 #define CSI_CSICR1_REDGE_MASK     CSI_CR1_REDGE_MASK
26290 #define CSI_CSICR1_REDGE_SHIFT     CSI_CR1_REDGE_SHIFT
26291 #define CSI_CSICR1_REDGE(x)     CSI_CR1_REDGE(x)
26292 #define CSI_CSICR1_INV_PCLK_MASK     CSI_CR1_INV_PCLK_MASK
26293 #define CSI_CSICR1_INV_PCLK_SHIFT     CSI_CR1_INV_PCLK_SHIFT
26294 #define CSI_CSICR1_INV_PCLK(x)     CSI_CR1_INV_PCLK(x)
26295 #define CSI_CSICR1_INV_DATA_MASK     CSI_CR1_INV_DATA_MASK
26296 #define CSI_CSICR1_INV_DATA_SHIFT     CSI_CR1_INV_DATA_SHIFT
26297 #define CSI_CSICR1_INV_DATA(x)     CSI_CR1_INV_DATA(x)
26298 #define CSI_CSICR1_GCLK_MODE_MASK     CSI_CR1_GCLK_MODE_MASK
26299 #define CSI_CSICR1_GCLK_MODE_SHIFT     CSI_CR1_GCLK_MODE_SHIFT
26300 #define CSI_CSICR1_GCLK_MODE(x)     CSI_CR1_GCLK_MODE(x)
26301 #define CSI_CSICR1_CLR_RXFIFO_MASK     CSI_CR1_CLR_RXFIFO_MASK
26302 #define CSI_CSICR1_CLR_RXFIFO_SHIFT     CSI_CR1_CLR_RXFIFO_SHIFT
26303 #define CSI_CSICR1_CLR_RXFIFO(x)     CSI_CR1_CLR_RXFIFO(x)
26304 #define CSI_CSICR1_CLR_STATFIFO_MASK     CSI_CR1_CLR_STATFIFO_MASK
26305 #define CSI_CSICR1_CLR_STATFIFO_SHIFT     CSI_CR1_CLR_STATFIFO_SHIFT
26306 #define CSI_CSICR1_CLR_STATFIFO(x)     CSI_CR1_CLR_STATFIFO(x)
26307 #define CSI_CSICR1_PACK_DIR_MASK     CSI_CR1_PACK_DIR_MASK
26308 #define CSI_CSICR1_PACK_DIR_SHIFT     CSI_CR1_PACK_DIR_SHIFT
26309 #define CSI_CSICR1_PACK_DIR(x)     CSI_CR1_PACK_DIR(x)
26310 #define CSI_CSICR1_FCC_MASK     CSI_CR1_FCC_MASK
26311 #define CSI_CSICR1_FCC_SHIFT     CSI_CR1_FCC_SHIFT
26312 #define CSI_CSICR1_FCC(x)     CSI_CR1_FCC(x)
26313 #define CSI_CSICR1_CCIR_EN_MASK     CSI_CR1_CCIR_EN_MASK
26314 #define CSI_CSICR1_CCIR_EN_SHIFT     CSI_CR1_CCIR_EN_SHIFT
26315 #define CSI_CSICR1_CCIR_EN(x)     CSI_CR1_CCIR_EN(x)
26316 #define CSI_CSICR1_HSYNC_POL_MASK     CSI_CR1_HSYNC_POL_MASK
26317 #define CSI_CSICR1_HSYNC_POL_SHIFT     CSI_CR1_HSYNC_POL_SHIFT
26318 #define CSI_CSICR1_HSYNC_POL(x)     CSI_CR1_HSYNC_POL(x)
26319 #define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_MASK     CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK
26320 #define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_SHIFT     CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT
26321 #define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE(x)     CSI_CR1_HISTOGRAM_CALC_DONE_IE(x)
26322 #define CSI_CSICR1_SOF_INTEN_MASK     CSI_CR1_SOF_INTEN_MASK
26323 #define CSI_CSICR1_SOF_INTEN_SHIFT     CSI_CR1_SOF_INTEN_SHIFT
26324 #define CSI_CSICR1_SOF_INTEN(x)     CSI_CR1_SOF_INTEN(x)
26325 #define CSI_CSICR1_SOF_POL_MASK     CSI_CR1_SOF_POL_MASK
26326 #define CSI_CSICR1_SOF_POL_SHIFT     CSI_CR1_SOF_POL_SHIFT
26327 #define CSI_CSICR1_SOF_POL(x)     CSI_CR1_SOF_POL(x)
26328 #define CSI_CSICR1_RXFF_INTEN_MASK     CSI_CR1_RXFF_INTEN_MASK
26329 #define CSI_CSICR1_RXFF_INTEN_SHIFT     CSI_CR1_RXFF_INTEN_SHIFT
26330 #define CSI_CSICR1_RXFF_INTEN(x)     CSI_CR1_RXFF_INTEN(x)
26331 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK     CSI_CR1_FB1_DMA_DONE_INTEN_MASK
26332 #define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT     CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT
26333 #define CSI_CSICR1_FB1_DMA_DONE_INTEN(x)     CSI_CR1_FB1_DMA_DONE_INTEN(x)
26334 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK     CSI_CR1_FB2_DMA_DONE_INTEN_MASK
26335 #define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT     CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT
26336 #define CSI_CSICR1_FB2_DMA_DONE_INTEN(x)     CSI_CR1_FB2_DMA_DONE_INTEN(x)
26337 #define CSI_CSICR1_STATFF_INTEN_MASK     CSI_CR1_STATFF_INTEN_MASK
26338 #define CSI_CSICR1_STATFF_INTEN_SHIFT     CSI_CR1_STATFF_INTEN_SHIFT
26339 #define CSI_CSICR1_STATFF_INTEN(x)     CSI_CR1_STATFF_INTEN(x)
26340 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK     CSI_CR1_SFF_DMA_DONE_INTEN_MASK
26341 #define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT     CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT
26342 #define CSI_CSICR1_SFF_DMA_DONE_INTEN(x)     CSI_CR1_SFF_DMA_DONE_INTEN(x)
26343 #define CSI_CSICR1_RF_OR_INTEN_MASK     CSI_CR1_RF_OR_INTEN_MASK
26344 #define CSI_CSICR1_RF_OR_INTEN_SHIFT     CSI_CR1_RF_OR_INTEN_SHIFT
26345 #define CSI_CSICR1_RF_OR_INTEN(x)     CSI_CR1_RF_OR_INTEN(x)
26346 #define CSI_CSICR1_SF_OR_INTEN_MASK     CSI_CR1_SF_OR_INTEN_MASK
26347 #define CSI_CSICR1_SF_OR_INTEN_SHIFT     CSI_CR1_SF_OR_INTEN_SHIFT
26348 #define CSI_CSICR1_SF_OR_INTEN(x)     CSI_CR1_SF_OR_INTEN(x)
26349 #define CSI_CSICR1_COF_INT_EN_MASK     CSI_CR1_COF_INT_EN_MASK
26350 #define CSI_CSICR1_COF_INT_EN_SHIFT     CSI_CR1_COF_INT_EN_SHIFT
26351 #define CSI_CSICR1_COF_INT_EN(x)     CSI_CR1_COF_INT_EN(x)
26352 #define CSI_CSICR1_VIDEO_MODE_MASK     CSI_CR1_VIDEO_MODE_MASK
26353 #define CSI_CSICR1_VIDEO_MODE_SHIFT     CSI_CR1_VIDEO_MODE_SHIFT
26354 #define CSI_CSICR1_VIDEO_MODE(x)     CSI_CR1_VIDEO_MODE(x)
26355 #define CSI_CSICR1_EOF_INT_EN_MASK     CSI_CR1_EOF_INT_EN_MASK
26356 #define CSI_CSICR1_EOF_INT_EN_SHIFT     CSI_CR1_EOF_INT_EN_SHIFT
26357 #define CSI_CSICR1_EOF_INT_EN(x)     CSI_CR1_EOF_INT_EN(x)
26358 #define CSI_CSICR1_EXT_VSYNC_MASK     CSI_CR1_EXT_VSYNC_MASK
26359 #define CSI_CSICR1_EXT_VSYNC_SHIFT     CSI_CR1_EXT_VSYNC_SHIFT
26360 #define CSI_CSICR1_EXT_VSYNC(x)     CSI_CR1_EXT_VSYNC(x)
26361 #define CSI_CSICR1_SWAP16_EN_MASK     CSI_CR1_SWAP16_EN_MASK
26362 #define CSI_CSICR1_SWAP16_EN_SHIFT     CSI_CR1_SWAP16_EN_SHIFT
26363 #define CSI_CSICR1_SWAP16_EN(x)     CSI_CR1_SWAP16_EN(x)
26364 #define CSI_CSICR2_HSC_MASK     CSI_CR2_HSC_MASK
26365 #define CSI_CSICR2_HSC_SHIFT     CSI_CR2_HSC_SHIFT
26366 #define CSI_CSICR2_HSC(x)     CSI_CR2_HSC(x)
26367 #define CSI_CSICR2_VSC_MASK     CSI_CR2_VSC_MASK
26368 #define CSI_CSICR2_VSC_SHIFT     CSI_CR2_VSC_SHIFT
26369 #define CSI_CSICR2_VSC(x)     CSI_CR2_VSC(x)
26370 #define CSI_CSICR2_LVRM_MASK     CSI_CR2_LVRM_MASK
26371 #define CSI_CSICR2_LVRM_SHIFT     CSI_CR2_LVRM_SHIFT
26372 #define CSI_CSICR2_LVRM(x)     CSI_CR2_LVRM(x)
26373 #define CSI_CSICR2_BTS_MASK     CSI_CR2_BTS_MASK
26374 #define CSI_CSICR2_BTS_SHIFT     CSI_CR2_BTS_SHIFT
26375 #define CSI_CSICR2_BTS(x)     CSI_CR2_BTS(x)
26376 #define CSI_CSICR2_SCE_MASK     CSI_CR2_SCE_MASK
26377 #define CSI_CSICR2_SCE_SHIFT     CSI_CR2_SCE_SHIFT
26378 #define CSI_CSICR2_SCE(x)     CSI_CR2_SCE(x)
26379 #define CSI_CSICR2_AFS_MASK     CSI_CR2_AFS_MASK
26380 #define CSI_CSICR2_AFS_SHIFT     CSI_CR2_AFS_SHIFT
26381 #define CSI_CSICR2_AFS(x)     CSI_CR2_AFS(x)
26382 #define CSI_CSICR2_DRM_MASK     CSI_CR2_DRM_MASK
26383 #define CSI_CSICR2_DRM_SHIFT     CSI_CR2_DRM_SHIFT
26384 #define CSI_CSICR2_DRM(x)     CSI_CR2_DRM(x)
26385 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK     CSI_CR2_DMA_BURST_TYPE_SFF_MASK
26386 #define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT     CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT
26387 #define CSI_CSICR2_DMA_BURST_TYPE_SFF(x)     CSI_CR2_DMA_BURST_TYPE_SFF(x)
26388 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK     CSI_CR2_DMA_BURST_TYPE_RFF_MASK
26389 #define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT     CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT
26390 #define CSI_CSICR2_DMA_BURST_TYPE_RFF(x)     CSI_CR2_DMA_BURST_TYPE_RFF(x)
26391 #define CSI_CSICR3_ECC_AUTO_EN_MASK     CSI_CR3_ECC_AUTO_EN_MASK
26392 #define CSI_CSICR3_ECC_AUTO_EN_SHIFT     CSI_CR3_ECC_AUTO_EN_SHIFT
26393 #define CSI_CSICR3_ECC_AUTO_EN(x)     CSI_CR3_ECC_AUTO_EN(x)
26394 #define CSI_CSICR3_ECC_INT_EN_MASK     CSI_CR3_ECC_INT_EN_MASK
26395 #define CSI_CSICR3_ECC_INT_EN_SHIFT     CSI_CR3_ECC_INT_EN_SHIFT
26396 #define CSI_CSICR3_ECC_INT_EN(x)     CSI_CR3_ECC_INT_EN(x)
26397 #define CSI_CSICR3_ZERO_PACK_EN_MASK     CSI_CR3_ZERO_PACK_EN_MASK
26398 #define CSI_CSICR3_ZERO_PACK_EN_SHIFT     CSI_CR3_ZERO_PACK_EN_SHIFT
26399 #define CSI_CSICR3_ZERO_PACK_EN(x)     CSI_CR3_ZERO_PACK_EN(x)
26400 #define CSI_CSICR3_SENSOR_16BITS_MASK     CSI_CR3_SENSOR_16BITS_MASK
26401 #define CSI_CSICR3_SENSOR_16BITS_SHIFT     CSI_CR3_SENSOR_16BITS_SHIFT
26402 #define CSI_CSICR3_SENSOR_16BITS(x)     CSI_CR3_SENSOR_16BITS(x)
26403 #define CSI_CSICR3_RxFF_LEVEL_MASK     CSI_CR3_RxFF_LEVEL_MASK
26404 #define CSI_CSICR3_RxFF_LEVEL_SHIFT     CSI_CR3_RxFF_LEVEL_SHIFT
26405 #define CSI_CSICR3_RxFF_LEVEL(x)     CSI_CR3_RxFF_LEVEL(x)
26406 #define CSI_CSICR3_HRESP_ERR_EN_MASK     CSI_CR3_HRESP_ERR_EN_MASK
26407 #define CSI_CSICR3_HRESP_ERR_EN_SHIFT     CSI_CR3_HRESP_ERR_EN_SHIFT
26408 #define CSI_CSICR3_HRESP_ERR_EN(x)     CSI_CR3_HRESP_ERR_EN(x)
26409 #define CSI_CSICR3_STATFF_LEVEL_MASK     CSI_CR3_STATFF_LEVEL_MASK
26410 #define CSI_CSICR3_STATFF_LEVEL_SHIFT     CSI_CR3_STATFF_LEVEL_SHIFT
26411 #define CSI_CSICR3_STATFF_LEVEL(x)     CSI_CR3_STATFF_LEVEL(x)
26412 #define CSI_CSICR3_DMA_REQ_EN_SFF_MASK     CSI_CR3_DMA_REQ_EN_SFF_MASK
26413 #define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT     CSI_CR3_DMA_REQ_EN_SFF_SHIFT
26414 #define CSI_CSICR3_DMA_REQ_EN_SFF(x)     CSI_CR3_DMA_REQ_EN_SFF(x)
26415 #define CSI_CSICR3_DMA_REQ_EN_RFF_MASK     CSI_CR3_DMA_REQ_EN_RFF_MASK
26416 #define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT     CSI_CR3_DMA_REQ_EN_RFF_SHIFT
26417 #define CSI_CSICR3_DMA_REQ_EN_RFF(x)     CSI_CR3_DMA_REQ_EN_RFF(x)
26418 #define CSI_CSICR3_DMA_REFLASH_SFF_MASK     CSI_CR3_DMA_REFLASH_SFF_MASK
26419 #define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT     CSI_CR3_DMA_REFLASH_SFF_SHIFT
26420 #define CSI_CSICR3_DMA_REFLASH_SFF(x)     CSI_CR3_DMA_REFLASH_SFF(x)
26421 #define CSI_CSICR3_DMA_REFLASH_RFF_MASK     CSI_CR3_DMA_REFLASH_RFF_MASK
26422 #define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT     CSI_CR3_DMA_REFLASH_RFF_SHIFT
26423 #define CSI_CSICR3_DMA_REFLASH_RFF(x)     CSI_CR3_DMA_REFLASH_RFF(x)
26424 #define CSI_CSICR3_FRMCNT_RST_MASK     CSI_CR3_FRMCNT_RST_MASK
26425 #define CSI_CSICR3_FRMCNT_RST_SHIFT     CSI_CR3_FRMCNT_RST_SHIFT
26426 #define CSI_CSICR3_FRMCNT_RST(x)     CSI_CR3_FRMCNT_RST(x)
26427 #define CSI_CSICR3_FRMCNT_MASK     CSI_CR3_FRMCNT_MASK
26428 #define CSI_CSICR3_FRMCNT_SHIFT     CSI_CR3_FRMCNT_SHIFT
26429 #define CSI_CSICR3_FRMCNT(x)     CSI_CR3_FRMCNT(x)
26430 #define CSI_CSISTATFIFO_STAT_MASK     CSI_STATFIFO_STAT_MASK
26431 #define CSI_CSISTATFIFO_STAT_SHIFT     CSI_STATFIFO_STAT_SHIFT
26432 #define CSI_CSISTATFIFO_STAT(x)     CSI_STATFIFO_STAT(x)
26433 #define CSI_CSIRFIFO_IMAGE_MASK     CSI_RFIFO_IMAGE_MASK
26434 #define CSI_CSIRFIFO_IMAGE_SHIFT     CSI_RFIFO_IMAGE_SHIFT
26435 #define CSI_CSIRFIFO_IMAGE(x)     CSI_RFIFO_IMAGE(x)
26436 #define CSI_CSIRXCNT_RXCNT_MASK     CSI_RXCNT_RXCNT_MASK
26437 #define CSI_CSIRXCNT_RXCNT_SHIFT     CSI_RXCNT_RXCNT_SHIFT
26438 #define CSI_CSIRXCNT_RXCNT(x)     CSI_RXCNT_RXCNT(x)
26439 #define CSI_CSISR_DRDY_MASK     CSI_SR_DRDY_MASK
26440 #define CSI_CSISR_DRDY_SHIFT     CSI_SR_DRDY_SHIFT
26441 #define CSI_CSISR_DRDY(x)     CSI_SR_DRDY(x)
26442 #define CSI_CSISR_ECC_INT_MASK     CSI_SR_ECC_INT_MASK
26443 #define CSI_CSISR_ECC_INT_SHIFT     CSI_SR_ECC_INT_SHIFT
26444 #define CSI_CSISR_ECC_INT(x)     CSI_SR_ECC_INT(x)
26445 #define CSI_CSISR_HISTOGRAM_CALC_DONE_INT_MASK     CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK
26446 #define CSI_CSISR_HISTOGRAM_CALC_DONE_INT_SHIFT     CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT
26447 #define CSI_CSISR_HISTOGRAM_CALC_DONE_INT(x)     CSI_SR_HISTOGRAM_CALC_DONE_INT(x)
26448 #define CSI_CSISR_HRESP_ERR_INT_MASK     CSI_SR_HRESP_ERR_INT_MASK
26449 #define CSI_CSISR_HRESP_ERR_INT_SHIFT     CSI_SR_HRESP_ERR_INT_SHIFT
26450 #define CSI_CSISR_HRESP_ERR_INT(x)     CSI_SR_HRESP_ERR_INT(x)
26451 #define CSI_CSISR_COF_INT_MASK     CSI_SR_COF_INT_MASK
26452 #define CSI_CSISR_COF_INT_SHIFT     CSI_SR_COF_INT_SHIFT
26453 #define CSI_CSISR_COF_INT(x)     CSI_SR_COF_INT(x)
26454 #define CSI_CSISR_F1_INT_MASK     CSI_SR_F1_INT_MASK
26455 #define CSI_CSISR_F1_INT_SHIFT     CSI_SR_F1_INT_SHIFT
26456 #define CSI_CSISR_F1_INT(x)     CSI_SR_F1_INT(x)
26457 #define CSI_CSISR_F2_INT_MASK     CSI_SR_F2_INT_MASK
26458 #define CSI_CSISR_F2_INT_SHIFT     CSI_SR_F2_INT_SHIFT
26459 #define CSI_CSISR_F2_INT(x)     CSI_SR_F2_INT(x)
26460 #define CSI_CSISR_SOF_INT_MASK     CSI_SR_SOF_INT_MASK
26461 #define CSI_CSISR_SOF_INT_SHIFT     CSI_SR_SOF_INT_SHIFT
26462 #define CSI_CSISR_SOF_INT(x)     CSI_SR_SOF_INT(x)
26463 #define CSI_CSISR_EOF_INT_MASK     CSI_SR_EOF_INT_MASK
26464 #define CSI_CSISR_EOF_INT_SHIFT     CSI_SR_EOF_INT_SHIFT
26465 #define CSI_CSISR_EOF_INT(x)     CSI_SR_EOF_INT(x)
26466 #define CSI_CSISR_RxFF_INT_MASK     CSI_SR_RxFF_INT_MASK
26467 #define CSI_CSISR_RxFF_INT_SHIFT     CSI_SR_RxFF_INT_SHIFT
26468 #define CSI_CSISR_RxFF_INT(x)     CSI_SR_RxFF_INT(x)
26469 #define CSI_CSISR_DMA_TSF_DONE_FB1_MASK     CSI_SR_DMA_TSF_DONE_FB1_MASK
26470 #define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT     CSI_SR_DMA_TSF_DONE_FB1_SHIFT
26471 #define CSI_CSISR_DMA_TSF_DONE_FB1(x)     CSI_SR_DMA_TSF_DONE_FB1(x)
26472 #define CSI_CSISR_DMA_TSF_DONE_FB2_MASK     CSI_SR_DMA_TSF_DONE_FB2_MASK
26473 #define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT     CSI_SR_DMA_TSF_DONE_FB2_SHIFT
26474 #define CSI_CSISR_DMA_TSF_DONE_FB2(x)     CSI_SR_DMA_TSF_DONE_FB2(x)
26475 #define CSI_CSISR_STATFF_INT_MASK     CSI_SR_STATFF_INT_MASK
26476 #define CSI_CSISR_STATFF_INT_SHIFT     CSI_SR_STATFF_INT_SHIFT
26477 #define CSI_CSISR_STATFF_INT(x)     CSI_SR_STATFF_INT(x)
26478 #define CSI_CSISR_DMA_TSF_DONE_SFF_MASK     CSI_SR_DMA_TSF_DONE_SFF_MASK
26479 #define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT     CSI_SR_DMA_TSF_DONE_SFF_SHIFT
26480 #define CSI_CSISR_DMA_TSF_DONE_SFF(x)     CSI_SR_DMA_TSF_DONE_SFF(x)
26481 #define CSI_CSISR_RF_OR_INT_MASK     CSI_SR_RF_OR_INT_MASK
26482 #define CSI_CSISR_RF_OR_INT_SHIFT     CSI_SR_RF_OR_INT_SHIFT
26483 #define CSI_CSISR_RF_OR_INT(x)     CSI_SR_RF_OR_INT(x)
26484 #define CSI_CSISR_SF_OR_INT_MASK     CSI_SR_SF_OR_INT_MASK
26485 #define CSI_CSISR_SF_OR_INT_SHIFT     CSI_SR_SF_OR_INT_SHIFT
26486 #define CSI_CSISR_SF_OR_INT(x)     CSI_SR_SF_OR_INT(x)
26487 #define CSI_CSISR_DMA_FIELD1_DONE_MASK     CSI_SR_DMA_FIELD1_DONE_MASK
26488 #define CSI_CSISR_DMA_FIELD1_DONE_SHIFT     CSI_SR_DMA_FIELD1_DONE_SHIFT
26489 #define CSI_CSISR_DMA_FIELD1_DONE(x)     CSI_SR_DMA_FIELD1_DONE(x)
26490 #define CSI_CSISR_DMA_FIELD0_DONE_MASK     CSI_SR_DMA_FIELD0_DONE_MASK
26491 #define CSI_CSISR_DMA_FIELD0_DONE_SHIFT     CSI_SR_DMA_FIELD0_DONE_SHIFT
26492 #define CSI_CSISR_DMA_FIELD0_DONE(x)     CSI_SR_DMA_FIELD0_DONE(x)
26493 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK     CSI_SR_BASEADDR_CHHANGE_ERROR_MASK
26494 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT     CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT
26495 #define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x)     CSI_SR_BASEADDR_CHHANGE_ERROR(x)
26496 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK     CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK
26497 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT     CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT
26498 #define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x)     CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x)
26499 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK     CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK
26500 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT     CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT
26501 #define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x)     CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x)
26502 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK     CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK
26503 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT     CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT
26504 #define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x)     CSI_DMASA_FB1_DMA_START_ADDR_FB1(x)
26505 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK     CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK
26506 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT     CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT
26507 #define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x)     CSI_DMASA_FB2_DMA_START_ADDR_FB2(x)
26508 #define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK     CSI_FBUF_PARA_FBUF_STRIDE_MASK
26509 #define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT     CSI_FBUF_PARA_FBUF_STRIDE_SHIFT
26510 #define CSI_CSIFBUF_PARA_FBUF_STRIDE(x)     CSI_FBUF_PARA_FBUF_STRIDE(x)
26511 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK     CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK
26512 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT     CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT
26513 #define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x)     CSI_FBUF_PARA_DEINTERLACE_STRIDE(x)
26514 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK     CSI_IMAG_PARA_IMAGE_HEIGHT_MASK
26515 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT     CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT
26516 #define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x)     CSI_IMAG_PARA_IMAGE_HEIGHT(x)
26517 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK     CSI_IMAG_PARA_IMAGE_WIDTH_MASK
26518 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT     CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT
26519 #define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x)     CSI_IMAG_PARA_IMAGE_WIDTH(x)
26520 #define CSI_CSICR18_NTSC_EN_MASK     CSI_CR18_NTSC_EN_MASK
26521 #define CSI_CSICR18_NTSC_EN_SHIFT     CSI_CR18_NTSC_EN_SHIFT
26522 #define CSI_CSICR18_NTSC_EN(x)     CSI_CR18_NTSC_EN(x)
26523 #define CSI_CSICR18_TVDECODER_IN_EN_MASK     CSI_CR18_TVDECODER_IN_EN_MASK
26524 #define CSI_CSICR18_TVDECODER_IN_EN_SHIFT     CSI_CR18_TVDECODER_IN_EN_SHIFT
26525 #define CSI_CSICR18_TVDECODER_IN_EN(x)     CSI_CR18_TVDECODER_IN_EN(x)
26526 #define CSI_CSICR18_DEINTERLACE_EN_MASK     CSI_CR18_DEINTERLACE_EN_MASK
26527 #define CSI_CSICR18_DEINTERLACE_EN_SHIFT     CSI_CR18_DEINTERLACE_EN_SHIFT
26528 #define CSI_CSICR18_DEINTERLACE_EN(x)     CSI_CR18_DEINTERLACE_EN(x)
26529 #define CSI_CSICR18_PARALLEL24_EN_MASK     CSI_CR18_PARALLEL24_EN_MASK
26530 #define CSI_CSICR18_PARALLEL24_EN_SHIFT     CSI_CR18_PARALLEL24_EN_SHIFT
26531 #define CSI_CSICR18_PARALLEL24_EN(x)     CSI_CR18_PARALLEL24_EN(x)
26532 #define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK     CSI_CR18_BASEADDR_SWITCH_EN_MASK
26533 #define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT     CSI_CR18_BASEADDR_SWITCH_EN_SHIFT
26534 #define CSI_CSICR18_BASEADDR_SWITCH_EN(x)     CSI_CR18_BASEADDR_SWITCH_EN(x)
26535 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK     CSI_CR18_BASEADDR_SWITCH_SEL_MASK
26536 #define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT     CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT
26537 #define CSI_CSICR18_BASEADDR_SWITCH_SEL(x)     CSI_CR18_BASEADDR_SWITCH_SEL(x)
26538 #define CSI_CSICR18_FIELD0_DONE_IE_MASK     CSI_CR18_FIELD0_DONE_IE_MASK
26539 #define CSI_CSICR18_FIELD0_DONE_IE_SHIFT     CSI_CR18_FIELD0_DONE_IE_SHIFT
26540 #define CSI_CSICR18_FIELD0_DONE_IE(x)     CSI_CR18_FIELD0_DONE_IE(x)
26541 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK     CSI_CR18_DMA_FIELD1_DONE_IE_MASK
26542 #define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT     CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT
26543 #define CSI_CSICR18_DMA_FIELD1_DONE_IE(x)     CSI_CR18_DMA_FIELD1_DONE_IE(x)
26544 #define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK     CSI_CR18_LAST_DMA_REQ_SEL_MASK
26545 #define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT     CSI_CR18_LAST_DMA_REQ_SEL_SHIFT
26546 #define CSI_CSICR18_LAST_DMA_REQ_SEL(x)     CSI_CR18_LAST_DMA_REQ_SEL(x)
26547 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK     CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK
26548 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT     CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT
26549 #define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x)     CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x)
26550 #define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK     CSI_CR18_RGB888A_FORMAT_SEL_MASK
26551 #define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT     CSI_CR18_RGB888A_FORMAT_SEL_SHIFT
26552 #define CSI_CSICR18_RGB888A_FORMAT_SEL(x)     CSI_CR18_RGB888A_FORMAT_SEL(x)
26553 #define CSI_CSICR18_AHB_HPROT_MASK     CSI_CR18_AHB_HPROT_MASK
26554 #define CSI_CSICR18_AHB_HPROT_SHIFT     CSI_CR18_AHB_HPROT_SHIFT
26555 #define CSI_CSICR18_AHB_HPROT(x)     CSI_CR18_AHB_HPROT(x)
26556 #define CSI_CSICR18_MASK_OPTION_MASK     CSI_CR18_MASK_OPTION_MASK
26557 #define CSI_CSICR18_MASK_OPTION_SHIFT     CSI_CR18_MASK_OPTION_SHIFT
26558 #define CSI_CSICR18_MASK_OPTION(x)     CSI_CR18_MASK_OPTION(x)
26559 #define CSI_CSICR18_MIPI_DOUBLE_CMPNT_MASK     CSI_CR18_MIPI_DOUBLE_CMPNT_MASK
26560 #define CSI_CSICR18_MIPI_DOUBLE_CMPNT_SHIFT     CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT
26561 #define CSI_CSICR18_MIPI_DOUBLE_CMPNT(x)     CSI_CR18_MIPI_DOUBLE_CMPNT(x)
26562 #define CSI_CSICR18_MIPI_YU_SWAP_MASK     CSI_CR18_MIPI_YU_SWAP_MASK
26563 #define CSI_CSICR18_MIPI_YU_SWAP_SHIFT     CSI_CR18_MIPI_YU_SWAP_SHIFT
26564 #define CSI_CSICR18_MIPI_YU_SWAP(x)     CSI_CR18_MIPI_YU_SWAP(x)
26565 #define CSI_CSICR18_DATA_FROM_MIPI_MASK     CSI_CR18_DATA_FROM_MIPI_MASK
26566 #define CSI_CSICR18_DATA_FROM_MIPI_SHIFT     CSI_CR18_DATA_FROM_MIPI_SHIFT
26567 #define CSI_CSICR18_DATA_FROM_MIPI(x)     CSI_CR18_DATA_FROM_MIPI(x)
26568 #define CSI_CSICR18_LINE_STRIDE_EN_MASK     CSI_CR18_LINE_STRIDE_EN_MASK
26569 #define CSI_CSICR18_LINE_STRIDE_EN_SHIFT     CSI_CR18_LINE_STRIDE_EN_SHIFT
26570 #define CSI_CSICR18_LINE_STRIDE_EN(x)     CSI_CR18_LINE_STRIDE_EN(x)
26571 #define CSI_CSICR18_MIPI_DATA_FORMAT_MASK     CSI_CR18_MIPI_DATA_FORMAT_MASK
26572 #define CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT     CSI_CR18_MIPI_DATA_FORMAT_SHIFT
26573 #define CSI_CSICR18_MIPI_DATA_FORMAT(x)     CSI_CR18_MIPI_DATA_FORMAT(x)
26574 #define CSI_CSICR18_CSI_ENABLE_MASK     CSI_CR18_CSI_ENABLE_MASK
26575 #define CSI_CSICR18_CSI_ENABLE_SHIFT     CSI_CR18_CSI_ENABLE_SHIFT
26576 #define CSI_CSICR18_CSI_ENABLE(x)     CSI_CR18_CSI_ENABLE(x)
26577 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK     CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK
26578 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT     CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT
26579 #define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x)     CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x)
26580 #define CSI_CSICR20_THRESHOLD_MASK     CSI_CR20_THRESHOLD_MASK
26581 #define CSI_CSICR20_THRESHOLD_SHIFT     CSI_CR20_THRESHOLD_SHIFT
26582 #define CSI_CSICR20_THRESHOLD(x)     CSI_CR20_THRESHOLD(x)
26583 #define CSI_CSICR20_BINARY_EN_MASK     CSI_CR20_BINARY_EN_MASK
26584 #define CSI_CSICR20_BINARY_EN_SHIFT     CSI_CR20_BINARY_EN_SHIFT
26585 #define CSI_CSICR20_BINARY_EN(x)     CSI_CR20_BINARY_EN(x)
26586 #define CSI_CSICR20_QR_DATA_FORMAT_MASK     CSI_CR20_QR_DATA_FORMAT_MASK
26587 #define CSI_CSICR20_QR_DATA_FORMAT_SHIFT     CSI_CR20_QR_DATA_FORMAT_SHIFT
26588 #define CSI_CSICR20_QR_DATA_FORMAT(x)     CSI_CR20_QR_DATA_FORMAT(x)
26589 #define CSI_CSICR20_BIG_END_MASK     CSI_CR20_BIG_END_MASK
26590 #define CSI_CSICR20_BIG_END_SHIFT     CSI_CR20_BIG_END_SHIFT
26591 #define CSI_CSICR20_BIG_END(x)     CSI_CR20_BIG_END(x)
26592 #define CSI_CSICR20_10BIT_NEW_EN_MASK     CSI_CR20_10BIT_NEW_EN_MASK
26593 #define CSI_CSICR20_10BIT_NEW_EN_SHIFT     CSI_CR20_10BIT_NEW_EN_SHIFT
26594 #define CSI_CSICR20_10BIT_NEW_EN(x)     CSI_CR20_10BIT_NEW_EN(x)
26595 #define CSI_CSICR20_HISTOGRAM_EN_MASK     CSI_CR20_HISTOGRAM_EN_MASK
26596 #define CSI_CSICR20_HISTOGRAM_EN_SHIFT     CSI_CR20_HISTOGRAM_EN_SHIFT
26597 #define CSI_CSICR20_HISTOGRAM_EN(x)     CSI_CR20_HISTOGRAM_EN(x)
26598 #define CSI_CSICR20_QRCODE_EN_MASK     CSI_CR20_QRCODE_EN_MASK
26599 #define CSI_CSICR20_QRCODE_EN_SHIFT     CSI_CR20_QRCODE_EN_SHIFT
26600 #define CSI_CSICR20_QRCODE_EN(x)     CSI_CR20_QRCODE_EN(x)
26601 #define CSI_CSICR21_PIXEL_COUNTERS_MASK     CSI_CR21_PIXEL_COUNTERS_MASK
26602 #define CSI_CSICR21_PIXEL_COUNTERS_SHIFT     CSI_CR21_PIXEL_COUNTERS_SHIFT
26603 #define CSI_CSICR21_PIXEL_COUNTERS(x)     CSI_CR21_PIXEL_COUNTERS(x)
26604 #define CSI_CSICR22_PIXEL_COUNTERS_MASK     CSI_CR22_PIXEL_COUNTERS_MASK
26605 #define CSI_CSICR22_PIXEL_COUNTERS_SHIFT     CSI_CR22_PIXEL_COUNTERS_SHIFT
26606 #define CSI_CSICR22_PIXEL_COUNTERS(x)     CSI_CR22_PIXEL_COUNTERS(x)
26607 #define CSI_CSICR23_PIXEL_COUNTERS_MASK     CSI_CR23_PIXEL_COUNTERS_MASK
26608 #define CSI_CSICR23_PIXEL_COUNTERS_SHIFT     CSI_CR23_PIXEL_COUNTERS_SHIFT
26609 #define CSI_CSICR23_PIXEL_COUNTERS(x)     CSI_CR23_PIXEL_COUNTERS(x)
26610 #define CSI_CSICR24_PIXEL_COUNTERS_MASK     CSI_CR24_PIXEL_COUNTERS_MASK
26611 #define CSI_CSICR24_PIXEL_COUNTERS_SHIFT     CSI_CR24_PIXEL_COUNTERS_SHIFT
26612 #define CSI_CSICR24_PIXEL_COUNTERS(x)     CSI_CR24_PIXEL_COUNTERS(x)
26613 #define CSI_CSICR25_PIXEL_COUNTERS_MASK     CSI_CR25_PIXEL_COUNTERS_MASK
26614 #define CSI_CSICR25_PIXEL_COUNTERS_SHIFT     CSI_CR25_PIXEL_COUNTERS_SHIFT
26615 #define CSI_CSICR25_PIXEL_COUNTERS(x)     CSI_CR25_PIXEL_COUNTERS(x)
26616 #define CSI_CSICR26_PIXEL_COUNTERS_MASK     CSI_CR26_PIXEL_COUNTERS_MASK
26617 #define CSI_CSICR26_PIXEL_COUNTERS_SHIFT     CSI_CR26_PIXEL_COUNTERS_SHIFT
26618 #define CSI_CSICR26_PIXEL_COUNTERS(x)     CSI_CR26_PIXEL_COUNTERS(x)
26619 #define CSI_CSICR27_PIXEL_COUNTERS_MASK     CSI_CR27_PIXEL_COUNTERS_MASK
26620 #define CSI_CSICR27_PIXEL_COUNTERS_SHIFT     CSI_CR27_PIXEL_COUNTERS_SHIFT
26621 #define CSI_CSICR27_PIXEL_COUNTERS(x)     CSI_CR27_PIXEL_COUNTERS(x)
26622 #define CSI_CSICR28_PIXEL_COUNTERS_MASK     CSI_CR28_PIXEL_COUNTERS_MASK
26623 #define CSI_CSICR28_PIXEL_COUNTERS_SHIFT     CSI_CR28_PIXEL_COUNTERS_SHIFT
26624 #define CSI_CSICR28_PIXEL_COUNTERS(x)     CSI_CR28_PIXEL_COUNTERS(x)
26625 #define CSI_CSICR29_PIXEL_COUNTERS_MASK     CSI_CR29_PIXEL_COUNTERS_MASK
26626 #define CSI_CSICR29_PIXEL_COUNTERS_SHIFT     CSI_CR29_PIXEL_COUNTERS_SHIFT
26627 #define CSI_CSICR29_PIXEL_COUNTERS(x)     CSI_CR29_PIXEL_COUNTERS(x)
26628 #define CSI_CSICR30_PIXEL_COUNTERS_MASK     CSI_CR30_PIXEL_COUNTERS_MASK
26629 #define CSI_CSICR30_PIXEL_COUNTERS_SHIFT     CSI_CR30_PIXEL_COUNTERS_SHIFT
26630 #define CSI_CSICR30_PIXEL_COUNTERS(x)     CSI_CR30_PIXEL_COUNTERS(x)
26631 #define CSI_CSICR31_PIXEL_COUNTERS_MASK     CSI_CR31_PIXEL_COUNTERS_MASK
26632 #define CSI_CSICR31_PIXEL_COUNTERS_SHIFT     CSI_CR31_PIXEL_COUNTERS_SHIFT
26633 #define CSI_CSICR31_PIXEL_COUNTERS(x)     CSI_CR31_PIXEL_COUNTERS(x)
26634 #define CSI_CSICR32_PIXEL_COUNTERS_MASK     CSI_CR32_PIXEL_COUNTERS_MASK
26635 #define CSI_CSICR32_PIXEL_COUNTERS_SHIFT     CSI_CR32_PIXEL_COUNTERS_SHIFT
26636 #define CSI_CSICR32_PIXEL_COUNTERS(x)     CSI_CR32_PIXEL_COUNTERS(x)
26637 #define CSI_CSICR33_PIXEL_COUNTERS_MASK     CSI_CR33_PIXEL_COUNTERS_MASK
26638 #define CSI_CSICR33_PIXEL_COUNTERS_SHIFT     CSI_CR33_PIXEL_COUNTERS_SHIFT
26639 #define CSI_CSICR33_PIXEL_COUNTERS(x)     CSI_CR33_PIXEL_COUNTERS(x)
26640 #define CSI_CSICR34_PIXEL_COUNTERS_MASK     CSI_CR34_PIXEL_COUNTERS_MASK
26641 #define CSI_CSICR34_PIXEL_COUNTERS_SHIFT     CSI_CR34_PIXEL_COUNTERS_SHIFT
26642 #define CSI_CSICR34_PIXEL_COUNTERS(x)     CSI_CR34_PIXEL_COUNTERS(x)
26643 #define CSI_CSICR35_PIXEL_COUNTERS_MASK     CSI_CR35_PIXEL_COUNTERS_MASK
26644 #define CSI_CSICR35_PIXEL_COUNTERS_SHIFT     CSI_CR35_PIXEL_COUNTERS_SHIFT
26645 #define CSI_CSICR35_PIXEL_COUNTERS(x)     CSI_CR35_PIXEL_COUNTERS(x)
26646 #define CSI_CSICR36_PIXEL_COUNTERS_MASK     CSI_CR36_PIXEL_COUNTERS_MASK
26647 #define CSI_CSICR36_PIXEL_COUNTERS_SHIFT     CSI_CR36_PIXEL_COUNTERS_SHIFT
26648 #define CSI_CSICR36_PIXEL_COUNTERS(x)     CSI_CR36_PIXEL_COUNTERS(x)
26649 #define CSI_CSICR37_PIXEL_COUNTERS_MASK     CSI_CR37_PIXEL_COUNTERS_MASK
26650 #define CSI_CSICR37_PIXEL_COUNTERS_SHIFT     CSI_CR37_PIXEL_COUNTERS_SHIFT
26651 #define CSI_CSICR37_PIXEL_COUNTERS(x)     CSI_CR37_PIXEL_COUNTERS(x)
26652 #define CSI_CSICR38_PIXEL_COUNTERS_MASK     CSI_CR38_PIXEL_COUNTERS_MASK
26653 #define CSI_CSICR38_PIXEL_COUNTERS_SHIFT     CSI_CR38_PIXEL_COUNTERS_SHIFT
26654 #define CSI_CSICR38_PIXEL_COUNTERS(x)     CSI_CR38_PIXEL_COUNTERS(x)
26655 #define CSI_CSICR39_PIXEL_COUNTERS_MASK     CSI_CR39_PIXEL_COUNTERS_MASK
26656 #define CSI_CSICR39_PIXEL_COUNTERS_SHIFT     CSI_CR39_PIXEL_COUNTERS_SHIFT
26657 #define CSI_CSICR39_PIXEL_COUNTERS(x)     CSI_CR39_PIXEL_COUNTERS(x)
26658 #define CSI_CSICR40_PIXEL_COUNTERS_MASK     CSI_CR40_PIXEL_COUNTERS_MASK
26659 #define CSI_CSICR40_PIXEL_COUNTERS_SHIFT     CSI_CR40_PIXEL_COUNTERS_SHIFT
26660 #define CSI_CSICR40_PIXEL_COUNTERS(x)     CSI_CR40_PIXEL_COUNTERS(x)
26661 #define CSI_CSICR41_PIXEL_COUNTERS_MASK     CSI_CR41_PIXEL_COUNTERS_MASK
26662 #define CSI_CSICR41_PIXEL_COUNTERS_SHIFT     CSI_CR41_PIXEL_COUNTERS_SHIFT
26663 #define CSI_CSICR41_PIXEL_COUNTERS(x)     CSI_CR41_PIXEL_COUNTERS(x)
26664 #define CSI_CSICR42_PIXEL_COUNTERS_MASK     CSI_CR42_PIXEL_COUNTERS_MASK
26665 #define CSI_CSICR42_PIXEL_COUNTERS_SHIFT     CSI_CR42_PIXEL_COUNTERS_SHIFT
26666 #define CSI_CSICR42_PIXEL_COUNTERS(x)     CSI_CR42_PIXEL_COUNTERS(x)
26667 #define CSI_CSICR43_PIXEL_COUNTERS_MASK     CSI_CR43_PIXEL_COUNTERS_MASK
26668 #define CSI_CSICR43_PIXEL_COUNTERS_SHIFT     CSI_CR43_PIXEL_COUNTERS_SHIFT
26669 #define CSI_CSICR43_PIXEL_COUNTERS(x)     CSI_CR43_PIXEL_COUNTERS(x)
26670 #define CSI_CSICR44_PIXEL_COUNTERS_MASK     CSI_CR44_PIXEL_COUNTERS_MASK
26671 #define CSI_CSICR44_PIXEL_COUNTERS_SHIFT     CSI_CR44_PIXEL_COUNTERS_SHIFT
26672 #define CSI_CSICR44_PIXEL_COUNTERS(x)     CSI_CR44_PIXEL_COUNTERS(x)
26673 #define CSI_CSICR45_PIXEL_COUNTERS_MASK     CSI_CR45_PIXEL_COUNTERS_MASK
26674 #define CSI_CSICR45_PIXEL_COUNTERS_SHIFT     CSI_CR45_PIXEL_COUNTERS_SHIFT
26675 #define CSI_CSICR45_PIXEL_COUNTERS(x)     CSI_CR45_PIXEL_COUNTERS(x)
26676 #define CSI_CSICR46_PIXEL_COUNTERS_MASK     CSI_CR46_PIXEL_COUNTERS_MASK
26677 #define CSI_CSICR46_PIXEL_COUNTERS_SHIFT     CSI_CR46_PIXEL_COUNTERS_SHIFT
26678 #define CSI_CSICR46_PIXEL_COUNTERS(x)     CSI_CR46_PIXEL_COUNTERS(x)
26679 #define CSI_CSICR47_PIXEL_COUNTERS_MASK     CSI_CR47_PIXEL_COUNTERS_MASK
26680 #define CSI_CSICR47_PIXEL_COUNTERS_SHIFT     CSI_CR47_PIXEL_COUNTERS_SHIFT
26681 #define CSI_CSICR47_PIXEL_COUNTERS(x)     CSI_CR47_PIXEL_COUNTERS(x)
26682 #define CSI_CSICR48_PIXEL_COUNTERS_MASK     CSI_CR48_PIXEL_COUNTERS_MASK
26683 #define CSI_CSICR48_PIXEL_COUNTERS_SHIFT     CSI_CR48_PIXEL_COUNTERS_SHIFT
26684 #define CSI_CSICR48_PIXEL_COUNTERS(x)     CSI_CR48_PIXEL_COUNTERS(x)
26685 #define CSI_CSICR49_PIXEL_COUNTERS_MASK     CSI_CR49_PIXEL_COUNTERS_MASK
26686 #define CSI_CSICR49_PIXEL_COUNTERS_SHIFT     CSI_CR49_PIXEL_COUNTERS_SHIFT
26687 #define CSI_CSICR49_PIXEL_COUNTERS(x)     CSI_CR49_PIXEL_COUNTERS(x)
26688 #define CSI_CSICR50_PIXEL_COUNTERS_MASK     CSI_CR50_PIXEL_COUNTERS_MASK
26689 #define CSI_CSICR50_PIXEL_COUNTERS_SHIFT     CSI_CR50_PIXEL_COUNTERS_SHIFT
26690 #define CSI_CSICR50_PIXEL_COUNTERS(x)     CSI_CR50_PIXEL_COUNTERS(x)
26691 #define CSI_CSICR51_PIXEL_COUNTERS_MASK     CSI_CR51_PIXEL_COUNTERS_MASK
26692 #define CSI_CSICR51_PIXEL_COUNTERS_SHIFT     CSI_CR51_PIXEL_COUNTERS_SHIFT
26693 #define CSI_CSICR51_PIXEL_COUNTERS(x)     CSI_CR51_PIXEL_COUNTERS(x)
26694 #define CSI_CSICR52_PIXEL_COUNTERS_MASK     CSI_CR52_PIXEL_COUNTERS_MASK
26695 #define CSI_CSICR52_PIXEL_COUNTERS_SHIFT     CSI_CR52_PIXEL_COUNTERS_SHIFT
26696 #define CSI_CSICR52_PIXEL_COUNTERS(x)     CSI_CR52_PIXEL_COUNTERS(x)
26697 #define CSI_CSICR53_PIXEL_COUNTERS_MASK     CSI_CR53_PIXEL_COUNTERS_MASK
26698 #define CSI_CSICR53_PIXEL_COUNTERS_SHIFT     CSI_CR53_PIXEL_COUNTERS_SHIFT
26699 #define CSI_CSICR53_PIXEL_COUNTERS(x)     CSI_CR53_PIXEL_COUNTERS(x)
26700 #define CSI_CSICR54_PIXEL_COUNTERS_MASK     CSI_CR54_PIXEL_COUNTERS_MASK
26701 #define CSI_CSICR54_PIXEL_COUNTERS_SHIFT     CSI_CR54_PIXEL_COUNTERS_SHIFT
26702 #define CSI_CSICR54_PIXEL_COUNTERS(x)     CSI_CR54_PIXEL_COUNTERS(x)
26703 #define CSI_CSICR55_PIXEL_COUNTERS_MASK     CSI_CR55_PIXEL_COUNTERS_MASK
26704 #define CSI_CSICR55_PIXEL_COUNTERS_SHIFT     CSI_CR55_PIXEL_COUNTERS_SHIFT
26705 #define CSI_CSICR55_PIXEL_COUNTERS(x)     CSI_CR55_PIXEL_COUNTERS(x)
26706 #define CSI_CSICR56_PIXEL_COUNTERS_MASK     CSI_CR56_PIXEL_COUNTERS_MASK
26707 #define CSI_CSICR56_PIXEL_COUNTERS_SHIFT     CSI_CR56_PIXEL_COUNTERS_SHIFT
26708 #define CSI_CSICR56_PIXEL_COUNTERS(x)     CSI_CR56_PIXEL_COUNTERS(x)
26709 #define CSI_CSICR57_PIXEL_COUNTERS_MASK     CSI_CR57_PIXEL_COUNTERS_MASK
26710 #define CSI_CSICR57_PIXEL_COUNTERS_SHIFT     CSI_CR57_PIXEL_COUNTERS_SHIFT
26711 #define CSI_CSICR57_PIXEL_COUNTERS(x)     CSI_CR57_PIXEL_COUNTERS(x)
26712 #define CSI_CSICR58_PIXEL_COUNTERS_MASK     CSI_CR58_PIXEL_COUNTERS_MASK
26713 #define CSI_CSICR58_PIXEL_COUNTERS_SHIFT     CSI_CR58_PIXEL_COUNTERS_SHIFT
26714 #define CSI_CSICR58_PIXEL_COUNTERS(x)     CSI_CR58_PIXEL_COUNTERS(x)
26715 #define CSI_CSICR59_PIXEL_COUNTERS_MASK     CSI_CR59_PIXEL_COUNTERS_MASK
26716 #define CSI_CSICR59_PIXEL_COUNTERS_SHIFT     CSI_CR59_PIXEL_COUNTERS_SHIFT
26717 #define CSI_CSICR59_PIXEL_COUNTERS(x)     CSI_CR59_PIXEL_COUNTERS(x)
26718 #define CSI_CSICR60_PIXEL_COUNTERS_MASK     CSI_CR60_PIXEL_COUNTERS_MASK
26719 #define CSI_CSICR60_PIXEL_COUNTERS_SHIFT     CSI_CR60_PIXEL_COUNTERS_SHIFT
26720 #define CSI_CSICR60_PIXEL_COUNTERS(x)     CSI_CR60_PIXEL_COUNTERS(x)
26721 #define CSI_CSICR61_PIXEL_COUNTERS_MASK     CSI_CR61_PIXEL_COUNTERS_MASK
26722 #define CSI_CSICR61_PIXEL_COUNTERS_SHIFT     CSI_CR61_PIXEL_COUNTERS_SHIFT
26723 #define CSI_CSICR61_PIXEL_COUNTERS(x)     CSI_CR61_PIXEL_COUNTERS(x)
26724 #define CSI_CSICR62_PIXEL_COUNTERS_MASK     CSI_CR62_PIXEL_COUNTERS_MASK
26725 #define CSI_CSICR62_PIXEL_COUNTERS_SHIFT     CSI_CR62_PIXEL_COUNTERS_SHIFT
26726 #define CSI_CSICR62_PIXEL_COUNTERS(x)     CSI_CR62_PIXEL_COUNTERS(x)
26727 #define CSI_CSICR63_PIXEL_COUNTERS_MASK     CSI_CR63_PIXEL_COUNTERS_MASK
26728 #define CSI_CSICR63_PIXEL_COUNTERS_SHIFT     CSI_CR63_PIXEL_COUNTERS_SHIFT
26729 #define CSI_CSICR63_PIXEL_COUNTERS(x)     CSI_CR63_PIXEL_COUNTERS(x)
26730 #define CSI_CSICR64_PIXEL_COUNTERS_MASK     CSI_CR64_PIXEL_COUNTERS_MASK
26731 #define CSI_CSICR64_PIXEL_COUNTERS_SHIFT     CSI_CR64_PIXEL_COUNTERS_SHIFT
26732 #define CSI_CSICR64_PIXEL_COUNTERS(x)     CSI_CR64_PIXEL_COUNTERS(x)
26733 #define CSI_CSICR65_PIXEL_COUNTERS_MASK     CSI_CR65_PIXEL_COUNTERS_MASK
26734 #define CSI_CSICR65_PIXEL_COUNTERS_SHIFT     CSI_CR65_PIXEL_COUNTERS_SHIFT
26735 #define CSI_CSICR65_PIXEL_COUNTERS(x)     CSI_CR65_PIXEL_COUNTERS(x)
26736 #define CSI_CSICR66_PIXEL_COUNTERS_MASK     CSI_CR66_PIXEL_COUNTERS_MASK
26737 #define CSI_CSICR66_PIXEL_COUNTERS_SHIFT     CSI_CR66_PIXEL_COUNTERS_SHIFT
26738 #define CSI_CSICR66_PIXEL_COUNTERS(x)     CSI_CR66_PIXEL_COUNTERS(x)
26739 #define CSI_CSICR67_PIXEL_COUNTERS_MASK     CSI_CR67_PIXEL_COUNTERS_MASK
26740 #define CSI_CSICR67_PIXEL_COUNTERS_SHIFT     CSI_CR67_PIXEL_COUNTERS_SHIFT
26741 #define CSI_CSICR67_PIXEL_COUNTERS(x)     CSI_CR67_PIXEL_COUNTERS(x)
26742 #define CSI_CSICR68_PIXEL_COUNTERS_MASK     CSI_CR68_PIXEL_COUNTERS_MASK
26743 #define CSI_CSICR68_PIXEL_COUNTERS_SHIFT     CSI_CR68_PIXEL_COUNTERS_SHIFT
26744 #define CSI_CSICR68_PIXEL_COUNTERS(x)     CSI_CR68_PIXEL_COUNTERS(x)
26745 #define CSI_CSICR69_PIXEL_COUNTERS_MASK     CSI_CR69_PIXEL_COUNTERS_MASK
26746 #define CSI_CSICR69_PIXEL_COUNTERS_SHIFT     CSI_CR69_PIXEL_COUNTERS_SHIFT
26747 #define CSI_CSICR69_PIXEL_COUNTERS(x)     CSI_CR69_PIXEL_COUNTERS(x)
26748 #define CSI_CSICR70_PIXEL_COUNTERS_MASK     CSI_CR70_PIXEL_COUNTERS_MASK
26749 #define CSI_CSICR70_PIXEL_COUNTERS_SHIFT     CSI_CR70_PIXEL_COUNTERS_SHIFT
26750 #define CSI_CSICR70_PIXEL_COUNTERS(x)     CSI_CR70_PIXEL_COUNTERS(x)
26751 #define CSI_CSICR71_PIXEL_COUNTERS_MASK     CSI_CR71_PIXEL_COUNTERS_MASK
26752 #define CSI_CSICR71_PIXEL_COUNTERS_SHIFT     CSI_CR71_PIXEL_COUNTERS_SHIFT
26753 #define CSI_CSICR71_PIXEL_COUNTERS(x)     CSI_CR71_PIXEL_COUNTERS(x)
26754 #define CSI_CSICR72_PIXEL_COUNTERS_MASK     CSI_CR72_PIXEL_COUNTERS_MASK
26755 #define CSI_CSICR72_PIXEL_COUNTERS_SHIFT     CSI_CR72_PIXEL_COUNTERS_SHIFT
26756 #define CSI_CSICR72_PIXEL_COUNTERS(x)     CSI_CR72_PIXEL_COUNTERS(x)
26757 #define CSI_CSICR73_PIXEL_COUNTERS_MASK     CSI_CR73_PIXEL_COUNTERS_MASK
26758 #define CSI_CSICR73_PIXEL_COUNTERS_SHIFT     CSI_CR73_PIXEL_COUNTERS_SHIFT
26759 #define CSI_CSICR73_PIXEL_COUNTERS(x)     CSI_CR73_PIXEL_COUNTERS(x)
26760 #define CSI_CSICR74_PIXEL_COUNTERS_MASK     CSI_CR74_PIXEL_COUNTERS_MASK
26761 #define CSI_CSICR74_PIXEL_COUNTERS_SHIFT     CSI_CR74_PIXEL_COUNTERS_SHIFT
26762 #define CSI_CSICR74_PIXEL_COUNTERS(x)     CSI_CR74_PIXEL_COUNTERS(x)
26763 #define CSI_CSICR75_PIXEL_COUNTERS_MASK     CSI_CR75_PIXEL_COUNTERS_MASK
26764 #define CSI_CSICR75_PIXEL_COUNTERS_SHIFT     CSI_CR75_PIXEL_COUNTERS_SHIFT
26765 #define CSI_CSICR75_PIXEL_COUNTERS(x)     CSI_CR75_PIXEL_COUNTERS(x)
26766 #define CSI_CSICR76_PIXEL_COUNTERS_MASK     CSI_CR76_PIXEL_COUNTERS_MASK
26767 #define CSI_CSICR76_PIXEL_COUNTERS_SHIFT     CSI_CR76_PIXEL_COUNTERS_SHIFT
26768 #define CSI_CSICR76_PIXEL_COUNTERS(x)     CSI_CR76_PIXEL_COUNTERS(x)
26769 #define CSI_CSICR77_PIXEL_COUNTERS_MASK     CSI_CR77_PIXEL_COUNTERS_MASK
26770 #define CSI_CSICR77_PIXEL_COUNTERS_SHIFT     CSI_CR77_PIXEL_COUNTERS_SHIFT
26771 #define CSI_CSICR77_PIXEL_COUNTERS(x)     CSI_CR77_PIXEL_COUNTERS(x)
26772 #define CSI_CSICR78_PIXEL_COUNTERS_MASK     CSI_CR78_PIXEL_COUNTERS_MASK
26773 #define CSI_CSICR78_PIXEL_COUNTERS_SHIFT     CSI_CR78_PIXEL_COUNTERS_SHIFT
26774 #define CSI_CSICR78_PIXEL_COUNTERS(x)     CSI_CR78_PIXEL_COUNTERS(x)
26775 #define CSI_CSICR79_PIXEL_COUNTERS_MASK     CSI_CR79_PIXEL_COUNTERS_MASK
26776 #define CSI_CSICR79_PIXEL_COUNTERS_SHIFT     CSI_CR79_PIXEL_COUNTERS_SHIFT
26777 #define CSI_CSICR79_PIXEL_COUNTERS(x)     CSI_CR79_PIXEL_COUNTERS(x)
26778 #define CSI_CSICR80_PIXEL_COUNTERS_MASK     CSI_CR80_PIXEL_COUNTERS_MASK
26779 #define CSI_CSICR80_PIXEL_COUNTERS_SHIFT     CSI_CR80_PIXEL_COUNTERS_SHIFT
26780 #define CSI_CSICR80_PIXEL_COUNTERS(x)     CSI_CR80_PIXEL_COUNTERS(x)
26781 #define CSI_CSICR81_PIXEL_COUNTERS_MASK     CSI_CR81_PIXEL_COUNTERS_MASK
26782 #define CSI_CSICR81_PIXEL_COUNTERS_SHIFT     CSI_CR81_PIXEL_COUNTERS_SHIFT
26783 #define CSI_CSICR81_PIXEL_COUNTERS(x)     CSI_CR81_PIXEL_COUNTERS(x)
26784 #define CSI_CSICR82_PIXEL_COUNTERS_MASK     CSI_CR82_PIXEL_COUNTERS_MASK
26785 #define CSI_CSICR82_PIXEL_COUNTERS_SHIFT     CSI_CR82_PIXEL_COUNTERS_SHIFT
26786 #define CSI_CSICR82_PIXEL_COUNTERS(x)     CSI_CR82_PIXEL_COUNTERS(x)
26787 #define CSI_CSICR83_PIXEL_COUNTERS_MASK     CSI_CR83_PIXEL_COUNTERS_MASK
26788 #define CSI_CSICR83_PIXEL_COUNTERS_SHIFT     CSI_CR83_PIXEL_COUNTERS_SHIFT
26789 #define CSI_CSICR83_PIXEL_COUNTERS(x)     CSI_CR83_PIXEL_COUNTERS(x)
26790 #define CSI_CSICR84_PIXEL_COUNTERS_MASK     CSI_CR84_PIXEL_COUNTERS_MASK
26791 #define CSI_CSICR84_PIXEL_COUNTERS_SHIFT     CSI_CR84_PIXEL_COUNTERS_SHIFT
26792 #define CSI_CSICR84_PIXEL_COUNTERS(x)     CSI_CR84_PIXEL_COUNTERS(x)
26793 #define CSI_CSICR85_PIXEL_COUNTERS_MASK     CSI_CR85_PIXEL_COUNTERS_MASK
26794 #define CSI_CSICR85_PIXEL_COUNTERS_SHIFT     CSI_CR85_PIXEL_COUNTERS_SHIFT
26795 #define CSI_CSICR85_PIXEL_COUNTERS(x)     CSI_CR85_PIXEL_COUNTERS(x)
26796 #define CSI_CSICR86_PIXEL_COUNTERS_MASK     CSI_CR86_PIXEL_COUNTERS_MASK
26797 #define CSI_CSICR86_PIXEL_COUNTERS_SHIFT     CSI_CR86_PIXEL_COUNTERS_SHIFT
26798 #define CSI_CSICR86_PIXEL_COUNTERS(x)     CSI_CR86_PIXEL_COUNTERS(x)
26799 #define CSI_CSICR87_PIXEL_COUNTERS_MASK     CSI_CR87_PIXEL_COUNTERS_MASK
26800 #define CSI_CSICR87_PIXEL_COUNTERS_SHIFT     CSI_CR87_PIXEL_COUNTERS_SHIFT
26801 #define CSI_CSICR87_PIXEL_COUNTERS(x)     CSI_CR87_PIXEL_COUNTERS(x)
26802 #define CSI_CSICR88_PIXEL_COUNTERS_MASK     CSI_CR88_PIXEL_COUNTERS_MASK
26803 #define CSI_CSICR88_PIXEL_COUNTERS_SHIFT     CSI_CR88_PIXEL_COUNTERS_SHIFT
26804 #define CSI_CSICR88_PIXEL_COUNTERS(x)     CSI_CR88_PIXEL_COUNTERS(x)
26805 #define CSI_CSICR89_PIXEL_COUNTERS_MASK     CSI_CR89_PIXEL_COUNTERS_MASK
26806 #define CSI_CSICR89_PIXEL_COUNTERS_SHIFT     CSI_CR89_PIXEL_COUNTERS_SHIFT
26807 #define CSI_CSICR89_PIXEL_COUNTERS(x)     CSI_CR89_PIXEL_COUNTERS(x)
26808 #define CSI_CSICR90_PIXEL_COUNTERS_MASK     CSI_CR90_PIXEL_COUNTERS_MASK
26809 #define CSI_CSICR90_PIXEL_COUNTERS_SHIFT     CSI_CR90_PIXEL_COUNTERS_SHIFT
26810 #define CSI_CSICR90_PIXEL_COUNTERS(x)     CSI_CR90_PIXEL_COUNTERS(x)
26811 #define CSI_CSICR91_PIXEL_COUNTERS_MASK     CSI_CR91_PIXEL_COUNTERS_MASK
26812 #define CSI_CSICR91_PIXEL_COUNTERS_SHIFT     CSI_CR91_PIXEL_COUNTERS_SHIFT
26813 #define CSI_CSICR91_PIXEL_COUNTERS(x)     CSI_CR91_PIXEL_COUNTERS(x)
26814 #define CSI_CSICR92_PIXEL_COUNTERS_MASK     CSI_CR92_PIXEL_COUNTERS_MASK
26815 #define CSI_CSICR92_PIXEL_COUNTERS_SHIFT     CSI_CR92_PIXEL_COUNTERS_SHIFT
26816 #define CSI_CSICR92_PIXEL_COUNTERS(x)     CSI_CR92_PIXEL_COUNTERS(x)
26817 #define CSI_CSICR93_PIXEL_COUNTERS_MASK     CSI_CR93_PIXEL_COUNTERS_MASK
26818 #define CSI_CSICR93_PIXEL_COUNTERS_SHIFT     CSI_CR93_PIXEL_COUNTERS_SHIFT
26819 #define CSI_CSICR93_PIXEL_COUNTERS(x)     CSI_CR93_PIXEL_COUNTERS(x)
26820 #define CSI_CSICR94_PIXEL_COUNTERS_MASK     CSI_CR94_PIXEL_COUNTERS_MASK
26821 #define CSI_CSICR94_PIXEL_COUNTERS_SHIFT     CSI_CR94_PIXEL_COUNTERS_SHIFT
26822 #define CSI_CSICR94_PIXEL_COUNTERS(x)     CSI_CR94_PIXEL_COUNTERS(x)
26823 #define CSI_CSICR95_PIXEL_COUNTERS_MASK     CSI_CR95_PIXEL_COUNTERS_MASK
26824 #define CSI_CSICR95_PIXEL_COUNTERS_SHIFT     CSI_CR95_PIXEL_COUNTERS_SHIFT
26825 #define CSI_CSICR95_PIXEL_COUNTERS(x)     CSI_CR95_PIXEL_COUNTERS(x)
26826 #define CSI_CSICR96_PIXEL_COUNTERS_MASK     CSI_CR96_PIXEL_COUNTERS_MASK
26827 #define CSI_CSICR96_PIXEL_COUNTERS_SHIFT     CSI_CR96_PIXEL_COUNTERS_SHIFT
26828 #define CSI_CSICR96_PIXEL_COUNTERS(x)     CSI_CR96_PIXEL_COUNTERS(x)
26829 #define CSI_CSICR97_PIXEL_COUNTERS_MASK     CSI_CR97_PIXEL_COUNTERS_MASK
26830 #define CSI_CSICR97_PIXEL_COUNTERS_SHIFT     CSI_CR97_PIXEL_COUNTERS_SHIFT
26831 #define CSI_CSICR97_PIXEL_COUNTERS(x)     CSI_CR97_PIXEL_COUNTERS(x)
26832 #define CSI_CSICR98_PIXEL_COUNTERS_MASK     CSI_CR98_PIXEL_COUNTERS_MASK
26833 #define CSI_CSICR98_PIXEL_COUNTERS_SHIFT     CSI_CR98_PIXEL_COUNTERS_SHIFT
26834 #define CSI_CSICR98_PIXEL_COUNTERS(x)     CSI_CR98_PIXEL_COUNTERS(x)
26835 #define CSI_CSICR99_PIXEL_COUNTERS_MASK     CSI_CR99_PIXEL_COUNTERS_MASK
26836 #define CSI_CSICR99_PIXEL_COUNTERS_SHIFT     CSI_CR99_PIXEL_COUNTERS_SHIFT
26837 #define CSI_CSICR99_PIXEL_COUNTERS(x)     CSI_CR99_PIXEL_COUNTERS(x)
26838 #define CSI_CSICR100_PIXEL_COUNTERS_MASK     CSI_CR100_PIXEL_COUNTERS_MASK
26839 #define CSI_CSICR100_PIXEL_COUNTERS_SHIFT     CSI_CR100_PIXEL_COUNTERS_SHIFT
26840 #define CSI_CSICR100_PIXEL_COUNTERS(x)     CSI_CR100_PIXEL_COUNTERS(x)
26841 #define CSI_CSICR101_PIXEL_COUNTERS_MASK     CSI_CR101_PIXEL_COUNTERS_MASK
26842 #define CSI_CSICR101_PIXEL_COUNTERS_SHIFT     CSI_CR101_PIXEL_COUNTERS_SHIFT
26843 #define CSI_CSICR101_PIXEL_COUNTERS(x)     CSI_CR101_PIXEL_COUNTERS(x)
26844 #define CSI_CSICR102_PIXEL_COUNTERS_MASK     CSI_CR102_PIXEL_COUNTERS_MASK
26845 #define CSI_CSICR102_PIXEL_COUNTERS_SHIFT     CSI_CR102_PIXEL_COUNTERS_SHIFT
26846 #define CSI_CSICR102_PIXEL_COUNTERS(x)     CSI_CR102_PIXEL_COUNTERS(x)
26847 #define CSI_CSICR103_PIXEL_COUNTERS_MASK     CSI_CR103_PIXEL_COUNTERS_MASK
26848 #define CSI_CSICR103_PIXEL_COUNTERS_SHIFT     CSI_CR103_PIXEL_COUNTERS_SHIFT
26849 #define CSI_CSICR103_PIXEL_COUNTERS(x)     CSI_CR103_PIXEL_COUNTERS(x)
26850 #define CSI_CSICR104_PIXEL_COUNTERS_MASK     CSI_CR104_PIXEL_COUNTERS_MASK
26851 #define CSI_CSICR104_PIXEL_COUNTERS_SHIFT     CSI_CR104_PIXEL_COUNTERS_SHIFT
26852 #define CSI_CSICR104_PIXEL_COUNTERS(x)     CSI_CR104_PIXEL_COUNTERS(x)
26853 #define CSI_CSICR105_PIXEL_COUNTERS_MASK     CSI_CR105_PIXEL_COUNTERS_MASK
26854 #define CSI_CSICR105_PIXEL_COUNTERS_SHIFT     CSI_CR105_PIXEL_COUNTERS_SHIFT
26855 #define CSI_CSICR105_PIXEL_COUNTERS(x)     CSI_CR105_PIXEL_COUNTERS(x)
26856 #define CSI_CSICR106_PIXEL_COUNTERS_MASK     CSI_CR106_PIXEL_COUNTERS_MASK
26857 #define CSI_CSICR106_PIXEL_COUNTERS_SHIFT     CSI_CR106_PIXEL_COUNTERS_SHIFT
26858 #define CSI_CSICR106_PIXEL_COUNTERS(x)     CSI_CR106_PIXEL_COUNTERS(x)
26859 #define CSI_CSICR107_PIXEL_COUNTERS_MASK     CSI_CR107_PIXEL_COUNTERS_MASK
26860 #define CSI_CSICR107_PIXEL_COUNTERS_SHIFT     CSI_CR107_PIXEL_COUNTERS_SHIFT
26861 #define CSI_CSICR107_PIXEL_COUNTERS(x)     CSI_CR107_PIXEL_COUNTERS(x)
26862 #define CSI_CSICR108_PIXEL_COUNTERS_MASK     CSI_CR108_PIXEL_COUNTERS_MASK
26863 #define CSI_CSICR108_PIXEL_COUNTERS_SHIFT     CSI_CR108_PIXEL_COUNTERS_SHIFT
26864 #define CSI_CSICR108_PIXEL_COUNTERS(x)     CSI_CR108_PIXEL_COUNTERS(x)
26865 #define CSI_CSICR109_PIXEL_COUNTERS_MASK     CSI_CR109_PIXEL_COUNTERS_MASK
26866 #define CSI_CSICR109_PIXEL_COUNTERS_SHIFT     CSI_CR109_PIXEL_COUNTERS_SHIFT
26867 #define CSI_CSICR109_PIXEL_COUNTERS(x)     CSI_CR109_PIXEL_COUNTERS(x)
26868 #define CSI_CSICR110_PIXEL_COUNTERS_MASK     CSI_CR110_PIXEL_COUNTERS_MASK
26869 #define CSI_CSICR110_PIXEL_COUNTERS_SHIFT     CSI_CR110_PIXEL_COUNTERS_SHIFT
26870 #define CSI_CSICR110_PIXEL_COUNTERS(x)     CSI_CR110_PIXEL_COUNTERS(x)
26871 #define CSI_CSICR111_PIXEL_COUNTERS_MASK     CSI_CR111_PIXEL_COUNTERS_MASK
26872 #define CSI_CSICR111_PIXEL_COUNTERS_SHIFT     CSI_CR111_PIXEL_COUNTERS_SHIFT
26873 #define CSI_CSICR111_PIXEL_COUNTERS(x)     CSI_CR111_PIXEL_COUNTERS(x)
26874 #define CSI_CSICR112_PIXEL_COUNTERS_MASK     CSI_CR112_PIXEL_COUNTERS_MASK
26875 #define CSI_CSICR112_PIXEL_COUNTERS_SHIFT     CSI_CR112_PIXEL_COUNTERS_SHIFT
26876 #define CSI_CSICR112_PIXEL_COUNTERS(x)     CSI_CR112_PIXEL_COUNTERS(x)
26877 #define CSI_CSICR113_PIXEL_COUNTERS_MASK     CSI_CR113_PIXEL_COUNTERS_MASK
26878 #define CSI_CSICR113_PIXEL_COUNTERS_SHIFT     CSI_CR113_PIXEL_COUNTERS_SHIFT
26879 #define CSI_CSICR113_PIXEL_COUNTERS(x)     CSI_CR113_PIXEL_COUNTERS(x)
26880 #define CSI_CSICR114_PIXEL_COUNTERS_MASK     CSI_CR114_PIXEL_COUNTERS_MASK
26881 #define CSI_CSICR114_PIXEL_COUNTERS_SHIFT     CSI_CR114_PIXEL_COUNTERS_SHIFT
26882 #define CSI_CSICR114_PIXEL_COUNTERS(x)     CSI_CR114_PIXEL_COUNTERS(x)
26883 #define CSI_CSICR115_PIXEL_COUNTERS_MASK     CSI_CR115_PIXEL_COUNTERS_MASK
26884 #define CSI_CSICR115_PIXEL_COUNTERS_SHIFT     CSI_CR115_PIXEL_COUNTERS_SHIFT
26885 #define CSI_CSICR115_PIXEL_COUNTERS(x)     CSI_CR115_PIXEL_COUNTERS(x)
26886 #define CSI_CSICR116_PIXEL_COUNTERS_MASK     CSI_CR116_PIXEL_COUNTERS_MASK
26887 #define CSI_CSICR116_PIXEL_COUNTERS_SHIFT     CSI_CR116_PIXEL_COUNTERS_SHIFT
26888 #define CSI_CSICR116_PIXEL_COUNTERS(x)     CSI_CR116_PIXEL_COUNTERS(x)
26889 #define CSI_CSICR117_PIXEL_COUNTERS_MASK     CSI_CR117_PIXEL_COUNTERS_MASK
26890 #define CSI_CSICR117_PIXEL_COUNTERS_SHIFT     CSI_CR117_PIXEL_COUNTERS_SHIFT
26891 #define CSI_CSICR117_PIXEL_COUNTERS(x)     CSI_CR117_PIXEL_COUNTERS(x)
26892 #define CSI_CSICR118_PIXEL_COUNTERS_MASK     CSI_CR118_PIXEL_COUNTERS_MASK
26893 #define CSI_CSICR118_PIXEL_COUNTERS_SHIFT     CSI_CR118_PIXEL_COUNTERS_SHIFT
26894 #define CSI_CSICR118_PIXEL_COUNTERS(x)     CSI_CR118_PIXEL_COUNTERS(x)
26895 #define CSI_CSICR119_PIXEL_COUNTERS_MASK     CSI_CR119_PIXEL_COUNTERS_MASK
26896 #define CSI_CSICR119_PIXEL_COUNTERS_SHIFT     CSI_CR119_PIXEL_COUNTERS_SHIFT
26897 #define CSI_CSICR119_PIXEL_COUNTERS(x)     CSI_CR119_PIXEL_COUNTERS(x)
26898 #define CSI_CSICR120_PIXEL_COUNTERS_MASK     CSI_CR120_PIXEL_COUNTERS_MASK
26899 #define CSI_CSICR120_PIXEL_COUNTERS_SHIFT     CSI_CR120_PIXEL_COUNTERS_SHIFT
26900 #define CSI_CSICR120_PIXEL_COUNTERS(x)     CSI_CR120_PIXEL_COUNTERS(x)
26901 #define CSI_CSICR121_PIXEL_COUNTERS_MASK     CSI_CR121_PIXEL_COUNTERS_MASK
26902 #define CSI_CSICR121_PIXEL_COUNTERS_SHIFT     CSI_CR121_PIXEL_COUNTERS_SHIFT
26903 #define CSI_CSICR121_PIXEL_COUNTERS(x)     CSI_CR121_PIXEL_COUNTERS(x)
26904 #define CSI_CSICR122_PIXEL_COUNTERS_MASK     CSI_CR122_PIXEL_COUNTERS_MASK
26905 #define CSI_CSICR122_PIXEL_COUNTERS_SHIFT     CSI_CR122_PIXEL_COUNTERS_SHIFT
26906 #define CSI_CSICR122_PIXEL_COUNTERS(x)     CSI_CR122_PIXEL_COUNTERS(x)
26907 #define CSI_CSICR123_PIXEL_COUNTERS_MASK     CSI_CR123_PIXEL_COUNTERS_MASK
26908 #define CSI_CSICR123_PIXEL_COUNTERS_SHIFT     CSI_CR123_PIXEL_COUNTERS_SHIFT
26909 #define CSI_CSICR123_PIXEL_COUNTERS(x)     CSI_CR123_PIXEL_COUNTERS(x)
26910 #define CSI_CSICR124_PIXEL_COUNTERS_MASK     CSI_CR124_PIXEL_COUNTERS_MASK
26911 #define CSI_CSICR124_PIXEL_COUNTERS_SHIFT     CSI_CR124_PIXEL_COUNTERS_SHIFT
26912 #define CSI_CSICR124_PIXEL_COUNTERS(x)     CSI_CR124_PIXEL_COUNTERS(x)
26913 #define CSI_CSICR125_PIXEL_COUNTERS_MASK     CSI_CR125_PIXEL_COUNTERS_MASK
26914 #define CSI_CSICR125_PIXEL_COUNTERS_SHIFT     CSI_CR125_PIXEL_COUNTERS_SHIFT
26915 #define CSI_CSICR125_PIXEL_COUNTERS(x)     CSI_CR125_PIXEL_COUNTERS(x)
26916 #define CSI_CSICR126_PIXEL_COUNTERS_MASK     CSI_CR126_PIXEL_COUNTERS_MASK
26917 #define CSI_CSICR126_PIXEL_COUNTERS_SHIFT     CSI_CR126_PIXEL_COUNTERS_SHIFT
26918 #define CSI_CSICR126_PIXEL_COUNTERS(x)     CSI_CR126_PIXEL_COUNTERS(x)
26919 #define CSI_CSICR127_PIXEL_COUNTERS_MASK     CSI_CR127_PIXEL_COUNTERS_MASK
26920 #define CSI_CSICR127_PIXEL_COUNTERS_SHIFT     CSI_CR127_PIXEL_COUNTERS_SHIFT
26921 #define CSI_CSICR127_PIXEL_COUNTERS(x)     CSI_CR127_PIXEL_COUNTERS(x)
26922 #define CSI_CSICR128_PIXEL_COUNTERS_MASK     CSI_CR128_PIXEL_COUNTERS_MASK
26923 #define CSI_CSICR128_PIXEL_COUNTERS_SHIFT     CSI_CR128_PIXEL_COUNTERS_SHIFT
26924 #define CSI_CSICR128_PIXEL_COUNTERS(x)     CSI_CR128_PIXEL_COUNTERS(x)
26925 #define CSI_CSICR129_PIXEL_COUNTERS_MASK     CSI_CR129_PIXEL_COUNTERS_MASK
26926 #define CSI_CSICR129_PIXEL_COUNTERS_SHIFT     CSI_CR129_PIXEL_COUNTERS_SHIFT
26927 #define CSI_CSICR129_PIXEL_COUNTERS(x)     CSI_CR129_PIXEL_COUNTERS(x)
26928 #define CSI_CSICR130_PIXEL_COUNTERS_MASK     CSI_CR130_PIXEL_COUNTERS_MASK
26929 #define CSI_CSICR130_PIXEL_COUNTERS_SHIFT     CSI_CR130_PIXEL_COUNTERS_SHIFT
26930 #define CSI_CSICR130_PIXEL_COUNTERS(x)     CSI_CR130_PIXEL_COUNTERS(x)
26931 #define CSI_CSICR131_PIXEL_COUNTERS_MASK     CSI_CR131_PIXEL_COUNTERS_MASK
26932 #define CSI_CSICR131_PIXEL_COUNTERS_SHIFT     CSI_CR131_PIXEL_COUNTERS_SHIFT
26933 #define CSI_CSICR131_PIXEL_COUNTERS(x)     CSI_CR131_PIXEL_COUNTERS(x)
26934 #define CSI_CSICR132_PIXEL_COUNTERS_MASK     CSI_CR132_PIXEL_COUNTERS_MASK
26935 #define CSI_CSICR132_PIXEL_COUNTERS_SHIFT     CSI_CR132_PIXEL_COUNTERS_SHIFT
26936 #define CSI_CSICR132_PIXEL_COUNTERS(x)     CSI_CR132_PIXEL_COUNTERS(x)
26937 #define CSI_CSICR133_PIXEL_COUNTERS_MASK     CSI_CR133_PIXEL_COUNTERS_MASK
26938 #define CSI_CSICR133_PIXEL_COUNTERS_SHIFT     CSI_CR133_PIXEL_COUNTERS_SHIFT
26939 #define CSI_CSICR133_PIXEL_COUNTERS(x)     CSI_CR133_PIXEL_COUNTERS(x)
26940 #define CSI_CSICR134_PIXEL_COUNTERS_MASK     CSI_CR134_PIXEL_COUNTERS_MASK
26941 #define CSI_CSICR134_PIXEL_COUNTERS_SHIFT     CSI_CR134_PIXEL_COUNTERS_SHIFT
26942 #define CSI_CSICR134_PIXEL_COUNTERS(x)     CSI_CR134_PIXEL_COUNTERS(x)
26943 #define CSI_CSICR135_PIXEL_COUNTERS_MASK     CSI_CR135_PIXEL_COUNTERS_MASK
26944 #define CSI_CSICR135_PIXEL_COUNTERS_SHIFT     CSI_CR135_PIXEL_COUNTERS_SHIFT
26945 #define CSI_CSICR135_PIXEL_COUNTERS(x)     CSI_CR135_PIXEL_COUNTERS(x)
26946 #define CSI_CSICR136_PIXEL_COUNTERS_MASK     CSI_CR136_PIXEL_COUNTERS_MASK
26947 #define CSI_CSICR136_PIXEL_COUNTERS_SHIFT     CSI_CR136_PIXEL_COUNTERS_SHIFT
26948 #define CSI_CSICR136_PIXEL_COUNTERS(x)     CSI_CR136_PIXEL_COUNTERS(x)
26949 #define CSI_CSICR137_PIXEL_COUNTERS_MASK     CSI_CR137_PIXEL_COUNTERS_MASK
26950 #define CSI_CSICR137_PIXEL_COUNTERS_SHIFT     CSI_CR137_PIXEL_COUNTERS_SHIFT
26951 #define CSI_CSICR137_PIXEL_COUNTERS(x)     CSI_CR137_PIXEL_COUNTERS(x)
26952 #define CSI_CSICR138_PIXEL_COUNTERS_MASK     CSI_CR138_PIXEL_COUNTERS_MASK
26953 #define CSI_CSICR138_PIXEL_COUNTERS_SHIFT     CSI_CR138_PIXEL_COUNTERS_SHIFT
26954 #define CSI_CSICR138_PIXEL_COUNTERS(x)     CSI_CR138_PIXEL_COUNTERS(x)
26955 #define CSI_CSICR139_PIXEL_COUNTERS_MASK     CSI_CR139_PIXEL_COUNTERS_MASK
26956 #define CSI_CSICR139_PIXEL_COUNTERS_SHIFT     CSI_CR139_PIXEL_COUNTERS_SHIFT
26957 #define CSI_CSICR139_PIXEL_COUNTERS(x)     CSI_CR139_PIXEL_COUNTERS(x)
26958 #define CSI_CSICR140_PIXEL_COUNTERS_MASK     CSI_CR140_PIXEL_COUNTERS_MASK
26959 #define CSI_CSICR140_PIXEL_COUNTERS_SHIFT     CSI_CR140_PIXEL_COUNTERS_SHIFT
26960 #define CSI_CSICR140_PIXEL_COUNTERS(x)     CSI_CR140_PIXEL_COUNTERS(x)
26961 #define CSI_CSICR141_PIXEL_COUNTERS_MASK     CSI_CR141_PIXEL_COUNTERS_MASK
26962 #define CSI_CSICR141_PIXEL_COUNTERS_SHIFT     CSI_CR141_PIXEL_COUNTERS_SHIFT
26963 #define CSI_CSICR141_PIXEL_COUNTERS(x)     CSI_CR141_PIXEL_COUNTERS(x)
26964 #define CSI_CSICR142_PIXEL_COUNTERS_MASK     CSI_CR142_PIXEL_COUNTERS_MASK
26965 #define CSI_CSICR142_PIXEL_COUNTERS_SHIFT     CSI_CR142_PIXEL_COUNTERS_SHIFT
26966 #define CSI_CSICR142_PIXEL_COUNTERS(x)     CSI_CR142_PIXEL_COUNTERS(x)
26967 #define CSI_CSICR143_PIXEL_COUNTERS_MASK     CSI_CR143_PIXEL_COUNTERS_MASK
26968 #define CSI_CSICR143_PIXEL_COUNTERS_SHIFT     CSI_CR143_PIXEL_COUNTERS_SHIFT
26969 #define CSI_CSICR143_PIXEL_COUNTERS(x)     CSI_CR143_PIXEL_COUNTERS(x)
26970 #define CSI_CSICR144_PIXEL_COUNTERS_MASK     CSI_CR144_PIXEL_COUNTERS_MASK
26971 #define CSI_CSICR144_PIXEL_COUNTERS_SHIFT     CSI_CR144_PIXEL_COUNTERS_SHIFT
26972 #define CSI_CSICR144_PIXEL_COUNTERS(x)     CSI_CR144_PIXEL_COUNTERS(x)
26973 #define CSI_CSICR145_PIXEL_COUNTERS_MASK     CSI_CR145_PIXEL_COUNTERS_MASK
26974 #define CSI_CSICR145_PIXEL_COUNTERS_SHIFT     CSI_CR145_PIXEL_COUNTERS_SHIFT
26975 #define CSI_CSICR145_PIXEL_COUNTERS(x)     CSI_CR145_PIXEL_COUNTERS(x)
26976 #define CSI_CSICR146_PIXEL_COUNTERS_MASK     CSI_CR146_PIXEL_COUNTERS_MASK
26977 #define CSI_CSICR146_PIXEL_COUNTERS_SHIFT     CSI_CR146_PIXEL_COUNTERS_SHIFT
26978 #define CSI_CSICR146_PIXEL_COUNTERS(x)     CSI_CR146_PIXEL_COUNTERS(x)
26979 #define CSI_CSICR147_PIXEL_COUNTERS_MASK     CSI_CR147_PIXEL_COUNTERS_MASK
26980 #define CSI_CSICR147_PIXEL_COUNTERS_SHIFT     CSI_CR147_PIXEL_COUNTERS_SHIFT
26981 #define CSI_CSICR147_PIXEL_COUNTERS(x)     CSI_CR147_PIXEL_COUNTERS(x)
26982 #define CSI_CSICR148_PIXEL_COUNTERS_MASK     CSI_CR148_PIXEL_COUNTERS_MASK
26983 #define CSI_CSICR148_PIXEL_COUNTERS_SHIFT     CSI_CR148_PIXEL_COUNTERS_SHIFT
26984 #define CSI_CSICR148_PIXEL_COUNTERS(x)     CSI_CR148_PIXEL_COUNTERS(x)
26985 #define CSI_CSICR149_PIXEL_COUNTERS_MASK     CSI_CR149_PIXEL_COUNTERS_MASK
26986 #define CSI_CSICR149_PIXEL_COUNTERS_SHIFT     CSI_CR149_PIXEL_COUNTERS_SHIFT
26987 #define CSI_CSICR149_PIXEL_COUNTERS(x)     CSI_CR149_PIXEL_COUNTERS(x)
26988 #define CSI_CSICR150_PIXEL_COUNTERS_MASK     CSI_CR150_PIXEL_COUNTERS_MASK
26989 #define CSI_CSICR150_PIXEL_COUNTERS_SHIFT     CSI_CR150_PIXEL_COUNTERS_SHIFT
26990 #define CSI_CSICR150_PIXEL_COUNTERS(x)     CSI_CR150_PIXEL_COUNTERS(x)
26991 #define CSI_CSICR151_PIXEL_COUNTERS_MASK     CSI_CR151_PIXEL_COUNTERS_MASK
26992 #define CSI_CSICR151_PIXEL_COUNTERS_SHIFT     CSI_CR151_PIXEL_COUNTERS_SHIFT
26993 #define CSI_CSICR151_PIXEL_COUNTERS(x)     CSI_CR151_PIXEL_COUNTERS(x)
26994 #define CSI_CSICR152_PIXEL_COUNTERS_MASK     CSI_CR152_PIXEL_COUNTERS_MASK
26995 #define CSI_CSICR152_PIXEL_COUNTERS_SHIFT     CSI_CR152_PIXEL_COUNTERS_SHIFT
26996 #define CSI_CSICR152_PIXEL_COUNTERS(x)     CSI_CR152_PIXEL_COUNTERS(x)
26997 #define CSI_CSICR153_PIXEL_COUNTERS_MASK     CSI_CR153_PIXEL_COUNTERS_MASK
26998 #define CSI_CSICR153_PIXEL_COUNTERS_SHIFT     CSI_CR153_PIXEL_COUNTERS_SHIFT
26999 #define CSI_CSICR153_PIXEL_COUNTERS(x)     CSI_CR153_PIXEL_COUNTERS(x)
27000 #define CSI_CSICR154_PIXEL_COUNTERS_MASK     CSI_CR154_PIXEL_COUNTERS_MASK
27001 #define CSI_CSICR154_PIXEL_COUNTERS_SHIFT     CSI_CR154_PIXEL_COUNTERS_SHIFT
27002 #define CSI_CSICR154_PIXEL_COUNTERS(x)     CSI_CR154_PIXEL_COUNTERS(x)
27003 #define CSI_CSICR155_PIXEL_COUNTERS_MASK     CSI_CR155_PIXEL_COUNTERS_MASK
27004 #define CSI_CSICR155_PIXEL_COUNTERS_SHIFT     CSI_CR155_PIXEL_COUNTERS_SHIFT
27005 #define CSI_CSICR155_PIXEL_COUNTERS(x)     CSI_CR155_PIXEL_COUNTERS(x)
27006 #define CSI_CSICR156_PIXEL_COUNTERS_MASK     CSI_CR156_PIXEL_COUNTERS_MASK
27007 #define CSI_CSICR156_PIXEL_COUNTERS_SHIFT     CSI_CR156_PIXEL_COUNTERS_SHIFT
27008 #define CSI_CSICR156_PIXEL_COUNTERS(x)     CSI_CR156_PIXEL_COUNTERS(x)
27009 #define CSI_CSICR157_PIXEL_COUNTERS_MASK     CSI_CR157_PIXEL_COUNTERS_MASK
27010 #define CSI_CSICR157_PIXEL_COUNTERS_SHIFT     CSI_CR157_PIXEL_COUNTERS_SHIFT
27011 #define CSI_CSICR157_PIXEL_COUNTERS(x)     CSI_CR157_PIXEL_COUNTERS(x)
27012 #define CSI_CSICR158_PIXEL_COUNTERS_MASK     CSI_CR158_PIXEL_COUNTERS_MASK
27013 #define CSI_CSICR158_PIXEL_COUNTERS_SHIFT     CSI_CR158_PIXEL_COUNTERS_SHIFT
27014 #define CSI_CSICR158_PIXEL_COUNTERS(x)     CSI_CR158_PIXEL_COUNTERS(x)
27015 #define CSI_CSICR159_PIXEL_COUNTERS_MASK     CSI_CR159_PIXEL_COUNTERS_MASK
27016 #define CSI_CSICR159_PIXEL_COUNTERS_SHIFT     CSI_CR159_PIXEL_COUNTERS_SHIFT
27017 #define CSI_CSICR159_PIXEL_COUNTERS(x)     CSI_CR159_PIXEL_COUNTERS(x)
27018 #define CSI_CSICR160_PIXEL_COUNTERS_MASK     CSI_CR160_PIXEL_COUNTERS_MASK
27019 #define CSI_CSICR160_PIXEL_COUNTERS_SHIFT     CSI_CR160_PIXEL_COUNTERS_SHIFT
27020 #define CSI_CSICR160_PIXEL_COUNTERS(x)     CSI_CR160_PIXEL_COUNTERS(x)
27021 #define CSI_CSICR161_PIXEL_COUNTERS_MASK     CSI_CR161_PIXEL_COUNTERS_MASK
27022 #define CSI_CSICR161_PIXEL_COUNTERS_SHIFT     CSI_CR161_PIXEL_COUNTERS_SHIFT
27023 #define CSI_CSICR161_PIXEL_COUNTERS(x)     CSI_CR161_PIXEL_COUNTERS(x)
27024 #define CSI_CSICR162_PIXEL_COUNTERS_MASK     CSI_CR162_PIXEL_COUNTERS_MASK
27025 #define CSI_CSICR162_PIXEL_COUNTERS_SHIFT     CSI_CR162_PIXEL_COUNTERS_SHIFT
27026 #define CSI_CSICR162_PIXEL_COUNTERS(x)     CSI_CR162_PIXEL_COUNTERS(x)
27027 #define CSI_CSICR163_PIXEL_COUNTERS_MASK     CSI_CR163_PIXEL_COUNTERS_MASK
27028 #define CSI_CSICR163_PIXEL_COUNTERS_SHIFT     CSI_CR163_PIXEL_COUNTERS_SHIFT
27029 #define CSI_CSICR163_PIXEL_COUNTERS(x)     CSI_CR163_PIXEL_COUNTERS(x)
27030 #define CSI_CSICR164_PIXEL_COUNTERS_MASK     CSI_CR164_PIXEL_COUNTERS_MASK
27031 #define CSI_CSICR164_PIXEL_COUNTERS_SHIFT     CSI_CR164_PIXEL_COUNTERS_SHIFT
27032 #define CSI_CSICR164_PIXEL_COUNTERS(x)     CSI_CR164_PIXEL_COUNTERS(x)
27033 #define CSI_CSICR165_PIXEL_COUNTERS_MASK     CSI_CR165_PIXEL_COUNTERS_MASK
27034 #define CSI_CSICR165_PIXEL_COUNTERS_SHIFT     CSI_CR165_PIXEL_COUNTERS_SHIFT
27035 #define CSI_CSICR165_PIXEL_COUNTERS(x)     CSI_CR165_PIXEL_COUNTERS(x)
27036 #define CSI_CSICR166_PIXEL_COUNTERS_MASK     CSI_CR166_PIXEL_COUNTERS_MASK
27037 #define CSI_CSICR166_PIXEL_COUNTERS_SHIFT     CSI_CR166_PIXEL_COUNTERS_SHIFT
27038 #define CSI_CSICR166_PIXEL_COUNTERS(x)     CSI_CR166_PIXEL_COUNTERS(x)
27039 #define CSI_CSICR167_PIXEL_COUNTERS_MASK     CSI_CR167_PIXEL_COUNTERS_MASK
27040 #define CSI_CSICR167_PIXEL_COUNTERS_SHIFT     CSI_CR167_PIXEL_COUNTERS_SHIFT
27041 #define CSI_CSICR167_PIXEL_COUNTERS(x)     CSI_CR167_PIXEL_COUNTERS(x)
27042 #define CSI_CSICR168_PIXEL_COUNTERS_MASK     CSI_CR168_PIXEL_COUNTERS_MASK
27043 #define CSI_CSICR168_PIXEL_COUNTERS_SHIFT     CSI_CR168_PIXEL_COUNTERS_SHIFT
27044 #define CSI_CSICR168_PIXEL_COUNTERS(x)     CSI_CR168_PIXEL_COUNTERS(x)
27045 #define CSI_CSICR169_PIXEL_COUNTERS_MASK     CSI_CR169_PIXEL_COUNTERS_MASK
27046 #define CSI_CSICR169_PIXEL_COUNTERS_SHIFT     CSI_CR169_PIXEL_COUNTERS_SHIFT
27047 #define CSI_CSICR169_PIXEL_COUNTERS(x)     CSI_CR169_PIXEL_COUNTERS(x)
27048 #define CSI_CSICR170_PIXEL_COUNTERS_MASK     CSI_CR170_PIXEL_COUNTERS_MASK
27049 #define CSI_CSICR170_PIXEL_COUNTERS_SHIFT     CSI_CR170_PIXEL_COUNTERS_SHIFT
27050 #define CSI_CSICR170_PIXEL_COUNTERS(x)     CSI_CR170_PIXEL_COUNTERS(x)
27051 #define CSI_CSICR171_PIXEL_COUNTERS_MASK     CSI_CR171_PIXEL_COUNTERS_MASK
27052 #define CSI_CSICR171_PIXEL_COUNTERS_SHIFT     CSI_CR171_PIXEL_COUNTERS_SHIFT
27053 #define CSI_CSICR171_PIXEL_COUNTERS(x)     CSI_CR171_PIXEL_COUNTERS(x)
27054 #define CSI_CSICR172_PIXEL_COUNTERS_MASK     CSI_CR172_PIXEL_COUNTERS_MASK
27055 #define CSI_CSICR172_PIXEL_COUNTERS_SHIFT     CSI_CR172_PIXEL_COUNTERS_SHIFT
27056 #define CSI_CSICR172_PIXEL_COUNTERS(x)     CSI_CR172_PIXEL_COUNTERS(x)
27057 #define CSI_CSICR173_PIXEL_COUNTERS_MASK     CSI_CR173_PIXEL_COUNTERS_MASK
27058 #define CSI_CSICR173_PIXEL_COUNTERS_SHIFT     CSI_CR173_PIXEL_COUNTERS_SHIFT
27059 #define CSI_CSICR173_PIXEL_COUNTERS(x)     CSI_CR173_PIXEL_COUNTERS(x)
27060 #define CSI_CSICR174_PIXEL_COUNTERS_MASK     CSI_CR174_PIXEL_COUNTERS_MASK
27061 #define CSI_CSICR174_PIXEL_COUNTERS_SHIFT     CSI_CR174_PIXEL_COUNTERS_SHIFT
27062 #define CSI_CSICR174_PIXEL_COUNTERS(x)     CSI_CR174_PIXEL_COUNTERS(x)
27063 #define CSI_CSICR175_PIXEL_COUNTERS_MASK     CSI_CR175_PIXEL_COUNTERS_MASK
27064 #define CSI_CSICR175_PIXEL_COUNTERS_SHIFT     CSI_CR175_PIXEL_COUNTERS_SHIFT
27065 #define CSI_CSICR175_PIXEL_COUNTERS(x)     CSI_CR175_PIXEL_COUNTERS(x)
27066 #define CSI_CSICR176_PIXEL_COUNTERS_MASK     CSI_CR176_PIXEL_COUNTERS_MASK
27067 #define CSI_CSICR176_PIXEL_COUNTERS_SHIFT     CSI_CR176_PIXEL_COUNTERS_SHIFT
27068 #define CSI_CSICR176_PIXEL_COUNTERS(x)     CSI_CR176_PIXEL_COUNTERS(x)
27069 #define CSI_CSICR177_PIXEL_COUNTERS_MASK     CSI_CR177_PIXEL_COUNTERS_MASK
27070 #define CSI_CSICR177_PIXEL_COUNTERS_SHIFT     CSI_CR177_PIXEL_COUNTERS_SHIFT
27071 #define CSI_CSICR177_PIXEL_COUNTERS(x)     CSI_CR177_PIXEL_COUNTERS(x)
27072 #define CSI_CSICR178_PIXEL_COUNTERS_MASK     CSI_CR178_PIXEL_COUNTERS_MASK
27073 #define CSI_CSICR178_PIXEL_COUNTERS_SHIFT     CSI_CR178_PIXEL_COUNTERS_SHIFT
27074 #define CSI_CSICR178_PIXEL_COUNTERS(x)     CSI_CR178_PIXEL_COUNTERS(x)
27075 #define CSI_CSICR179_PIXEL_COUNTERS_MASK     CSI_CR179_PIXEL_COUNTERS_MASK
27076 #define CSI_CSICR179_PIXEL_COUNTERS_SHIFT     CSI_CR179_PIXEL_COUNTERS_SHIFT
27077 #define CSI_CSICR179_PIXEL_COUNTERS(x)     CSI_CR179_PIXEL_COUNTERS(x)
27078 #define CSI_CSICR180_PIXEL_COUNTERS_MASK     CSI_CR180_PIXEL_COUNTERS_MASK
27079 #define CSI_CSICR180_PIXEL_COUNTERS_SHIFT     CSI_CR180_PIXEL_COUNTERS_SHIFT
27080 #define CSI_CSICR180_PIXEL_COUNTERS(x)     CSI_CR180_PIXEL_COUNTERS(x)
27081 #define CSI_CSICR181_PIXEL_COUNTERS_MASK     CSI_CR181_PIXEL_COUNTERS_MASK
27082 #define CSI_CSICR181_PIXEL_COUNTERS_SHIFT     CSI_CR181_PIXEL_COUNTERS_SHIFT
27083 #define CSI_CSICR181_PIXEL_COUNTERS(x)     CSI_CR181_PIXEL_COUNTERS(x)
27084 #define CSI_CSICR182_PIXEL_COUNTERS_MASK     CSI_CR182_PIXEL_COUNTERS_MASK
27085 #define CSI_CSICR182_PIXEL_COUNTERS_SHIFT     CSI_CR182_PIXEL_COUNTERS_SHIFT
27086 #define CSI_CSICR182_PIXEL_COUNTERS(x)     CSI_CR182_PIXEL_COUNTERS(x)
27087 #define CSI_CSICR183_PIXEL_COUNTERS_MASK     CSI_CR183_PIXEL_COUNTERS_MASK
27088 #define CSI_CSICR183_PIXEL_COUNTERS_SHIFT     CSI_CR183_PIXEL_COUNTERS_SHIFT
27089 #define CSI_CSICR183_PIXEL_COUNTERS(x)     CSI_CR183_PIXEL_COUNTERS(x)
27090 #define CSI_CSICR184_PIXEL_COUNTERS_MASK     CSI_CR184_PIXEL_COUNTERS_MASK
27091 #define CSI_CSICR184_PIXEL_COUNTERS_SHIFT     CSI_CR184_PIXEL_COUNTERS_SHIFT
27092 #define CSI_CSICR184_PIXEL_COUNTERS(x)     CSI_CR184_PIXEL_COUNTERS(x)
27093 #define CSI_CSICR185_PIXEL_COUNTERS_MASK     CSI_CR185_PIXEL_COUNTERS_MASK
27094 #define CSI_CSICR185_PIXEL_COUNTERS_SHIFT     CSI_CR185_PIXEL_COUNTERS_SHIFT
27095 #define CSI_CSICR185_PIXEL_COUNTERS(x)     CSI_CR185_PIXEL_COUNTERS(x)
27096 #define CSI_CSICR186_PIXEL_COUNTERS_MASK     CSI_CR186_PIXEL_COUNTERS_MASK
27097 #define CSI_CSICR186_PIXEL_COUNTERS_SHIFT     CSI_CR186_PIXEL_COUNTERS_SHIFT
27098 #define CSI_CSICR186_PIXEL_COUNTERS(x)     CSI_CR186_PIXEL_COUNTERS(x)
27099 #define CSI_CSICR187_PIXEL_COUNTERS_MASK     CSI_CR187_PIXEL_COUNTERS_MASK
27100 #define CSI_CSICR187_PIXEL_COUNTERS_SHIFT     CSI_CR187_PIXEL_COUNTERS_SHIFT
27101 #define CSI_CSICR187_PIXEL_COUNTERS(x)     CSI_CR187_PIXEL_COUNTERS(x)
27102 #define CSI_CSICR188_PIXEL_COUNTERS_MASK     CSI_CR188_PIXEL_COUNTERS_MASK
27103 #define CSI_CSICR188_PIXEL_COUNTERS_SHIFT     CSI_CR188_PIXEL_COUNTERS_SHIFT
27104 #define CSI_CSICR188_PIXEL_COUNTERS(x)     CSI_CR188_PIXEL_COUNTERS(x)
27105 #define CSI_CSICR189_PIXEL_COUNTERS_MASK     CSI_CR189_PIXEL_COUNTERS_MASK
27106 #define CSI_CSICR189_PIXEL_COUNTERS_SHIFT     CSI_CR189_PIXEL_COUNTERS_SHIFT
27107 #define CSI_CSICR189_PIXEL_COUNTERS(x)     CSI_CR189_PIXEL_COUNTERS(x)
27108 #define CSI_CSICR190_PIXEL_COUNTERS_MASK     CSI_CR190_PIXEL_COUNTERS_MASK
27109 #define CSI_CSICR190_PIXEL_COUNTERS_SHIFT     CSI_CR190_PIXEL_COUNTERS_SHIFT
27110 #define CSI_CSICR190_PIXEL_COUNTERS(x)     CSI_CR190_PIXEL_COUNTERS(x)
27111 #define CSI_CSICR191_PIXEL_COUNTERS_MASK     CSI_CR191_PIXEL_COUNTERS_MASK
27112 #define CSI_CSICR191_PIXEL_COUNTERS_SHIFT     CSI_CR191_PIXEL_COUNTERS_SHIFT
27113 #define CSI_CSICR191_PIXEL_COUNTERS(x)     CSI_CR191_PIXEL_COUNTERS(x)
27114 #define CSI_CSICR192_PIXEL_COUNTERS_MASK     CSI_CR192_PIXEL_COUNTERS_MASK
27115 #define CSI_CSICR192_PIXEL_COUNTERS_SHIFT     CSI_CR192_PIXEL_COUNTERS_SHIFT
27116 #define CSI_CSICR192_PIXEL_COUNTERS(x)     CSI_CR192_PIXEL_COUNTERS(x)
27117 #define CSI_CSICR193_PIXEL_COUNTERS_MASK     CSI_CR193_PIXEL_COUNTERS_MASK
27118 #define CSI_CSICR193_PIXEL_COUNTERS_SHIFT     CSI_CR193_PIXEL_COUNTERS_SHIFT
27119 #define CSI_CSICR193_PIXEL_COUNTERS(x)     CSI_CR193_PIXEL_COUNTERS(x)
27120 #define CSI_CSICR194_PIXEL_COUNTERS_MASK     CSI_CR194_PIXEL_COUNTERS_MASK
27121 #define CSI_CSICR194_PIXEL_COUNTERS_SHIFT     CSI_CR194_PIXEL_COUNTERS_SHIFT
27122 #define CSI_CSICR194_PIXEL_COUNTERS(x)     CSI_CR194_PIXEL_COUNTERS(x)
27123 #define CSI_CSICR195_PIXEL_COUNTERS_MASK     CSI_CR195_PIXEL_COUNTERS_MASK
27124 #define CSI_CSICR195_PIXEL_COUNTERS_SHIFT     CSI_CR195_PIXEL_COUNTERS_SHIFT
27125 #define CSI_CSICR195_PIXEL_COUNTERS(x)     CSI_CR195_PIXEL_COUNTERS(x)
27126 #define CSI_CSICR196_PIXEL_COUNTERS_MASK     CSI_CR196_PIXEL_COUNTERS_MASK
27127 #define CSI_CSICR196_PIXEL_COUNTERS_SHIFT     CSI_CR196_PIXEL_COUNTERS_SHIFT
27128 #define CSI_CSICR196_PIXEL_COUNTERS(x)     CSI_CR196_PIXEL_COUNTERS(x)
27129 #define CSI_CSICR197_PIXEL_COUNTERS_MASK     CSI_CR197_PIXEL_COUNTERS_MASK
27130 #define CSI_CSICR197_PIXEL_COUNTERS_SHIFT     CSI_CR197_PIXEL_COUNTERS_SHIFT
27131 #define CSI_CSICR197_PIXEL_COUNTERS(x)     CSI_CR197_PIXEL_COUNTERS(x)
27132 #define CSI_CSICR198_PIXEL_COUNTERS_MASK     CSI_CR198_PIXEL_COUNTERS_MASK
27133 #define CSI_CSICR198_PIXEL_COUNTERS_SHIFT     CSI_CR198_PIXEL_COUNTERS_SHIFT
27134 #define CSI_CSICR198_PIXEL_COUNTERS(x)     CSI_CR198_PIXEL_COUNTERS(x)
27135 #define CSI_CSICR199_PIXEL_COUNTERS_MASK     CSI_CR199_PIXEL_COUNTERS_MASK
27136 #define CSI_CSICR199_PIXEL_COUNTERS_SHIFT     CSI_CR199_PIXEL_COUNTERS_SHIFT
27137 #define CSI_CSICR199_PIXEL_COUNTERS(x)     CSI_CR199_PIXEL_COUNTERS(x)
27138 #define CSI_CSICR200_PIXEL_COUNTERS_MASK     CSI_CR200_PIXEL_COUNTERS_MASK
27139 #define CSI_CSICR200_PIXEL_COUNTERS_SHIFT     CSI_CR200_PIXEL_COUNTERS_SHIFT
27140 #define CSI_CSICR200_PIXEL_COUNTERS(x)     CSI_CR200_PIXEL_COUNTERS(x)
27141 #define CSI_CSICR201_PIXEL_COUNTERS_MASK     CSI_CR201_PIXEL_COUNTERS_MASK
27142 #define CSI_CSICR201_PIXEL_COUNTERS_SHIFT     CSI_CR201_PIXEL_COUNTERS_SHIFT
27143 #define CSI_CSICR201_PIXEL_COUNTERS(x)     CSI_CR201_PIXEL_COUNTERS(x)
27144 #define CSI_CSICR202_PIXEL_COUNTERS_MASK     CSI_CR202_PIXEL_COUNTERS_MASK
27145 #define CSI_CSICR202_PIXEL_COUNTERS_SHIFT     CSI_CR202_PIXEL_COUNTERS_SHIFT
27146 #define CSI_CSICR202_PIXEL_COUNTERS(x)     CSI_CR202_PIXEL_COUNTERS(x)
27147 #define CSI_CSICR203_PIXEL_COUNTERS_MASK     CSI_CR203_PIXEL_COUNTERS_MASK
27148 #define CSI_CSICR203_PIXEL_COUNTERS_SHIFT     CSI_CR203_PIXEL_COUNTERS_SHIFT
27149 #define CSI_CSICR203_PIXEL_COUNTERS(x)     CSI_CR203_PIXEL_COUNTERS(x)
27150 #define CSI_CSICR204_PIXEL_COUNTERS_MASK     CSI_CR204_PIXEL_COUNTERS_MASK
27151 #define CSI_CSICR204_PIXEL_COUNTERS_SHIFT     CSI_CR204_PIXEL_COUNTERS_SHIFT
27152 #define CSI_CSICR204_PIXEL_COUNTERS(x)     CSI_CR204_PIXEL_COUNTERS(x)
27153 #define CSI_CSICR205_PIXEL_COUNTERS_MASK     CSI_CR205_PIXEL_COUNTERS_MASK
27154 #define CSI_CSICR205_PIXEL_COUNTERS_SHIFT     CSI_CR205_PIXEL_COUNTERS_SHIFT
27155 #define CSI_CSICR205_PIXEL_COUNTERS(x)     CSI_CR205_PIXEL_COUNTERS(x)
27156 #define CSI_CSICR206_PIXEL_COUNTERS_MASK     CSI_CR206_PIXEL_COUNTERS_MASK
27157 #define CSI_CSICR206_PIXEL_COUNTERS_SHIFT     CSI_CR206_PIXEL_COUNTERS_SHIFT
27158 #define CSI_CSICR206_PIXEL_COUNTERS(x)     CSI_CR206_PIXEL_COUNTERS(x)
27159 #define CSI_CSICR207_PIXEL_COUNTERS_MASK     CSI_CR207_PIXEL_COUNTERS_MASK
27160 #define CSI_CSICR207_PIXEL_COUNTERS_SHIFT     CSI_CR207_PIXEL_COUNTERS_SHIFT
27161 #define CSI_CSICR207_PIXEL_COUNTERS(x)     CSI_CR207_PIXEL_COUNTERS(x)
27162 #define CSI_CSICR208_PIXEL_COUNTERS_MASK     CSI_CR208_PIXEL_COUNTERS_MASK
27163 #define CSI_CSICR208_PIXEL_COUNTERS_SHIFT     CSI_CR208_PIXEL_COUNTERS_SHIFT
27164 #define CSI_CSICR208_PIXEL_COUNTERS(x)     CSI_CR208_PIXEL_COUNTERS(x)
27165 #define CSI_CSICR209_PIXEL_COUNTERS_MASK     CSI_CR209_PIXEL_COUNTERS_MASK
27166 #define CSI_CSICR209_PIXEL_COUNTERS_SHIFT     CSI_CR209_PIXEL_COUNTERS_SHIFT
27167 #define CSI_CSICR209_PIXEL_COUNTERS(x)     CSI_CR209_PIXEL_COUNTERS(x)
27168 #define CSI_CSICR210_PIXEL_COUNTERS_MASK     CSI_CR210_PIXEL_COUNTERS_MASK
27169 #define CSI_CSICR210_PIXEL_COUNTERS_SHIFT     CSI_CR210_PIXEL_COUNTERS_SHIFT
27170 #define CSI_CSICR210_PIXEL_COUNTERS(x)     CSI_CR210_PIXEL_COUNTERS(x)
27171 #define CSI_CSICR211_PIXEL_COUNTERS_MASK     CSI_CR211_PIXEL_COUNTERS_MASK
27172 #define CSI_CSICR211_PIXEL_COUNTERS_SHIFT     CSI_CR211_PIXEL_COUNTERS_SHIFT
27173 #define CSI_CSICR211_PIXEL_COUNTERS(x)     CSI_CR211_PIXEL_COUNTERS(x)
27174 #define CSI_CSICR212_PIXEL_COUNTERS_MASK     CSI_CR212_PIXEL_COUNTERS_MASK
27175 #define CSI_CSICR212_PIXEL_COUNTERS_SHIFT     CSI_CR212_PIXEL_COUNTERS_SHIFT
27176 #define CSI_CSICR212_PIXEL_COUNTERS(x)     CSI_CR212_PIXEL_COUNTERS(x)
27177 #define CSI_CSICR213_PIXEL_COUNTERS_MASK     CSI_CR213_PIXEL_COUNTERS_MASK
27178 #define CSI_CSICR213_PIXEL_COUNTERS_SHIFT     CSI_CR213_PIXEL_COUNTERS_SHIFT
27179 #define CSI_CSICR213_PIXEL_COUNTERS(x)     CSI_CR213_PIXEL_COUNTERS(x)
27180 #define CSI_CSICR214_PIXEL_COUNTERS_MASK     CSI_CR214_PIXEL_COUNTERS_MASK
27181 #define CSI_CSICR214_PIXEL_COUNTERS_SHIFT     CSI_CR214_PIXEL_COUNTERS_SHIFT
27182 #define CSI_CSICR214_PIXEL_COUNTERS(x)     CSI_CR214_PIXEL_COUNTERS(x)
27183 #define CSI_CSICR215_PIXEL_COUNTERS_MASK     CSI_CR215_PIXEL_COUNTERS_MASK
27184 #define CSI_CSICR215_PIXEL_COUNTERS_SHIFT     CSI_CR215_PIXEL_COUNTERS_SHIFT
27185 #define CSI_CSICR215_PIXEL_COUNTERS(x)     CSI_CR215_PIXEL_COUNTERS(x)
27186 #define CSI_CSICR216_PIXEL_COUNTERS_MASK     CSI_CR216_PIXEL_COUNTERS_MASK
27187 #define CSI_CSICR216_PIXEL_COUNTERS_SHIFT     CSI_CR216_PIXEL_COUNTERS_SHIFT
27188 #define CSI_CSICR216_PIXEL_COUNTERS(x)     CSI_CR216_PIXEL_COUNTERS(x)
27189 #define CSI_CSICR217_PIXEL_COUNTERS_MASK     CSI_CR217_PIXEL_COUNTERS_MASK
27190 #define CSI_CSICR217_PIXEL_COUNTERS_SHIFT     CSI_CR217_PIXEL_COUNTERS_SHIFT
27191 #define CSI_CSICR217_PIXEL_COUNTERS(x)     CSI_CR217_PIXEL_COUNTERS(x)
27192 #define CSI_CSICR218_PIXEL_COUNTERS_MASK     CSI_CR218_PIXEL_COUNTERS_MASK
27193 #define CSI_CSICR218_PIXEL_COUNTERS_SHIFT     CSI_CR218_PIXEL_COUNTERS_SHIFT
27194 #define CSI_CSICR218_PIXEL_COUNTERS(x)     CSI_CR218_PIXEL_COUNTERS(x)
27195 #define CSI_CSICR219_PIXEL_COUNTERS_MASK     CSI_CR219_PIXEL_COUNTERS_MASK
27196 #define CSI_CSICR219_PIXEL_COUNTERS_SHIFT     CSI_CR219_PIXEL_COUNTERS_SHIFT
27197 #define CSI_CSICR219_PIXEL_COUNTERS(x)     CSI_CR219_PIXEL_COUNTERS(x)
27198 #define CSI_CSICR220_PIXEL_COUNTERS_MASK     CSI_CR220_PIXEL_COUNTERS_MASK
27199 #define CSI_CSICR220_PIXEL_COUNTERS_SHIFT     CSI_CR220_PIXEL_COUNTERS_SHIFT
27200 #define CSI_CSICR220_PIXEL_COUNTERS(x)     CSI_CR220_PIXEL_COUNTERS(x)
27201 #define CSI_CSICR221_PIXEL_COUNTERS_MASK     CSI_CR221_PIXEL_COUNTERS_MASK
27202 #define CSI_CSICR221_PIXEL_COUNTERS_SHIFT     CSI_CR221_PIXEL_COUNTERS_SHIFT
27203 #define CSI_CSICR221_PIXEL_COUNTERS(x)     CSI_CR221_PIXEL_COUNTERS(x)
27204 #define CSI_CSICR222_PIXEL_COUNTERS_MASK     CSI_CR222_PIXEL_COUNTERS_MASK
27205 #define CSI_CSICR222_PIXEL_COUNTERS_SHIFT     CSI_CR222_PIXEL_COUNTERS_SHIFT
27206 #define CSI_CSICR222_PIXEL_COUNTERS(x)     CSI_CR222_PIXEL_COUNTERS(x)
27207 #define CSI_CSICR223_PIXEL_COUNTERS_MASK     CSI_CR223_PIXEL_COUNTERS_MASK
27208 #define CSI_CSICR223_PIXEL_COUNTERS_SHIFT     CSI_CR223_PIXEL_COUNTERS_SHIFT
27209 #define CSI_CSICR223_PIXEL_COUNTERS(x)     CSI_CR223_PIXEL_COUNTERS(x)
27210 #define CSI_CSICR224_PIXEL_COUNTERS_MASK     CSI_CR224_PIXEL_COUNTERS_MASK
27211 #define CSI_CSICR224_PIXEL_COUNTERS_SHIFT     CSI_CR224_PIXEL_COUNTERS_SHIFT
27212 #define CSI_CSICR224_PIXEL_COUNTERS(x)     CSI_CR224_PIXEL_COUNTERS(x)
27213 #define CSI_CSICR225_PIXEL_COUNTERS_MASK     CSI_CR225_PIXEL_COUNTERS_MASK
27214 #define CSI_CSICR225_PIXEL_COUNTERS_SHIFT     CSI_CR225_PIXEL_COUNTERS_SHIFT
27215 #define CSI_CSICR225_PIXEL_COUNTERS(x)     CSI_CR225_PIXEL_COUNTERS(x)
27216 #define CSI_CSICR226_PIXEL_COUNTERS_MASK     CSI_CR226_PIXEL_COUNTERS_MASK
27217 #define CSI_CSICR226_PIXEL_COUNTERS_SHIFT     CSI_CR226_PIXEL_COUNTERS_SHIFT
27218 #define CSI_CSICR226_PIXEL_COUNTERS(x)     CSI_CR226_PIXEL_COUNTERS(x)
27219 #define CSI_CSICR227_PIXEL_COUNTERS_MASK     CSI_CR227_PIXEL_COUNTERS_MASK
27220 #define CSI_CSICR227_PIXEL_COUNTERS_SHIFT     CSI_CR227_PIXEL_COUNTERS_SHIFT
27221 #define CSI_CSICR227_PIXEL_COUNTERS(x)     CSI_CR227_PIXEL_COUNTERS(x)
27222 #define CSI_CSICR228_PIXEL_COUNTERS_MASK     CSI_CR228_PIXEL_COUNTERS_MASK
27223 #define CSI_CSICR228_PIXEL_COUNTERS_SHIFT     CSI_CR228_PIXEL_COUNTERS_SHIFT
27224 #define CSI_CSICR228_PIXEL_COUNTERS(x)     CSI_CR228_PIXEL_COUNTERS(x)
27225 #define CSI_CSICR229_PIXEL_COUNTERS_MASK     CSI_CR229_PIXEL_COUNTERS_MASK
27226 #define CSI_CSICR229_PIXEL_COUNTERS_SHIFT     CSI_CR229_PIXEL_COUNTERS_SHIFT
27227 #define CSI_CSICR229_PIXEL_COUNTERS(x)     CSI_CR229_PIXEL_COUNTERS(x)
27228 #define CSI_CSICR230_PIXEL_COUNTERS_MASK     CSI_CR230_PIXEL_COUNTERS_MASK
27229 #define CSI_CSICR230_PIXEL_COUNTERS_SHIFT     CSI_CR230_PIXEL_COUNTERS_SHIFT
27230 #define CSI_CSICR230_PIXEL_COUNTERS(x)     CSI_CR230_PIXEL_COUNTERS(x)
27231 #define CSI_CSICR231_PIXEL_COUNTERS_MASK     CSI_CR231_PIXEL_COUNTERS_MASK
27232 #define CSI_CSICR231_PIXEL_COUNTERS_SHIFT     CSI_CR231_PIXEL_COUNTERS_SHIFT
27233 #define CSI_CSICR231_PIXEL_COUNTERS(x)     CSI_CR231_PIXEL_COUNTERS(x)
27234 #define CSI_CSICR232_PIXEL_COUNTERS_MASK     CSI_CR232_PIXEL_COUNTERS_MASK
27235 #define CSI_CSICR232_PIXEL_COUNTERS_SHIFT     CSI_CR232_PIXEL_COUNTERS_SHIFT
27236 #define CSI_CSICR232_PIXEL_COUNTERS(x)     CSI_CR232_PIXEL_COUNTERS(x)
27237 #define CSI_CSICR233_PIXEL_COUNTERS_MASK     CSI_CR233_PIXEL_COUNTERS_MASK
27238 #define CSI_CSICR233_PIXEL_COUNTERS_SHIFT     CSI_CR233_PIXEL_COUNTERS_SHIFT
27239 #define CSI_CSICR233_PIXEL_COUNTERS(x)     CSI_CR233_PIXEL_COUNTERS(x)
27240 #define CSI_CSICR234_PIXEL_COUNTERS_MASK     CSI_CR234_PIXEL_COUNTERS_MASK
27241 #define CSI_CSICR234_PIXEL_COUNTERS_SHIFT     CSI_CR234_PIXEL_COUNTERS_SHIFT
27242 #define CSI_CSICR234_PIXEL_COUNTERS(x)     CSI_CR234_PIXEL_COUNTERS(x)
27243 #define CSI_CSICR235_PIXEL_COUNTERS_MASK     CSI_CR235_PIXEL_COUNTERS_MASK
27244 #define CSI_CSICR235_PIXEL_COUNTERS_SHIFT     CSI_CR235_PIXEL_COUNTERS_SHIFT
27245 #define CSI_CSICR235_PIXEL_COUNTERS(x)     CSI_CR235_PIXEL_COUNTERS(x)
27246 #define CSI_CSICR236_PIXEL_COUNTERS_MASK     CSI_CR236_PIXEL_COUNTERS_MASK
27247 #define CSI_CSICR236_PIXEL_COUNTERS_SHIFT     CSI_CR236_PIXEL_COUNTERS_SHIFT
27248 #define CSI_CSICR236_PIXEL_COUNTERS(x)     CSI_CR236_PIXEL_COUNTERS(x)
27249 #define CSI_CSICR237_PIXEL_COUNTERS_MASK     CSI_CR237_PIXEL_COUNTERS_MASK
27250 #define CSI_CSICR237_PIXEL_COUNTERS_SHIFT     CSI_CR237_PIXEL_COUNTERS_SHIFT
27251 #define CSI_CSICR237_PIXEL_COUNTERS(x)     CSI_CR237_PIXEL_COUNTERS(x)
27252 #define CSI_CSICR238_PIXEL_COUNTERS_MASK     CSI_CR238_PIXEL_COUNTERS_MASK
27253 #define CSI_CSICR238_PIXEL_COUNTERS_SHIFT     CSI_CR238_PIXEL_COUNTERS_SHIFT
27254 #define CSI_CSICR238_PIXEL_COUNTERS(x)     CSI_CR238_PIXEL_COUNTERS(x)
27255 #define CSI_CSICR239_PIXEL_COUNTERS_MASK     CSI_CR239_PIXEL_COUNTERS_MASK
27256 #define CSI_CSICR239_PIXEL_COUNTERS_SHIFT     CSI_CR239_PIXEL_COUNTERS_SHIFT
27257 #define CSI_CSICR239_PIXEL_COUNTERS(x)     CSI_CR239_PIXEL_COUNTERS(x)
27258 #define CSI_CSICR240_PIXEL_COUNTERS_MASK     CSI_CR240_PIXEL_COUNTERS_MASK
27259 #define CSI_CSICR240_PIXEL_COUNTERS_SHIFT     CSI_CR240_PIXEL_COUNTERS_SHIFT
27260 #define CSI_CSICR240_PIXEL_COUNTERS(x)     CSI_CR240_PIXEL_COUNTERS(x)
27261 #define CSI_CSICR241_PIXEL_COUNTERS_MASK     CSI_CR241_PIXEL_COUNTERS_MASK
27262 #define CSI_CSICR241_PIXEL_COUNTERS_SHIFT     CSI_CR241_PIXEL_COUNTERS_SHIFT
27263 #define CSI_CSICR241_PIXEL_COUNTERS(x)     CSI_CR241_PIXEL_COUNTERS(x)
27264 #define CSI_CSICR242_PIXEL_COUNTERS_MASK     CSI_CR242_PIXEL_COUNTERS_MASK
27265 #define CSI_CSICR242_PIXEL_COUNTERS_SHIFT     CSI_CR242_PIXEL_COUNTERS_SHIFT
27266 #define CSI_CSICR242_PIXEL_COUNTERS(x)     CSI_CR242_PIXEL_COUNTERS(x)
27267 #define CSI_CSICR243_PIXEL_COUNTERS_MASK     CSI_CR243_PIXEL_COUNTERS_MASK
27268 #define CSI_CSICR243_PIXEL_COUNTERS_SHIFT     CSI_CR243_PIXEL_COUNTERS_SHIFT
27269 #define CSI_CSICR243_PIXEL_COUNTERS(x)     CSI_CR243_PIXEL_COUNTERS(x)
27270 #define CSI_CSICR244_PIXEL_COUNTERS_MASK     CSI_CR244_PIXEL_COUNTERS_MASK
27271 #define CSI_CSICR244_PIXEL_COUNTERS_SHIFT     CSI_CR244_PIXEL_COUNTERS_SHIFT
27272 #define CSI_CSICR244_PIXEL_COUNTERS(x)     CSI_CR244_PIXEL_COUNTERS(x)
27273 #define CSI_CSICR245_PIXEL_COUNTERS_MASK     CSI_CR245_PIXEL_COUNTERS_MASK
27274 #define CSI_CSICR245_PIXEL_COUNTERS_SHIFT     CSI_CR245_PIXEL_COUNTERS_SHIFT
27275 #define CSI_CSICR245_PIXEL_COUNTERS(x)     CSI_CR245_PIXEL_COUNTERS(x)
27276 #define CSI_CSICR246_PIXEL_COUNTERS_MASK     CSI_CR246_PIXEL_COUNTERS_MASK
27277 #define CSI_CSICR246_PIXEL_COUNTERS_SHIFT     CSI_CR246_PIXEL_COUNTERS_SHIFT
27278 #define CSI_CSICR246_PIXEL_COUNTERS(x)     CSI_CR246_PIXEL_COUNTERS(x)
27279 #define CSI_CSICR247_PIXEL_COUNTERS_MASK     CSI_CR247_PIXEL_COUNTERS_MASK
27280 #define CSI_CSICR247_PIXEL_COUNTERS_SHIFT     CSI_CR247_PIXEL_COUNTERS_SHIFT
27281 #define CSI_CSICR247_PIXEL_COUNTERS(x)     CSI_CR247_PIXEL_COUNTERS(x)
27282 #define CSI_CSICR248_PIXEL_COUNTERS_MASK     CSI_CR248_PIXEL_COUNTERS_MASK
27283 #define CSI_CSICR248_PIXEL_COUNTERS_SHIFT     CSI_CR248_PIXEL_COUNTERS_SHIFT
27284 #define CSI_CSICR248_PIXEL_COUNTERS(x)     CSI_CR248_PIXEL_COUNTERS(x)
27285 #define CSI_CSICR249_PIXEL_COUNTERS_MASK     CSI_CR249_PIXEL_COUNTERS_MASK
27286 #define CSI_CSICR249_PIXEL_COUNTERS_SHIFT     CSI_CR249_PIXEL_COUNTERS_SHIFT
27287 #define CSI_CSICR249_PIXEL_COUNTERS(x)     CSI_CR249_PIXEL_COUNTERS(x)
27288 #define CSI_CSICR250_PIXEL_COUNTERS_MASK     CSI_CR250_PIXEL_COUNTERS_MASK
27289 #define CSI_CSICR250_PIXEL_COUNTERS_SHIFT     CSI_CR250_PIXEL_COUNTERS_SHIFT
27290 #define CSI_CSICR250_PIXEL_COUNTERS(x)     CSI_CR250_PIXEL_COUNTERS(x)
27291 #define CSI_CSICR251_PIXEL_COUNTERS_MASK     CSI_CR251_PIXEL_COUNTERS_MASK
27292 #define CSI_CSICR251_PIXEL_COUNTERS_SHIFT     CSI_CR251_PIXEL_COUNTERS_SHIFT
27293 #define CSI_CSICR251_PIXEL_COUNTERS(x)     CSI_CR251_PIXEL_COUNTERS(x)
27294 #define CSI_CSICR252_PIXEL_COUNTERS_MASK     CSI_CR252_PIXEL_COUNTERS_MASK
27295 #define CSI_CSICR252_PIXEL_COUNTERS_SHIFT     CSI_CR252_PIXEL_COUNTERS_SHIFT
27296 #define CSI_CSICR252_PIXEL_COUNTERS(x)     CSI_CR252_PIXEL_COUNTERS(x)
27297 #define CSI_CSICR253_PIXEL_COUNTERS_MASK     CSI_CR253_PIXEL_COUNTERS_MASK
27298 #define CSI_CSICR253_PIXEL_COUNTERS_SHIFT     CSI_CR253_PIXEL_COUNTERS_SHIFT
27299 #define CSI_CSICR253_PIXEL_COUNTERS(x)     CSI_CR253_PIXEL_COUNTERS(x)
27300 #define CSI_CSICR254_PIXEL_COUNTERS_MASK     CSI_CR254_PIXEL_COUNTERS_MASK
27301 #define CSI_CSICR254_PIXEL_COUNTERS_SHIFT     CSI_CR254_PIXEL_COUNTERS_SHIFT
27302 #define CSI_CSICR254_PIXEL_COUNTERS(x)     CSI_CR254_PIXEL_COUNTERS(x)
27303 #define CSI_CSICR255_PIXEL_COUNTERS_MASK     CSI_CR255_PIXEL_COUNTERS_MASK
27304 #define CSI_CSICR255_PIXEL_COUNTERS_SHIFT     CSI_CR255_PIXEL_COUNTERS_SHIFT
27305 #define CSI_CSICR255_PIXEL_COUNTERS(x)     CSI_CR255_PIXEL_COUNTERS(x)
27306 #define CSI_CSICR256_PIXEL_COUNTERS_MASK     CSI_CR256_PIXEL_COUNTERS_MASK
27307 #define CSI_CSICR256_PIXEL_COUNTERS_SHIFT     CSI_CR256_PIXEL_COUNTERS_SHIFT
27308 #define CSI_CSICR256_PIXEL_COUNTERS(x)     CSI_CR256_PIXEL_COUNTERS(x)
27309 #define CSI_CSICR257_PIXEL_COUNTERS_MASK     CSI_CR257_PIXEL_COUNTERS_MASK
27310 #define CSI_CSICR257_PIXEL_COUNTERS_SHIFT     CSI_CR257_PIXEL_COUNTERS_SHIFT
27311 #define CSI_CSICR257_PIXEL_COUNTERS(x)     CSI_CR257_PIXEL_COUNTERS(x)
27312 #define CSI_CSICR258_PIXEL_COUNTERS_MASK     CSI_CR258_PIXEL_COUNTERS_MASK
27313 #define CSI_CSICR258_PIXEL_COUNTERS_SHIFT     CSI_CR258_PIXEL_COUNTERS_SHIFT
27314 #define CSI_CSICR258_PIXEL_COUNTERS(x)     CSI_CR258_PIXEL_COUNTERS(x)
27315 #define CSI_CSICR259_PIXEL_COUNTERS_MASK     CSI_CR259_PIXEL_COUNTERS_MASK
27316 #define CSI_CSICR259_PIXEL_COUNTERS_SHIFT     CSI_CR259_PIXEL_COUNTERS_SHIFT
27317 #define CSI_CSICR259_PIXEL_COUNTERS(x)     CSI_CR259_PIXEL_COUNTERS(x)
27318 #define CSI_CSICR260_PIXEL_COUNTERS_MASK     CSI_CR260_PIXEL_COUNTERS_MASK
27319 #define CSI_CSICR260_PIXEL_COUNTERS_SHIFT     CSI_CR260_PIXEL_COUNTERS_SHIFT
27320 #define CSI_CSICR260_PIXEL_COUNTERS(x)     CSI_CR260_PIXEL_COUNTERS(x)
27321 #define CSI_CSICR261_PIXEL_COUNTERS_MASK     CSI_CR261_PIXEL_COUNTERS_MASK
27322 #define CSI_CSICR261_PIXEL_COUNTERS_SHIFT     CSI_CR261_PIXEL_COUNTERS_SHIFT
27323 #define CSI_CSICR261_PIXEL_COUNTERS(x)     CSI_CR261_PIXEL_COUNTERS(x)
27324 #define CSI_CSICR262_PIXEL_COUNTERS_MASK     CSI_CR262_PIXEL_COUNTERS_MASK
27325 #define CSI_CSICR262_PIXEL_COUNTERS_SHIFT     CSI_CR262_PIXEL_COUNTERS_SHIFT
27326 #define CSI_CSICR262_PIXEL_COUNTERS(x)     CSI_CR262_PIXEL_COUNTERS(x)
27327 #define CSI_CSICR263_PIXEL_COUNTERS_MASK     CSI_CR263_PIXEL_COUNTERS_MASK
27328 #define CSI_CSICR263_PIXEL_COUNTERS_SHIFT     CSI_CR263_PIXEL_COUNTERS_SHIFT
27329 #define CSI_CSICR263_PIXEL_COUNTERS(x)     CSI_CR263_PIXEL_COUNTERS(x)
27330 #define CSI_CSICR264_PIXEL_COUNTERS_MASK     CSI_CR264_PIXEL_COUNTERS_MASK
27331 #define CSI_CSICR264_PIXEL_COUNTERS_SHIFT     CSI_CR264_PIXEL_COUNTERS_SHIFT
27332 #define CSI_CSICR264_PIXEL_COUNTERS(x)     CSI_CR264_PIXEL_COUNTERS(x)
27333 #define CSI_CSICR265_PIXEL_COUNTERS_MASK     CSI_CR265_PIXEL_COUNTERS_MASK
27334 #define CSI_CSICR265_PIXEL_COUNTERS_SHIFT     CSI_CR265_PIXEL_COUNTERS_SHIFT
27335 #define CSI_CSICR265_PIXEL_COUNTERS(x)     CSI_CR265_PIXEL_COUNTERS(x)
27336 #define CSI_CSICR266_PIXEL_COUNTERS_MASK     CSI_CR266_PIXEL_COUNTERS_MASK
27337 #define CSI_CSICR266_PIXEL_COUNTERS_SHIFT     CSI_CR266_PIXEL_COUNTERS_SHIFT
27338 #define CSI_CSICR266_PIXEL_COUNTERS(x)     CSI_CR266_PIXEL_COUNTERS(x)
27339 #define CSI_CSICR267_PIXEL_COUNTERS_MASK     CSI_CR267_PIXEL_COUNTERS_MASK
27340 #define CSI_CSICR267_PIXEL_COUNTERS_SHIFT     CSI_CR267_PIXEL_COUNTERS_SHIFT
27341 #define CSI_CSICR267_PIXEL_COUNTERS(x)     CSI_CR267_PIXEL_COUNTERS(x)
27342 #define CSI_CSICR268_PIXEL_COUNTERS_MASK     CSI_CR268_PIXEL_COUNTERS_MASK
27343 #define CSI_CSICR268_PIXEL_COUNTERS_SHIFT     CSI_CR268_PIXEL_COUNTERS_SHIFT
27344 #define CSI_CSICR268_PIXEL_COUNTERS(x)     CSI_CR268_PIXEL_COUNTERS(x)
27345 #define CSI_CSICR269_PIXEL_COUNTERS_MASK     CSI_CR269_PIXEL_COUNTERS_MASK
27346 #define CSI_CSICR269_PIXEL_COUNTERS_SHIFT     CSI_CR269_PIXEL_COUNTERS_SHIFT
27347 #define CSI_CSICR269_PIXEL_COUNTERS(x)     CSI_CR269_PIXEL_COUNTERS(x)
27348 #define CSI_CSICR270_PIXEL_COUNTERS_MASK     CSI_CR270_PIXEL_COUNTERS_MASK
27349 #define CSI_CSICR270_PIXEL_COUNTERS_SHIFT     CSI_CR270_PIXEL_COUNTERS_SHIFT
27350 #define CSI_CSICR270_PIXEL_COUNTERS(x)     CSI_CR270_PIXEL_COUNTERS(x)
27351 #define CSI_CSICR271_PIXEL_COUNTERS_MASK     CSI_CR271_PIXEL_COUNTERS_MASK
27352 #define CSI_CSICR271_PIXEL_COUNTERS_SHIFT     CSI_CR271_PIXEL_COUNTERS_SHIFT
27353 #define CSI_CSICR271_PIXEL_COUNTERS(x)     CSI_CR271_PIXEL_COUNTERS(x)
27354 #define CSI_CSICR272_PIXEL_COUNTERS_MASK     CSI_CR272_PIXEL_COUNTERS_MASK
27355 #define CSI_CSICR272_PIXEL_COUNTERS_SHIFT     CSI_CR272_PIXEL_COUNTERS_SHIFT
27356 #define CSI_CSICR272_PIXEL_COUNTERS(x)     CSI_CR272_PIXEL_COUNTERS(x)
27357 #define CSI_CSICR273_PIXEL_COUNTERS_MASK     CSI_CR273_PIXEL_COUNTERS_MASK
27358 #define CSI_CSICR273_PIXEL_COUNTERS_SHIFT     CSI_CR273_PIXEL_COUNTERS_SHIFT
27359 #define CSI_CSICR273_PIXEL_COUNTERS(x)     CSI_CR273_PIXEL_COUNTERS(x)
27360 #define CSI_CSICR274_PIXEL_COUNTERS_MASK     CSI_CR274_PIXEL_COUNTERS_MASK
27361 #define CSI_CSICR274_PIXEL_COUNTERS_SHIFT     CSI_CR274_PIXEL_COUNTERS_SHIFT
27362 #define CSI_CSICR274_PIXEL_COUNTERS(x)     CSI_CR274_PIXEL_COUNTERS(x)
27363 #define CSI_CSICR275_PIXEL_COUNTERS_MASK     CSI_CR275_PIXEL_COUNTERS_MASK
27364 #define CSI_CSICR275_PIXEL_COUNTERS_SHIFT     CSI_CR275_PIXEL_COUNTERS_SHIFT
27365 #define CSI_CSICR275_PIXEL_COUNTERS(x)     CSI_CR275_PIXEL_COUNTERS(x)
27366 #define CSI_CSICR276_PIXEL_COUNTERS_MASK     CSI_CR276_PIXEL_COUNTERS_MASK
27367 #define CSI_CSICR276_PIXEL_COUNTERS_SHIFT     CSI_CR276_PIXEL_COUNTERS_SHIFT
27368 #define CSI_CSICR276_PIXEL_COUNTERS(x)     CSI_CR276_PIXEL_COUNTERS(x)
27369 
27370 
27371 /*!
27372  * @}
27373  */ /* end of group CSI_Peripheral_Access_Layer */
27374 
27375 
27376 /* ----------------------------------------------------------------------------
27377    -- DAC Peripheral Access Layer
27378    ---------------------------------------------------------------------------- */
27379 
27380 /*!
27381  * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
27382  * @{
27383  */
27384 
27385 /** DAC - Register Layout Typedef */
27386 typedef struct {
27387   __I  uint32_t VERID;                             /**< Version Identifier Register, offset: 0x0 */
27388   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
27389   __O  uint32_t DATA;                              /**< DAC Data Register, offset: 0x8 */
27390   __IO uint32_t CR;                                /**< DAC Status and Control Register, offset: 0xC */
27391   __I  uint32_t PTR;                               /**< DAC FIFO Pointer Register, offset: 0x10 */
27392   __IO uint32_t CR2;                               /**< DAC Status and Control Register 2, offset: 0x14 */
27393 } DAC_Type;
27394 
27395 /* ----------------------------------------------------------------------------
27396    -- DAC Register Masks
27397    ---------------------------------------------------------------------------- */
27398 
27399 /*!
27400  * @addtogroup DAC_Register_Masks DAC Register Masks
27401  * @{
27402  */
27403 
27404 /*! @name VERID - Version Identifier Register */
27405 /*! @{ */
27406 
27407 #define DAC_VERID_FEATURE_MASK                   (0xFFFFU)
27408 #define DAC_VERID_FEATURE_SHIFT                  (0U)
27409 /*! FEATURE - Feature Identification Number
27410  *  0b0000000000000000..Standard feature set
27411  *  0b0000000000000001..C40 feature set
27412  *  0b0000000000000010..5V DAC feature set
27413  *  0b0000000000000100..ADC BIST feature set
27414  */
27415 #define DAC_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK)
27416 
27417 #define DAC_VERID_MINOR_MASK                     (0xFF0000U)
27418 #define DAC_VERID_MINOR_SHIFT                    (16U)
27419 /*! MINOR - Minor version number */
27420 #define DAC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK)
27421 
27422 #define DAC_VERID_MAJOR_MASK                     (0xFF000000U)
27423 #define DAC_VERID_MAJOR_SHIFT                    (24U)
27424 /*! MAJOR - Major version number */
27425 #define DAC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK)
27426 /*! @} */
27427 
27428 /*! @name PARAM - Parameter Register */
27429 /*! @{ */
27430 
27431 #define DAC_PARAM_FIFOSZ_MASK                    (0x7U)
27432 #define DAC_PARAM_FIFOSZ_SHIFT                   (0U)
27433 /*! FIFOSZ - FIFO size
27434  *  0b000..FIFO depth is 2
27435  *  0b001..FIFO depth is 4
27436  *  0b010..FIFO depth is 8
27437  *  0b011..FIFO depth is 16
27438  *  0b100..FIFO depth is 32
27439  *  0b101..FIFO depth is 64
27440  *  0b110..FIFO depth is 128
27441  *  0b111..FIFO depth is 256
27442  */
27443 #define DAC_PARAM_FIFOSZ(x)                      (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)
27444 /*! @} */
27445 
27446 /*! @name DATA - DAC Data Register */
27447 /*! @{ */
27448 
27449 #define DAC_DATA_DATA0_MASK                      (0xFFFU)
27450 #define DAC_DATA_DATA0_SHIFT                     (0U)
27451 /*! DATA0 - FIFO DATA0 */
27452 #define DAC_DATA_DATA0(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK)
27453 /*! @} */
27454 
27455 /*! @name CR - DAC Status and Control Register */
27456 /*! @{ */
27457 
27458 #define DAC_CR_FULLF_MASK                        (0x1U)
27459 #define DAC_CR_FULLF_SHIFT                       (0U)
27460 /*! FULLF - Full Flag
27461  *  0b0..FIFO is not full.
27462  *  0b1..FIFO is full.
27463  */
27464 #define DAC_CR_FULLF(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK)
27465 
27466 #define DAC_CR_NEMPTF_MASK                       (0x2U)
27467 #define DAC_CR_NEMPTF_SHIFT                      (1U)
27468 /*! NEMPTF - Nearly Empty Flag
27469  *  0b0..More than one data is available in the FIFO.
27470  *  0b1..One data is available in the FIFO.
27471  */
27472 #define DAC_CR_NEMPTF(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK)
27473 
27474 #define DAC_CR_WMF_MASK                          (0x4U)
27475 #define DAC_CR_WMF_SHIFT                         (2U)
27476 /*! WMF - FIFO Watermark Status Flag
27477  *  0b0..The DAC buffer read pointer has not reached the watermark level.
27478  *  0b1..The DAC buffer read pointer has reached the watermark level.
27479  */
27480 #define DAC_CR_WMF(x)                            (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK)
27481 
27482 #define DAC_CR_UDFF_MASK                         (0x8U)
27483 #define DAC_CR_UDFF_SHIFT                        (3U)
27484 /*! UDFF - Underflow Flag
27485  *  0b0..No underflow has occurred since the last time the flag was cleared.
27486  *  0b1..At least one trigger underflow has occurred since the last time the flag was cleared.
27487  */
27488 #define DAC_CR_UDFF(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK)
27489 
27490 #define DAC_CR_OVFF_MASK                         (0x10U)
27491 #define DAC_CR_OVFF_SHIFT                        (4U)
27492 /*! OVFF - Overflow Flag
27493  *  0b0..No overflow has occurred since the last time the flag was cleared.
27494  *  0b1..At least one FIFO overflow has occurred since the last time the flag was cleared.
27495  */
27496 #define DAC_CR_OVFF(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK)
27497 
27498 #define DAC_CR_FULLIE_MASK                       (0x100U)
27499 #define DAC_CR_FULLIE_SHIFT                      (8U)
27500 /*! FULLIE - Full Interrupt Enable
27501  *  0b0..FIFO Full interrupt is disabled.
27502  *  0b1..FIFO Full interrupt is enabled.
27503  */
27504 #define DAC_CR_FULLIE(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK)
27505 
27506 #define DAC_CR_EMPTIE_MASK                       (0x200U)
27507 #define DAC_CR_EMPTIE_SHIFT                      (9U)
27508 /*! EMPTIE - Nearly Empty Interrupt Enable
27509  *  0b0..FIFO Nearly Empty interrupt is disabled.
27510  *  0b1..FIFO Nearly Empty interrupt is enabled.
27511  */
27512 #define DAC_CR_EMPTIE(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK)
27513 
27514 #define DAC_CR_WTMIE_MASK                        (0x400U)
27515 #define DAC_CR_WTMIE_SHIFT                       (10U)
27516 /*! WTMIE - Watermark Interrupt Enable
27517  *  0b0..Watermark interrupt is disabled.
27518  *  0b1..Watermark interrupt is enabled.
27519  */
27520 #define DAC_CR_WTMIE(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK)
27521 
27522 #define DAC_CR_SWTRG_MASK                        (0x1000U)
27523 #define DAC_CR_SWTRG_SHIFT                       (12U)
27524 /*! SWTRG - DAC Software Trigger
27525  *  0b0..The DAC soft trigger is not valid.
27526  *  0b1..The DAC soft trigger is valid.
27527  */
27528 #define DAC_CR_SWTRG(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK)
27529 
27530 #define DAC_CR_TRGSEL_MASK                       (0x2000U)
27531 #define DAC_CR_TRGSEL_SHIFT                      (13U)
27532 /*! TRGSEL - DAC Trigger Select
27533  *  0b0..The DAC hardware trigger is selected.
27534  *  0b1..The DAC software trigger is selected.
27535  */
27536 #define DAC_CR_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK)
27537 
27538 #define DAC_CR_DACRFS_MASK                       (0x4000U)
27539 #define DAC_CR_DACRFS_SHIFT                      (14U)
27540 /*! DACRFS - DAC Reference Select
27541  *  0b0..The DAC selects DACREF_1 as the reference voltage.
27542  *  0b1..The DAC selects DACREF_2 as the reference voltage.
27543  */
27544 #define DAC_CR_DACRFS(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK)
27545 
27546 #define DAC_CR_DACEN_MASK                        (0x8000U)
27547 #define DAC_CR_DACEN_SHIFT                       (15U)
27548 /*! DACEN - DAC Enable
27549  *  0b0..The DAC system is disabled.
27550  *  0b1..The DAC system is enabled.
27551  */
27552 #define DAC_CR_DACEN(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK)
27553 
27554 #define DAC_CR_FIFOEN_MASK                       (0x10000U)
27555 #define DAC_CR_FIFOEN_SHIFT                      (16U)
27556 /*! FIFOEN - FIFO Enable
27557  *  0b0..FIFO is disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion.
27558  *  0b1..FIFO is enabled. Data will first read from FIFO to buffer then go to conversion.
27559  */
27560 #define DAC_CR_FIFOEN(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK)
27561 
27562 #define DAC_CR_SWMD_MASK                         (0x20000U)
27563 #define DAC_CR_SWMD_SHIFT                        (17U)
27564 /*! SWMD - DAC FIFO Mode Select
27565  *  0b0..Normal mode
27566  *  0b1..Swing back mode
27567  */
27568 #define DAC_CR_SWMD(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK)
27569 
27570 #define DAC_CR_UVIE_MASK                         (0x40000U)
27571 #define DAC_CR_UVIE_SHIFT                        (18U)
27572 /*! UVIE - Underflow and overflow interrupt enable
27573  *  0b0..Underflow and overflow interrupt is disabled.
27574  *  0b1..Underflow and overflow interrupt is enabled.
27575  */
27576 #define DAC_CR_UVIE(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK)
27577 
27578 #define DAC_CR_FIFORST_MASK                      (0x200000U)
27579 #define DAC_CR_FIFORST_SHIFT                     (21U)
27580 /*! FIFORST - FIFO Reset
27581  *  0b0..No effect
27582  *  0b1..FIFO reset
27583  */
27584 #define DAC_CR_FIFORST(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK)
27585 
27586 #define DAC_CR_SWRST_MASK                        (0x400000U)
27587 #define DAC_CR_SWRST_SHIFT                       (22U)
27588 /*! SWRST - Software reset */
27589 #define DAC_CR_SWRST(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK)
27590 
27591 #define DAC_CR_DMAEN_MASK                        (0x800000U)
27592 #define DAC_CR_DMAEN_SHIFT                       (23U)
27593 /*! DMAEN - DMA Enable Select
27594  *  0b0..DMA is disabled.
27595  *  0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The
27596  *       interrupts will not be presented on this module at the same time.
27597  */
27598 #define DAC_CR_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK)
27599 
27600 #define DAC_CR_WML_MASK                          (0xFF000000U)
27601 #define DAC_CR_WML_SHIFT                         (24U)
27602 /*! WML - Watermark Level Select */
27603 #define DAC_CR_WML(x)                            (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK)
27604 /*! @} */
27605 
27606 /*! @name PTR - DAC FIFO Pointer Register */
27607 /*! @{ */
27608 
27609 #define DAC_PTR_DACWFP_MASK                      (0xFFU)
27610 #define DAC_PTR_DACWFP_SHIFT                     (0U)
27611 /*! DACWFP - DACWFP */
27612 #define DAC_PTR_DACWFP(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK)
27613 
27614 #define DAC_PTR_DACRFP_MASK                      (0xFF0000U)
27615 #define DAC_PTR_DACRFP_SHIFT                     (16U)
27616 /*! DACRFP - DACRFP */
27617 #define DAC_PTR_DACRFP(x)                        (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK)
27618 /*! @} */
27619 
27620 /*! @name CR2 - DAC Status and Control Register 2 */
27621 /*! @{ */
27622 
27623 #define DAC_CR2_BFEN_MASK                        (0x1U)
27624 #define DAC_CR2_BFEN_SHIFT                       (0U)
27625 /*! BFEN - Buffer Enable
27626  *  0b0..Opamp is not used as buffer
27627  *  0b1..Opamp is used as buffer
27628  */
27629 #define DAC_CR2_BFEN(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK)
27630 
27631 #define DAC_CR2_OEN_MASK                         (0x2U)
27632 #define DAC_CR2_OEN_SHIFT                        (1U)
27633 /*! OEN - Optional Enable
27634  *  0b0..Output buffer is not bypassed
27635  *  0b1..Output buffer is bypassed
27636  */
27637 #define DAC_CR2_OEN(x)                           (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK)
27638 
27639 #define DAC_CR2_BFMS_MASK                        (0x4U)
27640 #define DAC_CR2_BFMS_SHIFT                       (2U)
27641 /*! BFMS - Buffer Middle Speed Select
27642  *  0b0..Buffer middle speed not selected
27643  *  0b1..Buffer middle speed selected
27644  */
27645 #define DAC_CR2_BFMS(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK)
27646 
27647 #define DAC_CR2_BFHS_MASK                        (0x8U)
27648 #define DAC_CR2_BFHS_SHIFT                       (3U)
27649 /*! BFHS - Buffer High Speed Select
27650  *  0b0..Buffer high speed not selected
27651  *  0b1..Buffer high speed selected
27652  */
27653 #define DAC_CR2_BFHS(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK)
27654 
27655 #define DAC_CR2_IREF2_MASK                       (0x10U)
27656 #define DAC_CR2_IREF2_SHIFT                      (4U)
27657 /*! IREF2 - Internal PTAT (Proportional To Absolute Temperature) Current Reference Select
27658  *  0b0..Internal PTAT Current Reference not selected
27659  *  0b1..Internal PTAT Current Reference selected
27660  */
27661 #define DAC_CR2_IREF2(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK)
27662 
27663 #define DAC_CR2_IREF1_MASK                       (0x20U)
27664 #define DAC_CR2_IREF1_SHIFT                      (5U)
27665 /*! IREF1 - Internal ZTC (Zero Temperature Coefficient) Current Reference Select
27666  *  0b0..Internal ZTC Current Reference not selected
27667  *  0b1..Internal ZTC Current Reference selected
27668  */
27669 #define DAC_CR2_IREF1(x)                         (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK)
27670 
27671 #define DAC_CR2_IREF_MASK                        (0x40U)
27672 #define DAC_CR2_IREF_SHIFT                       (6U)
27673 /*! IREF - Internal Current Reference Select
27674  *  0b0..Internal Current Reference not selected
27675  *  0b1..Internal Current Reference selected
27676  */
27677 #define DAC_CR2_IREF(x)                          (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK)
27678 /*! @} */
27679 
27680 
27681 /*!
27682  * @}
27683  */ /* end of group DAC_Register_Masks */
27684 
27685 
27686 /* DAC - Peripheral instance base addresses */
27687 /** Peripheral DAC base address */
27688 #define DAC_BASE                                 (0x40064000u)
27689 /** Peripheral DAC base pointer */
27690 #define DAC                                      ((DAC_Type *)DAC_BASE)
27691 /** Array initializer of DAC peripheral base addresses */
27692 #define DAC_BASE_ADDRS                           { DAC_BASE }
27693 /** Array initializer of DAC peripheral base pointers */
27694 #define DAC_BASE_PTRS                            { DAC }
27695 /** Interrupt vectors for the DAC peripheral type */
27696 #define DAC_IRQS                                 { DAC_IRQn }
27697 
27698 /*!
27699  * @}
27700  */ /* end of group DAC_Peripheral_Access_Layer */
27701 
27702 
27703 /* ----------------------------------------------------------------------------
27704    -- DCDC Peripheral Access Layer
27705    ---------------------------------------------------------------------------- */
27706 
27707 /*!
27708  * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer
27709  * @{
27710  */
27711 
27712 /** DCDC - Register Layout Typedef */
27713 typedef struct {
27714   __IO uint32_t CTRL0;                             /**< DCDC Control Register 0, offset: 0x0 */
27715   __IO uint32_t CTRL1;                             /**< DCDC Control Register 1, offset: 0x4 */
27716   __IO uint32_t REG0;                              /**< DCDC Register 0, offset: 0x8 */
27717   __IO uint32_t REG1;                              /**< DCDC Register 1, offset: 0xC */
27718   __IO uint32_t REG2;                              /**< DCDC Register 2, offset: 0x10 */
27719   __IO uint32_t REG3;                              /**< DCDC Register 3, offset: 0x14 */
27720   __IO uint32_t REG4;                              /**< DCDC Register 4, offset: 0x18 */
27721   __IO uint32_t REG5;                              /**< DCDC Register 5, offset: 0x1C */
27722   __IO uint32_t REG6;                              /**< DCDC Register 6, offset: 0x20 */
27723   __IO uint32_t REG7;                              /**< DCDC Register 7, offset: 0x24 */
27724   __IO uint32_t REG7P;                             /**< DCDC Register 7 plus, offset: 0x28 */
27725   __IO uint32_t REG8;                              /**< DCDC Register 8, offset: 0x2C */
27726   __IO uint32_t REG9;                              /**< DCDC Register 9, offset: 0x30 */
27727   __IO uint32_t REG10;                             /**< DCDC Register 10, offset: 0x34 */
27728   __IO uint32_t REG11;                             /**< DCDC Register 11, offset: 0x38 */
27729   __IO uint32_t REG12;                             /**< DCDC Register 12, offset: 0x3C */
27730   __IO uint32_t REG13;                             /**< DCDC Register 13, offset: 0x40 */
27731   __IO uint32_t REG14;                             /**< DCDC Register 14, offset: 0x44 */
27732   __IO uint32_t REG15;                             /**< DCDC Register 15, offset: 0x48 */
27733   __IO uint32_t REG16;                             /**< DCDC Register 16, offset: 0x4C */
27734   __IO uint32_t REG17;                             /**< DCDC Register 17, offset: 0x50 */
27735   __IO uint32_t REG18;                             /**< DCDC Register 18, offset: 0x54 */
27736   __IO uint32_t REG19;                             /**< DCDC Register 19, offset: 0x58 */
27737   __IO uint32_t REG20;                             /**< DCDC Register 20, offset: 0x5C */
27738   __IO uint32_t REG21;                             /**< DCDC Register 21, offset: 0x60 */
27739   __IO uint32_t REG22;                             /**< DCDC Register 22, offset: 0x64 */
27740   __IO uint32_t REG23;                             /**< DCDC Register 23, offset: 0x68 */
27741   __IO uint32_t REG24;                             /**< DCDC Register 24, offset: 0x6C */
27742 } DCDC_Type;
27743 
27744 /* ----------------------------------------------------------------------------
27745    -- DCDC Register Masks
27746    ---------------------------------------------------------------------------- */
27747 
27748 /*!
27749  * @addtogroup DCDC_Register_Masks DCDC Register Masks
27750  * @{
27751  */
27752 
27753 /*! @name CTRL0 - DCDC Control Register 0 */
27754 /*! @{ */
27755 
27756 #define DCDC_CTRL0_ENABLE_MASK                   (0x1U)
27757 #define DCDC_CTRL0_ENABLE_SHIFT                  (0U)
27758 /*! ENABLE
27759  *  0b0..Disable (Bypass)
27760  *  0b1..Enable
27761  */
27762 #define DCDC_CTRL0_ENABLE(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
27763 
27764 #define DCDC_CTRL0_DIG_EN_MASK                   (0x2U)
27765 #define DCDC_CTRL0_DIG_EN_SHIFT                  (1U)
27766 /*! DIG_EN
27767  *  0b0..Reserved
27768  *  0b1..Enable
27769  */
27770 #define DCDC_CTRL0_DIG_EN(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DIG_EN_SHIFT)) & DCDC_CTRL0_DIG_EN_MASK)
27771 
27772 #define DCDC_CTRL0_STBY_EN_MASK                  (0x4U)
27773 #define DCDC_CTRL0_STBY_EN_SHIFT                 (2U)
27774 /*! STBY_EN
27775  *  0b1..Enter into standby mode
27776  */
27777 #define DCDC_CTRL0_STBY_EN(x)                    (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_EN_SHIFT)) & DCDC_CTRL0_STBY_EN_MASK)
27778 
27779 #define DCDC_CTRL0_LP_MODE_EN_MASK               (0x8U)
27780 #define DCDC_CTRL0_LP_MODE_EN_SHIFT              (3U)
27781 /*! LP_MODE_EN
27782  *  0b1..Enter into low-power mode
27783  */
27784 #define DCDC_CTRL0_LP_MODE_EN(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_LP_MODE_EN_MASK)
27785 
27786 #define DCDC_CTRL0_STBY_LP_MODE_EN_MASK          (0x10U)
27787 #define DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT         (4U)
27788 /*! STBY_LP_MODE_EN
27789  *  0b0..Disable DCDC entry into low-power mode from a GPC standby request
27790  *  0b1..Enable DCDC to enter into low-power mode from a GPC standby request
27791  */
27792 #define DCDC_CTRL0_STBY_LP_MODE_EN(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_STBY_LP_MODE_EN_MASK)
27793 
27794 #define DCDC_CTRL0_ENABLE_DCDC_CNT_MASK          (0x20U)
27795 #define DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT         (5U)
27796 /*! ENABLE_DCDC_CNT - Enable internal count for DCDC_OK timeout
27797  *  0b0..Wait DCDC_OK for ACK
27798  *  0b1..Enable internal count for DCDC_OK timeout
27799  */
27800 #define DCDC_CTRL0_ENABLE_DCDC_CNT(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT)) & DCDC_CTRL0_ENABLE_DCDC_CNT_MASK)
27801 
27802 #define DCDC_CTRL0_TRIM_HOLD_MASK                (0x40U)
27803 #define DCDC_CTRL0_TRIM_HOLD_SHIFT               (6U)
27804 /*! TRIM_HOLD - Hold trim input
27805  *  0b0..Sample trim input
27806  *  0b1..Hold trim input
27807  */
27808 #define DCDC_CTRL0_TRIM_HOLD(x)                  (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_TRIM_HOLD_SHIFT)) & DCDC_CTRL0_TRIM_HOLD_MASK)
27809 
27810 #define DCDC_CTRL0_DEBUG_BITS_MASK               (0x7FF80000U)
27811 #define DCDC_CTRL0_DEBUG_BITS_SHIFT              (19U)
27812 /*! DEBUG_BITS - DEBUG_BITS[11:0] */
27813 #define DCDC_CTRL0_DEBUG_BITS(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DEBUG_BITS_SHIFT)) & DCDC_CTRL0_DEBUG_BITS_MASK)
27814 
27815 #define DCDC_CTRL0_CONTROL_MODE_MASK             (0x80000000U)
27816 #define DCDC_CTRL0_CONTROL_MODE_SHIFT            (31U)
27817 /*! CONTROL_MODE - Control mode
27818  *  0b0..Software control mode
27819  *  0b1..Hardware control mode (controlled by GPC Setpoints)
27820  */
27821 #define DCDC_CTRL0_CONTROL_MODE(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
27822 /*! @} */
27823 
27824 /*! @name CTRL1 - DCDC Control Register 1 */
27825 /*! @{ */
27826 
27827 #define DCDC_CTRL1_VDD1P8CTRL_TRG_MASK           (0x1FU)
27828 #define DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT          (0U)
27829 /*! VDD1P8CTRL_TRG
27830  *  0b11111..2.275V
27831  *  0b01100..1.8V
27832  *  0b00000..1.5V
27833  */
27834 #define DCDC_CTRL1_VDD1P8CTRL_TRG(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)
27835 
27836 #define DCDC_CTRL1_VDD1P0CTRL_TRG_MASK           (0x1F00U)
27837 #define DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT          (8U)
27838 /*! VDD1P0CTRL_TRG
27839  *  0b11111..1.375V
27840  *  0b10000..1.0V
27841  *  0b00000..0.6V
27842  */
27843 #define DCDC_CTRL1_VDD1P0CTRL_TRG(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)
27844 
27845 #define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK      (0x1F0000U)
27846 #define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT     (16U)
27847 /*! VDD1P8CTRL_STBY_TRG
27848  *  0b11111..2.3V
27849  *  0b01011..1.8V
27850  *  0b00000..1.525V
27851  */
27852 #define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(x)        (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK)
27853 
27854 #define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK      (0x1F000000U)
27855 #define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT     (24U)
27856 /*! VDD1P0CTRL_STBY_TRG
27857  *  0b11111..1.4V
27858  *  0b01111..1.0V
27859  *  0b00000..0.625V
27860  */
27861 #define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(x)        (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)
27862 /*! @} */
27863 
27864 /*! @name REG0 - DCDC Register 0 */
27865 /*! @{ */
27866 
27867 #define DCDC_REG0_PWD_ZCD_MASK                   (0x1U)
27868 #define DCDC_REG0_PWD_ZCD_SHIFT                  (0U)
27869 /*! PWD_ZCD - Power Down Zero Cross Detection
27870  *  0b0..Zero cross detetion function powered up
27871  *  0b1..Zero cross detetion function powered down
27872  */
27873 #define DCDC_REG0_PWD_ZCD(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
27874 
27875 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK   (0x2U)
27876 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT  (1U)
27877 /*! DISABLE_AUTO_CLK_SWITCH - Disable Auto Clock Switch
27878  *  0b0..If DISABLE_AUTO_CLK_SWITCH is set to 0 and 24M xtal is OK, the clock source will switch from internal
27879  *       ring oscillator to 24M xtal automatically
27880  *  0b1..If DISABLE_AUTO_CLK_SWITCH is set to 1, SEL_CLK will determine which clock source the DCDC uses
27881  */
27882 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
27883 
27884 #define DCDC_REG0_SEL_CLK_MASK                   (0x4U)
27885 #define DCDC_REG0_SEL_CLK_SHIFT                  (2U)
27886 /*! SEL_CLK - Select Clock
27887  *  0b0..DCDC uses internal ring oscillator
27888  *  0b1..DCDC uses 24M xtal
27889  */
27890 #define DCDC_REG0_SEL_CLK(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
27891 
27892 #define DCDC_REG0_PWD_OSC_INT_MASK               (0x8U)
27893 #define DCDC_REG0_PWD_OSC_INT_SHIFT              (3U)
27894 /*! PWD_OSC_INT - Power down internal ring oscillator
27895  *  0b0..Internal ring oscillator powered up
27896  *  0b1..Internal ring oscillator powered down
27897  */
27898 #define DCDC_REG0_PWD_OSC_INT(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
27899 
27900 #define DCDC_REG0_PWD_CUR_SNS_CMP_MASK           (0x10U)
27901 #define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT          (4U)
27902 /*! PWD_CUR_SNS_CMP - Power down signal of the current detector
27903  *  0b0..Current Detector powered up
27904  *  0b1..Current Detector powered down
27905  */
27906 #define DCDC_REG0_PWD_CUR_SNS_CMP(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
27907 
27908 #define DCDC_REG0_CUR_SNS_THRSH_MASK             (0xE0U)
27909 #define DCDC_REG0_CUR_SNS_THRSH_SHIFT            (5U)
27910 /*! CUR_SNS_THRSH - Current Sense (detector) Threshold */
27911 #define DCDC_REG0_CUR_SNS_THRSH(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
27912 
27913 #define DCDC_REG0_PWD_OVERCUR_DET_MASK           (0x100U)
27914 #define DCDC_REG0_PWD_OVERCUR_DET_SHIFT          (8U)
27915 /*! PWD_OVERCUR_DET - Power down overcurrent detection comparator
27916  *  0b0..Overcurrent detection comparator is enabled
27917  *  0b1..Overcurrent detection comparator is disabled
27918  */
27919 #define DCDC_REG0_PWD_OVERCUR_DET(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
27920 
27921 #define DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK       (0x800U)
27922 #define DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT      (11U)
27923 /*! PWD_CMP_DCDC_IN_DET
27924  *  0b0..Low voltage detection comparator is enabled
27925  *  0b1..Low voltage detection comparator is disabled
27926  */
27927 #define DCDC_REG0_PWD_CMP_DCDC_IN_DET(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT)) & DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK)
27928 
27929 #define DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK       (0x10000U)
27930 #define DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT      (16U)
27931 /*! PWD_HIGH_VDD1P8_DET - Power Down High Voltage Detection for VDD1P8
27932  *  0b0..Overvoltage detection comparator for the VDD1P8 output is enabled
27933  *  0b1..Overvoltage detection comparator for the VDD1P8 output is disabled
27934  */
27935 #define DCDC_REG0_PWD_HIGH_VDD1P8_DET(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK)
27936 
27937 #define DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK       (0x20000U)
27938 #define DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT      (17U)
27939 /*! PWD_HIGH_VDD1P0_DET - Power Down High Voltage Detection for VDD1P0
27940  *  0b0..Overvoltage detection comparator for the VDD1P0 output is enabled
27941  *  0b1..Overvoltage detection comparator for the VDD1P0 output is disabled
27942  */
27943 #define DCDC_REG0_PWD_HIGH_VDD1P0_DET(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK)
27944 
27945 #define DCDC_REG0_LP_HIGH_HYS_MASK               (0x200000U)
27946 #define DCDC_REG0_LP_HIGH_HYS_SHIFT              (21U)
27947 /*! LP_HIGH_HYS - Low Power High Hysteric Value
27948  *  0b0..Adjust hysteretic value in low power to 12.5mV
27949  *  0b1..Adjust hysteretic value in low power to 25mV
27950  */
27951 #define DCDC_REG0_LP_HIGH_HYS(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
27952 
27953 #define DCDC_REG0_PWD_CMP_OFFSET_MASK            (0x4000000U)
27954 #define DCDC_REG0_PWD_CMP_OFFSET_SHIFT           (26U)
27955 /*! PWD_CMP_OFFSET - power down the out-of-range detection comparator
27956  *  0b0..Out-of-range comparator powered up
27957  *  0b1..Out-of-range comparator powered down
27958  */
27959 #define DCDC_REG0_PWD_CMP_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
27960 
27961 #define DCDC_REG0_XTALOK_DISABLE_MASK            (0x8000000U)
27962 #define DCDC_REG0_XTALOK_DISABLE_SHIFT           (27U)
27963 /*! XTALOK_DISABLE - Disable xtalok detection circuit
27964  *  0b0..Enable xtalok detection circuit
27965  *  0b1..Disable xtalok detection circuit and always outputs OK signal "1"
27966  */
27967 #define DCDC_REG0_XTALOK_DISABLE(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
27968 
27969 #define DCDC_REG0_XTAL_24M_OK_MASK               (0x20000000U)
27970 #define DCDC_REG0_XTAL_24M_OK_SHIFT              (29U)
27971 /*! XTAL_24M_OK - 24M XTAL OK
27972  *  0b0..DCDC uses internal ring oscillator
27973  *  0b1..DCDC uses xtal 24M
27974  */
27975 #define DCDC_REG0_XTAL_24M_OK(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
27976 
27977 #define DCDC_REG0_STS_DC_OK_MASK                 (0x80000000U)
27978 #define DCDC_REG0_STS_DC_OK_SHIFT                (31U)
27979 /*! STS_DC_OK - DCDC Output OK
27980  *  0b0..DCDC is settling
27981  *  0b1..DCDC already settled
27982  */
27983 #define DCDC_REG0_STS_DC_OK(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
27984 /*! @} */
27985 
27986 /*! @name REG1 - DCDC Register 1 */
27987 /*! @{ */
27988 
27989 #define DCDC_REG1_DM_CTRL_MASK                   (0x8U)
27990 #define DCDC_REG1_DM_CTRL_SHIFT                  (3U)
27991 /*! DM_CTRL - DM Control
27992  *  0b0..No change to ripple when the discontinuous current is present in DCM.
27993  *  0b1..Improves ripple when the inductor current goes to zero in DCM.
27994  */
27995 #define DCDC_REG1_DM_CTRL(x)                     (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DM_CTRL_SHIFT)) & DCDC_REG1_DM_CTRL_MASK)
27996 
27997 #define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK         (0x10U)
27998 #define DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT        (4U)
27999 /*! RLOAD_REG_EN_LPSR - Load Resistor Enable
28000  *  0b0..Disconnect load resistor
28001  *  0b1..Connect load resistor
28002  */
28003 #define DCDC_REG1_RLOAD_REG_EN_LPSR(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
28004 
28005 #define DCDC_REG1_VBG_TRIM_MASK                  (0x7C0U)
28006 #define DCDC_REG1_VBG_TRIM_SHIFT                 (6U)
28007 /*! VBG_TRIM - Trim Bandgap Voltage
28008  *  0b00000..0.452V
28009  *  0b10000..0.5V
28010  *  0b11111..0.545V
28011  */
28012 #define DCDC_REG1_VBG_TRIM(x)                    (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
28013 
28014 #define DCDC_REG1_LP_CMP_ISRC_SEL_MASK           (0x1800U)
28015 #define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT          (11U)
28016 /*! LP_CMP_ISRC_SEL - Low Power Comparator Current Bias
28017  *  0b00..50nA
28018  *  0b01..100nA
28019  *  0b10..200nA
28020  *  0b11..400nA
28021  */
28022 #define DCDC_REG1_LP_CMP_ISRC_SEL(x)             (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
28023 
28024 #define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK    (0x8000000U)
28025 #define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT   (27U)
28026 /*! LOOPCTRL_CM_HST_THRESH - Increase Threshold Detection */
28027 #define DCDC_REG1_LOOPCTRL_CM_HST_THRESH(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK)
28028 
28029 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK    (0x10000000U)
28030 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT   (28U)
28031 /*! LOOPCTRL_DF_HST_THRESH - Increase Threshold Detection */
28032 #define DCDC_REG1_LOOPCTRL_DF_HST_THRESH(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
28033 
28034 #define DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK       (0x20000000U)
28035 #define DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT      (29U)
28036 /*! LOOPCTRL_EN_CM_HYST
28037  *  0b0..Disable hysteresis in switching converter common mode analog comparators
28038  *  0b1..Enable hysteresis in switching converter common mode analog comparators
28039  */
28040 #define DCDC_REG1_LOOPCTRL_EN_CM_HYST(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK)
28041 
28042 #define DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK       (0x40000000U)
28043 #define DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT      (30U)
28044 /*! LOOPCTRL_EN_DF_HYST
28045  *  0b0..Disable hysteresis in switching converter differential mode analog comparators
28046  *  0b1..Enable hysteresis in switching converter differential mode analog comparators
28047  */
28048 #define DCDC_REG1_LOOPCTRL_EN_DF_HYST(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK)
28049 /*! @} */
28050 
28051 /*! @name REG2 - DCDC Register 2 */
28052 /*! @{ */
28053 
28054 #define DCDC_REG2_LOOPCTRL_DC_C_MASK             (0x3U)
28055 #define DCDC_REG2_LOOPCTRL_DC_C_SHIFT            (0U)
28056 #define DCDC_REG2_LOOPCTRL_DC_C(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
28057 
28058 #define DCDC_REG2_LOOPCTRL_DC_R_MASK             (0x3CU)
28059 #define DCDC_REG2_LOOPCTRL_DC_R_SHIFT            (2U)
28060 #define DCDC_REG2_LOOPCTRL_DC_R(x)               (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
28061 
28062 #define DCDC_REG2_LOOPCTRL_DC_FF_MASK            (0x1C0U)
28063 #define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT           (6U)
28064 #define DCDC_REG2_LOOPCTRL_DC_FF(x)              (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
28065 
28066 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK       (0xE00U)
28067 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT      (9U)
28068 /*! LOOPCTRL_EN_RCSCALE - Enable RC Scale */
28069 #define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
28070 
28071 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK    (0x1000U)
28072 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT   (12U)
28073 #define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x)      (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
28074 
28075 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK        (0x2000U)
28076 #define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT       (13U)
28077 #define DCDC_REG2_LOOPCTRL_HYST_SIGN(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
28078 
28079 #define DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK     (0x8000U)
28080 #define DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT    (15U)
28081 #define DCDC_REG2_BATTMONITOR_EN_BATADJ(x)       (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK)
28082 
28083 #define DCDC_REG2_BATTMONITOR_BATT_VAL_MASK      (0x3FF0000U)
28084 #define DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT     (16U)
28085 #define DCDC_REG2_BATTMONITOR_BATT_VAL(x)        (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT)) & DCDC_REG2_BATTMONITOR_BATT_VAL_MASK)
28086 
28087 #define DCDC_REG2_DCM_SET_CTRL_MASK              (0x10000000U)
28088 #define DCDC_REG2_DCM_SET_CTRL_SHIFT             (28U)
28089 /*! DCM_SET_CTRL - DCM Set Control */
28090 #define DCDC_REG2_DCM_SET_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
28091 
28092 #define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK       (0x40000000U)
28093 #define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT      (30U)
28094 #define DCDC_REG2_LOOPCTRL_TOGGLE_DIF(x)         (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT)) & DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK)
28095 /*! @} */
28096 
28097 /*! @name REG3 - DCDC Register 3 */
28098 /*! @{ */
28099 
28100 #define DCDC_REG3_IN_BROWNOUT_MASK               (0x4000U)
28101 #define DCDC_REG3_IN_BROWNOUT_SHIFT              (14U)
28102 /*! IN_BROWNOUT
28103  *  0b1..DCDC_IN is lower than 2.6V
28104  */
28105 #define DCDC_REG3_IN_BROWNOUT(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_IN_BROWNOUT_SHIFT)) & DCDC_REG3_IN_BROWNOUT_MASK)
28106 
28107 #define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK   (0x8000U)
28108 #define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT  (15U)
28109 /*! OVERVOLT_VDD1P8_DET_OUT
28110  *  0b1..VDD1P8 Overvoltage
28111  */
28112 #define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK)
28113 
28114 #define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK   (0x10000U)
28115 #define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT  (16U)
28116 /*! OVERVOLT_VDD1P0_DET_OUT
28117  *  0b1..VDD1P0 Overvoltage
28118  */
28119 #define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK)
28120 
28121 #define DCDC_REG3_OVERCUR_DETECT_OUT_MASK        (0x20000U)
28122 #define DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT       (17U)
28123 /*! OVERCUR_DETECT_OUT
28124  *  0b1..Overcurrent
28125  */
28126 #define DCDC_REG3_OVERCUR_DETECT_OUT(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT)) & DCDC_REG3_OVERCUR_DETECT_OUT_MASK)
28127 
28128 #define DCDC_REG3_ENABLE_FF_MASK                 (0x40000U)
28129 #define DCDC_REG3_ENABLE_FF_SHIFT                (18U)
28130 /*! ENABLE_FF
28131  *  0b1..Enable feed-forward (FF) function that can speed up transient settling.
28132  */
28133 #define DCDC_REG3_ENABLE_FF(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_ENABLE_FF_SHIFT)) & DCDC_REG3_ENABLE_FF_MASK)
28134 
28135 #define DCDC_REG3_DISABLE_PULSE_SKIP_MASK        (0x80000U)
28136 #define DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT       (19U)
28137 /*! DISABLE_PULSE_SKIP - Disable Pulse Skip
28138  *  0b0..Stop charging if the duty cycle is lower than what is set by NEGLIMIT_IN
28139  */
28140 #define DCDC_REG3_DISABLE_PULSE_SKIP(x)          (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_PULSE_SKIP_MASK)
28141 
28142 #define DCDC_REG3_DISABLE_IDLE_SKIP_MASK         (0x100000U)
28143 #define DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT        (20U)
28144 /*! DISABLE_IDLE_SKIP
28145  *  0b0..Enable the idle skip function. The DCDC will be idle when out-of-range comparator detects the output
28146  *       voltage is higher than the target by 25mV. This function requires the out-of-range comparator to be enabled
28147  *       (PWD_CMP_OFFSET=0).
28148  */
28149 #define DCDC_REG3_DISABLE_IDLE_SKIP(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_IDLE_SKIP_MASK)
28150 
28151 #define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK  (0x200000U)
28152 #define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT (21U)
28153 /*! DOUBLE_IBIAS_CMP_LP_LPSR
28154  *  0b1..Double the bias current of the comparator for low-voltage detector in LP (low-power) mode
28155  */
28156 #define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR(x)    (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT)) & DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK)
28157 
28158 #define DCDC_REG3_REG_FBK_SEL_MASK               (0xC00000U)
28159 #define DCDC_REG3_REG_FBK_SEL_SHIFT              (22U)
28160 #define DCDC_REG3_REG_FBK_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_REG_FBK_SEL_SHIFT)) & DCDC_REG3_REG_FBK_SEL_MASK)
28161 
28162 #define DCDC_REG3_MINPWR_DC_HALFCLK_MASK         (0x1000000U)
28163 #define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT        (24U)
28164 /*! MINPWR_DC_HALFCLK
28165  *  0b0..DCDC clock remains at full frequency for continuous mode
28166  *  0b1..DCDC clock set to half frequency for continuous mode
28167  */
28168 #define DCDC_REG3_MINPWR_DC_HALFCLK(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
28169 
28170 #define DCDC_REG3_MINPWR_HALF_FETS_MASK          (0x4000000U)
28171 #define DCDC_REG3_MINPWR_HALF_FETS_SHIFT         (26U)
28172 #define DCDC_REG3_MINPWR_HALF_FETS(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_HALF_FETS_SHIFT)) & DCDC_REG3_MINPWR_HALF_FETS_MASK)
28173 
28174 #define DCDC_REG3_MISC_DELAY_TIMING_MASK         (0x8000000U)
28175 #define DCDC_REG3_MISC_DELAY_TIMING_SHIFT        (27U)
28176 /*! MISC_DELAY_TIMING - Miscellaneous Delay Timing */
28177 #define DCDC_REG3_MISC_DELAY_TIMING(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
28178 
28179 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK   (0x20000000U)
28180 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT  (29U)
28181 /*! VDD1P0CTRL_DISABLE_STEP - Disable Step for VDD1P0
28182  *  0b0..Enable stepping for VDD1P0
28183  *  0b1..Disable stepping for VDD1P0
28184  */
28185 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
28186 
28187 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK   (0x40000000U)
28188 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT  (30U)
28189 /*! VDD1P8CTRL_DISABLE_STEP - Disable Step for VDD1P8
28190  *  0b0..Enable stepping for VDD1P8
28191  *  0b1..Disable stepping for VDD1P8
28192  */
28193 #define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP(x)     (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK)
28194 /*! @} */
28195 
28196 /*! @name REG4 - DCDC Register 4 */
28197 /*! @{ */
28198 
28199 #define DCDC_REG4_ENABLE_SP_MASK                 (0xFFFFU)
28200 #define DCDC_REG4_ENABLE_SP_SHIFT                (0U)
28201 #define DCDC_REG4_ENABLE_SP(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_ENABLE_SP_SHIFT)) & DCDC_REG4_ENABLE_SP_MASK)
28202 /*! @} */
28203 
28204 /*! @name REG5 - DCDC Register 5 */
28205 /*! @{ */
28206 
28207 #define DCDC_REG5_DIG_EN_SP_MASK                 (0xFFFFU)
28208 #define DCDC_REG5_DIG_EN_SP_SHIFT                (0U)
28209 #define DCDC_REG5_DIG_EN_SP(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG5_DIG_EN_SP_SHIFT)) & DCDC_REG5_DIG_EN_SP_MASK)
28210 /*! @} */
28211 
28212 /*! @name REG6 - DCDC Register 6 */
28213 /*! @{ */
28214 
28215 #define DCDC_REG6_LP_MODE_SP_MASK                (0xFFFFU)
28216 #define DCDC_REG6_LP_MODE_SP_SHIFT               (0U)
28217 #define DCDC_REG6_LP_MODE_SP(x)                  (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_LP_MODE_SP_SHIFT)) & DCDC_REG6_LP_MODE_SP_MASK)
28218 /*! @} */
28219 
28220 /*! @name REG7 - DCDC Register 7 */
28221 /*! @{ */
28222 
28223 #define DCDC_REG7_STBY_EN_SP_MASK                (0xFFFFU)
28224 #define DCDC_REG7_STBY_EN_SP_SHIFT               (0U)
28225 #define DCDC_REG7_STBY_EN_SP(x)                  (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_STBY_EN_SP_SHIFT)) & DCDC_REG7_STBY_EN_SP_MASK)
28226 /*! @} */
28227 
28228 /*! @name REG7P - DCDC Register 7 plus */
28229 /*! @{ */
28230 
28231 #define DCDC_REG7P_STBY_LP_MODE_SP_MASK          (0xFFFFU)
28232 #define DCDC_REG7P_STBY_LP_MODE_SP_SHIFT         (0U)
28233 #define DCDC_REG7P_STBY_LP_MODE_SP(x)            (((uint32_t)(((uint32_t)(x)) << DCDC_REG7P_STBY_LP_MODE_SP_SHIFT)) & DCDC_REG7P_STBY_LP_MODE_SP_MASK)
28234 /*! @} */
28235 
28236 /*! @name REG8 - DCDC Register 8 */
28237 /*! @{ */
28238 
28239 #define DCDC_REG8_ANA_TRG_SP0_MASK               (0xFFFFFFFFU)
28240 #define DCDC_REG8_ANA_TRG_SP0_SHIFT              (0U)
28241 #define DCDC_REG8_ANA_TRG_SP0(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG8_ANA_TRG_SP0_SHIFT)) & DCDC_REG8_ANA_TRG_SP0_MASK)
28242 /*! @} */
28243 
28244 /*! @name REG9 - DCDC Register 9 */
28245 /*! @{ */
28246 
28247 #define DCDC_REG9_ANA_TRG_SP1_MASK               (0xFFFFFFFFU)
28248 #define DCDC_REG9_ANA_TRG_SP1_SHIFT              (0U)
28249 #define DCDC_REG9_ANA_TRG_SP1(x)                 (((uint32_t)(((uint32_t)(x)) << DCDC_REG9_ANA_TRG_SP1_SHIFT)) & DCDC_REG9_ANA_TRG_SP1_MASK)
28250 /*! @} */
28251 
28252 /*! @name REG10 - DCDC Register 10 */
28253 /*! @{ */
28254 
28255 #define DCDC_REG10_ANA_TRG_SP2_MASK              (0xFFFFFFFFU)
28256 #define DCDC_REG10_ANA_TRG_SP2_SHIFT             (0U)
28257 #define DCDC_REG10_ANA_TRG_SP2(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG10_ANA_TRG_SP2_SHIFT)) & DCDC_REG10_ANA_TRG_SP2_MASK)
28258 /*! @} */
28259 
28260 /*! @name REG11 - DCDC Register 11 */
28261 /*! @{ */
28262 
28263 #define DCDC_REG11_ANA_TRG_SP3_MASK              (0xFFFFFFFFU)
28264 #define DCDC_REG11_ANA_TRG_SP3_SHIFT             (0U)
28265 #define DCDC_REG11_ANA_TRG_SP3(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG11_ANA_TRG_SP3_SHIFT)) & DCDC_REG11_ANA_TRG_SP3_MASK)
28266 /*! @} */
28267 
28268 /*! @name REG12 - DCDC Register 12 */
28269 /*! @{ */
28270 
28271 #define DCDC_REG12_DIG_TRG_SP0_MASK              (0xFFFFFFFFU)
28272 #define DCDC_REG12_DIG_TRG_SP0_SHIFT             (0U)
28273 #define DCDC_REG12_DIG_TRG_SP0(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG12_DIG_TRG_SP0_SHIFT)) & DCDC_REG12_DIG_TRG_SP0_MASK)
28274 /*! @} */
28275 
28276 /*! @name REG13 - DCDC Register 13 */
28277 /*! @{ */
28278 
28279 #define DCDC_REG13_DIG_TRG_SP1_MASK              (0xFFFFFFFFU)
28280 #define DCDC_REG13_DIG_TRG_SP1_SHIFT             (0U)
28281 #define DCDC_REG13_DIG_TRG_SP1(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG13_DIG_TRG_SP1_SHIFT)) & DCDC_REG13_DIG_TRG_SP1_MASK)
28282 /*! @} */
28283 
28284 /*! @name REG14 - DCDC Register 14 */
28285 /*! @{ */
28286 
28287 #define DCDC_REG14_DIG_TRG_SP2_MASK              (0xFFFFFFFFU)
28288 #define DCDC_REG14_DIG_TRG_SP2_SHIFT             (0U)
28289 #define DCDC_REG14_DIG_TRG_SP2(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG14_DIG_TRG_SP2_SHIFT)) & DCDC_REG14_DIG_TRG_SP2_MASK)
28290 /*! @} */
28291 
28292 /*! @name REG15 - DCDC Register 15 */
28293 /*! @{ */
28294 
28295 #define DCDC_REG15_DIG_TRG_SP3_MASK              (0xFFFFFFFFU)
28296 #define DCDC_REG15_DIG_TRG_SP3_SHIFT             (0U)
28297 #define DCDC_REG15_DIG_TRG_SP3(x)                (((uint32_t)(((uint32_t)(x)) << DCDC_REG15_DIG_TRG_SP3_SHIFT)) & DCDC_REG15_DIG_TRG_SP3_MASK)
28298 /*! @} */
28299 
28300 /*! @name REG16 - DCDC Register 16 */
28301 /*! @{ */
28302 
28303 #define DCDC_REG16_ANA_STBY_TRG_SP0_MASK         (0xFFFFFFFFU)
28304 #define DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT        (0U)
28305 #define DCDC_REG16_ANA_STBY_TRG_SP0(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT)) & DCDC_REG16_ANA_STBY_TRG_SP0_MASK)
28306 /*! @} */
28307 
28308 /*! @name REG17 - DCDC Register 17 */
28309 /*! @{ */
28310 
28311 #define DCDC_REG17_ANA_STBY_TRG_SP1_MASK         (0xFFFFFFFFU)
28312 #define DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT        (0U)
28313 #define DCDC_REG17_ANA_STBY_TRG_SP1(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
28314 /*! @} */
28315 
28316 /*! @name REG18 - DCDC Register 18 */
28317 /*! @{ */
28318 
28319 #define DCDC_REG18_ANA_STBY_TRG_SP2_MASK         (0xFFFFFFFFU)
28320 #define DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT        (0U)
28321 #define DCDC_REG18_ANA_STBY_TRG_SP2(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
28322 /*! @} */
28323 
28324 /*! @name REG19 - DCDC Register 19 */
28325 /*! @{ */
28326 
28327 #define DCDC_REG19_ANA_STBY_TRG_SP3_MASK         (0xFFFFFFFFU)
28328 #define DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT        (0U)
28329 #define DCDC_REG19_ANA_STBY_TRG_SP3(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
28330 /*! @} */
28331 
28332 /*! @name REG20 - DCDC Register 20 */
28333 /*! @{ */
28334 
28335 #define DCDC_REG20_DIG_STBY_TRG_SP0_MASK         (0xFFFFFFFFU)
28336 #define DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT        (0U)
28337 #define DCDC_REG20_DIG_STBY_TRG_SP0(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT)) & DCDC_REG20_DIG_STBY_TRG_SP0_MASK)
28338 /*! @} */
28339 
28340 /*! @name REG21 - DCDC Register 21 */
28341 /*! @{ */
28342 
28343 #define DCDC_REG21_DIG_STBY_TRG_SP1_MASK         (0xFFFFFFFFU)
28344 #define DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT        (0U)
28345 #define DCDC_REG21_DIG_STBY_TRG_SP1(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT)) & DCDC_REG21_DIG_STBY_TRG_SP1_MASK)
28346 /*! @} */
28347 
28348 /*! @name REG22 - DCDC Register 22 */
28349 /*! @{ */
28350 
28351 #define DCDC_REG22_DIG_STBY_TRG_SP2_MASK         (0xFFFFFFFFU)
28352 #define DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT        (0U)
28353 #define DCDC_REG22_DIG_STBY_TRG_SP2(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT)) & DCDC_REG22_DIG_STBY_TRG_SP2_MASK)
28354 /*! @} */
28355 
28356 /*! @name REG23 - DCDC Register 23 */
28357 /*! @{ */
28358 
28359 #define DCDC_REG23_DIG_STBY_TRG_SP3_MASK         (0xFFFFFFFFU)
28360 #define DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT        (0U)
28361 #define DCDC_REG23_DIG_STBY_TRG_SP3(x)           (((uint32_t)(((uint32_t)(x)) << DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT)) & DCDC_REG23_DIG_STBY_TRG_SP3_MASK)
28362 /*! @} */
28363 
28364 /*! @name REG24 - DCDC Register 24 */
28365 /*! @{ */
28366 
28367 #define DCDC_REG24_OK_COUNT_MASK                 (0xFFFFFFFFU)
28368 #define DCDC_REG24_OK_COUNT_SHIFT                (0U)
28369 #define DCDC_REG24_OK_COUNT(x)                   (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)
28370 /*! @} */
28371 
28372 
28373 /*!
28374  * @}
28375  */ /* end of group DCDC_Register_Masks */
28376 
28377 
28378 /* DCDC - Peripheral instance base addresses */
28379 /** Peripheral DCDC base address */
28380 #define DCDC_BASE                                (0x40CA8000u)
28381 /** Peripheral DCDC base pointer */
28382 #define DCDC                                     ((DCDC_Type *)DCDC_BASE)
28383 /** Array initializer of DCDC peripheral base addresses */
28384 #define DCDC_BASE_ADDRS                          { DCDC_BASE }
28385 /** Array initializer of DCDC peripheral base pointers */
28386 #define DCDC_BASE_PTRS                           { DCDC }
28387 
28388 /*!
28389  * @}
28390  */ /* end of group DCDC_Peripheral_Access_Layer */
28391 
28392 
28393 /* ----------------------------------------------------------------------------
28394    -- DCIC Peripheral Access Layer
28395    ---------------------------------------------------------------------------- */
28396 
28397 /*!
28398  * @addtogroup DCIC_Peripheral_Access_Layer DCIC Peripheral Access Layer
28399  * @{
28400  */
28401 
28402 /** DCIC - Register Layout Typedef */
28403 typedef struct {
28404   __IO uint32_t DCICC;                             /**< DCIC Control Register, offset: 0x0 */
28405   __IO uint32_t DCICIC;                            /**< DCIC Interrupt Control Register, offset: 0x4 */
28406   __IO uint32_t DCICS;                             /**< DCIC Status Register, offset: 0x8 */
28407        uint8_t RESERVED_0[4];
28408   struct {                                         /* offset: 0x10, array step: 0x10 */
28409     __IO uint32_t DCICRC;                            /**< DCIC ROI Config Register, array offset: 0x10, array step: 0x10 */
28410     __IO uint32_t DCICRS;                            /**< DCIC ROI Size Register, array offset: 0x14, array step: 0x10 */
28411     __IO uint32_t DCICRRS;                           /**< DCIC ROI Reference Signature Register, array offset: 0x18, array step: 0x10 */
28412     __I  uint32_t DCICRCS;                           /**< DCIC ROI Calculated Signature Register, array offset: 0x1C, array step: 0x10 */
28413   } REGION[16];
28414 } DCIC_Type;
28415 
28416 /* ----------------------------------------------------------------------------
28417    -- DCIC Register Masks
28418    ---------------------------------------------------------------------------- */
28419 
28420 /*!
28421  * @addtogroup DCIC_Register_Masks DCIC Register Masks
28422  * @{
28423  */
28424 
28425 /*! @name DCICC - DCIC Control Register */
28426 /*! @{ */
28427 
28428 #define DCIC_DCICC_IC_EN_MASK                    (0x1U)
28429 #define DCIC_DCICC_IC_EN_SHIFT                   (0U)
28430 /*! IC_EN
28431  *  0b0..Disabled
28432  *  0b1..Enabled
28433  */
28434 #define DCIC_DCICC_IC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_IC_EN_SHIFT)) & DCIC_DCICC_IC_EN_MASK)
28435 
28436 #define DCIC_DCICC_DE_POL_MASK                   (0x10U)
28437 #define DCIC_DCICC_DE_POL_SHIFT                  (4U)
28438 /*! DE_POL
28439  *  0b0..Active High.
28440  *  0b1..Active Low.
28441  */
28442 #define DCIC_DCICC_DE_POL(x)                     (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_DE_POL_SHIFT)) & DCIC_DCICC_DE_POL_MASK)
28443 
28444 #define DCIC_DCICC_HSYNC_POL_MASK                (0x20U)
28445 #define DCIC_DCICC_HSYNC_POL_SHIFT               (5U)
28446 /*! HSYNC_POL
28447  *  0b0..Active High.
28448  *  0b1..Active Low.
28449  */
28450 #define DCIC_DCICC_HSYNC_POL(x)                  (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_HSYNC_POL_SHIFT)) & DCIC_DCICC_HSYNC_POL_MASK)
28451 
28452 #define DCIC_DCICC_VSYNC_POL_MASK                (0x40U)
28453 #define DCIC_DCICC_VSYNC_POL_SHIFT               (6U)
28454 /*! VSYNC_POL
28455  *  0b0..Active High.
28456  *  0b1..Active Low.
28457  */
28458 #define DCIC_DCICC_VSYNC_POL(x)                  (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_VSYNC_POL_SHIFT)) & DCIC_DCICC_VSYNC_POL_MASK)
28459 
28460 #define DCIC_DCICC_CLK_POL_MASK                  (0x80U)
28461 #define DCIC_DCICC_CLK_POL_SHIFT                 (7U)
28462 /*! CLK_POL
28463  *  0b0..Not inverted (default).
28464  *  0b1..Inverted.
28465  */
28466 #define DCIC_DCICC_CLK_POL(x)                    (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_CLK_POL_SHIFT)) & DCIC_DCICC_CLK_POL_MASK)
28467 /*! @} */
28468 
28469 /*! @name DCICIC - DCIC Interrupt Control Register */
28470 /*! @{ */
28471 
28472 #define DCIC_DCICIC_EI_MASK_MASK                 (0x1U)
28473 #define DCIC_DCICIC_EI_MASK_SHIFT                (0U)
28474 /*! EI_MASK
28475  *  0b0..Mask disabled - Interrupt assertion enabled
28476  *  0b1..Mask enabled - Interrupt assertion disabled
28477  */
28478 #define DCIC_DCICIC_EI_MASK(x)                   (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_EI_MASK_SHIFT)) & DCIC_DCICIC_EI_MASK_MASK)
28479 
28480 #define DCIC_DCICIC_FI_MASK_MASK                 (0x2U)
28481 #define DCIC_DCICIC_FI_MASK_SHIFT                (1U)
28482 /*! FI_MASK
28483  *  0b0..Mask disabled - Interrupt assertion enabled
28484  *  0b1..Mask enabled - Interrupt assertion disabled
28485  */
28486 #define DCIC_DCICIC_FI_MASK(x)                   (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_FI_MASK_SHIFT)) & DCIC_DCICIC_FI_MASK_MASK)
28487 
28488 #define DCIC_DCICIC_FREEZE_MASK_MASK             (0x8U)
28489 #define DCIC_DCICIC_FREEZE_MASK_SHIFT            (3U)
28490 /*! FREEZE_MASK
28491  *  0b0..Masks change allowed
28492  *  0b1..Masks are frozen
28493  */
28494 #define DCIC_DCICIC_FREEZE_MASK(x)               (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_FREEZE_MASK_SHIFT)) & DCIC_DCICIC_FREEZE_MASK_MASK)
28495 
28496 #define DCIC_DCICIC_EXT_SIG_EN_MASK              (0x10000U)
28497 #define DCIC_DCICIC_EXT_SIG_EN_SHIFT             (16U)
28498 /*! EXT_SIG_EN
28499  *  0b0..Disabled
28500  *  0b1..Enabled
28501  */
28502 #define DCIC_DCICIC_EXT_SIG_EN(x)                (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_EXT_SIG_EN_SHIFT)) & DCIC_DCICIC_EXT_SIG_EN_MASK)
28503 /*! @} */
28504 
28505 /*! @name DCICS - DCIC Status Register */
28506 /*! @{ */
28507 
28508 #define DCIC_DCICS_ROI_MATCH_STAT_MASK           (0xFFFFU)
28509 #define DCIC_DCICS_ROI_MATCH_STAT_SHIFT          (0U)
28510 /*! ROI_MATCH_STAT
28511  *  0b0000000000000000..ROI calculated CRC matches expected signature
28512  *  0b0000000000000001..Mismatch at ROI calculated CRC
28513  */
28514 #define DCIC_DCICS_ROI_MATCH_STAT(x)             (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_ROI_MATCH_STAT_SHIFT)) & DCIC_DCICS_ROI_MATCH_STAT_MASK)
28515 
28516 #define DCIC_DCICS_EI_STAT_MASK                  (0x10000U)
28517 #define DCIC_DCICS_EI_STAT_SHIFT                 (16U)
28518 /*! EI_STAT
28519  *  0b0..No pending Interrupt
28520  *  0b1..Pending Interrupt
28521  */
28522 #define DCIC_DCICS_EI_STAT(x)                    (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_EI_STAT_SHIFT)) & DCIC_DCICS_EI_STAT_MASK)
28523 
28524 #define DCIC_DCICS_FI_STAT_MASK                  (0x20000U)
28525 #define DCIC_DCICS_FI_STAT_SHIFT                 (17U)
28526 /*! FI_STAT
28527  *  0b0..No pending Interrupt
28528  *  0b1..Pending Interrupt
28529  */
28530 #define DCIC_DCICS_FI_STAT(x)                    (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_FI_STAT_SHIFT)) & DCIC_DCICS_FI_STAT_MASK)
28531 /*! @} */
28532 
28533 /*! @name DCICRC - DCIC ROI Config Register */
28534 /*! @{ */
28535 
28536 #define DCIC_DCICRC_START_OFFSET_X_MASK          (0x1FFFU)
28537 #define DCIC_DCICRC_START_OFFSET_X_SHIFT         (0U)
28538 #define DCIC_DCICRC_START_OFFSET_X(x)            (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_START_OFFSET_X_SHIFT)) & DCIC_DCICRC_START_OFFSET_X_MASK)
28539 
28540 #define DCIC_DCICRC_START_OFFSET_Y_MASK          (0xFFF0000U)
28541 #define DCIC_DCICRC_START_OFFSET_Y_SHIFT         (16U)
28542 #define DCIC_DCICRC_START_OFFSET_Y(x)            (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_START_OFFSET_Y_SHIFT)) & DCIC_DCICRC_START_OFFSET_Y_MASK)
28543 
28544 #define DCIC_DCICRC_ROI_FREEZE_MASK              (0x40000000U)
28545 #define DCIC_DCICRC_ROI_FREEZE_SHIFT             (30U)
28546 /*! ROI_FREEZE
28547  *  0b0..ROI configuration can be changed
28548  *  0b1..ROI configuration is frozen
28549  */
28550 #define DCIC_DCICRC_ROI_FREEZE(x)                (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_ROI_FREEZE_SHIFT)) & DCIC_DCICRC_ROI_FREEZE_MASK)
28551 
28552 #define DCIC_DCICRC_ROI_EN_MASK                  (0x80000000U)
28553 #define DCIC_DCICRC_ROI_EN_SHIFT                 (31U)
28554 /*! ROI_EN
28555  *  0b0..Disabled
28556  *  0b1..Enabled
28557  */
28558 #define DCIC_DCICRC_ROI_EN(x)                    (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_ROI_EN_SHIFT)) & DCIC_DCICRC_ROI_EN_MASK)
28559 /*! @} */
28560 
28561 /* The count of DCIC_DCICRC */
28562 #define DCIC_DCICRC_COUNT                        (16U)
28563 
28564 /*! @name DCICRS - DCIC ROI Size Register */
28565 /*! @{ */
28566 
28567 #define DCIC_DCICRS_END_OFFSET_X_MASK            (0x1FFFU)
28568 #define DCIC_DCICRS_END_OFFSET_X_SHIFT           (0U)
28569 #define DCIC_DCICRS_END_OFFSET_X(x)              (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRS_END_OFFSET_X_SHIFT)) & DCIC_DCICRS_END_OFFSET_X_MASK)
28570 
28571 #define DCIC_DCICRS_END_OFFSET_Y_MASK            (0xFFF0000U)
28572 #define DCIC_DCICRS_END_OFFSET_Y_SHIFT           (16U)
28573 #define DCIC_DCICRS_END_OFFSET_Y(x)              (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRS_END_OFFSET_Y_SHIFT)) & DCIC_DCICRS_END_OFFSET_Y_MASK)
28574 /*! @} */
28575 
28576 /* The count of DCIC_DCICRS */
28577 #define DCIC_DCICRS_COUNT                        (16U)
28578 
28579 /*! @name DCICRRS - DCIC ROI Reference Signature Register */
28580 /*! @{ */
28581 
28582 #define DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK    (0xFFFFFFFFU)
28583 #define DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT   (0U)
28584 #define DCIC_DCICRRS_REFERENCE_SIGNATURE(x)      (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT)) & DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK)
28585 /*! @} */
28586 
28587 /* The count of DCIC_DCICRRS */
28588 #define DCIC_DCICRRS_COUNT                       (16U)
28589 
28590 /*! @name DCICRCS - DCIC ROI Calculated Signature Register */
28591 /*! @{ */
28592 
28593 #define DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK   (0xFFFFFFFFU)
28594 #define DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT  (0U)
28595 #define DCIC_DCICRCS_CALCULATED_SIGNATURE(x)     (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT)) & DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK)
28596 /*! @} */
28597 
28598 /* The count of DCIC_DCICRCS */
28599 #define DCIC_DCICRCS_COUNT                       (16U)
28600 
28601 
28602 /*!
28603  * @}
28604  */ /* end of group DCIC_Register_Masks */
28605 
28606 
28607 /* DCIC - Peripheral instance base addresses */
28608 /** Peripheral DCIC1 base address */
28609 #define DCIC1_BASE                               (0x40819000u)
28610 /** Peripheral DCIC1 base pointer */
28611 #define DCIC1                                    ((DCIC_Type *)DCIC1_BASE)
28612 /** Peripheral DCIC2 base address */
28613 #define DCIC2_BASE                               (0x4081A000u)
28614 /** Peripheral DCIC2 base pointer */
28615 #define DCIC2                                    ((DCIC_Type *)DCIC2_BASE)
28616 /** Array initializer of DCIC peripheral base addresses */
28617 #define DCIC_BASE_ADDRS                          { 0u, DCIC1_BASE, DCIC2_BASE }
28618 /** Array initializer of DCIC peripheral base pointers */
28619 #define DCIC_BASE_PTRS                           { (DCIC_Type *)0u, DCIC1, DCIC2 }
28620 
28621 /*!
28622  * @}
28623  */ /* end of group DCIC_Peripheral_Access_Layer */
28624 
28625 
28626 /* ----------------------------------------------------------------------------
28627    -- DMA Peripheral Access Layer
28628    ---------------------------------------------------------------------------- */
28629 
28630 /*!
28631  * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
28632  * @{
28633  */
28634 
28635 /** DMA - Register Layout Typedef */
28636 typedef struct {
28637   __IO uint32_t CR;                                /**< Control, offset: 0x0 */
28638   __I  uint32_t ES;                                /**< Error Status, offset: 0x4 */
28639        uint8_t RESERVED_0[4];
28640   __IO uint32_t ERQ;                               /**< Enable Request, offset: 0xC */
28641        uint8_t RESERVED_1[4];
28642   __IO uint32_t EEI;                               /**< Enable Error Interrupt, offset: 0x14 */
28643   __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt, offset: 0x18 */
28644   __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt, offset: 0x19 */
28645   __O  uint8_t CERQ;                               /**< Clear Enable Request, offset: 0x1A */
28646   __O  uint8_t SERQ;                               /**< Set Enable Request, offset: 0x1B */
28647   __O  uint8_t CDNE;                               /**< Clear DONE Status Bit, offset: 0x1C */
28648   __O  uint8_t SSRT;                               /**< Set START Bit, offset: 0x1D */
28649   __O  uint8_t CERR;                               /**< Clear Error, offset: 0x1E */
28650   __O  uint8_t CINT;                               /**< Clear Interrupt Request, offset: 0x1F */
28651        uint8_t RESERVED_2[4];
28652   __IO uint32_t INT;                               /**< Interrupt Request, offset: 0x24 */
28653        uint8_t RESERVED_3[4];
28654   __IO uint32_t ERR;                               /**< Error, offset: 0x2C */
28655        uint8_t RESERVED_4[4];
28656   __I  uint32_t HRS;                               /**< Hardware Request Status, offset: 0x34 */
28657        uint8_t RESERVED_5[12];
28658   __IO uint32_t EARS;                              /**< Enable Asynchronous Request in Stop, offset: 0x44 */
28659        uint8_t RESERVED_6[184];
28660   __IO uint8_t DCHPRI3;                            /**< Channel Priority, offset: 0x100 */
28661   __IO uint8_t DCHPRI2;                            /**< Channel Priority, offset: 0x101 */
28662   __IO uint8_t DCHPRI1;                            /**< Channel Priority, offset: 0x102 */
28663   __IO uint8_t DCHPRI0;                            /**< Channel Priority, offset: 0x103 */
28664   __IO uint8_t DCHPRI7;                            /**< Channel Priority, offset: 0x104 */
28665   __IO uint8_t DCHPRI6;                            /**< Channel Priority, offset: 0x105 */
28666   __IO uint8_t DCHPRI5;                            /**< Channel Priority, offset: 0x106 */
28667   __IO uint8_t DCHPRI4;                            /**< Channel Priority, offset: 0x107 */
28668   __IO uint8_t DCHPRI11;                           /**< Channel Priority, offset: 0x108 */
28669   __IO uint8_t DCHPRI10;                           /**< Channel Priority, offset: 0x109 */
28670   __IO uint8_t DCHPRI9;                            /**< Channel Priority, offset: 0x10A */
28671   __IO uint8_t DCHPRI8;                            /**< Channel Priority, offset: 0x10B */
28672   __IO uint8_t DCHPRI15;                           /**< Channel Priority, offset: 0x10C */
28673   __IO uint8_t DCHPRI14;                           /**< Channel Priority, offset: 0x10D */
28674   __IO uint8_t DCHPRI13;                           /**< Channel Priority, offset: 0x10E */
28675   __IO uint8_t DCHPRI12;                           /**< Channel Priority, offset: 0x10F */
28676   __IO uint8_t DCHPRI19;                           /**< Channel Priority, offset: 0x110 */
28677   __IO uint8_t DCHPRI18;                           /**< Channel Priority, offset: 0x111 */
28678   __IO uint8_t DCHPRI17;                           /**< Channel Priority, offset: 0x112 */
28679   __IO uint8_t DCHPRI16;                           /**< Channel Priority, offset: 0x113 */
28680   __IO uint8_t DCHPRI23;                           /**< Channel Priority, offset: 0x114 */
28681   __IO uint8_t DCHPRI22;                           /**< Channel Priority, offset: 0x115 */
28682   __IO uint8_t DCHPRI21;                           /**< Channel Priority, offset: 0x116 */
28683   __IO uint8_t DCHPRI20;                           /**< Channel Priority, offset: 0x117 */
28684   __IO uint8_t DCHPRI27;                           /**< Channel Priority, offset: 0x118 */
28685   __IO uint8_t DCHPRI26;                           /**< Channel Priority, offset: 0x119 */
28686   __IO uint8_t DCHPRI25;                           /**< Channel Priority, offset: 0x11A */
28687   __IO uint8_t DCHPRI24;                           /**< Channel Priority, offset: 0x11B */
28688   __IO uint8_t DCHPRI31;                           /**< Channel Priority, offset: 0x11C */
28689   __IO uint8_t DCHPRI30;                           /**< Channel Priority, offset: 0x11D */
28690   __IO uint8_t DCHPRI29;                           /**< Channel Priority, offset: 0x11E */
28691   __IO uint8_t DCHPRI28;                           /**< Channel Priority, offset: 0x11F */
28692        uint8_t RESERVED_7[3808];
28693   struct {                                         /* offset: 0x1000, array step: 0x20 */
28694     __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
28695     __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
28696     __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
28697     union {                                          /* offset: 0x1008, array step: 0x20 */
28698       __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
28699       __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
28700       __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
28701     };
28702     __IO int32_t SLAST;                              /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
28703     __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
28704     __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
28705     union {                                          /* offset: 0x1016, array step: 0x20 */
28706       __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
28707       __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
28708     };
28709     __IO int32_t DLAST_SGA;                          /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
28710     __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
28711     union {                                          /* offset: 0x101E, array step: 0x20 */
28712       __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
28713       __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
28714     };
28715   } TCD[32];
28716 } DMA_Type;
28717 
28718 /* ----------------------------------------------------------------------------
28719    -- DMA Register Masks
28720    ---------------------------------------------------------------------------- */
28721 
28722 /*!
28723  * @addtogroup DMA_Register_Masks DMA Register Masks
28724  * @{
28725  */
28726 
28727 /*! @name CR - Control */
28728 /*! @{ */
28729 
28730 #define DMA_CR_EDBG_MASK                         (0x2U)
28731 #define DMA_CR_EDBG_SHIFT                        (1U)
28732 /*! EDBG - Enable Debug
28733  *  0b0..When the chip is in Debug mode, the eDMA continues to operate.
28734  *  0b1..When the chip is in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete.
28735  */
28736 #define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
28737 
28738 #define DMA_CR_ERCA_MASK                         (0x4U)
28739 #define DMA_CR_ERCA_SHIFT                        (2U)
28740 /*! ERCA - Enable Round Robin Channel Arbitration
28741  *  0b0..Fixed priority arbitration within each group
28742  *  0b1..Round robin arbitration within each group
28743  */
28744 #define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
28745 
28746 #define DMA_CR_ERGA_MASK                         (0x8U)
28747 #define DMA_CR_ERGA_SHIFT                        (3U)
28748 /*! ERGA - Enable Round Robin Group Arbitration
28749  *  0b0..Fixed priority arbitration
28750  *  0b1..Round robin arbitration
28751  */
28752 #define DMA_CR_ERGA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
28753 
28754 #define DMA_CR_HOE_MASK                          (0x10U)
28755 #define DMA_CR_HOE_SHIFT                         (4U)
28756 /*! HOE - Halt On Error
28757  *  0b0..Normal operation
28758  *  0b1..Error causes HALT field to be automatically set to 1
28759  */
28760 #define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
28761 
28762 #define DMA_CR_HALT_MASK                         (0x20U)
28763 #define DMA_CR_HALT_SHIFT                        (5U)
28764 /*! HALT - Halt eDMA Operations
28765  *  0b0..Normal operation
28766  *  0b1..eDMA operations halted
28767  */
28768 #define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
28769 
28770 #define DMA_CR_CLM_MASK                          (0x40U)
28771 #define DMA_CR_CLM_SHIFT                         (6U)
28772 /*! CLM - Continuous Link Mode
28773  *  0b0..Continuous link mode is off
28774  *  0b1..Continuous link mode is on
28775  */
28776 #define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
28777 
28778 #define DMA_CR_EMLM_MASK                         (0x80U)
28779 #define DMA_CR_EMLM_SHIFT                        (7U)
28780 /*! EMLM - Enable Minor Loop Mapping
28781  *  0b0..Disabled
28782  *  0b1..Enabled
28783  */
28784 #define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
28785 
28786 #define DMA_CR_GRP0PRI_MASK                      (0x100U)
28787 #define DMA_CR_GRP0PRI_SHIFT                     (8U)
28788 /*! GRP0PRI - Channel Group 0 Priority */
28789 #define DMA_CR_GRP0PRI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
28790 
28791 #define DMA_CR_GRP1PRI_MASK                      (0x400U)
28792 #define DMA_CR_GRP1PRI_SHIFT                     (10U)
28793 /*! GRP1PRI - Channel Group 1 Priority */
28794 #define DMA_CR_GRP1PRI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
28795 
28796 #define DMA_CR_ECX_MASK                          (0x10000U)
28797 #define DMA_CR_ECX_SHIFT                         (16U)
28798 /*! ECX - Error Cancel Transfer
28799  *  0b0..Normal operation
28800  *  0b1..Cancel the remaining data transfer
28801  */
28802 #define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
28803 
28804 #define DMA_CR_CX_MASK                           (0x20000U)
28805 #define DMA_CR_CX_SHIFT                          (17U)
28806 /*! CX - Cancel Transfer
28807  *  0b0..Normal operation
28808  *  0b1..Cancel the remaining data transfer
28809  */
28810 #define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
28811 
28812 #define DMA_CR_VERSION_MASK                      (0x7F000000U)
28813 #define DMA_CR_VERSION_SHIFT                     (24U)
28814 /*! VERSION - eDMA version number */
28815 #define DMA_CR_VERSION(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_VERSION_SHIFT)) & DMA_CR_VERSION_MASK)
28816 
28817 #define DMA_CR_ACTIVE_MASK                       (0x80000000U)
28818 #define DMA_CR_ACTIVE_SHIFT                      (31U)
28819 /*! ACTIVE - eDMA Active Status
28820  *  0b0..eDMA is idle
28821  *  0b1..eDMA is executing a channel
28822  */
28823 #define DMA_CR_ACTIVE(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
28824 /*! @} */
28825 
28826 /*! @name ES - Error Status */
28827 /*! @{ */
28828 
28829 #define DMA_ES_DBE_MASK                          (0x1U)
28830 #define DMA_ES_DBE_SHIFT                         (0U)
28831 /*! DBE - Destination Bus Error
28832  *  0b0..No destination bus error.
28833  *  0b1..The most-recently recorded error was a bus error on a destination write.
28834  */
28835 #define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
28836 
28837 #define DMA_ES_SBE_MASK                          (0x2U)
28838 #define DMA_ES_SBE_SHIFT                         (1U)
28839 /*! SBE - Source Bus Error
28840  *  0b0..No source bus error.
28841  *  0b1..The most-recently recorded error was a bus error on a source read.
28842  */
28843 #define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
28844 
28845 #define DMA_ES_SGE_MASK                          (0x4U)
28846 #define DMA_ES_SGE_SHIFT                         (2U)
28847 /*! SGE - Scatter/Gather Configuration Error
28848  *  0b0..No scatter/gather configuration error.
28849  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_DLASTSGA field.
28850  */
28851 #define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
28852 
28853 #define DMA_ES_NCE_MASK                          (0x8U)
28854 #define DMA_ES_NCE_SHIFT                         (3U)
28855 /*! NCE - NBYTES/CITER Configuration Error
28856  *  0b0..No NBYTES/CITER configuration error.
28857  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER
28858  *       fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] = 0, or
28859  *       TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK].
28860  */
28861 #define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
28862 
28863 #define DMA_ES_DOE_MASK                          (0x10U)
28864 #define DMA_ES_DOE_SHIFT                         (4U)
28865 /*! DOE - Destination Offset Error
28866  *  0b0..No destination offset configuration error.
28867  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
28868  */
28869 #define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
28870 
28871 #define DMA_ES_DAE_MASK                          (0x20U)
28872 #define DMA_ES_DAE_SHIFT                         (5U)
28873 /*! DAE - Destination Address Error
28874  *  0b0..No destination address configuration error.
28875  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR
28876  *       is inconsistent with TCDn_ATTR[DSIZE].
28877  */
28878 #define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
28879 
28880 #define DMA_ES_SOE_MASK                          (0x40U)
28881 #define DMA_ES_SOE_SHIFT                         (6U)
28882 /*! SOE - Source Offset Error
28883  *  0b0..No source offset configuration error.
28884  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
28885  */
28886 #define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
28887 
28888 #define DMA_ES_SAE_MASK                          (0x80U)
28889 #define DMA_ES_SAE_SHIFT                         (7U)
28890 /*! SAE - Source Address Error
28891  *  0b0..No source address configuration error.
28892  *  0b1..The most-recently recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR
28893  *       is inconsistent with TCDn_ATTR[SSIZE].
28894  */
28895 #define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
28896 
28897 #define DMA_ES_ERRCHN_MASK                       (0x1F00U)
28898 #define DMA_ES_ERRCHN_SHIFT                      (8U)
28899 /*! ERRCHN - Error Channel Number or Canceled Channel Number */
28900 #define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
28901 
28902 #define DMA_ES_CPE_MASK                          (0x4000U)
28903 #define DMA_ES_CPE_SHIFT                         (14U)
28904 /*! CPE - Channel Priority Error
28905  *  0b0..No channel priority error.
28906  *  0b1..The most-recently recorded error was a configuration error in the channel priorities within a group.
28907  *       Channel priorities within a group are not unique.
28908  */
28909 #define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
28910 
28911 #define DMA_ES_GPE_MASK                          (0x8000U)
28912 #define DMA_ES_GPE_SHIFT                         (15U)
28913 /*! GPE - Group Priority Error
28914  *  0b0..No group priority error.
28915  *  0b1..The most-recently recorded error was a configuration error among the group priorities. All group priorities are not unique.
28916  */
28917 #define DMA_ES_GPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
28918 
28919 #define DMA_ES_ECX_MASK                          (0x10000U)
28920 #define DMA_ES_ECX_SHIFT                         (16U)
28921 /*! ECX - Transfer Canceled
28922  *  0b0..No canceled transfers
28923  *  0b1..The most-recently recorded entry was a canceled transfer initiated by the error cancel transfer field
28924  */
28925 #define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
28926 
28927 #define DMA_ES_VLD_MASK                          (0x80000000U)
28928 #define DMA_ES_VLD_SHIFT                         (31U)
28929 /*! VLD - Logical OR of all ERR status fields
28930  *  0b0..No ERR fields are 1
28931  *  0b1..At least one ERR field has a value of 1, indicating a valid error exists that has not been cleared
28932  */
28933 #define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
28934 /*! @} */
28935 
28936 /*! @name ERQ - Enable Request */
28937 /*! @{ */
28938 
28939 #define DMA_ERQ_ERQ0_MASK                        (0x1U)
28940 #define DMA_ERQ_ERQ0_SHIFT                       (0U)
28941 /*! ERQ0 - Enable DMA Request 0
28942  *  0b0..The DMA request signal for channel 0 is disabled
28943  *  0b1..The DMA request signal for channel 0 is enabled
28944  */
28945 #define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
28946 
28947 #define DMA_ERQ_ERQ1_MASK                        (0x2U)
28948 #define DMA_ERQ_ERQ1_SHIFT                       (1U)
28949 /*! ERQ1 - Enable DMA Request 1
28950  *  0b0..The DMA request signal for channel 1 is disabled
28951  *  0b1..The DMA request signal for channel 1 is enabled
28952  */
28953 #define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
28954 
28955 #define DMA_ERQ_ERQ2_MASK                        (0x4U)
28956 #define DMA_ERQ_ERQ2_SHIFT                       (2U)
28957 /*! ERQ2 - Enable DMA Request 2
28958  *  0b0..The DMA request signal for channel 2 is disabled
28959  *  0b1..The DMA request signal for channel 2 is enabled
28960  */
28961 #define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
28962 
28963 #define DMA_ERQ_ERQ3_MASK                        (0x8U)
28964 #define DMA_ERQ_ERQ3_SHIFT                       (3U)
28965 /*! ERQ3 - Enable DMA Request 3
28966  *  0b0..The DMA request signal for channel 3 is disabled
28967  *  0b1..The DMA request signal for channel 3 is enabled
28968  */
28969 #define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
28970 
28971 #define DMA_ERQ_ERQ4_MASK                        (0x10U)
28972 #define DMA_ERQ_ERQ4_SHIFT                       (4U)
28973 /*! ERQ4 - Enable DMA Request 4
28974  *  0b0..The DMA request signal for channel 4 is disabled
28975  *  0b1..The DMA request signal for channel 4 is enabled
28976  */
28977 #define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
28978 
28979 #define DMA_ERQ_ERQ5_MASK                        (0x20U)
28980 #define DMA_ERQ_ERQ5_SHIFT                       (5U)
28981 /*! ERQ5 - Enable DMA Request 5
28982  *  0b0..The DMA request signal for channel 5 is disabled
28983  *  0b1..The DMA request signal for channel 5 is enabled
28984  */
28985 #define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
28986 
28987 #define DMA_ERQ_ERQ6_MASK                        (0x40U)
28988 #define DMA_ERQ_ERQ6_SHIFT                       (6U)
28989 /*! ERQ6 - Enable DMA Request 6
28990  *  0b0..The DMA request signal for channel 6 is disabled
28991  *  0b1..The DMA request signal for channel 6 is enabled
28992  */
28993 #define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
28994 
28995 #define DMA_ERQ_ERQ7_MASK                        (0x80U)
28996 #define DMA_ERQ_ERQ7_SHIFT                       (7U)
28997 /*! ERQ7 - Enable DMA Request 7
28998  *  0b0..The DMA request signal for channel 7 is disabled
28999  *  0b1..The DMA request signal for channel 7 is enabled
29000  */
29001 #define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
29002 
29003 #define DMA_ERQ_ERQ8_MASK                        (0x100U)
29004 #define DMA_ERQ_ERQ8_SHIFT                       (8U)
29005 /*! ERQ8 - Enable DMA Request 8
29006  *  0b0..The DMA request signal for channel 8 is disabled
29007  *  0b1..The DMA request signal for channel 8 is enabled
29008  */
29009 #define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
29010 
29011 #define DMA_ERQ_ERQ9_MASK                        (0x200U)
29012 #define DMA_ERQ_ERQ9_SHIFT                       (9U)
29013 /*! ERQ9 - Enable DMA Request 9
29014  *  0b0..The DMA request signal for channel 9 is disabled
29015  *  0b1..The DMA request signal for channel 9 is enabled
29016  */
29017 #define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
29018 
29019 #define DMA_ERQ_ERQ10_MASK                       (0x400U)
29020 #define DMA_ERQ_ERQ10_SHIFT                      (10U)
29021 /*! ERQ10 - Enable DMA Request 10
29022  *  0b0..The DMA request signal for channel 10 is disabled
29023  *  0b1..The DMA request signal for channel 10 is enabled
29024  */
29025 #define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
29026 
29027 #define DMA_ERQ_ERQ11_MASK                       (0x800U)
29028 #define DMA_ERQ_ERQ11_SHIFT                      (11U)
29029 /*! ERQ11 - Enable DMA Request 11
29030  *  0b0..The DMA request signal for channel 11 is disabled
29031  *  0b1..The DMA request signal for channel 11 is enabled
29032  */
29033 #define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
29034 
29035 #define DMA_ERQ_ERQ12_MASK                       (0x1000U)
29036 #define DMA_ERQ_ERQ12_SHIFT                      (12U)
29037 /*! ERQ12 - Enable DMA Request 12
29038  *  0b0..The DMA request signal for channel 12 is disabled
29039  *  0b1..The DMA request signal for channel 12 is enabled
29040  */
29041 #define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
29042 
29043 #define DMA_ERQ_ERQ13_MASK                       (0x2000U)
29044 #define DMA_ERQ_ERQ13_SHIFT                      (13U)
29045 /*! ERQ13 - Enable DMA Request 13
29046  *  0b0..The DMA request signal for channel 13 is disabled
29047  *  0b1..The DMA request signal for channel 13 is enabled
29048  */
29049 #define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
29050 
29051 #define DMA_ERQ_ERQ14_MASK                       (0x4000U)
29052 #define DMA_ERQ_ERQ14_SHIFT                      (14U)
29053 /*! ERQ14 - Enable DMA Request 14
29054  *  0b0..The DMA request signal for channel 14 is disabled
29055  *  0b1..The DMA request signal for channel 14 is enabled
29056  */
29057 #define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
29058 
29059 #define DMA_ERQ_ERQ15_MASK                       (0x8000U)
29060 #define DMA_ERQ_ERQ15_SHIFT                      (15U)
29061 /*! ERQ15 - Enable DMA Request 15
29062  *  0b0..The DMA request signal for channel 15 is disabled
29063  *  0b1..The DMA request signal for channel 15 is enabled
29064  */
29065 #define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
29066 
29067 #define DMA_ERQ_ERQ16_MASK                       (0x10000U)
29068 #define DMA_ERQ_ERQ16_SHIFT                      (16U)
29069 /*! ERQ16 - Enable DMA Request 16
29070  *  0b0..The DMA request signal for channel 16 is disabled
29071  *  0b1..The DMA request signal for channel 16 is enabled
29072  */
29073 #define DMA_ERQ_ERQ16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
29074 
29075 #define DMA_ERQ_ERQ17_MASK                       (0x20000U)
29076 #define DMA_ERQ_ERQ17_SHIFT                      (17U)
29077 /*! ERQ17 - Enable DMA Request 17
29078  *  0b0..The DMA request signal for channel 17 is disabled
29079  *  0b1..The DMA request signal for channel 17 is enabled
29080  */
29081 #define DMA_ERQ_ERQ17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
29082 
29083 #define DMA_ERQ_ERQ18_MASK                       (0x40000U)
29084 #define DMA_ERQ_ERQ18_SHIFT                      (18U)
29085 /*! ERQ18 - Enable DMA Request 18
29086  *  0b0..The DMA request signal for channel 18 is disabled
29087  *  0b1..The DMA request signal for channel 18 is enabled
29088  */
29089 #define DMA_ERQ_ERQ18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
29090 
29091 #define DMA_ERQ_ERQ19_MASK                       (0x80000U)
29092 #define DMA_ERQ_ERQ19_SHIFT                      (19U)
29093 /*! ERQ19 - Enable DMA Request 19
29094  *  0b0..The DMA request signal for channel 19 is disabled
29095  *  0b1..The DMA request signal for channel 19 is enabled
29096  */
29097 #define DMA_ERQ_ERQ19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
29098 
29099 #define DMA_ERQ_ERQ20_MASK                       (0x100000U)
29100 #define DMA_ERQ_ERQ20_SHIFT                      (20U)
29101 /*! ERQ20 - Enable DMA Request 20
29102  *  0b0..The DMA request signal for channel 20 is disabled
29103  *  0b1..The DMA request signal for channel 20 is enabled
29104  */
29105 #define DMA_ERQ_ERQ20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
29106 
29107 #define DMA_ERQ_ERQ21_MASK                       (0x200000U)
29108 #define DMA_ERQ_ERQ21_SHIFT                      (21U)
29109 /*! ERQ21 - Enable DMA Request 21
29110  *  0b0..The DMA request signal for channel 21 is disabled
29111  *  0b1..The DMA request signal for channel 21 is enabled
29112  */
29113 #define DMA_ERQ_ERQ21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
29114 
29115 #define DMA_ERQ_ERQ22_MASK                       (0x400000U)
29116 #define DMA_ERQ_ERQ22_SHIFT                      (22U)
29117 /*! ERQ22 - Enable DMA Request 22
29118  *  0b0..The DMA request signal for channel 22 is disabled
29119  *  0b1..The DMA request signal for channel 22 is enabled
29120  */
29121 #define DMA_ERQ_ERQ22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
29122 
29123 #define DMA_ERQ_ERQ23_MASK                       (0x800000U)
29124 #define DMA_ERQ_ERQ23_SHIFT                      (23U)
29125 /*! ERQ23 - Enable DMA Request 23
29126  *  0b0..The DMA request signal for channel 23 is disabled
29127  *  0b1..The DMA request signal for channel 23 is enabled
29128  */
29129 #define DMA_ERQ_ERQ23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
29130 
29131 #define DMA_ERQ_ERQ24_MASK                       (0x1000000U)
29132 #define DMA_ERQ_ERQ24_SHIFT                      (24U)
29133 /*! ERQ24 - Enable DMA Request 24
29134  *  0b0..The DMA request signal for channel 24 is disabled
29135  *  0b1..The DMA request signal for channel 24 is enabled
29136  */
29137 #define DMA_ERQ_ERQ24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
29138 
29139 #define DMA_ERQ_ERQ25_MASK                       (0x2000000U)
29140 #define DMA_ERQ_ERQ25_SHIFT                      (25U)
29141 /*! ERQ25 - Enable DMA Request 25
29142  *  0b0..The DMA request signal for channel 25 is disabled
29143  *  0b1..The DMA request signal for channel 25 is enabled
29144  */
29145 #define DMA_ERQ_ERQ25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
29146 
29147 #define DMA_ERQ_ERQ26_MASK                       (0x4000000U)
29148 #define DMA_ERQ_ERQ26_SHIFT                      (26U)
29149 /*! ERQ26 - Enable DMA Request 26
29150  *  0b0..The DMA request signal for channel 26 is disabled
29151  *  0b1..The DMA request signal for channel 26 is enabled
29152  */
29153 #define DMA_ERQ_ERQ26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
29154 
29155 #define DMA_ERQ_ERQ27_MASK                       (0x8000000U)
29156 #define DMA_ERQ_ERQ27_SHIFT                      (27U)
29157 /*! ERQ27 - Enable DMA Request 27
29158  *  0b0..The DMA request signal for channel 27 is disabled
29159  *  0b1..The DMA request signal for channel 27 is enabled
29160  */
29161 #define DMA_ERQ_ERQ27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
29162 
29163 #define DMA_ERQ_ERQ28_MASK                       (0x10000000U)
29164 #define DMA_ERQ_ERQ28_SHIFT                      (28U)
29165 /*! ERQ28 - Enable DMA Request 28
29166  *  0b0..The DMA request signal for channel 28 is disabled
29167  *  0b1..The DMA request signal for channel 28 is enabled
29168  */
29169 #define DMA_ERQ_ERQ28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
29170 
29171 #define DMA_ERQ_ERQ29_MASK                       (0x20000000U)
29172 #define DMA_ERQ_ERQ29_SHIFT                      (29U)
29173 /*! ERQ29 - Enable DMA Request 29
29174  *  0b0..The DMA request signal for channel 29 is disabled
29175  *  0b1..The DMA request signal for channel 29 is enabled
29176  */
29177 #define DMA_ERQ_ERQ29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
29178 
29179 #define DMA_ERQ_ERQ30_MASK                       (0x40000000U)
29180 #define DMA_ERQ_ERQ30_SHIFT                      (30U)
29181 /*! ERQ30 - Enable DMA Request 30
29182  *  0b0..The DMA request signal for channel 30 is disabled
29183  *  0b1..The DMA request signal for channel 30 is enabled
29184  */
29185 #define DMA_ERQ_ERQ30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
29186 
29187 #define DMA_ERQ_ERQ31_MASK                       (0x80000000U)
29188 #define DMA_ERQ_ERQ31_SHIFT                      (31U)
29189 /*! ERQ31 - Enable DMA Request 31
29190  *  0b0..The DMA request signal for channel 31 is disabled
29191  *  0b1..The DMA request signal for channel 31 is enabled
29192  */
29193 #define DMA_ERQ_ERQ31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
29194 /*! @} */
29195 
29196 /*! @name EEI - Enable Error Interrupt */
29197 /*! @{ */
29198 
29199 #define DMA_EEI_EEI0_MASK                        (0x1U)
29200 #define DMA_EEI_EEI0_SHIFT                       (0U)
29201 /*! EEI0 - Enable Error Interrupt 0
29202  *  0b0..An error on channel 0 does not generate an error interrupt
29203  *  0b1..An error on channel 0 generates an error interrupt request
29204  */
29205 #define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
29206 
29207 #define DMA_EEI_EEI1_MASK                        (0x2U)
29208 #define DMA_EEI_EEI1_SHIFT                       (1U)
29209 /*! EEI1 - Enable Error Interrupt 1
29210  *  0b0..An error on channel 1 does not generate an error interrupt
29211  *  0b1..An error on channel 1 generates an error interrupt request
29212  */
29213 #define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
29214 
29215 #define DMA_EEI_EEI2_MASK                        (0x4U)
29216 #define DMA_EEI_EEI2_SHIFT                       (2U)
29217 /*! EEI2 - Enable Error Interrupt 2
29218  *  0b0..An error on channel 2 does not generate an error interrupt
29219  *  0b1..An error on channel 2 generates an error interrupt request
29220  */
29221 #define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
29222 
29223 #define DMA_EEI_EEI3_MASK                        (0x8U)
29224 #define DMA_EEI_EEI3_SHIFT                       (3U)
29225 /*! EEI3 - Enable Error Interrupt 3
29226  *  0b0..An error on channel 3 does not generate an error interrupt
29227  *  0b1..An error on channel 3 generates an error interrupt request
29228  */
29229 #define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
29230 
29231 #define DMA_EEI_EEI4_MASK                        (0x10U)
29232 #define DMA_EEI_EEI4_SHIFT                       (4U)
29233 /*! EEI4 - Enable Error Interrupt 4
29234  *  0b0..An error on channel 4 does not generate an error interrupt
29235  *  0b1..An error on channel 4 generates an error interrupt request
29236  */
29237 #define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
29238 
29239 #define DMA_EEI_EEI5_MASK                        (0x20U)
29240 #define DMA_EEI_EEI5_SHIFT                       (5U)
29241 /*! EEI5 - Enable Error Interrupt 5
29242  *  0b0..An error on channel 5 does not generate an error interrupt
29243  *  0b1..An error on channel 5 generates an error interrupt request
29244  */
29245 #define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
29246 
29247 #define DMA_EEI_EEI6_MASK                        (0x40U)
29248 #define DMA_EEI_EEI6_SHIFT                       (6U)
29249 /*! EEI6 - Enable Error Interrupt 6
29250  *  0b0..An error on channel 6 does not generate an error interrupt
29251  *  0b1..An error on channel 6 generates an error interrupt request
29252  */
29253 #define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
29254 
29255 #define DMA_EEI_EEI7_MASK                        (0x80U)
29256 #define DMA_EEI_EEI7_SHIFT                       (7U)
29257 /*! EEI7 - Enable Error Interrupt 7
29258  *  0b0..An error on channel 7 does not generate an error interrupt
29259  *  0b1..An error on channel 7 generates an error interrupt request
29260  */
29261 #define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
29262 
29263 #define DMA_EEI_EEI8_MASK                        (0x100U)
29264 #define DMA_EEI_EEI8_SHIFT                       (8U)
29265 /*! EEI8 - Enable Error Interrupt 8
29266  *  0b0..An error on channel 8 does not generate an error interrupt
29267  *  0b1..An error on channel 8 generates an error interrupt request
29268  */
29269 #define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
29270 
29271 #define DMA_EEI_EEI9_MASK                        (0x200U)
29272 #define DMA_EEI_EEI9_SHIFT                       (9U)
29273 /*! EEI9 - Enable Error Interrupt 9
29274  *  0b0..An error on channel 9 does not generate an error interrupt
29275  *  0b1..An error on channel 9 generates an error interrupt request
29276  */
29277 #define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
29278 
29279 #define DMA_EEI_EEI10_MASK                       (0x400U)
29280 #define DMA_EEI_EEI10_SHIFT                      (10U)
29281 /*! EEI10 - Enable Error Interrupt 10
29282  *  0b0..An error on channel 10 does not generate an error interrupt
29283  *  0b1..An error on channel 10 generates an error interrupt request
29284  */
29285 #define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
29286 
29287 #define DMA_EEI_EEI11_MASK                       (0x800U)
29288 #define DMA_EEI_EEI11_SHIFT                      (11U)
29289 /*! EEI11 - Enable Error Interrupt 11
29290  *  0b0..An error on channel 11 does not generate an error interrupt
29291  *  0b1..An error on channel 11 generates an error interrupt request
29292  */
29293 #define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
29294 
29295 #define DMA_EEI_EEI12_MASK                       (0x1000U)
29296 #define DMA_EEI_EEI12_SHIFT                      (12U)
29297 /*! EEI12 - Enable Error Interrupt 12
29298  *  0b0..An error on channel 12 does not generate an error interrupt
29299  *  0b1..An error on channel 12 generates an error interrupt request
29300  */
29301 #define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
29302 
29303 #define DMA_EEI_EEI13_MASK                       (0x2000U)
29304 #define DMA_EEI_EEI13_SHIFT                      (13U)
29305 /*! EEI13 - Enable Error Interrupt 13
29306  *  0b0..An error on channel 13 does not generate an error interrupt
29307  *  0b1..An error on channel 13 generates an error interrupt request
29308  */
29309 #define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
29310 
29311 #define DMA_EEI_EEI14_MASK                       (0x4000U)
29312 #define DMA_EEI_EEI14_SHIFT                      (14U)
29313 /*! EEI14 - Enable Error Interrupt 14
29314  *  0b0..An error on channel 14 does not generate an error interrupt
29315  *  0b1..An error on channel 14 generates an error interrupt request
29316  */
29317 #define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
29318 
29319 #define DMA_EEI_EEI15_MASK                       (0x8000U)
29320 #define DMA_EEI_EEI15_SHIFT                      (15U)
29321 /*! EEI15 - Enable Error Interrupt 15
29322  *  0b0..An error on channel 15 does not generate an error interrupt
29323  *  0b1..An error on channel 15 generates an error interrupt request
29324  */
29325 #define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
29326 
29327 #define DMA_EEI_EEI16_MASK                       (0x10000U)
29328 #define DMA_EEI_EEI16_SHIFT                      (16U)
29329 /*! EEI16 - Enable Error Interrupt 16
29330  *  0b0..An error on channel 16 does not generate an error interrupt
29331  *  0b1..An error on channel 16 generates an error interrupt request
29332  */
29333 #define DMA_EEI_EEI16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
29334 
29335 #define DMA_EEI_EEI17_MASK                       (0x20000U)
29336 #define DMA_EEI_EEI17_SHIFT                      (17U)
29337 /*! EEI17 - Enable Error Interrupt 17
29338  *  0b0..An error on channel 17 does not generate an error interrupt
29339  *  0b1..An error on channel 17 generates an error interrupt request
29340  */
29341 #define DMA_EEI_EEI17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
29342 
29343 #define DMA_EEI_EEI18_MASK                       (0x40000U)
29344 #define DMA_EEI_EEI18_SHIFT                      (18U)
29345 /*! EEI18 - Enable Error Interrupt 18
29346  *  0b0..An error on channel 18 does not generate an error interrupt
29347  *  0b1..An error on channel 18 generates an error interrupt request
29348  */
29349 #define DMA_EEI_EEI18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
29350 
29351 #define DMA_EEI_EEI19_MASK                       (0x80000U)
29352 #define DMA_EEI_EEI19_SHIFT                      (19U)
29353 /*! EEI19 - Enable Error Interrupt 19
29354  *  0b0..An error on channel 19 does not generate an error interrupt
29355  *  0b1..An error on channel 19 generates an error interrupt request
29356  */
29357 #define DMA_EEI_EEI19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
29358 
29359 #define DMA_EEI_EEI20_MASK                       (0x100000U)
29360 #define DMA_EEI_EEI20_SHIFT                      (20U)
29361 /*! EEI20 - Enable Error Interrupt 20
29362  *  0b0..An error on channel 20 does not generate an error interrupt
29363  *  0b1..An error on channel 20 generates an error interrupt request
29364  */
29365 #define DMA_EEI_EEI20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
29366 
29367 #define DMA_EEI_EEI21_MASK                       (0x200000U)
29368 #define DMA_EEI_EEI21_SHIFT                      (21U)
29369 /*! EEI21 - Enable Error Interrupt 21
29370  *  0b0..An error on channel 21 does not generate an error interrupt
29371  *  0b1..An error on channel 21 generates an error interrupt request
29372  */
29373 #define DMA_EEI_EEI21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
29374 
29375 #define DMA_EEI_EEI22_MASK                       (0x400000U)
29376 #define DMA_EEI_EEI22_SHIFT                      (22U)
29377 /*! EEI22 - Enable Error Interrupt 22
29378  *  0b0..An error on channel 22 does not generate an error interrupt
29379  *  0b1..An error on channel 22 generates an error interrupt request
29380  */
29381 #define DMA_EEI_EEI22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
29382 
29383 #define DMA_EEI_EEI23_MASK                       (0x800000U)
29384 #define DMA_EEI_EEI23_SHIFT                      (23U)
29385 /*! EEI23 - Enable Error Interrupt 23
29386  *  0b0..An error on channel 23 does not generate an error interrupt
29387  *  0b1..An error on channel 23 generates an error interrupt request
29388  */
29389 #define DMA_EEI_EEI23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
29390 
29391 #define DMA_EEI_EEI24_MASK                       (0x1000000U)
29392 #define DMA_EEI_EEI24_SHIFT                      (24U)
29393 /*! EEI24 - Enable Error Interrupt 24
29394  *  0b0..An error on channel 24 does not generate an error interrupt
29395  *  0b1..An error on channel 24 generates an error interrupt request
29396  */
29397 #define DMA_EEI_EEI24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
29398 
29399 #define DMA_EEI_EEI25_MASK                       (0x2000000U)
29400 #define DMA_EEI_EEI25_SHIFT                      (25U)
29401 /*! EEI25 - Enable Error Interrupt 25
29402  *  0b0..An error on channel 25 does not generate an error interrupt
29403  *  0b1..An error on channel 25 generates an error interrupt request
29404  */
29405 #define DMA_EEI_EEI25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
29406 
29407 #define DMA_EEI_EEI26_MASK                       (0x4000000U)
29408 #define DMA_EEI_EEI26_SHIFT                      (26U)
29409 /*! EEI26 - Enable Error Interrupt 26
29410  *  0b0..An error on channel 26 does not generate an error interrupt
29411  *  0b1..An error on channel 26 generates an error interrupt request
29412  */
29413 #define DMA_EEI_EEI26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
29414 
29415 #define DMA_EEI_EEI27_MASK                       (0x8000000U)
29416 #define DMA_EEI_EEI27_SHIFT                      (27U)
29417 /*! EEI27 - Enable Error Interrupt 27
29418  *  0b0..An error on channel 27 does not generate an error interrupt
29419  *  0b1..An error on channel 27 generates an error interrupt request
29420  */
29421 #define DMA_EEI_EEI27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
29422 
29423 #define DMA_EEI_EEI28_MASK                       (0x10000000U)
29424 #define DMA_EEI_EEI28_SHIFT                      (28U)
29425 /*! EEI28 - Enable Error Interrupt 28
29426  *  0b0..An error on channel 28 does not generate an error interrupt
29427  *  0b1..An error on channel 28 generates an error interrupt request
29428  */
29429 #define DMA_EEI_EEI28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
29430 
29431 #define DMA_EEI_EEI29_MASK                       (0x20000000U)
29432 #define DMA_EEI_EEI29_SHIFT                      (29U)
29433 /*! EEI29 - Enable Error Interrupt 29
29434  *  0b0..An error on channel 29 does not generate an error interrupt
29435  *  0b1..An error on channel 29 generates an error interrupt request
29436  */
29437 #define DMA_EEI_EEI29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
29438 
29439 #define DMA_EEI_EEI30_MASK                       (0x40000000U)
29440 #define DMA_EEI_EEI30_SHIFT                      (30U)
29441 /*! EEI30 - Enable Error Interrupt 30
29442  *  0b0..An error on channel 30 does not generate an error interrupt
29443  *  0b1..An error on channel 30 generates an error interrupt request
29444  */
29445 #define DMA_EEI_EEI30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
29446 
29447 #define DMA_EEI_EEI31_MASK                       (0x80000000U)
29448 #define DMA_EEI_EEI31_SHIFT                      (31U)
29449 /*! EEI31 - Enable Error Interrupt 31
29450  *  0b0..An error on channel 31 does not generate an error interrupt
29451  *  0b1..An error on channel 31 generates an error interrupt request
29452  */
29453 #define DMA_EEI_EEI31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
29454 /*! @} */
29455 
29456 /*! @name CEEI - Clear Enable Error Interrupt */
29457 /*! @{ */
29458 
29459 #define DMA_CEEI_CEEI_MASK                       (0x1FU)
29460 #define DMA_CEEI_CEEI_SHIFT                      (0U)
29461 /*! CEEI - Clear Enable Error Interrupt */
29462 #define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
29463 
29464 #define DMA_CEEI_CAEE_MASK                       (0x40U)
29465 #define DMA_CEEI_CAEE_SHIFT                      (6U)
29466 /*! CAEE - Clear All Enable Error Interrupts
29467  *  0b0..Write 0 only to the EEI field specified in the CEEI field
29468  *  0b1..Write 0 to all fields in EEI
29469  */
29470 #define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
29471 
29472 #define DMA_CEEI_NOP_MASK                        (0x80U)
29473 #define DMA_CEEI_NOP_SHIFT                       (7U)
29474 /*! NOP - No Op Enable
29475  *  0b0..Normal operation
29476  *  0b1..No operation, ignore the other fields in this register
29477  */
29478 #define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
29479 /*! @} */
29480 
29481 /*! @name SEEI - Set Enable Error Interrupt */
29482 /*! @{ */
29483 
29484 #define DMA_SEEI_SEEI_MASK                       (0x1FU)
29485 #define DMA_SEEI_SEEI_SHIFT                      (0U)
29486 /*! SEEI - Set Enable Error Interrupt */
29487 #define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
29488 
29489 #define DMA_SEEI_SAEE_MASK                       (0x40U)
29490 #define DMA_SEEI_SAEE_SHIFT                      (6U)
29491 /*! SAEE - Set All Enable Error Interrupts
29492  *  0b0..Write 1 only to the EEI field specified in the SEEI field
29493  *  0b1..Writes 1 to all fields in EEI
29494  */
29495 #define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
29496 
29497 #define DMA_SEEI_NOP_MASK                        (0x80U)
29498 #define DMA_SEEI_NOP_SHIFT                       (7U)
29499 /*! NOP - No Op Enable
29500  *  0b0..Normal operation
29501  *  0b1..No operation, ignore the other fields in this register
29502  */
29503 #define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
29504 /*! @} */
29505 
29506 /*! @name CERQ - Clear Enable Request */
29507 /*! @{ */
29508 
29509 #define DMA_CERQ_CERQ_MASK                       (0x1FU)
29510 #define DMA_CERQ_CERQ_SHIFT                      (0U)
29511 /*! CERQ - Clear Enable Request */
29512 #define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
29513 
29514 #define DMA_CERQ_CAER_MASK                       (0x40U)
29515 #define DMA_CERQ_CAER_SHIFT                      (6U)
29516 /*! CAER - Clear All Enable Requests
29517  *  0b0..Write 0 to only the ERQ field specified in the CERQ field
29518  *  0b1..Write 0 to all fields in ERQ
29519  */
29520 #define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
29521 
29522 #define DMA_CERQ_NOP_MASK                        (0x80U)
29523 #define DMA_CERQ_NOP_SHIFT                       (7U)
29524 /*! NOP - No Op Enable
29525  *  0b0..Normal operation
29526  *  0b1..No operation, ignore the other fields in this register
29527  */
29528 #define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
29529 /*! @} */
29530 
29531 /*! @name SERQ - Set Enable Request */
29532 /*! @{ */
29533 
29534 #define DMA_SERQ_SERQ_MASK                       (0x1FU)
29535 #define DMA_SERQ_SERQ_SHIFT                      (0U)
29536 /*! SERQ - Set Enable Request */
29537 #define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
29538 
29539 #define DMA_SERQ_SAER_MASK                       (0x40U)
29540 #define DMA_SERQ_SAER_SHIFT                      (6U)
29541 /*! SAER - Set All Enable Requests
29542  *  0b0..Write 1 to only the ERQ field specified in the SERQ field
29543  *  0b1..Write 1 to all fields in ERQ
29544  */
29545 #define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
29546 
29547 #define DMA_SERQ_NOP_MASK                        (0x80U)
29548 #define DMA_SERQ_NOP_SHIFT                       (7U)
29549 /*! NOP - No Op Enable
29550  *  0b0..Normal operation
29551  *  0b1..No operation, ignore the other fields in this register
29552  */
29553 #define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
29554 /*! @} */
29555 
29556 /*! @name CDNE - Clear DONE Status Bit */
29557 /*! @{ */
29558 
29559 #define DMA_CDNE_CDNE_MASK                       (0x1FU)
29560 #define DMA_CDNE_CDNE_SHIFT                      (0U)
29561 /*! CDNE - Clear DONE field */
29562 #define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
29563 
29564 #define DMA_CDNE_CADN_MASK                       (0x40U)
29565 #define DMA_CDNE_CADN_SHIFT                      (6U)
29566 /*! CADN - Clears All DONE fields
29567  *  0b0..Writes 0 to only the TCDn_CSR[DONE] field specified in the CDNE field
29568  *  0b1..Writes 0 to all bits in TCDn_CSR[DONE]
29569  */
29570 #define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
29571 
29572 #define DMA_CDNE_NOP_MASK                        (0x80U)
29573 #define DMA_CDNE_NOP_SHIFT                       (7U)
29574 /*! NOP - No Op Enable
29575  *  0b0..Normal operation
29576  *  0b1..No operation; all other fields in this register are ignored.
29577  */
29578 #define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
29579 /*! @} */
29580 
29581 /*! @name SSRT - Set START Bit */
29582 /*! @{ */
29583 
29584 #define DMA_SSRT_SSRT_MASK                       (0x1FU)
29585 #define DMA_SSRT_SSRT_SHIFT                      (0U)
29586 /*! SSRT - Set START field */
29587 #define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
29588 
29589 #define DMA_SSRT_SAST_MASK                       (0x40U)
29590 #define DMA_SSRT_SAST_SHIFT                      (6U)
29591 /*! SAST - Set All START fields (activates all channels)
29592  *  0b0..Write 1 to only the TCDn_CSR[START] field specified in the SSRT field
29593  *  0b1..Write 1 to all bits in TCDn_CSR[START]
29594  */
29595 #define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
29596 
29597 #define DMA_SSRT_NOP_MASK                        (0x80U)
29598 #define DMA_SSRT_NOP_SHIFT                       (7U)
29599 /*! NOP - No Op Enable
29600  *  0b0..Normal operation
29601  *  0b1..No operation; all other fields in this register are ignored.
29602  */
29603 #define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
29604 /*! @} */
29605 
29606 /*! @name CERR - Clear Error */
29607 /*! @{ */
29608 
29609 #define DMA_CERR_CERR_MASK                       (0x1FU)
29610 #define DMA_CERR_CERR_SHIFT                      (0U)
29611 /*! CERR - Clear Error Indicator */
29612 #define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
29613 
29614 #define DMA_CERR_CAEI_MASK                       (0x40U)
29615 #define DMA_CERR_CAEI_SHIFT                      (6U)
29616 /*! CAEI - Clear All Error Indicators
29617  *  0b0..Write 0 to only the ERR field specified in the CERR field
29618  *  0b1..Write 0 to all fields in ERR
29619  */
29620 #define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
29621 
29622 #define DMA_CERR_NOP_MASK                        (0x80U)
29623 #define DMA_CERR_NOP_SHIFT                       (7U)
29624 /*! NOP - No Op Enable
29625  *  0b0..Normal operation
29626  *  0b1..No operation; all other fields in this register are ignored.
29627  */
29628 #define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
29629 /*! @} */
29630 
29631 /*! @name CINT - Clear Interrupt Request */
29632 /*! @{ */
29633 
29634 #define DMA_CINT_CINT_MASK                       (0x1FU)
29635 #define DMA_CINT_CINT_SHIFT                      (0U)
29636 /*! CINT - Clear Interrupt Request */
29637 #define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
29638 
29639 #define DMA_CINT_CAIR_MASK                       (0x40U)
29640 #define DMA_CINT_CAIR_SHIFT                      (6U)
29641 /*! CAIR - Clear All Interrupt Requests
29642  *  0b0..Clear only the INT field specified in the CINT field
29643  *  0b1..Clear all bits in INT
29644  */
29645 #define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
29646 
29647 #define DMA_CINT_NOP_MASK                        (0x80U)
29648 #define DMA_CINT_NOP_SHIFT                       (7U)
29649 /*! NOP - No Op Enable
29650  *  0b0..Normal operation
29651  *  0b1..No operation; all other fields in this register are ignored.
29652  */
29653 #define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
29654 /*! @} */
29655 
29656 /*! @name INT - Interrupt Request */
29657 /*! @{ */
29658 
29659 #define DMA_INT_INT0_MASK                        (0x1U)
29660 #define DMA_INT_INT0_SHIFT                       (0U)
29661 /*! INT0 - Interrupt Request 0
29662  *  0b0..The interrupt request for channel 0 is cleared
29663  *  0b1..The interrupt request for channel 0 is active
29664  */
29665 #define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
29666 
29667 #define DMA_INT_INT1_MASK                        (0x2U)
29668 #define DMA_INT_INT1_SHIFT                       (1U)
29669 /*! INT1 - Interrupt Request 1
29670  *  0b0..The interrupt request for channel 1 is cleared
29671  *  0b1..The interrupt request for channel 1 is active
29672  */
29673 #define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
29674 
29675 #define DMA_INT_INT2_MASK                        (0x4U)
29676 #define DMA_INT_INT2_SHIFT                       (2U)
29677 /*! INT2 - Interrupt Request 2
29678  *  0b0..The interrupt request for channel 2 is cleared
29679  *  0b1..The interrupt request for channel 2 is active
29680  */
29681 #define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
29682 
29683 #define DMA_INT_INT3_MASK                        (0x8U)
29684 #define DMA_INT_INT3_SHIFT                       (3U)
29685 /*! INT3 - Interrupt Request 3
29686  *  0b0..The interrupt request for channel 3 is cleared
29687  *  0b1..The interrupt request for channel 3 is active
29688  */
29689 #define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
29690 
29691 #define DMA_INT_INT4_MASK                        (0x10U)
29692 #define DMA_INT_INT4_SHIFT                       (4U)
29693 /*! INT4 - Interrupt Request 4
29694  *  0b0..The interrupt request for channel 4 is cleared
29695  *  0b1..The interrupt request for channel 4 is active
29696  */
29697 #define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
29698 
29699 #define DMA_INT_INT5_MASK                        (0x20U)
29700 #define DMA_INT_INT5_SHIFT                       (5U)
29701 /*! INT5 - Interrupt Request 5
29702  *  0b0..The interrupt request for channel 5 is cleared
29703  *  0b1..The interrupt request for channel 5 is active
29704  */
29705 #define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
29706 
29707 #define DMA_INT_INT6_MASK                        (0x40U)
29708 #define DMA_INT_INT6_SHIFT                       (6U)
29709 /*! INT6 - Interrupt Request 6
29710  *  0b0..The interrupt request for channel 6 is cleared
29711  *  0b1..The interrupt request for channel 6 is active
29712  */
29713 #define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
29714 
29715 #define DMA_INT_INT7_MASK                        (0x80U)
29716 #define DMA_INT_INT7_SHIFT                       (7U)
29717 /*! INT7 - Interrupt Request 7
29718  *  0b0..The interrupt request for channel 7 is cleared
29719  *  0b1..The interrupt request for channel 7 is active
29720  */
29721 #define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
29722 
29723 #define DMA_INT_INT8_MASK                        (0x100U)
29724 #define DMA_INT_INT8_SHIFT                       (8U)
29725 /*! INT8 - Interrupt Request 8
29726  *  0b0..The interrupt request for channel 8 is cleared
29727  *  0b1..The interrupt request for channel 8 is active
29728  */
29729 #define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
29730 
29731 #define DMA_INT_INT9_MASK                        (0x200U)
29732 #define DMA_INT_INT9_SHIFT                       (9U)
29733 /*! INT9 - Interrupt Request 9
29734  *  0b0..The interrupt request for channel 9 is cleared
29735  *  0b1..The interrupt request for channel 9 is active
29736  */
29737 #define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
29738 
29739 #define DMA_INT_INT10_MASK                       (0x400U)
29740 #define DMA_INT_INT10_SHIFT                      (10U)
29741 /*! INT10 - Interrupt Request 10
29742  *  0b0..The interrupt request for channel 10 is cleared
29743  *  0b1..The interrupt request for channel 10 is active
29744  */
29745 #define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
29746 
29747 #define DMA_INT_INT11_MASK                       (0x800U)
29748 #define DMA_INT_INT11_SHIFT                      (11U)
29749 /*! INT11 - Interrupt Request 11
29750  *  0b0..The interrupt request for channel 11 is cleared
29751  *  0b1..The interrupt request for channel 11 is active
29752  */
29753 #define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
29754 
29755 #define DMA_INT_INT12_MASK                       (0x1000U)
29756 #define DMA_INT_INT12_SHIFT                      (12U)
29757 /*! INT12 - Interrupt Request 12
29758  *  0b0..The interrupt request for channel 12 is cleared
29759  *  0b1..The interrupt request for channel 12 is active
29760  */
29761 #define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
29762 
29763 #define DMA_INT_INT13_MASK                       (0x2000U)
29764 #define DMA_INT_INT13_SHIFT                      (13U)
29765 /*! INT13 - Interrupt Request 13
29766  *  0b0..The interrupt request for channel 13 is cleared
29767  *  0b1..The interrupt request for channel 13 is active
29768  */
29769 #define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
29770 
29771 #define DMA_INT_INT14_MASK                       (0x4000U)
29772 #define DMA_INT_INT14_SHIFT                      (14U)
29773 /*! INT14 - Interrupt Request 14
29774  *  0b0..The interrupt request for channel 14 is cleared
29775  *  0b1..The interrupt request for channel 14 is active
29776  */
29777 #define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
29778 
29779 #define DMA_INT_INT15_MASK                       (0x8000U)
29780 #define DMA_INT_INT15_SHIFT                      (15U)
29781 /*! INT15 - Interrupt Request 15
29782  *  0b0..The interrupt request for channel 15 is cleared
29783  *  0b1..The interrupt request for channel 15 is active
29784  */
29785 #define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
29786 
29787 #define DMA_INT_INT16_MASK                       (0x10000U)
29788 #define DMA_INT_INT16_SHIFT                      (16U)
29789 /*! INT16 - Interrupt Request 16
29790  *  0b0..The interrupt request for channel 16 is cleared
29791  *  0b1..The interrupt request for channel 16 is active
29792  */
29793 #define DMA_INT_INT16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
29794 
29795 #define DMA_INT_INT17_MASK                       (0x20000U)
29796 #define DMA_INT_INT17_SHIFT                      (17U)
29797 /*! INT17 - Interrupt Request 17
29798  *  0b0..The interrupt request for channel 17 is cleared
29799  *  0b1..The interrupt request for channel 17 is active
29800  */
29801 #define DMA_INT_INT17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
29802 
29803 #define DMA_INT_INT18_MASK                       (0x40000U)
29804 #define DMA_INT_INT18_SHIFT                      (18U)
29805 /*! INT18 - Interrupt Request 18
29806  *  0b0..The interrupt request for channel 18 is cleared
29807  *  0b1..The interrupt request for channel 18 is active
29808  */
29809 #define DMA_INT_INT18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
29810 
29811 #define DMA_INT_INT19_MASK                       (0x80000U)
29812 #define DMA_INT_INT19_SHIFT                      (19U)
29813 /*! INT19 - Interrupt Request 19
29814  *  0b0..The interrupt request for channel 19 is cleared
29815  *  0b1..The interrupt request for channel 19 is active
29816  */
29817 #define DMA_INT_INT19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
29818 
29819 #define DMA_INT_INT20_MASK                       (0x100000U)
29820 #define DMA_INT_INT20_SHIFT                      (20U)
29821 /*! INT20 - Interrupt Request 20
29822  *  0b0..The interrupt request for channel 20 is cleared
29823  *  0b1..The interrupt request for channel 20 is active
29824  */
29825 #define DMA_INT_INT20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
29826 
29827 #define DMA_INT_INT21_MASK                       (0x200000U)
29828 #define DMA_INT_INT21_SHIFT                      (21U)
29829 /*! INT21 - Interrupt Request 21
29830  *  0b0..The interrupt request for channel 21 is cleared
29831  *  0b1..The interrupt request for channel 21 is active
29832  */
29833 #define DMA_INT_INT21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
29834 
29835 #define DMA_INT_INT22_MASK                       (0x400000U)
29836 #define DMA_INT_INT22_SHIFT                      (22U)
29837 /*! INT22 - Interrupt Request 22
29838  *  0b0..The interrupt request for channel 22 is cleared
29839  *  0b1..The interrupt request for channel 22 is active
29840  */
29841 #define DMA_INT_INT22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
29842 
29843 #define DMA_INT_INT23_MASK                       (0x800000U)
29844 #define DMA_INT_INT23_SHIFT                      (23U)
29845 /*! INT23 - Interrupt Request 23
29846  *  0b0..The interrupt request for channel 23 is cleared
29847  *  0b1..The interrupt request for channel 23 is active
29848  */
29849 #define DMA_INT_INT23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
29850 
29851 #define DMA_INT_INT24_MASK                       (0x1000000U)
29852 #define DMA_INT_INT24_SHIFT                      (24U)
29853 /*! INT24 - Interrupt Request 24
29854  *  0b0..The interrupt request for channel 24 is cleared
29855  *  0b1..The interrupt request for channel 24 is active
29856  */
29857 #define DMA_INT_INT24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
29858 
29859 #define DMA_INT_INT25_MASK                       (0x2000000U)
29860 #define DMA_INT_INT25_SHIFT                      (25U)
29861 /*! INT25 - Interrupt Request 25
29862  *  0b0..The interrupt request for channel 25 is cleared
29863  *  0b1..The interrupt request for channel 25 is active
29864  */
29865 #define DMA_INT_INT25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
29866 
29867 #define DMA_INT_INT26_MASK                       (0x4000000U)
29868 #define DMA_INT_INT26_SHIFT                      (26U)
29869 /*! INT26 - Interrupt Request 26
29870  *  0b0..The interrupt request for channel 26 is cleared
29871  *  0b1..The interrupt request for channel 26 is active
29872  */
29873 #define DMA_INT_INT26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
29874 
29875 #define DMA_INT_INT27_MASK                       (0x8000000U)
29876 #define DMA_INT_INT27_SHIFT                      (27U)
29877 /*! INT27 - Interrupt Request 27
29878  *  0b0..The interrupt request for channel 27 is cleared
29879  *  0b1..The interrupt request for channel 27 is active
29880  */
29881 #define DMA_INT_INT27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
29882 
29883 #define DMA_INT_INT28_MASK                       (0x10000000U)
29884 #define DMA_INT_INT28_SHIFT                      (28U)
29885 /*! INT28 - Interrupt Request 28
29886  *  0b0..The interrupt request for channel 28 is cleared
29887  *  0b1..The interrupt request for channel 28 is active
29888  */
29889 #define DMA_INT_INT28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
29890 
29891 #define DMA_INT_INT29_MASK                       (0x20000000U)
29892 #define DMA_INT_INT29_SHIFT                      (29U)
29893 /*! INT29 - Interrupt Request 29
29894  *  0b0..The interrupt request for channel 29 is cleared
29895  *  0b1..The interrupt request for channel 29 is active
29896  */
29897 #define DMA_INT_INT29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
29898 
29899 #define DMA_INT_INT30_MASK                       (0x40000000U)
29900 #define DMA_INT_INT30_SHIFT                      (30U)
29901 /*! INT30 - Interrupt Request 30
29902  *  0b0..The interrupt request for channel 30 is cleared
29903  *  0b1..The interrupt request for channel 30 is active
29904  */
29905 #define DMA_INT_INT30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
29906 
29907 #define DMA_INT_INT31_MASK                       (0x80000000U)
29908 #define DMA_INT_INT31_SHIFT                      (31U)
29909 /*! INT31 - Interrupt Request 31
29910  *  0b0..The interrupt request for channel 31 is cleared
29911  *  0b1..The interrupt request for channel 31 is active
29912  */
29913 #define DMA_INT_INT31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
29914 /*! @} */
29915 
29916 /*! @name ERR - Error */
29917 /*! @{ */
29918 
29919 #define DMA_ERR_ERR0_MASK                        (0x1U)
29920 #define DMA_ERR_ERR0_SHIFT                       (0U)
29921 /*! ERR0 - Error In Channel 0
29922  *  0b0..No error in this channel has occurred
29923  *  0b1..An error in this channel has occurred
29924  */
29925 #define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
29926 
29927 #define DMA_ERR_ERR1_MASK                        (0x2U)
29928 #define DMA_ERR_ERR1_SHIFT                       (1U)
29929 /*! ERR1 - Error In Channel 1
29930  *  0b0..No error in this channel has occurred
29931  *  0b1..An error in this channel has occurred
29932  */
29933 #define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
29934 
29935 #define DMA_ERR_ERR2_MASK                        (0x4U)
29936 #define DMA_ERR_ERR2_SHIFT                       (2U)
29937 /*! ERR2 - Error In Channel 2
29938  *  0b0..No error in this channel has occurred
29939  *  0b1..An error in this channel has occurred
29940  */
29941 #define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
29942 
29943 #define DMA_ERR_ERR3_MASK                        (0x8U)
29944 #define DMA_ERR_ERR3_SHIFT                       (3U)
29945 /*! ERR3 - Error In Channel 3
29946  *  0b0..No error in this channel has occurred
29947  *  0b1..An error in this channel has occurred
29948  */
29949 #define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
29950 
29951 #define DMA_ERR_ERR4_MASK                        (0x10U)
29952 #define DMA_ERR_ERR4_SHIFT                       (4U)
29953 /*! ERR4 - Error In Channel 4
29954  *  0b0..No error in this channel has occurred
29955  *  0b1..An error in this channel has occurred
29956  */
29957 #define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
29958 
29959 #define DMA_ERR_ERR5_MASK                        (0x20U)
29960 #define DMA_ERR_ERR5_SHIFT                       (5U)
29961 /*! ERR5 - Error In Channel 5
29962  *  0b0..No error in this channel has occurred
29963  *  0b1..An error in this channel has occurred
29964  */
29965 #define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
29966 
29967 #define DMA_ERR_ERR6_MASK                        (0x40U)
29968 #define DMA_ERR_ERR6_SHIFT                       (6U)
29969 /*! ERR6 - Error In Channel 6
29970  *  0b0..No error in this channel has occurred
29971  *  0b1..An error in this channel has occurred
29972  */
29973 #define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
29974 
29975 #define DMA_ERR_ERR7_MASK                        (0x80U)
29976 #define DMA_ERR_ERR7_SHIFT                       (7U)
29977 /*! ERR7 - Error In Channel 7
29978  *  0b0..No error in this channel has occurred
29979  *  0b1..An error in this channel has occurred
29980  */
29981 #define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
29982 
29983 #define DMA_ERR_ERR8_MASK                        (0x100U)
29984 #define DMA_ERR_ERR8_SHIFT                       (8U)
29985 /*! ERR8 - Error In Channel 8
29986  *  0b0..No error in this channel has occurred
29987  *  0b1..An error in this channel has occurred
29988  */
29989 #define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
29990 
29991 #define DMA_ERR_ERR9_MASK                        (0x200U)
29992 #define DMA_ERR_ERR9_SHIFT                       (9U)
29993 /*! ERR9 - Error In Channel 9
29994  *  0b0..No error in this channel has occurred
29995  *  0b1..An error in this channel has occurred
29996  */
29997 #define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
29998 
29999 #define DMA_ERR_ERR10_MASK                       (0x400U)
30000 #define DMA_ERR_ERR10_SHIFT                      (10U)
30001 /*! ERR10 - Error In Channel 10
30002  *  0b0..No error in this channel has occurred
30003  *  0b1..An error in this channel has occurred
30004  */
30005 #define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
30006 
30007 #define DMA_ERR_ERR11_MASK                       (0x800U)
30008 #define DMA_ERR_ERR11_SHIFT                      (11U)
30009 /*! ERR11 - Error In Channel 11
30010  *  0b0..No error in this channel has occurred
30011  *  0b1..An error in this channel has occurred
30012  */
30013 #define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
30014 
30015 #define DMA_ERR_ERR12_MASK                       (0x1000U)
30016 #define DMA_ERR_ERR12_SHIFT                      (12U)
30017 /*! ERR12 - Error In Channel 12
30018  *  0b0..No error in this channel has occurred
30019  *  0b1..An error in this channel has occurred
30020  */
30021 #define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
30022 
30023 #define DMA_ERR_ERR13_MASK                       (0x2000U)
30024 #define DMA_ERR_ERR13_SHIFT                      (13U)
30025 /*! ERR13 - Error In Channel 13
30026  *  0b0..No error in this channel has occurred
30027  *  0b1..An error in this channel has occurred
30028  */
30029 #define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
30030 
30031 #define DMA_ERR_ERR14_MASK                       (0x4000U)
30032 #define DMA_ERR_ERR14_SHIFT                      (14U)
30033 /*! ERR14 - Error In Channel 14
30034  *  0b0..No error in this channel has occurred
30035  *  0b1..An error in this channel has occurred
30036  */
30037 #define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
30038 
30039 #define DMA_ERR_ERR15_MASK                       (0x8000U)
30040 #define DMA_ERR_ERR15_SHIFT                      (15U)
30041 /*! ERR15 - Error In Channel 15
30042  *  0b0..No error in this channel has occurred
30043  *  0b1..An error in this channel has occurred
30044  */
30045 #define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
30046 
30047 #define DMA_ERR_ERR16_MASK                       (0x10000U)
30048 #define DMA_ERR_ERR16_SHIFT                      (16U)
30049 /*! ERR16 - Error In Channel 16
30050  *  0b0..No error in this channel has occurred
30051  *  0b1..An error in this channel has occurred
30052  */
30053 #define DMA_ERR_ERR16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
30054 
30055 #define DMA_ERR_ERR17_MASK                       (0x20000U)
30056 #define DMA_ERR_ERR17_SHIFT                      (17U)
30057 /*! ERR17 - Error In Channel 17
30058  *  0b0..No error in this channel has occurred
30059  *  0b1..An error in this channel has occurred
30060  */
30061 #define DMA_ERR_ERR17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
30062 
30063 #define DMA_ERR_ERR18_MASK                       (0x40000U)
30064 #define DMA_ERR_ERR18_SHIFT                      (18U)
30065 /*! ERR18 - Error In Channel 18
30066  *  0b0..No error in this channel has occurred
30067  *  0b1..An error in this channel has occurred
30068  */
30069 #define DMA_ERR_ERR18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
30070 
30071 #define DMA_ERR_ERR19_MASK                       (0x80000U)
30072 #define DMA_ERR_ERR19_SHIFT                      (19U)
30073 /*! ERR19 - Error In Channel 19
30074  *  0b0..No error in this channel has occurred
30075  *  0b1..An error in this channel has occurred
30076  */
30077 #define DMA_ERR_ERR19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
30078 
30079 #define DMA_ERR_ERR20_MASK                       (0x100000U)
30080 #define DMA_ERR_ERR20_SHIFT                      (20U)
30081 /*! ERR20 - Error In Channel 20
30082  *  0b0..No error in this channel has occurred
30083  *  0b1..An error in this channel has occurred
30084  */
30085 #define DMA_ERR_ERR20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
30086 
30087 #define DMA_ERR_ERR21_MASK                       (0x200000U)
30088 #define DMA_ERR_ERR21_SHIFT                      (21U)
30089 /*! ERR21 - Error In Channel 21
30090  *  0b0..No error in this channel has occurred
30091  *  0b1..An error in this channel has occurred
30092  */
30093 #define DMA_ERR_ERR21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
30094 
30095 #define DMA_ERR_ERR22_MASK                       (0x400000U)
30096 #define DMA_ERR_ERR22_SHIFT                      (22U)
30097 /*! ERR22 - Error In Channel 22
30098  *  0b0..No error in this channel has occurred
30099  *  0b1..An error in this channel has occurred
30100  */
30101 #define DMA_ERR_ERR22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
30102 
30103 #define DMA_ERR_ERR23_MASK                       (0x800000U)
30104 #define DMA_ERR_ERR23_SHIFT                      (23U)
30105 /*! ERR23 - Error In Channel 23
30106  *  0b0..No error in this channel has occurred
30107  *  0b1..An error in this channel has occurred
30108  */
30109 #define DMA_ERR_ERR23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
30110 
30111 #define DMA_ERR_ERR24_MASK                       (0x1000000U)
30112 #define DMA_ERR_ERR24_SHIFT                      (24U)
30113 /*! ERR24 - Error In Channel 24
30114  *  0b0..No error in this channel has occurred
30115  *  0b1..An error in this channel has occurred
30116  */
30117 #define DMA_ERR_ERR24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
30118 
30119 #define DMA_ERR_ERR25_MASK                       (0x2000000U)
30120 #define DMA_ERR_ERR25_SHIFT                      (25U)
30121 /*! ERR25 - Error In Channel 25
30122  *  0b0..No error in this channel has occurred
30123  *  0b1..An error in this channel has occurred
30124  */
30125 #define DMA_ERR_ERR25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
30126 
30127 #define DMA_ERR_ERR26_MASK                       (0x4000000U)
30128 #define DMA_ERR_ERR26_SHIFT                      (26U)
30129 /*! ERR26 - Error In Channel 26
30130  *  0b0..No error in this channel has occurred
30131  *  0b1..An error in this channel has occurred
30132  */
30133 #define DMA_ERR_ERR26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
30134 
30135 #define DMA_ERR_ERR27_MASK                       (0x8000000U)
30136 #define DMA_ERR_ERR27_SHIFT                      (27U)
30137 /*! ERR27 - Error In Channel 27
30138  *  0b0..No error in this channel has occurred
30139  *  0b1..An error in this channel has occurred
30140  */
30141 #define DMA_ERR_ERR27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
30142 
30143 #define DMA_ERR_ERR28_MASK                       (0x10000000U)
30144 #define DMA_ERR_ERR28_SHIFT                      (28U)
30145 /*! ERR28 - Error In Channel 28
30146  *  0b0..No error in this channel has occurred
30147  *  0b1..An error in this channel has occurred
30148  */
30149 #define DMA_ERR_ERR28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
30150 
30151 #define DMA_ERR_ERR29_MASK                       (0x20000000U)
30152 #define DMA_ERR_ERR29_SHIFT                      (29U)
30153 /*! ERR29 - Error In Channel 29
30154  *  0b0..No error in this channel has occurred
30155  *  0b1..An error in this channel has occurred
30156  */
30157 #define DMA_ERR_ERR29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
30158 
30159 #define DMA_ERR_ERR30_MASK                       (0x40000000U)
30160 #define DMA_ERR_ERR30_SHIFT                      (30U)
30161 /*! ERR30 - Error In Channel 30
30162  *  0b0..No error in this channel has occurred
30163  *  0b1..An error in this channel has occurred
30164  */
30165 #define DMA_ERR_ERR30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
30166 
30167 #define DMA_ERR_ERR31_MASK                       (0x80000000U)
30168 #define DMA_ERR_ERR31_SHIFT                      (31U)
30169 /*! ERR31 - Error In Channel 31
30170  *  0b0..No error in this channel has occurred
30171  *  0b1..An error in this channel has occurred
30172  */
30173 #define DMA_ERR_ERR31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
30174 /*! @} */
30175 
30176 /*! @name HRS - Hardware Request Status */
30177 /*! @{ */
30178 
30179 #define DMA_HRS_HRS0_MASK                        (0x1U)
30180 #define DMA_HRS_HRS0_SHIFT                       (0U)
30181 /*! HRS0 - Hardware Request Status Channel 0
30182  *  0b0..A hardware service request for channel 0 is not present
30183  *  0b1..A hardware service request for channel 0 is present
30184  */
30185 #define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
30186 
30187 #define DMA_HRS_HRS1_MASK                        (0x2U)
30188 #define DMA_HRS_HRS1_SHIFT                       (1U)
30189 /*! HRS1 - Hardware Request Status Channel 1
30190  *  0b0..A hardware service request for channel 1 is not present
30191  *  0b1..A hardware service request for channel 1 is present
30192  */
30193 #define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
30194 
30195 #define DMA_HRS_HRS2_MASK                        (0x4U)
30196 #define DMA_HRS_HRS2_SHIFT                       (2U)
30197 /*! HRS2 - Hardware Request Status Channel 2
30198  *  0b0..A hardware service request for channel 2 is not present
30199  *  0b1..A hardware service request for channel 2 is present
30200  */
30201 #define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
30202 
30203 #define DMA_HRS_HRS3_MASK                        (0x8U)
30204 #define DMA_HRS_HRS3_SHIFT                       (3U)
30205 /*! HRS3 - Hardware Request Status Channel 3
30206  *  0b0..A hardware service request for channel 3 is not present
30207  *  0b1..A hardware service request for channel 3 is present
30208  */
30209 #define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
30210 
30211 #define DMA_HRS_HRS4_MASK                        (0x10U)
30212 #define DMA_HRS_HRS4_SHIFT                       (4U)
30213 /*! HRS4 - Hardware Request Status Channel 4
30214  *  0b0..A hardware service request for channel 4 is not present
30215  *  0b1..A hardware service request for channel 4 is present
30216  */
30217 #define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
30218 
30219 #define DMA_HRS_HRS5_MASK                        (0x20U)
30220 #define DMA_HRS_HRS5_SHIFT                       (5U)
30221 /*! HRS5 - Hardware Request Status Channel 5
30222  *  0b0..A hardware service request for channel 5 is not present
30223  *  0b1..A hardware service request for channel 5 is present
30224  */
30225 #define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
30226 
30227 #define DMA_HRS_HRS6_MASK                        (0x40U)
30228 #define DMA_HRS_HRS6_SHIFT                       (6U)
30229 /*! HRS6 - Hardware Request Status Channel 6
30230  *  0b0..A hardware service request for channel 6 is not present
30231  *  0b1..A hardware service request for channel 6 is present
30232  */
30233 #define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
30234 
30235 #define DMA_HRS_HRS7_MASK                        (0x80U)
30236 #define DMA_HRS_HRS7_SHIFT                       (7U)
30237 /*! HRS7 - Hardware Request Status Channel 7
30238  *  0b0..A hardware service request for channel 7 is not present
30239  *  0b1..A hardware service request for channel 7 is present
30240  */
30241 #define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
30242 
30243 #define DMA_HRS_HRS8_MASK                        (0x100U)
30244 #define DMA_HRS_HRS8_SHIFT                       (8U)
30245 /*! HRS8 - Hardware Request Status Channel 8
30246  *  0b0..A hardware service request for channel 8 is not present
30247  *  0b1..A hardware service request for channel 8 is present
30248  */
30249 #define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
30250 
30251 #define DMA_HRS_HRS9_MASK                        (0x200U)
30252 #define DMA_HRS_HRS9_SHIFT                       (9U)
30253 /*! HRS9 - Hardware Request Status Channel 9
30254  *  0b0..A hardware service request for channel 9 is not present
30255  *  0b1..A hardware service request for channel 9 is present
30256  */
30257 #define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
30258 
30259 #define DMA_HRS_HRS10_MASK                       (0x400U)
30260 #define DMA_HRS_HRS10_SHIFT                      (10U)
30261 /*! HRS10 - Hardware Request Status Channel 10
30262  *  0b0..A hardware service request for channel 10 is not present
30263  *  0b1..A hardware service request for channel 10 is present
30264  */
30265 #define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
30266 
30267 #define DMA_HRS_HRS11_MASK                       (0x800U)
30268 #define DMA_HRS_HRS11_SHIFT                      (11U)
30269 /*! HRS11 - Hardware Request Status Channel 11
30270  *  0b0..A hardware service request for channel 11 is not present
30271  *  0b1..A hardware service request for channel 11 is present
30272  */
30273 #define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
30274 
30275 #define DMA_HRS_HRS12_MASK                       (0x1000U)
30276 #define DMA_HRS_HRS12_SHIFT                      (12U)
30277 /*! HRS12 - Hardware Request Status Channel 12
30278  *  0b0..A hardware service request for channel 12 is not present
30279  *  0b1..A hardware service request for channel 12 is present
30280  */
30281 #define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
30282 
30283 #define DMA_HRS_HRS13_MASK                       (0x2000U)
30284 #define DMA_HRS_HRS13_SHIFT                      (13U)
30285 /*! HRS13 - Hardware Request Status Channel 13
30286  *  0b0..A hardware service request for channel 13 is not present
30287  *  0b1..A hardware service request for channel 13 is present
30288  */
30289 #define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
30290 
30291 #define DMA_HRS_HRS14_MASK                       (0x4000U)
30292 #define DMA_HRS_HRS14_SHIFT                      (14U)
30293 /*! HRS14 - Hardware Request Status Channel 14
30294  *  0b0..A hardware service request for channel 14 is not present
30295  *  0b1..A hardware service request for channel 14 is present
30296  */
30297 #define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
30298 
30299 #define DMA_HRS_HRS15_MASK                       (0x8000U)
30300 #define DMA_HRS_HRS15_SHIFT                      (15U)
30301 /*! HRS15 - Hardware Request Status Channel 15
30302  *  0b0..A hardware service request for channel 15 is not present
30303  *  0b1..A hardware service request for channel 15 is present
30304  */
30305 #define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
30306 
30307 #define DMA_HRS_HRS16_MASK                       (0x10000U)
30308 #define DMA_HRS_HRS16_SHIFT                      (16U)
30309 /*! HRS16 - Hardware Request Status Channel 16
30310  *  0b0..A hardware service request for channel 16 is not present
30311  *  0b1..A hardware service request for channel 16 is present
30312  */
30313 #define DMA_HRS_HRS16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
30314 
30315 #define DMA_HRS_HRS17_MASK                       (0x20000U)
30316 #define DMA_HRS_HRS17_SHIFT                      (17U)
30317 /*! HRS17 - Hardware Request Status Channel 17
30318  *  0b0..A hardware service request for channel 17 is not present
30319  *  0b1..A hardware service request for channel 17 is present
30320  */
30321 #define DMA_HRS_HRS17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
30322 
30323 #define DMA_HRS_HRS18_MASK                       (0x40000U)
30324 #define DMA_HRS_HRS18_SHIFT                      (18U)
30325 /*! HRS18 - Hardware Request Status Channel 18
30326  *  0b0..A hardware service request for channel 18 is not present
30327  *  0b1..A hardware service request for channel 18 is present
30328  */
30329 #define DMA_HRS_HRS18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
30330 
30331 #define DMA_HRS_HRS19_MASK                       (0x80000U)
30332 #define DMA_HRS_HRS19_SHIFT                      (19U)
30333 /*! HRS19 - Hardware Request Status Channel 19
30334  *  0b0..A hardware service request for channel 19 is not present
30335  *  0b1..A hardware service request for channel 19 is present
30336  */
30337 #define DMA_HRS_HRS19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
30338 
30339 #define DMA_HRS_HRS20_MASK                       (0x100000U)
30340 #define DMA_HRS_HRS20_SHIFT                      (20U)
30341 /*! HRS20 - Hardware Request Status Channel 20
30342  *  0b0..A hardware service request for channel 20 is not present
30343  *  0b1..A hardware service request for channel 20 is present
30344  */
30345 #define DMA_HRS_HRS20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
30346 
30347 #define DMA_HRS_HRS21_MASK                       (0x200000U)
30348 #define DMA_HRS_HRS21_SHIFT                      (21U)
30349 /*! HRS21 - Hardware Request Status Channel 21
30350  *  0b0..A hardware service request for channel 21 is not present
30351  *  0b1..A hardware service request for channel 21 is present
30352  */
30353 #define DMA_HRS_HRS21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
30354 
30355 #define DMA_HRS_HRS22_MASK                       (0x400000U)
30356 #define DMA_HRS_HRS22_SHIFT                      (22U)
30357 /*! HRS22 - Hardware Request Status Channel 22
30358  *  0b0..A hardware service request for channel 22 is not present
30359  *  0b1..A hardware service request for channel 22 is present
30360  */
30361 #define DMA_HRS_HRS22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
30362 
30363 #define DMA_HRS_HRS23_MASK                       (0x800000U)
30364 #define DMA_HRS_HRS23_SHIFT                      (23U)
30365 /*! HRS23 - Hardware Request Status Channel 23
30366  *  0b0..A hardware service request for channel 23 is not present
30367  *  0b1..A hardware service request for channel 23 is present
30368  */
30369 #define DMA_HRS_HRS23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
30370 
30371 #define DMA_HRS_HRS24_MASK                       (0x1000000U)
30372 #define DMA_HRS_HRS24_SHIFT                      (24U)
30373 /*! HRS24 - Hardware Request Status Channel 24
30374  *  0b0..A hardware service request for channel 24 is not present
30375  *  0b1..A hardware service request for channel 24 is present
30376  */
30377 #define DMA_HRS_HRS24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
30378 
30379 #define DMA_HRS_HRS25_MASK                       (0x2000000U)
30380 #define DMA_HRS_HRS25_SHIFT                      (25U)
30381 /*! HRS25 - Hardware Request Status Channel 25
30382  *  0b0..A hardware service request for channel 25 is not present
30383  *  0b1..A hardware service request for channel 25 is present
30384  */
30385 #define DMA_HRS_HRS25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
30386 
30387 #define DMA_HRS_HRS26_MASK                       (0x4000000U)
30388 #define DMA_HRS_HRS26_SHIFT                      (26U)
30389 /*! HRS26 - Hardware Request Status Channel 26
30390  *  0b0..A hardware service request for channel 26 is not present
30391  *  0b1..A hardware service request for channel 26 is present
30392  */
30393 #define DMA_HRS_HRS26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
30394 
30395 #define DMA_HRS_HRS27_MASK                       (0x8000000U)
30396 #define DMA_HRS_HRS27_SHIFT                      (27U)
30397 /*! HRS27 - Hardware Request Status Channel 27
30398  *  0b0..A hardware service request for channel 27 is not present
30399  *  0b1..A hardware service request for channel 27 is present
30400  */
30401 #define DMA_HRS_HRS27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
30402 
30403 #define DMA_HRS_HRS28_MASK                       (0x10000000U)
30404 #define DMA_HRS_HRS28_SHIFT                      (28U)
30405 /*! HRS28 - Hardware Request Status Channel 28
30406  *  0b0..A hardware service request for channel 28 is not present
30407  *  0b1..A hardware service request for channel 28 is present
30408  */
30409 #define DMA_HRS_HRS28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
30410 
30411 #define DMA_HRS_HRS29_MASK                       (0x20000000U)
30412 #define DMA_HRS_HRS29_SHIFT                      (29U)
30413 /*! HRS29 - Hardware Request Status Channel 29
30414  *  0b0..A hardware service request for channel 29 is not preset
30415  *  0b1..A hardware service request for channel 29 is present
30416  */
30417 #define DMA_HRS_HRS29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
30418 
30419 #define DMA_HRS_HRS30_MASK                       (0x40000000U)
30420 #define DMA_HRS_HRS30_SHIFT                      (30U)
30421 /*! HRS30 - Hardware Request Status Channel 30
30422  *  0b0..A hardware service request for channel 30 is not present
30423  *  0b1..A hardware service request for channel 30 is present
30424  */
30425 #define DMA_HRS_HRS30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
30426 
30427 #define DMA_HRS_HRS31_MASK                       (0x80000000U)
30428 #define DMA_HRS_HRS31_SHIFT                      (31U)
30429 /*! HRS31 - Hardware Request Status Channel 31
30430  *  0b0..A hardware service request for channel 31 is not present
30431  *  0b1..A hardware service request for channel 31 is present
30432  */
30433 #define DMA_HRS_HRS31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
30434 /*! @} */
30435 
30436 /*! @name EARS - Enable Asynchronous Request in Stop */
30437 /*! @{ */
30438 
30439 #define DMA_EARS_EDREQ_0_MASK                    (0x1U)
30440 #define DMA_EARS_EDREQ_0_SHIFT                   (0U)
30441 /*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
30442  *  0b0..Disable asynchronous DMA request for channel 0
30443  *  0b1..Enable asynchronous DMA request for channel 0
30444  */
30445 #define DMA_EARS_EDREQ_0(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
30446 
30447 #define DMA_EARS_EDREQ_1_MASK                    (0x2U)
30448 #define DMA_EARS_EDREQ_1_SHIFT                   (1U)
30449 /*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
30450  *  0b0..Disable asynchronous DMA request for channel 1
30451  *  0b1..Enable asynchronous DMA request for channel 1
30452  */
30453 #define DMA_EARS_EDREQ_1(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
30454 
30455 #define DMA_EARS_EDREQ_2_MASK                    (0x4U)
30456 #define DMA_EARS_EDREQ_2_SHIFT                   (2U)
30457 /*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
30458  *  0b0..Disable asynchronous DMA request for channel 2
30459  *  0b1..Enable asynchronous DMA request for channel 2
30460  */
30461 #define DMA_EARS_EDREQ_2(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
30462 
30463 #define DMA_EARS_EDREQ_3_MASK                    (0x8U)
30464 #define DMA_EARS_EDREQ_3_SHIFT                   (3U)
30465 /*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
30466  *  0b0..Disable asynchronous DMA request for channel 3
30467  *  0b1..Enable asynchronous DMA request for channel 3
30468  */
30469 #define DMA_EARS_EDREQ_3(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
30470 
30471 #define DMA_EARS_EDREQ_4_MASK                    (0x10U)
30472 #define DMA_EARS_EDREQ_4_SHIFT                   (4U)
30473 /*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4.
30474  *  0b0..Disable asynchronous DMA request for channel 4
30475  *  0b1..Enable asynchronous DMA request for channel 4
30476  */
30477 #define DMA_EARS_EDREQ_4(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
30478 
30479 #define DMA_EARS_EDREQ_5_MASK                    (0x20U)
30480 #define DMA_EARS_EDREQ_5_SHIFT                   (5U)
30481 /*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5.
30482  *  0b0..Disable asynchronous DMA request for channel 5
30483  *  0b1..Enable asynchronous DMA request for channel 5
30484  */
30485 #define DMA_EARS_EDREQ_5(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
30486 
30487 #define DMA_EARS_EDREQ_6_MASK                    (0x40U)
30488 #define DMA_EARS_EDREQ_6_SHIFT                   (6U)
30489 /*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6.
30490  *  0b0..Disable asynchronous DMA request for channel 6
30491  *  0b1..Enable asynchronous DMA request for channel 6
30492  */
30493 #define DMA_EARS_EDREQ_6(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
30494 
30495 #define DMA_EARS_EDREQ_7_MASK                    (0x80U)
30496 #define DMA_EARS_EDREQ_7_SHIFT                   (7U)
30497 /*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7.
30498  *  0b0..Disable asynchronous DMA request for channel 7
30499  *  0b1..Enable asynchronous DMA request for channel 7
30500  */
30501 #define DMA_EARS_EDREQ_7(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
30502 
30503 #define DMA_EARS_EDREQ_8_MASK                    (0x100U)
30504 #define DMA_EARS_EDREQ_8_SHIFT                   (8U)
30505 /*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8.
30506  *  0b0..Disable asynchronous DMA request for channel 8
30507  *  0b1..Enable asynchronous DMA request for channel 8
30508  */
30509 #define DMA_EARS_EDREQ_8(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
30510 
30511 #define DMA_EARS_EDREQ_9_MASK                    (0x200U)
30512 #define DMA_EARS_EDREQ_9_SHIFT                   (9U)
30513 /*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9.
30514  *  0b0..Disable asynchronous DMA request for channel 9
30515  *  0b1..Enable asynchronous DMA request for channel 9
30516  */
30517 #define DMA_EARS_EDREQ_9(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
30518 
30519 #define DMA_EARS_EDREQ_10_MASK                   (0x400U)
30520 #define DMA_EARS_EDREQ_10_SHIFT                  (10U)
30521 /*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10.
30522  *  0b0..Disable asynchronous DMA request for channel 10
30523  *  0b1..Enable asynchronous DMA request for channel 10
30524  */
30525 #define DMA_EARS_EDREQ_10(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
30526 
30527 #define DMA_EARS_EDREQ_11_MASK                   (0x800U)
30528 #define DMA_EARS_EDREQ_11_SHIFT                  (11U)
30529 /*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11.
30530  *  0b0..Disable asynchronous DMA request for channel 11
30531  *  0b1..Enable asynchronous DMA request for channel 11
30532  */
30533 #define DMA_EARS_EDREQ_11(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
30534 
30535 #define DMA_EARS_EDREQ_12_MASK                   (0x1000U)
30536 #define DMA_EARS_EDREQ_12_SHIFT                  (12U)
30537 /*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12.
30538  *  0b0..Disable asynchronous DMA request for channel 12
30539  *  0b1..Enable asynchronous DMA request for channel 12
30540  */
30541 #define DMA_EARS_EDREQ_12(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
30542 
30543 #define DMA_EARS_EDREQ_13_MASK                   (0x2000U)
30544 #define DMA_EARS_EDREQ_13_SHIFT                  (13U)
30545 /*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13.
30546  *  0b0..Disable asynchronous DMA request for channel 13
30547  *  0b1..Enable asynchronous DMA request for channel 13
30548  */
30549 #define DMA_EARS_EDREQ_13(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
30550 
30551 #define DMA_EARS_EDREQ_14_MASK                   (0x4000U)
30552 #define DMA_EARS_EDREQ_14_SHIFT                  (14U)
30553 /*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14.
30554  *  0b0..Disable asynchronous DMA request for channel 14
30555  *  0b1..Enable asynchronous DMA request for channel 14
30556  */
30557 #define DMA_EARS_EDREQ_14(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
30558 
30559 #define DMA_EARS_EDREQ_15_MASK                   (0x8000U)
30560 #define DMA_EARS_EDREQ_15_SHIFT                  (15U)
30561 /*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15.
30562  *  0b0..Disable asynchronous DMA request for channel 15
30563  *  0b1..Enable asynchronous DMA request for channel 15
30564  */
30565 #define DMA_EARS_EDREQ_15(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
30566 
30567 #define DMA_EARS_EDREQ_16_MASK                   (0x10000U)
30568 #define DMA_EARS_EDREQ_16_SHIFT                  (16U)
30569 /*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16.
30570  *  0b0..Disable asynchronous DMA request for channel 16
30571  *  0b1..Enable asynchronous DMA request for channel 16
30572  */
30573 #define DMA_EARS_EDREQ_16(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
30574 
30575 #define DMA_EARS_EDREQ_17_MASK                   (0x20000U)
30576 #define DMA_EARS_EDREQ_17_SHIFT                  (17U)
30577 /*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17.
30578  *  0b0..Disable asynchronous DMA request for channel 17
30579  *  0b1..Enable asynchronous DMA request for channel 17
30580  */
30581 #define DMA_EARS_EDREQ_17(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
30582 
30583 #define DMA_EARS_EDREQ_18_MASK                   (0x40000U)
30584 #define DMA_EARS_EDREQ_18_SHIFT                  (18U)
30585 /*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18.
30586  *  0b0..Disable asynchronous DMA request for channel 18
30587  *  0b1..Enable asynchronous DMA request for channel 18
30588  */
30589 #define DMA_EARS_EDREQ_18(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
30590 
30591 #define DMA_EARS_EDREQ_19_MASK                   (0x80000U)
30592 #define DMA_EARS_EDREQ_19_SHIFT                  (19U)
30593 /*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19.
30594  *  0b0..Disable asynchronous DMA request for channel 19
30595  *  0b1..Enable asynchronous DMA request for channel 19
30596  */
30597 #define DMA_EARS_EDREQ_19(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
30598 
30599 #define DMA_EARS_EDREQ_20_MASK                   (0x100000U)
30600 #define DMA_EARS_EDREQ_20_SHIFT                  (20U)
30601 /*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20.
30602  *  0b0..Disable asynchronous DMA request for channel 20
30603  *  0b1..Enable asynchronous DMA request for channel 20
30604  */
30605 #define DMA_EARS_EDREQ_20(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
30606 
30607 #define DMA_EARS_EDREQ_21_MASK                   (0x200000U)
30608 #define DMA_EARS_EDREQ_21_SHIFT                  (21U)
30609 /*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21.
30610  *  0b0..Disable asynchronous DMA request for channel 21
30611  *  0b1..Enable asynchronous DMA request for channel 21
30612  */
30613 #define DMA_EARS_EDREQ_21(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
30614 
30615 #define DMA_EARS_EDREQ_22_MASK                   (0x400000U)
30616 #define DMA_EARS_EDREQ_22_SHIFT                  (22U)
30617 /*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22.
30618  *  0b0..Disable asynchronous DMA request for channel 22
30619  *  0b1..Enable asynchronous DMA request for channel 22
30620  */
30621 #define DMA_EARS_EDREQ_22(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
30622 
30623 #define DMA_EARS_EDREQ_23_MASK                   (0x800000U)
30624 #define DMA_EARS_EDREQ_23_SHIFT                  (23U)
30625 /*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23.
30626  *  0b0..Disable asynchronous DMA request for channel 23
30627  *  0b1..Enable asynchronous DMA request for channel 23
30628  */
30629 #define DMA_EARS_EDREQ_23(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
30630 
30631 #define DMA_EARS_EDREQ_24_MASK                   (0x1000000U)
30632 #define DMA_EARS_EDREQ_24_SHIFT                  (24U)
30633 /*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24.
30634  *  0b0..Disable asynchronous DMA request for channel 24
30635  *  0b1..Enable asynchronous DMA request for channel 24
30636  */
30637 #define DMA_EARS_EDREQ_24(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
30638 
30639 #define DMA_EARS_EDREQ_25_MASK                   (0x2000000U)
30640 #define DMA_EARS_EDREQ_25_SHIFT                  (25U)
30641 /*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25.
30642  *  0b0..Disable asynchronous DMA request for channel 25
30643  *  0b1..Enable asynchronous DMA request for channel 25
30644  */
30645 #define DMA_EARS_EDREQ_25(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
30646 
30647 #define DMA_EARS_EDREQ_26_MASK                   (0x4000000U)
30648 #define DMA_EARS_EDREQ_26_SHIFT                  (26U)
30649 /*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26.
30650  *  0b0..Disable asynchronous DMA request for channel 26
30651  *  0b1..Enable asynchronous DMA request for channel 26
30652  */
30653 #define DMA_EARS_EDREQ_26(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
30654 
30655 #define DMA_EARS_EDREQ_27_MASK                   (0x8000000U)
30656 #define DMA_EARS_EDREQ_27_SHIFT                  (27U)
30657 /*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27.
30658  *  0b0..Disable asynchronous DMA request for channel 27
30659  *  0b1..Enable asynchronous DMA request for channel 27
30660  */
30661 #define DMA_EARS_EDREQ_27(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
30662 
30663 #define DMA_EARS_EDREQ_28_MASK                   (0x10000000U)
30664 #define DMA_EARS_EDREQ_28_SHIFT                  (28U)
30665 /*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28.
30666  *  0b0..Disable asynchronous DMA request for channel 28
30667  *  0b1..Enable asynchronous DMA request for channel 28
30668  */
30669 #define DMA_EARS_EDREQ_28(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
30670 
30671 #define DMA_EARS_EDREQ_29_MASK                   (0x20000000U)
30672 #define DMA_EARS_EDREQ_29_SHIFT                  (29U)
30673 /*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29.
30674  *  0b0..Disable asynchronous DMA request for channel 29
30675  *  0b1..Enable asynchronous DMA request for channel 29
30676  */
30677 #define DMA_EARS_EDREQ_29(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
30678 
30679 #define DMA_EARS_EDREQ_30_MASK                   (0x40000000U)
30680 #define DMA_EARS_EDREQ_30_SHIFT                  (30U)
30681 /*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30.
30682  *  0b0..Disable asynchronous DMA request for channel 30
30683  *  0b1..Enable asynchronous DMA request for channel 30
30684  */
30685 #define DMA_EARS_EDREQ_30(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
30686 
30687 #define DMA_EARS_EDREQ_31_MASK                   (0x80000000U)
30688 #define DMA_EARS_EDREQ_31_SHIFT                  (31U)
30689 /*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31.
30690  *  0b0..Disable asynchronous DMA request for channel 31
30691  *  0b1..Enable asynchronous DMA request for channel 31
30692  */
30693 #define DMA_EARS_EDREQ_31(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
30694 /*! @} */
30695 
30696 /*! @name DCHPRI3 - Channel Priority */
30697 /*! @{ */
30698 
30699 #define DMA_DCHPRI3_CHPRI_MASK                   (0xFU)
30700 #define DMA_DCHPRI3_CHPRI_SHIFT                  (0U)
30701 /*! CHPRI - Channel n Arbitration Priority */
30702 #define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
30703 
30704 #define DMA_DCHPRI3_GRPPRI_MASK                  (0x30U)
30705 #define DMA_DCHPRI3_GRPPRI_SHIFT                 (4U)
30706 /*! GRPPRI - Channel n Current Group Priority */
30707 #define DMA_DCHPRI3_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
30708 
30709 #define DMA_DCHPRI3_DPA_MASK                     (0x40U)
30710 #define DMA_DCHPRI3_DPA_SHIFT                    (6U)
30711 /*! DPA - Disable Preempt Ability. This field resets to 0.
30712  *  0b0..Channel n can suspend a lower priority channel
30713  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
30714  */
30715 #define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
30716 
30717 #define DMA_DCHPRI3_ECP_MASK                     (0x80U)
30718 #define DMA_DCHPRI3_ECP_SHIFT                    (7U)
30719 /*! ECP - Enable Channel Preemption. This field resets to 0.
30720  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
30721  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
30722  */
30723 #define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
30724 /*! @} */
30725 
30726 /*! @name DCHPRI2 - Channel Priority */
30727 /*! @{ */
30728 
30729 #define DMA_DCHPRI2_CHPRI_MASK                   (0xFU)
30730 #define DMA_DCHPRI2_CHPRI_SHIFT                  (0U)
30731 /*! CHPRI - Channel n Arbitration Priority */
30732 #define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
30733 
30734 #define DMA_DCHPRI2_GRPPRI_MASK                  (0x30U)
30735 #define DMA_DCHPRI2_GRPPRI_SHIFT                 (4U)
30736 /*! GRPPRI - Channel n Current Group Priority */
30737 #define DMA_DCHPRI2_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
30738 
30739 #define DMA_DCHPRI2_DPA_MASK                     (0x40U)
30740 #define DMA_DCHPRI2_DPA_SHIFT                    (6U)
30741 /*! DPA - Disable Preempt Ability. This field resets to 0.
30742  *  0b0..Channel n can suspend a lower priority channel
30743  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
30744  */
30745 #define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
30746 
30747 #define DMA_DCHPRI2_ECP_MASK                     (0x80U)
30748 #define DMA_DCHPRI2_ECP_SHIFT                    (7U)
30749 /*! ECP - Enable Channel Preemption. This field resets to 0.
30750  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
30751  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
30752  */
30753 #define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
30754 /*! @} */
30755 
30756 /*! @name DCHPRI1 - Channel Priority */
30757 /*! @{ */
30758 
30759 #define DMA_DCHPRI1_CHPRI_MASK                   (0xFU)
30760 #define DMA_DCHPRI1_CHPRI_SHIFT                  (0U)
30761 /*! CHPRI - Channel n Arbitration Priority */
30762 #define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
30763 
30764 #define DMA_DCHPRI1_GRPPRI_MASK                  (0x30U)
30765 #define DMA_DCHPRI1_GRPPRI_SHIFT                 (4U)
30766 /*! GRPPRI - Channel n Current Group Priority */
30767 #define DMA_DCHPRI1_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
30768 
30769 #define DMA_DCHPRI1_DPA_MASK                     (0x40U)
30770 #define DMA_DCHPRI1_DPA_SHIFT                    (6U)
30771 /*! DPA - Disable Preempt Ability. This field resets to 0.
30772  *  0b0..Channel n can suspend a lower priority channel
30773  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
30774  */
30775 #define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
30776 
30777 #define DMA_DCHPRI1_ECP_MASK                     (0x80U)
30778 #define DMA_DCHPRI1_ECP_SHIFT                    (7U)
30779 /*! ECP - Enable Channel Preemption. This field resets to 0.
30780  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
30781  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
30782  */
30783 #define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
30784 /*! @} */
30785 
30786 /*! @name DCHPRI0 - Channel Priority */
30787 /*! @{ */
30788 
30789 #define DMA_DCHPRI0_CHPRI_MASK                   (0xFU)
30790 #define DMA_DCHPRI0_CHPRI_SHIFT                  (0U)
30791 /*! CHPRI - Channel n Arbitration Priority */
30792 #define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
30793 
30794 #define DMA_DCHPRI0_GRPPRI_MASK                  (0x30U)
30795 #define DMA_DCHPRI0_GRPPRI_SHIFT                 (4U)
30796 /*! GRPPRI - Channel n Current Group Priority */
30797 #define DMA_DCHPRI0_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
30798 
30799 #define DMA_DCHPRI0_DPA_MASK                     (0x40U)
30800 #define DMA_DCHPRI0_DPA_SHIFT                    (6U)
30801 /*! DPA - Disable Preempt Ability. This field resets to 0.
30802  *  0b0..Channel n can suspend a lower priority channel
30803  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
30804  */
30805 #define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
30806 
30807 #define DMA_DCHPRI0_ECP_MASK                     (0x80U)
30808 #define DMA_DCHPRI0_ECP_SHIFT                    (7U)
30809 /*! ECP - Enable Channel Preemption. This field resets to 0.
30810  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
30811  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
30812  */
30813 #define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
30814 /*! @} */
30815 
30816 /*! @name DCHPRI7 - Channel Priority */
30817 /*! @{ */
30818 
30819 #define DMA_DCHPRI7_CHPRI_MASK                   (0xFU)
30820 #define DMA_DCHPRI7_CHPRI_SHIFT                  (0U)
30821 /*! CHPRI - Channel n Arbitration Priority */
30822 #define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
30823 
30824 #define DMA_DCHPRI7_GRPPRI_MASK                  (0x30U)
30825 #define DMA_DCHPRI7_GRPPRI_SHIFT                 (4U)
30826 /*! GRPPRI - Channel n Current Group Priority */
30827 #define DMA_DCHPRI7_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
30828 
30829 #define DMA_DCHPRI7_DPA_MASK                     (0x40U)
30830 #define DMA_DCHPRI7_DPA_SHIFT                    (6U)
30831 /*! DPA - Disable Preempt Ability. This field resets to 0.
30832  *  0b0..Channel n can suspend a lower priority channel
30833  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
30834  */
30835 #define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
30836 
30837 #define DMA_DCHPRI7_ECP_MASK                     (0x80U)
30838 #define DMA_DCHPRI7_ECP_SHIFT                    (7U)
30839 /*! ECP - Enable Channel Preemption. This field resets to 0.
30840  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
30841  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
30842  */
30843 #define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
30844 /*! @} */
30845 
30846 /*! @name DCHPRI6 - Channel Priority */
30847 /*! @{ */
30848 
30849 #define DMA_DCHPRI6_CHPRI_MASK                   (0xFU)
30850 #define DMA_DCHPRI6_CHPRI_SHIFT                  (0U)
30851 /*! CHPRI - Channel n Arbitration Priority */
30852 #define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
30853 
30854 #define DMA_DCHPRI6_GRPPRI_MASK                  (0x30U)
30855 #define DMA_DCHPRI6_GRPPRI_SHIFT                 (4U)
30856 /*! GRPPRI - Channel n Current Group Priority */
30857 #define DMA_DCHPRI6_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
30858 
30859 #define DMA_DCHPRI6_DPA_MASK                     (0x40U)
30860 #define DMA_DCHPRI6_DPA_SHIFT                    (6U)
30861 /*! DPA - Disable Preempt Ability. This field resets to 0.
30862  *  0b0..Channel n can suspend a lower priority channel
30863  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
30864  */
30865 #define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
30866 
30867 #define DMA_DCHPRI6_ECP_MASK                     (0x80U)
30868 #define DMA_DCHPRI6_ECP_SHIFT                    (7U)
30869 /*! ECP - Enable Channel Preemption. This field resets to 0.
30870  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
30871  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
30872  */
30873 #define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
30874 /*! @} */
30875 
30876 /*! @name DCHPRI5 - Channel Priority */
30877 /*! @{ */
30878 
30879 #define DMA_DCHPRI5_CHPRI_MASK                   (0xFU)
30880 #define DMA_DCHPRI5_CHPRI_SHIFT                  (0U)
30881 /*! CHPRI - Channel n Arbitration Priority */
30882 #define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
30883 
30884 #define DMA_DCHPRI5_GRPPRI_MASK                  (0x30U)
30885 #define DMA_DCHPRI5_GRPPRI_SHIFT                 (4U)
30886 /*! GRPPRI - Channel n Current Group Priority */
30887 #define DMA_DCHPRI5_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
30888 
30889 #define DMA_DCHPRI5_DPA_MASK                     (0x40U)
30890 #define DMA_DCHPRI5_DPA_SHIFT                    (6U)
30891 /*! DPA - Disable Preempt Ability. This field resets to 0.
30892  *  0b0..Channel n can suspend a lower priority channel
30893  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
30894  */
30895 #define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
30896 
30897 #define DMA_DCHPRI5_ECP_MASK                     (0x80U)
30898 #define DMA_DCHPRI5_ECP_SHIFT                    (7U)
30899 /*! ECP - Enable Channel Preemption. This field resets to 0.
30900  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
30901  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
30902  */
30903 #define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
30904 /*! @} */
30905 
30906 /*! @name DCHPRI4 - Channel Priority */
30907 /*! @{ */
30908 
30909 #define DMA_DCHPRI4_CHPRI_MASK                   (0xFU)
30910 #define DMA_DCHPRI4_CHPRI_SHIFT                  (0U)
30911 /*! CHPRI - Channel n Arbitration Priority */
30912 #define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
30913 
30914 #define DMA_DCHPRI4_GRPPRI_MASK                  (0x30U)
30915 #define DMA_DCHPRI4_GRPPRI_SHIFT                 (4U)
30916 /*! GRPPRI - Channel n Current Group Priority */
30917 #define DMA_DCHPRI4_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
30918 
30919 #define DMA_DCHPRI4_DPA_MASK                     (0x40U)
30920 #define DMA_DCHPRI4_DPA_SHIFT                    (6U)
30921 /*! DPA - Disable Preempt Ability. This field resets to 0.
30922  *  0b0..Channel n can suspend a lower priority channel
30923  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
30924  */
30925 #define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
30926 
30927 #define DMA_DCHPRI4_ECP_MASK                     (0x80U)
30928 #define DMA_DCHPRI4_ECP_SHIFT                    (7U)
30929 /*! ECP - Enable Channel Preemption. This field resets to 0.
30930  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
30931  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
30932  */
30933 #define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
30934 /*! @} */
30935 
30936 /*! @name DCHPRI11 - Channel Priority */
30937 /*! @{ */
30938 
30939 #define DMA_DCHPRI11_CHPRI_MASK                  (0xFU)
30940 #define DMA_DCHPRI11_CHPRI_SHIFT                 (0U)
30941 /*! CHPRI - Channel n Arbitration Priority */
30942 #define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
30943 
30944 #define DMA_DCHPRI11_GRPPRI_MASK                 (0x30U)
30945 #define DMA_DCHPRI11_GRPPRI_SHIFT                (4U)
30946 /*! GRPPRI - Channel n Current Group Priority */
30947 #define DMA_DCHPRI11_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
30948 
30949 #define DMA_DCHPRI11_DPA_MASK                    (0x40U)
30950 #define DMA_DCHPRI11_DPA_SHIFT                   (6U)
30951 /*! DPA - Disable Preempt Ability. This field resets to 0.
30952  *  0b0..Channel n can suspend a lower priority channel
30953  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
30954  */
30955 #define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
30956 
30957 #define DMA_DCHPRI11_ECP_MASK                    (0x80U)
30958 #define DMA_DCHPRI11_ECP_SHIFT                   (7U)
30959 /*! ECP - Enable Channel Preemption. This field resets to 0.
30960  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
30961  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
30962  */
30963 #define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
30964 /*! @} */
30965 
30966 /*! @name DCHPRI10 - Channel Priority */
30967 /*! @{ */
30968 
30969 #define DMA_DCHPRI10_CHPRI_MASK                  (0xFU)
30970 #define DMA_DCHPRI10_CHPRI_SHIFT                 (0U)
30971 /*! CHPRI - Channel n Arbitration Priority */
30972 #define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
30973 
30974 #define DMA_DCHPRI10_GRPPRI_MASK                 (0x30U)
30975 #define DMA_DCHPRI10_GRPPRI_SHIFT                (4U)
30976 /*! GRPPRI - Channel n Current Group Priority */
30977 #define DMA_DCHPRI10_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
30978 
30979 #define DMA_DCHPRI10_DPA_MASK                    (0x40U)
30980 #define DMA_DCHPRI10_DPA_SHIFT                   (6U)
30981 /*! DPA - Disable Preempt Ability. This field resets to 0.
30982  *  0b0..Channel n can suspend a lower priority channel
30983  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
30984  */
30985 #define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
30986 
30987 #define DMA_DCHPRI10_ECP_MASK                    (0x80U)
30988 #define DMA_DCHPRI10_ECP_SHIFT                   (7U)
30989 /*! ECP - Enable Channel Preemption. This field resets to 0.
30990  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
30991  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
30992  */
30993 #define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
30994 /*! @} */
30995 
30996 /*! @name DCHPRI9 - Channel Priority */
30997 /*! @{ */
30998 
30999 #define DMA_DCHPRI9_CHPRI_MASK                   (0xFU)
31000 #define DMA_DCHPRI9_CHPRI_SHIFT                  (0U)
31001 /*! CHPRI - Channel n Arbitration Priority */
31002 #define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
31003 
31004 #define DMA_DCHPRI9_GRPPRI_MASK                  (0x30U)
31005 #define DMA_DCHPRI9_GRPPRI_SHIFT                 (4U)
31006 /*! GRPPRI - Channel n Current Group Priority */
31007 #define DMA_DCHPRI9_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
31008 
31009 #define DMA_DCHPRI9_DPA_MASK                     (0x40U)
31010 #define DMA_DCHPRI9_DPA_SHIFT                    (6U)
31011 /*! DPA - Disable Preempt Ability. This field resets to 0.
31012  *  0b0..Channel n can suspend a lower priority channel
31013  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31014  */
31015 #define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
31016 
31017 #define DMA_DCHPRI9_ECP_MASK                     (0x80U)
31018 #define DMA_DCHPRI9_ECP_SHIFT                    (7U)
31019 /*! ECP - Enable Channel Preemption. This field resets to 0.
31020  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31021  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31022  */
31023 #define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
31024 /*! @} */
31025 
31026 /*! @name DCHPRI8 - Channel Priority */
31027 /*! @{ */
31028 
31029 #define DMA_DCHPRI8_CHPRI_MASK                   (0xFU)
31030 #define DMA_DCHPRI8_CHPRI_SHIFT                  (0U)
31031 /*! CHPRI - Channel n Arbitration Priority */
31032 #define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
31033 
31034 #define DMA_DCHPRI8_GRPPRI_MASK                  (0x30U)
31035 #define DMA_DCHPRI8_GRPPRI_SHIFT                 (4U)
31036 /*! GRPPRI - Channel n Current Group Priority */
31037 #define DMA_DCHPRI8_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
31038 
31039 #define DMA_DCHPRI8_DPA_MASK                     (0x40U)
31040 #define DMA_DCHPRI8_DPA_SHIFT                    (6U)
31041 /*! DPA - Disable Preempt Ability. This field resets to 0.
31042  *  0b0..Channel n can suspend a lower priority channel
31043  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31044  */
31045 #define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
31046 
31047 #define DMA_DCHPRI8_ECP_MASK                     (0x80U)
31048 #define DMA_DCHPRI8_ECP_SHIFT                    (7U)
31049 /*! ECP - Enable Channel Preemption. This field resets to 0.
31050  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31051  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31052  */
31053 #define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
31054 /*! @} */
31055 
31056 /*! @name DCHPRI15 - Channel Priority */
31057 /*! @{ */
31058 
31059 #define DMA_DCHPRI15_CHPRI_MASK                  (0xFU)
31060 #define DMA_DCHPRI15_CHPRI_SHIFT                 (0U)
31061 /*! CHPRI - Channel n Arbitration Priority */
31062 #define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
31063 
31064 #define DMA_DCHPRI15_GRPPRI_MASK                 (0x30U)
31065 #define DMA_DCHPRI15_GRPPRI_SHIFT                (4U)
31066 /*! GRPPRI - Channel n Current Group Priority */
31067 #define DMA_DCHPRI15_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
31068 
31069 #define DMA_DCHPRI15_DPA_MASK                    (0x40U)
31070 #define DMA_DCHPRI15_DPA_SHIFT                   (6U)
31071 /*! DPA - Disable Preempt Ability. This field resets to 0.
31072  *  0b0..Channel n can suspend a lower priority channel
31073  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31074  */
31075 #define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
31076 
31077 #define DMA_DCHPRI15_ECP_MASK                    (0x80U)
31078 #define DMA_DCHPRI15_ECP_SHIFT                   (7U)
31079 /*! ECP - Enable Channel Preemption. This field resets to 0.
31080  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31081  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31082  */
31083 #define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
31084 /*! @} */
31085 
31086 /*! @name DCHPRI14 - Channel Priority */
31087 /*! @{ */
31088 
31089 #define DMA_DCHPRI14_CHPRI_MASK                  (0xFU)
31090 #define DMA_DCHPRI14_CHPRI_SHIFT                 (0U)
31091 /*! CHPRI - Channel n Arbitration Priority */
31092 #define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
31093 
31094 #define DMA_DCHPRI14_GRPPRI_MASK                 (0x30U)
31095 #define DMA_DCHPRI14_GRPPRI_SHIFT                (4U)
31096 /*! GRPPRI - Channel n Current Group Priority */
31097 #define DMA_DCHPRI14_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
31098 
31099 #define DMA_DCHPRI14_DPA_MASK                    (0x40U)
31100 #define DMA_DCHPRI14_DPA_SHIFT                   (6U)
31101 /*! DPA - Disable Preempt Ability. This field resets to 0.
31102  *  0b0..Channel n can suspend a lower priority channel
31103  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31104  */
31105 #define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
31106 
31107 #define DMA_DCHPRI14_ECP_MASK                    (0x80U)
31108 #define DMA_DCHPRI14_ECP_SHIFT                   (7U)
31109 /*! ECP - Enable Channel Preemption. This field resets to 0.
31110  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31111  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31112  */
31113 #define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
31114 /*! @} */
31115 
31116 /*! @name DCHPRI13 - Channel Priority */
31117 /*! @{ */
31118 
31119 #define DMA_DCHPRI13_CHPRI_MASK                  (0xFU)
31120 #define DMA_DCHPRI13_CHPRI_SHIFT                 (0U)
31121 /*! CHPRI - Channel n Arbitration Priority */
31122 #define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
31123 
31124 #define DMA_DCHPRI13_GRPPRI_MASK                 (0x30U)
31125 #define DMA_DCHPRI13_GRPPRI_SHIFT                (4U)
31126 /*! GRPPRI - Channel n Current Group Priority */
31127 #define DMA_DCHPRI13_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
31128 
31129 #define DMA_DCHPRI13_DPA_MASK                    (0x40U)
31130 #define DMA_DCHPRI13_DPA_SHIFT                   (6U)
31131 /*! DPA - Disable Preempt Ability. This field resets to 0.
31132  *  0b0..Channel n can suspend a lower priority channel
31133  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31134  */
31135 #define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
31136 
31137 #define DMA_DCHPRI13_ECP_MASK                    (0x80U)
31138 #define DMA_DCHPRI13_ECP_SHIFT                   (7U)
31139 /*! ECP - Enable Channel Preemption. This field resets to 0.
31140  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31141  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31142  */
31143 #define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
31144 /*! @} */
31145 
31146 /*! @name DCHPRI12 - Channel Priority */
31147 /*! @{ */
31148 
31149 #define DMA_DCHPRI12_CHPRI_MASK                  (0xFU)
31150 #define DMA_DCHPRI12_CHPRI_SHIFT                 (0U)
31151 /*! CHPRI - Channel n Arbitration Priority */
31152 #define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
31153 
31154 #define DMA_DCHPRI12_GRPPRI_MASK                 (0x30U)
31155 #define DMA_DCHPRI12_GRPPRI_SHIFT                (4U)
31156 /*! GRPPRI - Channel n Current Group Priority */
31157 #define DMA_DCHPRI12_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
31158 
31159 #define DMA_DCHPRI12_DPA_MASK                    (0x40U)
31160 #define DMA_DCHPRI12_DPA_SHIFT                   (6U)
31161 /*! DPA - Disable Preempt Ability. This field resets to 0.
31162  *  0b0..Channel n can suspend a lower priority channel
31163  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31164  */
31165 #define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
31166 
31167 #define DMA_DCHPRI12_ECP_MASK                    (0x80U)
31168 #define DMA_DCHPRI12_ECP_SHIFT                   (7U)
31169 /*! ECP - Enable Channel Preemption. This field resets to 0.
31170  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31171  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31172  */
31173 #define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
31174 /*! @} */
31175 
31176 /*! @name DCHPRI19 - Channel Priority */
31177 /*! @{ */
31178 
31179 #define DMA_DCHPRI19_CHPRI_MASK                  (0xFU)
31180 #define DMA_DCHPRI19_CHPRI_SHIFT                 (0U)
31181 /*! CHPRI - Channel n Arbitration Priority */
31182 #define DMA_DCHPRI19_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
31183 
31184 #define DMA_DCHPRI19_GRPPRI_MASK                 (0x30U)
31185 #define DMA_DCHPRI19_GRPPRI_SHIFT                (4U)
31186 /*! GRPPRI - Channel n Current Group Priority */
31187 #define DMA_DCHPRI19_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
31188 
31189 #define DMA_DCHPRI19_DPA_MASK                    (0x40U)
31190 #define DMA_DCHPRI19_DPA_SHIFT                   (6U)
31191 /*! DPA - Disable Preempt Ability. This field resets to 0.
31192  *  0b0..Channel n can suspend a lower priority channel
31193  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31194  */
31195 #define DMA_DCHPRI19_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
31196 
31197 #define DMA_DCHPRI19_ECP_MASK                    (0x80U)
31198 #define DMA_DCHPRI19_ECP_SHIFT                   (7U)
31199 /*! ECP - Enable Channel Preemption. This field resets to 0.
31200  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31201  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31202  */
31203 #define DMA_DCHPRI19_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
31204 /*! @} */
31205 
31206 /*! @name DCHPRI18 - Channel Priority */
31207 /*! @{ */
31208 
31209 #define DMA_DCHPRI18_CHPRI_MASK                  (0xFU)
31210 #define DMA_DCHPRI18_CHPRI_SHIFT                 (0U)
31211 /*! CHPRI - Channel n Arbitration Priority */
31212 #define DMA_DCHPRI18_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
31213 
31214 #define DMA_DCHPRI18_GRPPRI_MASK                 (0x30U)
31215 #define DMA_DCHPRI18_GRPPRI_SHIFT                (4U)
31216 /*! GRPPRI - Channel n Current Group Priority */
31217 #define DMA_DCHPRI18_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
31218 
31219 #define DMA_DCHPRI18_DPA_MASK                    (0x40U)
31220 #define DMA_DCHPRI18_DPA_SHIFT                   (6U)
31221 /*! DPA - Disable Preempt Ability. This field resets to 0.
31222  *  0b0..Channel n can suspend a lower priority channel
31223  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31224  */
31225 #define DMA_DCHPRI18_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
31226 
31227 #define DMA_DCHPRI18_ECP_MASK                    (0x80U)
31228 #define DMA_DCHPRI18_ECP_SHIFT                   (7U)
31229 /*! ECP - Enable Channel Preemption. This field resets to 0.
31230  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31231  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31232  */
31233 #define DMA_DCHPRI18_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
31234 /*! @} */
31235 
31236 /*! @name DCHPRI17 - Channel Priority */
31237 /*! @{ */
31238 
31239 #define DMA_DCHPRI17_CHPRI_MASK                  (0xFU)
31240 #define DMA_DCHPRI17_CHPRI_SHIFT                 (0U)
31241 /*! CHPRI - Channel n Arbitration Priority */
31242 #define DMA_DCHPRI17_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
31243 
31244 #define DMA_DCHPRI17_GRPPRI_MASK                 (0x30U)
31245 #define DMA_DCHPRI17_GRPPRI_SHIFT                (4U)
31246 /*! GRPPRI - Channel n Current Group Priority */
31247 #define DMA_DCHPRI17_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
31248 
31249 #define DMA_DCHPRI17_DPA_MASK                    (0x40U)
31250 #define DMA_DCHPRI17_DPA_SHIFT                   (6U)
31251 /*! DPA - Disable Preempt Ability. This field resets to 0.
31252  *  0b0..Channel n can suspend a lower priority channel
31253  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31254  */
31255 #define DMA_DCHPRI17_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
31256 
31257 #define DMA_DCHPRI17_ECP_MASK                    (0x80U)
31258 #define DMA_DCHPRI17_ECP_SHIFT                   (7U)
31259 /*! ECP - Enable Channel Preemption. This field resets to 0.
31260  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31261  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31262  */
31263 #define DMA_DCHPRI17_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
31264 /*! @} */
31265 
31266 /*! @name DCHPRI16 - Channel Priority */
31267 /*! @{ */
31268 
31269 #define DMA_DCHPRI16_CHPRI_MASK                  (0xFU)
31270 #define DMA_DCHPRI16_CHPRI_SHIFT                 (0U)
31271 /*! CHPRI - Channel n Arbitration Priority */
31272 #define DMA_DCHPRI16_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
31273 
31274 #define DMA_DCHPRI16_GRPPRI_MASK                 (0x30U)
31275 #define DMA_DCHPRI16_GRPPRI_SHIFT                (4U)
31276 /*! GRPPRI - Channel n Current Group Priority */
31277 #define DMA_DCHPRI16_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
31278 
31279 #define DMA_DCHPRI16_DPA_MASK                    (0x40U)
31280 #define DMA_DCHPRI16_DPA_SHIFT                   (6U)
31281 /*! DPA - Disable Preempt Ability. This field resets to 0.
31282  *  0b0..Channel n can suspend a lower priority channel
31283  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31284  */
31285 #define DMA_DCHPRI16_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
31286 
31287 #define DMA_DCHPRI16_ECP_MASK                    (0x80U)
31288 #define DMA_DCHPRI16_ECP_SHIFT                   (7U)
31289 /*! ECP - Enable Channel Preemption. This field resets to 0.
31290  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31291  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31292  */
31293 #define DMA_DCHPRI16_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
31294 /*! @} */
31295 
31296 /*! @name DCHPRI23 - Channel Priority */
31297 /*! @{ */
31298 
31299 #define DMA_DCHPRI23_CHPRI_MASK                  (0xFU)
31300 #define DMA_DCHPRI23_CHPRI_SHIFT                 (0U)
31301 /*! CHPRI - Channel n Arbitration Priority */
31302 #define DMA_DCHPRI23_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
31303 
31304 #define DMA_DCHPRI23_GRPPRI_MASK                 (0x30U)
31305 #define DMA_DCHPRI23_GRPPRI_SHIFT                (4U)
31306 /*! GRPPRI - Channel n Current Group Priority */
31307 #define DMA_DCHPRI23_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
31308 
31309 #define DMA_DCHPRI23_DPA_MASK                    (0x40U)
31310 #define DMA_DCHPRI23_DPA_SHIFT                   (6U)
31311 /*! DPA - Disable Preempt Ability. This field resets to 0.
31312  *  0b0..Channel n can suspend a lower priority channel
31313  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31314  */
31315 #define DMA_DCHPRI23_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
31316 
31317 #define DMA_DCHPRI23_ECP_MASK                    (0x80U)
31318 #define DMA_DCHPRI23_ECP_SHIFT                   (7U)
31319 /*! ECP - Enable Channel Preemption. This field resets to 0.
31320  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31321  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31322  */
31323 #define DMA_DCHPRI23_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
31324 /*! @} */
31325 
31326 /*! @name DCHPRI22 - Channel Priority */
31327 /*! @{ */
31328 
31329 #define DMA_DCHPRI22_CHPRI_MASK                  (0xFU)
31330 #define DMA_DCHPRI22_CHPRI_SHIFT                 (0U)
31331 /*! CHPRI - Channel n Arbitration Priority */
31332 #define DMA_DCHPRI22_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
31333 
31334 #define DMA_DCHPRI22_GRPPRI_MASK                 (0x30U)
31335 #define DMA_DCHPRI22_GRPPRI_SHIFT                (4U)
31336 /*! GRPPRI - Channel n Current Group Priority */
31337 #define DMA_DCHPRI22_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
31338 
31339 #define DMA_DCHPRI22_DPA_MASK                    (0x40U)
31340 #define DMA_DCHPRI22_DPA_SHIFT                   (6U)
31341 /*! DPA - Disable Preempt Ability. This field resets to 0.
31342  *  0b0..Channel n can suspend a lower priority channel
31343  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31344  */
31345 #define DMA_DCHPRI22_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
31346 
31347 #define DMA_DCHPRI22_ECP_MASK                    (0x80U)
31348 #define DMA_DCHPRI22_ECP_SHIFT                   (7U)
31349 /*! ECP - Enable Channel Preemption. This field resets to 0.
31350  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31351  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31352  */
31353 #define DMA_DCHPRI22_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
31354 /*! @} */
31355 
31356 /*! @name DCHPRI21 - Channel Priority */
31357 /*! @{ */
31358 
31359 #define DMA_DCHPRI21_CHPRI_MASK                  (0xFU)
31360 #define DMA_DCHPRI21_CHPRI_SHIFT                 (0U)
31361 /*! CHPRI - Channel n Arbitration Priority */
31362 #define DMA_DCHPRI21_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
31363 
31364 #define DMA_DCHPRI21_GRPPRI_MASK                 (0x30U)
31365 #define DMA_DCHPRI21_GRPPRI_SHIFT                (4U)
31366 /*! GRPPRI - Channel n Current Group Priority */
31367 #define DMA_DCHPRI21_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
31368 
31369 #define DMA_DCHPRI21_DPA_MASK                    (0x40U)
31370 #define DMA_DCHPRI21_DPA_SHIFT                   (6U)
31371 /*! DPA - Disable Preempt Ability. This field resets to 0.
31372  *  0b0..Channel n can suspend a lower priority channel
31373  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31374  */
31375 #define DMA_DCHPRI21_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
31376 
31377 #define DMA_DCHPRI21_ECP_MASK                    (0x80U)
31378 #define DMA_DCHPRI21_ECP_SHIFT                   (7U)
31379 /*! ECP - Enable Channel Preemption. This field resets to 0.
31380  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31381  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31382  */
31383 #define DMA_DCHPRI21_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
31384 /*! @} */
31385 
31386 /*! @name DCHPRI20 - Channel Priority */
31387 /*! @{ */
31388 
31389 #define DMA_DCHPRI20_CHPRI_MASK                  (0xFU)
31390 #define DMA_DCHPRI20_CHPRI_SHIFT                 (0U)
31391 /*! CHPRI - Channel n Arbitration Priority */
31392 #define DMA_DCHPRI20_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
31393 
31394 #define DMA_DCHPRI20_GRPPRI_MASK                 (0x30U)
31395 #define DMA_DCHPRI20_GRPPRI_SHIFT                (4U)
31396 /*! GRPPRI - Channel n Current Group Priority */
31397 #define DMA_DCHPRI20_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
31398 
31399 #define DMA_DCHPRI20_DPA_MASK                    (0x40U)
31400 #define DMA_DCHPRI20_DPA_SHIFT                   (6U)
31401 /*! DPA - Disable Preempt Ability. This field resets to 0.
31402  *  0b0..Channel n can suspend a lower priority channel
31403  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31404  */
31405 #define DMA_DCHPRI20_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
31406 
31407 #define DMA_DCHPRI20_ECP_MASK                    (0x80U)
31408 #define DMA_DCHPRI20_ECP_SHIFT                   (7U)
31409 /*! ECP - Enable Channel Preemption. This field resets to 0.
31410  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31411  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31412  */
31413 #define DMA_DCHPRI20_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
31414 /*! @} */
31415 
31416 /*! @name DCHPRI27 - Channel Priority */
31417 /*! @{ */
31418 
31419 #define DMA_DCHPRI27_CHPRI_MASK                  (0xFU)
31420 #define DMA_DCHPRI27_CHPRI_SHIFT                 (0U)
31421 /*! CHPRI - Channel n Arbitration Priority */
31422 #define DMA_DCHPRI27_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
31423 
31424 #define DMA_DCHPRI27_GRPPRI_MASK                 (0x30U)
31425 #define DMA_DCHPRI27_GRPPRI_SHIFT                (4U)
31426 /*! GRPPRI - Channel n Current Group Priority */
31427 #define DMA_DCHPRI27_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
31428 
31429 #define DMA_DCHPRI27_DPA_MASK                    (0x40U)
31430 #define DMA_DCHPRI27_DPA_SHIFT                   (6U)
31431 /*! DPA - Disable Preempt Ability. This field resets to 0.
31432  *  0b0..Channel n can suspend a lower priority channel
31433  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31434  */
31435 #define DMA_DCHPRI27_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
31436 
31437 #define DMA_DCHPRI27_ECP_MASK                    (0x80U)
31438 #define DMA_DCHPRI27_ECP_SHIFT                   (7U)
31439 /*! ECP - Enable Channel Preemption. This field resets to 0.
31440  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31441  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31442  */
31443 #define DMA_DCHPRI27_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
31444 /*! @} */
31445 
31446 /*! @name DCHPRI26 - Channel Priority */
31447 /*! @{ */
31448 
31449 #define DMA_DCHPRI26_CHPRI_MASK                  (0xFU)
31450 #define DMA_DCHPRI26_CHPRI_SHIFT                 (0U)
31451 /*! CHPRI - Channel n Arbitration Priority */
31452 #define DMA_DCHPRI26_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
31453 
31454 #define DMA_DCHPRI26_GRPPRI_MASK                 (0x30U)
31455 #define DMA_DCHPRI26_GRPPRI_SHIFT                (4U)
31456 /*! GRPPRI - Channel n Current Group Priority */
31457 #define DMA_DCHPRI26_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
31458 
31459 #define DMA_DCHPRI26_DPA_MASK                    (0x40U)
31460 #define DMA_DCHPRI26_DPA_SHIFT                   (6U)
31461 /*! DPA - Disable Preempt Ability. This field resets to 0.
31462  *  0b0..Channel n can suspend a lower priority channel
31463  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31464  */
31465 #define DMA_DCHPRI26_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
31466 
31467 #define DMA_DCHPRI26_ECP_MASK                    (0x80U)
31468 #define DMA_DCHPRI26_ECP_SHIFT                   (7U)
31469 /*! ECP - Enable Channel Preemption. This field resets to 0.
31470  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31471  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31472  */
31473 #define DMA_DCHPRI26_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
31474 /*! @} */
31475 
31476 /*! @name DCHPRI25 - Channel Priority */
31477 /*! @{ */
31478 
31479 #define DMA_DCHPRI25_CHPRI_MASK                  (0xFU)
31480 #define DMA_DCHPRI25_CHPRI_SHIFT                 (0U)
31481 /*! CHPRI - Channel n Arbitration Priority */
31482 #define DMA_DCHPRI25_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
31483 
31484 #define DMA_DCHPRI25_GRPPRI_MASK                 (0x30U)
31485 #define DMA_DCHPRI25_GRPPRI_SHIFT                (4U)
31486 /*! GRPPRI - Channel n Current Group Priority */
31487 #define DMA_DCHPRI25_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
31488 
31489 #define DMA_DCHPRI25_DPA_MASK                    (0x40U)
31490 #define DMA_DCHPRI25_DPA_SHIFT                   (6U)
31491 /*! DPA - Disable Preempt Ability. This field resets to 0.
31492  *  0b0..Channel n can suspend a lower priority channel
31493  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31494  */
31495 #define DMA_DCHPRI25_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
31496 
31497 #define DMA_DCHPRI25_ECP_MASK                    (0x80U)
31498 #define DMA_DCHPRI25_ECP_SHIFT                   (7U)
31499 /*! ECP - Enable Channel Preemption. This field resets to 0.
31500  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31501  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31502  */
31503 #define DMA_DCHPRI25_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
31504 /*! @} */
31505 
31506 /*! @name DCHPRI24 - Channel Priority */
31507 /*! @{ */
31508 
31509 #define DMA_DCHPRI24_CHPRI_MASK                  (0xFU)
31510 #define DMA_DCHPRI24_CHPRI_SHIFT                 (0U)
31511 /*! CHPRI - Channel n Arbitration Priority */
31512 #define DMA_DCHPRI24_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
31513 
31514 #define DMA_DCHPRI24_GRPPRI_MASK                 (0x30U)
31515 #define DMA_DCHPRI24_GRPPRI_SHIFT                (4U)
31516 /*! GRPPRI - Channel n Current Group Priority */
31517 #define DMA_DCHPRI24_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
31518 
31519 #define DMA_DCHPRI24_DPA_MASK                    (0x40U)
31520 #define DMA_DCHPRI24_DPA_SHIFT                   (6U)
31521 /*! DPA - Disable Preempt Ability. This field resets to 0.
31522  *  0b0..Channel n can suspend a lower priority channel
31523  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31524  */
31525 #define DMA_DCHPRI24_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
31526 
31527 #define DMA_DCHPRI24_ECP_MASK                    (0x80U)
31528 #define DMA_DCHPRI24_ECP_SHIFT                   (7U)
31529 /*! ECP - Enable Channel Preemption. This field resets to 0.
31530  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31531  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31532  */
31533 #define DMA_DCHPRI24_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
31534 /*! @} */
31535 
31536 /*! @name DCHPRI31 - Channel Priority */
31537 /*! @{ */
31538 
31539 #define DMA_DCHPRI31_CHPRI_MASK                  (0xFU)
31540 #define DMA_DCHPRI31_CHPRI_SHIFT                 (0U)
31541 /*! CHPRI - Channel n Arbitration Priority */
31542 #define DMA_DCHPRI31_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
31543 
31544 #define DMA_DCHPRI31_GRPPRI_MASK                 (0x30U)
31545 #define DMA_DCHPRI31_GRPPRI_SHIFT                (4U)
31546 /*! GRPPRI - Channel n Current Group Priority */
31547 #define DMA_DCHPRI31_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
31548 
31549 #define DMA_DCHPRI31_DPA_MASK                    (0x40U)
31550 #define DMA_DCHPRI31_DPA_SHIFT                   (6U)
31551 /*! DPA - Disable Preempt Ability. This field resets to 0.
31552  *  0b0..Channel n can suspend a lower priority channel
31553  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31554  */
31555 #define DMA_DCHPRI31_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
31556 
31557 #define DMA_DCHPRI31_ECP_MASK                    (0x80U)
31558 #define DMA_DCHPRI31_ECP_SHIFT                   (7U)
31559 /*! ECP - Enable Channel Preemption. This field resets to 0.
31560  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31561  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31562  */
31563 #define DMA_DCHPRI31_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
31564 /*! @} */
31565 
31566 /*! @name DCHPRI30 - Channel Priority */
31567 /*! @{ */
31568 
31569 #define DMA_DCHPRI30_CHPRI_MASK                  (0xFU)
31570 #define DMA_DCHPRI30_CHPRI_SHIFT                 (0U)
31571 /*! CHPRI - Channel n Arbitration Priority */
31572 #define DMA_DCHPRI30_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
31573 
31574 #define DMA_DCHPRI30_GRPPRI_MASK                 (0x30U)
31575 #define DMA_DCHPRI30_GRPPRI_SHIFT                (4U)
31576 /*! GRPPRI - Channel n Current Group Priority */
31577 #define DMA_DCHPRI30_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
31578 
31579 #define DMA_DCHPRI30_DPA_MASK                    (0x40U)
31580 #define DMA_DCHPRI30_DPA_SHIFT                   (6U)
31581 /*! DPA - Disable Preempt Ability. This field resets to 0.
31582  *  0b0..Channel n can suspend a lower priority channel
31583  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31584  */
31585 #define DMA_DCHPRI30_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
31586 
31587 #define DMA_DCHPRI30_ECP_MASK                    (0x80U)
31588 #define DMA_DCHPRI30_ECP_SHIFT                   (7U)
31589 /*! ECP - Enable Channel Preemption. This field resets to 0.
31590  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31591  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31592  */
31593 #define DMA_DCHPRI30_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
31594 /*! @} */
31595 
31596 /*! @name DCHPRI29 - Channel Priority */
31597 /*! @{ */
31598 
31599 #define DMA_DCHPRI29_CHPRI_MASK                  (0xFU)
31600 #define DMA_DCHPRI29_CHPRI_SHIFT                 (0U)
31601 /*! CHPRI - Channel n Arbitration Priority */
31602 #define DMA_DCHPRI29_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
31603 
31604 #define DMA_DCHPRI29_GRPPRI_MASK                 (0x30U)
31605 #define DMA_DCHPRI29_GRPPRI_SHIFT                (4U)
31606 /*! GRPPRI - Channel n Current Group Priority */
31607 #define DMA_DCHPRI29_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
31608 
31609 #define DMA_DCHPRI29_DPA_MASK                    (0x40U)
31610 #define DMA_DCHPRI29_DPA_SHIFT                   (6U)
31611 /*! DPA - Disable Preempt Ability. This field resets to 0.
31612  *  0b0..Channel n can suspend a lower priority channel
31613  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31614  */
31615 #define DMA_DCHPRI29_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
31616 
31617 #define DMA_DCHPRI29_ECP_MASK                    (0x80U)
31618 #define DMA_DCHPRI29_ECP_SHIFT                   (7U)
31619 /*! ECP - Enable Channel Preemption. This field resets to 0.
31620  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31621  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31622  */
31623 #define DMA_DCHPRI29_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
31624 /*! @} */
31625 
31626 /*! @name DCHPRI28 - Channel Priority */
31627 /*! @{ */
31628 
31629 #define DMA_DCHPRI28_CHPRI_MASK                  (0xFU)
31630 #define DMA_DCHPRI28_CHPRI_SHIFT                 (0U)
31631 /*! CHPRI - Channel n Arbitration Priority */
31632 #define DMA_DCHPRI28_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
31633 
31634 #define DMA_DCHPRI28_GRPPRI_MASK                 (0x30U)
31635 #define DMA_DCHPRI28_GRPPRI_SHIFT                (4U)
31636 /*! GRPPRI - Channel n Current Group Priority */
31637 #define DMA_DCHPRI28_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
31638 
31639 #define DMA_DCHPRI28_DPA_MASK                    (0x40U)
31640 #define DMA_DCHPRI28_DPA_SHIFT                   (6U)
31641 /*! DPA - Disable Preempt Ability. This field resets to 0.
31642  *  0b0..Channel n can suspend a lower priority channel
31643  *  0b1..Channel n cannot suspend any channel, regardless of channel priority
31644  */
31645 #define DMA_DCHPRI28_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
31646 
31647 #define DMA_DCHPRI28_ECP_MASK                    (0x80U)
31648 #define DMA_DCHPRI28_ECP_SHIFT                   (7U)
31649 /*! ECP - Enable Channel Preemption. This field resets to 0.
31650  *  0b0..Channel n cannot be suspended by a higher priority channel's service request
31651  *  0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
31652  */
31653 #define DMA_DCHPRI28_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
31654 /*! @} */
31655 
31656 /*! @name SADDR - TCD Source Address */
31657 /*! @{ */
31658 
31659 #define DMA_SADDR_SADDR_MASK                     (0xFFFFFFFFU)
31660 #define DMA_SADDR_SADDR_SHIFT                    (0U)
31661 /*! SADDR - Source Address */
31662 #define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
31663 /*! @} */
31664 
31665 /* The count of DMA_SADDR */
31666 #define DMA_SADDR_COUNT                          (32U)
31667 
31668 /*! @name SOFF - TCD Signed Source Address Offset */
31669 /*! @{ */
31670 
31671 #define DMA_SOFF_SOFF_MASK                       (0xFFFFU)
31672 #define DMA_SOFF_SOFF_SHIFT                      (0U)
31673 /*! SOFF - Source address signed offset */
31674 #define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
31675 /*! @} */
31676 
31677 /* The count of DMA_SOFF */
31678 #define DMA_SOFF_COUNT                           (32U)
31679 
31680 /*! @name ATTR - TCD Transfer Attributes */
31681 /*! @{ */
31682 
31683 #define DMA_ATTR_DSIZE_MASK                      (0x7U)
31684 #define DMA_ATTR_DSIZE_SHIFT                     (0U)
31685 /*! DSIZE - Destination data transfer size */
31686 #define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
31687 
31688 #define DMA_ATTR_DMOD_MASK                       (0xF8U)
31689 #define DMA_ATTR_DMOD_SHIFT                      (3U)
31690 /*! DMOD - Destination Address Modulo */
31691 #define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
31692 
31693 #define DMA_ATTR_SSIZE_MASK                      (0x700U)
31694 #define DMA_ATTR_SSIZE_SHIFT                     (8U)
31695 /*! SSIZE - Source data transfer size
31696  *  0b000..8-bit
31697  *  0b001..16-bit
31698  *  0b010..32-bit
31699  *  0b011..64-bit
31700  *  0b100..Reserved
31701  *  0b101..32-byte burst (4 beats of 64 bits)
31702  *  0b110..Reserved
31703  *  0b111..Reserved
31704  */
31705 #define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
31706 
31707 #define DMA_ATTR_SMOD_MASK                       (0xF800U)
31708 #define DMA_ATTR_SMOD_SHIFT                      (11U)
31709 /*! SMOD - Source Address Modulo
31710  *  0b00000..Source address modulo feature is disabled
31711  *  0b00001-0b11111..Value defines address range used to set up circular data queue
31712  */
31713 #define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
31714 /*! @} */
31715 
31716 /* The count of DMA_ATTR */
31717 #define DMA_ATTR_COUNT                           (32U)
31718 
31719 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
31720 /*! @{ */
31721 
31722 #define DMA_NBYTES_MLNO_NBYTES_MASK              (0xFFFFFFFFU)
31723 #define DMA_NBYTES_MLNO_NBYTES_SHIFT             (0U)
31724 /*! NBYTES - Minor Byte Transfer Count */
31725 #define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
31726 /*! @} */
31727 
31728 /* The count of DMA_NBYTES_MLNO */
31729 #define DMA_NBYTES_MLNO_COUNT                    (32U)
31730 
31731 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
31732 /*! @{ */
31733 
31734 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK           (0x3FFFFFFFU)
31735 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          (0U)
31736 /*! NBYTES - Minor Byte Transfer Count */
31737 #define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
31738 
31739 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK            (0x40000000U)
31740 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           (30U)
31741 /*! DMLOE - Destination Minor Loop Offset Enable
31742  *  0b0..The minor loop offset is not applied to the DADDR
31743  *  0b1..The minor loop offset is applied to the DADDR
31744  */
31745 #define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
31746 
31747 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK            (0x80000000U)
31748 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           (31U)
31749 /*! SMLOE - Source Minor Loop Offset Enable
31750  *  0b0..The minor loop offset is not applied to the SADDR
31751  *  0b1..The minor loop offset is applied to the SADDR
31752  */
31753 #define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
31754 /*! @} */
31755 
31756 /* The count of DMA_NBYTES_MLOFFNO */
31757 #define DMA_NBYTES_MLOFFNO_COUNT                 (32U)
31758 
31759 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
31760 /*! @{ */
31761 
31762 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK          (0x3FFU)
31763 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         (0U)
31764 /*! NBYTES - Minor Byte Transfer Count */
31765 #define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
31766 
31767 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK           (0x3FFFFC00U)
31768 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          (10U)
31769 /*! MLOFF - If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the
31770  *    source or destination address to form the next-state value after the minor loop completes.
31771  */
31772 #define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
31773 
31774 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK           (0x40000000U)
31775 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          (30U)
31776 /*! DMLOE - Destination Minor Loop Offset Enable
31777  *  0b0..The minor loop offset is not applied to the DADDR
31778  *  0b1..The minor loop offset is applied to the DADDR
31779  */
31780 #define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
31781 
31782 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK           (0x80000000U)
31783 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          (31U)
31784 /*! SMLOE - Source Minor Loop Offset Enable
31785  *  0b0..The minor loop offset is not applied to the SADDR
31786  *  0b1..The minor loop offset is applied to the SADDR
31787  */
31788 #define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
31789 /*! @} */
31790 
31791 /* The count of DMA_NBYTES_MLOFFYES */
31792 #define DMA_NBYTES_MLOFFYES_COUNT                (32U)
31793 
31794 /*! @name SLAST - TCD Last Source Address Adjustment */
31795 /*! @{ */
31796 
31797 #define DMA_SLAST_SLAST_MASK                     (0xFFFFFFFFU)
31798 #define DMA_SLAST_SLAST_SHIFT                    (0U)
31799 /*! SLAST - Last Source Address Adjustment */
31800 #define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
31801 /*! @} */
31802 
31803 /* The count of DMA_SLAST */
31804 #define DMA_SLAST_COUNT                          (32U)
31805 
31806 /*! @name DADDR - TCD Destination Address */
31807 /*! @{ */
31808 
31809 #define DMA_DADDR_DADDR_MASK                     (0xFFFFFFFFU)
31810 #define DMA_DADDR_DADDR_SHIFT                    (0U)
31811 /*! DADDR - Destination Address */
31812 #define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
31813 /*! @} */
31814 
31815 /* The count of DMA_DADDR */
31816 #define DMA_DADDR_COUNT                          (32U)
31817 
31818 /*! @name DOFF - TCD Signed Destination Address Offset */
31819 /*! @{ */
31820 
31821 #define DMA_DOFF_DOFF_MASK                       (0xFFFFU)
31822 #define DMA_DOFF_DOFF_SHIFT                      (0U)
31823 /*! DOFF - Destination Address Signed Offset */
31824 #define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
31825 /*! @} */
31826 
31827 /* The count of DMA_DOFF */
31828 #define DMA_DOFF_COUNT                           (32U)
31829 
31830 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
31831 /*! @{ */
31832 
31833 #define DMA_CITER_ELINKNO_CITER_MASK             (0x7FFFU)
31834 #define DMA_CITER_ELINKNO_CITER_SHIFT            (0U)
31835 /*! CITER - Current Major Iteration Count */
31836 #define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
31837 
31838 #define DMA_CITER_ELINKNO_ELINK_MASK             (0x8000U)
31839 #define DMA_CITER_ELINKNO_ELINK_SHIFT            (15U)
31840 /*! ELINK - Enable channel-to-channel linking on minor-loop complete
31841  *  0b0..Channel-to-channel linking is disabled
31842  *  0b1..Channel-to-channel linking is enabled
31843  */
31844 #define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
31845 /*! @} */
31846 
31847 /* The count of DMA_CITER_ELINKNO */
31848 #define DMA_CITER_ELINKNO_COUNT                  (32U)
31849 
31850 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
31851 /*! @{ */
31852 
31853 #define DMA_CITER_ELINKYES_CITER_MASK            (0x1FFU)
31854 #define DMA_CITER_ELINKYES_CITER_SHIFT           (0U)
31855 /*! CITER - Current Major Iteration Count */
31856 #define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
31857 
31858 #define DMA_CITER_ELINKYES_LINKCH_MASK           (0x3E00U)
31859 #define DMA_CITER_ELINKYES_LINKCH_SHIFT          (9U)
31860 /*! LINKCH - Minor Loop Link Channel Number */
31861 #define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
31862 
31863 #define DMA_CITER_ELINKYES_ELINK_MASK            (0x8000U)
31864 #define DMA_CITER_ELINKYES_ELINK_SHIFT           (15U)
31865 /*! ELINK - Enable channel-to-channel linking on minor-loop complete
31866  *  0b0..Channel-to-channel linking is disabled
31867  *  0b1..Channel-to-channel linking is enabled
31868  */
31869 #define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
31870 /*! @} */
31871 
31872 /* The count of DMA_CITER_ELINKYES */
31873 #define DMA_CITER_ELINKYES_COUNT                 (32U)
31874 
31875 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
31876 /*! @{ */
31877 
31878 #define DMA_DLAST_SGA_DLASTSGA_MASK              (0xFFFFFFFFU)
31879 #define DMA_DLAST_SGA_DLASTSGA_SHIFT             (0U)
31880 /*! DLASTSGA - Destination last address adjustment, or next memory address TCD for channel (scatter/gather) */
31881 #define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
31882 /*! @} */
31883 
31884 /* The count of DMA_DLAST_SGA */
31885 #define DMA_DLAST_SGA_COUNT                      (32U)
31886 
31887 /*! @name CSR - TCD Control and Status */
31888 /*! @{ */
31889 
31890 #define DMA_CSR_START_MASK                       (0x1U)
31891 #define DMA_CSR_START_SHIFT                      (0U)
31892 /*! START - Channel Start
31893  *  0b0..Channel is not explicitly started
31894  *  0b1..Channel is explicitly started via a software initiated service request
31895  */
31896 #define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
31897 
31898 #define DMA_CSR_INTMAJOR_MASK                    (0x2U)
31899 #define DMA_CSR_INTMAJOR_SHIFT                   (1U)
31900 /*! INTMAJOR - Enable an interrupt when major iteration count completes.
31901  *  0b0..End of major loop interrupt is disabled
31902  *  0b1..End of major loop interrupt is enabled
31903  */
31904 #define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
31905 
31906 #define DMA_CSR_INTHALF_MASK                     (0x4U)
31907 #define DMA_CSR_INTHALF_SHIFT                    (2U)
31908 /*! INTHALF - Enable an interrupt when major counter is half complete.
31909  *  0b0..Half-point interrupt is disabled
31910  *  0b1..Half-point interrupt is enabled
31911  */
31912 #define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
31913 
31914 #define DMA_CSR_DREQ_MASK                        (0x8U)
31915 #define DMA_CSR_DREQ_SHIFT                       (3U)
31916 /*! DREQ - Disable Request
31917  *  0b0..The channel's ERQ field is not affected
31918  *  0b1..The channel's ERQ field value changes to 0 when the major loop is complete
31919  */
31920 #define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
31921 
31922 #define DMA_CSR_ESG_MASK                         (0x10U)
31923 #define DMA_CSR_ESG_SHIFT                        (4U)
31924 /*! ESG - Enable Scatter/Gather Processing
31925  *  0b0..The current channel's TCD is normal format
31926  *  0b1..The current channel's TCD specifies a scatter gather format
31927  */
31928 #define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
31929 
31930 #define DMA_CSR_MAJORELINK_MASK                  (0x20U)
31931 #define DMA_CSR_MAJORELINK_SHIFT                 (5U)
31932 /*! MAJORELINK - Enable channel-to-channel linking on major loop complete
31933  *  0b0..Channel-to-channel linking is disabled
31934  *  0b1..Channel-to-channel linking is enabled
31935  */
31936 #define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
31937 
31938 #define DMA_CSR_ACTIVE_MASK                      (0x40U)
31939 #define DMA_CSR_ACTIVE_SHIFT                     (6U)
31940 /*! ACTIVE - Channel Active */
31941 #define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
31942 
31943 #define DMA_CSR_DONE_MASK                        (0x80U)
31944 #define DMA_CSR_DONE_SHIFT                       (7U)
31945 /*! DONE - Channel Done */
31946 #define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
31947 
31948 #define DMA_CSR_MAJORLINKCH_MASK                 (0x1F00U)
31949 #define DMA_CSR_MAJORLINKCH_SHIFT                (8U)
31950 /*! MAJORLINKCH - Major Loop Link Channel Number */
31951 #define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
31952 
31953 #define DMA_CSR_BWC_MASK                         (0xC000U)
31954 #define DMA_CSR_BWC_SHIFT                        (14U)
31955 /*! BWC - Bandwidth Control
31956  *  0b00..No eDMA engine stalls
31957  *  0b01..Reserved
31958  *  0b10..eDMA engine stalls for 4 cycles after each R/W
31959  *  0b11..eDMA engine stalls for 8 cycles after each R/W
31960  */
31961 #define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
31962 /*! @} */
31963 
31964 /* The count of DMA_CSR */
31965 #define DMA_CSR_COUNT                            (32U)
31966 
31967 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
31968 /*! @{ */
31969 
31970 #define DMA_BITER_ELINKNO_BITER_MASK             (0x7FFFU)
31971 #define DMA_BITER_ELINKNO_BITER_SHIFT            (0U)
31972 /*! BITER - Starting Major Iteration Count */
31973 #define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
31974 
31975 #define DMA_BITER_ELINKNO_ELINK_MASK             (0x8000U)
31976 #define DMA_BITER_ELINKNO_ELINK_SHIFT            (15U)
31977 /*! ELINK - Enables channel-to-channel linking on minor loop complete
31978  *  0b0..Channel-to-channel linking is disabled
31979  *  0b1..Channel-to-channel linking is enabled
31980  */
31981 #define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
31982 /*! @} */
31983 
31984 /* The count of DMA_BITER_ELINKNO */
31985 #define DMA_BITER_ELINKNO_COUNT                  (32U)
31986 
31987 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
31988 /*! @{ */
31989 
31990 #define DMA_BITER_ELINKYES_BITER_MASK            (0x1FFU)
31991 #define DMA_BITER_ELINKYES_BITER_SHIFT           (0U)
31992 /*! BITER - Starting major iteration count */
31993 #define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
31994 
31995 #define DMA_BITER_ELINKYES_LINKCH_MASK           (0x3E00U)
31996 #define DMA_BITER_ELINKYES_LINKCH_SHIFT          (9U)
31997 /*! LINKCH - Link Channel Number */
31998 #define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
31999 
32000 #define DMA_BITER_ELINKYES_ELINK_MASK            (0x8000U)
32001 #define DMA_BITER_ELINKYES_ELINK_SHIFT           (15U)
32002 /*! ELINK - Enables channel-to-channel linking on minor loop complete
32003  *  0b0..Channel-to-channel linking is disabled
32004  *  0b1..Channel-to-channel linking is enabled
32005  */
32006 #define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
32007 /*! @} */
32008 
32009 /* The count of DMA_BITER_ELINKYES */
32010 #define DMA_BITER_ELINKYES_COUNT                 (32U)
32011 
32012 
32013 /*!
32014  * @}
32015  */ /* end of group DMA_Register_Masks */
32016 
32017 
32018 /* DMA - Peripheral instance base addresses */
32019 /** Peripheral DMA0 base address */
32020 #define DMA0_BASE                                (0x40070000u)
32021 /** Peripheral DMA0 base pointer */
32022 #define DMA0                                     ((DMA_Type *)DMA0_BASE)
32023 /** Array initializer of DMA peripheral base addresses */
32024 #define DMA_BASE_ADDRS                           { DMA0_BASE }
32025 /** Array initializer of DMA peripheral base pointers */
32026 #define DMA_BASE_PTRS                            { DMA0 }
32027 /** Interrupt vectors for the DMA peripheral type */
32028 #define DMA_CHN_IRQS                             { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
32029 #define DMA_ERROR_IRQS                           { DMA_ERROR_IRQn }
32030 
32031 /*!
32032  * @}
32033  */ /* end of group DMA_Peripheral_Access_Layer */
32034 
32035 
32036 /* ----------------------------------------------------------------------------
32037    -- DMAMUX Peripheral Access Layer
32038    ---------------------------------------------------------------------------- */
32039 
32040 /*!
32041  * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
32042  * @{
32043  */
32044 
32045 /** DMAMUX - Register Layout Typedef */
32046 typedef struct {
32047   __IO uint32_t CHCFG[32];                         /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */
32048 } DMAMUX_Type;
32049 
32050 /* ----------------------------------------------------------------------------
32051    -- DMAMUX Register Masks
32052    ---------------------------------------------------------------------------- */
32053 
32054 /*!
32055  * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
32056  * @{
32057  */
32058 
32059 /*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */
32060 /*! @{ */
32061 
32062 #define DMAMUX_CHCFG_SOURCE_MASK                 (0xFFU)
32063 #define DMAMUX_CHCFG_SOURCE_SHIFT                (0U)
32064 /*! SOURCE - DMA Channel Source (Slot Number) */
32065 #define DMAMUX_CHCFG_SOURCE(x)                   (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
32066 
32067 #define DMAMUX_CHCFG_A_ON_MASK                   (0x20000000U)
32068 #define DMAMUX_CHCFG_A_ON_SHIFT                  (29U)
32069 /*! A_ON - DMA Channel Always Enable
32070  *  0b0..DMA Channel Always ON function is disabled
32071  *  0b1..DMA Channel Always ON function is enabled
32072  */
32073 #define DMAMUX_CHCFG_A_ON(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
32074 
32075 #define DMAMUX_CHCFG_TRIG_MASK                   (0x40000000U)
32076 #define DMAMUX_CHCFG_TRIG_SHIFT                  (30U)
32077 /*! TRIG - DMA Channel Trigger Enable
32078  *  0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the
32079  *       specified source to the DMA channel. (Normal mode)
32080  *  0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
32081  */
32082 #define DMAMUX_CHCFG_TRIG(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
32083 
32084 #define DMAMUX_CHCFG_ENBL_MASK                   (0x80000000U)
32085 #define DMAMUX_CHCFG_ENBL_SHIFT                  (31U)
32086 /*! ENBL - DMA Mux Channel Enable
32087  *  0b0..DMA Mux channel is disabled
32088  *  0b1..DMA Mux channel is enabled
32089  */
32090 #define DMAMUX_CHCFG_ENBL(x)                     (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
32091 /*! @} */
32092 
32093 /* The count of DMAMUX_CHCFG */
32094 #define DMAMUX_CHCFG_COUNT                       (32U)
32095 
32096 
32097 /*!
32098  * @}
32099  */ /* end of group DMAMUX_Register_Masks */
32100 
32101 
32102 /* DMAMUX - Peripheral instance base addresses */
32103 /** Peripheral DMAMUX0 base address */
32104 #define DMAMUX0_BASE                             (0x40074000u)
32105 /** Peripheral DMAMUX0 base pointer */
32106 #define DMAMUX0                                  ((DMAMUX_Type *)DMAMUX0_BASE)
32107 /** Array initializer of DMAMUX peripheral base addresses */
32108 #define DMAMUX_BASE_ADDRS                        { DMAMUX0_BASE }
32109 /** Array initializer of DMAMUX peripheral base pointers */
32110 #define DMAMUX_BASE_PTRS                         { DMAMUX0 }
32111 
32112 /*!
32113  * @}
32114  */ /* end of group DMAMUX_Peripheral_Access_Layer */
32115 
32116 
32117 /* ----------------------------------------------------------------------------
32118    -- DSI_HOST Peripheral Access Layer
32119    ---------------------------------------------------------------------------- */
32120 
32121 /*!
32122  * @addtogroup DSI_HOST_Peripheral_Access_Layer DSI_HOST Peripheral Access Layer
32123  * @{
32124  */
32125 
32126 /** DSI_HOST - Register Layout Typedef */
32127 typedef struct {
32128   __IO uint32_t CFG_NUM_LANES;                     /**< offset: 0x0 */
32129   __IO uint32_t CFG_NONCONTINUOUS_CLK;             /**< offset: 0x4 */
32130   __IO uint32_t CFG_T_PRE;                         /**< offset: 0x8 */
32131   __IO uint32_t CFG_T_POST;                        /**< offset: 0xC */
32132   __IO uint32_t CFG_TX_GAP;                        /**< offset: 0x10 */
32133   __IO uint32_t CFG_AUTOINSERT_EOTP;               /**< offset: 0x14 */
32134   __IO uint32_t CFG_EXTRA_CMDS_AFTER_EOTP;         /**< offset: 0x18 */
32135   __IO uint32_t CFG_HTX_TO_COUNT;                  /**< offset: 0x1C */
32136   __IO uint32_t CFG_LRX_H_TO_COUNT;                /**< offset: 0x20 */
32137   __IO uint32_t CFG_BTA_H_TO_COUNT;                /**< offset: 0x24 */
32138   __IO uint32_t CFG_TWAKEUP;                       /**< offset: 0x28 */
32139   __I  uint32_t CFG_STATUS_OUT;                    /**< offset: 0x2C */
32140   __I  uint32_t RX_ERROR_STATUS;                   /**< offset: 0x30 */
32141 } DSI_HOST_Type;
32142 
32143 /* ----------------------------------------------------------------------------
32144    -- DSI_HOST Register Masks
32145    ---------------------------------------------------------------------------- */
32146 
32147 /*!
32148  * @addtogroup DSI_HOST_Register_Masks DSI_HOST Register Masks
32149  * @{
32150  */
32151 
32152 /*! @name CFG_NUM_LANES -  */
32153 /*! @{ */
32154 
32155 #define DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK    (0x3U)
32156 #define DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT   (0U)
32157 /*! NUM_LANES - Sets the number of active lanes that are to be used for transmitting data.
32158  *  0b00..1 lane
32159  *  0b01..2 lanes
32160  */
32161 #define DSI_HOST_CFG_NUM_LANES_NUM_LANES(x)      (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT)) & DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK)
32162 /*! @} */
32163 
32164 /*! @name CFG_NONCONTINUOUS_CLK -  */
32165 /*! @{ */
32166 
32167 #define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK (0x1U)
32168 #define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT (0U)
32169 /*! CLK_MODE - Sets the Host Controller into non-continuous MIPI clock mode. When in non-continuous
32170  *    clock mode, the high speed clock will transition into low power mode between transmissions.
32171  *  0b0..Continuous high speed clock
32172  *  0b1..Non-Continuous high speed clock
32173  */
32174 #define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT)) & DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK)
32175 /*! @} */
32176 
32177 /*! @name CFG_T_PRE -  */
32178 /*! @{ */
32179 
32180 #define DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK      (0xFFU)
32181 #define DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT     (0U)
32182 /*! NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) that the controller will
32183  *    wait after enabling the clock lane for HS operation before enabling the data lanes for HS
32184  *    operation. This setting represents the TCLK-PRE DPHY timing parameter. The minimum value for this
32185  *    port is 1.
32186  */
32187 #define DSI_HOST_CFG_T_PRE_NUM_PERIODS(x)        (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK)
32188 /*! @} */
32189 
32190 /*! @name CFG_T_POST -  */
32191 /*! @{ */
32192 
32193 #define DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK     (0xFFU)
32194 #define DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT    (0U)
32195 /*! NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) to wait before putting
32196  *    the clock lane into LP mode after the data lanes have been detected to be in Stop State. This
32197  *    setting represents the DPHY timing parameters TLPX + TCLK-PREPARE + TCLK-ZERO + TCLK-PRE
32198  *    requirement for the clock lane before the data lane is allowed to change from LP11 to start a high
32199  *    speed transmission. The minimum value for this port is 1.
32200  */
32201 #define DSI_HOST_CFG_T_POST_NUM_PERIODS(x)       (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK)
32202 /*! @} */
32203 
32204 /*! @name CFG_TX_GAP -  */
32205 /*! @{ */
32206 
32207 #define DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK     (0xFFU)
32208 #define DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT    (0U)
32209 /*! NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) that the controller will
32210  *    wait after the clock lane has been put into LP mode before enabling the clock lane for HS mode
32211  *    again. This setting represents the THS-EXIT DPHY timing parameter. The minimum value for this
32212  *    port is 1.
32213  */
32214 #define DSI_HOST_CFG_TX_GAP_NUM_PERIODS(x)       (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK)
32215 /*! @} */
32216 
32217 /*! @name CFG_AUTOINSERT_EOTP -  */
32218 /*! @{ */
32219 
32220 #define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK (0x1U)
32221 #define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT (0U)
32222 /*! AUTOINSERT - Enables the Host Controller to automatically insert an EoTp short packet when switching from HS to LP mode.
32223  *  0b0..EoTp is not automatically inserted
32224  *  0b1..EoTp is automatically inserted
32225  */
32226 #define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT)) & DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK)
32227 /*! @} */
32228 
32229 /*! @name CFG_EXTRA_CMDS_AFTER_EOTP -  */
32230 /*! @{ */
32231 
32232 #define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK (0xFFU)
32233 #define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT (0U)
32234 /*! EXTRA_EOTP - Configures the DSI Host Controller to send extra End Of Transmission Packets after
32235  *    the end of a packet. The value is the number of extra EOTP packets sent.
32236  */
32237 #define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT)) & DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK)
32238 /*! @} */
32239 
32240 /*! @name CFG_HTX_TO_COUNT -  */
32241 /*! @{ */
32242 
32243 #define DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK     (0xFFFFFFU)
32244 #define DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT    (0U)
32245 /*! COUNT - Sets the value of the DSI Host High Speed TX timeout count in clk_byte clock periods
32246  *    that once reached will initiate a timeout error and follow the recovery procedure documented in
32247  *    the DSI specification.
32248  */
32249 #define DSI_HOST_CFG_HTX_TO_COUNT_COUNT(x)       (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK)
32250 /*! @} */
32251 
32252 /*! @name CFG_LRX_H_TO_COUNT -  */
32253 /*! @{ */
32254 
32255 #define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK   (0xFFFFFFU)
32256 #define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT  (0U)
32257 /*! COUNT - Sets the value of the DSI Host low power RX timeout count in clk_byte clock periods that
32258  *    once reached will initiate a timeout error and follow the recovery procedure documented in
32259  *    the DSI specification.
32260  */
32261 #define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK)
32262 /*! @} */
32263 
32264 /*! @name CFG_BTA_H_TO_COUNT -  */
32265 /*! @{ */
32266 
32267 #define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK   (0xFFFFFFU)
32268 #define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT  (0U)
32269 /*! COUNT - Sets the value of the DSI Host Bus Turn Around (BTA) timeout in clk_byte clock periods
32270  *    that once reached will initiate a timeout error.
32271  */
32272 #define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT(x)     (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK)
32273 /*! @} */
32274 
32275 /*! @name CFG_TWAKEUP -  */
32276 /*! @{ */
32277 
32278 #define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK    (0x7FFFFU)
32279 #define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT   (0U)
32280 /*! NUM_PERIODS - DPHY Twakeup timing parameter. Sets the number of clk_esc clock periods to keep a
32281  *    clock or data lane in Mark-1 state after exiting ULPS. The MIPI DPHY spec requires a minimum
32282  *    of 1ms in Mark-1 state after leaving ULPS.
32283  */
32284 #define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS(x)      (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK)
32285 /*! @} */
32286 
32287 /*! @name CFG_STATUS_OUT -  */
32288 /*! @{ */
32289 
32290 #define DSI_HOST_CFG_STATUS_OUT_STATUS_MASK      (0xFFFFFFFFU)
32291 #define DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT     (0U)
32292 /*! STATUS - Status Register */
32293 #define DSI_HOST_CFG_STATUS_OUT_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT)) & DSI_HOST_CFG_STATUS_OUT_STATUS_MASK)
32294 /*! @} */
32295 
32296 /*! @name RX_ERROR_STATUS -  */
32297 /*! @{ */
32298 
32299 #define DSI_HOST_RX_ERROR_STATUS_STATUS_MASK     (0x7FFU)
32300 #define DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT    (0U)
32301 /*! STATUS - Status Register for Host receive error detection, ECC errors, CRC errors and for timeout indicators */
32302 #define DSI_HOST_RX_ERROR_STATUS_STATUS(x)       (((uint32_t)(((uint32_t)(x)) << DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT)) & DSI_HOST_RX_ERROR_STATUS_STATUS_MASK)
32303 /*! @} */
32304 
32305 
32306 /*!
32307  * @}
32308  */ /* end of group DSI_HOST_Register_Masks */
32309 
32310 
32311 /* DSI_HOST - Peripheral instance base addresses */
32312 /** Peripheral DSI_HOST base address */
32313 #define DSI_HOST_BASE                            (0x4080C000u)
32314 /** Peripheral DSI_HOST base pointer */
32315 #define DSI_HOST                                 ((DSI_HOST_Type *)DSI_HOST_BASE)
32316 /** Array initializer of DSI_HOST peripheral base addresses */
32317 #define DSI_HOST_BASE_ADDRS                      { DSI_HOST_BASE }
32318 /** Array initializer of DSI_HOST peripheral base pointers */
32319 #define DSI_HOST_BASE_PTRS                       { DSI_HOST }
32320 /** Interrupt vectors for the DSI_HOST peripheral type */
32321 #define DSI_HOST_DSI_IRQS                        { MIPI_DSI_IRQn }
32322 
32323 /*!
32324  * @}
32325  */ /* end of group DSI_HOST_Peripheral_Access_Layer */
32326 
32327 
32328 /* ----------------------------------------------------------------------------
32329    -- DSI_HOST_APB_PKT_IF Peripheral Access Layer
32330    ---------------------------------------------------------------------------- */
32331 
32332 /*!
32333  * @addtogroup DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer DSI_HOST_APB_PKT_IF Peripheral Access Layer
32334  * @{
32335  */
32336 
32337 /** DSI_HOST_APB_PKT_IF - Register Layout Typedef */
32338 typedef struct {
32339   __IO uint32_t TX_PAYLOAD;                        /**< offset: 0x0 */
32340   __IO uint32_t PKT_CONTROL;                       /**< offset: 0x4 */
32341   __IO uint32_t SEND_PACKET;                       /**< offset: 0x8 */
32342   __I  uint32_t PKT_STATUS;                        /**< offset: 0xC */
32343   __I  uint32_t PKT_FIFO_WR_LEVEL;                 /**< offset: 0x10 */
32344   __I  uint32_t PKT_FIFO_RD_LEVEL;                 /**< offset: 0x14 */
32345   __I  uint32_t PKT_RX_PAYLOAD;                    /**< offset: 0x18 */
32346   __I  uint32_t PKT_RX_PKT_HEADER;                 /**< offset: 0x1C */
32347   __I  uint32_t IRQ_STATUS;                        /**< offset: 0x20 */
32348   __I  uint32_t IRQ_STATUS2;                       /**< offset: 0x24 */
32349   __IO uint32_t IRQ_MASK;                          /**< offset: 0x28 */
32350   __IO uint32_t IRQ_MASK2;                         /**< offset: 0x2C */
32351 } DSI_HOST_APB_PKT_IF_Type;
32352 
32353 /* ----------------------------------------------------------------------------
32354    -- DSI_HOST_APB_PKT_IF Register Masks
32355    ---------------------------------------------------------------------------- */
32356 
32357 /*!
32358  * @addtogroup DSI_HOST_APB_PKT_IF_Register_Masks DSI_HOST_APB_PKT_IF Register Masks
32359  * @{
32360  */
32361 
32362 /*! @name TX_PAYLOAD -  */
32363 /*! @{ */
32364 
32365 #define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU)
32366 #define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_SHIFT (0U)
32367 /*! PAYLOAD - Tx Payload data write register. Write to this register loads the payload FIFO with 32 bit values. */
32368 #define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_SHIFT)) & DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_MASK)
32369 /*! @} */
32370 
32371 /*! @name PKT_CONTROL -  */
32372 /*! @{ */
32373 
32374 #define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_MASK (0x7FFFFFFU)
32375 #define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_SHIFT (0U)
32376 /*! CTRL - Tx packet control */
32377 #define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL(x)  (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_MASK)
32378 /*! @} */
32379 
32380 /*! @name SEND_PACKET -  */
32381 /*! @{ */
32382 
32383 #define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_MASK (0x1U)
32384 #define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_SHIFT (0U)
32385 /*! TX_SEND - Tx send packet, writing to this register causes the packet described in dsi_host_pkt_control to be sent.
32386  *  0b0..Packet not sent
32387  *  0b1..Packet is sent
32388  */
32389 #define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_SHIFT)) & DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_MASK)
32390 /*! @} */
32391 
32392 /*! @name PKT_STATUS -  */
32393 /*! @{ */
32394 
32395 #define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_MASK (0x1FFU)
32396 #define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_SHIFT (0U)
32397 /*! STATUS - Status of APB to packet interface. */
32398 #define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_MASK)
32399 /*! @} */
32400 
32401 /*! @name PKT_FIFO_WR_LEVEL -  */
32402 /*! @{ */
32403 
32404 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_MASK (0xFFFFU)
32405 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_SHIFT (0U)
32406 /*! WR - Write level of APB to pkt interface FIFO */
32407 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_MASK)
32408 /*! @} */
32409 
32410 /*! @name PKT_FIFO_RD_LEVEL -  */
32411 /*! @{ */
32412 
32413 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_MASK (0xFFFFU)
32414 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_SHIFT (0U)
32415 /*! RD - Read level of APB to pkt interface FIFO */
32416 #define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_MASK)
32417 /*! @} */
32418 
32419 /*! @name PKT_RX_PAYLOAD -  */
32420 /*! @{ */
32421 
32422 #define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU)
32423 #define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_SHIFT (0U)
32424 /*! PAYLOAD - APB to pkt interface Rx payload read */
32425 #define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_MASK)
32426 /*! @} */
32427 
32428 /*! @name PKT_RX_PKT_HEADER -  */
32429 /*! @{ */
32430 
32431 #define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_MASK (0xFFFFFFU)
32432 #define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_SHIFT (0U)
32433 /*! HEADER - APB to pkt interface Rx packet header */
32434 #define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_MASK)
32435 /*! @} */
32436 
32437 /*! @name IRQ_STATUS -  */
32438 /*! @{ */
32439 
32440 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_MASK (0xFFFFFFFFU)
32441 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_SHIFT (0U)
32442 /*! STATUS - Status of APB to packet interface. */
32443 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_MASK)
32444 /*! @} */
32445 
32446 /*! @name IRQ_STATUS2 -  */
32447 /*! @{ */
32448 
32449 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_MASK (0x7U)
32450 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_SHIFT (0U)
32451 /*! STATUS2 - Status of APB to packet interface part 2, read part 2 first then dsi_host_irq_status.
32452  *    Reading dsi_host_irq_status will clear both status and status2.
32453  */
32454 #define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_MASK)
32455 /*! @} */
32456 
32457 /*! @name IRQ_MASK -  */
32458 /*! @{ */
32459 
32460 #define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_MASK   (0xFFFFFFFFU)
32461 #define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_SHIFT  (0U)
32462 /*! MASK - IRQ Mask */
32463 #define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK(x)     (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_MASK)
32464 /*! @} */
32465 
32466 /*! @name IRQ_MASK2 -  */
32467 /*! @{ */
32468 
32469 #define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_MASK (0x7U)
32470 #define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_SHIFT (0U)
32471 /*! MASK2 - IRQ mask 2 */
32472 #define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_MASK)
32473 /*! @} */
32474 
32475 
32476 /*!
32477  * @}
32478  */ /* end of group DSI_HOST_APB_PKT_IF_Register_Masks */
32479 
32480 
32481 /* DSI_HOST_APB_PKT_IF - Peripheral instance base addresses */
32482 /** Peripheral DSI_HOST_APB_PKT_IF base address */
32483 #define DSI_HOST_APB_PKT_IF_BASE                 (0x4080C280u)
32484 /** Peripheral DSI_HOST_APB_PKT_IF base pointer */
32485 #define DSI_HOST_APB_PKT_IF                      ((DSI_HOST_APB_PKT_IF_Type *)DSI_HOST_APB_PKT_IF_BASE)
32486 /** Array initializer of DSI_HOST_APB_PKT_IF peripheral base addresses */
32487 #define DSI_HOST_APB_PKT_IF_BASE_ADDRS           { DSI_HOST_APB_PKT_IF_BASE }
32488 /** Array initializer of DSI_HOST_APB_PKT_IF peripheral base pointers */
32489 #define DSI_HOST_APB_PKT_IF_BASE_PTRS            { DSI_HOST_APB_PKT_IF }
32490 
32491 /*!
32492  * @}
32493  */ /* end of group DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer */
32494 
32495 
32496 /* ----------------------------------------------------------------------------
32497    -- DSI_HOST_DPI_INTFC Peripheral Access Layer
32498    ---------------------------------------------------------------------------- */
32499 
32500 /*!
32501  * @addtogroup DSI_HOST_DPI_INTFC_Peripheral_Access_Layer DSI_HOST_DPI_INTFC Peripheral Access Layer
32502  * @{
32503  */
32504 
32505 /** DSI_HOST_DPI_INTFC - Register Layout Typedef */
32506 typedef struct {
32507   __IO uint32_t PIXEL_PAYLOAD_SIZE;                /**< offset: 0x0 */
32508   __IO uint32_t PIXEL_FIFO_SEND_LEVEL;             /**< offset: 0x4 */
32509   __IO uint32_t INTERFACE_COLOR_CODING;            /**< offset: 0x8 */
32510   __IO uint32_t PIXEL_FORMAT;                      /**< offset: 0xC */
32511   __IO uint32_t VSYNC_POLARITY;                    /**< offset: 0x10 */
32512   __IO uint32_t HSYNC_POLARITY;                    /**< offset: 0x14 */
32513   __IO uint32_t VIDEO_MODE;                        /**< offset: 0x18 */
32514   __IO uint32_t HFP;                               /**< offset: 0x1C */
32515   __IO uint32_t HBP;                               /**< offset: 0x20 */
32516   __IO uint32_t HSA;                               /**< offset: 0x24 */
32517   __IO uint32_t ENABLE_MULT_PKTS;                  /**< offset: 0x28 */
32518   __IO uint32_t VBP;                               /**< offset: 0x2C */
32519   __IO uint32_t VFP;                               /**< offset: 0x30 */
32520   __IO uint32_t BLLP_MODE;                         /**< offset: 0x34 */
32521   __IO uint32_t USE_NULL_PKT_BLLP;                 /**< offset: 0x38 */
32522   __IO uint32_t VACTIVE;                           /**< offset: 0x3C */
32523 } DSI_HOST_DPI_INTFC_Type;
32524 
32525 /* ----------------------------------------------------------------------------
32526    -- DSI_HOST_DPI_INTFC Register Masks
32527    ---------------------------------------------------------------------------- */
32528 
32529 /*!
32530  * @addtogroup DSI_HOST_DPI_INTFC_Register_Masks DSI_HOST_DPI_INTFC Register Masks
32531  * @{
32532  */
32533 
32534 /*! @name PIXEL_PAYLOAD_SIZE -  */
32535 /*! @{ */
32536 
32537 #define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK (0xFFFFU)
32538 #define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT (0U)
32539 /*! PAYLOAD_SIZE - Maximum number of pixels that should be sent as one DSI packet. Recommended to be
32540  *    evenly divisible by the line size (in pixels).
32541  */
32542 #define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK)
32543 /*! @} */
32544 
32545 /*! @name PIXEL_FIFO_SEND_LEVEL -  */
32546 /*! @{ */
32547 
32548 #define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK (0xFFFFU)
32549 #define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT (0U)
32550 /*! FIFO_SEND_LEVEL - In order to optimize DSI utility, the DPI bridge buffers a certain number of
32551  *    DPI pixels before initiating a DSI packet. This configuration port controls the level at which
32552  *    the DPI Host bridge begins sending pixels.
32553  */
32554 #define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK)
32555 /*! @} */
32556 
32557 /*! @name INTERFACE_COLOR_CODING -  */
32558 /*! @{ */
32559 
32560 #define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK (0x7U)
32561 #define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT (0U)
32562 /*! RGB_CONFIG - Sets the distribution of RGB bits within the 24-bit d bus, as specified by the DPI specification.
32563  *  0b000..16-bit Configuration 1
32564  *  0b001..16-bit Configuration 2
32565  *  0b010..16-bit Configuration 3
32566  *  0b011..18-bit Configuration 1
32567  *  0b100..18-bit Configuration 2
32568  *  0b101..24-bit
32569  *  0b110, 0b111..Reserved
32570  */
32571 #define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT)) & DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK)
32572 /*! @} */
32573 
32574 /*! @name PIXEL_FORMAT -  */
32575 /*! @{ */
32576 
32577 #define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK (0x3U)
32578 #define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT (0U)
32579 /*! PIXEL_FORMAT - Sets the DSI packet type of the pixels
32580  *  0b00..16 bit
32581  *  0b01..18 bit
32582  *  0b10..18 bit loosely packed
32583  *  0b11..24 bit
32584  */
32585 #define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK)
32586 /*! @} */
32587 
32588 /*! @name VSYNC_POLARITY -  */
32589 /*! @{ */
32590 
32591 #define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK (0x1U)
32592 #define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT (0U)
32593 /*! VSYNC_POLARITY - Sets polarity of dpi_vsync_input
32594  *  0b0..active low
32595  *  0b1..active high
32596  */
32597 #define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK)
32598 /*! @} */
32599 
32600 /*! @name HSYNC_POLARITY -  */
32601 /*! @{ */
32602 
32603 #define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK (0x1U)
32604 #define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT (0U)
32605 /*! HSYNC_POLARITY - Sets polarity of dpi_hsync_input
32606  *  0b0..active low
32607  *  0b1..active high
32608  */
32609 #define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK)
32610 /*! @} */
32611 
32612 /*! @name VIDEO_MODE -  */
32613 /*! @{ */
32614 
32615 #define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK (0x3U)
32616 #define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT (0U)
32617 /*! VIDEO_MODE - Select DSI video mode that the host DPI module should generate packets for.
32618  *  0b00..Non-Burst mode with Sync Pulses
32619  *  0b01..Non-Burst mode with Sync Events
32620  *  0b10..Burst mode
32621  *  0b11..Reserved, not valid
32622  */
32623 #define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT)) & DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK)
32624 /*! @} */
32625 
32626 /*! @name HFP -  */
32627 /*! @{ */
32628 
32629 #define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK (0xFFFFU)
32630 #define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT (0U)
32631 /*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet. */
32632 #define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK)
32633 /*! @} */
32634 
32635 /*! @name HBP -  */
32636 /*! @{ */
32637 
32638 #define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK (0xFFFFU)
32639 #define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT (0U)
32640 /*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet. */
32641 #define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK)
32642 /*! @} */
32643 
32644 /*! @name HSA -  */
32645 /*! @{ */
32646 
32647 #define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK (0xFFFFU)
32648 #define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT (0U)
32649 /*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet. */
32650 #define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE(x)   (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK)
32651 /*! @} */
32652 
32653 /*! @name ENABLE_MULT_PKTS -  */
32654 /*! @{ */
32655 
32656 #define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK (0x1U)
32657 #define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT (0U)
32658 /*! ENABLE_MULT_PKTS - Enable Multiple packets per video line. When enabled,
32659  *    PIXEL_PAYLOAD_SIZE[PAYLOAD_SIZE] must be set to exactly half the size of the video line
32660  *  0b0..Video Line is sent in a single packet
32661  *  0b1..Video Line is sent in two packets
32662  */
32663 #define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT)) & DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK)
32664 /*! @} */
32665 
32666 /*! @name VBP -  */
32667 /*! @{ */
32668 
32669 #define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK    (0xFFU)
32670 #define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT   (0U)
32671 /*! NUM_LINES - Sets the number of lines in the vertical back porch. */
32672 #define DSI_HOST_DPI_INTFC_VBP_NUM_LINES(x)      (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK)
32673 /*! @} */
32674 
32675 /*! @name VFP -  */
32676 /*! @{ */
32677 
32678 #define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK    (0xFFU)
32679 #define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT   (0U)
32680 /*! NUM_LINES - Sets the number of lines in the vertical front porch. */
32681 #define DSI_HOST_DPI_INTFC_VFP_NUM_LINES(x)      (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK)
32682 /*! @} */
32683 
32684 /*! @name BLLP_MODE -  */
32685 /*! @{ */
32686 
32687 #define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK     (0x1U)
32688 #define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT    (0U)
32689 /*! LP - Optimize bllp periods to Low Power mode when possible
32690  *  0b0..Blanking packets are sent during BLLP periods
32691  *  0b1..LP mode is used for BLLP periods
32692  */
32693 #define DSI_HOST_DPI_INTFC_BLLP_MODE_LP(x)       (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT)) & DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK)
32694 /*! @} */
32695 
32696 /*! @name USE_NULL_PKT_BLLP -  */
32697 /*! @{ */
32698 
32699 #define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK (0x1U)
32700 #define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT (0U)
32701 /*! NULL - Selects type of blanking packet to be sent during bllp
32702  *  0b0..Blanking packet used in bllp region 1
32703  *  0b1..Null packet used in bllp region
32704  */
32705 #define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT)) & DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK)
32706 /*! @} */
32707 
32708 /*! @name VACTIVE -  */
32709 /*! @{ */
32710 
32711 #define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK (0x3FFFU)
32712 #define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT (0U)
32713 /*! NUM_LINES - Sets the number of lines in the vertical active aread. */
32714 #define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES(x)  (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK)
32715 /*! @} */
32716 
32717 
32718 /*!
32719  * @}
32720  */ /* end of group DSI_HOST_DPI_INTFC_Register_Masks */
32721 
32722 
32723 /* DSI_HOST_DPI_INTFC - Peripheral instance base addresses */
32724 /** Peripheral DSI_HOST_DPI_INTFC base address */
32725 #define DSI_HOST_DPI_INTFC_BASE                  (0x4080C200u)
32726 /** Peripheral DSI_HOST_DPI_INTFC base pointer */
32727 #define DSI_HOST_DPI_INTFC                       ((DSI_HOST_DPI_INTFC_Type *)DSI_HOST_DPI_INTFC_BASE)
32728 /** Array initializer of DSI_HOST_DPI_INTFC peripheral base addresses */
32729 #define DSI_HOST_DPI_INTFC_BASE_ADDRS            { DSI_HOST_DPI_INTFC_BASE }
32730 /** Array initializer of DSI_HOST_DPI_INTFC peripheral base pointers */
32731 #define DSI_HOST_DPI_INTFC_BASE_PTRS             { DSI_HOST_DPI_INTFC }
32732 
32733 /*!
32734  * @}
32735  */ /* end of group DSI_HOST_DPI_INTFC_Peripheral_Access_Layer */
32736 
32737 
32738 /* ----------------------------------------------------------------------------
32739    -- DSI_HOST_NXP_FDSOI28_DPHY_INTFC Peripheral Access Layer
32740    ---------------------------------------------------------------------------- */
32741 
32742 /*!
32743  * @addtogroup DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Peripheral_Access_Layer DSI_HOST_NXP_FDSOI28_DPHY_INTFC Peripheral Access Layer
32744  * @{
32745  */
32746 
32747 /** DSI_HOST_NXP_FDSOI28_DPHY_INTFC - Register Layout Typedef */
32748 typedef struct {
32749   __IO uint32_t PD_TX;                             /**< offset: 0x0 */
32750   __IO uint32_t M_PRG_HS_PREPARE;                  /**< offset: 0x4 */
32751   __IO uint32_t MC_PRG_HS_PREPARE;                 /**< offset: 0x8 */
32752   __IO uint32_t M_PRG_HS_ZERO;                     /**< offset: 0xC */
32753   __IO uint32_t MC_PRG_HS_ZERO;                    /**< offset: 0x10 */
32754   __IO uint32_t M_PRG_HS_TRAIL;                    /**< offset: 0x14 */
32755   __IO uint32_t MC_PRG_HS_TRAIL;                   /**< offset: 0x18 */
32756   __IO uint32_t PD_PLL;                            /**< offset: 0x1C */
32757   __IO uint32_t TST;                               /**< offset: 0x20 */
32758   __IO uint32_t CN;                                /**< offset: 0x24 */
32759   __IO uint32_t CM;                                /**< offset: 0x28 */
32760   __IO uint32_t CO;                                /**< offset: 0x2C */
32761   __I  uint32_t LOCK;                              /**< offset: 0x30 */
32762   __IO uint32_t LOCK_BYP;                          /**< offset: 0x34 */
32763   __IO uint32_t TX_RCAL;                           /**< offset: 0x38 */
32764   __IO uint32_t AUTO_PD_EN;                        /**< offset: 0x3C */
32765   __IO uint32_t RXLPRP;                            /**< offset: 0x40 */
32766   __IO uint32_t RXCDRP;                            /**< offset: 0x44 */
32767 } DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type;
32768 
32769 /* ----------------------------------------------------------------------------
32770    -- DSI_HOST_NXP_FDSOI28_DPHY_INTFC Register Masks
32771    ---------------------------------------------------------------------------- */
32772 
32773 /*!
32774  * @addtogroup DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Register_Masks DSI_HOST_NXP_FDSOI28_DPHY_INTFC Register Masks
32775  * @{
32776  */
32777 
32778 /*! @name PD_TX -  */
32779 /*! @{ */
32780 
32781 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_MASK (0x1U)
32782 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_SHIFT (0U)
32783 /*! PD_TX - Power Down input for D-PHY
32784  *  0b1..Power Down
32785  *  0b0..Power Up
32786  */
32787 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_MASK)
32788 /*! @} */
32789 
32790 /*! @name M_PRG_HS_PREPARE -  */
32791 /*! @{ */
32792 
32793 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK (0x3U)
32794 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT (0U)
32795 /*! M_PRG_HS_PREPARE - DPHY m_PRG_HS_PREPARE input */
32796 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK)
32797 /*! @} */
32798 
32799 /*! @name MC_PRG_HS_PREPARE -  */
32800 /*! @{ */
32801 
32802 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK (0x1U)
32803 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT (0U)
32804 /*! MC_PRG_HS_PREPARE - DPHY mc_PRG_HS_PREPARE input */
32805 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK)
32806 /*! @} */
32807 
32808 /*! @name M_PRG_HS_ZERO -  */
32809 /*! @{ */
32810 
32811 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK (0x1FU)
32812 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT (0U)
32813 /*! M_PRG_HS_ZERO - DPHY m_PRG_HS_ZERO input */
32814 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK)
32815 /*! @} */
32816 
32817 /*! @name MC_PRG_HS_ZERO -  */
32818 /*! @{ */
32819 
32820 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK (0x3FU)
32821 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT (0U)
32822 /*! MC_PRG_HS_ZERO - DPHY mc_PRG_HS_ZERO input */
32823 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK)
32824 /*! @} */
32825 
32826 /*! @name M_PRG_HS_TRAIL -  */
32827 /*! @{ */
32828 
32829 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK (0xFU)
32830 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT (0U)
32831 /*! M_PRG_HS_TRAIL - DPHY m_PRG_HS_TRAIL input */
32832 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK)
32833 /*! @} */
32834 
32835 /*! @name MC_PRG_HS_TRAIL -  */
32836 /*! @{ */
32837 
32838 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK (0xFU)
32839 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT (0U)
32840 /*! MC_PRG_HS_TRAIL - DPHY mc_PRG_HS_TRAIL input */
32841 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK)
32842 /*! @} */
32843 
32844 /*! @name PD_PLL -  */
32845 /*! @{ */
32846 
32847 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_MASK (0x1U)
32848 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_SHIFT (0U)
32849 /*! PD_PLL - Power-down signal
32850  *  0b1..Power down PLL
32851  *  0b0..Power up PLL
32852  */
32853 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_MASK)
32854 /*! @} */
32855 
32856 /*! @name TST -  */
32857 /*! @{ */
32858 
32859 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_MASK (0x3FU)
32860 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_SHIFT (0U)
32861 /*! TST - Test */
32862 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_MASK)
32863 /*! @} */
32864 
32865 /*! @name CN -  */
32866 /*! @{ */
32867 
32868 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_MASK (0x1FU)
32869 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_SHIFT (0U)
32870 /*! CN - Control N divider */
32871 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_MASK)
32872 /*! @} */
32873 
32874 /*! @name CM -  */
32875 /*! @{ */
32876 
32877 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_MASK (0xFFU)
32878 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_SHIFT (0U)
32879 /*! CM - Control M divider */
32880 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_MASK)
32881 /*! @} */
32882 
32883 /*! @name CO -  */
32884 /*! @{ */
32885 
32886 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_MASK (0x3U)
32887 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_SHIFT (0U)
32888 /*! CO - Control O divider
32889  *  0b00..Divide by 1
32890  *  0b01..Divide by 2
32891  *  0b10..Divide by 4
32892  *  0b11..Divide by 8
32893  */
32894 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_MASK)
32895 /*! @} */
32896 
32897 /*! @name LOCK -  */
32898 /*! @{ */
32899 
32900 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_MASK (0x1U)
32901 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_SHIFT (0U)
32902 /*! LOCK - Lock Detect output
32903  *  0b1..PLL has achieved frequency lock
32904  *  0b0..PLL not locked
32905  */
32906 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_MASK)
32907 /*! @} */
32908 
32909 /*! @name LOCK_BYP -  */
32910 /*! @{ */
32911 
32912 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_MASK (0x1U)
32913 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_SHIFT (0U)
32914 /*! LOCK_BYP - DPHY LOCK_BYP input
32915  *  0b0..PLL LOCK signal will gate TxByteClkHS clock
32916  *  0b1..PLL LOCK signal will not gate TxByteClkHS clock, CIL based counter will be used to gate the TxByteClkHS
32917  */
32918 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_MASK)
32919 /*! @} */
32920 
32921 /*! @name TX_RCAL -  */
32922 /*! @{ */
32923 
32924 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_MASK (0x3U)
32925 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_SHIFT (0U)
32926 /*! TX_RCAL - On-chip termination control bits for manual calibration of HS-TX
32927  *  0b00..20% higher than mid-range. Highest impedance setting
32928  *  0b01..Mid-range impedance setting (default)
32929  *  0b10..15% lower than mid-range
32930  *  0b11..25% lower than mid-range. Lowest impedance setting
32931  */
32932 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_MASK)
32933 /*! @} */
32934 
32935 /*! @name AUTO_PD_EN -  */
32936 /*! @{ */
32937 
32938 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_MASK (0x1U)
32939 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_SHIFT (0U)
32940 /*! AUTO_PD_EN - DPHY AUTO_PD_EN input
32941  *  0b0..Inactive lanes are powered up and driving LP11
32942  *  0b1..inactive lanes are powered down
32943  */
32944 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_MASK)
32945 /*! @} */
32946 
32947 /*! @name RXLPRP -  */
32948 /*! @{ */
32949 
32950 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_MASK (0x3U)
32951 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_SHIFT (0U)
32952 /*! RXLPRP - DPHY RXLPRP input */
32953 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_MASK)
32954 /*! @} */
32955 
32956 /*! @name RXCDRP -  */
32957 /*! @{ */
32958 
32959 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_MASK (0x3U)
32960 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_SHIFT (0U)
32961 /*! RXCDRP - DPHY RXCDRP input
32962  *  0b00..344mV
32963  *  0b01..325mV (Default)
32964  *  0b10..307mV
32965  *  0b11..Invalid
32966  */
32967 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_MASK)
32968 /*! @} */
32969 
32970 
32971 /*!
32972  * @}
32973  */ /* end of group DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Register_Masks */
32974 
32975 
32976 /* DSI_HOST_NXP_FDSOI28_DPHY_INTFC - Peripheral instance base addresses */
32977 /** Peripheral DSI_HOST_DPHY_INTFC base address */
32978 #define DSI_HOST_DPHY_INTFC_BASE                 (0x4080C300u)
32979 /** Peripheral DSI_HOST_DPHY_INTFC base pointer */
32980 #define DSI_HOST_DPHY_INTFC                      ((DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type *)DSI_HOST_DPHY_INTFC_BASE)
32981 /** Array initializer of DSI_HOST_NXP_FDSOI28_DPHY_INTFC peripheral base
32982  * addresses */
32983 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_ADDRS { DSI_HOST_DPHY_INTFC_BASE }
32984 /** Array initializer of DSI_HOST_NXP_FDSOI28_DPHY_INTFC peripheral base
32985  * pointers */
32986 #define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_PTRS { DSI_HOST_DPHY_INTFC }
32987 
32988 /*!
32989  * @}
32990  */ /* end of group DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Peripheral_Access_Layer */
32991 
32992 
32993 /* ----------------------------------------------------------------------------
32994    -- EMVSIM Peripheral Access Layer
32995    ---------------------------------------------------------------------------- */
32996 
32997 /*!
32998  * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
32999  * @{
33000  */
33001 
33002 /** EMVSIM - Register Layout Typedef */
33003 typedef struct {
33004   __I  uint32_t VER_ID;                            /**< Version ID Register, offset: 0x0 */
33005   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
33006   __IO uint32_t CLKCFG;                            /**< Clock Configuration Register, offset: 0x8 */
33007   __IO uint32_t DIVISOR;                           /**< Baud Rate Divisor Register, offset: 0xC */
33008   __IO uint32_t CTRL;                              /**< Control Register, offset: 0x10 */
33009   __IO uint32_t INT_MASK;                          /**< Interrupt Mask Register, offset: 0x14 */
33010   __IO uint32_t RX_THD;                            /**< Receiver Threshold Register, offset: 0x18 */
33011   __IO uint32_t TX_THD;                            /**< Transmitter Threshold Register, offset: 0x1C */
33012   __IO uint32_t RX_STATUS;                         /**< Receive Status Register, offset: 0x20 */
33013   __IO uint32_t TX_STATUS;                         /**< Transmitter Status Register, offset: 0x24 */
33014   __IO uint32_t PCSR;                              /**< Port Control and Status Register, offset: 0x28 */
33015   __I  uint32_t RX_BUF;                            /**< Receive Data Read Buffer, offset: 0x2C */
33016   __O  uint32_t TX_BUF;                            /**< Transmit Data Buffer, offset: 0x30 */
33017   __IO uint32_t TX_GETU;                           /**< Transmitter Guard ETU Value Register, offset: 0x34 */
33018   __IO uint32_t CWT_VAL;                           /**< Character Wait Time Value Register, offset: 0x38 */
33019   __IO uint32_t BWT_VAL;                           /**< Block Wait Time Value Register, offset: 0x3C */
33020   __IO uint32_t BGT_VAL;                           /**< Block Guard Time Value Register, offset: 0x40 */
33021   __IO uint32_t GPCNT0_VAL;                        /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */
33022   __IO uint32_t GPCNT1_VAL;                        /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
33023 } EMVSIM_Type;
33024 
33025 /* ----------------------------------------------------------------------------
33026    -- EMVSIM Register Masks
33027    ---------------------------------------------------------------------------- */
33028 
33029 /*!
33030  * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
33031  * @{
33032  */
33033 
33034 /*! @name VER_ID - Version ID Register */
33035 /*! @{ */
33036 
33037 #define EMVSIM_VER_ID_VER_MASK                   (0xFFFFFFFFU)
33038 #define EMVSIM_VER_ID_VER_SHIFT                  (0U)
33039 /*! VER - Version ID of the module */
33040 #define EMVSIM_VER_ID_VER(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
33041 /*! @} */
33042 
33043 /*! @name PARAM - Parameter Register */
33044 /*! @{ */
33045 
33046 #define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK          (0xFFU)
33047 #define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT         (0U)
33048 /*! RX_FIFO_DEPTH - Receive FIFO Depth */
33049 #define EMVSIM_PARAM_RX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
33050 
33051 #define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK          (0xFF00U)
33052 #define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT         (8U)
33053 /*! TX_FIFO_DEPTH - Transmit FIFO Depth */
33054 #define EMVSIM_PARAM_TX_FIFO_DEPTH(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
33055 /*! @} */
33056 
33057 /*! @name CLKCFG - Clock Configuration Register */
33058 /*! @{ */
33059 
33060 #define EMVSIM_CLKCFG_CLK_PRSC_MASK              (0xFFU)
33061 #define EMVSIM_CLKCFG_CLK_PRSC_SHIFT             (0U)
33062 /*! CLK_PRSC - Clock Prescaler Value */
33063 #define EMVSIM_CLKCFG_CLK_PRSC(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
33064 
33065 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK        (0x300U)
33066 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT       (8U)
33067 /*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select
33068  *  0b00..Disabled / Reset
33069  *  0b01..Card Clock
33070  *  0b10..Receive Clock
33071  *  0b11..ETU Clock (transmit clock)
33072  */
33073 #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
33074 
33075 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK        (0xC00U)
33076 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT       (10U)
33077 /*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select
33078  *  0b00..Disabled / Reset
33079  *  0b01..Card Clock
33080  *  0b10..Receive Clock
33081  *  0b11..ETU Clock (transmit clock)
33082  */
33083 #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
33084 /*! @} */
33085 
33086 /*! @name DIVISOR - Baud Rate Divisor Register */
33087 /*! @{ */
33088 
33089 #define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK        (0x1FFU)
33090 #define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT       (0U)
33091 /*! DIVISOR_VALUE - Divisor (F/D) Value
33092  *  0b000000000-0b000000100..Invalid. As per ISO 7816 specification, minimum value of F/D is 5
33093  *  0b000000101-0b011111111..Divisor value F/D
33094  */
33095 #define EMVSIM_DIVISOR_DIVISOR_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
33096 /*! @} */
33097 
33098 /*! @name CTRL - Control Register */
33099 /*! @{ */
33100 
33101 #define EMVSIM_CTRL_IC_MASK                      (0x1U)
33102 #define EMVSIM_CTRL_IC_SHIFT                     (0U)
33103 /*! IC - Inverse Convention
33104  *  0b0..Direction convention transfers enabled
33105  *  0b1..Inverse convention transfers enabled
33106  */
33107 #define EMVSIM_CTRL_IC(x)                        (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
33108 
33109 #define EMVSIM_CTRL_ICM_MASK                     (0x2U)
33110 #define EMVSIM_CTRL_ICM_SHIFT                    (1U)
33111 /*! ICM - Initial Character Mode
33112  *  0b0..Initial Character Mode disabled
33113  *  0b1..Initial Character Mode enabled
33114  */
33115 #define EMVSIM_CTRL_ICM(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
33116 
33117 #define EMVSIM_CTRL_ANACK_MASK                   (0x4U)
33118 #define EMVSIM_CTRL_ANACK_SHIFT                  (2U)
33119 /*! ANACK - Auto NACK Enable
33120  *  0b0..NACK generation on errors disabled
33121  *  0b1..NACK generation on errors enabled
33122  */
33123 #define EMVSIM_CTRL_ANACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
33124 
33125 #define EMVSIM_CTRL_ONACK_MASK                   (0x8U)
33126 #define EMVSIM_CTRL_ONACK_SHIFT                  (3U)
33127 /*! ONACK - Overrun NACK Enable
33128  *  0b0..NACK generation on overrun is disabled
33129  *  0b1..NACK generation on overrun is enabled
33130  */
33131 #define EMVSIM_CTRL_ONACK(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
33132 
33133 #define EMVSIM_CTRL_FLSH_RX_MASK                 (0x100U)
33134 #define EMVSIM_CTRL_FLSH_RX_SHIFT                (8U)
33135 /*! FLSH_RX - Flush Receiver Bit
33136  *  0b0..EMVSIM Receiver normal operation
33137  *  0b1..EMVSIM Receiver held in Reset
33138  */
33139 #define EMVSIM_CTRL_FLSH_RX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
33140 
33141 #define EMVSIM_CTRL_FLSH_TX_MASK                 (0x200U)
33142 #define EMVSIM_CTRL_FLSH_TX_SHIFT                (9U)
33143 /*! FLSH_TX - Flush Transmitter Bit
33144  *  0b0..EMVSIM Transmitter normal operation
33145  *  0b1..EMVSIM Transmitter held in Reset
33146  */
33147 #define EMVSIM_CTRL_FLSH_TX(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
33148 
33149 #define EMVSIM_CTRL_SW_RST_MASK                  (0x400U)
33150 #define EMVSIM_CTRL_SW_RST_SHIFT                 (10U)
33151 /*! SW_RST - Software Reset Bit
33152  *  0b0..EMVSIM Normal operation
33153  *  0b1..EMVSIM held in Reset
33154  */
33155 #define EMVSIM_CTRL_SW_RST(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
33156 
33157 #define EMVSIM_CTRL_KILL_CLOCKS_MASK             (0x800U)
33158 #define EMVSIM_CTRL_KILL_CLOCKS_SHIFT            (11U)
33159 /*! KILL_CLOCKS - Kill all internal clocks
33160  *  0b0..EMVSIM input clock enabled
33161  *  0b1..EMVSIM input clock is disabled
33162  */
33163 #define EMVSIM_CTRL_KILL_CLOCKS(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
33164 
33165 #define EMVSIM_CTRL_DOZE_EN_MASK                 (0x1000U)
33166 #define EMVSIM_CTRL_DOZE_EN_SHIFT                (12U)
33167 /*! DOZE_EN - Doze Enable
33168  *  0b0..DOZE instruction gates all internal EMVSIM clocks as well as the Smart Card clock when the transmit FIFO is empty
33169  *  0b1..DOZE instruction has no effect on EMVSIM module
33170  */
33171 #define EMVSIM_CTRL_DOZE_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
33172 
33173 #define EMVSIM_CTRL_STOP_EN_MASK                 (0x2000U)
33174 #define EMVSIM_CTRL_STOP_EN_SHIFT                (13U)
33175 /*! STOP_EN - STOP Enable
33176  *  0b0..STOP instruction shuts down all EMVSIM clocks
33177  *  0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card)
33178  */
33179 #define EMVSIM_CTRL_STOP_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
33180 
33181 #define EMVSIM_CTRL_RCV_EN_MASK                  (0x10000U)
33182 #define EMVSIM_CTRL_RCV_EN_SHIFT                 (16U)
33183 /*! RCV_EN - Receiver Enable
33184  *  0b0..EMVSIM Receiver disabled
33185  *  0b1..EMVSIM Receiver enabled
33186  */
33187 #define EMVSIM_CTRL_RCV_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
33188 
33189 #define EMVSIM_CTRL_XMT_EN_MASK                  (0x20000U)
33190 #define EMVSIM_CTRL_XMT_EN_SHIFT                 (17U)
33191 /*! XMT_EN - Transmitter Enable
33192  *  0b0..EMVSIM Transmitter disabled
33193  *  0b1..EMVSIM Transmitter enabled
33194  */
33195 #define EMVSIM_CTRL_XMT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
33196 
33197 #define EMVSIM_CTRL_RCVR_11_MASK                 (0x40000U)
33198 #define EMVSIM_CTRL_RCVR_11_SHIFT                (18U)
33199 /*! RCVR_11 - Receiver 11 ETU Mode Enable
33200  *  0b0..Receiver configured for 12 ETU operation mode
33201  *  0b1..Receiver configured for 11 ETU operation mode
33202  */
33203 #define EMVSIM_CTRL_RCVR_11(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
33204 
33205 #define EMVSIM_CTRL_RX_DMA_EN_MASK               (0x80000U)
33206 #define EMVSIM_CTRL_RX_DMA_EN_SHIFT              (19U)
33207 /*! RX_DMA_EN - Receive DMA Enable
33208  *  0b0..No DMA Read Request asserted for Receiver
33209  *  0b1..DMA Read Request asserted for Receiver
33210  */
33211 #define EMVSIM_CTRL_RX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
33212 
33213 #define EMVSIM_CTRL_TX_DMA_EN_MASK               (0x100000U)
33214 #define EMVSIM_CTRL_TX_DMA_EN_SHIFT              (20U)
33215 /*! TX_DMA_EN - Transmit DMA Enable
33216  *  0b0..No DMA Write Request asserted for Transmitter
33217  *  0b1..DMA Write Request asserted for Transmitter
33218  */
33219 #define EMVSIM_CTRL_TX_DMA_EN(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
33220 
33221 #define EMVSIM_CTRL_INV_CRC_VAL_MASK             (0x1000000U)
33222 #define EMVSIM_CTRL_INV_CRC_VAL_SHIFT            (24U)
33223 /*! INV_CRC_VAL - Invert bits in the CRC Output Value
33224  *  0b0..Bits in CRC Output value are not inverted.
33225  *  0b1..Bits in CRC Output value are inverted.
33226  */
33227 #define EMVSIM_CTRL_INV_CRC_VAL(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
33228 
33229 #define EMVSIM_CTRL_CRC_OUT_FLIP_MASK            (0x2000000U)
33230 #define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT           (25U)
33231 /*! CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip
33232  *  0b0..Bits within the CRC output bytes are not reversed i.e. 15:0 remains 15:0
33233  *  0b1..Bits within the CRC output bytes are reversed i.e. 15:0 becomes {8:15,0:7}
33234  */
33235 #define EMVSIM_CTRL_CRC_OUT_FLIP(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
33236 
33237 #define EMVSIM_CTRL_CRC_IN_FLIP_MASK             (0x4000000U)
33238 #define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT            (26U)
33239 /*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control
33240  *  0b0..Bits in the input byte are not reversed (i.e. 7:0 remain 7:0) before the CRC calculation
33241  *  0b1..Bits in the input byte are reversed (i.e. 7:0 becomes 0:7) before CRC calculation
33242  */
33243 #define EMVSIM_CTRL_CRC_IN_FLIP(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
33244 
33245 #define EMVSIM_CTRL_CWT_EN_MASK                  (0x8000000U)
33246 #define EMVSIM_CTRL_CWT_EN_SHIFT                 (27U)
33247 /*! CWT_EN - Character Wait Time Counter Enable
33248  *  0b0..Character Wait time Counter is disabled
33249  *  0b1..Character Wait time counter is enabled
33250  */
33251 #define EMVSIM_CTRL_CWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
33252 
33253 #define EMVSIM_CTRL_LRC_EN_MASK                  (0x10000000U)
33254 #define EMVSIM_CTRL_LRC_EN_SHIFT                 (28U)
33255 /*! LRC_EN - LRC Enable
33256  *  0b0..8-bit Linear Redundancy Checking disabled
33257  *  0b1..8-bit Linear Redundancy Checking enabled
33258  */
33259 #define EMVSIM_CTRL_LRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
33260 
33261 #define EMVSIM_CTRL_CRC_EN_MASK                  (0x20000000U)
33262 #define EMVSIM_CTRL_CRC_EN_SHIFT                 (29U)
33263 /*! CRC_EN - CRC Enable
33264  *  0b0..16-bit Cyclic Redundancy Checking disabled
33265  *  0b1..16-bit Cyclic Redundancy Checking enabled
33266  */
33267 #define EMVSIM_CTRL_CRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
33268 
33269 #define EMVSIM_CTRL_XMT_CRC_LRC_MASK             (0x40000000U)
33270 #define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT            (30U)
33271 /*! XMT_CRC_LRC - Transmit CRC or LRC Enable
33272  *  0b0..No CRC or LRC value is transmitted
33273  *  0b1..Transmit LRC or CRC info when FIFO empties (whichever is enabled)
33274  */
33275 #define EMVSIM_CTRL_XMT_CRC_LRC(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
33276 
33277 #define EMVSIM_CTRL_BWT_EN_MASK                  (0x80000000U)
33278 #define EMVSIM_CTRL_BWT_EN_SHIFT                 (31U)
33279 /*! BWT_EN - Block Wait Time Counter Enable
33280  *  0b0..Disable BWT, BGT Counters
33281  *  0b1..Enable BWT, BGT Counters
33282  */
33283 #define EMVSIM_CTRL_BWT_EN(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
33284 /*! @} */
33285 
33286 /*! @name INT_MASK - Interrupt Mask Register */
33287 /*! @{ */
33288 
33289 #define EMVSIM_INT_MASK_RDT_IM_MASK              (0x1U)
33290 #define EMVSIM_INT_MASK_RDT_IM_SHIFT             (0U)
33291 /*! RDT_IM - Receive Data Threshold Interrupt Mask
33292  *  0b0..RDTF interrupt enabled
33293  *  0b1..RDTF interrupt masked
33294  */
33295 #define EMVSIM_INT_MASK_RDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
33296 
33297 #define EMVSIM_INT_MASK_TC_IM_MASK               (0x2U)
33298 #define EMVSIM_INT_MASK_TC_IM_SHIFT              (1U)
33299 /*! TC_IM - Transmit Complete Interrupt Mask
33300  *  0b0..TCF interrupt enabled
33301  *  0b1..TCF interrupt masked
33302  */
33303 #define EMVSIM_INT_MASK_TC_IM(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
33304 
33305 #define EMVSIM_INT_MASK_RFO_IM_MASK              (0x4U)
33306 #define EMVSIM_INT_MASK_RFO_IM_SHIFT             (2U)
33307 /*! RFO_IM - Receive FIFO Overflow Interrupt Mask
33308  *  0b0..RFO interrupt enabled
33309  *  0b1..RFO interrupt masked
33310  */
33311 #define EMVSIM_INT_MASK_RFO_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
33312 
33313 #define EMVSIM_INT_MASK_ETC_IM_MASK              (0x8U)
33314 #define EMVSIM_INT_MASK_ETC_IM_SHIFT             (3U)
33315 /*! ETC_IM - Early Transmit Complete Interrupt Mask
33316  *  0b0..ETC interrupt enabled
33317  *  0b1..ETC interrupt masked
33318  */
33319 #define EMVSIM_INT_MASK_ETC_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
33320 
33321 #define EMVSIM_INT_MASK_TFE_IM_MASK              (0x10U)
33322 #define EMVSIM_INT_MASK_TFE_IM_SHIFT             (4U)
33323 /*! TFE_IM - Transmit FIFO Empty Interrupt Mask
33324  *  0b0..TFE interrupt enabled
33325  *  0b1..TFE interrupt masked
33326  */
33327 #define EMVSIM_INT_MASK_TFE_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
33328 
33329 #define EMVSIM_INT_MASK_TNACK_IM_MASK            (0x20U)
33330 #define EMVSIM_INT_MASK_TNACK_IM_SHIFT           (5U)
33331 /*! TNACK_IM - Transmit NACK Threshold Interrupt Mask
33332  *  0b0..TNTE interrupt enabled
33333  *  0b1..TNTE interrupt masked
33334  */
33335 #define EMVSIM_INT_MASK_TNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
33336 
33337 #define EMVSIM_INT_MASK_TFF_IM_MASK              (0x40U)
33338 #define EMVSIM_INT_MASK_TFF_IM_SHIFT             (6U)
33339 /*! TFF_IM - Transmit FIFO Full Interrupt Mask
33340  *  0b0..TFF interrupt enabled
33341  *  0b1..TFF interrupt masked
33342  */
33343 #define EMVSIM_INT_MASK_TFF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
33344 
33345 #define EMVSIM_INT_MASK_TDT_IM_MASK              (0x80U)
33346 #define EMVSIM_INT_MASK_TDT_IM_SHIFT             (7U)
33347 /*! TDT_IM - Transmit Data Threshold Interrupt Mask
33348  *  0b0..TDTF interrupt enabled
33349  *  0b1..TDTF interrupt masked
33350  */
33351 #define EMVSIM_INT_MASK_TDT_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
33352 
33353 #define EMVSIM_INT_MASK_GPCNT0_IM_MASK           (0x100U)
33354 #define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT          (8U)
33355 /*! GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask
33356  *  0b0..GPCNT0_TO interrupt enabled
33357  *  0b1..GPCNT0_TO interrupt masked
33358  */
33359 #define EMVSIM_INT_MASK_GPCNT0_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
33360 
33361 #define EMVSIM_INT_MASK_CWT_ERR_IM_MASK          (0x200U)
33362 #define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT         (9U)
33363 /*! CWT_ERR_IM - Character Wait Time Error Interrupt Mask
33364  *  0b0..CWT_ERR interrupt enabled
33365  *  0b1..CWT_ERR interrupt masked
33366  */
33367 #define EMVSIM_INT_MASK_CWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
33368 
33369 #define EMVSIM_INT_MASK_RNACK_IM_MASK            (0x400U)
33370 #define EMVSIM_INT_MASK_RNACK_IM_SHIFT           (10U)
33371 /*! RNACK_IM - Receiver NACK Threshold Interrupt Mask
33372  *  0b0..RTE interrupt enabled
33373  *  0b1..RTE interrupt masked
33374  */
33375 #define EMVSIM_INT_MASK_RNACK_IM(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
33376 
33377 #define EMVSIM_INT_MASK_BWT_ERR_IM_MASK          (0x800U)
33378 #define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT         (11U)
33379 /*! BWT_ERR_IM - Block Wait Time Error Interrupt Mask
33380  *  0b0..BWT_ERR interrupt enabled
33381  *  0b1..BWT_ERR interrupt masked
33382  */
33383 #define EMVSIM_INT_MASK_BWT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
33384 
33385 #define EMVSIM_INT_MASK_BGT_ERR_IM_MASK          (0x1000U)
33386 #define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT         (12U)
33387 /*! BGT_ERR_IM - Block Guard Time Error Interrupt
33388  *  0b0..BGT_ERR interrupt enabled
33389  *  0b1..BGT_ERR interrupt masked
33390  */
33391 #define EMVSIM_INT_MASK_BGT_ERR_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
33392 
33393 #define EMVSIM_INT_MASK_GPCNT1_IM_MASK           (0x2000U)
33394 #define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT          (13U)
33395 /*! GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask
33396  *  0b0..GPCNT1_TO interrupt enabled
33397  *  0b1..GPCNT1_TO interrupt masked
33398  */
33399 #define EMVSIM_INT_MASK_GPCNT1_IM(x)             (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
33400 
33401 #define EMVSIM_INT_MASK_RX_DATA_IM_MASK          (0x4000U)
33402 #define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT         (14U)
33403 /*! RX_DATA_IM - Receive Data Interrupt Mask
33404  *  0b0..RX_DATA interrupt enabled
33405  *  0b1..RX_DATA interrupt masked
33406  */
33407 #define EMVSIM_INT_MASK_RX_DATA_IM(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
33408 
33409 #define EMVSIM_INT_MASK_PEF_IM_MASK              (0x8000U)
33410 #define EMVSIM_INT_MASK_PEF_IM_SHIFT             (15U)
33411 /*! PEF_IM - Parity Error Interrupt Mask
33412  *  0b0..PEF interrupt enabled
33413  *  0b1..PEF interrupt masked
33414  */
33415 #define EMVSIM_INT_MASK_PEF_IM(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
33416 /*! @} */
33417 
33418 /*! @name RX_THD - Receiver Threshold Register */
33419 /*! @{ */
33420 
33421 #define EMVSIM_RX_THD_RDT_MASK                   (0xFU)
33422 #define EMVSIM_RX_THD_RDT_SHIFT                  (0U)
33423 /*! RDT - Receiver Data Threshold Value */
33424 #define EMVSIM_RX_THD_RDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
33425 
33426 #define EMVSIM_RX_THD_RNCK_THD_MASK              (0xF00U)
33427 #define EMVSIM_RX_THD_RNCK_THD_SHIFT             (8U)
33428 /*! RNCK_THD - Receiver NACK Threshold Value */
33429 #define EMVSIM_RX_THD_RNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)
33430 /*! @} */
33431 
33432 /*! @name TX_THD - Transmitter Threshold Register */
33433 /*! @{ */
33434 
33435 #define EMVSIM_TX_THD_TDT_MASK                   (0xFU)
33436 #define EMVSIM_TX_THD_TDT_SHIFT                  (0U)
33437 /*! TDT - Transmitter Data Threshold Value */
33438 #define EMVSIM_TX_THD_TDT(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
33439 
33440 #define EMVSIM_TX_THD_TNCK_THD_MASK              (0xF00U)
33441 #define EMVSIM_TX_THD_TNCK_THD_SHIFT             (8U)
33442 /*! TNCK_THD - Transmitter NACK Threshold Value */
33443 #define EMVSIM_TX_THD_TNCK_THD(x)                (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)
33444 /*! @} */
33445 
33446 /*! @name RX_STATUS - Receive Status Register */
33447 /*! @{ */
33448 
33449 #define EMVSIM_RX_STATUS_RFO_MASK                (0x1U)
33450 #define EMVSIM_RX_STATUS_RFO_SHIFT               (0U)
33451 /*! RFO - Receive FIFO Overflow Flag
33452  *  0b0..No overrun error has occurred
33453  *  0b1..A byte was received when the received FIFO was already full
33454  */
33455 #define EMVSIM_RX_STATUS_RFO(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
33456 
33457 #define EMVSIM_RX_STATUS_RX_DATA_MASK            (0x10U)
33458 #define EMVSIM_RX_STATUS_RX_DATA_SHIFT           (4U)
33459 /*! RX_DATA - Receive Data Interrupt Flag
33460  *  0b0..No new byte is received
33461  *  0b1..New byte is received ans stored in Receive FIFO
33462  */
33463 #define EMVSIM_RX_STATUS_RX_DATA(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
33464 
33465 #define EMVSIM_RX_STATUS_RDTF_MASK               (0x20U)
33466 #define EMVSIM_RX_STATUS_RDTF_SHIFT              (5U)
33467 /*! RDTF - Receive Data Threshold Interrupt Flag
33468  *  0b0..Number of unread bytes in receive FIFO less than the value set by RDT
33469  *  0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT.
33470  */
33471 #define EMVSIM_RX_STATUS_RDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
33472 
33473 #define EMVSIM_RX_STATUS_LRC_OK_MASK             (0x40U)
33474 #define EMVSIM_RX_STATUS_LRC_OK_SHIFT            (6U)
33475 /*! LRC_OK - LRC Check OK Flag
33476  *  0b0..Current LRC value does not match remainder.
33477  *  0b1..Current calculated LRC value matches the expected result (i.e. zero).
33478  */
33479 #define EMVSIM_RX_STATUS_LRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
33480 
33481 #define EMVSIM_RX_STATUS_CRC_OK_MASK             (0x80U)
33482 #define EMVSIM_RX_STATUS_CRC_OK_SHIFT            (7U)
33483 /*! CRC_OK - CRC Check OK Flag
33484  *  0b0..Current CRC value does not match remainder.
33485  *  0b1..Current calculated CRC value matches the expected result.
33486  */
33487 #define EMVSIM_RX_STATUS_CRC_OK(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
33488 
33489 #define EMVSIM_RX_STATUS_CWT_ERR_MASK            (0x100U)
33490 #define EMVSIM_RX_STATUS_CWT_ERR_SHIFT           (8U)
33491 /*! CWT_ERR - Character Wait Time Error Flag
33492  *  0b0..No CWT violation has occurred
33493  *  0b1..Time between two consecutive characters has exceeded the value in CWT_VAL.
33494  */
33495 #define EMVSIM_RX_STATUS_CWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
33496 
33497 #define EMVSIM_RX_STATUS_RTE_MASK                (0x200U)
33498 #define EMVSIM_RX_STATUS_RTE_SHIFT               (9U)
33499 /*! RTE - Received NACK Threshold Error Flag
33500  *  0b0..Number of NACKs generated by the receiver is less than the value programmed in RNCK_THD
33501  *  0b1..Number of NACKs generated by the receiver is equal to the value programmed in RNCK_THD
33502  */
33503 #define EMVSIM_RX_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
33504 
33505 #define EMVSIM_RX_STATUS_BWT_ERR_MASK            (0x400U)
33506 #define EMVSIM_RX_STATUS_BWT_ERR_SHIFT           (10U)
33507 /*! BWT_ERR - Block Wait Time Error Flag
33508  *  0b0..Block wait time not exceeded
33509  *  0b1..Block wait time was exceeded
33510  */
33511 #define EMVSIM_RX_STATUS_BWT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
33512 
33513 #define EMVSIM_RX_STATUS_BGT_ERR_MASK            (0x800U)
33514 #define EMVSIM_RX_STATUS_BGT_ERR_SHIFT           (11U)
33515 /*! BGT_ERR - Block Guard Time Error Flag
33516  *  0b0..Block guard time was sufficient
33517  *  0b1..Block guard time was too small
33518  */
33519 #define EMVSIM_RX_STATUS_BGT_ERR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
33520 
33521 #define EMVSIM_RX_STATUS_PEF_MASK                (0x1000U)
33522 #define EMVSIM_RX_STATUS_PEF_SHIFT               (12U)
33523 /*! PEF - Parity Error Flag
33524  *  0b0..No parity error detected
33525  *  0b1..Parity error detected
33526  */
33527 #define EMVSIM_RX_STATUS_PEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
33528 
33529 #define EMVSIM_RX_STATUS_FEF_MASK                (0x2000U)
33530 #define EMVSIM_RX_STATUS_FEF_SHIFT               (13U)
33531 /*! FEF - Frame Error Flag
33532  *  0b0..No frame error detected
33533  *  0b1..Frame error detected
33534  */
33535 #define EMVSIM_RX_STATUS_FEF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
33536 
33537 #define EMVSIM_RX_STATUS_RX_WPTR_MASK            (0xF0000U)
33538 #define EMVSIM_RX_STATUS_RX_WPTR_SHIFT           (16U)
33539 /*! RX_WPTR - Receive FIFO Write Pointer Value */
33540 #define EMVSIM_RX_STATUS_RX_WPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
33541 
33542 #define EMVSIM_RX_STATUS_RX_CNT_MASK             (0xF000000U)
33543 #define EMVSIM_RX_STATUS_RX_CNT_SHIFT            (24U)
33544 /*! RX_CNT - Receive FIFO Byte Count
33545  *  0b0000..FIFO is emtpy
33546  */
33547 #define EMVSIM_RX_STATUS_RX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)
33548 /*! @} */
33549 
33550 /*! @name TX_STATUS - Transmitter Status Register */
33551 /*! @{ */
33552 
33553 #define EMVSIM_TX_STATUS_TNTE_MASK               (0x1U)
33554 #define EMVSIM_TX_STATUS_TNTE_SHIFT              (0U)
33555 /*! TNTE - Transmit NACK Threshold Error Flag
33556  *  0b0..Transmit NACK threshold has not been reached
33557  *  0b1..Transmit NACK threshold reached; transmitter frozen
33558  */
33559 #define EMVSIM_TX_STATUS_TNTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
33560 
33561 #define EMVSIM_TX_STATUS_TFE_MASK                (0x8U)
33562 #define EMVSIM_TX_STATUS_TFE_SHIFT               (3U)
33563 /*! TFE - Transmit FIFO Empty Flag
33564  *  0b0..Transmit FIFO is not empty
33565  *  0b1..Transmit FIFO is empty
33566  */
33567 #define EMVSIM_TX_STATUS_TFE(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
33568 
33569 #define EMVSIM_TX_STATUS_ETCF_MASK               (0x10U)
33570 #define EMVSIM_TX_STATUS_ETCF_SHIFT              (4U)
33571 /*! ETCF - Early Transmit Complete Flag
33572  *  0b0..Transmit pending or in progress
33573  *  0b1..Transmit complete
33574  */
33575 #define EMVSIM_TX_STATUS_ETCF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
33576 
33577 #define EMVSIM_TX_STATUS_TCF_MASK                (0x20U)
33578 #define EMVSIM_TX_STATUS_TCF_SHIFT               (5U)
33579 /*! TCF - Transmit Complete Flag
33580  *  0b0..Transmit pending or in progress
33581  *  0b1..Transmit complete
33582  */
33583 #define EMVSIM_TX_STATUS_TCF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
33584 
33585 #define EMVSIM_TX_STATUS_TFF_MASK                (0x40U)
33586 #define EMVSIM_TX_STATUS_TFF_SHIFT               (6U)
33587 /*! TFF - Transmit FIFO Full Flag
33588  *  0b0..Transmit FIFO Full condition has not occurred
33589  *  0b1..A Transmit FIFO Full condition has occurred
33590  */
33591 #define EMVSIM_TX_STATUS_TFF(x)                  (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
33592 
33593 #define EMVSIM_TX_STATUS_TDTF_MASK               (0x80U)
33594 #define EMVSIM_TX_STATUS_TDTF_SHIFT              (7U)
33595 /*! TDTF - Transmit Data Threshold Flag
33596  *  0b0..Number of bytes in FIFO is greater than TDT, or bit has been cleared
33597  *  0b1..Number of bytes in FIFO is less than or equal to TDT
33598  */
33599 #define EMVSIM_TX_STATUS_TDTF(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
33600 
33601 #define EMVSIM_TX_STATUS_GPCNT0_TO_MASK          (0x100U)
33602 #define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT         (8U)
33603 /*! GPCNT0_TO - General Purpose Counter 0 Timeout Flag
33604  *  0b0..GPCNT0 time not reached, or bit has been cleared.
33605  *  0b1..General Purpose counter has reached the GPCNT0 value
33606  */
33607 #define EMVSIM_TX_STATUS_GPCNT0_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
33608 
33609 #define EMVSIM_TX_STATUS_GPCNT1_TO_MASK          (0x200U)
33610 #define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT         (9U)
33611 /*! GPCNT1_TO - General Purpose Counter 1 Timeout Flag
33612  *  0b0..GPCNT1 time not reached, or bit has been cleared.
33613  *  0b1..General Purpose counter has reached the GPCNT1 value
33614  */
33615 #define EMVSIM_TX_STATUS_GPCNT1_TO(x)            (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
33616 
33617 #define EMVSIM_TX_STATUS_TX_RPTR_MASK            (0xF0000U)
33618 #define EMVSIM_TX_STATUS_TX_RPTR_SHIFT           (16U)
33619 /*! TX_RPTR - Transmit FIFO Read Pointer */
33620 #define EMVSIM_TX_STATUS_TX_RPTR(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
33621 
33622 #define EMVSIM_TX_STATUS_TX_CNT_MASK             (0xF000000U)
33623 #define EMVSIM_TX_STATUS_TX_CNT_SHIFT            (24U)
33624 /*! TX_CNT - Transmit FIFO Byte Count
33625  *  0b0000..FIFO is emtpy
33626  */
33627 #define EMVSIM_TX_STATUS_TX_CNT(x)               (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)
33628 /*! @} */
33629 
33630 /*! @name PCSR - Port Control and Status Register */
33631 /*! @{ */
33632 
33633 #define EMVSIM_PCSR_SAPD_MASK                    (0x1U)
33634 #define EMVSIM_PCSR_SAPD_SHIFT                   (0U)
33635 /*! SAPD - Auto Power Down Enable
33636  *  0b0..Auto power down disabled
33637  *  0b1..Auto power down enabled
33638  */
33639 #define EMVSIM_PCSR_SAPD(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
33640 
33641 #define EMVSIM_PCSR_SVCC_EN_MASK                 (0x2U)
33642 #define EMVSIM_PCSR_SVCC_EN_SHIFT                (1U)
33643 /*! SVCC_EN - Vcc Enable for Smart Card
33644  *  0b0..Smart Card Voltage disabled
33645  *  0b1..Smart Card Voltage enabled
33646  */
33647 #define EMVSIM_PCSR_SVCC_EN(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
33648 
33649 #define EMVSIM_PCSR_VCCENP_MASK                  (0x4U)
33650 #define EMVSIM_PCSR_VCCENP_SHIFT                 (2U)
33651 /*! VCCENP - VCC Enable Polarity Control
33652  *  0b0..SVCC_EN is active high. Polarity of SVCC_EN is unchanged.
33653  *  0b1..SVCC_EN is active low. Polarity of SVCC_EN is inverted.
33654  */
33655 #define EMVSIM_PCSR_VCCENP(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
33656 
33657 #define EMVSIM_PCSR_SRST_MASK                    (0x8U)
33658 #define EMVSIM_PCSR_SRST_SHIFT                   (3U)
33659 /*! SRST - Reset to Smart Card
33660  *  0b0..Smart Card Reset is asserted
33661  *  0b1..Smart Card Reset is de-asserted
33662  */
33663 #define EMVSIM_PCSR_SRST(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
33664 
33665 #define EMVSIM_PCSR_SCEN_MASK                    (0x10U)
33666 #define EMVSIM_PCSR_SCEN_SHIFT                   (4U)
33667 /*! SCEN - Clock Enable for Smart Card
33668  *  0b0..Smart Card Clock Disabled
33669  *  0b1..Smart Card Clock Enabled
33670  */
33671 #define EMVSIM_PCSR_SCEN(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
33672 
33673 #define EMVSIM_PCSR_SCSP_MASK                    (0x20U)
33674 #define EMVSIM_PCSR_SCSP_SHIFT                   (5U)
33675 /*! SCSP - Smart Card Clock Stop Polarity
33676  *  0b0..Clock is logic 0 when stopped by SCEN
33677  *  0b1..Clock is logic 1 when stopped by SCEN
33678  */
33679 #define EMVSIM_PCSR_SCSP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
33680 
33681 #define EMVSIM_PCSR_SPD_MASK                     (0x80U)
33682 #define EMVSIM_PCSR_SPD_SHIFT                    (7U)
33683 /*! SPD - Auto Power Down Control
33684  *  0b0..No effect
33685  *  0b1..Start Auto Powerdown or Power Down is in progress
33686  */
33687 #define EMVSIM_PCSR_SPD(x)                       (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
33688 
33689 #define EMVSIM_PCSR_SPDIM_MASK                   (0x1000000U)
33690 #define EMVSIM_PCSR_SPDIM_SHIFT                  (24U)
33691 /*! SPDIM - Smart Card Presence Detect Interrupt Mask
33692  *  0b0..SIM presence detect interrupt is enabled
33693  *  0b1..SIM presence detect interrupt is masked
33694  */
33695 #define EMVSIM_PCSR_SPDIM(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
33696 
33697 #define EMVSIM_PCSR_SPDIF_MASK                   (0x2000000U)
33698 #define EMVSIM_PCSR_SPDIF_SHIFT                  (25U)
33699 /*! SPDIF - Smart Card Presence Detect Interrupt Flag
33700  *  0b0..No insertion or removal of Smart Card detected on Port
33701  *  0b1..Insertion or removal of Smart Card detected on Port
33702  */
33703 #define EMVSIM_PCSR_SPDIF(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
33704 
33705 #define EMVSIM_PCSR_SPDP_MASK                    (0x4000000U)
33706 #define EMVSIM_PCSR_SPDP_SHIFT                   (26U)
33707 /*! SPDP - Smart Card Presence Detect Pin Status
33708  *  0b0..SIM Presence Detect pin is logic low
33709  *  0b1..SIM Presence Detectpin is logic high
33710  */
33711 #define EMVSIM_PCSR_SPDP(x)                      (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
33712 
33713 #define EMVSIM_PCSR_SPDES_MASK                   (0x8000000U)
33714 #define EMVSIM_PCSR_SPDES_SHIFT                  (27U)
33715 /*! SPDES - SIM Presence Detect Edge Select
33716  *  0b0..Falling edge on the pin
33717  *  0b1..Rising edge on the pin
33718  */
33719 #define EMVSIM_PCSR_SPDES(x)                     (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)
33720 /*! @} */
33721 
33722 /*! @name RX_BUF - Receive Data Read Buffer */
33723 /*! @{ */
33724 
33725 #define EMVSIM_RX_BUF_RX_BYTE_MASK               (0xFFU)
33726 #define EMVSIM_RX_BUF_RX_BYTE_SHIFT              (0U)
33727 /*! RX_BYTE - Receive Data Byte Read */
33728 #define EMVSIM_RX_BUF_RX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)
33729 /*! @} */
33730 
33731 /*! @name TX_BUF - Transmit Data Buffer */
33732 /*! @{ */
33733 
33734 #define EMVSIM_TX_BUF_TX_BYTE_MASK               (0xFFU)
33735 #define EMVSIM_TX_BUF_TX_BYTE_SHIFT              (0U)
33736 /*! TX_BYTE - Transmit Data Byte */
33737 #define EMVSIM_TX_BUF_TX_BYTE(x)                 (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)
33738 /*! @} */
33739 
33740 /*! @name TX_GETU - Transmitter Guard ETU Value Register */
33741 /*! @{ */
33742 
33743 #define EMVSIM_TX_GETU_GETU_MASK                 (0xFFU)
33744 #define EMVSIM_TX_GETU_GETU_SHIFT                (0U)
33745 /*! GETU - Transmitter Guard Time Value in ETU */
33746 #define EMVSIM_TX_GETU_GETU(x)                   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
33747 /*! @} */
33748 
33749 /*! @name CWT_VAL - Character Wait Time Value Register */
33750 /*! @{ */
33751 
33752 #define EMVSIM_CWT_VAL_CWT_MASK                  (0xFFFFU)
33753 #define EMVSIM_CWT_VAL_CWT_SHIFT                 (0U)
33754 /*! CWT - Character Wait Time Value */
33755 #define EMVSIM_CWT_VAL_CWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)
33756 /*! @} */
33757 
33758 /*! @name BWT_VAL - Block Wait Time Value Register */
33759 /*! @{ */
33760 
33761 #define EMVSIM_BWT_VAL_BWT_MASK                  (0xFFFFFFFFU)
33762 #define EMVSIM_BWT_VAL_BWT_SHIFT                 (0U)
33763 /*! BWT - Block Wait Time Value */
33764 #define EMVSIM_BWT_VAL_BWT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)
33765 /*! @} */
33766 
33767 /*! @name BGT_VAL - Block Guard Time Value Register */
33768 /*! @{ */
33769 
33770 #define EMVSIM_BGT_VAL_BGT_MASK                  (0xFFFFU)
33771 #define EMVSIM_BGT_VAL_BGT_SHIFT                 (0U)
33772 /*! BGT - Block Guard Time Value */
33773 #define EMVSIM_BGT_VAL_BGT(x)                    (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)
33774 /*! @} */
33775 
33776 /*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */
33777 /*! @{ */
33778 
33779 #define EMVSIM_GPCNT0_VAL_GPCNT0_MASK            (0xFFFFU)
33780 #define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT           (0U)
33781 /*! GPCNT0 - General Purpose Counter 0 Timeout Value */
33782 #define EMVSIM_GPCNT0_VAL_GPCNT0(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
33783 /*! @} */
33784 
33785 /*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */
33786 /*! @{ */
33787 
33788 #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK            (0xFFFFU)
33789 #define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT           (0U)
33790 /*! GPCNT1 - General Purpose Counter 1 Timeout Value */
33791 #define EMVSIM_GPCNT1_VAL_GPCNT1(x)              (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
33792 /*! @} */
33793 
33794 
33795 /*!
33796  * @}
33797  */ /* end of group EMVSIM_Register_Masks */
33798 
33799 
33800 /* EMVSIM - Peripheral instance base addresses */
33801 /** Peripheral EMVSIM1 base address */
33802 #define EMVSIM1_BASE                             (0x40154000u)
33803 /** Peripheral EMVSIM1 base pointer */
33804 #define EMVSIM1                                  ((EMVSIM_Type *)EMVSIM1_BASE)
33805 /** Peripheral EMVSIM2 base address */
33806 #define EMVSIM2_BASE                             (0x40158000u)
33807 /** Peripheral EMVSIM2 base pointer */
33808 #define EMVSIM2                                  ((EMVSIM_Type *)EMVSIM2_BASE)
33809 /** Array initializer of EMVSIM peripheral base addresses */
33810 #define EMVSIM_BASE_ADDRS                        { 0u, EMVSIM1_BASE, EMVSIM2_BASE }
33811 /** Array initializer of EMVSIM peripheral base pointers */
33812 #define EMVSIM_BASE_PTRS                         { (EMVSIM_Type *)0u, EMVSIM1, EMVSIM2 }
33813 /** Interrupt vectors for the EMVSIM peripheral type */
33814 #define EMVSIM_IRQS                              { NotAvail_IRQn, EMVSIM1_IRQn, EMVSIM2_IRQn }
33815 
33816 /*!
33817  * @}
33818  */ /* end of group EMVSIM_Peripheral_Access_Layer */
33819 
33820 
33821 /* ----------------------------------------------------------------------------
33822    -- ENC Peripheral Access Layer
33823    ---------------------------------------------------------------------------- */
33824 
33825 /*!
33826  * @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer
33827  * @{
33828  */
33829 
33830 /** ENC - Register Layout Typedef */
33831 typedef struct {
33832   __IO uint16_t CTRL;                              /**< Control Register, offset: 0x0 */
33833   __IO uint16_t FILT;                              /**< Input Filter Register, offset: 0x2 */
33834   __IO uint16_t WTR;                               /**< Watchdog Timeout Register, offset: 0x4 */
33835   __IO uint16_t POSD;                              /**< Position Difference Counter Register, offset: 0x6 */
33836   __I  uint16_t POSDH;                             /**< Position Difference Hold Register, offset: 0x8 */
33837   __IO uint16_t REV;                               /**< Revolution Counter Register, offset: 0xA */
33838   __I  uint16_t REVH;                              /**< Revolution Hold Register, offset: 0xC */
33839   __IO uint16_t UPOS;                              /**< Upper Position Counter Register, offset: 0xE */
33840   __IO uint16_t LPOS;                              /**< Lower Position Counter Register, offset: 0x10 */
33841   __I  uint16_t UPOSH;                             /**< Upper Position Hold Register, offset: 0x12 */
33842   __I  uint16_t LPOSH;                             /**< Lower Position Hold Register, offset: 0x14 */
33843   __IO uint16_t UINIT;                             /**< Upper Initialization Register, offset: 0x16 */
33844   __IO uint16_t LINIT;                             /**< Lower Initialization Register, offset: 0x18 */
33845   __I  uint16_t IMR;                               /**< Input Monitor Register, offset: 0x1A */
33846   __IO uint16_t TST;                               /**< Test Register, offset: 0x1C */
33847   __IO uint16_t CTRL2;                             /**< Control 2 Register, offset: 0x1E */
33848   __IO uint16_t UMOD;                              /**< Upper Modulus Register, offset: 0x20 */
33849   __IO uint16_t LMOD;                              /**< Lower Modulus Register, offset: 0x22 */
33850   __IO uint16_t UCOMP;                             /**< Upper Position Compare Register, offset: 0x24 */
33851   __IO uint16_t LCOMP;                             /**< Lower Position Compare Register, offset: 0x26 */
33852   __I  uint16_t LASTEDGE;                          /**< Last Edge Time Register, offset: 0x28 */
33853   __I  uint16_t LASTEDGEH;                         /**< Last Edge Time Hold Register, offset: 0x2A */
33854   __I  uint16_t POSDPER;                           /**< Position Difference Period Counter Register, offset: 0x2C */
33855   __I  uint16_t POSDPERBFR;                        /**< Position Difference Period Buffer Register, offset: 0x2E */
33856   __I  uint16_t POSDPERH;                          /**< Position Difference Period Hold Register, offset: 0x30 */
33857   __IO uint16_t CTRL3;                             /**< Control 3 Register, offset: 0x32 */
33858 } ENC_Type;
33859 
33860 /* ----------------------------------------------------------------------------
33861    -- ENC Register Masks
33862    ---------------------------------------------------------------------------- */
33863 
33864 /*!
33865  * @addtogroup ENC_Register_Masks ENC Register Masks
33866  * @{
33867  */
33868 
33869 /*! @name CTRL - Control Register */
33870 /*! @{ */
33871 
33872 #define ENC_CTRL_CMPIE_MASK                      (0x1U)
33873 #define ENC_CTRL_CMPIE_SHIFT                     (0U)
33874 /*! CMPIE - Compare Interrupt Enable
33875  *  0b0..Disabled
33876  *  0b1..Enabled
33877  */
33878 #define ENC_CTRL_CMPIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
33879 
33880 #define ENC_CTRL_CMPIRQ_MASK                     (0x2U)
33881 #define ENC_CTRL_CMPIRQ_SHIFT                    (1U)
33882 /*! CMPIRQ - Compare Interrupt Request
33883  *  0b0..No match has occurred (the counter does not match the COMP value)
33884  *  0b1..COMP match has occurred (the counter matches the COMP value)
33885  */
33886 #define ENC_CTRL_CMPIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
33887 
33888 #define ENC_CTRL_WDE_MASK                        (0x4U)
33889 #define ENC_CTRL_WDE_SHIFT                       (2U)
33890 /*! WDE - Watchdog Enable
33891  *  0b0..Disabled
33892  *  0b1..Enabled
33893  */
33894 #define ENC_CTRL_WDE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
33895 
33896 #define ENC_CTRL_DIE_MASK                        (0x8U)
33897 #define ENC_CTRL_DIE_SHIFT                       (3U)
33898 /*! DIE - Watchdog Timeout Interrupt Enable
33899  *  0b0..Disabled
33900  *  0b1..Enabled
33901  */
33902 #define ENC_CTRL_DIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
33903 
33904 #define ENC_CTRL_DIRQ_MASK                       (0x10U)
33905 #define ENC_CTRL_DIRQ_SHIFT                      (4U)
33906 /*! DIRQ - Watchdog Timeout Interrupt Request
33907  *  0b0..No Watchdog timeout interrupt has occurred
33908  *  0b1..Watchdog timeout interrupt has occurred
33909  */
33910 #define ENC_CTRL_DIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
33911 
33912 #define ENC_CTRL_XNE_MASK                        (0x20U)
33913 #define ENC_CTRL_XNE_SHIFT                       (5U)
33914 /*! XNE - Use Negative Edge of INDEX Pulse
33915  *  0b0..Use positive edge of INDEX pulse
33916  *  0b1..Use negative edge of INDEX pulse
33917  */
33918 #define ENC_CTRL_XNE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
33919 
33920 #define ENC_CTRL_XIP_MASK                        (0x40U)
33921 #define ENC_CTRL_XIP_SHIFT                       (6U)
33922 /*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS
33923  *  0b0..INDEX pulse does not initialize the position counter
33924  *  0b1..INDEX pulse initializes the position counter
33925  */
33926 #define ENC_CTRL_XIP(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
33927 
33928 #define ENC_CTRL_XIE_MASK                        (0x80U)
33929 #define ENC_CTRL_XIE_SHIFT                       (7U)
33930 /*! XIE - INDEX Pulse Interrupt Enable
33931  *  0b0..Disabled
33932  *  0b1..Enabled
33933  */
33934 #define ENC_CTRL_XIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
33935 
33936 #define ENC_CTRL_XIRQ_MASK                       (0x100U)
33937 #define ENC_CTRL_XIRQ_SHIFT                      (8U)
33938 /*! XIRQ - INDEX Pulse Interrupt Request
33939  *  0b0..INDEX pulse has not occurred
33940  *  0b1..INDEX pulse has occurred
33941  */
33942 #define ENC_CTRL_XIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
33943 
33944 #define ENC_CTRL_PH1_MASK                        (0x200U)
33945 #define ENC_CTRL_PH1_SHIFT                       (9U)
33946 /*! PH1 - Enable Signal Phase Count Mode
33947  *  0b0..Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal.
33948  *  0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The
33949  *       PHASEB input and the REV bit control the counter direction: If CTRL[REV] = 0, PHASEB = 0, then count up If
33950  *       CTRL[REV] = 1, PHASEB = 1, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1,
33951  *       PHASEB = 0, then count down
33952  */
33953 #define ENC_CTRL_PH1(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
33954 
33955 #define ENC_CTRL_REV_MASK                        (0x400U)
33956 #define ENC_CTRL_REV_SHIFT                       (10U)
33957 /*! REV - Enable Reverse Direction Counting
33958  *  0b0..Count normally
33959  *  0b1..Count in the reverse direction
33960  */
33961 #define ENC_CTRL_REV(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
33962 
33963 #define ENC_CTRL_SWIP_MASK                       (0x800U)
33964 #define ENC_CTRL_SWIP_SHIFT                      (11U)
33965 /*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS
33966  *  0b0..No action
33967  *  0b1..Initialize position counter (using upper and lower initialization registers, UINIT and LINIT)
33968  */
33969 #define ENC_CTRL_SWIP(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
33970 
33971 #define ENC_CTRL_HNE_MASK                        (0x1000U)
33972 #define ENC_CTRL_HNE_SHIFT                       (12U)
33973 /*! HNE - Use Negative Edge of HOME Input
33974  *  0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS
33975  *  0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS
33976  */
33977 #define ENC_CTRL_HNE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
33978 
33979 #define ENC_CTRL_HIP_MASK                        (0x2000U)
33980 #define ENC_CTRL_HIP_SHIFT                       (13U)
33981 /*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS
33982  *  0b0..No action
33983  *  0b1..HOME signal initializes the position counter
33984  */
33985 #define ENC_CTRL_HIP(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
33986 
33987 #define ENC_CTRL_HIE_MASK                        (0x4000U)
33988 #define ENC_CTRL_HIE_SHIFT                       (14U)
33989 /*! HIE - HOME Interrupt Enable
33990  *  0b0..Disabled
33991  *  0b1..Enabled
33992  */
33993 #define ENC_CTRL_HIE(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
33994 
33995 #define ENC_CTRL_HIRQ_MASK                       (0x8000U)
33996 #define ENC_CTRL_HIRQ_SHIFT                      (15U)
33997 /*! HIRQ - HOME Signal Transition Interrupt Request
33998  *  0b0..No transition on the HOME signal has occurred
33999  *  0b1..A transition on the HOME signal has occurred
34000  */
34001 #define ENC_CTRL_HIRQ(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
34002 /*! @} */
34003 
34004 /*! @name FILT - Input Filter Register */
34005 /*! @{ */
34006 
34007 #define ENC_FILT_FILT_PER_MASK                   (0xFFU)
34008 #define ENC_FILT_FILT_PER_SHIFT                  (0U)
34009 /*! FILT_PER - Input Filter Sample Period */
34010 #define ENC_FILT_FILT_PER(x)                     (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)
34011 
34012 #define ENC_FILT_FILT_CNT_MASK                   (0x700U)
34013 #define ENC_FILT_FILT_CNT_SHIFT                  (8U)
34014 /*! FILT_CNT - Input Filter Sample Count */
34015 #define ENC_FILT_FILT_CNT(x)                     (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)
34016 /*! @} */
34017 
34018 /*! @name WTR - Watchdog Timeout Register */
34019 /*! @{ */
34020 
34021 #define ENC_WTR_WDOG_MASK                        (0xFFFFU)
34022 #define ENC_WTR_WDOG_SHIFT                       (0U)
34023 /*! WDOG - WDOG */
34024 #define ENC_WTR_WDOG(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)
34025 /*! @} */
34026 
34027 /*! @name POSD - Position Difference Counter Register */
34028 /*! @{ */
34029 
34030 #define ENC_POSD_POSD_MASK                       (0xFFFFU)
34031 #define ENC_POSD_POSD_SHIFT                      (0U)
34032 /*! POSD - POSD */
34033 #define ENC_POSD_POSD(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)
34034 /*! @} */
34035 
34036 /*! @name POSDH - Position Difference Hold Register */
34037 /*! @{ */
34038 
34039 #define ENC_POSDH_POSDH_MASK                     (0xFFFFU)
34040 #define ENC_POSDH_POSDH_SHIFT                    (0U)
34041 /*! POSDH - POSDH */
34042 #define ENC_POSDH_POSDH(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)
34043 /*! @} */
34044 
34045 /*! @name REV - Revolution Counter Register */
34046 /*! @{ */
34047 
34048 #define ENC_REV_REV_MASK                         (0xFFFFU)
34049 #define ENC_REV_REV_SHIFT                        (0U)
34050 /*! REV - REV */
34051 #define ENC_REV_REV(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)
34052 /*! @} */
34053 
34054 /*! @name REVH - Revolution Hold Register */
34055 /*! @{ */
34056 
34057 #define ENC_REVH_REVH_MASK                       (0xFFFFU)
34058 #define ENC_REVH_REVH_SHIFT                      (0U)
34059 /*! REVH - REVH */
34060 #define ENC_REVH_REVH(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)
34061 /*! @} */
34062 
34063 /*! @name UPOS - Upper Position Counter Register */
34064 /*! @{ */
34065 
34066 #define ENC_UPOS_POS_MASK                        (0xFFFFU)
34067 #define ENC_UPOS_POS_SHIFT                       (0U)
34068 /*! POS - POS */
34069 #define ENC_UPOS_POS(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)
34070 /*! @} */
34071 
34072 /*! @name LPOS - Lower Position Counter Register */
34073 /*! @{ */
34074 
34075 #define ENC_LPOS_POS_MASK                        (0xFFFFU)
34076 #define ENC_LPOS_POS_SHIFT                       (0U)
34077 /*! POS - POS */
34078 #define ENC_LPOS_POS(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)
34079 /*! @} */
34080 
34081 /*! @name UPOSH - Upper Position Hold Register */
34082 /*! @{ */
34083 
34084 #define ENC_UPOSH_POSH_MASK                      (0xFFFFU)
34085 #define ENC_UPOSH_POSH_SHIFT                     (0U)
34086 /*! POSH - POSH */
34087 #define ENC_UPOSH_POSH(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)
34088 /*! @} */
34089 
34090 /*! @name LPOSH - Lower Position Hold Register */
34091 /*! @{ */
34092 
34093 #define ENC_LPOSH_POSH_MASK                      (0xFFFFU)
34094 #define ENC_LPOSH_POSH_SHIFT                     (0U)
34095 /*! POSH - POSH */
34096 #define ENC_LPOSH_POSH(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)
34097 /*! @} */
34098 
34099 /*! @name UINIT - Upper Initialization Register */
34100 /*! @{ */
34101 
34102 #define ENC_UINIT_INIT_MASK                      (0xFFFFU)
34103 #define ENC_UINIT_INIT_SHIFT                     (0U)
34104 /*! INIT - INIT */
34105 #define ENC_UINIT_INIT(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)
34106 /*! @} */
34107 
34108 /*! @name LINIT - Lower Initialization Register */
34109 /*! @{ */
34110 
34111 #define ENC_LINIT_INIT_MASK                      (0xFFFFU)
34112 #define ENC_LINIT_INIT_SHIFT                     (0U)
34113 /*! INIT - INIT */
34114 #define ENC_LINIT_INIT(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)
34115 /*! @} */
34116 
34117 /*! @name IMR - Input Monitor Register */
34118 /*! @{ */
34119 
34120 #define ENC_IMR_HOME_MASK                        (0x1U)
34121 #define ENC_IMR_HOME_SHIFT                       (0U)
34122 /*! HOME - HOME */
34123 #define ENC_IMR_HOME(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)
34124 
34125 #define ENC_IMR_INDEX_MASK                       (0x2U)
34126 #define ENC_IMR_INDEX_SHIFT                      (1U)
34127 /*! INDEX - INDEX */
34128 #define ENC_IMR_INDEX(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)
34129 
34130 #define ENC_IMR_PHB_MASK                         (0x4U)
34131 #define ENC_IMR_PHB_SHIFT                        (2U)
34132 /*! PHB - PHB */
34133 #define ENC_IMR_PHB(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)
34134 
34135 #define ENC_IMR_PHA_MASK                         (0x8U)
34136 #define ENC_IMR_PHA_SHIFT                        (3U)
34137 /*! PHA - PHA */
34138 #define ENC_IMR_PHA(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)
34139 
34140 #define ENC_IMR_FHOM_MASK                        (0x10U)
34141 #define ENC_IMR_FHOM_SHIFT                       (4U)
34142 /*! FHOM - FHOM */
34143 #define ENC_IMR_FHOM(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)
34144 
34145 #define ENC_IMR_FIND_MASK                        (0x20U)
34146 #define ENC_IMR_FIND_SHIFT                       (5U)
34147 /*! FIND - FIND */
34148 #define ENC_IMR_FIND(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)
34149 
34150 #define ENC_IMR_FPHB_MASK                        (0x40U)
34151 #define ENC_IMR_FPHB_SHIFT                       (6U)
34152 /*! FPHB - FPHB */
34153 #define ENC_IMR_FPHB(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)
34154 
34155 #define ENC_IMR_FPHA_MASK                        (0x80U)
34156 #define ENC_IMR_FPHA_SHIFT                       (7U)
34157 /*! FPHA - FPHA */
34158 #define ENC_IMR_FPHA(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)
34159 /*! @} */
34160 
34161 /*! @name TST - Test Register */
34162 /*! @{ */
34163 
34164 #define ENC_TST_TEST_COUNT_MASK                  (0xFFU)
34165 #define ENC_TST_TEST_COUNT_SHIFT                 (0U)
34166 /*! TEST_COUNT - TEST_COUNT */
34167 #define ENC_TST_TEST_COUNT(x)                    (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)
34168 
34169 #define ENC_TST_TEST_PERIOD_MASK                 (0x1F00U)
34170 #define ENC_TST_TEST_PERIOD_SHIFT                (8U)
34171 /*! TEST_PERIOD - TEST_PERIOD */
34172 #define ENC_TST_TEST_PERIOD(x)                   (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)
34173 
34174 #define ENC_TST_QDN_MASK                         (0x2000U)
34175 #define ENC_TST_QDN_SHIFT                        (13U)
34176 /*! QDN - Quadrature Decoder Negative Signal
34177  *  0b0..Generates a positive quadrature decoder signal
34178  *  0b1..Generates a negative quadrature decoder signal
34179  */
34180 #define ENC_TST_QDN(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)
34181 
34182 #define ENC_TST_TCE_MASK                         (0x4000U)
34183 #define ENC_TST_TCE_SHIFT                        (14U)
34184 /*! TCE - Test Counter Enable
34185  *  0b0..Disabled
34186  *  0b1..Enabled
34187  */
34188 #define ENC_TST_TCE(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)
34189 
34190 #define ENC_TST_TEN_MASK                         (0x8000U)
34191 #define ENC_TST_TEN_SHIFT                        (15U)
34192 /*! TEN - Test Mode Enable
34193  *  0b0..Disabled
34194  *  0b1..Enabled
34195  */
34196 #define ENC_TST_TEN(x)                           (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
34197 /*! @} */
34198 
34199 /*! @name CTRL2 - Control 2 Register */
34200 /*! @{ */
34201 
34202 #define ENC_CTRL2_UPDHLD_MASK                    (0x1U)
34203 #define ENC_CTRL2_UPDHLD_SHIFT                   (0U)
34204 /*! UPDHLD - Update Hold Registers
34205  *  0b0..Disable updates of hold registers on the rising edge of TRIGGER input signal
34206  *  0b1..Enable updates of hold registers on the rising edge of TRIGGER input signal
34207  */
34208 #define ENC_CTRL2_UPDHLD(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
34209 
34210 #define ENC_CTRL2_UPDPOS_MASK                    (0x2U)
34211 #define ENC_CTRL2_UPDPOS_SHIFT                   (1U)
34212 /*! UPDPOS - Update Position Registers
34213  *  0b0..No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER
34214  *  0b1..Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER
34215  */
34216 #define ENC_CTRL2_UPDPOS(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
34217 
34218 #define ENC_CTRL2_MOD_MASK                       (0x4U)
34219 #define ENC_CTRL2_MOD_SHIFT                      (2U)
34220 /*! MOD - Enable Modulo Counting
34221  *  0b0..Disable modulo counting
34222  *  0b1..Enable modulo counting
34223  */
34224 #define ENC_CTRL2_MOD(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
34225 
34226 #define ENC_CTRL2_DIR_MASK                       (0x8U)
34227 #define ENC_CTRL2_DIR_SHIFT                      (3U)
34228 /*! DIR - Count Direction Flag
34229  *  0b0..Last count was in the down direction
34230  *  0b1..Last count was in the up direction
34231  */
34232 #define ENC_CTRL2_DIR(x)                         (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
34233 
34234 #define ENC_CTRL2_RUIE_MASK                      (0x10U)
34235 #define ENC_CTRL2_RUIE_SHIFT                     (4U)
34236 /*! RUIE - Roll-under Interrupt Enable
34237  *  0b0..Disabled
34238  *  0b1..Enabled
34239  */
34240 #define ENC_CTRL2_RUIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
34241 
34242 #define ENC_CTRL2_RUIRQ_MASK                     (0x20U)
34243 #define ENC_CTRL2_RUIRQ_SHIFT                    (5U)
34244 /*! RUIRQ - Roll-under Interrupt Request
34245  *  0b0..No roll-under has occurred
34246  *  0b1..Roll-under has occurred
34247  */
34248 #define ENC_CTRL2_RUIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
34249 
34250 #define ENC_CTRL2_ROIE_MASK                      (0x40U)
34251 #define ENC_CTRL2_ROIE_SHIFT                     (6U)
34252 /*! ROIE - Roll-over Interrupt Enable
34253  *  0b0..Disabled
34254  *  0b1..Enabled
34255  */
34256 #define ENC_CTRL2_ROIE(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
34257 
34258 #define ENC_CTRL2_ROIRQ_MASK                     (0x80U)
34259 #define ENC_CTRL2_ROIRQ_SHIFT                    (7U)
34260 /*! ROIRQ - Roll-over Interrupt Request
34261  *  0b0..No roll-over has occurred
34262  *  0b1..Roll-over has occurred
34263  */
34264 #define ENC_CTRL2_ROIRQ(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
34265 
34266 #define ENC_CTRL2_REVMOD_MASK                    (0x100U)
34267 #define ENC_CTRL2_REVMOD_SHIFT                   (8U)
34268 /*! REVMOD - Revolution Counter Modulus Enable
34269  *  0b0..Use INDEX pulse to increment/decrement revolution counter (REV)
34270  *  0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV)
34271  */
34272 #define ENC_CTRL2_REVMOD(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
34273 
34274 #define ENC_CTRL2_OUTCTL_MASK                    (0x200U)
34275 #define ENC_CTRL2_OUTCTL_SHIFT                   (9U)
34276 /*! OUTCTL - Output Control
34277  *  0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP )
34278  *  0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read
34279  */
34280 #define ENC_CTRL2_OUTCTL(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
34281 
34282 #define ENC_CTRL2_SABIE_MASK                     (0x400U)
34283 #define ENC_CTRL2_SABIE_SHIFT                    (10U)
34284 /*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable
34285  *  0b0..Disabled
34286  *  0b1..Enabled
34287  */
34288 #define ENC_CTRL2_SABIE(x)                       (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)
34289 
34290 #define ENC_CTRL2_SABIRQ_MASK                    (0x800U)
34291 #define ENC_CTRL2_SABIRQ_SHIFT                   (11U)
34292 /*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request
34293  *  0b0..No simultaneous change of PHASEA and PHASEB has occurred
34294  *  0b1..A simultaneous change of PHASEA and PHASEB has occurred
34295  */
34296 #define ENC_CTRL2_SABIRQ(x)                      (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
34297 /*! @} */
34298 
34299 /*! @name UMOD - Upper Modulus Register */
34300 /*! @{ */
34301 
34302 #define ENC_UMOD_MOD_MASK                        (0xFFFFU)
34303 #define ENC_UMOD_MOD_SHIFT                       (0U)
34304 /*! MOD - MOD */
34305 #define ENC_UMOD_MOD(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)
34306 /*! @} */
34307 
34308 /*! @name LMOD - Lower Modulus Register */
34309 /*! @{ */
34310 
34311 #define ENC_LMOD_MOD_MASK                        (0xFFFFU)
34312 #define ENC_LMOD_MOD_SHIFT                       (0U)
34313 /*! MOD - MOD */
34314 #define ENC_LMOD_MOD(x)                          (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)
34315 /*! @} */
34316 
34317 /*! @name UCOMP - Upper Position Compare Register */
34318 /*! @{ */
34319 
34320 #define ENC_UCOMP_COMP_MASK                      (0xFFFFU)
34321 #define ENC_UCOMP_COMP_SHIFT                     (0U)
34322 /*! COMP - COMP */
34323 #define ENC_UCOMP_COMP(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)
34324 /*! @} */
34325 
34326 /*! @name LCOMP - Lower Position Compare Register */
34327 /*! @{ */
34328 
34329 #define ENC_LCOMP_COMP_MASK                      (0xFFFFU)
34330 #define ENC_LCOMP_COMP_SHIFT                     (0U)
34331 /*! COMP - COMP */
34332 #define ENC_LCOMP_COMP(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)
34333 /*! @} */
34334 
34335 /*! @name LASTEDGE - Last Edge Time Register */
34336 /*! @{ */
34337 
34338 #define ENC_LASTEDGE_LASTEDGE_MASK               (0xFFFFU)
34339 #define ENC_LASTEDGE_LASTEDGE_SHIFT              (0U)
34340 /*! LASTEDGE - Last Edge Time Counter */
34341 #define ENC_LASTEDGE_LASTEDGE(x)                 (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGE_LASTEDGE_SHIFT)) & ENC_LASTEDGE_LASTEDGE_MASK)
34342 /*! @} */
34343 
34344 /*! @name LASTEDGEH - Last Edge Time Hold Register */
34345 /*! @{ */
34346 
34347 #define ENC_LASTEDGEH_LASTEDGEH_MASK             (0xFFFFU)
34348 #define ENC_LASTEDGEH_LASTEDGEH_SHIFT            (0U)
34349 /*! LASTEDGEH - Last Edge Time Hold */
34350 #define ENC_LASTEDGEH_LASTEDGEH(x)               (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGEH_LASTEDGEH_SHIFT)) & ENC_LASTEDGEH_LASTEDGEH_MASK)
34351 /*! @} */
34352 
34353 /*! @name POSDPER - Position Difference Period Counter Register */
34354 /*! @{ */
34355 
34356 #define ENC_POSDPER_POSDPER_MASK                 (0xFFFFU)
34357 #define ENC_POSDPER_POSDPER_SHIFT                (0U)
34358 /*! POSDPER - Position difference period */
34359 #define ENC_POSDPER_POSDPER(x)                   (((uint16_t)(((uint16_t)(x)) << ENC_POSDPER_POSDPER_SHIFT)) & ENC_POSDPER_POSDPER_MASK)
34360 /*! @} */
34361 
34362 /*! @name POSDPERBFR - Position Difference Period Buffer Register */
34363 /*! @{ */
34364 
34365 #define ENC_POSDPERBFR_POSDPERBFR_MASK           (0xFFFFU)
34366 #define ENC_POSDPERBFR_POSDPERBFR_SHIFT          (0U)
34367 /*! POSDPERBFR - Position difference period buffer */
34368 #define ENC_POSDPERBFR_POSDPERBFR(x)             (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERBFR_POSDPERBFR_SHIFT)) & ENC_POSDPERBFR_POSDPERBFR_MASK)
34369 /*! @} */
34370 
34371 /*! @name POSDPERH - Position Difference Period Hold Register */
34372 /*! @{ */
34373 
34374 #define ENC_POSDPERH_POSDPERH_MASK               (0xFFFFU)
34375 #define ENC_POSDPERH_POSDPERH_SHIFT              (0U)
34376 /*! POSDPERH - Position difference period hold */
34377 #define ENC_POSDPERH_POSDPERH(x)                 (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERH_POSDPERH_SHIFT)) & ENC_POSDPERH_POSDPERH_MASK)
34378 /*! @} */
34379 
34380 /*! @name CTRL3 - Control 3 Register */
34381 /*! @{ */
34382 
34383 #define ENC_CTRL3_PMEN_MASK                      (0x1U)
34384 #define ENC_CTRL3_PMEN_SHIFT                     (0U)
34385 /*! PMEN - Period measurement function enable
34386  *  0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS, or REV is read.
34387  *  0b1..Period measurement functions are used. POSD is loaded to POSDH and then cleared only when POSD is read.
34388  */
34389 #define ENC_CTRL3_PMEN(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PMEN_SHIFT)) & ENC_CTRL3_PMEN_MASK)
34390 
34391 #define ENC_CTRL3_PRSC_MASK                      (0xF0U)
34392 #define ENC_CTRL3_PRSC_SHIFT                     (4U)
34393 /*! PRSC - Prescaler */
34394 #define ENC_CTRL3_PRSC(x)                        (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PRSC_SHIFT)) & ENC_CTRL3_PRSC_MASK)
34395 /*! @} */
34396 
34397 
34398 /*!
34399  * @}
34400  */ /* end of group ENC_Register_Masks */
34401 
34402 
34403 /* ENC - Peripheral instance base addresses */
34404 /** Peripheral ENC1 base address */
34405 #define ENC1_BASE                                (0x40174000u)
34406 /** Peripheral ENC1 base pointer */
34407 #define ENC1                                     ((ENC_Type *)ENC1_BASE)
34408 /** Peripheral ENC2 base address */
34409 #define ENC2_BASE                                (0x40178000u)
34410 /** Peripheral ENC2 base pointer */
34411 #define ENC2                                     ((ENC_Type *)ENC2_BASE)
34412 /** Peripheral ENC3 base address */
34413 #define ENC3_BASE                                (0x4017C000u)
34414 /** Peripheral ENC3 base pointer */
34415 #define ENC3                                     ((ENC_Type *)ENC3_BASE)
34416 /** Peripheral ENC4 base address */
34417 #define ENC4_BASE                                (0x40180000u)
34418 /** Peripheral ENC4 base pointer */
34419 #define ENC4                                     ((ENC_Type *)ENC4_BASE)
34420 /** Array initializer of ENC peripheral base addresses */
34421 #define ENC_BASE_ADDRS                           { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
34422 /** Array initializer of ENC peripheral base pointers */
34423 #define ENC_BASE_PTRS                            { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
34424 /** Interrupt vectors for the ENC peripheral type */
34425 #define ENC_COMPARE_IRQS                         { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
34426 #define ENC_HOME_IRQS                            { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
34427 #define ENC_WDOG_IRQS                            { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
34428 #define ENC_INDEX_IRQS                           { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
34429 #define ENC_INPUT_SWITCH_IRQS                    { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
34430 
34431 /*!
34432  * @}
34433  */ /* end of group ENC_Peripheral_Access_Layer */
34434 
34435 
34436 /* ----------------------------------------------------------------------------
34437    -- ENET Peripheral Access Layer
34438    ---------------------------------------------------------------------------- */
34439 
34440 /*!
34441  * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
34442  * @{
34443  */
34444 
34445 /** ENET - Register Layout Typedef */
34446 typedef struct {
34447        uint8_t RESERVED_0[4];
34448   __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
34449   __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
34450        uint8_t RESERVED_1[4];
34451   __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */
34452   __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */
34453        uint8_t RESERVED_2[12];
34454   __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
34455        uint8_t RESERVED_3[24];
34456   __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
34457   __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
34458        uint8_t RESERVED_4[28];
34459   __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
34460        uint8_t RESERVED_5[28];
34461   __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
34462        uint8_t RESERVED_6[60];
34463   __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
34464        uint8_t RESERVED_7[28];
34465   __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
34466   __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
34467   __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
34468   __IO uint32_t TXIC[3];                           /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
34469        uint8_t RESERVED_8[4];
34470   __IO uint32_t RXIC[3];                           /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
34471        uint8_t RESERVED_9[12];
34472   __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
34473   __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
34474   __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
34475   __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
34476        uint8_t RESERVED_10[28];
34477   __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
34478        uint8_t RESERVED_11[24];
34479   __IO uint32_t RDSR1;                             /**< Receive Descriptor Ring 1 Start Register, offset: 0x160, available only on: ENET_1G (missing on ENET) */
34480   __IO uint32_t TDSR1;                             /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164, available only on: ENET_1G (missing on ENET) */
34481   __IO uint32_t MRBR1;                             /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168, available only on: ENET_1G (missing on ENET) */
34482   __IO uint32_t RDSR2;                             /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C, available only on: ENET_1G (missing on ENET) */
34483   __IO uint32_t TDSR2;                             /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170, available only on: ENET_1G (missing on ENET) */
34484   __IO uint32_t MRBR2;                             /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174, available only on: ENET_1G (missing on ENET) */
34485        uint8_t RESERVED_12[8];
34486   __IO uint32_t RDSR;                              /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */
34487   __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */
34488   __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */
34489        uint8_t RESERVED_13[4];
34490   __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
34491   __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
34492   __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
34493   __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
34494   __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
34495   __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
34496   __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
34497   __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
34498   __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
34499        uint8_t RESERVED_14[12];
34500   __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
34501   __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
34502   __IO uint32_t RCMR[2];                           /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4, available only on: ENET_1G (missing on ENET) */
34503        uint8_t RESERVED_15[8];
34504   __IO uint32_t DMACFG[2];                         /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4, available only on: ENET_1G (missing on ENET) */
34505   __IO uint32_t RDAR1;                             /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0, available only on: ENET_1G (missing on ENET) */
34506   __IO uint32_t TDAR1;                             /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4, available only on: ENET_1G (missing on ENET) */
34507   __IO uint32_t RDAR2;                             /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8, available only on: ENET_1G (missing on ENET) */
34508   __IO uint32_t TDAR2;                             /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC, available only on: ENET_1G (missing on ENET) */
34509   __IO uint32_t QOS;                               /**< QOS Scheme, offset: 0x1F0, available only on: ENET_1G (missing on ENET) */
34510        uint8_t RESERVED_16[16];
34511   __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
34512   __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
34513   __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
34514   __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
34515   __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
34516   __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
34517   __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
34518   __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
34519   __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
34520   __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
34521   __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
34522   __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
34523   __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
34524   __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
34525   __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
34526   __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
34527   __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
34528        uint8_t RESERVED_17[4];
34529   __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
34530   __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
34531   __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
34532   __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
34533   __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
34534   __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
34535   __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
34536   __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
34537   __I  uint32_t IEEE_T_SQE;                        /**< Reserved Statistic Register, offset: 0x26C */
34538   __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
34539   __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
34540        uint8_t RESERVED_18[12];
34541   __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
34542   __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
34543   __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
34544   __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
34545   __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
34546   __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
34547   __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
34548   __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
34549        uint8_t RESERVED_19[4];
34550   __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
34551   __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
34552   __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
34553   __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
34554   __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
34555   __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
34556   __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
34557   __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
34558   __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
34559   __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
34560   __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
34561   __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
34562   __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
34563   __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
34564   __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
34565        uint8_t RESERVED_20[284];
34566   __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
34567   __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
34568   __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
34569   __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
34570   __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
34571   __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
34572   __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
34573        uint8_t RESERVED_21[488];
34574   __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
34575   struct {                                         /* offset: 0x608, array step: 0x8 */
34576     __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
34577     __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
34578   } CHANNEL[4];
34579 } ENET_Type;
34580 
34581 /* ----------------------------------------------------------------------------
34582    -- ENET Register Masks
34583    ---------------------------------------------------------------------------- */
34584 
34585 /*!
34586  * @addtogroup ENET_Register_Masks ENET Register Masks
34587  * @{
34588  */
34589 
34590 /*! @name EIR - Interrupt Event Register */
34591 /*! @{ */
34592 
34593 #define ENET_EIR_RXB1_MASK                       (0x1U)
34594 #define ENET_EIR_RXB1_SHIFT                      (0U)
34595 /*! RXB1 - Receive buffer interrupt, class 1 */
34596 #define ENET_EIR_RXB1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)
34597 
34598 #define ENET_EIR_RXF1_MASK                       (0x2U)
34599 #define ENET_EIR_RXF1_SHIFT                      (1U)
34600 /*! RXF1 - Receive frame interrupt, class 1 */
34601 #define ENET_EIR_RXF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)
34602 
34603 #define ENET_EIR_TXB1_MASK                       (0x4U)
34604 #define ENET_EIR_TXB1_SHIFT                      (2U)
34605 /*! TXB1 - Transmit buffer interrupt, class 1 */
34606 #define ENET_EIR_TXB1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)
34607 
34608 #define ENET_EIR_TXF1_MASK                       (0x8U)
34609 #define ENET_EIR_TXF1_SHIFT                      (3U)
34610 /*! TXF1 - Transmit frame interrupt, class 1 */
34611 #define ENET_EIR_TXF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)
34612 
34613 #define ENET_EIR_RXB2_MASK                       (0x10U)
34614 #define ENET_EIR_RXB2_SHIFT                      (4U)
34615 /*! RXB2 - Receive buffer interrupt, class 2 */
34616 #define ENET_EIR_RXB2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)
34617 
34618 #define ENET_EIR_RXF2_MASK                       (0x20U)
34619 #define ENET_EIR_RXF2_SHIFT                      (5U)
34620 /*! RXF2 - Receive frame interrupt, class 2 */
34621 #define ENET_EIR_RXF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)
34622 
34623 #define ENET_EIR_TXB2_MASK                       (0x40U)
34624 #define ENET_EIR_TXB2_SHIFT                      (6U)
34625 /*! TXB2 - Transmit buffer interrupt, class 2 */
34626 #define ENET_EIR_TXB2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)
34627 
34628 #define ENET_EIR_TXF2_MASK                       (0x80U)
34629 #define ENET_EIR_TXF2_SHIFT                      (7U)
34630 /*! TXF2 - Transmit frame interrupt, class 2 */
34631 #define ENET_EIR_TXF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)
34632 
34633 #define ENET_EIR_RXFLUSH_0_MASK                  (0x1000U)
34634 #define ENET_EIR_RXFLUSH_0_SHIFT                 (12U)
34635 #define ENET_EIR_RXFLUSH_0(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK)
34636 
34637 #define ENET_EIR_RXFLUSH_1_MASK                  (0x2000U)
34638 #define ENET_EIR_RXFLUSH_1_SHIFT                 (13U)
34639 #define ENET_EIR_RXFLUSH_1(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK)
34640 
34641 #define ENET_EIR_RXFLUSH_2_MASK                  (0x4000U)
34642 #define ENET_EIR_RXFLUSH_2_SHIFT                 (14U)
34643 #define ENET_EIR_RXFLUSH_2(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK)
34644 
34645 #define ENET_EIR_TS_TIMER_MASK                   (0x8000U)
34646 #define ENET_EIR_TS_TIMER_SHIFT                  (15U)
34647 /*! TS_TIMER - Timestamp Timer */
34648 #define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
34649 
34650 #define ENET_EIR_TS_AVAIL_MASK                   (0x10000U)
34651 #define ENET_EIR_TS_AVAIL_SHIFT                  (16U)
34652 /*! TS_AVAIL - Transmit Timestamp Available */
34653 #define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
34654 
34655 #define ENET_EIR_WAKEUP_MASK                     (0x20000U)
34656 #define ENET_EIR_WAKEUP_SHIFT                    (17U)
34657 /*! WAKEUP - Node Wakeup Request Indication */
34658 #define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
34659 
34660 #define ENET_EIR_PLR_MASK                        (0x40000U)
34661 #define ENET_EIR_PLR_SHIFT                       (18U)
34662 /*! PLR - Payload Receive Error */
34663 #define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
34664 
34665 #define ENET_EIR_UN_MASK                         (0x80000U)
34666 #define ENET_EIR_UN_SHIFT                        (19U)
34667 /*! UN - Transmit FIFO Underrun */
34668 #define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
34669 
34670 #define ENET_EIR_RL_MASK                         (0x100000U)
34671 #define ENET_EIR_RL_SHIFT                        (20U)
34672 /*! RL - Collision Retry Limit */
34673 #define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
34674 
34675 #define ENET_EIR_LC_MASK                         (0x200000U)
34676 #define ENET_EIR_LC_SHIFT                        (21U)
34677 /*! LC - Late Collision */
34678 #define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
34679 
34680 #define ENET_EIR_EBERR_MASK                      (0x400000U)
34681 #define ENET_EIR_EBERR_SHIFT                     (22U)
34682 /*! EBERR - Ethernet Bus Error */
34683 #define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
34684 
34685 #define ENET_EIR_MII_MASK                        (0x800000U)
34686 #define ENET_EIR_MII_SHIFT                       (23U)
34687 /*! MII - MII Interrupt. */
34688 #define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
34689 
34690 #define ENET_EIR_RXB_MASK                        (0x1000000U)
34691 #define ENET_EIR_RXB_SHIFT                       (24U)
34692 /*! RXB - Receive Buffer Interrupt */
34693 #define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
34694 
34695 #define ENET_EIR_RXF_MASK                        (0x2000000U)
34696 #define ENET_EIR_RXF_SHIFT                       (25U)
34697 /*! RXF - Receive Frame Interrupt */
34698 #define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
34699 
34700 #define ENET_EIR_TXB_MASK                        (0x4000000U)
34701 #define ENET_EIR_TXB_SHIFT                       (26U)
34702 /*! TXB - Transmit Buffer Interrupt */
34703 #define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
34704 
34705 #define ENET_EIR_TXF_MASK                        (0x8000000U)
34706 #define ENET_EIR_TXF_SHIFT                       (27U)
34707 /*! TXF - Transmit Frame Interrupt */
34708 #define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
34709 
34710 #define ENET_EIR_GRA_MASK                        (0x10000000U)
34711 #define ENET_EIR_GRA_SHIFT                       (28U)
34712 /*! GRA - Graceful Stop Complete */
34713 #define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
34714 
34715 #define ENET_EIR_BABT_MASK                       (0x20000000U)
34716 #define ENET_EIR_BABT_SHIFT                      (29U)
34717 /*! BABT - Babbling Transmit Error */
34718 #define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
34719 
34720 #define ENET_EIR_BABR_MASK                       (0x40000000U)
34721 #define ENET_EIR_BABR_SHIFT                      (30U)
34722 /*! BABR - Babbling Receive Error */
34723 #define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
34724 /*! @} */
34725 
34726 /*! @name EIMR - Interrupt Mask Register */
34727 /*! @{ */
34728 
34729 #define ENET_EIMR_RXB1_MASK                      (0x1U)
34730 #define ENET_EIMR_RXB1_SHIFT                     (0U)
34731 /*! RXB1 - Receive buffer interrupt, class 1
34732  *  0b0..The corresponding interrupt source is masked.
34733  *  0b1..The corresponding interrupt source is not masked.
34734  */
34735 #define ENET_EIMR_RXB1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)
34736 
34737 #define ENET_EIMR_RXF1_MASK                      (0x2U)
34738 #define ENET_EIMR_RXF1_SHIFT                     (1U)
34739 /*! RXF1 - Receive frame interrupt, class 1
34740  *  0b0..The corresponding interrupt source is masked.
34741  *  0b1..The corresponding interrupt source is not masked.
34742  */
34743 #define ENET_EIMR_RXF1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)
34744 
34745 #define ENET_EIMR_TXB1_MASK                      (0x4U)
34746 #define ENET_EIMR_TXB1_SHIFT                     (2U)
34747 /*! TXB1 - Transmit buffer interrupt, class 1
34748  *  0b0..The corresponding interrupt source is masked.
34749  *  0b1..The corresponding interrupt source is not masked.
34750  */
34751 #define ENET_EIMR_TXB1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)
34752 
34753 #define ENET_EIMR_TXF1_MASK                      (0x8U)
34754 #define ENET_EIMR_TXF1_SHIFT                     (3U)
34755 /*! TXF1 - Transmit frame interrupt, class 1
34756  *  0b0..The corresponding interrupt source is masked.
34757  *  0b1..The corresponding interrupt source is not masked.
34758  */
34759 #define ENET_EIMR_TXF1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)
34760 
34761 #define ENET_EIMR_RXB2_MASK                      (0x10U)
34762 #define ENET_EIMR_RXB2_SHIFT                     (4U)
34763 /*! RXB2 - Receive buffer interrupt, class 2
34764  *  0b0..The corresponding interrupt source is masked.
34765  *  0b1..The corresponding interrupt source is not masked.
34766  */
34767 #define ENET_EIMR_RXB2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)
34768 
34769 #define ENET_EIMR_RXF2_MASK                      (0x20U)
34770 #define ENET_EIMR_RXF2_SHIFT                     (5U)
34771 /*! RXF2 - Receive frame interrupt, class 2
34772  *  0b0..The corresponding interrupt source is masked.
34773  *  0b1..The corresponding interrupt source is not masked.
34774  */
34775 #define ENET_EIMR_RXF2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)
34776 
34777 #define ENET_EIMR_TXB2_MASK                      (0x40U)
34778 #define ENET_EIMR_TXB2_SHIFT                     (6U)
34779 /*! TXB2 - Transmit buffer interrupt, class 2
34780  *  0b0..The corresponding interrupt source is masked.
34781  *  0b1..The corresponding interrupt source is not masked.
34782  */
34783 #define ENET_EIMR_TXB2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)
34784 
34785 #define ENET_EIMR_TXF2_MASK                      (0x80U)
34786 #define ENET_EIMR_TXF2_SHIFT                     (7U)
34787 /*! TXF2 - Transmit frame interrupt, class 2
34788  *  0b0..The corresponding interrupt source is masked.
34789  *  0b1..The corresponding interrupt source is not masked.
34790  */
34791 #define ENET_EIMR_TXF2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)
34792 
34793 #define ENET_EIMR_RXFLUSH_0_MASK                 (0x1000U)
34794 #define ENET_EIMR_RXFLUSH_0_SHIFT                (12U)
34795 /*! RXFLUSH_0
34796  *  0b0..The corresponding interrupt source is masked.
34797  *  0b1..The corresponding interrupt source is not masked.
34798  */
34799 #define ENET_EIMR_RXFLUSH_0(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)
34800 
34801 #define ENET_EIMR_RXFLUSH_1_MASK                 (0x2000U)
34802 #define ENET_EIMR_RXFLUSH_1_SHIFT                (13U)
34803 /*! RXFLUSH_1
34804  *  0b0..The corresponding interrupt source is masked.
34805  *  0b1..The corresponding interrupt source is not masked.
34806  */
34807 #define ENET_EIMR_RXFLUSH_1(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)
34808 
34809 #define ENET_EIMR_RXFLUSH_2_MASK                 (0x4000U)
34810 #define ENET_EIMR_RXFLUSH_2_SHIFT                (14U)
34811 /*! RXFLUSH_2
34812  *  0b0..The corresponding interrupt source is masked.
34813  *  0b1..The corresponding interrupt source is not masked.
34814  */
34815 #define ENET_EIMR_RXFLUSH_2(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)
34816 
34817 #define ENET_EIMR_TS_TIMER_MASK                  (0x8000U)
34818 #define ENET_EIMR_TS_TIMER_SHIFT                 (15U)
34819 /*! TS_TIMER - TS_TIMER Interrupt Mask
34820  *  0b0..The corresponding interrupt source is masked.
34821  *  0b1..The corresponding interrupt source is not masked.
34822  */
34823 #define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
34824 
34825 #define ENET_EIMR_TS_AVAIL_MASK                  (0x10000U)
34826 #define ENET_EIMR_TS_AVAIL_SHIFT                 (16U)
34827 /*! TS_AVAIL - TS_AVAIL Interrupt Mask
34828  *  0b0..The corresponding interrupt source is masked.
34829  *  0b1..The corresponding interrupt source is not masked.
34830  */
34831 #define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
34832 
34833 #define ENET_EIMR_WAKEUP_MASK                    (0x20000U)
34834 #define ENET_EIMR_WAKEUP_SHIFT                   (17U)
34835 /*! WAKEUP - WAKEUP Interrupt Mask
34836  *  0b0..The corresponding interrupt source is masked.
34837  *  0b1..The corresponding interrupt source is not masked.
34838  */
34839 #define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
34840 
34841 #define ENET_EIMR_PLR_MASK                       (0x40000U)
34842 #define ENET_EIMR_PLR_SHIFT                      (18U)
34843 /*! PLR - PLR Interrupt Mask
34844  *  0b0..The corresponding interrupt source is masked.
34845  *  0b1..The corresponding interrupt source is not masked.
34846  */
34847 #define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
34848 
34849 #define ENET_EIMR_UN_MASK                        (0x80000U)
34850 #define ENET_EIMR_UN_SHIFT                       (19U)
34851 /*! UN - UN Interrupt Mask
34852  *  0b0..The corresponding interrupt source is masked.
34853  *  0b1..The corresponding interrupt source is not masked.
34854  */
34855 #define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
34856 
34857 #define ENET_EIMR_RL_MASK                        (0x100000U)
34858 #define ENET_EIMR_RL_SHIFT                       (20U)
34859 /*! RL - RL Interrupt Mask
34860  *  0b0..The corresponding interrupt source is masked.
34861  *  0b1..The corresponding interrupt source is not masked.
34862  */
34863 #define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
34864 
34865 #define ENET_EIMR_LC_MASK                        (0x200000U)
34866 #define ENET_EIMR_LC_SHIFT                       (21U)
34867 /*! LC - LC Interrupt Mask
34868  *  0b0..The corresponding interrupt source is masked.
34869  *  0b1..The corresponding interrupt source is not masked.
34870  */
34871 #define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
34872 
34873 #define ENET_EIMR_EBERR_MASK                     (0x400000U)
34874 #define ENET_EIMR_EBERR_SHIFT                    (22U)
34875 /*! EBERR - EBERR Interrupt Mask
34876  *  0b0..The corresponding interrupt source is masked.
34877  *  0b1..The corresponding interrupt source is not masked.
34878  */
34879 #define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
34880 
34881 #define ENET_EIMR_MII_MASK                       (0x800000U)
34882 #define ENET_EIMR_MII_SHIFT                      (23U)
34883 /*! MII - MII Interrupt Mask
34884  *  0b0..The corresponding interrupt source is masked.
34885  *  0b1..The corresponding interrupt source is not masked.
34886  */
34887 #define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
34888 
34889 #define ENET_EIMR_RXB_MASK                       (0x1000000U)
34890 #define ENET_EIMR_RXB_SHIFT                      (24U)
34891 /*! RXB - RXB Interrupt Mask
34892  *  0b0..The corresponding interrupt source is masked.
34893  *  0b1..The corresponding interrupt source is not masked.
34894  */
34895 #define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
34896 
34897 #define ENET_EIMR_RXF_MASK                       (0x2000000U)
34898 #define ENET_EIMR_RXF_SHIFT                      (25U)
34899 /*! RXF - RXF Interrupt Mask
34900  *  0b0..The corresponding interrupt source is masked.
34901  *  0b1..The corresponding interrupt source is not masked.
34902  */
34903 #define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
34904 
34905 #define ENET_EIMR_TXB_MASK                       (0x4000000U)
34906 #define ENET_EIMR_TXB_SHIFT                      (26U)
34907 /*! TXB - TXB Interrupt Mask
34908  *  0b0..The corresponding interrupt source is masked.
34909  *  0b1..The corresponding interrupt source is not masked.
34910  */
34911 #define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
34912 
34913 #define ENET_EIMR_TXF_MASK                       (0x8000000U)
34914 #define ENET_EIMR_TXF_SHIFT                      (27U)
34915 /*! TXF - TXF Interrupt Mask
34916  *  0b0..The corresponding interrupt source is masked.
34917  *  0b1..The corresponding interrupt source is not masked.
34918  */
34919 #define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
34920 
34921 #define ENET_EIMR_GRA_MASK                       (0x10000000U)
34922 #define ENET_EIMR_GRA_SHIFT                      (28U)
34923 /*! GRA - GRA Interrupt Mask
34924  *  0b0..The corresponding interrupt source is masked.
34925  *  0b1..The corresponding interrupt source is not masked.
34926  */
34927 #define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
34928 
34929 #define ENET_EIMR_BABT_MASK                      (0x20000000U)
34930 #define ENET_EIMR_BABT_SHIFT                     (29U)
34931 /*! BABT - BABT Interrupt Mask
34932  *  0b0..The corresponding interrupt source is masked.
34933  *  0b1..The corresponding interrupt source is not masked.
34934  */
34935 #define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
34936 
34937 #define ENET_EIMR_BABR_MASK                      (0x40000000U)
34938 #define ENET_EIMR_BABR_SHIFT                     (30U)
34939 /*! BABR - BABR Interrupt Mask
34940  *  0b0..The corresponding interrupt source is masked.
34941  *  0b1..The corresponding interrupt source is not masked.
34942  */
34943 #define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
34944 /*! @} */
34945 
34946 /*! @name RDAR - Receive Descriptor Active Register - Ring 0 */
34947 /*! @{ */
34948 
34949 #define ENET_RDAR_RDAR_MASK                      (0x1000000U)
34950 #define ENET_RDAR_RDAR_SHIFT                     (24U)
34951 /*! RDAR - Receive Descriptor Active */
34952 #define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
34953 /*! @} */
34954 
34955 /*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */
34956 /*! @{ */
34957 
34958 #define ENET_TDAR_TDAR_MASK                      (0x1000000U)
34959 #define ENET_TDAR_TDAR_SHIFT                     (24U)
34960 /*! TDAR - Transmit Descriptor Active */
34961 #define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
34962 /*! @} */
34963 
34964 /*! @name ECR - Ethernet Control Register */
34965 /*! @{ */
34966 
34967 #define ENET_ECR_RESET_MASK                      (0x1U)
34968 #define ENET_ECR_RESET_SHIFT                     (0U)
34969 /*! RESET - Ethernet MAC Reset */
34970 #define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
34971 
34972 #define ENET_ECR_ETHEREN_MASK                    (0x2U)
34973 #define ENET_ECR_ETHEREN_SHIFT                   (1U)
34974 /*! ETHEREN - Ethernet Enable
34975  *  0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
34976  *  0b1..MAC is enabled, and reception and transmission are possible.
34977  */
34978 #define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
34979 
34980 #define ENET_ECR_MAGICEN_MASK                    (0x4U)
34981 #define ENET_ECR_MAGICEN_SHIFT                   (2U)
34982 /*! MAGICEN - Magic Packet Detection Enable
34983  *  0b0..Magic detection logic disabled.
34984  *  0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
34985  */
34986 #define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
34987 
34988 #define ENET_ECR_SLEEP_MASK                      (0x8U)
34989 #define ENET_ECR_SLEEP_SHIFT                     (3U)
34990 /*! SLEEP - Sleep Mode Enable
34991  *  0b0..Normal operating mode.
34992  *  0b1..Sleep mode.
34993  */
34994 #define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
34995 
34996 #define ENET_ECR_EN1588_MASK                     (0x10U)
34997 #define ENET_ECR_EN1588_SHIFT                    (4U)
34998 /*! EN1588 - EN1588 Enable
34999  *  0b0..Legacy FEC buffer descriptors and functions enabled.
35000  *  0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588.
35001  */
35002 #define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
35003 
35004 #define ENET_ECR_SPEED_MASK                      (0x20U)
35005 #define ENET_ECR_SPEED_SHIFT                     (5U)
35006 /*! SPEED
35007  *  0b0..10/100-Mbit/s mode
35008  *  0b1..1000-Mbit/s mode
35009  */
35010 #define ENET_ECR_SPEED(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)
35011 
35012 #define ENET_ECR_DBGEN_MASK                      (0x40U)
35013 #define ENET_ECR_DBGEN_SHIFT                     (6U)
35014 /*! DBGEN - Debug Enable
35015  *  0b0..MAC continues operation in debug mode.
35016  *  0b1..MAC enters hardware freeze mode when the processor is in debug mode.
35017  */
35018 #define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
35019 
35020 #define ENET_ECR_DBSWP_MASK                      (0x100U)
35021 #define ENET_ECR_DBSWP_SHIFT                     (8U)
35022 /*! DBSWP - Descriptor Byte Swapping Enable
35023  *  0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
35024  *  0b1..The buffer descriptor bytes are swapped to support little-endian devices.
35025  */
35026 #define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
35027 
35028 #define ENET_ECR_SVLANEN_MASK                    (0x200U)
35029 #define ENET_ECR_SVLANEN_SHIFT                   (9U)
35030 /*! SVLANEN - S-VLAN enable
35031  *  0b0..Only the EtherType 0x8100 will be considered for VLAN detection.
35032  *  0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in
35033  *       receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the
35034  *       classification match comparators, RCMRn.
35035  */
35036 #define ENET_ECR_SVLANEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)
35037 
35038 #define ENET_ECR_VLANUSE2ND_MASK                 (0x400U)
35039 #define ENET_ECR_VLANUSE2ND_SHIFT                (10U)
35040 /*! VLANUSE2ND - VLAN use second tag
35041  *  0b0..Always extract data from the first VLAN tag if it exists.
35042  *  0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A
35043  *       double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The
35044  *       second tag must be a C-VLAN
35045  */
35046 #define ENET_ECR_VLANUSE2ND(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)
35047 
35048 #define ENET_ECR_SVLANDBL_MASK                   (0x800U)
35049 #define ENET_ECR_SVLANDBL_SHIFT                  (11U)
35050 /*! SVLANDBL - S-VLAN double tag
35051  *  0b0..Disable S-VLAN double tag
35052  *  0b1..Enable S-VLAN double tag
35053  */
35054 #define ENET_ECR_SVLANDBL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)
35055 
35056 #define ENET_ECR_TXC_DLY_MASK                    (0x10000U)
35057 #define ENET_ECR_TXC_DLY_SHIFT                   (16U)
35058 /*! TXC_DLY - Transmit clock delay
35059  *  0b0..RGMII_TXC is not delayed.
35060  *  0b1..Generate delayed version of RGMII_TXC.
35061  */
35062 #define ENET_ECR_TXC_DLY(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK)
35063 /*! @} */
35064 
35065 /*! @name MMFR - MII Management Frame Register */
35066 /*! @{ */
35067 
35068 #define ENET_MMFR_DATA_MASK                      (0xFFFFU)
35069 #define ENET_MMFR_DATA_SHIFT                     (0U)
35070 /*! DATA - Management Frame Data */
35071 #define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
35072 
35073 #define ENET_MMFR_TA_MASK                        (0x30000U)
35074 #define ENET_MMFR_TA_SHIFT                       (16U)
35075 /*! TA - Turn Around */
35076 #define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
35077 
35078 #define ENET_MMFR_RA_MASK                        (0x7C0000U)
35079 #define ENET_MMFR_RA_SHIFT                       (18U)
35080 /*! RA - Register Address */
35081 #define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
35082 
35083 #define ENET_MMFR_PA_MASK                        (0xF800000U)
35084 #define ENET_MMFR_PA_SHIFT                       (23U)
35085 /*! PA - PHY Address */
35086 #define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
35087 
35088 #define ENET_MMFR_OP_MASK                        (0x30000000U)
35089 #define ENET_MMFR_OP_SHIFT                       (28U)
35090 /*! OP - Operation Code */
35091 #define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
35092 
35093 #define ENET_MMFR_ST_MASK                        (0xC0000000U)
35094 #define ENET_MMFR_ST_SHIFT                       (30U)
35095 /*! ST - Start Of Frame Delimiter */
35096 #define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
35097 /*! @} */
35098 
35099 /*! @name MSCR - MII Speed Control Register */
35100 /*! @{ */
35101 
35102 #define ENET_MSCR_MII_SPEED_MASK                 (0x7EU)
35103 #define ENET_MSCR_MII_SPEED_SHIFT                (1U)
35104 /*! MII_SPEED - MII Speed */
35105 #define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
35106 
35107 #define ENET_MSCR_DIS_PRE_MASK                   (0x80U)
35108 #define ENET_MSCR_DIS_PRE_SHIFT                  (7U)
35109 /*! DIS_PRE - Disable Preamble
35110  *  0b0..Preamble enabled.
35111  *  0b1..Preamble (32 ones) is not prepended to the MII management frame.
35112  */
35113 #define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
35114 
35115 #define ENET_MSCR_HOLDTIME_MASK                  (0x700U)
35116 #define ENET_MSCR_HOLDTIME_SHIFT                 (8U)
35117 /*! HOLDTIME - Hold time On MDIO Output
35118  *  0b000..1 internal module clock cycle
35119  *  0b001..2 internal module clock cycles
35120  *  0b010..3 internal module clock cycles
35121  *  0b111..8 internal module clock cycles
35122  */
35123 #define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
35124 /*! @} */
35125 
35126 /*! @name MIBC - MIB Control Register */
35127 /*! @{ */
35128 
35129 #define ENET_MIBC_MIB_CLEAR_MASK                 (0x20000000U)
35130 #define ENET_MIBC_MIB_CLEAR_SHIFT                (29U)
35131 /*! MIB_CLEAR - MIB Clear
35132  *  0b0..See note above.
35133  *  0b1..All statistics counters are reset to 0.
35134  */
35135 #define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
35136 
35137 #define ENET_MIBC_MIB_IDLE_MASK                  (0x40000000U)
35138 #define ENET_MIBC_MIB_IDLE_SHIFT                 (30U)
35139 /*! MIB_IDLE - MIB Idle
35140  *  0b0..The MIB block is updating MIB counters.
35141  *  0b1..The MIB block is not currently updating any MIB counters.
35142  */
35143 #define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
35144 
35145 #define ENET_MIBC_MIB_DIS_MASK                   (0x80000000U)
35146 #define ENET_MIBC_MIB_DIS_SHIFT                  (31U)
35147 /*! MIB_DIS - Disable MIB Logic
35148  *  0b0..MIB logic is enabled.
35149  *  0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
35150  */
35151 #define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
35152 /*! @} */
35153 
35154 /*! @name RCR - Receive Control Register */
35155 /*! @{ */
35156 
35157 #define ENET_RCR_LOOP_MASK                       (0x1U)
35158 #define ENET_RCR_LOOP_SHIFT                      (0U)
35159 /*! LOOP - Internal Loopback
35160  *  0b0..Loopback disabled.
35161  *  0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
35162  */
35163 #define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
35164 
35165 #define ENET_RCR_DRT_MASK                        (0x2U)
35166 #define ENET_RCR_DRT_SHIFT                       (1U)
35167 /*! DRT - Disable Receive On Transmit
35168  *  0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
35169  *  0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
35170  */
35171 #define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
35172 
35173 #define ENET_RCR_MII_MODE_MASK                   (0x4U)
35174 #define ENET_RCR_MII_MODE_SHIFT                  (2U)
35175 /*! MII_MODE - Media Independent Interface Mode
35176  *  0b0..Reserved.
35177  *  0b1..MII or RMII mode, as indicated by the RMII_MODE field.
35178  */
35179 #define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
35180 
35181 #define ENET_RCR_PROM_MASK                       (0x8U)
35182 #define ENET_RCR_PROM_SHIFT                      (3U)
35183 /*! PROM - Promiscuous Mode
35184  *  0b0..Disabled.
35185  *  0b1..Enabled.
35186  */
35187 #define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
35188 
35189 #define ENET_RCR_BC_REJ_MASK                     (0x10U)
35190 #define ENET_RCR_BC_REJ_SHIFT                    (4U)
35191 /*! BC_REJ - Broadcast Frame Reject
35192  *  0b0..Will not reject frames as described above
35193  *  0b1..Will reject frames as described above
35194  */
35195 #define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
35196 
35197 #define ENET_RCR_FCE_MASK                        (0x20U)
35198 #define ENET_RCR_FCE_SHIFT                       (5U)
35199 /*! FCE - Flow Control Enable
35200  *  0b0..Disable flow control
35201  *  0b1..Enable flow control
35202  */
35203 #define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
35204 
35205 #define ENET_RCR_RGMII_EN_MASK                   (0x40U)
35206 #define ENET_RCR_RGMII_EN_SHIFT                  (6U)
35207 /*! RGMII_EN - RGMII Mode Enable
35208  *  0b0..MAC configured for non-RGMII operation
35209  *  0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If
35210  *       ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode.
35211  */
35212 #define ENET_RCR_RGMII_EN(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)
35213 
35214 #define ENET_RCR_RMII_MODE_MASK                  (0x100U)
35215 #define ENET_RCR_RMII_MODE_SHIFT                 (8U)
35216 /*! RMII_MODE - RMII Mode Enable
35217  *  0b0..MAC configured for MII mode.
35218  *  0b1..MAC configured for RMII operation.
35219  */
35220 #define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
35221 
35222 #define ENET_RCR_RMII_10T_MASK                   (0x200U)
35223 #define ENET_RCR_RMII_10T_SHIFT                  (9U)
35224 /*! RMII_10T
35225  *  0b0..100-Mbit/s or 1-Gbit/s operation.
35226  *  0b1..10-Mbit/s operation.
35227  */
35228 #define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
35229 
35230 #define ENET_RCR_PADEN_MASK                      (0x1000U)
35231 #define ENET_RCR_PADEN_SHIFT                     (12U)
35232 /*! PADEN - Enable Frame Padding Remove On Receive
35233  *  0b0..No padding is removed on receive by the MAC.
35234  *  0b1..Padding is removed from received frames.
35235  */
35236 #define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
35237 
35238 #define ENET_RCR_PAUFWD_MASK                     (0x2000U)
35239 #define ENET_RCR_PAUFWD_SHIFT                    (13U)
35240 /*! PAUFWD - Terminate/Forward Pause Frames
35241  *  0b0..Pause frames are terminated and discarded in the MAC.
35242  *  0b1..Pause frames are forwarded to the user application.
35243  */
35244 #define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
35245 
35246 #define ENET_RCR_CRCFWD_MASK                     (0x4000U)
35247 #define ENET_RCR_CRCFWD_SHIFT                    (14U)
35248 /*! CRCFWD - Terminate/Forward Received CRC
35249  *  0b0..The CRC field of received frames is transmitted to the user application.
35250  *  0b1..The CRC field is stripped from the frame.
35251  */
35252 #define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
35253 
35254 #define ENET_RCR_CFEN_MASK                       (0x8000U)
35255 #define ENET_RCR_CFEN_SHIFT                      (15U)
35256 /*! CFEN - MAC Control Frame Enable
35257  *  0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
35258  *  0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
35259  */
35260 #define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
35261 
35262 #define ENET_RCR_MAX_FL_MASK                     (0x3FFF0000U)
35263 #define ENET_RCR_MAX_FL_SHIFT                    (16U)
35264 /*! MAX_FL - Maximum Frame Length */
35265 #define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
35266 
35267 #define ENET_RCR_NLC_MASK                        (0x40000000U)
35268 #define ENET_RCR_NLC_SHIFT                       (30U)
35269 /*! NLC - Payload Length Check Disable
35270  *  0b0..The payload length check is disabled.
35271  *  0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
35272  */
35273 #define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
35274 
35275 #define ENET_RCR_GRS_MASK                        (0x80000000U)
35276 #define ENET_RCR_GRS_SHIFT                       (31U)
35277 /*! GRS - Graceful Receive Stopped
35278  *  0b0..Receive not stopped
35279  *  0b1..Receive stopped
35280  */
35281 #define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
35282 /*! @} */
35283 
35284 /*! @name TCR - Transmit Control Register */
35285 /*! @{ */
35286 
35287 #define ENET_TCR_GTS_MASK                        (0x1U)
35288 #define ENET_TCR_GTS_SHIFT                       (0U)
35289 /*! GTS - Graceful Transmit Stop
35290  *  0b0..Disable graceful transmit stop
35291  *  0b1..Enable graceful transmit stop
35292  */
35293 #define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
35294 
35295 #define ENET_TCR_FDEN_MASK                       (0x4U)
35296 #define ENET_TCR_FDEN_SHIFT                      (2U)
35297 /*! FDEN - Full-Duplex Enable
35298  *  0b0..Disable full-duplex
35299  *  0b1..Enable full-duplex
35300  */
35301 #define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
35302 
35303 #define ENET_TCR_TFC_PAUSE_MASK                  (0x8U)
35304 #define ENET_TCR_TFC_PAUSE_SHIFT                 (3U)
35305 /*! TFC_PAUSE - Transmit Frame Control Pause
35306  *  0b0..No PAUSE frame transmitted.
35307  *  0b1..The MAC stops transmission of data frames after the current transmission is complete.
35308  */
35309 #define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
35310 
35311 #define ENET_TCR_RFC_PAUSE_MASK                  (0x10U)
35312 #define ENET_TCR_RFC_PAUSE_SHIFT                 (4U)
35313 /*! RFC_PAUSE - Receive Frame Control Pause */
35314 #define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
35315 
35316 #define ENET_TCR_ADDSEL_MASK                     (0xE0U)
35317 #define ENET_TCR_ADDSEL_SHIFT                    (5U)
35318 /*! ADDSEL - Source MAC Address Select On Transmit
35319  *  0b000..Node MAC address programmed on PADDR1/2 registers.
35320  *  0b100..Reserved.
35321  *  0b101..Reserved.
35322  *  0b110..Reserved.
35323  */
35324 #define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
35325 
35326 #define ENET_TCR_ADDINS_MASK                     (0x100U)
35327 #define ENET_TCR_ADDINS_SHIFT                    (8U)
35328 /*! ADDINS - Set MAC Address On Transmit
35329  *  0b0..The source MAC address is not modified by the MAC.
35330  *  0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
35331  */
35332 #define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
35333 
35334 #define ENET_TCR_CRCFWD_MASK                     (0x200U)
35335 #define ENET_TCR_CRCFWD_SHIFT                    (9U)
35336 /*! CRCFWD - Forward Frame From Application With CRC
35337  *  0b0..TxBD[TC] controls whether the frame has a CRC from the application.
35338  *  0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
35339  */
35340 #define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
35341 /*! @} */
35342 
35343 /*! @name PALR - Physical Address Lower Register */
35344 /*! @{ */
35345 
35346 #define ENET_PALR_PADDR1_MASK                    (0xFFFFFFFFU)
35347 #define ENET_PALR_PADDR1_SHIFT                   (0U)
35348 /*! PADDR1 - Pause Address */
35349 #define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
35350 /*! @} */
35351 
35352 /*! @name PAUR - Physical Address Upper Register */
35353 /*! @{ */
35354 
35355 #define ENET_PAUR_TYPE_MASK                      (0xFFFFU)
35356 #define ENET_PAUR_TYPE_SHIFT                     (0U)
35357 /*! TYPE - Type Field In PAUSE Frames */
35358 #define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
35359 
35360 #define ENET_PAUR_PADDR2_MASK                    (0xFFFF0000U)
35361 #define ENET_PAUR_PADDR2_SHIFT                   (16U)
35362 #define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
35363 /*! @} */
35364 
35365 /*! @name OPD - Opcode/Pause Duration Register */
35366 /*! @{ */
35367 
35368 #define ENET_OPD_PAUSE_DUR_MASK                  (0xFFFFU)
35369 #define ENET_OPD_PAUSE_DUR_SHIFT                 (0U)
35370 /*! PAUSE_DUR - Pause Duration */
35371 #define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
35372 
35373 #define ENET_OPD_OPCODE_MASK                     (0xFFFF0000U)
35374 #define ENET_OPD_OPCODE_SHIFT                    (16U)
35375 /*! OPCODE - Opcode Field In PAUSE Frames */
35376 #define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
35377 /*! @} */
35378 
35379 /*! @name TXIC - Transmit Interrupt Coalescing Register */
35380 /*! @{ */
35381 
35382 #define ENET_TXIC_ICTT_MASK                      (0xFFFFU)
35383 #define ENET_TXIC_ICTT_SHIFT                     (0U)
35384 /*! ICTT - Interrupt coalescing timer threshold */
35385 #define ENET_TXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
35386 
35387 #define ENET_TXIC_ICFT_MASK                      (0xFF00000U)
35388 #define ENET_TXIC_ICFT_SHIFT                     (20U)
35389 /*! ICFT - Interrupt coalescing frame count threshold */
35390 #define ENET_TXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
35391 
35392 #define ENET_TXIC_ICCS_MASK                      (0x40000000U)
35393 #define ENET_TXIC_ICCS_SHIFT                     (30U)
35394 /*! ICCS - Interrupt Coalescing Timer Clock Source Select
35395  *  0b0..Use MII/GMII TX clocks.
35396  *  0b1..Use ENET system clock.
35397  */
35398 #define ENET_TXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
35399 
35400 #define ENET_TXIC_ICEN_MASK                      (0x80000000U)
35401 #define ENET_TXIC_ICEN_SHIFT                     (31U)
35402 /*! ICEN - Interrupt Coalescing Enable
35403  *  0b0..Disable Interrupt coalescing.
35404  *  0b1..Enable Interrupt coalescing.
35405  */
35406 #define ENET_TXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
35407 /*! @} */
35408 
35409 /* The count of ENET_TXIC */
35410 #define ENET_TXIC_COUNT                          (3U)
35411 
35412 /*! @name RXIC - Receive Interrupt Coalescing Register */
35413 /*! @{ */
35414 
35415 #define ENET_RXIC_ICTT_MASK                      (0xFFFFU)
35416 #define ENET_RXIC_ICTT_SHIFT                     (0U)
35417 /*! ICTT - Interrupt coalescing timer threshold */
35418 #define ENET_RXIC_ICTT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
35419 
35420 #define ENET_RXIC_ICFT_MASK                      (0xFF00000U)
35421 #define ENET_RXIC_ICFT_SHIFT                     (20U)
35422 /*! ICFT - Interrupt coalescing frame count threshold */
35423 #define ENET_RXIC_ICFT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
35424 
35425 #define ENET_RXIC_ICCS_MASK                      (0x40000000U)
35426 #define ENET_RXIC_ICCS_SHIFT                     (30U)
35427 /*! ICCS - Interrupt Coalescing Timer Clock Source Select
35428  *  0b0..Use MII/GMII TX clocks.
35429  *  0b1..Use ENET system clock.
35430  */
35431 #define ENET_RXIC_ICCS(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
35432 
35433 #define ENET_RXIC_ICEN_MASK                      (0x80000000U)
35434 #define ENET_RXIC_ICEN_SHIFT                     (31U)
35435 /*! ICEN - Interrupt Coalescing Enable
35436  *  0b0..Disable Interrupt coalescing.
35437  *  0b1..Enable Interrupt coalescing.
35438  */
35439 #define ENET_RXIC_ICEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
35440 /*! @} */
35441 
35442 /* The count of ENET_RXIC */
35443 #define ENET_RXIC_COUNT                          (3U)
35444 
35445 /*! @name IAUR - Descriptor Individual Upper Address Register */
35446 /*! @{ */
35447 
35448 #define ENET_IAUR_IADDR1_MASK                    (0xFFFFFFFFU)
35449 #define ENET_IAUR_IADDR1_SHIFT                   (0U)
35450 #define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
35451 /*! @} */
35452 
35453 /*! @name IALR - Descriptor Individual Lower Address Register */
35454 /*! @{ */
35455 
35456 #define ENET_IALR_IADDR2_MASK                    (0xFFFFFFFFU)
35457 #define ENET_IALR_IADDR2_SHIFT                   (0U)
35458 #define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
35459 /*! @} */
35460 
35461 /*! @name GAUR - Descriptor Group Upper Address Register */
35462 /*! @{ */
35463 
35464 #define ENET_GAUR_GADDR1_MASK                    (0xFFFFFFFFU)
35465 #define ENET_GAUR_GADDR1_SHIFT                   (0U)
35466 #define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
35467 /*! @} */
35468 
35469 /*! @name GALR - Descriptor Group Lower Address Register */
35470 /*! @{ */
35471 
35472 #define ENET_GALR_GADDR2_MASK                    (0xFFFFFFFFU)
35473 #define ENET_GALR_GADDR2_SHIFT                   (0U)
35474 #define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
35475 /*! @} */
35476 
35477 /*! @name TFWR - Transmit FIFO Watermark Register */
35478 /*! @{ */
35479 
35480 #define ENET_TFWR_TFWR_MASK                      (0x3FU)
35481 #define ENET_TFWR_TFWR_SHIFT                     (0U)
35482 /*! TFWR - Transmit FIFO Write
35483  *  0b000000..64 bytes written.
35484  *  0b000001..64 bytes written.
35485  *  0b000010..128 bytes written.
35486  *  0b000011..192 bytes written.
35487  *  0b011111..1984 bytes written.
35488  */
35489 #define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
35490 
35491 #define ENET_TFWR_STRFWD_MASK                    (0x100U)
35492 #define ENET_TFWR_STRFWD_SHIFT                   (8U)
35493 /*! STRFWD - Store And Forward Enable
35494  *  0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
35495  *  0b1..Enabled.
35496  */
35497 #define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
35498 /*! @} */
35499 
35500 /*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */
35501 /*! @{ */
35502 
35503 #define ENET_RDSR1_R_DES_START_MASK              (0xFFFFFFF8U)
35504 #define ENET_RDSR1_R_DES_START_SHIFT             (3U)
35505 #define ENET_RDSR1_R_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK)
35506 /*! @} */
35507 
35508 /*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */
35509 /*! @{ */
35510 
35511 #define ENET_TDSR1_X_DES_START_MASK              (0xFFFFFFF8U)
35512 #define ENET_TDSR1_X_DES_START_SHIFT             (3U)
35513 #define ENET_TDSR1_X_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK)
35514 /*! @} */
35515 
35516 /*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */
35517 /*! @{ */
35518 
35519 #define ENET_MRBR1_R_BUF_SIZE_MASK               (0x7F0U)
35520 #define ENET_MRBR1_R_BUF_SIZE_SHIFT              (4U)
35521 #define ENET_MRBR1_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK)
35522 /*! @} */
35523 
35524 /*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */
35525 /*! @{ */
35526 
35527 #define ENET_RDSR2_R_DES_START_MASK              (0xFFFFFFF8U)
35528 #define ENET_RDSR2_R_DES_START_SHIFT             (3U)
35529 #define ENET_RDSR2_R_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK)
35530 /*! @} */
35531 
35532 /*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */
35533 /*! @{ */
35534 
35535 #define ENET_TDSR2_X_DES_START_MASK              (0xFFFFFFF8U)
35536 #define ENET_TDSR2_X_DES_START_SHIFT             (3U)
35537 #define ENET_TDSR2_X_DES_START(x)                (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK)
35538 /*! @} */
35539 
35540 /*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */
35541 /*! @{ */
35542 
35543 #define ENET_MRBR2_R_BUF_SIZE_MASK               (0x7F0U)
35544 #define ENET_MRBR2_R_BUF_SIZE_SHIFT              (4U)
35545 #define ENET_MRBR2_R_BUF_SIZE(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK)
35546 /*! @} */
35547 
35548 /*! @name RDSR - Receive Descriptor Ring 0 Start Register */
35549 /*! @{ */
35550 
35551 #define ENET_RDSR_R_DES_START_MASK               (0xFFFFFFF8U)
35552 #define ENET_RDSR_R_DES_START_SHIFT              (3U)
35553 #define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
35554 /*! @} */
35555 
35556 /*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */
35557 /*! @{ */
35558 
35559 #define ENET_TDSR_X_DES_START_MASK               (0xFFFFFFF8U)
35560 #define ENET_TDSR_X_DES_START_SHIFT              (3U)
35561 #define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
35562 /*! @} */
35563 
35564 /*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */
35565 /*! @{ */
35566 
35567 #define ENET_MRBR_R_BUF_SIZE_MASK                (0x3FF0U)  /* Merged from fields with different position or width, of widths (7, 10), largest definition used */
35568 #define ENET_MRBR_R_BUF_SIZE_SHIFT               (4U)
35569 #define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)  /* Merged from fields with different position or width, of widths (7, 10), largest definition used */
35570 /*! @} */
35571 
35572 /*! @name RSFL - Receive FIFO Section Full Threshold */
35573 /*! @{ */
35574 
35575 #define ENET_RSFL_RX_SECTION_FULL_MASK           (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
35576 #define ENET_RSFL_RX_SECTION_FULL_SHIFT          (0U)
35577 /*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold */
35578 #define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
35579 /*! @} */
35580 
35581 /*! @name RSEM - Receive FIFO Section Empty Threshold */
35582 /*! @{ */
35583 
35584 #define ENET_RSEM_RX_SECTION_EMPTY_MASK          (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
35585 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         (0U)
35586 /*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold */
35587 #define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
35588 
35589 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK        (0x1F0000U)
35590 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       (16U)
35591 /*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold */
35592 #define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
35593 /*! @} */
35594 
35595 /*! @name RAEM - Receive FIFO Almost Empty Threshold */
35596 /*! @{ */
35597 
35598 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK           (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
35599 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          (0U)
35600 /*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold */
35601 #define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
35602 /*! @} */
35603 
35604 /*! @name RAFL - Receive FIFO Almost Full Threshold */
35605 /*! @{ */
35606 
35607 #define ENET_RAFL_RX_ALMOST_FULL_MASK            (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
35608 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT           (0U)
35609 /*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold */
35610 #define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
35611 /*! @} */
35612 
35613 /*! @name TSEM - Transmit FIFO Section Empty Threshold */
35614 /*! @{ */
35615 
35616 #define ENET_TSEM_TX_SECTION_EMPTY_MASK          (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
35617 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         (0U)
35618 /*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold */
35619 #define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
35620 /*! @} */
35621 
35622 /*! @name TAEM - Transmit FIFO Almost Empty Threshold */
35623 /*! @{ */
35624 
35625 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK           (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
35626 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          (0U)
35627 /*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold */
35628 #define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
35629 /*! @} */
35630 
35631 /*! @name TAFL - Transmit FIFO Almost Full Threshold */
35632 /*! @{ */
35633 
35634 #define ENET_TAFL_TX_ALMOST_FULL_MASK            (0x3FFU)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
35635 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT           (0U)
35636 /*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold */
35637 #define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)  /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
35638 /*! @} */
35639 
35640 /*! @name TIPG - Transmit Inter-Packet Gap */
35641 /*! @{ */
35642 
35643 #define ENET_TIPG_IPG_MASK                       (0x1FU)
35644 #define ENET_TIPG_IPG_SHIFT                      (0U)
35645 /*! IPG - Transmit Inter-Packet Gap */
35646 #define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
35647 /*! @} */
35648 
35649 /*! @name FTRL - Frame Truncation Length */
35650 /*! @{ */
35651 
35652 #define ENET_FTRL_TRUNC_FL_MASK                  (0x3FFFU)
35653 #define ENET_FTRL_TRUNC_FL_SHIFT                 (0U)
35654 /*! TRUNC_FL - Frame Truncation Length */
35655 #define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
35656 /*! @} */
35657 
35658 /*! @name TACC - Transmit Accelerator Function Configuration */
35659 /*! @{ */
35660 
35661 #define ENET_TACC_SHIFT16_MASK                   (0x1U)
35662 #define ENET_TACC_SHIFT16_SHIFT                  (0U)
35663 /*! SHIFT16 - TX FIFO Shift-16
35664  *  0b0..Disabled.
35665  *  0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the
35666  *       frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
35667  *       function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is
35668  *       extended to a 16-byte header.
35669  */
35670 #define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
35671 
35672 #define ENET_TACC_IPCHK_MASK                     (0x8U)
35673 #define ENET_TACC_IPCHK_SHIFT                    (3U)
35674 /*! IPCHK
35675  *  0b0..Checksum is not inserted.
35676  *  0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must
35677  *       be cleared. If a non-IP frame is transmitted the frame is not modified.
35678  */
35679 #define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
35680 
35681 #define ENET_TACC_PROCHK_MASK                    (0x10U)
35682 #define ENET_TACC_PROCHK_SHIFT                   (4U)
35683 /*! PROCHK
35684  *  0b0..Checksum not inserted.
35685  *  0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
35686  *       frame. The checksum field must be cleared. The other frames are not modified.
35687  */
35688 #define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
35689 /*! @} */
35690 
35691 /*! @name RACC - Receive Accelerator Function Configuration */
35692 /*! @{ */
35693 
35694 #define ENET_RACC_PADREM_MASK                    (0x1U)
35695 #define ENET_RACC_PADREM_SHIFT                   (0U)
35696 /*! PADREM - Enable Padding Removal For Short IP Frames
35697  *  0b0..Padding not removed.
35698  *  0b1..Any bytes following the IP payload section of the frame are removed from the frame.
35699  */
35700 #define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
35701 
35702 #define ENET_RACC_IPDIS_MASK                     (0x2U)
35703 #define ENET_RACC_IPDIS_SHIFT                    (1U)
35704 /*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
35705  *  0b0..Frames with wrong IPv4 header checksum are not discarded.
35706  *  0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
35707  *       header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in
35708  *       store and forward mode (RSFL cleared).
35709  */
35710 #define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
35711 
35712 #define ENET_RACC_PRODIS_MASK                    (0x4U)
35713 #define ENET_RACC_PRODIS_SHIFT                   (2U)
35714 /*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
35715  *  0b0..Frames with wrong checksum are not discarded.
35716  *  0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame
35717  *       is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL
35718  *       cleared).
35719  */
35720 #define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
35721 
35722 #define ENET_RACC_LINEDIS_MASK                   (0x40U)
35723 #define ENET_RACC_LINEDIS_SHIFT                  (6U)
35724 /*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
35725  *  0b0..Frames with errors are not discarded.
35726  *  0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
35727  */
35728 #define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
35729 
35730 #define ENET_RACC_SHIFT16_MASK                   (0x80U)
35731 #define ENET_RACC_SHIFT16_SHIFT                  (7U)
35732 /*! SHIFT16 - RX FIFO Shift-16
35733  *  0b0..Disabled.
35734  *  0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
35735  */
35736 #define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
35737 /*! @} */
35738 
35739 /*! @name RCMR - Receive Classification Match Register for Class n */
35740 /*! @{ */
35741 
35742 #define ENET_RCMR_CMP0_MASK                      (0x7U)
35743 #define ENET_RCMR_CMP0_SHIFT                     (0U)
35744 /*! CMP0 - Compare 0 */
35745 #define ENET_RCMR_CMP0(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)
35746 
35747 #define ENET_RCMR_CMP1_MASK                      (0x70U)
35748 #define ENET_RCMR_CMP1_SHIFT                     (4U)
35749 /*! CMP1 - Compare 1 */
35750 #define ENET_RCMR_CMP1(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)
35751 
35752 #define ENET_RCMR_CMP2_MASK                      (0x700U)
35753 #define ENET_RCMR_CMP2_SHIFT                     (8U)
35754 /*! CMP2 - Compare 2 */
35755 #define ENET_RCMR_CMP2(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)
35756 
35757 #define ENET_RCMR_CMP3_MASK                      (0x7000U)
35758 #define ENET_RCMR_CMP3_SHIFT                     (12U)
35759 /*! CMP3 - Compare 3 */
35760 #define ENET_RCMR_CMP3(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)
35761 
35762 #define ENET_RCMR_MATCHEN_MASK                   (0x10000U)
35763 #define ENET_RCMR_MATCHEN_SHIFT                  (16U)
35764 /*! MATCHEN - Match Enable
35765  *  0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert.
35766  *  0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received.
35767  */
35768 #define ENET_RCMR_MATCHEN(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)
35769 /*! @} */
35770 
35771 /* The count of ENET_RCMR */
35772 #define ENET_RCMR_COUNT                          (2U)
35773 
35774 /*! @name DMACFG - DMA Class Based Configuration */
35775 /*! @{ */
35776 
35777 #define ENET_DMACFG_IDLE_SLOPE_MASK              (0xFFFFU)
35778 #define ENET_DMACFG_IDLE_SLOPE_SHIFT             (0U)
35779 /*! IDLE_SLOPE - Idle slope */
35780 #define ENET_DMACFG_IDLE_SLOPE(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)
35781 
35782 #define ENET_DMACFG_DMA_CLASS_EN_MASK            (0x10000U)
35783 #define ENET_DMACFG_DMA_CLASS_EN_SHIFT           (16U)
35784 /*! DMA_CLASS_EN - DMA class enable
35785  *  0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also
35786  *       requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2
35787  *       queues are disabled then their frames will be placed in queue 0.
35788  *  0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic.
35789  */
35790 #define ENET_DMACFG_DMA_CLASS_EN(x)              (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)
35791 
35792 #define ENET_DMACFG_CALC_NOIPG_MASK              (0x20000U)
35793 #define ENET_DMACFG_CALC_NOIPG_SHIFT             (17U)
35794 /*! CALC_NOIPG - Calculate no IPG
35795  *  0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred
35796  *       for a frame when doing bandwidth calculations. This is the default.
35797  *  0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping,
35798  *       when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every
35799  *       frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames
35800  *       will become more bandwidth than large frames due to the relation of data to IPG overhead).
35801  */
35802 #define ENET_DMACFG_CALC_NOIPG(x)                (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)
35803 /*! @} */
35804 
35805 /* The count of ENET_DMACFG */
35806 #define ENET_DMACFG_COUNT                        (2U)
35807 
35808 /*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */
35809 /*! @{ */
35810 
35811 #define ENET_RDAR1_RDAR_MASK                     (0x1000000U)
35812 #define ENET_RDAR1_RDAR_SHIFT                    (24U)
35813 /*! RDAR - Receive Descriptor Active */
35814 #define ENET_RDAR1_RDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)
35815 /*! @} */
35816 
35817 /*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */
35818 /*! @{ */
35819 
35820 #define ENET_TDAR1_TDAR_MASK                     (0x1000000U)
35821 #define ENET_TDAR1_TDAR_SHIFT                    (24U)
35822 /*! TDAR - Transmit Descriptor Active */
35823 #define ENET_TDAR1_TDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK)
35824 /*! @} */
35825 
35826 /*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */
35827 /*! @{ */
35828 
35829 #define ENET_RDAR2_RDAR_MASK                     (0x1000000U)
35830 #define ENET_RDAR2_RDAR_SHIFT                    (24U)
35831 /*! RDAR - Receive Descriptor Active */
35832 #define ENET_RDAR2_RDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)
35833 /*! @} */
35834 
35835 /*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */
35836 /*! @{ */
35837 
35838 #define ENET_TDAR2_TDAR_MASK                     (0x1000000U)
35839 #define ENET_TDAR2_TDAR_SHIFT                    (24U)
35840 /*! TDAR - Transmit Descriptor Active */
35841 #define ENET_TDAR2_TDAR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK)
35842 /*! @} */
35843 
35844 /*! @name QOS - QOS Scheme */
35845 /*! @{ */
35846 
35847 #define ENET_QOS_TX_SCHEME_MASK                  (0x7U)
35848 #define ENET_QOS_TX_SCHEME_SHIFT                 (0U)
35849 /*! TX_SCHEME - TX scheme configuration
35850  *  0b000..Credit-based scheme
35851  *  0b001..Round-robin scheme
35852  *  0b010-0b111..Reserved
35853  */
35854 #define ENET_QOS_TX_SCHEME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)
35855 
35856 #define ENET_QOS_RX_FLUSH0_MASK                  (0x8U)
35857 #define ENET_QOS_RX_FLUSH0_SHIFT                 (3U)
35858 /*! RX_FLUSH0 - RX Flush Ring 0
35859  *  0b0..Disable
35860  *  0b1..Enable
35861  */
35862 #define ENET_QOS_RX_FLUSH0(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)
35863 
35864 #define ENET_QOS_RX_FLUSH1_MASK                  (0x10U)
35865 #define ENET_QOS_RX_FLUSH1_SHIFT                 (4U)
35866 /*! RX_FLUSH1 - RX Flush Ring 1
35867  *  0b0..Disable
35868  *  0b1..Enable
35869  */
35870 #define ENET_QOS_RX_FLUSH1(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)
35871 
35872 #define ENET_QOS_RX_FLUSH2_MASK                  (0x20U)
35873 #define ENET_QOS_RX_FLUSH2_SHIFT                 (5U)
35874 /*! RX_FLUSH2 - RX Flush Ring 2
35875  *  0b0..Disable
35876  *  0b1..Enable
35877  */
35878 #define ENET_QOS_RX_FLUSH2(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)
35879 /*! @} */
35880 
35881 /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
35882 /*! @{ */
35883 
35884 #define ENET_RMON_T_PACKETS_TXPKTS_MASK          (0xFFFFU)
35885 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         (0U)
35886 /*! TXPKTS - Packet count */
35887 #define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
35888 /*! @} */
35889 
35890 /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
35891 /*! @{ */
35892 
35893 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK           (0xFFFFU)
35894 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          (0U)
35895 /*! TXPKTS - Number of broadcast packets */
35896 #define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
35897 /*! @} */
35898 
35899 /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
35900 /*! @{ */
35901 
35902 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK           (0xFFFFU)
35903 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          (0U)
35904 /*! TXPKTS - Number of multicast packets */
35905 #define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
35906 /*! @} */
35907 
35908 /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
35909 /*! @{ */
35910 
35911 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        (0xFFFFU)
35912 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       (0U)
35913 /*! TXPKTS - Number of packets with CRC/align error */
35914 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
35915 /*! @} */
35916 
35917 /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
35918 /*! @{ */
35919 
35920 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        (0xFFFFU)
35921 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       (0U)
35922 /*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC */
35923 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
35924 /*! @} */
35925 
35926 /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
35927 /*! @{ */
35928 
35929 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         (0xFFFFU)
35930 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        (0U)
35931 /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC */
35932 #define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
35933 /*! @} */
35934 
35935 /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
35936 /*! @{ */
35937 
35938 #define ENET_RMON_T_FRAG_TXPKTS_MASK             (0xFFFFU)
35939 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT            (0U)
35940 /*! TXPKTS - Number of packets less than 64 bytes with bad CRC */
35941 #define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
35942 /*! @} */
35943 
35944 /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
35945 /*! @{ */
35946 
35947 #define ENET_RMON_T_JAB_TXPKTS_MASK              (0xFFFFU)
35948 #define ENET_RMON_T_JAB_TXPKTS_SHIFT             (0U)
35949 /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC */
35950 #define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
35951 /*! @} */
35952 
35953 /*! @name RMON_T_COL - Tx Collision Count Statistic Register */
35954 /*! @{ */
35955 
35956 #define ENET_RMON_T_COL_TXPKTS_MASK              (0xFFFFU)
35957 #define ENET_RMON_T_COL_TXPKTS_SHIFT             (0U)
35958 /*! TXPKTS - Number of transmit collisions */
35959 #define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
35960 /*! @} */
35961 
35962 /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
35963 /*! @{ */
35964 
35965 #define ENET_RMON_T_P64_TXPKTS_MASK              (0xFFFFU)
35966 #define ENET_RMON_T_P64_TXPKTS_SHIFT             (0U)
35967 /*! TXPKTS - Number of 64-byte transmit packets */
35968 #define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
35969 /*! @} */
35970 
35971 /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
35972 /*! @{ */
35973 
35974 #define ENET_RMON_T_P65TO127_TXPKTS_MASK         (0xFFFFU)
35975 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        (0U)
35976 /*! TXPKTS - Number of 65- to 127-byte transmit packets */
35977 #define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
35978 /*! @} */
35979 
35980 /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
35981 /*! @{ */
35982 
35983 #define ENET_RMON_T_P128TO255_TXPKTS_MASK        (0xFFFFU)
35984 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       (0U)
35985 /*! TXPKTS - Number of 128- to 255-byte transmit packets */
35986 #define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
35987 /*! @} */
35988 
35989 /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
35990 /*! @{ */
35991 
35992 #define ENET_RMON_T_P256TO511_TXPKTS_MASK        (0xFFFFU)
35993 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       (0U)
35994 /*! TXPKTS - Number of 256- to 511-byte transmit packets */
35995 #define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
35996 /*! @} */
35997 
35998 /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
35999 /*! @{ */
36000 
36001 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK       (0xFFFFU)
36002 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      (0U)
36003 /*! TXPKTS - Number of 512- to 1023-byte transmit packets */
36004 #define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
36005 /*! @} */
36006 
36007 /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
36008 /*! @{ */
36009 
36010 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      (0xFFFFU)
36011 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     (0U)
36012 /*! TXPKTS - Number of 1024- to 2047-byte transmit packets */
36013 #define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
36014 /*! @} */
36015 
36016 /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
36017 /*! @{ */
36018 
36019 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        (0xFFFFU)
36020 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       (0U)
36021 /*! TXPKTS - Number of transmit packets greater than 2048 bytes */
36022 #define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
36023 /*! @} */
36024 
36025 /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
36026 /*! @{ */
36027 
36028 #define ENET_RMON_T_OCTETS_TXOCTS_MASK           (0xFFFFFFFFU)
36029 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          (0U)
36030 /*! TXOCTS - Number of transmit octets */
36031 #define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
36032 /*! @} */
36033 
36034 /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
36035 /*! @{ */
36036 
36037 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK          (0xFFFFU)
36038 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         (0U)
36039 /*! COUNT - Number of frames transmitted OK */
36040 #define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
36041 /*! @} */
36042 
36043 /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
36044 /*! @{ */
36045 
36046 #define ENET_IEEE_T_1COL_COUNT_MASK              (0xFFFFU)
36047 #define ENET_IEEE_T_1COL_COUNT_SHIFT             (0U)
36048 /*! COUNT - Number of frames transmitted with one collision */
36049 #define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
36050 /*! @} */
36051 
36052 /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
36053 /*! @{ */
36054 
36055 #define ENET_IEEE_T_MCOL_COUNT_MASK              (0xFFFFU)
36056 #define ENET_IEEE_T_MCOL_COUNT_SHIFT             (0U)
36057 /*! COUNT - Number of frames transmitted with multiple collisions */
36058 #define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
36059 /*! @} */
36060 
36061 /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
36062 /*! @{ */
36063 
36064 #define ENET_IEEE_T_DEF_COUNT_MASK               (0xFFFFU)
36065 #define ENET_IEEE_T_DEF_COUNT_SHIFT              (0U)
36066 /*! COUNT - Number of frames transmitted with deferral delay */
36067 #define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
36068 /*! @} */
36069 
36070 /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
36071 /*! @{ */
36072 
36073 #define ENET_IEEE_T_LCOL_COUNT_MASK              (0xFFFFU)
36074 #define ENET_IEEE_T_LCOL_COUNT_SHIFT             (0U)
36075 /*! COUNT - Number of frames transmitted with late collision */
36076 #define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
36077 /*! @} */
36078 
36079 /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
36080 /*! @{ */
36081 
36082 #define ENET_IEEE_T_EXCOL_COUNT_MASK             (0xFFFFU)
36083 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT            (0U)
36084 /*! COUNT - Number of frames transmitted with excessive collisions */
36085 #define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
36086 /*! @} */
36087 
36088 /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
36089 /*! @{ */
36090 
36091 #define ENET_IEEE_T_MACERR_COUNT_MASK            (0xFFFFU)
36092 #define ENET_IEEE_T_MACERR_COUNT_SHIFT           (0U)
36093 /*! COUNT - Number of frames transmitted with transmit FIFO underrun */
36094 #define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
36095 /*! @} */
36096 
36097 /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
36098 /*! @{ */
36099 
36100 #define ENET_IEEE_T_CSERR_COUNT_MASK             (0xFFFFU)
36101 #define ENET_IEEE_T_CSERR_COUNT_SHIFT            (0U)
36102 /*! COUNT - Number of frames transmitted with carrier sense error */
36103 #define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
36104 /*! @} */
36105 
36106 /*! @name IEEE_T_SQE - Reserved Statistic Register */
36107 /*! @{ */
36108 
36109 #define ENET_IEEE_T_SQE_COUNT_MASK               (0xFFFFU)
36110 #define ENET_IEEE_T_SQE_COUNT_SHIFT              (0U)
36111 /*! COUNT - This read-only field is reserved and always has the value 0 */
36112 #define ENET_IEEE_T_SQE_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
36113 /*! @} */
36114 
36115 /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
36116 /*! @{ */
36117 
36118 #define ENET_IEEE_T_FDXFC_COUNT_MASK             (0xFFFFU)
36119 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT            (0U)
36120 /*! COUNT - Number of flow-control pause frames transmitted */
36121 #define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
36122 /*! @} */
36123 
36124 /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
36125 /*! @{ */
36126 
36127 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
36128 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        (0U)
36129 /*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). */
36130 #define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
36131 /*! @} */
36132 
36133 /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
36134 /*! @{ */
36135 
36136 #define ENET_RMON_R_PACKETS_COUNT_MASK           (0xFFFFU)
36137 #define ENET_RMON_R_PACKETS_COUNT_SHIFT          (0U)
36138 /*! COUNT - Number of packets received */
36139 #define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
36140 /*! @} */
36141 
36142 /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
36143 /*! @{ */
36144 
36145 #define ENET_RMON_R_BC_PKT_COUNT_MASK            (0xFFFFU)
36146 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT           (0U)
36147 /*! COUNT - Number of receive broadcast packets */
36148 #define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
36149 /*! @} */
36150 
36151 /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
36152 /*! @{ */
36153 
36154 #define ENET_RMON_R_MC_PKT_COUNT_MASK            (0xFFFFU)
36155 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT           (0U)
36156 /*! COUNT - Number of receive multicast packets */
36157 #define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
36158 /*! @} */
36159 
36160 /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
36161 /*! @{ */
36162 
36163 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         (0xFFFFU)
36164 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        (0U)
36165 /*! COUNT - Number of receive packets with CRC or align error */
36166 #define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
36167 /*! @} */
36168 
36169 /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
36170 /*! @{ */
36171 
36172 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK         (0xFFFFU)
36173 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        (0U)
36174 /*! COUNT - Number of receive packets with less than 64 bytes and good CRC */
36175 #define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
36176 /*! @} */
36177 
36178 /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
36179 /*! @{ */
36180 
36181 #define ENET_RMON_R_OVERSIZE_COUNT_MASK          (0xFFFFU)
36182 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         (0U)
36183 /*! COUNT - Number of receive packets greater than MAX_FL and good CRC */
36184 #define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
36185 /*! @} */
36186 
36187 /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
36188 /*! @{ */
36189 
36190 #define ENET_RMON_R_FRAG_COUNT_MASK              (0xFFFFU)
36191 #define ENET_RMON_R_FRAG_COUNT_SHIFT             (0U)
36192 /*! COUNT - Number of receive packets with less than 64 bytes and bad CRC */
36193 #define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
36194 /*! @} */
36195 
36196 /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
36197 /*! @{ */
36198 
36199 #define ENET_RMON_R_JAB_COUNT_MASK               (0xFFFFU)
36200 #define ENET_RMON_R_JAB_COUNT_SHIFT              (0U)
36201 /*! COUNT - Number of receive packets greater than MAX_FL and bad CRC */
36202 #define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
36203 /*! @} */
36204 
36205 /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
36206 /*! @{ */
36207 
36208 #define ENET_RMON_R_P64_COUNT_MASK               (0xFFFFU)
36209 #define ENET_RMON_R_P64_COUNT_SHIFT              (0U)
36210 /*! COUNT - Number of 64-byte receive packets */
36211 #define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
36212 /*! @} */
36213 
36214 /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
36215 /*! @{ */
36216 
36217 #define ENET_RMON_R_P65TO127_COUNT_MASK          (0xFFFFU)
36218 #define ENET_RMON_R_P65TO127_COUNT_SHIFT         (0U)
36219 /*! COUNT - Number of 65- to 127-byte receive packets */
36220 #define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
36221 /*! @} */
36222 
36223 /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
36224 /*! @{ */
36225 
36226 #define ENET_RMON_R_P128TO255_COUNT_MASK         (0xFFFFU)
36227 #define ENET_RMON_R_P128TO255_COUNT_SHIFT        (0U)
36228 /*! COUNT - Number of 128- to 255-byte receive packets */
36229 #define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
36230 /*! @} */
36231 
36232 /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
36233 /*! @{ */
36234 
36235 #define ENET_RMON_R_P256TO511_COUNT_MASK         (0xFFFFU)
36236 #define ENET_RMON_R_P256TO511_COUNT_SHIFT        (0U)
36237 /*! COUNT - Number of 256- to 511-byte receive packets */
36238 #define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
36239 /*! @} */
36240 
36241 /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
36242 /*! @{ */
36243 
36244 #define ENET_RMON_R_P512TO1023_COUNT_MASK        (0xFFFFU)
36245 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT       (0U)
36246 /*! COUNT - Number of 512- to 1023-byte receive packets */
36247 #define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
36248 /*! @} */
36249 
36250 /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
36251 /*! @{ */
36252 
36253 #define ENET_RMON_R_P1024TO2047_COUNT_MASK       (0xFFFFU)
36254 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      (0U)
36255 /*! COUNT - Number of 1024- to 2047-byte receive packets */
36256 #define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
36257 /*! @} */
36258 
36259 /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
36260 /*! @{ */
36261 
36262 #define ENET_RMON_R_P_GTE2048_COUNT_MASK         (0xFFFFU)
36263 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        (0U)
36264 /*! COUNT - Number of greater-than-2048-byte receive packets */
36265 #define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
36266 /*! @} */
36267 
36268 /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
36269 /*! @{ */
36270 
36271 #define ENET_RMON_R_OCTETS_COUNT_MASK            (0xFFFFFFFFU)
36272 #define ENET_RMON_R_OCTETS_COUNT_SHIFT           (0U)
36273 /*! COUNT - Number of receive octets */
36274 #define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
36275 /*! @} */
36276 
36277 /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
36278 /*! @{ */
36279 
36280 #define ENET_IEEE_R_DROP_COUNT_MASK              (0xFFFFU)
36281 #define ENET_IEEE_R_DROP_COUNT_SHIFT             (0U)
36282 /*! COUNT - Frame count */
36283 #define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
36284 /*! @} */
36285 
36286 /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
36287 /*! @{ */
36288 
36289 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK          (0xFFFFU)
36290 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         (0U)
36291 /*! COUNT - Number of frames received OK */
36292 #define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
36293 /*! @} */
36294 
36295 /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
36296 /*! @{ */
36297 
36298 #define ENET_IEEE_R_CRC_COUNT_MASK               (0xFFFFU)
36299 #define ENET_IEEE_R_CRC_COUNT_SHIFT              (0U)
36300 /*! COUNT - Number of frames received with CRC error */
36301 #define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
36302 /*! @} */
36303 
36304 /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
36305 /*! @{ */
36306 
36307 #define ENET_IEEE_R_ALIGN_COUNT_MASK             (0xFFFFU)
36308 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT            (0U)
36309 /*! COUNT - Number of frames received with alignment error */
36310 #define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
36311 /*! @} */
36312 
36313 /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
36314 /*! @{ */
36315 
36316 #define ENET_IEEE_R_MACERR_COUNT_MASK            (0xFFFFU)
36317 #define ENET_IEEE_R_MACERR_COUNT_SHIFT           (0U)
36318 /*! COUNT - Receive FIFO overflow count */
36319 #define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
36320 /*! @} */
36321 
36322 /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
36323 /*! @{ */
36324 
36325 #define ENET_IEEE_R_FDXFC_COUNT_MASK             (0xFFFFU)
36326 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT            (0U)
36327 /*! COUNT - Number of flow-control pause frames received */
36328 #define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
36329 /*! @} */
36330 
36331 /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
36332 /*! @{ */
36333 
36334 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
36335 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        (0U)
36336 /*! COUNT - Number of octets for frames received without error */
36337 #define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
36338 /*! @} */
36339 
36340 /*! @name ATCR - Adjustable Timer Control Register */
36341 /*! @{ */
36342 
36343 #define ENET_ATCR_EN_MASK                        (0x1U)
36344 #define ENET_ATCR_EN_SHIFT                       (0U)
36345 /*! EN - Enable Timer
36346  *  0b0..The timer stops at the current value.
36347  *  0b1..The timer starts incrementing.
36348  */
36349 #define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
36350 
36351 #define ENET_ATCR_OFFEN_MASK                     (0x4U)
36352 #define ENET_ATCR_OFFEN_SHIFT                    (2U)
36353 /*! OFFEN - Enable One-Shot Offset Event
36354  *  0b0..Disable.
36355  *  0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
36356  *       when the offset event is reached, so no further event occurs until the field is set again. The timer
36357  *       offset value must be set before setting this field.
36358  */
36359 #define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
36360 
36361 #define ENET_ATCR_OFFRST_MASK                    (0x8U)
36362 #define ENET_ATCR_OFFRST_SHIFT                   (3U)
36363 /*! OFFRST - Reset Timer On Offset Event
36364  *  0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
36365  *  0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
36366  */
36367 #define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
36368 
36369 #define ENET_ATCR_PEREN_MASK                     (0x10U)
36370 #define ENET_ATCR_PEREN_SHIFT                    (4U)
36371 /*! PEREN - Enable Periodical Event
36372  *  0b0..Disable.
36373  *  0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when
36374  *       the timer wraps around according to the periodic setting ATPER. The timer period value must be set before
36375  *       setting this bit. Not all devices contain the event signal output. See the chip configuration details.
36376  */
36377 #define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
36378 
36379 #define ENET_ATCR_PINPER_MASK                    (0x80U)
36380 #define ENET_ATCR_PINPER_SHIFT                   (7U)
36381 /*! PINPER - Enables event signal output external pin frc_evt_period assertion on period event
36382  *  0b0..Disable.
36383  *  0b1..Enable.
36384  */
36385 #define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
36386 
36387 #define ENET_ATCR_RESTART_MASK                   (0x200U)
36388 #define ENET_ATCR_RESTART_SHIFT                  (9U)
36389 /*! RESTART - Reset Timer */
36390 #define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
36391 
36392 #define ENET_ATCR_CAPTURE_MASK                   (0x800U)
36393 #define ENET_ATCR_CAPTURE_SHIFT                  (11U)
36394 /*! CAPTURE - Capture Timer Value
36395  *  0b0..No effect.
36396  *  0b1..The current time is captured and can be read from the ATVR register.
36397  */
36398 #define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
36399 
36400 #define ENET_ATCR_SLAVE_MASK                     (0x2000U)
36401 #define ENET_ATCR_SLAVE_SHIFT                    (13U)
36402 /*! SLAVE - Enable Timer Slave Mode
36403  *  0b0..The timer is active and all configuration fields in this register are relevant.
36404  *  0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except
36405  *       CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
36406  */
36407 #define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
36408 /*! @} */
36409 
36410 /*! @name ATVR - Timer Value Register */
36411 /*! @{ */
36412 
36413 #define ENET_ATVR_ATIME_MASK                     (0xFFFFFFFFU)
36414 #define ENET_ATVR_ATIME_SHIFT                    (0U)
36415 #define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
36416 /*! @} */
36417 
36418 /*! @name ATOFF - Timer Offset Register */
36419 /*! @{ */
36420 
36421 #define ENET_ATOFF_OFFSET_MASK                   (0xFFFFFFFFU)
36422 #define ENET_ATOFF_OFFSET_SHIFT                  (0U)
36423 #define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
36424 /*! @} */
36425 
36426 /*! @name ATPER - Timer Period Register */
36427 /*! @{ */
36428 
36429 #define ENET_ATPER_PERIOD_MASK                   (0xFFFFFFFFU)
36430 #define ENET_ATPER_PERIOD_SHIFT                  (0U)
36431 /*! PERIOD - Value for generating periodic events */
36432 #define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
36433 /*! @} */
36434 
36435 /*! @name ATCOR - Timer Correction Register */
36436 /*! @{ */
36437 
36438 #define ENET_ATCOR_COR_MASK                      (0x7FFFFFFFU)
36439 #define ENET_ATCOR_COR_SHIFT                     (0U)
36440 /*! COR - Correction Counter Wrap-Around Value */
36441 #define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
36442 /*! @} */
36443 
36444 /*! @name ATINC - Time-Stamping Clock Period Register */
36445 /*! @{ */
36446 
36447 #define ENET_ATINC_INC_MASK                      (0x7FU)
36448 #define ENET_ATINC_INC_SHIFT                     (0U)
36449 /*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds */
36450 #define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
36451 
36452 #define ENET_ATINC_INC_CORR_MASK                 (0x7F00U)
36453 #define ENET_ATINC_INC_CORR_SHIFT                (8U)
36454 /*! INC_CORR - Correction Increment Value */
36455 #define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
36456 /*! @} */
36457 
36458 /*! @name ATSTMP - Timestamp of Last Transmitted Frame */
36459 /*! @{ */
36460 
36461 #define ENET_ATSTMP_TIMESTAMP_MASK               (0xFFFFFFFFU)
36462 #define ENET_ATSTMP_TIMESTAMP_SHIFT              (0U)
36463 /*! TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the
36464  *    ff_tx_ts_frm signal asserted from the user application
36465  */
36466 #define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
36467 /*! @} */
36468 
36469 /*! @name TGSR - Timer Global Status Register */
36470 /*! @{ */
36471 
36472 #define ENET_TGSR_TF0_MASK                       (0x1U)
36473 #define ENET_TGSR_TF0_SHIFT                      (0U)
36474 /*! TF0 - Copy Of Timer Flag For Channel 0
36475  *  0b0..Timer Flag for Channel 0 is clear
36476  *  0b1..Timer Flag for Channel 0 is set
36477  */
36478 #define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
36479 
36480 #define ENET_TGSR_TF1_MASK                       (0x2U)
36481 #define ENET_TGSR_TF1_SHIFT                      (1U)
36482 /*! TF1 - Copy Of Timer Flag For Channel 1
36483  *  0b0..Timer Flag for Channel 1 is clear
36484  *  0b1..Timer Flag for Channel 1 is set
36485  */
36486 #define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
36487 
36488 #define ENET_TGSR_TF2_MASK                       (0x4U)
36489 #define ENET_TGSR_TF2_SHIFT                      (2U)
36490 /*! TF2 - Copy Of Timer Flag For Channel 2
36491  *  0b0..Timer Flag for Channel 2 is clear
36492  *  0b1..Timer Flag for Channel 2 is set
36493  */
36494 #define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
36495 
36496 #define ENET_TGSR_TF3_MASK                       (0x8U)
36497 #define ENET_TGSR_TF3_SHIFT                      (3U)
36498 /*! TF3 - Copy Of Timer Flag For Channel 3
36499  *  0b0..Timer Flag for Channel 3 is clear
36500  *  0b1..Timer Flag for Channel 3 is set
36501  */
36502 #define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
36503 /*! @} */
36504 
36505 /*! @name TCSR - Timer Control Status Register */
36506 /*! @{ */
36507 
36508 #define ENET_TCSR_TDRE_MASK                      (0x1U)
36509 #define ENET_TCSR_TDRE_SHIFT                     (0U)
36510 /*! TDRE - Timer DMA Request Enable
36511  *  0b0..DMA request is disabled
36512  *  0b1..DMA request is enabled
36513  */
36514 #define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
36515 
36516 #define ENET_TCSR_TMODE_MASK                     (0x3CU)
36517 #define ENET_TCSR_TMODE_SHIFT                    (2U)
36518 /*! TMODE - Timer Mode
36519  *  0b0000..Timer Channel is disabled.
36520  *  0b0001..Timer Channel is configured for Input Capture on rising edge.
36521  *  0b0010..Timer Channel is configured for Input Capture on falling edge.
36522  *  0b0011..Timer Channel is configured for Input Capture on both edges.
36523  *  0b0100..Timer Channel is configured for Output Compare - software only.
36524  *  0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
36525  *  0b0110..Timer Channel is configured for Output Compare - clear output on compare.
36526  *  0b0111..Timer Channel is configured for Output Compare - set output on compare.
36527  *  0b1000..Reserved
36528  *  0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
36529  *  0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
36530  *  0b110x..Reserved
36531  *  0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
36532  *  0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
36533  */
36534 #define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
36535 
36536 #define ENET_TCSR_TIE_MASK                       (0x40U)
36537 #define ENET_TCSR_TIE_SHIFT                      (6U)
36538 /*! TIE - Timer Interrupt Enable
36539  *  0b0..Interrupt is disabled
36540  *  0b1..Interrupt is enabled
36541  */
36542 #define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
36543 
36544 #define ENET_TCSR_TF_MASK                        (0x80U)
36545 #define ENET_TCSR_TF_SHIFT                       (7U)
36546 /*! TF - Timer Flag
36547  *  0b0..Input Capture or Output Compare has not occurred.
36548  *  0b1..Input Capture or Output Compare has occurred.
36549  */
36550 #define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
36551 
36552 #define ENET_TCSR_TPWC_MASK                      (0xF800U)
36553 #define ENET_TCSR_TPWC_SHIFT                     (11U)
36554 /*! TPWC - Timer Pulse Width Control
36555  *  0b00000..Pulse width is one 1588-clock cycle.
36556  *  0b00001..Pulse width is two 1588-clock cycles.
36557  *  0b00010..Pulse width is three 1588-clock cycles.
36558  *  0b00011..Pulse width is four 1588-clock cycles.
36559  *  0b11111..Pulse width is 32 1588-clock cycles.
36560  */
36561 #define ENET_TCSR_TPWC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
36562 /*! @} */
36563 
36564 /* The count of ENET_TCSR */
36565 #define ENET_TCSR_COUNT                          (4U)
36566 
36567 /*! @name TCCR - Timer Compare Capture Register */
36568 /*! @{ */
36569 
36570 #define ENET_TCCR_TCC_MASK                       (0xFFFFFFFFU)
36571 #define ENET_TCCR_TCC_SHIFT                      (0U)
36572 /*! TCC - Timer Capture Compare */
36573 #define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
36574 /*! @} */
36575 
36576 /* The count of ENET_TCCR */
36577 #define ENET_TCCR_COUNT                          (4U)
36578 
36579 
36580 /*!
36581  * @}
36582  */ /* end of group ENET_Register_Masks */
36583 
36584 
36585 /* ENET - Peripheral instance base addresses */
36586 /** Peripheral ENET base address */
36587 #define ENET_BASE                                (0x40424000u)
36588 /** Peripheral ENET base pointer */
36589 #define ENET                                     ((ENET_Type *)ENET_BASE)
36590 /** Peripheral ENET_1G base address */
36591 #define ENET_1G_BASE                             (0x40420000u)
36592 /** Peripheral ENET_1G base pointer */
36593 #define ENET_1G                                  ((ENET_Type *)ENET_1G_BASE)
36594 /** Array initializer of ENET peripheral base addresses */
36595 #define ENET_BASE_ADDRS                          { ENET_BASE, ENET_1G_BASE }
36596 /** Array initializer of ENET peripheral base pointers */
36597 #define ENET_BASE_PTRS                           { ENET, ENET_1G }
36598 /** Interrupt vectors for the ENET peripheral type */
36599 #define ENET_Transmit_IRQS                       { ENET_IRQn, ENET_1G_IRQn }
36600 #define ENET_Receive_IRQS                        { ENET_IRQn, ENET_1G_IRQn }
36601 #define ENET_Error_IRQS                          { ENET_IRQn, ENET_1G_IRQn }
36602 #define ENET_1588_Timer_IRQS                     { ENET_1588_Timer_IRQn, ENET_1G_1588_Timer_IRQn }
36603 #define ENET_Ts_IRQS                             { ENET_IRQn, ENET_1G_IRQn }
36604 /* ENET Buffer Descriptor and Buffer Address Alignment. */
36605 #define ENET_BUFF_ALIGNMENT                      (64U)
36606 
36607 
36608 /*!
36609  * @}
36610  */ /* end of group ENET_Peripheral_Access_Layer */
36611 
36612 
36613 /* ----------------------------------------------------------------------------
36614    -- ENET_QOS Peripheral Access Layer
36615    ---------------------------------------------------------------------------- */
36616 
36617 /*!
36618  * @addtogroup ENET_QOS_Peripheral_Access_Layer ENET_QOS Peripheral Access Layer
36619  * @{
36620  */
36621 
36622 /** ENET_QOS - Register Layout Typedef */
36623 typedef struct {
36624   __IO uint32_t MAC_CONFIGURATION;                 /**< MAC Configuration Register, offset: 0x0 */
36625   __IO uint32_t MAC_EXT_CONFIGURATION;             /**< MAC Extended Configuration Register, offset: 0x4 */
36626   __IO uint32_t MAC_PACKET_FILTER;                 /**< MAC Packet Filter, offset: 0x8 */
36627   __IO uint32_t MAC_WATCHDOG_TIMEOUT;              /**< Watchdog Timeout, offset: 0xC */
36628   __IO uint32_t MAC_HASH_TABLE_REG0;               /**< MAC Hash Table Register 0, offset: 0x10 */
36629   __IO uint32_t MAC_HASH_TABLE_REG1;               /**< MAC Hash Table Register 1, offset: 0x14 */
36630        uint8_t RESERVED_0[56];
36631   __IO uint32_t MAC_VLAN_TAG_CTRL;                 /**< MAC VLAN Tag Control, offset: 0x50 */
36632   __IO uint32_t MAC_VLAN_TAG_DATA;                 /**< MAC VLAN Tag Data, offset: 0x54 */
36633   __IO uint32_t MAC_VLAN_HASH_TABLE;               /**< MAC VLAN Hash Table, offset: 0x58 */
36634        uint8_t RESERVED_1[4];
36635   __IO uint32_t MAC_VLAN_INCL;                     /**< VLAN Tag Inclusion or Replacement, offset: 0x60 */
36636   __IO uint32_t MAC_INNER_VLAN_INCL;               /**< MAC Inner VLAN Tag Inclusion or Replacement, offset: 0x64 */
36637        uint8_t RESERVED_2[8];
36638   __IO uint32_t MAC_TX_FLOW_CTRL_Q[5];             /**< MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control, array offset: 0x70, array step: 0x4 */
36639        uint8_t RESERVED_3[12];
36640   __IO uint32_t MAC_RX_FLOW_CTRL;                  /**< MAC Rx Flow Control, offset: 0x90 */
36641   __IO uint32_t MAC_RXQ_CTRL4;                     /**< Receive Queue Control 4, offset: 0x94 */
36642   __IO uint32_t MAC_TXQ_PRTY_MAP0;                 /**< Transmit Queue Priority Mapping 0, offset: 0x98 */
36643   __IO uint32_t MAC_TXQ_PRTY_MAP1;                 /**< Transmit Queue Priority Mapping 1, offset: 0x9C */
36644   __IO uint32_t MAC_RXQ_CTRL[4];                   /**< Receive Queue Control 0..Receive Queue Control 3, array offset: 0xA0, array step: 0x4 */
36645   __I  uint32_t MAC_INTERRUPT_STATUS;              /**< Interrupt Status, offset: 0xB0 */
36646   __IO uint32_t MAC_INTERRUPT_ENABLE;              /**< Interrupt Enable, offset: 0xB4 */
36647   __I  uint32_t MAC_RX_TX_STATUS;                  /**< Receive Transmit Status, offset: 0xB8 */
36648        uint8_t RESERVED_4[4];
36649   __IO uint32_t MAC_PMT_CONTROL_STATUS;            /**< PMT Control and Status, offset: 0xC0 */
36650   __IO uint32_t MAC_RWK_PACKET_FILTER;             /**< Remote Wakeup Filter, offset: 0xC4 */
36651        uint8_t RESERVED_5[8];
36652   __IO uint32_t MAC_LPI_CONTROL_STATUS;            /**< LPI Control and Status, offset: 0xD0 */
36653   __IO uint32_t MAC_LPI_TIMERS_CONTROL;            /**< LPI Timers Control, offset: 0xD4 */
36654   __IO uint32_t MAC_LPI_ENTRY_TIMER;               /**< Tx LPI Entry Timer Control, offset: 0xD8 */
36655   __IO uint32_t MAC_ONEUS_TIC_COUNTER;             /**< One-microsecond Reference Timer, offset: 0xDC */
36656        uint8_t RESERVED_6[24];
36657   __IO uint32_t MAC_PHYIF_CONTROL_STATUS;          /**< PHY Interface Control and Status, offset: 0xF8 */
36658        uint8_t RESERVED_7[20];
36659   __I  uint32_t MAC_VERSION;                       /**< MAC Version, offset: 0x110 */
36660   __I  uint32_t MAC_DEBUG;                         /**< MAC Debug, offset: 0x114 */
36661        uint8_t RESERVED_8[4];
36662   __I  uint32_t MAC_HW_FEAT[4];                    /**< Optional Features or Functions 0..Optional Features or Functions 3, array offset: 0x11C, array step: 0x4 */
36663        uint8_t RESERVED_9[212];
36664   __IO uint32_t MAC_MDIO_ADDRESS;                  /**< MDIO Address, offset: 0x200 */
36665   __IO uint32_t MAC_MDIO_DATA;                     /**< MAC MDIO Data, offset: 0x204 */
36666        uint8_t RESERVED_10[40];
36667   __IO uint32_t MAC_CSR_SW_CTRL;                   /**< CSR Software Control, offset: 0x230 */
36668   __IO uint32_t MAC_FPE_CTRL_STS;                  /**< Frame Preemption Control, offset: 0x234 */
36669        uint8_t RESERVED_11[8];
36670   __I  uint32_t MAC_PRESN_TIME_NS;                 /**< 32-bit Binary Rollover Equivalent Time, offset: 0x240 */
36671   __IO uint32_t MAC_PRESN_TIME_UPDT;               /**< MAC 1722 Presentation Time, offset: 0x244 */
36672        uint8_t RESERVED_12[184];
36673   struct {                                         /* offset: 0x300, array step: 0x8 */
36674     __IO uint32_t HIGH;                              /**< MAC Address0 High..MAC Address63 High, array offset: 0x300, array step: 0x8 */
36675     __IO uint32_t LOW;                               /**< MAC Address0 Low..MAC Address63 Low, array offset: 0x304, array step: 0x8 */
36676   } MAC_ADDRESS[64];
36677        uint8_t RESERVED_13[512];
36678   __IO uint32_t MAC_MMC_CONTROL;                   /**< MMC Control, offset: 0x700 */
36679   __I  uint32_t MAC_MMC_RX_INTERRUPT;              /**< MMC Rx Interrupt, offset: 0x704 */
36680   __I  uint32_t MAC_MMC_TX_INTERRUPT;              /**< MMC Tx Interrupt, offset: 0x708 */
36681   __IO uint32_t MAC_MMC_RX_INTERRUPT_MASK;         /**< MMC Rx Interrupt Mask, offset: 0x70C */
36682   __IO uint32_t MAC_MMC_TX_INTERRUPT_MASK;         /**< MMC Tx Interrupt Mask, offset: 0x710 */
36683   __I  uint32_t MAC_TX_OCTET_COUNT_GOOD_BAD;       /**< Tx Octet Count Good and Bad, offset: 0x714 */
36684   __I  uint32_t MAC_TX_PACKET_COUNT_GOOD_BAD;      /**< Tx Packet Count Good and Bad, offset: 0x718 */
36685   __I  uint32_t MAC_TX_BROADCAST_PACKETS_GOOD;     /**< Tx Broadcast Packets Good, offset: 0x71C */
36686   __I  uint32_t MAC_TX_MULTICAST_PACKETS_GOOD;     /**< Tx Multicast Packets Good, offset: 0x720 */
36687   __I  uint32_t MAC_TX_64OCTETS_PACKETS_GOOD_BAD;  /**< Tx Good and Bad 64-Byte Packets, offset: 0x724 */
36688   __I  uint32_t MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 65 to 127-Byte Packets, offset: 0x728 */
36689   __I  uint32_t MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 128 to 255-Byte Packets, offset: 0x72C */
36690   __I  uint32_t MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 256 to 511-Byte Packets, offset: 0x730 */
36691   __I  uint32_t MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 512 to 1023-Byte Packets, offset: 0x734 */
36692   __I  uint32_t MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 1024 to Max-Byte Packets, offset: 0x738 */
36693   __I  uint32_t MAC_TX_UNICAST_PACKETS_GOOD_BAD;   /**< Good and Bad Unicast Packets Transmitted, offset: 0x73C */
36694   __I  uint32_t MAC_TX_MULTICAST_PACKETS_GOOD_BAD; /**< Good and Bad Multicast Packets Transmitted, offset: 0x740 */
36695   __I  uint32_t MAC_TX_BROADCAST_PACKETS_GOOD_BAD; /**< Good and Bad Broadcast Packets Transmitted, offset: 0x744 */
36696   __I  uint32_t MAC_TX_UNDERFLOW_ERROR_PACKETS;    /**< Tx Packets Aborted By Underflow Error, offset: 0x748 */
36697   __I  uint32_t MAC_TX_SINGLE_COLLISION_GOOD_PACKETS; /**< Single Collision Good Packets Transmitted, offset: 0x74C */
36698   __I  uint32_t MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS; /**< Multiple Collision Good Packets Transmitted, offset: 0x750 */
36699   __I  uint32_t MAC_TX_DEFERRED_PACKETS;           /**< Deferred Packets Transmitted, offset: 0x754 */
36700   __I  uint32_t MAC_TX_LATE_COLLISION_PACKETS;     /**< Late Collision Packets Transmitted, offset: 0x758 */
36701   __I  uint32_t MAC_TX_EXCESSIVE_COLLISION_PACKETS; /**< Excessive Collision Packets Transmitted, offset: 0x75C */
36702   __I  uint32_t MAC_TX_CARRIER_ERROR_PACKETS;      /**< Carrier Error Packets Transmitted, offset: 0x760 */
36703   __I  uint32_t MAC_TX_OCTET_COUNT_GOOD;           /**< Bytes Transmitted in Good Packets, offset: 0x764 */
36704   __I  uint32_t MAC_TX_PACKET_COUNT_GOOD;          /**< Good Packets Transmitted, offset: 0x768 */
36705   __I  uint32_t MAC_TX_EXCESSIVE_DEFERRAL_ERROR;   /**< Packets Aborted By Excessive Deferral Error, offset: 0x76C */
36706   __I  uint32_t MAC_TX_PAUSE_PACKETS;              /**< Pause Packets Transmitted, offset: 0x770 */
36707   __I  uint32_t MAC_TX_VLAN_PACKETS_GOOD;          /**< Good VLAN Packets Transmitted, offset: 0x774 */
36708   __I  uint32_t MAC_TX_OSIZE_PACKETS_GOOD;         /**< Good Oversize Packets Transmitted, offset: 0x778 */
36709        uint8_t RESERVED_14[4];
36710   __I  uint32_t MAC_RX_PACKETS_COUNT_GOOD_BAD;     /**< Good and Bad Packets Received, offset: 0x780 */
36711   __I  uint32_t MAC_RX_OCTET_COUNT_GOOD_BAD;       /**< Bytes in Good and Bad Packets Received, offset: 0x784 */
36712   __I  uint32_t MAC_RX_OCTET_COUNT_GOOD;           /**< Bytes in Good Packets Received, offset: 0x788 */
36713   __I  uint32_t MAC_RX_BROADCAST_PACKETS_GOOD;     /**< Good Broadcast Packets Received, offset: 0x78C */
36714   __I  uint32_t MAC_RX_MULTICAST_PACKETS_GOOD;     /**< Good Multicast Packets Received, offset: 0x790 */
36715   __I  uint32_t MAC_RX_CRC_ERROR_PACKETS;          /**< CRC Error Packets Received, offset: 0x794 */
36716   __I  uint32_t MAC_RX_ALIGNMENT_ERROR_PACKETS;    /**< Alignment Error Packets Received, offset: 0x798 */
36717   __I  uint32_t MAC_RX_RUNT_ERROR_PACKETS;         /**< Runt Error Packets Received, offset: 0x79C */
36718   __I  uint32_t MAC_RX_JABBER_ERROR_PACKETS;       /**< Jabber Error Packets Received, offset: 0x7A0 */
36719   __I  uint32_t MAC_RX_UNDERSIZE_PACKETS_GOOD;     /**< Good Undersize Packets Received, offset: 0x7A4 */
36720   __I  uint32_t MAC_RX_OVERSIZE_PACKETS_GOOD;      /**< Good Oversize Packets Received, offset: 0x7A8 */
36721   __I  uint32_t MAC_RX_64OCTETS_PACKETS_GOOD_BAD;  /**< Good and Bad 64-Byte Packets Received, offset: 0x7AC */
36722   __I  uint32_t MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 64-to-127 Byte Packets Received, offset: 0x7B0 */
36723   __I  uint32_t MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 128-to-255 Byte Packets Received, offset: 0x7B4 */
36724   __I  uint32_t MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 256-to-511 Byte Packets Received, offset: 0x7B8 */
36725   __I  uint32_t MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 512-to-1023 Byte Packets Received, offset: 0x7BC */
36726   __I  uint32_t MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 1024-to-Max Byte Packets Received, offset: 0x7C0 */
36727   __I  uint32_t MAC_RX_UNICAST_PACKETS_GOOD;       /**< Good Unicast Packets Received, offset: 0x7C4 */
36728   __I  uint32_t MAC_RX_LENGTH_ERROR_PACKETS;       /**< Length Error Packets Received, offset: 0x7C8 */
36729   __I  uint32_t MAC_RX_OUT_OF_RANGE_TYPE_PACKETS;  /**< Out-of-range Type Packets Received, offset: 0x7CC */
36730   __I  uint32_t MAC_RX_PAUSE_PACKETS;              /**< Pause Packets Received, offset: 0x7D0 */
36731   __I  uint32_t MAC_RX_FIFO_OVERFLOW_PACKETS;      /**< Missed Packets Due to FIFO Overflow, offset: 0x7D4 */
36732   __I  uint32_t MAC_RX_VLAN_PACKETS_GOOD_BAD;      /**< Good and Bad VLAN Packets Received, offset: 0x7D8 */
36733   __I  uint32_t MAC_RX_WATCHDOG_ERROR_PACKETS;     /**< Watchdog Error Packets Received, offset: 0x7DC */
36734   __I  uint32_t MAC_RX_RECEIVE_ERROR_PACKETS;      /**< Receive Error Packets Received, offset: 0x7E0 */
36735   __I  uint32_t MAC_RX_CONTROL_PACKETS_GOOD;       /**< Good Control Packets Received, offset: 0x7E4 */
36736        uint8_t RESERVED_15[4];
36737   __I  uint32_t MAC_TX_LPI_USEC_CNTR;              /**< Microseconds Tx LPI Asserted, offset: 0x7EC */
36738   __I  uint32_t MAC_TX_LPI_TRAN_CNTR;              /**< Number of Times Tx LPI Asserted, offset: 0x7F0 */
36739   __I  uint32_t MAC_RX_LPI_USEC_CNTR;              /**< Microseconds Rx LPI Sampled, offset: 0x7F4 */
36740   __I  uint32_t MAC_RX_LPI_TRAN_CNTR;              /**< Number of Times Rx LPI Entered, offset: 0x7F8 */
36741        uint8_t RESERVED_16[4];
36742   __IO uint32_t MAC_MMC_IPC_RX_INTERRUPT_MASK;     /**< MMC IPC Receive Interrupt Mask, offset: 0x800 */
36743        uint8_t RESERVED_17[4];
36744   __I  uint32_t MAC_MMC_IPC_RX_INTERRUPT;          /**< MMC IPC Receive Interrupt, offset: 0x808 */
36745        uint8_t RESERVED_18[4];
36746   __I  uint32_t MAC_RXIPV4_GOOD_PACKETS;           /**< Good IPv4 Datagrams Received, offset: 0x810 */
36747   __I  uint32_t MAC_RXIPV4_HEADER_ERROR_PACKETS;   /**< IPv4 Datagrams Received with Header Errors, offset: 0x814 */
36748   __I  uint32_t MAC_RXIPV4_NO_PAYLOAD_PACKETS;     /**< IPv4 Datagrams Received with No Payload, offset: 0x818 */
36749   __I  uint32_t MAC_RXIPV4_FRAGMENTED_PACKETS;     /**< IPv4 Datagrams Received with Fragmentation, offset: 0x81C */
36750   __I  uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS; /**< IPv4 Datagrams Received with UDP Checksum Disabled, offset: 0x820 */
36751   __I  uint32_t MAC_RXIPV6_GOOD_PACKETS;           /**< Good IPv6 Datagrams Received, offset: 0x824 */
36752   __I  uint32_t MAC_RXIPV6_HEADER_ERROR_PACKETS;   /**< IPv6 Datagrams Received with Header Errors, offset: 0x828 */
36753   __I  uint32_t MAC_RXIPV6_NO_PAYLOAD_PACKETS;     /**< IPv6 Datagrams Received with No Payload, offset: 0x82C */
36754   __I  uint32_t MAC_RXUDP_GOOD_PACKETS;            /**< IPv6 Datagrams Received with Good UDP, offset: 0x830 */
36755   __I  uint32_t MAC_RXUDP_ERROR_PACKETS;           /**< IPv6 Datagrams Received with UDP Checksum Error, offset: 0x834 */
36756   __I  uint32_t MAC_RXTCP_GOOD_PACKETS;            /**< IPv6 Datagrams Received with Good TCP Payload, offset: 0x838 */
36757   __I  uint32_t MAC_RXTCP_ERROR_PACKETS;           /**< IPv6 Datagrams Received with TCP Checksum Error, offset: 0x83C */
36758   __I  uint32_t MAC_RXICMP_GOOD_PACKETS;           /**< IPv6 Datagrams Received with Good ICMP Payload, offset: 0x840 */
36759   __I  uint32_t MAC_RXICMP_ERROR_PACKETS;          /**< IPv6 Datagrams Received with ICMP Checksum Error, offset: 0x844 */
36760        uint8_t RESERVED_19[8];
36761   __I  uint32_t MAC_RXIPV4_GOOD_OCTETS;            /**< Good Bytes Received in IPv4 Datagrams, offset: 0x850 */
36762   __I  uint32_t MAC_RXIPV4_HEADER_ERROR_OCTETS;    /**< Bytes Received in IPv4 Datagrams with Header Errors, offset: 0x854 */
36763   __I  uint32_t MAC_RXIPV4_NO_PAYLOAD_OCTETS;      /**< Bytes Received in IPv4 Datagrams with No Payload, offset: 0x858 */
36764   __I  uint32_t MAC_RXIPV4_FRAGMENTED_OCTETS;      /**< Bytes Received in Fragmented IPv4 Datagrams, offset: 0x85C */
36765   __I  uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS; /**< Bytes Received with UDP Checksum Disabled, offset: 0x860 */
36766   __I  uint32_t MAC_RXIPV6_GOOD_OCTETS;            /**< Bytes Received in Good IPv6 Datagrams, offset: 0x864 */
36767   __I  uint32_t MAC_RXIPV6_HEADER_ERROR_OCTETS;    /**< Bytes Received in IPv6 Datagrams with Data Errors, offset: 0x868 */
36768   __I  uint32_t MAC_RXIPV6_NO_PAYLOAD_OCTETS;      /**< Bytes Received in IPv6 Datagrams with No Payload, offset: 0x86C */
36769   __I  uint32_t MAC_RXUDP_GOOD_OCTETS;             /**< Bytes Received in Good UDP Segment, offset: 0x870 */
36770   __I  uint32_t MAC_RXUDP_ERROR_OCTETS;            /**< Bytes Received in UDP Segment with Checksum Errors, offset: 0x874 */
36771   __I  uint32_t MAC_RXTCP_GOOD_OCTETS;             /**< Bytes Received in Good TCP Segment, offset: 0x878 */
36772   __I  uint32_t MAC_RXTCP_ERROR_OCTETS;            /**< Bytes Received in TCP Segment with Checksum Errors, offset: 0x87C */
36773   __I  uint32_t MAC_RXICMP_GOOD_OCTETS;            /**< Bytes Received in Good ICMP Segment, offset: 0x880 */
36774   __I  uint32_t MAC_RXICMP_ERROR_OCTETS;           /**< Bytes Received in ICMP Segment with Checksum Errors, offset: 0x884 */
36775        uint8_t RESERVED_20[24];
36776   __I  uint32_t MAC_MMC_FPE_TX_INTERRUPT;          /**< MMC FPE Transmit Interrupt, offset: 0x8A0 */
36777   __IO uint32_t MAC_MMC_FPE_TX_INTERRUPT_MASK;     /**< MMC FPE Transmit Mask Interrupt, offset: 0x8A4 */
36778   __I  uint32_t MAC_MMC_TX_FPE_FRAGMENT_CNTR;      /**< MMC FPE Transmitted Fragment Counter, offset: 0x8A8 */
36779   __I  uint32_t MAC_MMC_TX_HOLD_REQ_CNTR;          /**< MMC FPE Transmitted Hold Request Counter, offset: 0x8AC */
36780        uint8_t RESERVED_21[16];
36781   __I  uint32_t MAC_MMC_FPE_RX_INTERRUPT;          /**< MMC FPE Receive Interrupt, offset: 0x8C0 */
36782   __IO uint32_t MAC_MMC_FPE_RX_INTERRUPT_MASK;     /**< MMC FPE Receive Interrupt Mask, offset: 0x8C4 */
36783   __I  uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR; /**< MMC Receive Packet Reassembly Error Counter, offset: 0x8C8 */
36784   __I  uint32_t MAC_MMC_RX_PACKET_SMD_ERR_CNTR;    /**< MMC Receive Packet SMD Error Counter, offset: 0x8CC */
36785   __I  uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR; /**< MMC Receive Packet Successful Reassembly Counter, offset: 0x8D0 */
36786   __I  uint32_t MAC_MMC_RX_FPE_FRAGMENT_CNTR;      /**< MMC FPE Received Fragment Counter, offset: 0x8D4 */
36787        uint8_t RESERVED_22[40];
36788   __IO uint32_t MAC_L3_L4_CONTROL0;                /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0x900 */
36789   __IO uint32_t MAC_LAYER4_ADDRESS0;               /**< Layer 4 Address 0, offset: 0x904 */
36790        uint8_t RESERVED_23[8];
36791   __IO uint32_t MAC_LAYER3_ADDR0_REG0;             /**< Layer 3 Address 0 Register 0, offset: 0x910 */
36792   __IO uint32_t MAC_LAYER3_ADDR1_REG0;             /**< Layer 3 Address 1 Register 0, offset: 0x914 */
36793   __IO uint32_t MAC_LAYER3_ADDR2_REG0;             /**< Layer 3 Address 2 Register 0, offset: 0x918 */
36794   __IO uint32_t MAC_LAYER3_ADDR3_REG0;             /**< Layer 3 Address 3 Register 0, offset: 0x91C */
36795        uint8_t RESERVED_24[16];
36796   __IO uint32_t MAC_L3_L4_CONTROL1;                /**< Layer 3 and Layer 4 Control of Filter 1, offset: 0x930 */
36797   __IO uint32_t MAC_LAYER4_ADDRESS1;               /**< Layer 4 Address 0, offset: 0x934 */
36798        uint8_t RESERVED_25[8];
36799   __IO uint32_t MAC_LAYER3_ADDR0_REG1;             /**< Layer 3 Address 0 Register 1, offset: 0x940 */
36800   __IO uint32_t MAC_LAYER3_ADDR1_REG1;             /**< Layer 3 Address 1 Register 1, offset: 0x944 */
36801   __IO uint32_t MAC_LAYER3_ADDR2_REG1;             /**< Layer 3 Address 2 Register 1, offset: 0x948 */
36802   __IO uint32_t MAC_LAYER3_ADDR3_REG1;             /**< Layer 3 Address 3 Register 1, offset: 0x94C */
36803        uint8_t RESERVED_26[16];
36804   __IO uint32_t MAC_L3_L4_CONTROL2;                /**< Layer 3 and Layer 4 Control of Filter 2, offset: 0x960 */
36805   __IO uint32_t MAC_LAYER4_ADDRESS2;               /**< Layer 4 Address 2, offset: 0x964 */
36806        uint8_t RESERVED_27[8];
36807   __IO uint32_t MAC_LAYER3_ADDR0_REG2;             /**< Layer 3 Address 0 Register 2, offset: 0x970 */
36808   __IO uint32_t MAC_LAYER3_ADDR1_REG2;             /**< Layer 3 Address 0 Register 2, offset: 0x974 */
36809   __IO uint32_t MAC_LAYER3_ADDR2_REG2;             /**< Layer 3 Address 2 Register 2, offset: 0x978 */
36810   __IO uint32_t MAC_LAYER3_ADDR3_REG2;             /**< Layer 3 Address 3 Register 2, offset: 0x97C */
36811        uint8_t RESERVED_28[16];
36812   __IO uint32_t MAC_L3_L4_CONTROL3;                /**< Layer 3 and Layer 4 Control of Filter 3, offset: 0x990 */
36813   __IO uint32_t MAC_LAYER4_ADDRESS3;               /**< Layer 4 Address 3, offset: 0x994 */
36814        uint8_t RESERVED_29[8];
36815   __IO uint32_t MAC_LAYER3_ADDR0_REG3;             /**< Layer 3 Address 0 Register 3, offset: 0x9A0 */
36816   __IO uint32_t MAC_LAYER3_ADDR1_REG3;             /**< Layer 3 Address 1 Register 3, offset: 0x9A4 */
36817   __IO uint32_t MAC_LAYER3_ADDR2_REG3;             /**< Layer 3 Address 2 Register 3, offset: 0x9A8 */
36818   __IO uint32_t MAC_LAYER3_ADDR3_REG3;             /**< Layer 3 Address 3 Register 3, offset: 0x9AC */
36819        uint8_t RESERVED_30[16];
36820   __IO uint32_t MAC_L3_L4_CONTROL4;                /**< Layer 3 and Layer 4 Control of Filter 4, offset: 0x9C0 */
36821   __IO uint32_t MAC_LAYER4_ADDRESS4;               /**< Layer 4 Address 4, offset: 0x9C4 */
36822        uint8_t RESERVED_31[8];
36823   __IO uint32_t MAC_LAYER3_ADDR0_REG4;             /**< Layer 3 Address 0 Register 4, offset: 0x9D0 */
36824   __IO uint32_t MAC_LAYER3_ADDR1_REG4;             /**< Layer 3 Address 1 Register 4, offset: 0x9D4 */
36825   __IO uint32_t MAC_LAYER3_ADDR2_REG4;             /**< Layer 3 Address 2 Register 4, offset: 0x9D8 */
36826   __IO uint32_t MAC_LAYER3_ADDR3_REG4;             /**< Layer 3 Address 3 Register 4, offset: 0x9DC */
36827        uint8_t RESERVED_32[16];
36828   __IO uint32_t MAC_L3_L4_CONTROL5;                /**< Layer 3 and Layer 4 Control of Filter 5, offset: 0x9F0 */
36829   __IO uint32_t MAC_LAYER4_ADDRESS5;               /**< Layer 4 Address 5, offset: 0x9F4 */
36830        uint8_t RESERVED_33[8];
36831   __IO uint32_t MAC_LAYER3_ADDR0_REG5;             /**< Layer 3 Address 0 Register 5, offset: 0xA00 */
36832   __IO uint32_t MAC_LAYER3_ADDR1_REG5;             /**< Layer 3 Address 1 Register 5, offset: 0xA04 */
36833   __IO uint32_t MAC_LAYER3_ADDR2_REG5;             /**< Layer 3 Address 2 Register 5, offset: 0xA08 */
36834   __IO uint32_t MAC_LAYER3_ADDR3_REG5;             /**< Layer 3 Address 3 Register 5, offset: 0xA0C */
36835        uint8_t RESERVED_34[16];
36836   __IO uint32_t MAC_L3_L4_CONTROL6;                /**< Layer 3 and Layer 4 Control of Filter 6, offset: 0xA20 */
36837   __IO uint32_t MAC_LAYER4_ADDRESS6;               /**< Layer 4 Address 6, offset: 0xA24 */
36838        uint8_t RESERVED_35[8];
36839   __IO uint32_t MAC_LAYER3_ADDR0_REG6;             /**< Layer 3 Address 0 Register 6, offset: 0xA30 */
36840   __IO uint32_t MAC_LAYER3_ADDR1_REG6;             /**< Layer 3 Address 1 Register 6, offset: 0xA34 */
36841   __IO uint32_t MAC_LAYER3_ADDR2_REG6;             /**< Layer 3 Address 2 Register 6, offset: 0xA38 */
36842   __IO uint32_t MAC_LAYER3_ADDR3_REG6;             /**< Layer 3 Address 3 Register 6, offset: 0xA3C */
36843        uint8_t RESERVED_36[16];
36844   __IO uint32_t MAC_L3_L4_CONTROL7;                /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0xA50 */
36845   __IO uint32_t MAC_LAYER4_ADDRESS7;               /**< Layer 4 Address 7, offset: 0xA54 */
36846        uint8_t RESERVED_37[8];
36847   __IO uint32_t MAC_LAYER3_ADDR0_REG7;             /**< Layer 3 Address 0 Register 7, offset: 0xA60 */
36848   __IO uint32_t MAC_LAYER3_ADDR1_REG7;             /**< Layer 3 Address 1 Register 7, offset: 0xA64 */
36849   __IO uint32_t MAC_LAYER3_ADDR2_REG7;             /**< Layer 3 Address 2 Register 7, offset: 0xA68 */
36850   __IO uint32_t MAC_LAYER3_ADDR3_REG7;             /**< Layer 3 Address 3 Register 7, offset: 0xA6C */
36851        uint8_t RESERVED_38[144];
36852   __IO uint32_t MAC_TIMESTAMP_CONTROL;             /**< Timestamp Control, offset: 0xB00 */
36853   __IO uint32_t MAC_SUB_SECOND_INCREMENT;          /**< Subsecond Increment, offset: 0xB04 */
36854   __I  uint32_t MAC_SYSTEM_TIME_SECONDS;           /**< System Time Seconds, offset: 0xB08 */
36855   __I  uint32_t MAC_SYSTEM_TIME_NANOSECONDS;       /**< System Time Nanoseconds, offset: 0xB0C */
36856   __IO uint32_t MAC_SYSTEM_TIME_SECONDS_UPDATE;    /**< System Time Seconds Update, offset: 0xB10 */
36857   __IO uint32_t MAC_SYSTEM_TIME_NANOSECONDS_UPDATE; /**< System Time Nanoseconds Update, offset: 0xB14 */
36858   __IO uint32_t MAC_TIMESTAMP_ADDEND;              /**< Timestamp Addend, offset: 0xB18 */
36859   __IO uint32_t MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS; /**< System Time - Higher Word Seconds, offset: 0xB1C */
36860   __I  uint32_t MAC_TIMESTAMP_STATUS;              /**< Timestamp Status, offset: 0xB20 */
36861        uint8_t RESERVED_39[12];
36862   __I  uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Transmit Timestamp Status Nanoseconds, offset: 0xB30 */
36863   __I  uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS;   /**< Transmit Timestamp Status Seconds, offset: 0xB34 */
36864        uint8_t RESERVED_40[8];
36865   __IO uint32_t MAC_AUXILIARY_CONTROL;             /**< Auxiliary Timestamp Control, offset: 0xB40 */
36866        uint8_t RESERVED_41[4];
36867   __I  uint32_t MAC_AUXILIARY_TIMESTAMP_NANOSECONDS; /**< Auxiliary Timestamp Nanoseconds, offset: 0xB48 */
36868   __I  uint32_t MAC_AUXILIARY_TIMESTAMP_SECONDS;   /**< Auxiliary Timestamp Seconds, offset: 0xB4C */
36869   __IO uint32_t MAC_TIMESTAMP_INGRESS_ASYM_CORR;   /**< Timestamp Ingress Asymmetry Correction, offset: 0xB50 */
36870   __IO uint32_t MAC_TIMESTAMP_EGRESS_ASYM_CORR;    /**< imestamp Egress Asymmetry Correction, offset: 0xB54 */
36871   __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp Ingress Correction Nanosecond, offset: 0xB58 */
36872   __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp Egress Correction Nanosecond, offset: 0xB5C */
36873   __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC; /**< Timestamp Ingress Correction Subnanosecond, offset: 0xB60 */
36874   __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC; /**< Timestamp Egress Correction Subnanosecond, offset: 0xB64 */
36875   __I  uint32_t MAC_TIMESTAMP_INGRESS_LATENCY;     /**< Timestamp Ingress Latency, offset: 0xB68 */
36876   __I  uint32_t MAC_TIMESTAMP_EGRESS_LATENCY;      /**< Timestamp Egress Latency, offset: 0xB6C */
36877   __IO uint32_t MAC_PPS_CONTROL;                   /**< PPS Control, offset: 0xB70 */
36878        uint8_t RESERVED_42[12];
36879   __IO uint32_t MAC_PPS0_TARGET_TIME_SECONDS;      /**< PPS0 Target Time Seconds, offset: 0xB80 */
36880   __IO uint32_t MAC_PPS0_TARGET_TIME_NANOSECONDS;  /**< PPS0 Target Time Nanoseconds, offset: 0xB84 */
36881   __IO uint32_t MAC_PPS0_INTERVAL;                 /**< PPS0 Interval, offset: 0xB88 */
36882   __IO uint32_t MAC_PPS0_WIDTH;                    /**< PPS0 Width, offset: 0xB8C */
36883   __IO uint32_t MAC_PPS1_TARGET_TIME_SECONDS;      /**< PPS1 Target Time Seconds, offset: 0xB90 */
36884   __IO uint32_t MAC_PPS1_TARGET_TIME_NANOSECONDS;  /**< PPS1 Target Time Nanoseconds, offset: 0xB94 */
36885   __IO uint32_t MAC_PPS1_INTERVAL;                 /**< PPS1 Interval, offset: 0xB98 */
36886   __IO uint32_t MAC_PPS1_WIDTH;                    /**< PPS1 Width, offset: 0xB9C */
36887   __IO uint32_t MAC_PPS2_TARGET_TIME_SECONDS;      /**< PPS2 Target Time Seconds, offset: 0xBA0 */
36888   __IO uint32_t MAC_PPS2_TARGET_TIME_NANOSECONDS;  /**< PPS2 Target Time Nanoseconds, offset: 0xBA4 */
36889   __IO uint32_t MAC_PPS2_INTERVAL;                 /**< PPS2 Interval, offset: 0xBA8 */
36890   __IO uint32_t MAC_PPS2_WIDTH;                    /**< PPS2 Width, offset: 0xBAC */
36891   __IO uint32_t MAC_PPS3_TARGET_TIME_SECONDS;      /**< PPS3 Target Time Seconds, offset: 0xBB0 */
36892   __IO uint32_t MAC_PPS3_TARGET_TIME_NANOSECONDS;  /**< PPS3 Target Time Nanoseconds, offset: 0xBB4 */
36893   __IO uint32_t MAC_PPS3_INTERVAL;                 /**< PPS3 Interval, offset: 0xBB8 */
36894   __IO uint32_t MAC_PPS3_WIDTH;                    /**< PPS3 Width, offset: 0xBBC */
36895   __IO uint32_t MAC_PTO_CONTROL;                   /**< PTP Offload Engine Control, offset: 0xBC0 */
36896   __IO uint32_t MAC_SOURCE_PORT_IDENTITY0;         /**< Source Port Identity 0, offset: 0xBC4 */
36897   __IO uint32_t MAC_SOURCE_PORT_IDENTITY1;         /**< Source Port Identity 1, offset: 0xBC8 */
36898   __IO uint32_t MAC_SOURCE_PORT_IDENTITY2;         /**< Source Port Identity 2, offset: 0xBCC */
36899   __IO uint32_t MAC_LOG_MESSAGE_INTERVAL;          /**< Log Message Interval, offset: 0xBD0 */
36900        uint8_t RESERVED_43[44];
36901   __IO uint32_t MTL_OPERATION_MODE;                /**< MTL Operation Mode, offset: 0xC00 */
36902        uint8_t RESERVED_44[4];
36903   __IO uint32_t MTL_DBG_CTL;                       /**< FIFO Debug Access Control and Status, offset: 0xC08 */
36904   __IO uint32_t MTL_DBG_STS;                       /**< FIFO Debug Status, offset: 0xC0C */
36905   __IO uint32_t MTL_FIFO_DEBUG_DATA;               /**< FIFO Debug Data, offset: 0xC10 */
36906        uint8_t RESERVED_45[12];
36907   __I  uint32_t MTL_INTERRUPT_STATUS;              /**< MTL Interrupt Status, offset: 0xC20 */
36908        uint8_t RESERVED_46[12];
36909   __IO uint32_t MTL_RXQ_DMA_MAP0;                  /**< Receive Queue and DMA Channel Mapping 0, offset: 0xC30 */
36910   __IO uint32_t MTL_RXQ_DMA_MAP1;                  /**< Receive Queue and DMA Channel Mapping 1, offset: 0xC34 */
36911        uint8_t RESERVED_47[8];
36912   __IO uint32_t MTL_TBS_CTRL;                      /**< Time Based Scheduling Control, offset: 0xC40 */
36913        uint8_t RESERVED_48[12];
36914   __IO uint32_t MTL_EST_CONTROL;                   /**< Enhancements to Scheduled Transmission Control, offset: 0xC50 */
36915        uint8_t RESERVED_49[4];
36916   __IO uint32_t MTL_EST_STATUS;                    /**< Enhancements to Scheduled Transmission Status, offset: 0xC58 */
36917        uint8_t RESERVED_50[4];
36918   __IO uint32_t MTL_EST_SCH_ERROR;                 /**< EST Scheduling Error, offset: 0xC60 */
36919   __IO uint32_t MTL_EST_FRM_SIZE_ERROR;            /**< EST Frame Size Error, offset: 0xC64 */
36920   __I  uint32_t MTL_EST_FRM_SIZE_CAPTURE;          /**< EST Frame Size Capture, offset: 0xC68 */
36921        uint8_t RESERVED_51[4];
36922   __IO uint32_t MTL_EST_INTR_ENABLE;               /**< EST Interrupt Enable, offset: 0xC70 */
36923        uint8_t RESERVED_52[12];
36924   __IO uint32_t MTL_EST_GCL_CONTROL;               /**< EST GCL Control, offset: 0xC80 */
36925   __IO uint32_t MTL_EST_GCL_DATA;                  /**< EST GCL Data, offset: 0xC84 */
36926        uint8_t RESERVED_53[8];
36927   __IO uint32_t MTL_FPE_CTRL_STS;                  /**< Frame Preemption Control and Status, offset: 0xC90 */
36928   __IO uint32_t MTL_FPE_ADVANCE;                   /**< Frame Preemption Hold and Release Advance, offset: 0xC94 */
36929        uint8_t RESERVED_54[8];
36930   __IO uint32_t MTL_RXP_CONTROL_STATUS;            /**< RXP Control Status, offset: 0xCA0 */
36931   __IO uint32_t MTL_RXP_INTERRUPT_CONTROL_STATUS;  /**< RXP Interrupt Control Status, offset: 0xCA4 */
36932   __I  uint32_t MTL_RXP_DROP_CNT;                  /**< RXP Drop Count, offset: 0xCA8 */
36933   __I  uint32_t MTL_RXP_ERROR_CNT;                 /**< RXP Error Count, offset: 0xCAC */
36934   __IO uint32_t MTL_RXP_INDIRECT_ACC_CONTROL_STATUS; /**< RXP Indirect Access Control and Status, offset: 0xCB0 */
36935   __IO uint32_t MTL_RXP_INDIRECT_ACC_DATA;         /**< RXP Indirect Access Data, offset: 0xCB4 */
36936        uint8_t RESERVED_55[72];
36937   struct {                                         /* offset: 0xD00, array step: 0x40 */
36938     __IO uint32_t MTL_TXQX_OP_MODE;                  /**< Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode, array offset: 0xD00, array step: 0x40 */
36939     __I  uint32_t MTL_TXQX_UNDRFLW;                  /**< Queue 0 Underflow Counter..Queue 4 Underflow Counter, array offset: 0xD04, array step: 0x40 */
36940     __I  uint32_t MTL_TXQX_DBG;                      /**< Queue 0 Transmit Debug..Queue 4 Transmit Debug, array offset: 0xD08, array step: 0x40 */
36941          uint8_t RESERVED_0[4];
36942     __IO uint32_t MTL_TXQX_ETS_CTRL;                 /**< Queue 1 ETS Control..Queue 4 ETS Control, array offset: 0xD10, array step: 0x40, valid indices: [1-4] */
36943     __I  uint32_t MTL_TXQX_ETS_STAT;                 /**< Queue 0 ETS Status..Queue 4 ETS Status, array offset: 0xD14, array step: 0x40 */
36944     __IO uint32_t MTL_TXQX_QNTM_WGHT;                /**< Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights, array offset: 0xD18, array step: 0x40 */
36945     __IO uint32_t MTL_TXQX_SNDSLP_CRDT;              /**< Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit, array offset: 0xD1C, array step: 0x40, valid indices: [1-4] */
36946     __IO uint32_t MTL_TXQX_HI_CRDT;                  /**< Queue 1 hiCredit..Queue 4 hiCredit, array offset: 0xD20, array step: 0x40, valid indices: [1-4] */
36947     __IO uint32_t MTL_TXQX_LO_CRDT;                  /**< Queue 1 loCredit..Queue 4 loCredit, array offset: 0xD24, array step: 0x40, valid indices: [1-4] */
36948          uint8_t RESERVED_1[4];
36949     __IO uint32_t MTL_TXQX_INTCTRL_STAT;             /**< Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status, array offset: 0xD2C, array step: 0x40 */
36950     __IO uint32_t MTL_RXQX_OP_MODE;                  /**< Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode, array offset: 0xD30, array step: 0x40 */
36951     __I  uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT;       /**< Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter, array offset: 0xD34, array step: 0x40 */
36952     __I  uint32_t MTL_RXQX_DBG;                      /**< Queue 0 Receive Debug..Queue 4 Receive Debug, array offset: 0xD38, array step: 0x40 */
36953     __IO uint32_t MTL_RXQX_CTRL;                     /**< Queue 0 Receive Control..Queue 4 Receive Control, array offset: 0xD3C, array step: 0x40 */
36954   } MTL_QUEUE[5];
36955        uint8_t RESERVED_56[448];
36956   __IO uint32_t DMA_MODE;                          /**< DMA Bus Mode, offset: 0x1000 */
36957   __IO uint32_t DMA_SYSBUS_MODE;                   /**< DMA System Bus Mode, offset: 0x1004 */
36958   __I  uint32_t DMA_INTERRUPT_STATUS;              /**< DMA Interrupt Status, offset: 0x1008 */
36959   __I  uint32_t DMA_DEBUG_STATUS0;                 /**< DMA Debug Status 0, offset: 0x100C */
36960   __I  uint32_t DMA_DEBUG_STATUS1;                 /**< DMA Debug Status 1, offset: 0x1010 */
36961        uint8_t RESERVED_57[44];
36962   __IO uint32_t DMA_AXI_LPI_ENTRY_INTERVAL;        /**< AXI LPI Entry Interval Control, offset: 0x1040 */
36963        uint8_t RESERVED_58[12];
36964   __IO uint32_t DMA_TBS_CTRL;                      /**< TBS Control, offset: 0x1050 */
36965        uint8_t RESERVED_59[172];
36966   struct {                                         /* offset: 0x1100, array step: 0x80 */
36967     __IO uint32_t DMA_CHX_CTRL;                      /**< DMA Channel 0 Control..DMA Channel 4 Control, array offset: 0x1100, array step: 0x80 */
36968     __IO uint32_t DMA_CHX_TX_CTRL;                   /**< DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control, array offset: 0x1104, array step: 0x80 */
36969     __IO uint32_t DMA_CHX_RX_CTRL;                   /**< DMA Channel 0 Receive Control..DMA Channel 4 Receive Control, array offset: 0x1108, array step: 0x80 */
36970          uint8_t RESERVED_0[8];
36971     __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR;          /**< Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address, array offset: 0x1114, array step: 0x80 */
36972          uint8_t RESERVED_1[4];
36973     __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR;          /**< Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address, array offset: 0x111C, array step: 0x80 */
36974     __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR;           /**< Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer, array offset: 0x1120, array step: 0x80 */
36975          uint8_t RESERVED_2[4];
36976     __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR;           /**< Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer, array offset: 0x1128, array step: 0x80 */
36977     __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH;        /**< Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length, array offset: 0x112C, array step: 0x80 */
36978     __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH;        /**< Channel 0 Rx Descriptor Ring Length..Channel 4 Rx Descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
36979     __IO uint32_t DMA_CHX_INT_EN;                    /**< Channel 0 Interrupt Enable..Channel 4 Interrupt Enable, array offset: 0x1134, array step: 0x80 */
36980     __IO uint32_t DMA_CHX_RX_INT_WDTIMER;            /**< Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
36981     __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT;       /**< Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
36982          uint8_t RESERVED_3[4];
36983     __I  uint32_t DMA_CHX_CUR_HST_TXDESC;            /**< Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor, array offset: 0x1144, array step: 0x80 */
36984          uint8_t RESERVED_4[4];
36985     __I  uint32_t DMA_CHX_CUR_HST_RXDESC;            /**< Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor, array offset: 0x114C, array step: 0x80 */
36986          uint8_t RESERVED_5[4];
36987     __I  uint32_t DMA_CHX_CUR_HST_TXBUF;             /**< Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address, array offset: 0x1154, array step: 0x80 */
36988          uint8_t RESERVED_6[4];
36989     __I  uint32_t DMA_CHX_CUR_HST_RXBUF;             /**< Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
36990     __IO uint32_t DMA_CHX_STAT;                      /**< DMA Channel 0 Status..DMA Channel 4 Status, array offset: 0x1160, array step: 0x80 */
36991     __I  uint32_t DMA_CHX_MISS_FRAME_CNT;            /**< Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter, array offset: 0x1164, array step: 0x80 */
36992     __I  uint32_t DMA_CHX_RXP_ACCEPT_CNT;            /**< Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter, array offset: 0x1168, array step: 0x80 */
36993     __I  uint32_t DMA_CHX_RX_ERI_CNT;                /**< Channel 0 Receive ERI Counter..Channel 4 Receive ERI Counter, array offset: 0x116C, array step: 0x80 */
36994          uint8_t RESERVED_7[16];
36995   } DMA_CH[5];
36996 } ENET_QOS_Type;
36997 
36998 /* ----------------------------------------------------------------------------
36999    -- ENET_QOS Register Masks
37000    ---------------------------------------------------------------------------- */
37001 
37002 /*!
37003  * @addtogroup ENET_QOS_Register_Masks ENET_QOS Register Masks
37004  * @{
37005  */
37006 
37007 /*! @name MAC_CONFIGURATION - MAC Configuration Register */
37008 /*! @{ */
37009 
37010 #define ENET_QOS_MAC_CONFIGURATION_RE_MASK       (0x1U)
37011 #define ENET_QOS_MAC_CONFIGURATION_RE_SHIFT      (0U)
37012 /*! RE - Receiver Enable
37013  *  0b0..Receiver is disabled
37014  *  0b1..Receiver is enabled
37015  */
37016 #define ENET_QOS_MAC_CONFIGURATION_RE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_RE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_RE_MASK)
37017 
37018 #define ENET_QOS_MAC_CONFIGURATION_TE_MASK       (0x2U)
37019 #define ENET_QOS_MAC_CONFIGURATION_TE_SHIFT      (1U)
37020 /*! TE - Transmitter Enable
37021  *  0b0..Transmitter is disabled
37022  *  0b1..Transmitter is enabled
37023  */
37024 #define ENET_QOS_MAC_CONFIGURATION_TE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_TE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_TE_MASK)
37025 
37026 #define ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK   (0xCU)
37027 #define ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT  (2U)
37028 /*! PRELEN - Preamble Length for Transmit packets
37029  *  0b10..3 bytes of preamble
37030  *  0b01..5 bytes of preamble
37031  *  0b00..7 bytes of preamble
37032  *  0b11..Reserved
37033  */
37034 #define ENET_QOS_MAC_CONFIGURATION_PRELEN(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK)
37035 
37036 #define ENET_QOS_MAC_CONFIGURATION_DC_MASK       (0x10U)
37037 #define ENET_QOS_MAC_CONFIGURATION_DC_SHIFT      (4U)
37038 /*! DC - Deferral Check
37039  *  0b0..Deferral check function is disabled
37040  *  0b1..Deferral check function is enabled
37041  */
37042 #define ENET_QOS_MAC_CONFIGURATION_DC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DC_MASK)
37043 
37044 #define ENET_QOS_MAC_CONFIGURATION_BL_MASK       (0x60U)
37045 #define ENET_QOS_MAC_CONFIGURATION_BL_SHIFT      (5U)
37046 /*! BL - Back-Off Limit
37047  *  0b11..k = min(n,1)
37048  *  0b00..k = min(n,10)
37049  *  0b10..k = min(n,4)
37050  *  0b01..k = min(n,8)
37051  */
37052 #define ENET_QOS_MAC_CONFIGURATION_BL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BL_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BL_MASK)
37053 
37054 #define ENET_QOS_MAC_CONFIGURATION_DR_MASK       (0x100U)
37055 #define ENET_QOS_MAC_CONFIGURATION_DR_SHIFT      (8U)
37056 /*! DR - Disable Retry
37057  *  0b1..Disable Retry
37058  *  0b0..Enable Retry
37059  */
37060 #define ENET_QOS_MAC_CONFIGURATION_DR(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DR_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DR_MASK)
37061 
37062 #define ENET_QOS_MAC_CONFIGURATION_DCRS_MASK     (0x200U)
37063 #define ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT    (9U)
37064 /*! DCRS - Disable Carrier Sense During Transmission
37065  *  0b1..Disable Carrier Sense During Transmission
37066  *  0b0..Enable Carrier Sense During Transmission
37067  */
37068 #define ENET_QOS_MAC_CONFIGURATION_DCRS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DCRS_MASK)
37069 
37070 #define ENET_QOS_MAC_CONFIGURATION_DO_MASK       (0x400U)
37071 #define ENET_QOS_MAC_CONFIGURATION_DO_SHIFT      (10U)
37072 /*! DO - Disable Receive Own
37073  *  0b1..Disable Receive Own
37074  *  0b0..Enable Receive Own
37075  */
37076 #define ENET_QOS_MAC_CONFIGURATION_DO(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DO_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DO_MASK)
37077 
37078 #define ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK   (0x800U)
37079 #define ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT  (11U)
37080 /*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode
37081  *  0b0..ECRSFD is disabled
37082  *  0b1..ECRSFD is enabled
37083  */
37084 #define ENET_QOS_MAC_CONFIGURATION_ECRSFD(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK)
37085 
37086 #define ENET_QOS_MAC_CONFIGURATION_LM_MASK       (0x1000U)
37087 #define ENET_QOS_MAC_CONFIGURATION_LM_SHIFT      (12U)
37088 /*! LM - Loopback Mode
37089  *  0b0..Loopback is disabled
37090  *  0b1..Loopback is enabled
37091  */
37092 #define ENET_QOS_MAC_CONFIGURATION_LM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_LM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_LM_MASK)
37093 
37094 #define ENET_QOS_MAC_CONFIGURATION_DM_MASK       (0x2000U)
37095 #define ENET_QOS_MAC_CONFIGURATION_DM_SHIFT      (13U)
37096 /*! DM - Duplex Mode
37097  *  0b1..Full-duplex mode
37098  *  0b0..Half-duplex mode
37099  */
37100 #define ENET_QOS_MAC_CONFIGURATION_DM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DM_MASK)
37101 
37102 #define ENET_QOS_MAC_CONFIGURATION_FES_MASK      (0x4000U)
37103 #define ENET_QOS_MAC_CONFIGURATION_FES_SHIFT     (14U)
37104 /*! FES - Speed
37105  *  0b1..100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0
37106  *  0b0..10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0
37107  */
37108 #define ENET_QOS_MAC_CONFIGURATION_FES(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_FES_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_FES_MASK)
37109 
37110 #define ENET_QOS_MAC_CONFIGURATION_PS_MASK       (0x8000U)
37111 #define ENET_QOS_MAC_CONFIGURATION_PS_SHIFT      (15U)
37112 /*! PS - Port Select
37113  *  0b0..For 1000 or 2500 Mbps operations
37114  *  0b1..For 10 or 100 Mbps operations
37115  */
37116 #define ENET_QOS_MAC_CONFIGURATION_PS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PS_MASK)
37117 
37118 #define ENET_QOS_MAC_CONFIGURATION_JE_MASK       (0x10000U)
37119 #define ENET_QOS_MAC_CONFIGURATION_JE_SHIFT      (16U)
37120 /*! JE - Jumbo Packet Enable When this bit is set, the MAC allows jumbo packets of 9,018 bytes
37121  *    (9,022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet
37122  *    status.
37123  *  0b0..Jumbo packet is disabled
37124  *  0b1..Jumbo packet is enabled
37125  */
37126 #define ENET_QOS_MAC_CONFIGURATION_JE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JE_MASK)
37127 
37128 #define ENET_QOS_MAC_CONFIGURATION_JD_MASK       (0x20000U)
37129 #define ENET_QOS_MAC_CONFIGURATION_JD_SHIFT      (17U)
37130 /*! JD - Jabber Disable
37131  *  0b1..Jabber is disabled
37132  *  0b0..Jabber is enabled
37133  */
37134 #define ENET_QOS_MAC_CONFIGURATION_JD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JD_MASK)
37135 
37136 #define ENET_QOS_MAC_CONFIGURATION_BE_MASK       (0x40000U)
37137 #define ENET_QOS_MAC_CONFIGURATION_BE_SHIFT      (18U)
37138 /*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during
37139  *    transmission in the GMII half-duplex mode.
37140  *  0b0..Packet Burst is disabled
37141  *  0b1..Packet Burst is enabled
37142  */
37143 #define ENET_QOS_MAC_CONFIGURATION_BE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BE_MASK)
37144 
37145 #define ENET_QOS_MAC_CONFIGURATION_WD_MASK       (0x80000U)
37146 #define ENET_QOS_MAC_CONFIGURATION_WD_SHIFT      (19U)
37147 /*! WD - Watchdog Disable
37148  *  0b1..Watchdog is disabled
37149  *  0b0..Watchdog is enabled
37150  */
37151 #define ENET_QOS_MAC_CONFIGURATION_WD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_WD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_WD_MASK)
37152 
37153 #define ENET_QOS_MAC_CONFIGURATION_ACS_MASK      (0x100000U)
37154 #define ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT     (20U)
37155 /*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field
37156  *    on the incoming packets only if the value of the length field is less than 1,536 bytes.
37157  *  0b0..Automatic Pad or CRC Stripping is disabled
37158  *  0b1..Automatic Pad or CRC Stripping is enabled
37159  */
37160 #define ENET_QOS_MAC_CONFIGURATION_ACS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ACS_MASK)
37161 
37162 #define ENET_QOS_MAC_CONFIGURATION_CST_MASK      (0x200000U)
37163 #define ENET_QOS_MAC_CONFIGURATION_CST_SHIFT     (21U)
37164 /*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all
37165  *    packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding
37166  *    the packet to the application.
37167  *  0b0..CRC stripping for Type packets is disabled
37168  *  0b1..CRC stripping for Type packets is enabled
37169  */
37170 #define ENET_QOS_MAC_CONFIGURATION_CST(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_CST_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_CST_MASK)
37171 
37172 #define ENET_QOS_MAC_CONFIGURATION_S2KP_MASK     (0x400000U)
37173 #define ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT    (22U)
37174 /*! S2KP - IEEE 802.
37175  *  0b0..Support upto 2K packet is disabled
37176  *  0b1..Support upto 2K packet is Enabled
37177  */
37178 #define ENET_QOS_MAC_CONFIGURATION_S2KP(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_S2KP_MASK)
37179 
37180 #define ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK   (0x800000U)
37181 #define ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT  (23U)
37182 /*! GPSLCE - Giant Packet Size Limit Control Enable
37183  *  0b0..Giant Packet Size Limit Control is disabled
37184  *  0b1..Giant Packet Size Limit Control is enabled
37185  */
37186 #define ENET_QOS_MAC_CONFIGURATION_GPSLCE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK)
37187 
37188 #define ENET_QOS_MAC_CONFIGURATION_IPG_MASK      (0x7000000U)
37189 #define ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT     (24U)
37190 /*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission.
37191  *  0b111..40 bit times IPG
37192  *  0b110..48 bit times IPG
37193  *  0b101..56 bit times IPG
37194  *  0b100..64 bit times IPG
37195  *  0b011..72 bit times IPG
37196  *  0b010..80 bit times IPG
37197  *  0b001..88 bit times IPG
37198  *  0b000..96 bit times IPG
37199  */
37200 #define ENET_QOS_MAC_CONFIGURATION_IPG(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPG_MASK)
37201 
37202 #define ENET_QOS_MAC_CONFIGURATION_IPC_MASK      (0x8000000U)
37203 #define ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT     (27U)
37204 /*! IPC - Checksum Offload
37205  *  0b0..IP header/payload checksum checking is disabled
37206  *  0b1..IP header/payload checksum checking is enabled
37207  */
37208 #define ENET_QOS_MAC_CONFIGURATION_IPC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPC_MASK)
37209 
37210 #define ENET_QOS_MAC_CONFIGURATION_SARC_MASK     (0x70000000U)
37211 #define ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT    (28U)
37212 /*! SARC - Source Address Insertion or Replacement Control
37213  *  0b010..Contents of MAC Addr-0 inserted in SA field
37214  *  0b011..Contents of MAC Addr-0 replaces SA field
37215  *  0b110..Contents of MAC Addr-1 inserted in SA field
37216  *  0b111..Contents of MAC Addr-1 replaces SA field
37217  *  0b000..mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation
37218  */
37219 #define ENET_QOS_MAC_CONFIGURATION_SARC(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_SARC_MASK)
37220 /*! @} */
37221 
37222 /*! @name MAC_EXT_CONFIGURATION - MAC Extended Configuration Register */
37223 /*! @{ */
37224 
37225 #define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFFU)
37226 #define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0U)
37227 /*! GPSL - Giant Packet Size Limit */
37228 #define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK)
37229 
37230 #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK (0x10000U)
37231 #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT (16U)
37232 /*! DCRCC - Disable CRC Checking for Received Packets
37233  *  0b1..CRC Checking is disabled
37234  *  0b0..CRC Checking is enabled
37235  */
37236 #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK)
37237 
37238 #define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK (0x20000U)
37239 #define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT (17U)
37240 /*! SPEN - Slow Protocol Detection Enable
37241  *  0b0..Slow Protocol Detection is disabled
37242  *  0b1..Slow Protocol Detection is enabled
37243  */
37244 #define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK)
37245 
37246 #define ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK  (0x40000U)
37247 #define ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT (18U)
37248 /*! USP - Unicast Slow Protocol Packet Detect
37249  *  0b0..Unicast Slow Protocol Packet Detection is disabled
37250  *  0b1..Unicast Slow Protocol Packet Detection is enabled
37251  */
37252 #define ENET_QOS_MAC_EXT_CONFIGURATION_USP(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK)
37253 
37254 #define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK  (0x80000U)
37255 #define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT (19U)
37256 /*! PDC - Packet Duplication Control
37257  *  0b0..Packet Duplication Control is disabled
37258  *  0b1..Packet Duplication Control is enabled
37259  */
37260 #define ENET_QOS_MAC_EXT_CONFIGURATION_PDC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK)
37261 
37262 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK (0x1000000U)
37263 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT (24U)
37264 /*! EIPGEN - Extended Inter-Packet Gap Enable
37265  *  0b0..Extended Inter-Packet Gap is disabled
37266  *  0b1..Extended Inter-Packet Gap is enabled
37267  */
37268 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK)
37269 
37270 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK (0x3E000000U)
37271 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25U)
37272 /*! EIPG - Extended Inter-Packet Gap */
37273 #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK)
37274 /*! @} */
37275 
37276 /*! @name MAC_PACKET_FILTER - MAC Packet Filter */
37277 /*! @{ */
37278 
37279 #define ENET_QOS_MAC_PACKET_FILTER_PR_MASK       (0x1U)
37280 #define ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT      (0U)
37281 /*! PR - Promiscuous Mode
37282  *  0b0..Promiscuous Mode is disabled
37283  *  0b1..Promiscuous Mode is enabled
37284  */
37285 #define ENET_QOS_MAC_PACKET_FILTER_PR(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PR_MASK)
37286 
37287 #define ENET_QOS_MAC_PACKET_FILTER_HUC_MASK      (0x2U)
37288 #define ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT     (1U)
37289 /*! HUC - Hash Unicast
37290  *  0b0..Hash Unicast is disabled
37291  *  0b1..Hash Unicast is enabled
37292  */
37293 #define ENET_QOS_MAC_PACKET_FILTER_HUC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HUC_MASK)
37294 
37295 #define ENET_QOS_MAC_PACKET_FILTER_HMC_MASK      (0x4U)
37296 #define ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT     (2U)
37297 /*! HMC - Hash Multicast
37298  *  0b0..Hash Multicast is disabled
37299  *  0b1..Hash Multicast is enabled
37300  */
37301 #define ENET_QOS_MAC_PACKET_FILTER_HMC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HMC_MASK)
37302 
37303 #define ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK     (0x8U)
37304 #define ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT    (3U)
37305 /*! DAIF - DA Inverse Filtering
37306  *  0b0..DA Inverse Filtering is disabled
37307  *  0b1..DA Inverse Filtering is enabled
37308  */
37309 #define ENET_QOS_MAC_PACKET_FILTER_DAIF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK)
37310 
37311 #define ENET_QOS_MAC_PACKET_FILTER_PM_MASK       (0x10U)
37312 #define ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT      (4U)
37313 /*! PM - Pass All Multicast
37314  *  0b0..Pass All Multicast is disabled
37315  *  0b1..Pass All Multicast is enabled
37316  */
37317 #define ENET_QOS_MAC_PACKET_FILTER_PM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PM_MASK)
37318 
37319 #define ENET_QOS_MAC_PACKET_FILTER_DBF_MASK      (0x20U)
37320 #define ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT     (5U)
37321 /*! DBF - Disable Broadcast Packets
37322  *  0b1..Disable Broadcast Packets
37323  *  0b0..Enable Broadcast Packets
37324  */
37325 #define ENET_QOS_MAC_PACKET_FILTER_DBF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DBF_MASK)
37326 
37327 #define ENET_QOS_MAC_PACKET_FILTER_PCF_MASK      (0xC0U)
37328 #define ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT     (6U)
37329 /*! PCF - Pass Control Packets These bits control the forwarding of all control packets (including
37330  *    unicast and multicast Pause packets).
37331  *  0b00..MAC filters all control packets from reaching the application
37332  *  0b10..MAC forwards all control packets to the application even if they fail the Address filter
37333  *  0b11..MAC forwards the control packets that pass the Address filter
37334  *  0b01..MAC forwards all control packets except Pause packets to the application even if they fail the Address filter
37335  */
37336 #define ENET_QOS_MAC_PACKET_FILTER_PCF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PCF_MASK)
37337 
37338 #define ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK     (0x100U)
37339 #define ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT    (8U)
37340 /*! SAIF - SA Inverse Filtering
37341  *  0b0..SA Inverse Filtering is disabled
37342  *  0b1..SA Inverse Filtering is enabled
37343  */
37344 #define ENET_QOS_MAC_PACKET_FILTER_SAIF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK)
37345 
37346 #define ENET_QOS_MAC_PACKET_FILTER_SAF_MASK      (0x200U)
37347 #define ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT     (9U)
37348 /*! SAF - Source Address Filter Enable
37349  *  0b0..SA Filtering is disabled
37350  *  0b1..SA Filtering is enabled
37351  */
37352 #define ENET_QOS_MAC_PACKET_FILTER_SAF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAF_MASK)
37353 
37354 #define ENET_QOS_MAC_PACKET_FILTER_HPF_MASK      (0x400U)
37355 #define ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT     (10U)
37356 /*! HPF - Hash or Perfect Filter
37357  *  0b0..Hash or Perfect Filter is disabled
37358  *  0b1..Hash or Perfect Filter is enabled
37359  */
37360 #define ENET_QOS_MAC_PACKET_FILTER_HPF(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HPF_MASK)
37361 
37362 #define ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK     (0x10000U)
37363 #define ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT    (16U)
37364 /*! VTFE - VLAN Tag Filter Enable
37365  *  0b0..VLAN Tag Filter is disabled
37366  *  0b1..VLAN Tag Filter is enabled
37367  */
37368 #define ENET_QOS_MAC_PACKET_FILTER_VTFE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK)
37369 
37370 #define ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK     (0x100000U)
37371 #define ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT    (20U)
37372 /*! IPFE - Layer 3 and Layer 4 Filter Enable
37373  *  0b0..Layer 3 and Layer 4 Filters are disabled
37374  *  0b1..Layer 3 and Layer 4 Filters are enabled
37375  */
37376 #define ENET_QOS_MAC_PACKET_FILTER_IPFE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK)
37377 
37378 #define ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK     (0x200000U)
37379 #define ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT    (21U)
37380 /*! DNTU - Drop Non-TCP/UDP over IP Packets
37381  *  0b1..Drop Non-TCP/UDP over IP Packets
37382  *  0b0..Forward Non-TCP/UDP over IP Packets
37383  */
37384 #define ENET_QOS_MAC_PACKET_FILTER_DNTU(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK)
37385 
37386 #define ENET_QOS_MAC_PACKET_FILTER_RA_MASK       (0x80000000U)
37387 #define ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT      (31U)
37388 /*! RA - Receive All
37389  *  0b0..Receive All is disabled
37390  *  0b1..Receive All is enabled
37391  */
37392 #define ENET_QOS_MAC_PACKET_FILTER_RA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_RA_MASK)
37393 /*! @} */
37394 
37395 /*! @name MAC_WATCHDOG_TIMEOUT - Watchdog Timeout */
37396 /*! @{ */
37397 
37398 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK   (0xFU)
37399 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT  (0U)
37400 /*! WTO - Watchdog Timeout
37401  *  0b1000..10 KB
37402  *  0b1001..11 KB
37403  *  0b1010..12 KB
37404  *  0b1011..13 KB
37405  *  0b1100..14 KB
37406  *  0b1101..15 KB
37407  *  0b1110..16383 Bytes
37408  *  0b0000..2 KB
37409  *  0b0001..3 KB
37410  *  0b0010..4 KB
37411  *  0b0011..5 KB
37412  *  0b0100..6 KB
37413  *  0b0101..7 KB
37414  *  0b0110..8 KB
37415  *  0b0111..9 KB
37416  *  0b1111..Reserved
37417  */
37418 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK)
37419 
37420 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK   (0x100U)
37421 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT  (8U)
37422 /*! PWE - Programmable Watchdog Enable
37423  *  0b0..Programmable Watchdog is disabled
37424  *  0b1..Programmable Watchdog is enabled
37425  */
37426 #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK)
37427 /*! @} */
37428 
37429 /*! @name MAC_HASH_TABLE_REG0 - MAC Hash Table Register 0 */
37430 /*! @{ */
37431 
37432 #define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFFU)
37433 #define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0U)
37434 /*! HT31T0 - MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table. */
37435 #define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK)
37436 /*! @} */
37437 
37438 /*! @name MAC_HASH_TABLE_REG1 - MAC Hash Table Register 1 */
37439 /*! @{ */
37440 
37441 #define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFFU)
37442 #define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0U)
37443 /*! HT63T32 - MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table. */
37444 #define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK)
37445 /*! @} */
37446 
37447 /*! @name MAC_VLAN_TAG_CTRL - MAC VLAN Tag Control */
37448 /*! @{ */
37449 
37450 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK       (0x1U)
37451 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT      (0U)
37452 /*! OB - Operation Busy
37453  *  0b0..Operation Busy is disabled
37454  *  0b1..Operation Busy is enabled
37455  */
37456 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OB(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK)
37457 
37458 #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK       (0x2U)
37459 #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT      (1U)
37460 /*! CT - Command Type
37461  *  0b1..Read operation
37462  *  0b0..Write operation
37463  */
37464 #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK)
37465 
37466 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK      (0x7CU)
37467 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT     (2U)
37468 /*! OFS - Offset */
37469 #define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK)
37470 
37471 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK     (0x20000U)
37472 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT    (17U)
37473 /*! VTIM - VLAN Tag Inverse Match Enable
37474  *  0b0..VLAN Tag Inverse Match is disabled
37475  *  0b1..VLAN Tag Inverse Match is enabled
37476  */
37477 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK)
37478 
37479 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK     (0x40000U)
37480 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT    (18U)
37481 /*! ESVL - Enable S-VLAN When this bit is set, the MAC transmitter and receiver consider the S-VLAN
37482  *    packets (Type = 0x88A8) as valid VLAN tagged packets.
37483  *  0b0..S-VLAN is disabled
37484  *  0b1..S-VLAN is enabled
37485  */
37486 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK)
37487 
37488 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK     (0x600000U)
37489 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT    (21U)
37490 /*! EVLS - Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the
37491  *    outer VLAN Tag in received packet.
37492  *  0b11..Always strip
37493  *  0b00..Do not strip
37494  *  0b10..Strip if VLAN filter fails
37495  *  0b01..Strip if VLAN filter passes
37496  */
37497 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK)
37498 
37499 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK   (0x1000000U)
37500 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT  (24U)
37501 /*! EVLRXS - Enable VLAN Tag in Rx status
37502  *  0b0..VLAN Tag in Rx status is disabled
37503  *  0b1..VLAN Tag in Rx status is enabled
37504  */
37505 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK)
37506 
37507 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK     (0x2000000U)
37508 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT    (25U)
37509 /*! VTHM - VLAN Tag Hash Table Match Enable
37510  *  0b0..VLAN Tag Hash Table Match is disabled
37511  *  0b1..VLAN Tag Hash Table Match is enabled
37512  */
37513 #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK)
37514 
37515 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK    (0x4000000U)
37516 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT   (26U)
37517 /*! EDVLP - Enable Double VLAN Processing
37518  *  0b0..Double VLAN Processing is disabled
37519  *  0b1..Double VLAN Processing is enabled
37520  */
37521 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK)
37522 
37523 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK   (0x8000000U)
37524 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT  (27U)
37525 /*! ERIVLT - ERIVLT
37526  *  0b0..Inner VLAN tag is disabled
37527  *  0b1..Inner VLAN tag is enabled
37528  */
37529 #define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK)
37530 
37531 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK    (0x30000000U)
37532 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT   (28U)
37533 /*! EIVLS - Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation
37534  *    on inner VLAN Tag in received packet.
37535  *  0b11..Always strip
37536  *  0b00..Do not strip
37537  *  0b10..Strip if VLAN filter fails
37538  *  0b01..Strip if VLAN filter passes
37539  */
37540 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK)
37541 
37542 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK  (0x80000000U)
37543 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT (31U)
37544 /*! EIVLRXS - Enable Inner VLAN Tag in Rx Status
37545  *  0b0..Inner VLAN Tag in Rx status is disabled
37546  *  0b1..Inner VLAN Tag in Rx status is enabled
37547  */
37548 #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK)
37549 /*! @} */
37550 
37551 /*! @name MAC_VLAN_TAG_DATA - MAC VLAN Tag Data */
37552 /*! @{ */
37553 
37554 #define ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK      (0xFFFFU)
37555 #define ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT     (0U)
37556 /*! VID - VLAN Tag ID */
37557 #define ENET_QOS_MAC_VLAN_TAG_DATA_VID(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK)
37558 
37559 #define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK      (0x10000U)
37560 #define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT     (16U)
37561 /*! VEN - VLAN Tag Enable
37562  *  0b0..VLAN Tag is disabled
37563  *  0b1..VLAN Tag is enabled
37564  */
37565 #define ENET_QOS_MAC_VLAN_TAG_DATA_VEN(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK)
37566 
37567 #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK      (0x20000U)
37568 #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT     (17U)
37569 /*! ETV - 12bits or 16bits VLAN comparison
37570  *  0b1..12 bit VLAN comparison
37571  *  0b0..16 bit VLAN comparison
37572  */
37573 #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK)
37574 
37575 #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK   (0x40000U)
37576 #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT  (18U)
37577 /*! DOVLTC - Disable VLAN Type Comparison
37578  *  0b1..VLAN type comparison is disabled
37579  *  0b0..VLAN type comparison is enabled
37580  */
37581 #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK)
37582 
37583 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK   (0x80000U)
37584 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT  (19U)
37585 /*! ERSVLM - Enable S-VLAN Match for received Frames
37586  *  0b0..Receive S-VLAN Match is disabled
37587  *  0b1..Receive S-VLAN Match is enabled
37588  */
37589 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK)
37590 
37591 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK   (0x100000U)
37592 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT  (20U)
37593 /*! ERIVLT - Enable Inner VLAN Tag Comparison
37594  *  0b0..Inner VLAN tag comparison is disabled
37595  *  0b1..Inner VLAN tag comparison is enabled
37596  */
37597 #define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK)
37598 
37599 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK  (0x1000000U)
37600 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT (24U)
37601 /*! DMACHEN - DMA Channel Number Enable
37602  *  0b0..DMA Channel Number is disabled
37603  *  0b1..DMA Channel Number is enabled
37604  */
37605 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK)
37606 
37607 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK   (0xE000000U)
37608 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT  (25U)
37609 /*! DMACHN - DMA Channel Number */
37610 #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK)
37611 /*! @} */
37612 
37613 /*! @name MAC_VLAN_HASH_TABLE - MAC VLAN Hash Table */
37614 /*! @{ */
37615 
37616 #define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK   (0xFFFFU)
37617 #define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT  (0U)
37618 /*! VLHT - VLAN Hash Table This field contains the 16-bit VLAN Hash Table. */
37619 #define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT)) & ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK)
37620 /*! @} */
37621 
37622 /*! @name MAC_VLAN_INCL - VLAN Tag Inclusion or Replacement */
37623 /*! @{ */
37624 
37625 #define ENET_QOS_MAC_VLAN_INCL_VLT_MASK          (0xFFFFU)
37626 #define ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT         (0U)
37627 /*! VLT - VLAN Tag for Transmit Packets */
37628 #define ENET_QOS_MAC_VLAN_INCL_VLT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLT_MASK)
37629 
37630 #define ENET_QOS_MAC_VLAN_INCL_VLC_MASK          (0x30000U)
37631 #define ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT         (16U)
37632 /*! VLC - VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion, insertion, or
37633  *    replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag
37634  *    (bytes 15 and 16) of all transmitted packets with VLAN tags.
37635  *  0b01..VLAN tag deletion
37636  *  0b10..VLAN tag insertion
37637  *  0b00..No VLAN tag deletion, insertion, or replacement
37638  *  0b11..VLAN tag replacement
37639  */
37640 #define ENET_QOS_MAC_VLAN_INCL_VLC(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLC_MASK)
37641 
37642 #define ENET_QOS_MAC_VLAN_INCL_VLP_MASK          (0x40000U)
37643 #define ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT         (18U)
37644 /*! VLP - VLAN Priority Control
37645  *  0b0..VLAN Priority Control is disabled
37646  *  0b1..VLAN Priority Control is enabled
37647  */
37648 #define ENET_QOS_MAC_VLAN_INCL_VLP(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLP_MASK)
37649 
37650 #define ENET_QOS_MAC_VLAN_INCL_CSVL_MASK         (0x80000U)
37651 #define ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT        (19U)
37652 /*! CSVL - C-VLAN or S-VLAN
37653  *  0b0..C-VLAN type (0x8100) is inserted or replaced
37654  *  0b1..S-VLAN type (0x88A8) is inserted or replaced
37655  */
37656 #define ENET_QOS_MAC_VLAN_INCL_CSVL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CSVL_MASK)
37657 
37658 #define ENET_QOS_MAC_VLAN_INCL_VLTI_MASK         (0x100000U)
37659 #define ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT        (20U)
37660 /*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or
37661  *    replaced in Tx packet should be taken from: - The Tx descriptor
37662  *  0b0..VLAN Tag Input is disabled
37663  *  0b1..VLAN Tag Input is enabled
37664  */
37665 #define ENET_QOS_MAC_VLAN_INCL_VLTI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLTI_MASK)
37666 
37667 #define ENET_QOS_MAC_VLAN_INCL_CBTI_MASK         (0x200000U)
37668 #define ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT        (21U)
37669 /*! CBTI - Channel based tag insertion
37670  *  0b0..Channel based tag insertion is disabled
37671  *  0b1..Channel based tag insertion is enabled
37672  */
37673 #define ENET_QOS_MAC_VLAN_INCL_CBTI(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CBTI_MASK)
37674 
37675 #define ENET_QOS_MAC_VLAN_INCL_ADDR_MASK         (0x7000000U)
37676 #define ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT        (24U)
37677 /*! ADDR - Address */
37678 #define ENET_QOS_MAC_VLAN_INCL_ADDR(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_ADDR_MASK)
37679 
37680 #define ENET_QOS_MAC_VLAN_INCL_RDWR_MASK         (0x40000000U)
37681 #define ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT        (30U)
37682 /*! RDWR - Read write control
37683  *  0b0..Read operation of indirect access
37684  *  0b1..Write operation of indirect access
37685  */
37686 #define ENET_QOS_MAC_VLAN_INCL_RDWR(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_RDWR_MASK)
37687 
37688 #define ENET_QOS_MAC_VLAN_INCL_BUSY_MASK         (0x80000000U)
37689 #define ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT        (31U)
37690 /*! BUSY - Busy
37691  *  0b1..Busy status detected
37692  *  0b0..Busy status not detected
37693  */
37694 #define ENET_QOS_MAC_VLAN_INCL_BUSY(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_BUSY_MASK)
37695 /*! @} */
37696 
37697 /*! @name MAC_INNER_VLAN_INCL - MAC Inner VLAN Tag Inclusion or Replacement */
37698 /*! @{ */
37699 
37700 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK    (0xFFFFU)
37701 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT   (0U)
37702 /*! VLT - VLAN Tag for Transmit Packets */
37703 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLT(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK)
37704 
37705 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK    (0x30000U)
37706 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT   (16U)
37707 /*! VLC - VLAN Tag Control in Transmit Packets
37708  *  0b01..VLAN tag deletion
37709  *  0b10..VLAN tag insertion
37710  *  0b00..No VLAN tag deletion, insertion, or replacement
37711  *  0b11..VLAN tag replacement
37712  */
37713 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK)
37714 
37715 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK    (0x40000U)
37716 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT   (18U)
37717 /*! VLP - VLAN Priority Control
37718  *  0b0..VLAN Priority Control is disabled
37719  *  0b1..VLAN Priority Control is enabled
37720  */
37721 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLP(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK)
37722 
37723 #define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK   (0x80000U)
37724 #define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT  (19U)
37725 /*! CSVL - C-VLAN or S-VLAN
37726  *  0b0..C-VLAN type (0x8100) is inserted
37727  *  0b1..S-VLAN type (0x88A8) is inserted
37728  */
37729 #define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK)
37730 
37731 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK   (0x100000U)
37732 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT  (20U)
37733 /*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or
37734  *    replaced in Tx packet should be taken from: - The Tx descriptor
37735  *  0b0..VLAN Tag Input is disabled
37736  *  0b1..VLAN Tag Input is enabled
37737  */
37738 #define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK)
37739 /*! @} */
37740 
37741 /*! @name MAC_TX_FLOW_CTRL_Q - MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control */
37742 /*! @{ */
37743 
37744 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK (0x1U)
37745 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT (0U)
37746 /*! FCB_BPA - Flow Control Busy or Backpressure Activate
37747  *  0b0..Flow Control Busy or Backpressure Activate is disabled
37748  *  0b1..Flow Control Busy or Backpressure Activate is enabled
37749  */
37750 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK)
37751 
37752 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK     (0x2U)
37753 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT    (1U)
37754 /*! TFE - Transmit Flow Control Enable
37755  *  0b0..Transmit Flow Control is disabled
37756  *  0b1..Transmit Flow Control is enabled
37757  */
37758 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
37759 
37760 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK     (0x70U)
37761 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT    (4U)
37762 /*! PLT - Pause Low Threshold
37763  *  0b011..Pause Time minus 144 Slot Times (PT -144 slot times)
37764  *  0b100..Pause Time minus 256 Slot Times (PT -256 slot times)
37765  *  0b001..Pause Time minus 28 Slot Times (PT -28 slot times)
37766  *  0b010..Pause Time minus 36 Slot Times (PT -36 slot times)
37767  *  0b000..Pause Time minus 4 Slot Times (PT -4 slot times)
37768  *  0b101..Pause Time minus 512 Slot Times (PT -512 slot times)
37769  *  0b110..Reserved
37770  */
37771 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
37772 
37773 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK    (0x80U)
37774 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT   (7U)
37775 /*! DZPQ - Disable Zero-Quanta Pause
37776  *  0b1..Zero-Quanta Pause packet generation is disabled
37777  *  0b0..Zero-Quanta Pause packet generation is enabled
37778  */
37779 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
37780 
37781 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK      (0xFFFF0000U)
37782 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT     (16U)
37783 /*! PT - Pause Time */
37784 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK)
37785 /*! @} */
37786 
37787 /* The count of ENET_QOS_MAC_TX_FLOW_CTRL_Q */
37788 #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_COUNT        (5U)
37789 
37790 /*! @name MAC_RX_FLOW_CTRL - MAC Rx Flow Control */
37791 /*! @{ */
37792 
37793 #define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK       (0x1U)
37794 #define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT      (0U)
37795 /*! RFE - Receive Flow Control Enable
37796  *  0b0..Receive Flow Control is disabled
37797  *  0b1..Receive Flow Control is enabled
37798  */
37799 #define ENET_QOS_MAC_RX_FLOW_CTRL_RFE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK)
37800 
37801 #define ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK        (0x2U)
37802 #define ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT       (1U)
37803 /*! UP - Unicast Pause Packet Detect
37804  *  0b0..Unicast Pause Packet Detect disabled
37805  *  0b1..Unicast Pause Packet Detect enabled
37806  */
37807 #define ENET_QOS_MAC_RX_FLOW_CTRL_UP(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK)
37808 
37809 #define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK      (0x100U)
37810 #define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT     (8U)
37811 /*! PFCE - Priority Based Flow Control Enable
37812  *  0b0..Priority Based Flow Control is disabled
37813  *  0b1..Priority Based Flow Control is enabled
37814  */
37815 #define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK)
37816 /*! @} */
37817 
37818 /*! @name MAC_RXQ_CTRL4 - Receive Queue Control 4 */
37819 /*! @{ */
37820 
37821 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK        (0x1U)
37822 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT       (0U)
37823 /*! UFFQE - Unicast Address Filter Fail Packets Queuing Enable.
37824  *  0b0..Unicast Address Filter Fail Packets Queuing is disabled
37825  *  0b1..Unicast Address Filter Fail Packets Queuing is enabled
37826  */
37827 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK)
37828 
37829 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK         (0xEU)
37830 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT        (1U)
37831 /*! UFFQ - Unicast Address Filter Fail Packets Queue. */
37832 #define ENET_QOS_MAC_RXQ_CTRL4_UFFQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK)
37833 
37834 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK        (0x100U)
37835 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT       (8U)
37836 /*! MFFQE - Multicast Address Filter Fail Packets Queuing Enable.
37837  *  0b0..Multicast Address Filter Fail Packets Queuing is disabled
37838  *  0b1..Multicast Address Filter Fail Packets Queuing is enabled
37839  */
37840 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK)
37841 
37842 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK         (0xE00U)
37843 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT        (9U)
37844 /*! MFFQ - Multicast Address Filter Fail Packets Queue. */
37845 #define ENET_QOS_MAC_RXQ_CTRL4_MFFQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK)
37846 
37847 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK        (0x10000U)
37848 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT       (16U)
37849 /*! VFFQE - VLAN Tag Filter Fail Packets Queuing Enable
37850  *  0b0..VLAN tag Filter Fail Packets Queuing is disabled
37851  *  0b1..VLAN tag Filter Fail Packets Queuing is enabled
37852  */
37853 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK)
37854 
37855 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK         (0xE0000U)
37856 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT        (17U)
37857 /*! VFFQ - VLAN Tag Filter Fail Packets Queue */
37858 #define ENET_QOS_MAC_RXQ_CTRL4_VFFQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK)
37859 /*! @} */
37860 
37861 /*! @name MAC_TXQ_PRTY_MAP0 - Transmit Queue Priority Mapping 0 */
37862 /*! @{ */
37863 
37864 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK    (0xFFU)
37865 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT   (0U)
37866 /*! PSTQ0 - Priorities Selected in Transmit Queue 0 */
37867 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK)
37868 
37869 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK    (0xFF00U)
37870 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT   (8U)
37871 /*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit. */
37872 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK)
37873 
37874 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK    (0xFF0000U)
37875 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT   (16U)
37876 /*! PSTQ2 - Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit. */
37877 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK)
37878 
37879 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK    (0xFF000000U)
37880 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT   (24U)
37881 /*! PSTQ3 - Priorities Selected in Transmit Queue 3 This bit is similar to the PSTQ0 bit. */
37882 #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK)
37883 /*! @} */
37884 
37885 /*! @name MAC_TXQ_PRTY_MAP1 - Transmit Queue Priority Mapping 1 */
37886 /*! @{ */
37887 
37888 #define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK    (0xFFU)
37889 #define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT   (0U)
37890 /*! PSTQ4 - Priorities Selected in Transmit Queue 4 */
37891 #define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK)
37892 /*! @} */
37893 
37894 /*! @name MAC_RXQ_CTRL - Receive Queue Control 0..Receive Queue Control 3 */
37895 /*! @{ */
37896 
37897 #define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK         (0x7U)
37898 #define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT        (0U)
37899 /*! AVCPQ - AV Untagged Control Packets Queue
37900  *  0b000..Receive Queue 0
37901  *  0b001..Receive Queue 1
37902  *  0b010..Receive Queue 2
37903  *  0b011..Receive Queue 3
37904  *  0b100..Receive Queue 4
37905  *  0b101..Reserved
37906  *  0b110..Reserved
37907  *  0b111..Reserved
37908  */
37909 #define ENET_QOS_MAC_RXQ_CTRL_AVCPQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK)
37910 
37911 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK         (0xFFU)
37912 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT        (0U)
37913 /*! PSRQ0 - Priorities Selected in the Receive Queue 0 */
37914 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ0(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK)
37915 
37916 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK         (0xFFU)
37917 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT        (0U)
37918 /*! PSRQ4 - Priorities Selected in the Receive Queue 4 */
37919 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ4(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK)
37920 
37921 #define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK        (0x3U)
37922 #define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT       (0U)
37923 /*! RXQ0EN - Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB.
37924  *  0b00..Queue not enabled
37925  *  0b01..Queue enabled for AV
37926  *  0b10..Queue enabled for DCB/Generic
37927  *  0b11..Reserved
37928  */
37929 #define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK)
37930 
37931 #define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK        (0xCU)
37932 #define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT       (2U)
37933 /*! RXQ1EN - Receive Queue 1 Enable This field is similar to the RXQ0EN field.
37934  *  0b00..Queue not enabled
37935  *  0b01..Queue enabled for AV
37936  *  0b10..Queue enabled for DCB/Generic
37937  *  0b11..Reserved
37938  */
37939 #define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK)
37940 
37941 #define ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK          (0x70U)
37942 #define ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT         (4U)
37943 /*! PTPQ - PTP Packets Queue
37944  *  0b000..Receive Queue 0
37945  *  0b001..Receive Queue 1
37946  *  0b010..Receive Queue 2
37947  *  0b011..Receive Queue 3
37948  *  0b100..Receive Queue 4
37949  *  0b101..Reserved
37950  *  0b110..Reserved
37951  *  0b111..Reserved
37952  */
37953 #define ENET_QOS_MAC_RXQ_CTRL_PTPQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK)
37954 
37955 #define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK        (0x30U)
37956 #define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT       (4U)
37957 /*! RXQ2EN - Receive Queue 2 Enable This field is similar to the RXQ0EN field.
37958  *  0b00..Queue not enabled
37959  *  0b01..Queue enabled for AV
37960  *  0b10..Queue enabled for DCB/Generic
37961  *  0b11..Reserved
37962  */
37963 #define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK)
37964 
37965 #define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK        (0xC0U)
37966 #define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT       (6U)
37967 /*! RXQ3EN - Receive Queue 3 Enable This field is similar to the RXQ0EN field.
37968  *  0b00..Queue not enabled
37969  *  0b01..Queue enabled for AV
37970  *  0b10..Queue enabled for DCB/Generic
37971  *  0b11..Reserved
37972  */
37973 #define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK)
37974 
37975 #define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK        (0x700U)
37976 #define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT       (8U)
37977 /*! DCBCPQ - DCB Control Packets Queue
37978  *  0b000..Receive Queue 0
37979  *  0b001..Receive Queue 1
37980  *  0b010..Receive Queue 2
37981  *  0b011..Receive Queue 3
37982  *  0b100..Receive Queue 4
37983  *  0b101..Reserved
37984  *  0b110..Reserved
37985  *  0b111..Reserved
37986  */
37987 #define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK)
37988 
37989 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK         (0xFF00U)
37990 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT        (8U)
37991 /*! PSRQ1 - Priorities Selected in the Receive Queue 1 */
37992 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ1(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK)
37993 
37994 #define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK        (0x300U)
37995 #define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT       (8U)
37996 /*! RXQ4EN - Receive Queue 4 Enable This field is similar to the RXQ0EN field.
37997  *  0b00..Queue not enabled
37998  *  0b01..Queue enabled for AV
37999  *  0b10..Queue enabled for DCB/Generic
38000  *  0b11..Reserved
38001  */
38002 #define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK)
38003 
38004 #define ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK           (0x7000U)
38005 #define ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT          (12U)
38006 /*! UPQ - Untagged Packet Queue
38007  *  0b000..Receive Queue 0
38008  *  0b001..Receive Queue 1
38009  *  0b010..Receive Queue 2
38010  *  0b011..Receive Queue 3
38011  *  0b100..Receive Queue 4
38012  *  0b101..Reserved
38013  *  0b110..Reserved
38014  *  0b111..Reserved
38015  */
38016 #define ENET_QOS_MAC_RXQ_CTRL_UPQ(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK)
38017 
38018 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK         (0x70000U)
38019 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT        (16U)
38020 /*! MCBCQ - Multicast and Broadcast Queue
38021  *  0b000..Receive Queue 0
38022  *  0b001..Receive Queue 1
38023  *  0b010..Receive Queue 2
38024  *  0b011..Receive Queue 3
38025  *  0b100..Receive Queue 4
38026  *  0b101..Reserved
38027  *  0b110..Reserved
38028  *  0b111..Reserved
38029  */
38030 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQ(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK)
38031 
38032 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK         (0xFF0000U)
38033 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT        (16U)
38034 /*! PSRQ2 - Priorities Selected in the Receive Queue 2 */
38035 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ2(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK)
38036 
38037 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK       (0x100000U)
38038 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT      (20U)
38039 /*! MCBCQEN - Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast
38040  *    packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed
38041  *    to Rx Queue specified in MCBCQ field.
38042  *  0b0..Multicast and Broadcast Queue is disabled
38043  *  0b1..Multicast and Broadcast Queue is enabled
38044  */
38045 #define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK)
38046 
38047 #define ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK        (0x200000U)
38048 #define ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT       (21U)
38049 /*! TACPQE - Tagged AV Control Packets Queuing Enable.
38050  *  0b0..Tagged AV Control Packets Queuing is disabled
38051  *  0b1..Tagged AV Control Packets Queuing is enabled
38052  */
38053 #define ENET_QOS_MAC_RXQ_CTRL_TACPQE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK)
38054 
38055 #define ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK          (0xC00000U)
38056 #define ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT         (22U)
38057 /*! TPQC - Tagged PTP over Ethernet Packets Queuing Control. */
38058 #define ENET_QOS_MAC_RXQ_CTRL_TPQC(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK)
38059 
38060 #define ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK          (0x7000000U)
38061 #define ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT         (24U)
38062 /*! FPRQ - Frame Preemption Residue Queue */
38063 #define ENET_QOS_MAC_RXQ_CTRL_FPRQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK)
38064 
38065 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK         (0xFF000000U)
38066 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT        (24U)
38067 /*! PSRQ3 - Priorities Selected in the Receive Queue 3 */
38068 #define ENET_QOS_MAC_RXQ_CTRL_PSRQ3(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK)
38069 /*! @} */
38070 
38071 /* The count of ENET_QOS_MAC_RXQ_CTRL */
38072 #define ENET_QOS_MAC_RXQ_CTRL_COUNT              (4U)
38073 
38074 /*! @name MAC_INTERRUPT_STATUS - Interrupt Status */
38075 /*! @{ */
38076 
38077 #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK (0x1U)
38078 #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT (0U)
38079 /*! RGSMIIIS - RGMII or SMII Interrupt Status
38080  *  0b1..RGMII or SMII Interrupt Status is active
38081  *  0b0..RGMII or SMII Interrupt Status is not active
38082  */
38083 #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK)
38084 
38085 #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK (0x8U)
38086 #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT (3U)
38087 /*! PHYIS - PHY Interrupt
38088  *  0b1..PHY Interrupt detected
38089  *  0b0..PHY Interrupt not detected
38090  */
38091 #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK)
38092 
38093 #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK (0x10U)
38094 #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT (4U)
38095 /*! PMTIS - PMT Interrupt Status
38096  *  0b1..PMT Interrupt status active
38097  *  0b0..PMT Interrupt status not active
38098  */
38099 #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK)
38100 
38101 #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK (0x20U)
38102 #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT (5U)
38103 /*! LPIIS - LPI Interrupt Status
38104  *  0b1..LPI Interrupt status active
38105  *  0b0..LPI Interrupt status not active
38106  */
38107 #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK)
38108 
38109 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK (0x100U)
38110 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT (8U)
38111 /*! MMCIS - MMC Interrupt Status
38112  *  0b1..MMC Interrupt status active
38113  *  0b0..MMC Interrupt status not active
38114  */
38115 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK)
38116 
38117 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK (0x200U)
38118 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT (9U)
38119 /*! MMCRXIS - MMC Receive Interrupt Status
38120  *  0b1..MMC Receive Interrupt status active
38121  *  0b0..MMC Receive Interrupt status not active
38122  */
38123 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK)
38124 
38125 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK (0x400U)
38126 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT (10U)
38127 /*! MMCTXIS - MMC Transmit Interrupt Status
38128  *  0b1..MMC Transmit Interrupt status active
38129  *  0b0..MMC Transmit Interrupt status not active
38130  */
38131 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK)
38132 
38133 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK (0x800U)
38134 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT (11U)
38135 /*! MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status
38136  *  0b1..MMC Receive Checksum Offload Interrupt status active
38137  *  0b0..MMC Receive Checksum Offload Interrupt status not active
38138  */
38139 #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK)
38140 
38141 #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK  (0x1000U)
38142 #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT (12U)
38143 /*! TSIS - Timestamp Interrupt Status
38144  *  0b1..Timestamp Interrupt status active
38145  *  0b0..Timestamp Interrupt status not active
38146  */
38147 #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK)
38148 
38149 #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK (0x2000U)
38150 #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT (13U)
38151 /*! TXSTSIS - Transmit Status Interrupt
38152  *  0b1..Transmit Interrupt status active
38153  *  0b0..Transmit Interrupt status not active
38154  */
38155 #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK)
38156 
38157 #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK (0x4000U)
38158 #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT (14U)
38159 /*! RXSTSIS - Receive Status Interrupt
38160  *  0b1..Receive Interrupt status active
38161  *  0b0..Receive Interrupt status not active
38162  */
38163 #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK)
38164 
38165 #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK (0x20000U)
38166 #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT (17U)
38167 /*! FPEIS - Frame Preemption Interrupt Status
38168  *  0b1..Frame Preemption Interrupt status active
38169  *  0b0..Frame Preemption Interrupt status not active
38170  */
38171 #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK)
38172 
38173 #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK (0x40000U)
38174 #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT (18U)
38175 /*! MDIOIS - MDIO Interrupt Status
38176  *  0b1..MDIO Interrupt status active
38177  *  0b0..MDIO Interrupt status not active
38178  */
38179 #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK)
38180 
38181 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK (0x80000U)
38182 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT (19U)
38183 /*! MFTIS - MMC FPE Transmit Interrupt Status
38184  *  0b1..MMC FPE Transmit Interrupt status active
38185  *  0b0..MMC FPE Transmit Interrupt status not active
38186  */
38187 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK)
38188 
38189 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK (0x100000U)
38190 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT (20U)
38191 /*! MFRIS - MMC FPE Receive Interrupt Status
38192  *  0b1..MMC FPE Receive Interrupt status active
38193  *  0b0..MMC FPE Receive Interrupt status not active
38194  */
38195 #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK)
38196 /*! @} */
38197 
38198 /*! @name MAC_INTERRUPT_ENABLE - Interrupt Enable */
38199 /*! @{ */
38200 
38201 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK (0x1U)
38202 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT (0U)
38203 /*! RGSMIIIE - RGMII or SMII Interrupt Enable When this bit is set, it enables the assertion of the
38204  *    interrupt signal because of the setting of RGSMIIIS bit in MAC_INTERRUPT_STATUS register.
38205  *  0b0..RGMII or SMII Interrupt is disabled
38206  *  0b1..RGMII or SMII Interrupt is enabled
38207  */
38208 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK)
38209 
38210 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK (0x8U)
38211 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT (3U)
38212 /*! PHYIE - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt
38213  *    signal because of the setting of MAC_INTERRUPT_STATUS[PHYIS].
38214  *  0b0..PHY Interrupt is disabled
38215  *  0b1..PHY Interrupt is enabled
38216  */
38217 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK)
38218 
38219 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK (0x10U)
38220 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT (4U)
38221 /*! PMTIE - PMT Interrupt Enable When this bit is set, it enables the assertion of the interrupt
38222  *    signal because of the setting of MAC_INTERRUPT_STATUS[PMTIS].
38223  *  0b0..PMT Interrupt is disabled
38224  *  0b1..PMT Interrupt is enabled
38225  */
38226 #define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK)
38227 
38228 #define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK (0x20U)
38229 #define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT (5U)
38230 /*! LPIIE - LPI Interrupt Enable When this bit is set, it enables the assertion of the interrupt
38231  *    signal because of the setting of MAC_INTERRUPT_STATUS[LPIIS].
38232  *  0b0..LPI Interrupt is disabled
38233  *  0b1..LPI Interrupt is enabled
38234  */
38235 #define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK)
38236 
38237 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK  (0x1000U)
38238 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT (12U)
38239 /*! TSIE - Timestamp Interrupt Enable When this bit is set, it enables the assertion of the
38240  *    interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TSIS].
38241  *  0b0..Timestamp Interrupt is disabled
38242  *  0b1..Timestamp Interrupt is enabled
38243  */
38244 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK)
38245 
38246 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK (0x2000U)
38247 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT (13U)
38248 /*! TXSTSIE - Transmit Status Interrupt Enable When this bit is set, it enables the assertion of the
38249  *    interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TXSTSIS].
38250  *  0b0..Timestamp Status Interrupt is disabled
38251  *  0b1..Timestamp Status Interrupt is enabled
38252  */
38253 #define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK)
38254 
38255 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK (0x4000U)
38256 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT (14U)
38257 /*! RXSTSIE - Receive Status Interrupt Enable When this bit is set, it enables the assertion of the
38258  *    interrupt signal because of the setting of MAC_INTERRUPT_STATUS[RXSTSIS].
38259  *  0b0..Receive Status Interrupt is disabled
38260  *  0b1..Receive Status Interrupt is enabled
38261  */
38262 #define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK)
38263 
38264 #define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK (0x20000U)
38265 #define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT (17U)
38266 /*! FPEIE - Frame Preemption Interrupt Enable When this bit is set, it enables the assertion of the
38267  *    interrupt when FPEIS field is set in the MAC_INTERRUPT_STATUS.
38268  *  0b0..Frame Preemption Interrupt is disabled
38269  *  0b1..Frame Preemption Interrupt is enabled
38270  */
38271 #define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK)
38272 
38273 #define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK (0x40000U)
38274 #define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT (18U)
38275 /*! MDIOIE - MDIO Interrupt Enable When this bit is set, it enables the assertion of the interrupt
38276  *    when MDIOIS field is set in the MAC_INTERRUPT_STATUS register.
38277  *  0b0..MDIO Interrupt is disabled
38278  *  0b1..MDIO Interrupt is enabled
38279  */
38280 #define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK)
38281 /*! @} */
38282 
38283 /*! @name MAC_RX_TX_STATUS - Receive Transmit Status */
38284 /*! @{ */
38285 
38286 #define ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK       (0x1U)
38287 #define ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT      (0U)
38288 /*! TJT - Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which
38289  *    happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled)
38290  *    and JD bit is reset in the MAC_CONFIGURATION register.
38291  *  0b1..Transmit Jabber Timeout occurred
38292  *  0b0..No Transmit Jabber Timeout
38293  */
38294 #define ENET_QOS_MAC_RX_TX_STATUS_TJT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK)
38295 
38296 #define ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK     (0x2U)
38297 #define ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT    (1U)
38298 /*! NCARR - No Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
38299  *    indicates that the carrier signal from the PHY is not present at the end of preamble transmission.
38300  *  0b1..No carrier
38301  *  0b0..Carrier is present
38302  */
38303 #define ENET_QOS_MAC_RX_TX_STATUS_NCARR(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK)
38304 
38305 #define ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK     (0x4U)
38306 #define ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT    (2U)
38307 /*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
38308  *    indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i
38309  *    signal was inactive for one or more transmission clock periods during packet transmission.
38310  *  0b1..Loss of carrier
38311  *  0b0..Carrier is present
38312  */
38313 #define ENET_QOS_MAC_RX_TX_STATUS_LCARR(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK)
38314 
38315 #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK     (0x8U)
38316 #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT    (3U)
38317 /*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MAC_OPERATION_MODE register and the
38318  *    DC bit is set in the MAC_CONFIGURATION register, this bit indicates that the transmission
38319  *    ended because of excessive deferral of over 24,288 bit times (155,680 in 1000/2500 Mbps mode or
38320  *    when Jumbo packet is enabled).
38321  *  0b1..Excessive deferral
38322  *  0b0..No Excessive deferral
38323  */
38324 #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK)
38325 
38326 #define ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK      (0x10U)
38327 #define ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT     (4U)
38328 /*! LCOL - Late Collision When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
38329  *    indicates that the packet transmission aborted because a collision occurred after the collision
38330  *    window (64 bytes including Preamble in MII mode; 512 bytes including Preamble and Carrier
38331  *    Extension in GMII mode).
38332  *  0b1..Late collision is sensed
38333  *  0b0..No collision
38334  */
38335 #define ENET_QOS_MAC_RX_TX_STATUS_LCOL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK)
38336 
38337 #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK     (0x20U)
38338 #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT    (5U)
38339 /*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this
38340  *    bit indicates that the transmission aborted after 16 successive collisions while attempting
38341  *    to transmit the current packet.
38342  *  0b1..Excessive collision is sensed
38343  *  0b0..No collision
38344  */
38345 #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK)
38346 
38347 #define ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK       (0x100U)
38348 #define ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT      (8U)
38349 /*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048
38350  *    bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the
38351  *    MAC_CONFIGURATION register.
38352  *  0b1..Receive watchdog timed out
38353  *  0b0..No receive watchdog timeout
38354  */
38355 #define ENET_QOS_MAC_RX_TX_STATUS_RWT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK)
38356 /*! @} */
38357 
38358 /*! @name MAC_PMT_CONTROL_STATUS - PMT Control and Status */
38359 /*! @{ */
38360 
38361 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK (0x1U)
38362 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT (0U)
38363 /*! PWRDWN - Power Down When this bit is set, the MAC receiver drops all received packets until it
38364  *    receives the expected magic packet or remote wake-up packet.
38365  *  0b0..Power down is disabled
38366  *  0b1..Power down is enabled
38367  */
38368 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK)
38369 
38370 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK (0x2U)
38371 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT (1U)
38372 /*! MGKPKTEN - Magic Packet Enable When this bit is set, a power management event is generated when the MAC receives a magic packet.
38373  *  0b0..Magic Packet is disabled
38374  *  0b1..Magic Packet is enabled
38375  */
38376 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK)
38377 
38378 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK (0x4U)
38379 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT (2U)
38380 /*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is
38381  *    generated when the MAC receives a remote wake-up packet.
38382  *  0b0..Remote wake-up packet is disabled
38383  *  0b1..Remote wake-up packet is enabled
38384  */
38385 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK)
38386 
38387 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK (0x20U)
38388 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT (5U)
38389 /*! MGKPRCVD - Magic Packet Received When this bit is set, it indicates that the power management
38390  *    event is generated because of the reception of a magic packet.
38391  *  0b1..Magic packet is received
38392  *  0b0..No Magic packet is received
38393  */
38394 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK)
38395 
38396 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK (0x40U)
38397 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT (6U)
38398 /*! RWKPRCVD - Remote Wake-Up Packet Received When this bit is set, it indicates that the power
38399  *    management event is generated because of the reception of a remote wake-up packet.
38400  *  0b1..Remote wake-up packet is received
38401  *  0b0..Remote wake-up packet is received
38402  */
38403 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK)
38404 
38405 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK (0x200U)
38406 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT (9U)
38407 /*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF)
38408  *    address recognition is detected as a remote wake-up packet.
38409  *  0b0..Global unicast is disabled
38410  *  0b1..Global unicast is enabled
38411  */
38412 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK)
38413 
38414 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK (0x400U)
38415 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT (10U)
38416 /*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the
38417  *    MAC receiver drops all received frames until it receives the expected Wake-up frame.
38418  *  0b0..Remote Wake-up Packet Forwarding is disabled
38419  *  0b1..Remote Wake-up Packet Forwarding is enabled
38420  */
38421 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK)
38422 
38423 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK (0x1F000000U)
38424 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT (24U)
38425 /*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7, 15, or 31 when
38426  *    4, 8, or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter
38427  *    register pointer.
38428  */
38429 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK)
38430 
38431 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK (0x80000000U)
38432 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT (31U)
38433 /*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the
38434  *    remote wake-up packet filter register pointer is reset to 3'b000.
38435  *  0b0..Remote Wake-Up Packet Filter Register Pointer is not Reset
38436  *  0b1..Remote Wake-Up Packet Filter Register Pointer is Reset
38437  */
38438 #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK)
38439 /*! @} */
38440 
38441 /*! @name MAC_RWK_PACKET_FILTER - Remote Wakeup Filter */
38442 /*! @{ */
38443 
38444 #define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK (0xFFFFFFFFU)
38445 #define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT (0U)
38446 /*! WKUPFRMFTR - RWK Packet Filter This field contains the various controls of RWK Packet filter. */
38447 #define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT)) & ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK)
38448 /*! @} */
38449 
38450 /*! @name MAC_LPI_CONTROL_STATUS - LPI Control and Status */
38451 /*! @{ */
38452 
38453 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK (0x1U)
38454 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT (0U)
38455 /*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
38456  *    entered the LPI state because of the setting of the LPIEN bit.
38457  *  0b1..Transmit LPI entry detected
38458  *  0b0..Transmit LPI entry not detected
38459  */
38460 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK)
38461 
38462 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK (0x2U)
38463 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT (1U)
38464 /*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited
38465  *    the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired.
38466  *  0b1..Transmit LPI exit detected
38467  *  0b0..Transmit LPI exit not detected
38468  */
38469 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK)
38470 
38471 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK (0x4U)
38472 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT (2U)
38473 /*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received
38474  *    an LPI pattern and entered the LPI state.
38475  *  0b1..Receive LPI entry detected
38476  *  0b0..Receive LPI entry not detected
38477  */
38478 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK)
38479 
38480 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK (0x8U)
38481 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT (3U)
38482 /*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped
38483  *    receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the
38484  *    normal reception.
38485  *  0b1..Receive LPI exit detected
38486  *  0b0..Receive LPI exit not detected
38487  */
38488 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK)
38489 
38490 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK (0x100U)
38491 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT (8U)
38492 /*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the
38493  *    LPI pattern on the GMII or MII interface.
38494  *  0b1..Transmit LPI state detected
38495  *  0b0..Transmit LPI state not detected
38496  */
38497 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK)
38498 
38499 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK (0x200U)
38500 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT (9U)
38501 /*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI
38502  *    pattern on the GMII or MII interface.
38503  *  0b1..Receive LPI state detected
38504  *  0b0..Receive LPI state not detected
38505  */
38506 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK)
38507 
38508 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK (0x10000U)
38509 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT (16U)
38510 /*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state.
38511  *  0b0..LPI state is disabled
38512  *  0b1..LPI state is enabled
38513  */
38514 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK)
38515 
38516 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK (0x20000U)
38517 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT (17U)
38518 /*! PLS - PHY Link Status This bit indicates the link status of the PHY.
38519  *  0b0..link is down
38520  *  0b1..link is okay (UP)
38521  */
38522 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK)
38523 
38524 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK (0x40000U)
38525 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT (18U)
38526 /*! PLSEN - PHY Link Status Enable This bit enables the link status received on the RGMII, SGMII, or
38527  *    SMII Receive paths to be used for activating the LPI LS TIMER.
38528  *  0b0..PHY Link Status is disabled
38529  *  0b1..PHY Link Status is enabled
38530  */
38531 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK)
38532 
38533 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK (0x80000U)
38534 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT (19U)
38535 /*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming
38536  *    out of the LPI mode on the Transmit side.
38537  *  0b0..LPI Tx Automate is disabled
38538  *  0b1..LPI Tx Automate is enabled
38539  */
38540 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK)
38541 
38542 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK (0x100000U)
38543 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT (20U)
38544 /*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state.
38545  *  0b0..LPI Timer is disabled
38546  *  0b1..LPI Timer is enabled
38547  */
38548 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK)
38549 
38550 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK (0x200000U)
38551 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT (21U)
38552 /*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts
38553  *    sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped.
38554  *  0b0..LPI Tx Clock Stop is disabled
38555  *  0b1..LPI Tx Clock Stop is enabled
38556  */
38557 #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK)
38558 /*! @} */
38559 
38560 /*! @name MAC_LPI_TIMERS_CONTROL - LPI Timers Control */
38561 /*! @{ */
38562 
38563 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK (0xFFFFU)
38564 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT (0U)
38565 /*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC
38566  *    waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal
38567  *    transmission.
38568  */
38569 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK)
38570 
38571 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK (0x3FF0000U)
38572 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT (16U)
38573 /*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link
38574  *    status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY.
38575  */
38576 #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK)
38577 /*! @} */
38578 
38579 /*! @name MAC_LPI_ENTRY_TIMER - Tx LPI Entry Timer Control */
38580 /*! @{ */
38581 
38582 #define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK  (0xFFFF8U)
38583 #define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT (3U)
38584 /*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI
38585  *    mode, after it has transmitted all the frames.
38586  */
38587 #define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT)) & ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK)
38588 /*! @} */
38589 
38590 /*! @name MAC_ONEUS_TIC_COUNTER - One-microsecond Reference Timer */
38591 /*! @{ */
38592 
38593 #define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK (0xFFFU)
38594 #define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT (0U)
38595 /*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us. */
38596 #define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT)) & ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK)
38597 /*! @} */
38598 
38599 /*! @name MAC_PHYIF_CONTROL_STATUS - PHY Interface Control and Status */
38600 /*! @{ */
38601 
38602 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK (0x1U)
38603 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT (0U)
38604 /*! TC - Transmit Configuration in RGMII, SGMII, or SMII When set, this bit enables the transmission
38605  *    of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or
38606  *    SGMII port.
38607  *  0b0..Disable Transmit Configuration in RGMII, SGMII, or SMII
38608  *  0b1..Enable Transmit Configuration in RGMII, SGMII, or SMII
38609  */
38610 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK)
38611 
38612 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK (0x2U)
38613 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT (1U)
38614 /*! LUD - Link Up or Down This bit indicates whether the link is up or down during transmission of
38615  *    configuration in the RGMII, SGMII, or SMII interface.
38616  *  0b0..Link down
38617  *  0b1..Link up
38618  */
38619 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK)
38620 
38621 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK (0x10000U)
38622 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT (16U)
38623 /*! LNKMOD - Link Mode This bit indicates the current mode of operation of the link.
38624  *  0b1..Full-duplex mode
38625  *  0b0..Half-duplex mode
38626  */
38627 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK)
38628 
38629 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK (0x60000U)
38630 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT (17U)
38631 /*! LNKSPEED - Link Speed This bit indicates the current speed of the link.
38632  *  0b10..125 MHz
38633  *  0b00..2.5 MHz
38634  *  0b01..25 MHz
38635  *  0b11..Reserved
38636  */
38637 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK)
38638 
38639 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK (0x80000U)
38640 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT (19U)
38641 /*! LNKSTS - Link Status This bit indicates whether the link is up (1'b1) or down (1'b0).
38642  *  0b1..Link up
38643  *  0b0..Link down
38644  */
38645 #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK)
38646 /*! @} */
38647 
38648 /*! @name MAC_VERSION - MAC Version */
38649 /*! @{ */
38650 
38651 #define ENET_QOS_MAC_VERSION_SNPSVER_MASK        (0xFFU)
38652 #define ENET_QOS_MAC_VERSION_SNPSVER_SHIFT       (0U)
38653 /*! SNPSVER - Synopsys-defined Version */
38654 #define ENET_QOS_MAC_VERSION_SNPSVER(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_SNPSVER_SHIFT)) & ENET_QOS_MAC_VERSION_SNPSVER_MASK)
38655 
38656 #define ENET_QOS_MAC_VERSION_USERVER_MASK        (0xFF00U)
38657 #define ENET_QOS_MAC_VERSION_USERVER_SHIFT       (8U)
38658 /*! USERVER - User-defined Version (8'h10) */
38659 #define ENET_QOS_MAC_VERSION_USERVER(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_USERVER_SHIFT)) & ENET_QOS_MAC_VERSION_USERVER_MASK)
38660 /*! @} */
38661 
38662 /*! @name MAC_DEBUG - MAC Debug */
38663 /*! @{ */
38664 
38665 #define ENET_QOS_MAC_DEBUG_RPESTS_MASK           (0x1U)
38666 #define ENET_QOS_MAC_DEBUG_RPESTS_SHIFT          (0U)
38667 /*! RPESTS - MAC GMII or MII Receive Protocol Engine Status When this bit is set, it indicates that
38668  *    the MAC GMII or MII receive protocol engine is actively receiving data, and it is not in the
38669  *    Idle state.
38670  *  0b1..MAC GMII or MII Receive Protocol Engine Status detected
38671  *  0b0..MAC GMII or MII Receive Protocol Engine Status not detected
38672  */
38673 #define ENET_QOS_MAC_DEBUG_RPESTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RPESTS_MASK)
38674 
38675 #define ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK         (0x6U)
38676 #define ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT        (1U)
38677 /*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates
38678  *    the active state of the small FIFO Read and Write controllers of the MAC Receive Packet
38679  *    Controller module.
38680  */
38681 #define ENET_QOS_MAC_DEBUG_RFCFCSTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK)
38682 
38683 #define ENET_QOS_MAC_DEBUG_TPESTS_MASK           (0x10000U)
38684 #define ENET_QOS_MAC_DEBUG_TPESTS_SHIFT          (16U)
38685 /*! TPESTS - MAC GMII or MII Transmit Protocol Engine Status When this bit is set, it indicates that
38686  *    the MAC GMII or MII transmit protocol engine is actively transmitting data, and it is not in
38687  *    the Idle state.
38688  *  0b1..MAC GMII or MII Transmit Protocol Engine Status detected
38689  *  0b0..MAC GMII or MII Transmit Protocol Engine Status not detected
38690  */
38691 #define ENET_QOS_MAC_DEBUG_TPESTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TPESTS_MASK)
38692 
38693 #define ENET_QOS_MAC_DEBUG_TFCSTS_MASK           (0x60000U)
38694 #define ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT          (17U)
38695 /*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module.
38696  *  0b10..Generating and transmitting a Pause control packet (in full-duplex mode)
38697  *  0b00..Idle state
38698  *  0b11..Transferring input packet for transmission
38699  *  0b01..Waiting for one of the following: Status of the previous packet OR IPG or back off period to be over
38700  */
38701 #define ENET_QOS_MAC_DEBUG_TFCSTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TFCSTS_MASK)
38702 /*! @} */
38703 
38704 /*! @name MAC_HW_FEAT - Optional Features or Functions 0..Optional Features or Functions 3 */
38705 /*! @{ */
38706 
38707 #define ENET_QOS_MAC_HW_FEAT_MIISEL_MASK         (0x1U)
38708 #define ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT        (0U)
38709 /*! MIISEL - 10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation
38710  *  0b1..10 or 100 Mbps support
38711  *  0b0..No 10 or 100 Mbps support
38712  */
38713 #define ENET_QOS_MAC_HW_FEAT_MIISEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MIISEL_MASK)
38714 
38715 #define ENET_QOS_MAC_HW_FEAT_NRVF_MASK           (0x7U)
38716 #define ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT          (0U)
38717 /*! NRVF - Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected:
38718  *  0b011..16 Extended Rx VLAN Filters
38719  *  0b100..24 Extended Rx VLAN Filters
38720  *  0b101..32 Extended Rx VLAN Filters
38721  *  0b001..4 Extended Rx VLAN Filters
38722  *  0b010..8 Extended Rx VLAN Filters
38723  *  0b000..No Extended Rx VLAN Filters
38724  *  0b110..Reserved
38725  */
38726 #define ENET_QOS_MAC_HW_FEAT_NRVF(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT)) & ENET_QOS_MAC_HW_FEAT_NRVF_MASK)
38727 
38728 #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK     (0x1FU)
38729 #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT    (0U)
38730 /*! RXFIFOSIZE - MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in
38731  *    bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7:
38732  *  0b00011..1024 bytes
38733  *  0b00000..128 bytes
38734  *  0b01010..128 KB
38735  *  0b00111..16384 bytes
38736  *  0b00100..2048 bytes
38737  *  0b00001..256 bytes
38738  *  0b01011..256 KB
38739  *  0b01000..32 KB
38740  *  0b00101..4096 bytes
38741  *  0b00010..512 bytes
38742  *  0b01001..64 KB
38743  *  0b00110..8192 bytes
38744  *  0b01100..Reserved
38745  */
38746 #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK)
38747 
38748 #define ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK         (0xFU)
38749 #define ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT        (0U)
38750 /*! RXQCNT - Number of MTL Receive Queues This field indicates the number of MTL Receive queues:
38751  *  0b0000..1 MTL Rx Queue
38752  *  0b0001..2 MTL Rx Queues
38753  *  0b0010..3 MTL Rx Queues
38754  *  0b0011..4 MTL Rx Queues
38755  *  0b0100..5 MTL Rx Queues
38756  *  0b0101..Reserved
38757  *  0b0110..Reserved
38758  *  0b0111..Reserved
38759  */
38760 #define ENET_QOS_MAC_HW_FEAT_RXQCNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK)
38761 
38762 #define ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK        (0x2U)
38763 #define ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT       (1U)
38764 /*! GMIISEL - 1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation
38765  *  0b1..1000 Mbps support
38766  *  0b0..No 1000 Mbps support
38767  */
38768 #define ENET_QOS_MAC_HW_FEAT_GMIISEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK)
38769 
38770 #define ENET_QOS_MAC_HW_FEAT_HDSEL_MASK          (0x4U)
38771 #define ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT         (2U)
38772 /*! HDSEL - Half-duplex Support This bit is set to 1 when the half-duplex mode is selected
38773  *  0b1..Half-duplex support
38774  *  0b0..No Half-duplex support
38775  */
38776 #define ENET_QOS_MAC_HW_FEAT_HDSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HDSEL_MASK)
38777 
38778 #define ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK         (0x8U)
38779 #define ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT        (3U)
38780 /*! PCSSEL - PCS Registers (TBI, SGMII, or RTBI PHY interface) This bit is set to 1 when the TBI,
38781  *    SGMII, or RTBI PHY interface option is selected
38782  *  0b1..PCS Registers (TBI, SGMII, or RTBI PHY interface)
38783  *  0b0..No PCS Registers (TBI, SGMII, or RTBI PHY interface)
38784  */
38785 #define ENET_QOS_MAC_HW_FEAT_PCSSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK)
38786 
38787 #define ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK        (0x10U)
38788 #define ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT       (4U)
38789 /*! CBTISEL - Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the
38790  *    Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected.
38791  *  0b1..Enable Queue/Channel based VLAN tag insertion on Tx feature is selected
38792  *  0b0..Enable Queue/Channel based VLAN tag insertion on Tx feature is not selected
38793  */
38794 #define ENET_QOS_MAC_HW_FEAT_CBTISEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK)
38795 
38796 #define ENET_QOS_MAC_HW_FEAT_VLHASH_MASK         (0x10U)
38797 #define ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT        (4U)
38798 /*! VLHASH - VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected
38799  *  0b1..VLAN Hash Filter selected
38800  *  0b0..VLAN Hash Filter not selected
38801  */
38802 #define ENET_QOS_MAC_HW_FEAT_VLHASH(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_QOS_MAC_HW_FEAT_VLHASH_MASK)
38803 
38804 #define ENET_QOS_MAC_HW_FEAT_DVLAN_MASK          (0x20U)
38805 #define ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT         (5U)
38806 /*! DVLAN - Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected.
38807  *  0b1..Double VLAN option is selected
38808  *  0b0..Double VLAN option is not selected
38809  */
38810 #define ENET_QOS_MAC_HW_FEAT_DVLAN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DVLAN_MASK)
38811 
38812 #define ENET_QOS_MAC_HW_FEAT_SMASEL_MASK         (0x20U)
38813 #define ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT        (5U)
38814 /*! SMASEL - SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected
38815  *  0b1..SMA (MDIO) Interface selected
38816  *  0b0..SMA (MDIO) Interface not selected
38817  */
38818 #define ENET_QOS_MAC_HW_FEAT_SMASEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SMASEL_MASK)
38819 
38820 #define ENET_QOS_MAC_HW_FEAT_SPRAM_MASK          (0x20U)
38821 #define ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT         (5U)
38822 /*! SPRAM - Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected.
38823  *  0b1..Single Port RAM feature is selected
38824  *  0b0..Single Port RAM feature is not selected
38825  */
38826 #define ENET_QOS_MAC_HW_FEAT_SPRAM(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPRAM_MASK)
38827 
38828 #define ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK         (0x40U)
38829 #define ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT        (6U)
38830 /*! RWKSEL - PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected
38831  *  0b1..PMT Remote Wake-up Packet Enable option is selected
38832  *  0b0..PMT Remote Wake-up Packet Enable option is not selected
38833  */
38834 #define ENET_QOS_MAC_HW_FEAT_RWKSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK)
38835 
38836 #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK     (0x7C0U)
38837 #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT    (6U)
38838 /*! TXFIFOSIZE - MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in
38839  *    bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7:
38840  *  0b00011..1024 bytes
38841  *  0b00000..128 bytes
38842  *  0b01010..128 KB
38843  *  0b00111..16384 bytes
38844  *  0b00100..2048 bytes
38845  *  0b00001..256 bytes
38846  *  0b01000..32 KB
38847  *  0b00101..4096 bytes
38848  *  0b00010..512 bytes
38849  *  0b01001..64 KB
38850  *  0b00110..8192 bytes
38851  *  0b01011..Reserved
38852  */
38853 #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK)
38854 
38855 #define ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK         (0x3C0U)
38856 #define ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT        (6U)
38857 /*! TXQCNT - Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues:
38858  *  0b0000..1 MTL Tx Queue
38859  *  0b0001..2 MTL Tx Queues
38860  *  0b0010..3 MTL Tx Queues
38861  *  0b0011..4 MTL Tx Queues
38862  *  0b0100..5 MTL Tx Queues
38863  *  0b0101..Reserved
38864  *  0b0110..Reserved
38865  *  0b0111..Reserved
38866  */
38867 #define ENET_QOS_MAC_HW_FEAT_TXQCNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK)
38868 
38869 #define ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK         (0x80U)
38870 #define ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT        (7U)
38871 /*! MGKSEL - PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected
38872  *  0b1..PMT Magic Packet Enable option is selected
38873  *  0b0..PMT Magic Packet Enable option is not selected
38874  */
38875 #define ENET_QOS_MAC_HW_FEAT_MGKSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK)
38876 
38877 #define ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK         (0x100U)
38878 #define ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT        (8U)
38879 /*! MMCSEL - RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected
38880  *  0b1..RMON Module Enable option is selected
38881  *  0b0..RMON Module Enable option is not selected
38882  */
38883 #define ENET_QOS_MAC_HW_FEAT_MMCSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK)
38884 
38885 #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK      (0x200U)
38886 #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT     (9U)
38887 /*! ARPOFFSEL - ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected
38888  *  0b1..ARP Offload Enable option is selected
38889  *  0b0..ARP Offload Enable option is not selected
38890  */
38891 #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK)
38892 
38893 #define ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK        (0x200U)
38894 #define ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT       (9U)
38895 /*! PDUPSEL - Broadcast/Multicast Packet Duplication This bit is set to 1 when the
38896  *    Broadcast/Multicast Packet Duplication feature is selected.
38897  *  0b1..Broadcast/Multicast Packet Duplication feature is selected
38898  *  0b0..Broadcast/Multicast Packet Duplication feature is not selected
38899  */
38900 #define ENET_QOS_MAC_HW_FEAT_PDUPSEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK)
38901 
38902 #define ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK         (0x400U)
38903 #define ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT        (10U)
38904 /*! FRPSEL - Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible
38905  *    Programmable Receive Parser option is selected.
38906  *  0b1..Flexible Receive Parser feature is selected
38907  *  0b0..Flexible Receive Parser feature is not selected
38908  */
38909 #define ENET_QOS_MAC_HW_FEAT_FRPSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK)
38910 
38911 #define ENET_QOS_MAC_HW_FEAT_FRPBS_MASK          (0x1800U)
38912 #define ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT         (11U)
38913 /*! FRPBS - Flexible Receive Parser Buffer size This field indicates the supported Max Number of
38914  *    bytes of the packet data to be Parsed by Flexible Receive Parser.
38915  *  0b01..128 Bytes
38916  *  0b10..256 Bytes
38917  *  0b00..64 Bytes
38918  *  0b11..Reserved
38919  */
38920 #define ENET_QOS_MAC_HW_FEAT_FRPBS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPBS_MASK)
38921 
38922 #define ENET_QOS_MAC_HW_FEAT_OSTEN_MASK          (0x800U)
38923 #define ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT         (11U)
38924 /*! OSTEN - One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected.
38925  *  0b1..One-Step Timestamping feature is selected
38926  *  0b0..One-Step Timestamping feature is not selected
38927  */
38928 #define ENET_QOS_MAC_HW_FEAT_OSTEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_OSTEN_MASK)
38929 
38930 #define ENET_QOS_MAC_HW_FEAT_PTOEN_MASK          (0x1000U)
38931 #define ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT         (12U)
38932 /*! PTOEN - PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected.
38933  *  0b1..PTP Offload feature is selected
38934  *  0b0..PTP Offload feature is not selected
38935  */
38936 #define ENET_QOS_MAC_HW_FEAT_PTOEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PTOEN_MASK)
38937 
38938 #define ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK        (0xF000U)
38939 #define ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT       (12U)
38940 /*! RXCHCNT - Number of DMA Receive Channels This field indicates the number of DMA Receive channels:
38941  *  0b0000..1 MTL Rx Channel
38942  *  0b0001..2 MTL Rx Channels
38943  *  0b0010..3 MTL Rx Channels
38944  *  0b0011..4 MTL Rx Channels
38945  *  0b0100..5 MTL Rx Channels
38946  *  0b0101..Reserved
38947  *  0b0110..Reserved
38948  *  0b0111..Reserved
38949  */
38950 #define ENET_QOS_MAC_HW_FEAT_RXCHCNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK)
38951 
38952 #define ENET_QOS_MAC_HW_FEAT_TSSEL_MASK          (0x1000U)
38953 #define ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT         (12U)
38954 /*! TSSEL - IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected
38955  *  0b1..IEEE 1588-2008 Timestamp Enable option is selected
38956  *  0b0..IEEE 1588-2008 Timestamp Enable option is not selected
38957  */
38958 #define ENET_QOS_MAC_HW_FEAT_TSSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSEL_MASK)
38959 
38960 #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK      (0x2000U)
38961 #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT     (13U)
38962 /*! ADVTHWORD - IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected
38963  *  0b1..IEEE 1588 High Word Register option is selected
38964  *  0b0..IEEE 1588 High Word Register option is not selected
38965  */
38966 #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK)
38967 
38968 #define ENET_QOS_MAC_HW_FEAT_EEESEL_MASK         (0x2000U)
38969 #define ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT        (13U)
38970 /*! EEESEL - Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient
38971  *    Ethernet (EEE) option is selected
38972  *  0b1..Energy Efficient Ethernet Enable option is selected
38973  *  0b0..Energy Efficient Ethernet Enable option is not selected
38974  */
38975 #define ENET_QOS_MAC_HW_FEAT_EEESEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_EEESEL_MASK)
38976 
38977 #define ENET_QOS_MAC_HW_FEAT_FRPES_MASK          (0x6000U)
38978 #define ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT         (13U)
38979 /*! FRPES - Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser
38980  *    Entries supported by Flexible Receive Parser.
38981  *  0b01..128 Entries
38982  *  0b10..256 Entries
38983  *  0b00..64 Entries
38984  *  0b11..Reserved
38985  */
38986 #define ENET_QOS_MAC_HW_FEAT_FRPES(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPES_MASK)
38987 
38988 #define ENET_QOS_MAC_HW_FEAT_ADDR64_MASK         (0xC000U)
38989 #define ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT        (14U)
38990 /*! ADDR64 - Address Width.
38991  *  0b00..32
38992  *  0b01..40
38993  *  0b10..48
38994  *  0b11..Reserved
38995  */
38996 #define ENET_QOS_MAC_HW_FEAT_ADDR64(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDR64_MASK)
38997 
38998 #define ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK       (0x4000U)
38999 #define ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT      (14U)
39000 /*! TXCOESEL - Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit
39001  *    TCP/IP Checksum Insertion option is selected
39002  *  0b1..Transmit Checksum Offload Enable option is selected
39003  *  0b0..Transmit Checksum Offload Enable option is not selected
39004  */
39005 #define ENET_QOS_MAC_HW_FEAT_TXCOESEL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK)
39006 
39007 #define ENET_QOS_MAC_HW_FEAT_DCBEN_MASK          (0x10000U)
39008 #define ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT         (16U)
39009 /*! DCBEN - DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected
39010  *  0b1..DCB Feature is selected
39011  *  0b0..DCB Feature is not selected
39012  */
39013 #define ENET_QOS_MAC_HW_FEAT_DCBEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DCBEN_MASK)
39014 
39015 #define ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK         (0x10000U)
39016 #define ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT        (16U)
39017 /*! ESTSEL - Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable
39018  *    Enhancements to Scheduling Traffic feature is selected.
39019  *  0b1..Enable Enhancements to Scheduling Traffic feature is selected
39020  *  0b0..Enable Enhancements to Scheduling Traffic feature is not selected
39021  */
39022 #define ENET_QOS_MAC_HW_FEAT_ESTSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK)
39023 
39024 #define ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK       (0x10000U)
39025 #define ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT      (16U)
39026 /*! RXCOESEL - Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected
39027  *  0b1..Receive Checksum Offload Enable option is selected
39028  *  0b0..Receive Checksum Offload Enable option is not selected
39029  */
39030 #define ENET_QOS_MAC_HW_FEAT_RXCOESEL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK)
39031 
39032 #define ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK         (0xE0000U)
39033 #define ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT        (17U)
39034 /*! ESTDEP - Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5
39035  *  0b101..1024
39036  *  0b010..128
39037  *  0b011..256
39038  *  0b100..512
39039  *  0b001..64
39040  *  0b000..No Depth configured
39041  *  0b110..Reserved
39042  */
39043 #define ENET_QOS_MAC_HW_FEAT_ESTDEP(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK)
39044 
39045 #define ENET_QOS_MAC_HW_FEAT_SPHEN_MASK          (0x20000U)
39046 #define ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT         (17U)
39047 /*! SPHEN - Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected
39048  *  0b1..Split Header Feature is selected
39049  *  0b0..Split Header Feature is not selected
39050  */
39051 #define ENET_QOS_MAC_HW_FEAT_SPHEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPHEN_MASK)
39052 
39053 #define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK   (0x7C0000U)
39054 #define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT  (18U)
39055 /*! ADDMACADRSEL - MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is
39056  *    selected for Enable Additional 1-31 MAC Address Registers option
39057  */
39058 #define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK)
39059 
39060 #define ENET_QOS_MAC_HW_FEAT_TSOEN_MASK          (0x40000U)
39061 #define ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT         (18U)
39062 /*! TSOEN - TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation
39063  *    Offloading for TCP/IP Packets option is selected
39064  *  0b1..TCP Segmentation Offload Feature is selected
39065  *  0b0..TCP Segmentation Offload Feature is not selected
39066  */
39067 #define ENET_QOS_MAC_HW_FEAT_TSOEN(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSOEN_MASK)
39068 
39069 #define ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK        (0x3C0000U)
39070 #define ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT       (18U)
39071 /*! TXCHCNT - Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels:
39072  *  0b0000..1 MTL Tx Channel
39073  *  0b0001..2 MTL Tx Channels
39074  *  0b0010..3 MTL Tx Channels
39075  *  0b0011..4 MTL Tx Channels
39076  *  0b0100..5 MTL Tx Channels
39077  *  0b0101..Reserved
39078  *  0b0110..Reserved
39079  *  0b0111..Reserved
39080  */
39081 #define ENET_QOS_MAC_HW_FEAT_TXCHCNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK)
39082 
39083 #define ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK        (0x80000U)
39084 #define ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT       (19U)
39085 /*! DBGMEMA - DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected
39086  *  0b1..DMA Debug Registers option is selected
39087  *  0b0..DMA Debug Registers option is not selected
39088  */
39089 #define ENET_QOS_MAC_HW_FEAT_DBGMEMA(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK)
39090 
39091 #define ENET_QOS_MAC_HW_FEAT_AVSEL_MASK          (0x100000U)
39092 #define ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT         (20U)
39093 /*! AVSEL - AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected.
39094  *  0b1..AV Feature is selected
39095  *  0b0..AV Feature is not selected
39096  */
39097 #define ENET_QOS_MAC_HW_FEAT_AVSEL(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AVSEL_MASK)
39098 
39099 #define ENET_QOS_MAC_HW_FEAT_ESTWID_MASK         (0x300000U)
39100 #define ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT        (20U)
39101 /*! ESTWID - Width of the Time Interval field in the Gate Control List This field indicates the
39102  *    width of the Configured Time Interval Field
39103  *  0b00..Width not configured
39104  *  0b01..16
39105  *  0b10..20
39106  *  0b11..24
39107  */
39108 #define ENET_QOS_MAC_HW_FEAT_ESTWID(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTWID_MASK)
39109 
39110 #define ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK         (0x200000U)
39111 #define ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT        (21U)
39112 /*! RAVSEL - Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video
39113  *    Bridging option on Rx Side Only is selected.
39114  *  0b1..Rx Side Only AV Feature is selected
39115  *  0b0..Rx Side Only AV Feature is not selected
39116  */
39117 #define ENET_QOS_MAC_HW_FEAT_RAVSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK)
39118 
39119 #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK    (0x800000U)
39120 #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT   (23U)
39121 /*! MACADR32SEL - MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32
39122  *    MAC Address Registers (32-63) option is selected
39123  *  0b1..MAC Addresses 32-63 Select option is selected
39124  *  0b0..MAC Addresses 32-63 Select option is not selected
39125  */
39126 #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK)
39127 
39128 #define ENET_QOS_MAC_HW_FEAT_POUOST_MASK         (0x800000U)
39129 #define ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT        (23U)
39130 /*! POUOST - One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One
39131  *    step timestamp for PTP over UDP/IP feature is selected.
39132  *  0b1..One Step for PTP over UDP/IP Feature is selected
39133  *  0b0..One Step for PTP over UDP/IP Feature is not selected
39134  */
39135 #define ENET_QOS_MAC_HW_FEAT_POUOST(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT)) & ENET_QOS_MAC_HW_FEAT_POUOST_MASK)
39136 
39137 #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK      (0x3000000U)
39138 #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT     (24U)
39139 /*! HASHTBLSZ - Hash Table Size This field indicates the size of the hash table:
39140  *  0b10..128
39141  *  0b11..256
39142  *  0b01..64
39143  *  0b00..No hash table
39144  */
39145 #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK)
39146 
39147 #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK    (0x1000000U)
39148 #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT   (24U)
39149 /*! MACADR64SEL - MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64
39150  *    MAC Address Registers (64-127) option is selected
39151  *  0b1..MAC Addresses 64-127 Select option is selected
39152  *  0b0..MAC Addresses 64-127 Select option is not selected
39153  */
39154 #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK)
39155 
39156 #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK      (0x7000000U)
39157 #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT     (24U)
39158 /*! PPSOUTNUM - Number of PPS Outputs This field indicates the number of PPS outputs:
39159  *  0b001..1 PPS output
39160  *  0b010..2 PPS output
39161  *  0b011..3 PPS output
39162  *  0b100..4 PPS output
39163  *  0b000..No PPS output
39164  *  0b101..Reserved
39165  */
39166 #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK)
39167 
39168 #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK       (0x6000000U)
39169 #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT      (25U)
39170 /*! TSSTSSEL - Timestamp System Time Source This bit indicates the source of the Timestamp system
39171  *    time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected
39172  *  0b10..Both
39173  *  0b01..External
39174  *  0b00..Internal
39175  *  0b11..Reserved
39176  */
39177 #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK)
39178 
39179 #define ENET_QOS_MAC_HW_FEAT_FPESEL_MASK         (0x4000000U)
39180 #define ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT        (26U)
39181 /*! FPESEL - Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected.
39182  *  0b1..Frame Preemption Enable feature is selected
39183  *  0b0..Frame Preemption Enable feature is not selected
39184  */
39185 #define ENET_QOS_MAC_HW_FEAT_FPESEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FPESEL_MASK)
39186 
39187 #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK       (0x78000000U)
39188 #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT      (27U)
39189 /*! L3L4FNUM - Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters:
39190  *  0b0001..1 L3 or L4 Filter
39191  *  0b0010..2 L3 or L4 Filters
39192  *  0b0011..3 L3 or L4 Filters
39193  *  0b0100..4 L3 or L4 Filters
39194  *  0b0101..5 L3 or L4 Filters
39195  *  0b0110..6 L3 or L4 Filters
39196  *  0b0111..7 L3 or L4 Filters
39197  *  0b1000..8 L3 or L4 Filters
39198  *  0b0000..No L3 or L4 Filter
39199  */
39200 #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK)
39201 
39202 #define ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK      (0x8000000U)
39203 #define ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT     (27U)
39204 /*! SAVLANINS - Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and
39205  *    VLAN Insertion on Tx option is selected
39206  *  0b1..Source Address or VLAN Insertion Enable option is selected
39207  *  0b0..Source Address or VLAN Insertion Enable option is not selected
39208  */
39209 #define ENET_QOS_MAC_HW_FEAT_SAVLANINS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK)
39210 
39211 #define ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK         (0x8000000U)
39212 #define ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT        (27U)
39213 /*! TBSSEL - Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected.
39214  *  0b1..Time Based Scheduling Enable feature is selected
39215  *  0b0..Time Based Scheduling Enable feature is not selected
39216  */
39217 #define ENET_QOS_MAC_HW_FEAT_TBSSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK)
39218 
39219 #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK      (0x70000000U)
39220 #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT     (28U)
39221 /*! ACTPHYSEL - Active PHY Selected When you have multiple PHY interfaces in your configuration,
39222  *    this field indicates the sampled value of phy_intf_sel_i during reset de-assertion.
39223  *  0b000..GMII or MII
39224  *  0b111..RevMII
39225  *  0b001..RGMII
39226  *  0b100..RMII
39227  *  0b101..RTBI
39228  *  0b010..SGMII
39229  *  0b110..SMII
39230  *  0b011..TBI
39231  */
39232 #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK)
39233 
39234 #define ENET_QOS_MAC_HW_FEAT_ASP_MASK            (0x30000000U)
39235 #define ENET_QOS_MAC_HW_FEAT_ASP_SHIFT           (28U)
39236 /*! ASP - Automotive Safety Package Following are the encoding for the different Safety features
39237  *  0b10..All the Automotive Safety features are selected without the "Parity Port Enable for external interface" feature
39238  *  0b11..All the Automotive Safety features are selected with the "Parity Port Enable for external interface" feature
39239  *  0b01..Only "ECC protection for external memory" feature is selected
39240  *  0b00..No Safety features selected
39241  */
39242 #define ENET_QOS_MAC_HW_FEAT_ASP(x)              (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ASP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ASP_MASK)
39243 
39244 #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK     (0x70000000U)
39245 #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT    (28U)
39246 /*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs:
39247  *  0b001..1 auxiliary input
39248  *  0b010..2 auxiliary input
39249  *  0b011..3 auxiliary input
39250  *  0b100..4 auxiliary input
39251  *  0b000..No auxiliary input
39252  *  0b101..Reserved
39253  */
39254 #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK)
39255 /*! @} */
39256 
39257 /* The count of ENET_QOS_MAC_HW_FEAT */
39258 #define ENET_QOS_MAC_HW_FEAT_COUNT               (4U)
39259 
39260 /*! @name MAC_MDIO_ADDRESS - MDIO Address */
39261 /*! @{ */
39262 
39263 #define ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK        (0x1U)
39264 #define ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT       (0U)
39265 /*! GB - GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave.
39266  *  0b0..GMII Busy is disabled
39267  *  0b1..GMII Busy is enabled
39268  */
39269 #define ENET_QOS_MAC_MDIO_ADDRESS_GB(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK)
39270 
39271 #define ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK      (0x2U)
39272 #define ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT     (1U)
39273 /*! C45E - Clause 45 PHY Enable When this bit is set, Clause 45 capable PHY is connected to MDIO.
39274  *  0b0..Clause 45 PHY is disabled
39275  *  0b1..Clause 45 PHY is enabled
39276  */
39277 #define ENET_QOS_MAC_MDIO_ADDRESS_C45E(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK)
39278 
39279 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK     (0x4U)
39280 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT    (2U)
39281 /*! GOC_0 - GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII.
39282  *  0b0..GMII Operation Command 0 is disabled
39283  *  0b1..GMII Operation Command 0 is enabled
39284  */
39285 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK)
39286 
39287 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK     (0x8U)
39288 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT    (3U)
39289 /*! GOC_1 - GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or
39290  *    RevMII, GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read
39291  *    Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY or RevMII is enabled, only Write
39292  *    and Read commands are valid.
39293  *  0b0..GMII Operation Command 1 is disabled
39294  *  0b1..GMII Operation Command 1 is enabled
39295  */
39296 #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK)
39297 
39298 #define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK      (0x10U)
39299 #define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT     (4U)
39300 /*! SKAP - Skip Address Packet When this bit is set, the SMA does not send the address packets
39301  *    before read, write, or post-read increment address packets.
39302  *  0b0..Skip Address Packet is disabled
39303  *  0b1..Skip Address Packet is enabled
39304  */
39305 #define ENET_QOS_MAC_MDIO_ADDRESS_SKAP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK)
39306 
39307 #define ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK        (0xF00U)
39308 #define ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT       (8U)
39309 /*! CR - CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock
39310  *    according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC
39311  *    clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR clock/62 - 0010: CSR clock
39312  *    = 20-35 MHz; MDC clock = CSR clock/16 - 0011: CSR clock = 35-60 MHz; MDC clock = CSR clock/26
39313  *    - 0100: CSR clock = 150-250 MHz; MDC clock = CSR clock/102 - 0101: CSR clock = 250-300 MHz;
39314  *    MDC clock = CSR clock/124 - 0110: CSR clock = 300-500 MHz; MDC clock = CSR clock/204 - 0111: CSR
39315  *    clock = 500-800 MHz; MDC clock = CSR clock/324 The suggested range of CSR clock frequency
39316  *    applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1.
39317  */
39318 #define ENET_QOS_MAC_MDIO_ADDRESS_CR(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK)
39319 
39320 #define ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK       (0x7000U)
39321 #define ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT      (12U)
39322 /*! NTC - Number of Trailing Clocks This field controls the number of trailing clock cycles
39323  *    generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame.
39324  */
39325 #define ENET_QOS_MAC_MDIO_ADDRESS_NTC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK)
39326 
39327 #define ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK       (0x1F0000U)
39328 #define ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT      (16U)
39329 /*! RDA - Register/Device Address These bits select the PHY register in selected Clause 22 PHY device. */
39330 #define ENET_QOS_MAC_MDIO_ADDRESS_RDA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK)
39331 
39332 #define ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK        (0x3E00000U)
39333 #define ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT       (21U)
39334 /*! PA - Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing. */
39335 #define ENET_QOS_MAC_MDIO_ADDRESS_PA(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK)
39336 
39337 #define ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK       (0x4000000U)
39338 #define ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT      (26U)
39339 /*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then
39340  *    the MAC informs the completion of a read or write command at the end of frame transfer (before
39341  *    the trailing clocks are transmitted).
39342  *  0b0..Back to Back transactions disabled
39343  *  0b1..Back to Back transactions enabled
39344  */
39345 #define ENET_QOS_MAC_MDIO_ADDRESS_BTB(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK)
39346 
39347 #define ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK       (0x8000000U)
39348 #define ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT      (27U)
39349 /*! PSE - Preamble Suppression Enable When this bit is set, the SMA suppresses the 32-bit preamble
39350  *    and transmits MDIO frames with only 1 preamble bit.
39351  *  0b0..Preamble Suppression disabled
39352  *  0b1..Preamble Suppression enabled
39353  */
39354 #define ENET_QOS_MAC_MDIO_ADDRESS_PSE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK)
39355 /*! @} */
39356 
39357 /*! @name MAC_MDIO_DATA - MAC MDIO Data */
39358 /*! @{ */
39359 
39360 #define ENET_QOS_MAC_MDIO_DATA_GD_MASK           (0xFFFFU)
39361 #define ENET_QOS_MAC_MDIO_DATA_GD_SHIFT          (0U)
39362 /*! GD - GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a
39363  *    Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a
39364  *    Management Write operation.
39365  */
39366 #define ENET_QOS_MAC_MDIO_DATA_GD(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_GD_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_GD_MASK)
39367 
39368 #define ENET_QOS_MAC_MDIO_DATA_RA_MASK           (0xFFFF0000U)
39369 #define ENET_QOS_MAC_MDIO_DATA_RA_SHIFT          (16U)
39370 /*! RA - Register Address This field is valid only when C45E is set. */
39371 #define ENET_QOS_MAC_MDIO_DATA_RA(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_RA_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_RA_MASK)
39372 /*! @} */
39373 
39374 /*! @name MAC_CSR_SW_CTRL - CSR Software Control */
39375 /*! @{ */
39376 
39377 #define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK       (0x1U)
39378 #define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT      (0U)
39379 /*! RCWE - Register Clear on Write 1 Enable When this bit is set, the access mode of some register
39380  *    fields changes to Clear on Write 1, the application needs to set that respective bit to 1 to
39381  *    clear it.
39382  *  0b0..Register Clear on Write 1 is disabled
39383  *  0b1..Register Clear on Write 1 is enabled
39384  */
39385 #define ENET_QOS_MAC_CSR_SW_CTRL_RCWE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT)) & ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK)
39386 /*! @} */
39387 
39388 /*! @name MAC_FPE_CTRL_STS - Frame Preemption Control */
39389 /*! @{ */
39390 
39391 #define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK      (0x1U)
39392 #define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT     (0U)
39393 /*! EFPE - Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled.
39394  *  0b0..Tx Frame Preemption is disabled
39395  *  0b1..Tx Frame Preemption is enabled
39396  */
39397 #define ENET_QOS_MAC_FPE_CTRL_STS_EFPE(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK)
39398 
39399 #define ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK      (0x2U)
39400 #define ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT     (1U)
39401 /*! SVER - Send Verify mPacket When set indicates hardware to send a verify mPacket.
39402  *  0b0..Send Verify mPacket is disabled
39403  *  0b1..Send Verify mPacket is enabled
39404  */
39405 #define ENET_QOS_MAC_FPE_CTRL_STS_SVER(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK)
39406 
39407 #define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK      (0x4U)
39408 #define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT     (2U)
39409 /*! SRSP - Send Respond mPacket When set indicates hardware to send a Respond mPacket.
39410  *  0b0..Send Respond mPacket is disabled
39411  *  0b1..Send Respond mPacket is enabled
39412  */
39413 #define ENET_QOS_MAC_FPE_CTRL_STS_SRSP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK)
39414 
39415 #define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK  (0x8U)
39416 #define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT (3U)
39417 /*! S1_SET_0 - Synopsys Reserved, Must be set to "0". */
39418 #define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK)
39419 
39420 #define ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK      (0x10000U)
39421 #define ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT     (16U)
39422 /*! RVER - Received Verify Frame Set when a Verify mPacket is received.
39423  *  0b1..Received Verify Frame
39424  *  0b0..Not received Verify Frame
39425  */
39426 #define ENET_QOS_MAC_FPE_CTRL_STS_RVER(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK)
39427 
39428 #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK      (0x20000U)
39429 #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT     (17U)
39430 /*! RRSP - Received Respond Frame Set when a Respond mPacket is received.
39431  *  0b1..Received Respond Frame
39432  *  0b0..Not received Respond Frame
39433  */
39434 #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK)
39435 
39436 #define ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK      (0x40000U)
39437 #define ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT     (18U)
39438 /*! TVER - Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field).
39439  *  0b1..transmitted Verify Frame
39440  *  0b0..Not transmitted Verify Frame
39441  */
39442 #define ENET_QOS_MAC_FPE_CTRL_STS_TVER(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK)
39443 
39444 #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK      (0x80000U)
39445 #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT     (19U)
39446 /*! TRSP - Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field).
39447  *  0b1..transmitted Respond Frame
39448  *  0b0..Not transmitted Respond Frame
39449  */
39450 #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK)
39451 /*! @} */
39452 
39453 /*! @name MAC_PRESN_TIME_NS - 32-bit Binary Rollover Equivalent Time */
39454 /*! @{ */
39455 
39456 #define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK     (0xFFFFFFFFU)
39457 #define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT    (0U)
39458 /*! MPTN - MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary
39459  *    rollover equivalent time of the PTP System Time in ns
39460  */
39461 #define ENET_QOS_MAC_PRESN_TIME_NS_MPTN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK)
39462 /*! @} */
39463 
39464 /*! @name MAC_PRESN_TIME_UPDT - MAC 1722 Presentation Time */
39465 /*! @{ */
39466 
39467 #define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK   (0xFFFFFFFFU)
39468 #define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT  (0U)
39469 /*! MPTU - MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time. */
39470 #define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK)
39471 /*! @} */
39472 
39473 /*! @name HIGH - MAC Address0 High..MAC Address63 High */
39474 /*! @{ */
39475 
39476 #define ENET_QOS_HIGH_ADDRHI_MASK                (0xFFFFU)
39477 #define ENET_QOS_HIGH_ADDRHI_SHIFT               (0U)
39478 /*! ADDRHI - MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. */
39479 #define ENET_QOS_HIGH_ADDRHI(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_ADDRHI_SHIFT)) & ENET_QOS_HIGH_ADDRHI_MASK)
39480 
39481 #define ENET_QOS_HIGH_DCS_MASK                   (0x1F0000U)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
39482 #define ENET_QOS_HIGH_DCS_SHIFT                  (16U)
39483 /*! DCS - DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field
39484  *    contains the binary representation of the DMA Channel number to which an Rx packet whose DA
39485  *    matches the MAC Address(#i) content is routed.
39486  */
39487 #define ENET_QOS_HIGH_DCS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_DCS_SHIFT)) & ENET_QOS_HIGH_DCS_MASK)  /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
39488 
39489 #define ENET_QOS_HIGH_MBC_MASK                   (0x3F000000U)
39490 #define ENET_QOS_HIGH_MBC_SHIFT                  (24U)
39491 /*! MBC - Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. */
39492 #define ENET_QOS_HIGH_MBC(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_MBC_SHIFT)) & ENET_QOS_HIGH_MBC_MASK)
39493 
39494 #define ENET_QOS_HIGH_SA_MASK                    (0x40000000U)
39495 #define ENET_QOS_HIGH_SA_SHIFT                   (30U)
39496 /*! SA - Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA
39497  *    fields of the received packet.
39498  *  0b0..Compare with Destination Address
39499  *  0b1..Compare with Source Address
39500  */
39501 #define ENET_QOS_HIGH_SA(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_SA_SHIFT)) & ENET_QOS_HIGH_SA_MASK)
39502 
39503 #define ENET_QOS_HIGH_AE_MASK                    (0x80000000U)
39504 #define ENET_QOS_HIGH_AE_SHIFT                   (31U)
39505 /*! AE - Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering.
39506  *  0b0..INVALID : This bit must be always set to 1
39507  *  0b1..This bit is always set to 1
39508  */
39509 #define ENET_QOS_HIGH_AE(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_AE_SHIFT)) & ENET_QOS_HIGH_AE_MASK)
39510 /*! @} */
39511 
39512 /* The count of ENET_QOS_HIGH */
39513 #define ENET_QOS_HIGH_COUNT                      (64U)
39514 
39515 /*! @name LOW - MAC Address0 Low..MAC Address63 Low */
39516 /*! @{ */
39517 
39518 #define ENET_QOS_LOW_ADDRLO_MASK                 (0xFFFFFFFFU)
39519 #define ENET_QOS_LOW_ADDRLO_SHIFT                (0U)
39520 /*! ADDRLO - MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. */
39521 #define ENET_QOS_LOW_ADDRLO(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_LOW_ADDRLO_SHIFT)) & ENET_QOS_LOW_ADDRLO_MASK)
39522 /*! @} */
39523 
39524 /* The count of ENET_QOS_LOW */
39525 #define ENET_QOS_LOW_COUNT                       (64U)
39526 
39527 /*! @name MAC_MMC_CONTROL - MMC Control */
39528 /*! @{ */
39529 
39530 #define ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK     (0x1U)
39531 #define ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT    (0U)
39532 /*! CNTRST - Counters Reset When this bit is set, all counters are reset.
39533  *  0b0..Counters are not reset
39534  *  0b1..All counters are reset
39535  */
39536 #define ENET_QOS_MAC_MMC_CONTROL_CNTRST(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK)
39537 
39538 #define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK  (0x2U)
39539 #define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT (1U)
39540 /*! CNTSTOPRO - Counter Stop Rollover When this bit is set, the counter does not roll over to zero after reaching the maximum value.
39541  *  0b0..Counter Stop Rollover is disabled
39542  *  0b1..Counter Stop Rollover is enabled
39543  */
39544 #define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK)
39545 
39546 #define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK    (0x4U)
39547 #define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT   (2U)
39548 /*! RSTONRD - Reset on Read When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset).
39549  *  0b0..Reset on Read is disabled
39550  *  0b1..Reset on Read is enabled
39551  */
39552 #define ENET_QOS_MAC_MMC_CONTROL_RSTONRD(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK)
39553 
39554 #define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK   (0x8U)
39555 #define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT  (3U)
39556 /*! CNTFREEZ - MMC Counter Freeze When this bit is set, it freezes all MMC counters to their current value.
39557  *  0b0..MMC Counter Freeze is disabled
39558  *  0b1..MMC Counter Freeze is enabled
39559  */
39560 #define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK)
39561 
39562 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK    (0x10U)
39563 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT   (4U)
39564 /*! CNTPRST - Counters Preset When this bit is set, all counters are initialized or preset to almost
39565  *    full or almost half according to the CNTPRSTLVL bit.
39566  *  0b0..Counters Preset is disabled
39567  *  0b1..Counters Preset is enabled
39568  */
39569 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRST(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK)
39570 
39571 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK (0x20U)
39572 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT (5U)
39573 /*! CNTPRSTLVL - Full-Half Preset When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value.
39574  *  0b0..Full-Half Preset is disabled
39575  *  0b1..Full-Half Preset is enabled
39576  */
39577 #define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK)
39578 
39579 #define ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK      (0x100U)
39580 #define ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT     (8U)
39581 /*! UCDBC - Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit.
39582  *  0b0..Update MMC Counters for Dropped Broadcast Packets is disabled
39583  *  0b1..Update MMC Counters for Dropped Broadcast Packets is enabled
39584  */
39585 #define ENET_QOS_MAC_MMC_CONTROL_UCDBC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK)
39586 /*! @} */
39587 
39588 /*! @name MAC_MMC_RX_INTERRUPT - MMC Rx Interrupt */
39589 /*! @{ */
39590 
39591 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK (0x1U)
39592 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT (0U)
39593 /*! RXGBPKTIS - MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the
39594  *    rxpacketcount_gb counter reaches half of the maximum value or the maximum value.
39595  *  0b1..MMC Receive Good Bad Packet Counter Interrupt Status detected
39596  *  0b0..MMC Receive Good Bad Packet Counter Interrupt Status not detected
39597  */
39598 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK)
39599 
39600 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK (0x2U)
39601 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT (1U)
39602 /*! RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the
39603  *    rxoctetcount_gb counter reaches half of the maximum value or the maximum value.
39604  *  0b1..MMC Receive Good Bad Octet Counter Interrupt Status detected
39605  *  0b0..MMC Receive Good Bad Octet Counter Interrupt Status not detected
39606  */
39607 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK)
39608 
39609 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK (0x4U)
39610 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT (2U)
39611 /*! RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status This bit is set when the
39612  *    rxoctetcount_g counter reaches half of the maximum value or the maximum value.
39613  *  0b1..MMC Receive Good Octet Counter Interrupt Status detected
39614  *  0b0..MMC Receive Good Octet Counter Interrupt Status not detected
39615  */
39616 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK)
39617 
39618 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK (0x8U)
39619 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT (3U)
39620 /*! RXBCGPIS - MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the
39621  *    rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value.
39622  *  0b1..MMC Receive Broadcast Good Packet Counter Interrupt Status detected
39623  *  0b0..MMC Receive Broadcast Good Packet Counter Interrupt Status not detected
39624  */
39625 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK)
39626 
39627 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK (0x10U)
39628 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT (4U)
39629 /*! RXMCGPIS - MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the
39630  *    rxmulticastpackets_g counter reaches half of the maximum value or the maximum value.
39631  *  0b1..MMC Receive Multicast Good Packet Counter Interrupt Status detected
39632  *  0b0..MMC Receive Multicast Good Packet Counter Interrupt Status not detected
39633  */
39634 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK)
39635 
39636 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK (0x20U)
39637 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT (5U)
39638 /*! RXCRCERPIS - MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the
39639  *    rxcrcerror counter reaches half of the maximum value or the maximum value.
39640  *  0b1..MMC Receive CRC Error Packet Counter Interrupt Status detected
39641  *  0b0..MMC Receive CRC Error Packet Counter Interrupt Status not detected
39642  */
39643 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK)
39644 
39645 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK (0x40U)
39646 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT (6U)
39647 /*! RXALGNERPIS - MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when
39648  *    the rxalignmenterror counter reaches half of the maximum value or the maximum value.
39649  *  0b1..MMC Receive Alignment Error Packet Counter Interrupt Status detected
39650  *  0b0..MMC Receive Alignment Error Packet Counter Interrupt Status not detected
39651  */
39652 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK)
39653 
39654 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK (0x80U)
39655 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT (7U)
39656 /*! RXRUNTPIS - MMC Receive Runt Packet Counter Interrupt Status This bit is set when the
39657  *    rxrunterror counter reaches half of the maximum value or the maximum value.
39658  *  0b1..MMC Receive Runt Packet Counter Interrupt Status detected
39659  *  0b0..MMC Receive Runt Packet Counter Interrupt Status not detected
39660  */
39661 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK)
39662 
39663 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK (0x100U)
39664 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT (8U)
39665 /*! RXJABERPIS - MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the
39666  *    rxjabbererror counter reaches half of the maximum value or the maximum value.
39667  *  0b1..MMC Receive Jabber Error Packet Counter Interrupt Status detected
39668  *  0b0..MMC Receive Jabber Error Packet Counter Interrupt Status not detected
39669  */
39670 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK)
39671 
39672 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK (0x200U)
39673 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT (9U)
39674 /*! RXUSIZEGPIS - MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when
39675  *    the rxundersize_g counter reaches half of the maximum value or the maximum value.
39676  *  0b1..MMC Receive Undersize Good Packet Counter Interrupt Status detected
39677  *  0b0..MMC Receive Undersize Good Packet Counter Interrupt Status not detected
39678  */
39679 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK)
39680 
39681 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK (0x400U)
39682 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT (10U)
39683 /*! RXOSIZEGPIS - MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the
39684  *    rxoversize_g counter reaches half of the maximum value or the maximum value.
39685  *  0b1..MMC Receive Oversize Good Packet Counter Interrupt Status detected
39686  *  0b0..MMC Receive Oversize Good Packet Counter Interrupt Status not detected
39687  */
39688 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK)
39689 
39690 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK (0x800U)
39691 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT (11U)
39692 /*! RX64OCTGBPIS - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set
39693  *    when the rx64octets_gb counter reaches half of the maximum value or the maximum value.
39694  *  0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status detected
39695  *  0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status not detected
39696  */
39697 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK)
39698 
39699 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK (0x1000U)
39700 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT (12U)
39701 /*! RX65T127OCTGBPIS - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit
39702  *    is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum
39703  *    value.
39704  *  0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected
39705  *  0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected
39706  */
39707 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK)
39708 
39709 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK (0x2000U)
39710 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT (13U)
39711 /*! RX128T255OCTGBPIS - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This
39712  *    bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the
39713  *    maximum value.
39714  *  0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected
39715  *  0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected
39716  */
39717 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK)
39718 
39719 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK (0x4000U)
39720 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT (14U)
39721 /*! RX256T511OCTGBPIS - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This
39722  *    bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the
39723  *    maximum value.
39724  *  0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected
39725  *  0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected
39726  */
39727 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK)
39728 
39729 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK (0x8000U)
39730 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT (15U)
39731 /*! RX512T1023OCTGBPIS - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This
39732  *    bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the
39733  *    maximum value.
39734  *  0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected
39735  *  0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected
39736  */
39737 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK)
39738 
39739 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK (0x10000U)
39740 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT (16U)
39741 /*! RX1024TMAXOCTGBPIS - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status
39742  *    This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the
39743  *    maximum value.
39744  *  0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected
39745  *  0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected
39746  */
39747 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK)
39748 
39749 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK (0x20000U)
39750 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT (17U)
39751 /*! RXUCGPIS - MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the
39752  *    rxunicastpackets_g counter reaches half of the maximum value or the maximum value.
39753  *  0b1..MMC Receive Unicast Good Packet Counter Interrupt Status detected
39754  *  0b0..MMC Receive Unicast Good Packet Counter Interrupt Status not detected
39755  */
39756 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK)
39757 
39758 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK (0x40000U)
39759 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT (18U)
39760 /*! RXLENERPIS - MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the
39761  *    rxlengtherror counter reaches half of the maximum value or the maximum value.
39762  *  0b1..MMC Receive Length Error Packet Counter Interrupt Status detected
39763  *  0b0..MMC Receive Length Error Packet Counter Interrupt Status not detected
39764  */
39765 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK)
39766 
39767 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK (0x80000U)
39768 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT (19U)
39769 /*! RXORANGEPIS - MMC Receive Out Of Range Error Packet Counter Interrupt Status.
39770  *  0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Status detected
39771  *  0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Status not detected
39772  */
39773 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK)
39774 
39775 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK (0x100000U)
39776 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT (20U)
39777 /*! RXPAUSPIS - MMC Receive Pause Packet Counter Interrupt Status This bit is set when the
39778  *    rxpausepackets counter reaches half of the maximum value or the maximum value.
39779  *  0b1..MMC Receive Pause Packet Counter Interrupt Status detected
39780  *  0b0..MMC Receive Pause Packet Counter Interrupt Status not detected
39781  */
39782 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK)
39783 
39784 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK (0x200000U)
39785 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT (21U)
39786 /*! RXFOVPIS - MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the
39787  *    rxfifooverflow counter reaches half of the maximum value or the maximum value.
39788  *  0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Status detected
39789  *  0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Status not detected
39790  */
39791 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK)
39792 
39793 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK (0x400000U)
39794 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT (22U)
39795 /*! RXVLANGBPIS - MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the
39796  *    rxvlanpackets_gb counter reaches half of the maximum value or the maximum value.
39797  *  0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Status detected
39798  *  0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Status not detected
39799  */
39800 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK)
39801 
39802 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK (0x800000U)
39803 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT (23U)
39804 /*! RXWDOGPIS - MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the
39805  *    rxwatchdog error counter reaches half of the maximum value or the maximum value.
39806  *  0b1..MMC Receive Watchdog Error Packet Counter Interrupt Status detected
39807  *  0b0..MMC Receive Watchdog Error Packet Counter Interrupt Status not detected
39808  */
39809 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK)
39810 
39811 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK (0x1000000U)
39812 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT (24U)
39813 /*! RXRCVERRPIS - MMC Receive Error Packet Counter Interrupt Status This bit is set when the
39814  *    rxrcverror counter reaches half of the maximum value or the maximum value.
39815  *  0b1..MMC Receive Error Packet Counter Interrupt Status detected
39816  *  0b0..MMC Receive Error Packet Counter Interrupt Status not detected
39817  */
39818 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK)
39819 
39820 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK (0x2000000U)
39821 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT (25U)
39822 /*! RXCTRLPIS - MMC Receive Control Packet Counter Interrupt Status This bit is set when the
39823  *    rxctrlpackets_g counter reaches half of the maximum value or the maximum value.
39824  *  0b1..MMC Receive Control Packet Counter Interrupt Status detected
39825  *  0b0..MMC Receive Control Packet Counter Interrupt Status not detected
39826  */
39827 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK)
39828 
39829 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK (0x4000000U)
39830 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT (26U)
39831 /*! RXLPIUSCIS - MMC Receive LPI microsecond counter interrupt status This bit is set when the
39832  *    Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
39833  *  0b1..MMC Receive LPI microsecond Counter Interrupt Status detected
39834  *  0b0..MMC Receive LPI microsecond Counter Interrupt Status not detected
39835  */
39836 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK)
39837 
39838 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK (0x8000000U)
39839 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT (27U)
39840 /*! RXLPITRCIS - MMC Receive LPI transition counter interrupt status This bit is set when the
39841  *    Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
39842  *  0b1..MMC Receive LPI transition Counter Interrupt Status detected
39843  *  0b0..MMC Receive LPI transition Counter Interrupt Status not detected
39844  */
39845 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK)
39846 /*! @} */
39847 
39848 /*! @name MAC_MMC_TX_INTERRUPT - MMC Tx Interrupt */
39849 /*! @{ */
39850 
39851 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK (0x1U)
39852 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT (0U)
39853 /*! TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the
39854  *    txoctetcount_gb counter reaches half of the maximum value or the maximum value.
39855  *  0b1..MMC Transmit Good Bad Octet Counter Interrupt Status detected
39856  *  0b0..MMC Transmit Good Bad Octet Counter Interrupt Status not detected
39857  */
39858 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK)
39859 
39860 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK (0x2U)
39861 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT (1U)
39862 /*! TXGBPKTIS - MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the
39863  *    txpacketcount_gb counter reaches half of the maximum value or the maximum value.
39864  *  0b1..MMC Transmit Good Bad Packet Counter Interrupt Status detected
39865  *  0b0..MMC Transmit Good Bad Packet Counter Interrupt Status not detected
39866  */
39867 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK)
39868 
39869 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK (0x4U)
39870 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT (2U)
39871 /*! TXBCGPIS - MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the
39872  *    txbroadcastpackets_g counter reaches half of the maximum value or the maximum value.
39873  *  0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Status detected
39874  *  0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Status not detected
39875  */
39876 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK)
39877 
39878 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK (0x8U)
39879 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT (3U)
39880 /*! TXMCGPIS - MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the
39881  *    txmulticastpackets_g counter reaches half of the maximum value or the maximum value.
39882  *  0b1..MMC Transmit Multicast Good Packet Counter Interrupt Status detected
39883  *  0b0..MMC Transmit Multicast Good Packet Counter Interrupt Status not detected
39884  */
39885 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK)
39886 
39887 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK (0x10U)
39888 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT (4U)
39889 /*! TX64OCTGBPIS - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set
39890  *    when the tx64octets_gb counter reaches half of the maximum value or the maximum value.
39891  *  0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status detected
39892  *  0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status not detected
39893  */
39894 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK)
39895 
39896 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK (0x20U)
39897 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT (5U)
39898 /*! TX65T127OCTGBPIS - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This
39899  *    bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it
39900  *    reaches the maximum value.
39901  *  0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected
39902  *  0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected
39903  */
39904 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK)
39905 
39906 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK (0x40U)
39907 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT (6U)
39908 /*! TX128T255OCTGBPIS - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This
39909  *    bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the
39910  *    maximum value.
39911  *  0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected
39912  *  0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected
39913  */
39914 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK)
39915 
39916 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK (0x80U)
39917 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT (7U)
39918 /*! TX256T511OCTGBPIS - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This
39919  *    bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the
39920  *    maximum value.
39921  *  0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected
39922  *  0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected
39923  */
39924 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK)
39925 
39926 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK (0x100U)
39927 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT (8U)
39928 /*! TX512T1023OCTGBPIS - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status
39929  *    This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the
39930  *    maximum value.
39931  *  0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected
39932  *  0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected
39933  */
39934 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK)
39935 
39936 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK (0x200U)
39937 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT (9U)
39938 /*! TX1024TMAXOCTGBPIS - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status
39939  *    This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or
39940  *    the maximum value.
39941  *  0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected
39942  *  0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected
39943  */
39944 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK)
39945 
39946 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK (0x400U)
39947 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT (10U)
39948 /*! TXUCGBPIS - MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when
39949  *    the txunicastpackets_gb counter reaches half of the maximum value or the maximum value.
39950  *  0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status detected
39951  *  0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status not detected
39952  */
39953 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK)
39954 
39955 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK (0x800U)
39956 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT (11U)
39957 /*! TXMCGBPIS - MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when
39958  *    the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value.
39959  *  0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status detected
39960  *  0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status not detected
39961  */
39962 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK)
39963 
39964 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK (0x1000U)
39965 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT (12U)
39966 /*! TXBCGBPIS - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when
39967  *    the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value.
39968  *  0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status detected
39969  *  0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status not detected
39970  */
39971 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK)
39972 
39973 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK (0x2000U)
39974 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT (13U)
39975 /*! TXUFLOWERPIS - MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when
39976  *    the txunderflowerror counter reaches half of the maximum value or the maximum value.
39977  *  0b1..MMC Transmit Underflow Error Packet Counter Interrupt Status detected
39978  *  0b0..MMC Transmit Underflow Error Packet Counter Interrupt Status not detected
39979  */
39980 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK)
39981 
39982 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK (0x4000U)
39983 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT (14U)
39984 /*! TXSCOLGPIS - MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set
39985  *    when the txsinglecol_g counter reaches half of the maximum value or the maximum value.
39986  *  0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Status detected
39987  *  0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Status not detected
39988  */
39989 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK)
39990 
39991 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK (0x8000U)
39992 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT (15U)
39993 /*! TXMCOLGPIS - MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is
39994  *    set when the txmulticol_g counter reaches half of the maximum value or the maximum value.
39995  *  0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status detected
39996  *  0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status not detected
39997  */
39998 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK)
39999 
40000 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK (0x10000U)
40001 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT (16U)
40002 /*! TXDEFPIS - MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the
40003  *    txdeferred counter reaches half of the maximum value or the maximum value.
40004  *  0b1..MMC Transmit Deferred Packet Counter Interrupt Status detected
40005  *  0b0..MMC Transmit Deferred Packet Counter Interrupt Status not detected
40006  */
40007 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK)
40008 
40009 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK (0x20000U)
40010 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT (17U)
40011 /*! TXLATCOLPIS - MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when
40012  *    the txlatecol counter reaches half of the maximum value or the maximum value.
40013  *  0b1..MMC Transmit Late Collision Packet Counter Interrupt Status detected
40014  *  0b0..MMC Transmit Late Collision Packet Counter Interrupt Status not detected
40015  */
40016 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK)
40017 
40018 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK (0x40000U)
40019 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT (18U)
40020 /*! TXEXCOLPIS - MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set
40021  *    when the txexesscol counter reaches half of the maximum value or the maximum value.
40022  *  0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Status detected
40023  *  0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Status not detected
40024  */
40025 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK)
40026 
40027 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK (0x80000U)
40028 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT (19U)
40029 /*! TXCARERPIS - MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the
40030  *    txcarriererror counter reaches half of the maximum value or the maximum value.
40031  *  0b1..MMC Transmit Carrier Error Packet Counter Interrupt Status detected
40032  *  0b0..MMC Transmit Carrier Error Packet Counter Interrupt Status not detected
40033  */
40034 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK)
40035 
40036 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK (0x100000U)
40037 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT (20U)
40038 /*! TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status This bit is set when the
40039  *    txoctetcount_g counter reaches half of the maximum value or the maximum value.
40040  *  0b1..MMC Transmit Good Octet Counter Interrupt Status detected
40041  *  0b0..MMC Transmit Good Octet Counter Interrupt Status not detected
40042  */
40043 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK)
40044 
40045 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK (0x200000U)
40046 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT (21U)
40047 /*! TXGPKTIS - MMC Transmit Good Packet Counter Interrupt Status This bit is set when the
40048  *    txpacketcount_g counter reaches half of the maximum value or the maximum value.
40049  *  0b1..MMC Transmit Good Packet Counter Interrupt Status detected
40050  *  0b0..MMC Transmit Good Packet Counter Interrupt Status not detected
40051  */
40052 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK)
40053 
40054 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK (0x400000U)
40055 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT (22U)
40056 /*! TXEXDEFPIS - MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set
40057  *    when the txexcessdef counter reaches half of the maximum value or the maximum value.
40058  *  0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Status detected
40059  *  0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Status not detected
40060  */
40061 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK)
40062 
40063 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK (0x800000U)
40064 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT (23U)
40065 /*! TXPAUSPIS - MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the
40066  *    txpausepacketserror counter reaches half of the maximum value or the maximum value.
40067  *  0b1..MMC Transmit Pause Packet Counter Interrupt Status detected
40068  *  0b0..MMC Transmit Pause Packet Counter Interrupt Status not detected
40069  */
40070 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK)
40071 
40072 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK (0x1000000U)
40073 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT (24U)
40074 /*! TXVLANGPIS - MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the
40075  *    txvlanpackets_g counter reaches half of the maximum value or the maximum value.
40076  *  0b1..MMC Transmit VLAN Good Packet Counter Interrupt Status detected
40077  *  0b0..MMC Transmit VLAN Good Packet Counter Interrupt Status not detected
40078  */
40079 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK)
40080 
40081 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK (0x2000000U)
40082 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT (25U)
40083 /*! TXOSIZEGPIS - MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when
40084  *    the txoversize_g counter reaches half of the maximum value or the maximum value.
40085  *  0b1..MMC Transmit Oversize Good Packet Counter Interrupt Status detected
40086  *  0b0..MMC Transmit Oversize Good Packet Counter Interrupt Status not detected
40087  */
40088 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK)
40089 
40090 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK (0x4000000U)
40091 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT (26U)
40092 /*! TXLPIUSCIS - MMC Transmit LPI microsecond counter interrupt status This bit is set when the
40093  *    Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
40094  *  0b1..MMC Transmit LPI microsecond Counter Interrupt Status detected
40095  *  0b0..MMC Transmit LPI microsecond Counter Interrupt Status not detected
40096  */
40097 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK)
40098 
40099 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK (0x8000000U)
40100 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT (27U)
40101 /*! TXLPITRCIS - MMC Transmit LPI transition counter interrupt status This bit is set when the
40102  *    Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
40103  *  0b1..MMC Transmit LPI transition Counter Interrupt Status detected
40104  *  0b0..MMC Transmit LPI transition Counter Interrupt Status not detected
40105  */
40106 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK)
40107 /*! @} */
40108 
40109 /*! @name MAC_MMC_RX_INTERRUPT_MASK - MMC Rx Interrupt Mask */
40110 /*! @{ */
40111 
40112 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK (0x1U)
40113 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT (0U)
40114 /*! RXGBPKTIM - MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the
40115  *    interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value.
40116  *  0b0..MMC Receive Good Bad Packet Counter Interrupt Mask is disabled
40117  *  0b1..MMC Receive Good Bad Packet Counter Interrupt Mask is enabled
40118  */
40119 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK)
40120 
40121 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK (0x2U)
40122 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT (1U)
40123 /*! RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the
40124  *    interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value.
40125  *  0b0..MMC Receive Good Bad Octet Counter Interrupt Mask is disabled
40126  *  0b1..MMC Receive Good Bad Octet Counter Interrupt Mask is enabled
40127  */
40128 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK)
40129 
40130 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK (0x4U)
40131 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT (2U)
40132 /*! RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt
40133  *    when the rxoctetcount_g counter reaches half of the maximum value or the maximum value.
40134  *  0b0..MMC Receive Good Octet Counter Interrupt Mask is disabled
40135  *  0b1..MMC Receive Good Octet Counter Interrupt Mask is enabled
40136  */
40137 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK)
40138 
40139 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK (0x8U)
40140 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT (3U)
40141 /*! RXBCGPIM - MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the
40142  *    interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the
40143  *    maximum value.
40144  *  0b0..MMC Receive Broadcast Good Packet Counter Interrupt Mask is disabled
40145  *  0b1..MMC Receive Broadcast Good Packet Counter Interrupt Mask is enabled
40146  */
40147 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK)
40148 
40149 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK (0x10U)
40150 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT (4U)
40151 /*! RXMCGPIM - MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the
40152  *    interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the
40153  *    maximum value.
40154  *  0b0..MMC Receive Multicast Good Packet Counter Interrupt Mask is disabled
40155  *  0b1..MMC Receive Multicast Good Packet Counter Interrupt Mask is enabled
40156  */
40157 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK)
40158 
40159 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK (0x20U)
40160 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT (5U)
40161 /*! RXCRCERPIM - MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the
40162  *    interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value.
40163  *  0b0..MMC Receive CRC Error Packet Counter Interrupt Mask is disabled
40164  *  0b1..MMC Receive CRC Error Packet Counter Interrupt Mask is enabled
40165  */
40166 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK)
40167 
40168 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK (0x40U)
40169 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT (6U)
40170 /*! RXALGNERPIM - MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks
40171  *    the interrupt when the rxalignmenterror counter reaches half of the maximum value or the
40172  *    maximum value.
40173  *  0b0..MMC Receive Alignment Error Packet Counter Interrupt Mask is disabled
40174  *  0b1..MMC Receive Alignment Error Packet Counter Interrupt Mask is enabled
40175  */
40176 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK)
40177 
40178 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK (0x80U)
40179 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT (7U)
40180 /*! RXRUNTPIM - MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt
40181  *    when the rxrunterror counter reaches half of the maximum value or the maximum value.
40182  *  0b0..MMC Receive Runt Packet Counter Interrupt Mask is disabled
40183  *  0b1..MMC Receive Runt Packet Counter Interrupt Mask is enabled
40184  */
40185 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK)
40186 
40187 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK (0x100U)
40188 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT (8U)
40189 /*! RXJABERPIM - MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the
40190  *    interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value.
40191  *  0b0..MMC Receive Jabber Error Packet Counter Interrupt Mask is disabled
40192  *  0b1..MMC Receive Jabber Error Packet Counter Interrupt Mask is enabled
40193  */
40194 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK)
40195 
40196 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK (0x200U)
40197 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT (9U)
40198 /*! RXUSIZEGPIM - MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks
40199  *    the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum
40200  *    value.
40201  *  0b0..MMC Receive Undersize Good Packet Counter Interrupt Mask is disabled
40202  *  0b1..MMC Receive Undersize Good Packet Counter Interrupt Mask is enabled
40203  */
40204 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK)
40205 
40206 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK (0x400U)
40207 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT (10U)
40208 /*! RXOSIZEGPIM - MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the
40209  *    interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum
40210  *    value.
40211  *  0b0..MMC Receive Oversize Good Packet Counter Interrupt Mask is disabled
40212  *  0b1..MMC Receive Oversize Good Packet Counter Interrupt Mask is enabled
40213  */
40214 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK)
40215 
40216 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK (0x800U)
40217 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT (11U)
40218 /*! RX64OCTGBPIM - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit
40219  *    masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the
40220  *    maximum value.
40221  *  0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is disabled
40222  *  0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is enabled
40223  */
40224 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK)
40225 
40226 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK (0x1000U)
40227 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT (12U)
40228 /*! RX65T127OCTGBPIM - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting
40229  *    this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum
40230  *    value or the maximum value.
40231  *  0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled
40232  *  0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled
40233  */
40234 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK)
40235 
40236 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK (0x2000U)
40237 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT (13U)
40238 /*! RX128T255OCTGBPIM - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting
40239  *    this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum
40240  *    value or the maximum value.
40241  *  0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled
40242  *  0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled
40243  */
40244 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK)
40245 
40246 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK (0x4000U)
40247 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT (14U)
40248 /*! RX256T511OCTGBPIM - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting
40249  *    this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum
40250  *    value or the maximum value.
40251  *  0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled
40252  *  0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled
40253  */
40254 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK)
40255 
40256 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK (0x8000U)
40257 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT (15U)
40258 /*! RX512T1023OCTGBPIM - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask
40259  *    Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the
40260  *    maximum value or the maximum value.
40261  *  0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled
40262  *  0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled
40263  */
40264 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK)
40265 
40266 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK (0x10000U)
40267 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT (16U)
40268 /*! RX1024TMAXOCTGBPIM - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask.
40269  *  0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled
40270  *  0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled
40271  */
40272 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK)
40273 
40274 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK (0x20000U)
40275 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT (17U)
40276 /*! RXUCGPIM - MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the
40277  *    interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum
40278  *    value.
40279  *  0b0..MMC Receive Unicast Good Packet Counter Interrupt Mask is disabled
40280  *  0b1..MMC Receive Unicast Good Packet Counter Interrupt Mask is enabled
40281  */
40282 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK)
40283 
40284 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK (0x40000U)
40285 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT (18U)
40286 /*! RXLENERPIM - MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the
40287  *    interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value.
40288  *  0b0..MMC Receive Length Error Packet Counter Interrupt Mask is disabled
40289  *  0b1..MMC Receive Length Error Packet Counter Interrupt Mask is enabled
40290  */
40291 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK)
40292 
40293 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK (0x80000U)
40294 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT (19U)
40295 /*! RXORANGEPIM - MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit
40296  *    masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the
40297  *    maximum value.
40298  *  0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is disabled
40299  *  0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is enabled
40300  */
40301 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK)
40302 
40303 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK (0x100000U)
40304 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT (20U)
40305 /*! RXPAUSPIM - MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt
40306  *    when the rxpausepackets counter reaches half of the maximum value or the maximum value.
40307  *  0b0..MMC Receive Pause Packet Counter Interrupt Mask is disabled
40308  *  0b1..MMC Receive Pause Packet Counter Interrupt Mask is enabled
40309  */
40310 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK)
40311 
40312 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK (0x200000U)
40313 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT (21U)
40314 /*! RXFOVPIM - MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the
40315  *    interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value.
40316  *  0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is disabled
40317  *  0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is enabled
40318  */
40319 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK)
40320 
40321 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK (0x400000U)
40322 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT (22U)
40323 /*! RXVLANGBPIM - MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the
40324  *    interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum
40325  *    value.
40326  *  0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is disabled
40327  *  0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is enabled
40328  */
40329 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK)
40330 
40331 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK (0x800000U)
40332 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT (23U)
40333 /*! RXWDOGPIM - MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the
40334  *    interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value.
40335  *  0b0..MMC Receive Watchdog Error Packet Counter Interrupt Mask is disabled
40336  *  0b1..MMC Receive Watchdog Error Packet Counter Interrupt Mask is enabled
40337  */
40338 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK)
40339 
40340 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK (0x1000000U)
40341 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT (24U)
40342 /*! RXRCVERRPIM - MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the
40343  *    interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value.
40344  *  0b0..MMC Receive Error Packet Counter Interrupt Mask is disabled
40345  *  0b1..MMC Receive Error Packet Counter Interrupt Mask is enabled
40346  */
40347 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK)
40348 
40349 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK (0x2000000U)
40350 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT (25U)
40351 /*! RXCTRLPIM - MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the
40352  *    interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value.
40353  *  0b0..MMC Receive Control Packet Counter Interrupt Mask is disabled
40354  *  0b1..MMC Receive Control Packet Counter Interrupt Mask is enabled
40355  */
40356 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK)
40357 
40358 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK (0x4000000U)
40359 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT (26U)
40360 /*! RXLPIUSCIM - MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the
40361  *    interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
40362  *  0b0..MMC Receive LPI microsecond counter interrupt Mask is disabled
40363  *  0b1..MMC Receive LPI microsecond counter interrupt Mask is enabled
40364  */
40365 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK)
40366 
40367 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK (0x8000000U)
40368 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT (27U)
40369 /*! RXLPITRCIM - MMC Receive LPI transition counter interrupt Mask Setting this bit masks the
40370  *    interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
40371  *  0b0..MMC Receive LPI transition counter interrupt Mask is disabled
40372  *  0b1..MMC Receive LPI transition counter interrupt Mask is enabled
40373  */
40374 #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK)
40375 /*! @} */
40376 
40377 /*! @name MAC_MMC_TX_INTERRUPT_MASK - MMC Tx Interrupt Mask */
40378 /*! @{ */
40379 
40380 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK (0x1U)
40381 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT (0U)
40382 /*! TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the
40383  *    interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value.
40384  *  0b0..MMC Transmit Good Bad Octet Counter Interrupt Mask is disabled
40385  *  0b1..MMC Transmit Good Bad Octet Counter Interrupt Mask is enabled
40386  */
40387 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK)
40388 
40389 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK (0x2U)
40390 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT (1U)
40391 /*! TXGBPKTIM - MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the
40392  *    interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value.
40393  *  0b0..MMC Transmit Good Bad Packet Counter Interrupt Mask is disabled
40394  *  0b1..MMC Transmit Good Bad Packet Counter Interrupt Mask is enabled
40395  */
40396 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK)
40397 
40398 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK (0x4U)
40399 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT (2U)
40400 /*! TXBCGPIM - MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the
40401  *    interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the
40402  *    maximum value.
40403  *  0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is disabled
40404  *  0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is enabled
40405  */
40406 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK)
40407 
40408 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK (0x8U)
40409 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT (3U)
40410 /*! TXMCGPIM - MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the
40411  *    interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the
40412  *    maximum value.
40413  *  0b0..MMC Transmit Multicast Good Packet Counter Interrupt Mask is disabled
40414  *  0b1..MMC Transmit Multicast Good Packet Counter Interrupt Mask is enabled
40415  */
40416 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK)
40417 
40418 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK (0x10U)
40419 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT (4U)
40420 /*! TX64OCTGBPIM - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit
40421  *    masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the
40422  *    maximum value.
40423  *  0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is disabled
40424  *  0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is enabled
40425  */
40426 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK)
40427 
40428 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK (0x20U)
40429 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT (5U)
40430 /*! TX65T127OCTGBPIM - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting
40431  *    this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum
40432  *    value or the maximum value.
40433  *  0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled
40434  *  0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled
40435  */
40436 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK)
40437 
40438 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK (0x40U)
40439 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT (6U)
40440 /*! TX128T255OCTGBPIM - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting
40441  *    this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum
40442  *    value or the maximum value.
40443  *  0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled
40444  *  0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled
40445  */
40446 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK)
40447 
40448 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK (0x80U)
40449 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT (7U)
40450 /*! TX256T511OCTGBPIM - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting
40451  *    this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum
40452  *    value or the maximum value.
40453  *  0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled
40454  *  0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled
40455  */
40456 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK)
40457 
40458 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK (0x100U)
40459 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT (8U)
40460 /*! TX512T1023OCTGBPIM - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask
40461  *    Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the
40462  *    maximum value or the maximum value.
40463  *  0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled
40464  *  0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled
40465  */
40466 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK)
40467 
40468 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK (0x200U)
40469 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT (9U)
40470 /*! TX1024TMAXOCTGBPIM - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask
40471  *    Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the
40472  *    maximum value or the maximum value.
40473  *  0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled
40474  *  0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled
40475  */
40476 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK)
40477 
40478 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK (0x400U)
40479 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT (10U)
40480 /*! TXUCGBPIM - MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks
40481  *    the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the
40482  *    maximum value.
40483  *  0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is disabled
40484  *  0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is enabled
40485  */
40486 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK)
40487 
40488 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK (0x800U)
40489 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT (11U)
40490 /*! TXMCGBPIM - MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks
40491  *    the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the
40492  *    maximum value.
40493  *  0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is disabled
40494  *  0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is enabled
40495  */
40496 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK)
40497 
40498 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK (0x1000U)
40499 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT (12U)
40500 /*! TXBCGBPIM - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks
40501  *    the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the
40502  *    maximum value.
40503  *  0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is disabled
40504  *  0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is enabled
40505  */
40506 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK)
40507 
40508 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK (0x2000U)
40509 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT (13U)
40510 /*! TXUFLOWERPIM - MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks
40511  *    the interrupt when the txunderflowerror counter reaches half of the maximum value or the
40512  *    maximum value.
40513  *  0b0..MMC Transmit Underflow Error Packet Counter Interrupt Mask is disabled
40514  *  0b1..MMC Transmit Underflow Error Packet Counter Interrupt Mask is enabled
40515  */
40516 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK)
40517 
40518 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK (0x4000U)
40519 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT (14U)
40520 /*! TXSCOLGPIM - MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit
40521  *    masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the
40522  *    maximum value.
40523  *  0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is disabled
40524  *  0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is enabled
40525  */
40526 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK)
40527 
40528 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK (0x8000U)
40529 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT (15U)
40530 /*! TXMCOLGPIM - MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit
40531  *    masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the
40532  *    maximum value.
40533  *  0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is disabled
40534  *  0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is enabled
40535  */
40536 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK)
40537 
40538 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK (0x10000U)
40539 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT (16U)
40540 /*! TXDEFPIM - MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the
40541  *    interrupt when the txdeferred counter reaches half of the maximum value or the maximum value.
40542  *  0b0..MMC Transmit Deferred Packet Counter Interrupt Mask is disabled
40543  *  0b1..MMC Transmit Deferred Packet Counter Interrupt Mask is enabled
40544  */
40545 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK)
40546 
40547 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK (0x20000U)
40548 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT (17U)
40549 /*! TXLATCOLPIM - MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks
40550  *    the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value.
40551  *  0b0..MMC Transmit Late Collision Packet Counter Interrupt Mask is disabled
40552  *  0b1..MMC Transmit Late Collision Packet Counter Interrupt Mask is enabled
40553  */
40554 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK)
40555 
40556 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK (0x40000U)
40557 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT (18U)
40558 /*! TXEXCOLPIM - MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit
40559  *    masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum
40560  *    value.
40561  *  0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is disabled
40562  *  0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is enabled
40563  */
40564 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK)
40565 
40566 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK (0x80000U)
40567 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT (19U)
40568 /*! TXCARERPIM - MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the
40569  *    interrupt when the txcarriererror counter reaches half of the maximum value or the maximum
40570  *    value.
40571  *  0b0..MMC Transmit Carrier Error Packet Counter Interrupt Mask is disabled
40572  *  0b1..MMC Transmit Carrier Error Packet Counter Interrupt Mask is enabled
40573  */
40574 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK)
40575 
40576 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK (0x100000U)
40577 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT (20U)
40578 /*! TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt
40579  *    when the txoctetcount_g counter reaches half of the maximum value or the maximum value.
40580  *  0b0..MMC Transmit Good Octet Counter Interrupt Mask is disabled
40581  *  0b1..MMC Transmit Good Octet Counter Interrupt Mask is enabled
40582  */
40583 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK)
40584 
40585 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK (0x200000U)
40586 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT (21U)
40587 /*! TXGPKTIM - MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt
40588  *    when the txpacketcount_g counter reaches half of the maximum value or the maximum value.
40589  *  0b0..MMC Transmit Good Packet Counter Interrupt Mask is disabled
40590  *  0b1..MMC Transmit Good Packet Counter Interrupt Mask is enabled
40591  */
40592 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK)
40593 
40594 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK (0x400000U)
40595 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT (22U)
40596 /*! TXEXDEFPIM - MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit
40597  *    masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum
40598  *    value.
40599  *  0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is disabled
40600  *  0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is enabled
40601  */
40602 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK)
40603 
40604 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK (0x800000U)
40605 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT (23U)
40606 /*! TXPAUSPIM - MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the
40607  *    interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value.
40608  *  0b0..MMC Transmit Pause Packet Counter Interrupt Mask is disabled
40609  *  0b1..MMC Transmit Pause Packet Counter Interrupt Mask is enabled
40610  */
40611 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK)
40612 
40613 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK (0x1000000U)
40614 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT (24U)
40615 /*! TXVLANGPIM - MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the
40616  *    interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value.
40617  *  0b0..MMC Transmit VLAN Good Packet Counter Interrupt Mask is disabled
40618  *  0b1..MMC Transmit VLAN Good Packet Counter Interrupt Mask is enabled
40619  */
40620 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK)
40621 
40622 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK (0x2000000U)
40623 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT (25U)
40624 /*! TXOSIZEGPIM - MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks
40625  *    the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum
40626  *    value.
40627  *  0b0..MMC Transmit Oversize Good Packet Counter Interrupt Mask is disabled
40628  *  0b1..MMC Transmit Oversize Good Packet Counter Interrupt Mask is enabled
40629  */
40630 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK)
40631 
40632 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK (0x4000000U)
40633 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT (26U)
40634 /*! TXLPIUSCIM - MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the
40635  *    interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
40636  *  0b0..MMC Transmit LPI microsecond counter interrupt Mask is disabled
40637  *  0b1..MMC Transmit LPI microsecond counter interrupt Mask is enabled
40638  */
40639 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK)
40640 
40641 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK (0x8000000U)
40642 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT (27U)
40643 /*! TXLPITRCIM - MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the
40644  *    interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
40645  *  0b0..MMC Transmit LPI transition counter interrupt Mask is disabled
40646  *  0b1..MMC Transmit LPI transition counter interrupt Mask is enabled
40647  */
40648 #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK)
40649 /*! @} */
40650 
40651 /*! @name MAC_TX_OCTET_COUNT_GOOD_BAD - Tx Octet Count Good and Bad */
40652 /*! @{ */
40653 
40654 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFFU)
40655 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0U)
40656 /*! TXOCTGB - Tx Octet Count Good Bad This field indicates the number of bytes transmitted,
40657  *    exclusive of preamble and retried bytes, in good and bad packets.
40658  */
40659 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK)
40660 /*! @} */
40661 
40662 /*! @name MAC_TX_PACKET_COUNT_GOOD_BAD - Tx Packet Count Good and Bad */
40663 /*! @{ */
40664 
40665 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFFU)
40666 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0U)
40667 /*! TXPKTGB - Tx Packet Count Good Bad This field indicates the number of good and bad packets
40668  *    transmitted, exclusive of retried packets.
40669  */
40670 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK)
40671 /*! @} */
40672 
40673 /*! @name MAC_TX_BROADCAST_PACKETS_GOOD - Tx Broadcast Packets Good */
40674 /*! @{ */
40675 
40676 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xFFFFFFFFU)
40677 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT (0U)
40678 /*! TXBCASTG - Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted. */
40679 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK)
40680 /*! @} */
40681 
40682 /*! @name MAC_TX_MULTICAST_PACKETS_GOOD - Tx Multicast Packets Good */
40683 /*! @{ */
40684 
40685 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xFFFFFFFFU)
40686 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT (0U)
40687 /*! TXMCASTG - Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted. */
40688 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK)
40689 /*! @} */
40690 
40691 /*! @name MAC_TX_64OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 64-Byte Packets */
40692 /*! @{ */
40693 
40694 #define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xFFFFFFFFU)
40695 #define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT (0U)
40696 /*! TX64OCTGB - Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets
40697  *    transmitted with length 64 bytes, exclusive of preamble and retried packets.
40698  */
40699 #define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT)) & ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK)
40700 /*! @} */
40701 
40702 /*! @name MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 65 to 127-Byte Packets */
40703 /*! @{ */
40704 
40705 #define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xFFFFFFFFU)
40706 #define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT (0U)
40707 /*! TX65_127OCTGB - Tx 65To127Octets Packets Good Bad This field indicates the number of good and
40708  *    bad packets transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble
40709  *    and retried packets.
40710  */
40711 #define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK)
40712 /*! @} */
40713 
40714 /*! @name MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 128 to 255-Byte Packets */
40715 /*! @{ */
40716 
40717 #define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xFFFFFFFFU)
40718 #define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT (0U)
40719 /*! TX128_255OCTGB - Tx 128To255Octets Packets Good Bad This field indicates the number of good and
40720  *    bad packets transmitted with length between 128 and 255 (inclusive) bytes, exclusive of
40721  *    preamble and retried packets.
40722  */
40723 #define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK)
40724 /*! @} */
40725 
40726 /*! @name MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 256 to 511-Byte Packets */
40727 /*! @{ */
40728 
40729 #define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xFFFFFFFFU)
40730 #define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT (0U)
40731 /*! TX256_511OCTGB - Tx 256To511Octets Packets Good Bad This field indicates the number of good and
40732  *    bad packets transmitted with length between 256 and 511 (inclusive) bytes, exclusive of
40733  *    preamble and retried packets.
40734  */
40735 #define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK)
40736 /*! @} */
40737 
40738 /*! @name MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 512 to 1023-Byte Packets */
40739 /*! @{ */
40740 
40741 #define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xFFFFFFFFU)
40742 #define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT (0U)
40743 /*! TX512_1023OCTGB - Tx 512To1023Octets Packets Good Bad This field indicates the number of good
40744  *    and bad packets transmitted with length between 512 and 1023 (inclusive) bytes, exclusive of
40745  *    preamble and retried packets.
40746  */
40747 #define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK)
40748 /*! @} */
40749 
40750 /*! @name MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 1024 to Max-Byte Packets */
40751 /*! @{ */
40752 
40753 #define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xFFFFFFFFU)
40754 #define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT (0U)
40755 /*! TX1024_MAXOCTGB - Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good
40756  *    and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes, exclusive of
40757  *    preamble and retried packets.
40758  */
40759 #define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK)
40760 /*! @} */
40761 
40762 /*! @name MAC_TX_UNICAST_PACKETS_GOOD_BAD - Good and Bad Unicast Packets Transmitted */
40763 /*! @{ */
40764 
40765 #define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xFFFFFFFFU)
40766 #define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT (0U)
40767 /*! TXUCASTGB - Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted. */
40768 #define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT)) & ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK)
40769 /*! @} */
40770 
40771 /*! @name MAC_TX_MULTICAST_PACKETS_GOOD_BAD - Good and Bad Multicast Packets Transmitted */
40772 /*! @{ */
40773 
40774 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xFFFFFFFFU)
40775 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT (0U)
40776 /*! TXMCASTGB - Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted. */
40777 #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK)
40778 /*! @} */
40779 
40780 /*! @name MAC_TX_BROADCAST_PACKETS_GOOD_BAD - Good and Bad Broadcast Packets Transmitted */
40781 /*! @{ */
40782 
40783 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xFFFFFFFFU)
40784 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT (0U)
40785 /*! TXBCASTGB - Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted. */
40786 #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK)
40787 /*! @} */
40788 
40789 /*! @name MAC_TX_UNDERFLOW_ERROR_PACKETS - Tx Packets Aborted By Underflow Error */
40790 /*! @{ */
40791 
40792 #define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFFU)
40793 #define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0U)
40794 /*! TXUNDRFLW - Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error. */
40795 #define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT)) & ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK)
40796 /*! @} */
40797 
40798 /*! @name MAC_TX_SINGLE_COLLISION_GOOD_PACKETS - Single Collision Good Packets Transmitted */
40799 /*! @{ */
40800 
40801 #define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xFFFFFFFFU)
40802 #define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT (0U)
40803 /*! TXSNGLCOLG - Tx Single Collision Good Packets This field indicates the number of successfully
40804  *    transmitted packets after a single collision in the half-duplex mode.
40805  */
40806 #define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT)) & ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK)
40807 /*! @} */
40808 
40809 /*! @name MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS - Multiple Collision Good Packets Transmitted */
40810 /*! @{ */
40811 
40812 #define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xFFFFFFFFU)
40813 #define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT (0U)
40814 /*! TXMULTCOLG - Tx Multiple Collision Good Packets This field indicates the number of successfully
40815  *    transmitted packets after multiple collisions in the half-duplex mode.
40816  */
40817 #define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT)) & ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK)
40818 /*! @} */
40819 
40820 /*! @name MAC_TX_DEFERRED_PACKETS - Deferred Packets Transmitted */
40821 /*! @{ */
40822 
40823 #define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xFFFFFFFFU)
40824 #define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT (0U)
40825 /*! TXDEFRD - Tx Deferred Packets This field indicates the number of successfully transmitted after
40826  *    a deferral in the half-duplex mode.
40827  */
40828 #define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT)) & ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK)
40829 /*! @} */
40830 
40831 /*! @name MAC_TX_LATE_COLLISION_PACKETS - Late Collision Packets Transmitted */
40832 /*! @{ */
40833 
40834 #define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xFFFFFFFFU)
40835 #define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT (0U)
40836 /*! TXLATECOL - Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error. */
40837 #define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT)) & ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK)
40838 /*! @} */
40839 
40840 /*! @name MAC_TX_EXCESSIVE_COLLISION_PACKETS - Excessive Collision Packets Transmitted */
40841 /*! @{ */
40842 
40843 #define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xFFFFFFFFU)
40844 #define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT (0U)
40845 /*! TXEXSCOL - Tx Excessive Collision Packets This field indicates the number of packets aborted
40846  *    because of excessive (16) collision errors.
40847  */
40848 #define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK)
40849 /*! @} */
40850 
40851 /*! @name MAC_TX_CARRIER_ERROR_PACKETS - Carrier Error Packets Transmitted */
40852 /*! @{ */
40853 
40854 #define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFFU)
40855 #define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0U)
40856 /*! TXCARR - Tx Carrier Error Packets This field indicates the number of packets aborted because of
40857  *    carrier sense error (no carrier or loss of carrier).
40858  */
40859 #define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT)) & ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK)
40860 /*! @} */
40861 
40862 /*! @name MAC_TX_OCTET_COUNT_GOOD - Bytes Transmitted in Good Packets */
40863 /*! @{ */
40864 
40865 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFFU)
40866 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0U)
40867 /*! TXOCTG - Tx Octet Count Good This field indicates the number of bytes transmitted, exclusive of preamble, only in good packets. */
40868 #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK)
40869 /*! @} */
40870 
40871 /*! @name MAC_TX_PACKET_COUNT_GOOD - Good Packets Transmitted */
40872 /*! @{ */
40873 
40874 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFFU)
40875 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0U)
40876 /*! TXPKTG - Tx Packet Count Good This field indicates the number of good packets transmitted. */
40877 #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK)
40878 /*! @} */
40879 
40880 /*! @name MAC_TX_EXCESSIVE_DEFERRAL_ERROR - Packets Aborted By Excessive Deferral Error */
40881 /*! @{ */
40882 
40883 #define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xFFFFFFFFU)
40884 #define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT (0U)
40885 /*! TXEXSDEF - Tx Excessive Deferral Error This field indicates the number of packets aborted
40886  *    because of excessive deferral error (deferred for more than two max-sized packet times).
40887  */
40888 #define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK)
40889 /*! @} */
40890 
40891 /*! @name MAC_TX_PAUSE_PACKETS - Pause Packets Transmitted */
40892 /*! @{ */
40893 
40894 #define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xFFFFFFFFU)
40895 #define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT (0U)
40896 /*! TXPAUSE - Tx Pause Packets This field indicates the number of good Pause packets transmitted. */
40897 #define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT)) & ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK)
40898 /*! @} */
40899 
40900 /*! @name MAC_TX_VLAN_PACKETS_GOOD - Good VLAN Packets Transmitted */
40901 /*! @{ */
40902 
40903 #define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xFFFFFFFFU)
40904 #define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT (0U)
40905 /*! TXVLANG - Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted. */
40906 #define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT)) & ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK)
40907 /*! @} */
40908 
40909 /*! @name MAC_TX_OSIZE_PACKETS_GOOD - Good Oversize Packets Transmitted */
40910 /*! @{ */
40911 
40912 #define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xFFFFFFFFU)
40913 #define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT (0U)
40914 /*! TXOSIZG - Tx OSize Packets Good This field indicates the number of packets transmitted without
40915  *    errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged packets;
40916  *    2000 bytes if enabled in S2KP bit of the CONFIGURATION register).
40917  */
40918 #define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT)) & ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK)
40919 /*! @} */
40920 
40921 /*! @name MAC_RX_PACKETS_COUNT_GOOD_BAD - Good and Bad Packets Received */
40922 /*! @{ */
40923 
40924 #define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFFU)
40925 #define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0U)
40926 /*! RXPKTGB - Rx Packets Count Good Bad This field indicates the number of good and bad packets received. */
40927 #define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT)) & ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK)
40928 /*! @} */
40929 
40930 /*! @name MAC_RX_OCTET_COUNT_GOOD_BAD - Bytes in Good and Bad Packets Received */
40931 /*! @{ */
40932 
40933 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFFU)
40934 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0U)
40935 /*! RXOCTGB - Rx Octet Count Good Bad This field indicates the number of bytes received, exclusive
40936  *    of preamble, in good and bad packets.
40937  */
40938 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK)
40939 /*! @} */
40940 
40941 /*! @name MAC_RX_OCTET_COUNT_GOOD - Bytes in Good Packets Received */
40942 /*! @{ */
40943 
40944 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFFU)
40945 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0U)
40946 /*! RXOCTG - Rx Octet Count Good This field indicates the number of bytes received, exclusive of preamble, only in good packets. */
40947 #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK)
40948 /*! @} */
40949 
40950 /*! @name MAC_RX_BROADCAST_PACKETS_GOOD - Good Broadcast Packets Received */
40951 /*! @{ */
40952 
40953 #define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xFFFFFFFFU)
40954 #define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT (0U)
40955 /*! RXBCASTG - Rx Broadcast Packets Good This field indicates the number of good broadcast packets received. */
40956 #define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT)) & ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK)
40957 /*! @} */
40958 
40959 /*! @name MAC_RX_MULTICAST_PACKETS_GOOD - Good Multicast Packets Received */
40960 /*! @{ */
40961 
40962 #define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFFU)
40963 #define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0U)
40964 /*! RXMCASTG - Rx Multicast Packets Good This field indicates the number of good multicast packets received. */
40965 #define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT)) & ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK)
40966 /*! @} */
40967 
40968 /*! @name MAC_RX_CRC_ERROR_PACKETS - CRC Error Packets Received */
40969 /*! @{ */
40970 
40971 #define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFFU)
40972 #define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0U)
40973 /*! RXCRCERR - Rx CRC Error Packets This field indicates the number of packets received with CRC error. */
40974 #define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT)) & ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK)
40975 /*! @} */
40976 
40977 /*! @name MAC_RX_ALIGNMENT_ERROR_PACKETS - Alignment Error Packets Received */
40978 /*! @{ */
40979 
40980 #define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xFFFFFFFFU)
40981 #define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT (0U)
40982 /*! RXALGNERR - Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error. */
40983 #define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT)) & ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK)
40984 /*! @} */
40985 
40986 /*! @name MAC_RX_RUNT_ERROR_PACKETS - Runt Error Packets Received */
40987 /*! @{ */
40988 
40989 #define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xFFFFFFFFU)
40990 #define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT (0U)
40991 /*! RXRUNTERR - Rx Runt Error Packets This field indicates the number of packets received with runt
40992  *    (length less than 64 bytes and CRC error) error.
40993  */
40994 #define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT)) & ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK)
40995 /*! @} */
40996 
40997 /*! @name MAC_RX_JABBER_ERROR_PACKETS - Jabber Error Packets Received */
40998 /*! @{ */
40999 
41000 #define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xFFFFFFFFU)
41001 #define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT (0U)
41002 /*! RXJABERR - Rx Jabber Error Packets This field indicates the number of giant packets received
41003  *    with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC
41004  *    error.
41005  */
41006 #define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT)) & ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK)
41007 /*! @} */
41008 
41009 /*! @name MAC_RX_UNDERSIZE_PACKETS_GOOD - Good Undersize Packets Received */
41010 /*! @{ */
41011 
41012 #define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xFFFFFFFFU)
41013 #define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT (0U)
41014 /*! RXUNDERSZG - Rx Undersize Packets Good This field indicates the number of packets received with
41015  *    length less than 64 bytes, without any errors.
41016  */
41017 #define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT)) & ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK)
41018 /*! @} */
41019 
41020 /*! @name MAC_RX_OVERSIZE_PACKETS_GOOD - Good Oversize Packets Received */
41021 /*! @{ */
41022 
41023 #define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xFFFFFFFFU)
41024 #define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT (0U)
41025 /*! RXOVERSZG - Rx Oversize Packets Good This field indicates the number of packets received without
41026  *    errors, with length greater than the maxsize (1,518 bytes or 1,522 bytes for VLAN tagged
41027  *    packets; 2000 bytes if enabled in the S2KP bit of the MAC_CONFIGURATION register).
41028  */
41029 #define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT)) & ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK)
41030 /*! @} */
41031 
41032 /*! @name MAC_RX_64OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-Byte Packets Received */
41033 /*! @{ */
41034 
41035 #define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xFFFFFFFFU)
41036 #define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT (0U)
41037 /*! RX64OCTGB - Rx 64 Octets Packets Good Bad This field indicates the number of good and bad
41038  *    packets received with length 64 bytes, exclusive of the preamble.
41039  */
41040 #define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT)) & ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK)
41041 /*! @} */
41042 
41043 /*! @name MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-to-127 Byte Packets Received */
41044 /*! @{ */
41045 
41046 #define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xFFFFFFFFU)
41047 #define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT (0U)
41048 /*! RX65_127OCTGB - Rx 65-127 Octets Packets Good Bad This field indicates the number of good and
41049  *    bad packets received with length between 65 and 127 (inclusive) bytes, exclusive of the preamble.
41050  */
41051 #define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK)
41052 /*! @} */
41053 
41054 /*! @name MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD - Good and Bad 128-to-255 Byte Packets Received */
41055 /*! @{ */
41056 
41057 #define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xFFFFFFFFU)
41058 #define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT (0U)
41059 /*! RX128_255OCTGB - Rx 128-255 Octets Packets Good Bad This field indicates the number of good and
41060  *    bad packets received with length between 128 and 255 (inclusive) bytes, exclusive of the
41061  *    preamble.
41062  */
41063 #define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK)
41064 /*! @} */
41065 
41066 /*! @name MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD - Good and Bad 256-to-511 Byte Packets Received */
41067 /*! @{ */
41068 
41069 #define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xFFFFFFFFU)
41070 #define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT (0U)
41071 /*! RX256_511OCTGB - Rx 256-511 Octets Packets Good Bad This field indicates the number of good and
41072  *    bad packets received with length between 256 and 511 (inclusive) bytes, exclusive of the
41073  *    preamble.
41074  */
41075 #define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK)
41076 /*! @} */
41077 
41078 /*! @name MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD - Good and Bad 512-to-1023 Byte Packets Received */
41079 /*! @{ */
41080 
41081 #define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xFFFFFFFFU)
41082 #define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT (0U)
41083 /*! RX512_1023OCTGB - RX 512-1023 Octets Packets Good Bad This field indicates the number of good
41084  *    and bad packets received with length between 512 and 1023 (inclusive) bytes, exclusive of the
41085  *    preamble.
41086  */
41087 #define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK)
41088 /*! @} */
41089 
41090 /*! @name MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Good and Bad 1024-to-Max Byte Packets Received */
41091 /*! @{ */
41092 
41093 #define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xFFFFFFFFU)
41094 #define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT (0U)
41095 /*! RX1024_MAXOCTGB - Rx 1024-Max Octets Good Bad This field indicates the number of good and bad
41096  *    packets received with length between 1024 and maxsize (inclusive) bytes, exclusive of the
41097  *    preamble.
41098  */
41099 #define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK)
41100 /*! @} */
41101 
41102 /*! @name MAC_RX_UNICAST_PACKETS_GOOD - Good Unicast Packets Received */
41103 /*! @{ */
41104 
41105 #define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xFFFFFFFFU)
41106 #define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT (0U)
41107 /*! RXUCASTG - Rx Unicast Packets Good This field indicates the number of good unicast packets received. */
41108 #define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT)) & ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK)
41109 /*! @} */
41110 
41111 /*! @name MAC_RX_LENGTH_ERROR_PACKETS - Length Error Packets Received */
41112 /*! @{ */
41113 
41114 #define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFFU)
41115 #define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0U)
41116 /*! RXLENERR - Rx Length Error Packets This field indicates the number of packets received with
41117  *    length error (Length Type field not equal to packet size), for all packets with valid length field.
41118  */
41119 #define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT)) & ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK)
41120 /*! @} */
41121 
41122 /*! @name MAC_RX_OUT_OF_RANGE_TYPE_PACKETS - Out-of-range Type Packets Received */
41123 /*! @{ */
41124 
41125 #define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xFFFFFFFFU)
41126 #define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT (0U)
41127 /*! RXOUTOFRNG - Rx Out of Range Type Packet This field indicates the number of packets received
41128  *    with length field not equal to the valid packet size (greater than 1,500 but less than 1,536).
41129  */
41130 #define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT)) & ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK)
41131 /*! @} */
41132 
41133 /*! @name MAC_RX_PAUSE_PACKETS - Pause Packets Received */
41134 /*! @{ */
41135 
41136 #define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xFFFFFFFFU)
41137 #define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT (0U)
41138 /*! RXPAUSEPKT - Rx Pause Packets This field indicates the number of good and valid Pause packets received. */
41139 #define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT)) & ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK)
41140 /*! @} */
41141 
41142 /*! @name MAC_RX_FIFO_OVERFLOW_PACKETS - Missed Packets Due to FIFO Overflow */
41143 /*! @{ */
41144 
41145 #define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFFU)
41146 #define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0U)
41147 /*! RXFIFOOVFL - Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow. */
41148 #define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT)) & ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK)
41149 /*! @} */
41150 
41151 /*! @name MAC_RX_VLAN_PACKETS_GOOD_BAD - Good and Bad VLAN Packets Received */
41152 /*! @{ */
41153 
41154 #define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xFFFFFFFFU)
41155 #define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT (0U)
41156 /*! RXVLANPKTGB - Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received. */
41157 #define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT)) & ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK)
41158 /*! @} */
41159 
41160 /*! @name MAC_RX_WATCHDOG_ERROR_PACKETS - Watchdog Error Packets Received */
41161 /*! @{ */
41162 
41163 #define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xFFFFFFFFU)
41164 #define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT (0U)
41165 /*! RXWDGERR - Rx Watchdog Error Packets This field indicates the number of packets received with
41166  *    error because of watchdog timeout error (packets with a data load larger than 2,048 bytes (when
41167  *    JE and WD bits are reset in MAC_CONFIGURATION register), 10,240 bytes (when JE bit is set and
41168  *    WD bit is reset in MAC_CONFIGURATION register), 16,384 bytes (when WD bit is set in
41169  *    MAC_CONFIGURATION register) or the value programmed in the MAC_WATCHDOG_TIMEOUT register).
41170  */
41171 #define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT)) & ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK)
41172 /*! @} */
41173 
41174 /*! @name MAC_RX_RECEIVE_ERROR_PACKETS - Receive Error Packets Received */
41175 /*! @{ */
41176 
41177 #define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xFFFFFFFFU)
41178 #define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT (0U)
41179 /*! RXRCVERR - Rx Receive Error Packets This field indicates the number of packets received with
41180  *    Receive error or Packet Extension error on the GMII or MII interface.
41181  */
41182 #define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT)) & ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK)
41183 /*! @} */
41184 
41185 /*! @name MAC_RX_CONTROL_PACKETS_GOOD - Good Control Packets Received */
41186 /*! @{ */
41187 
41188 #define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xFFFFFFFFU)
41189 #define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT (0U)
41190 /*! RXCTRLG - Rx Control Packets Good This field indicates the number of good control packets received. */
41191 #define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT)) & ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK)
41192 /*! @} */
41193 
41194 /*! @name MAC_TX_LPI_USEC_CNTR - Microseconds Tx LPI Asserted */
41195 /*! @{ */
41196 
41197 #define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK (0xFFFFFFFFU)
41198 #define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT (0U)
41199 /*! TXLPIUSC - Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted. */
41200 #define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT)) & ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK)
41201 /*! @} */
41202 
41203 /*! @name MAC_TX_LPI_TRAN_CNTR - Number of Times Tx LPI Asserted */
41204 /*! @{ */
41205 
41206 #define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK (0xFFFFFFFFU)
41207 #define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT (0U)
41208 /*! TXLPITRC - Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred. */
41209 #define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT)) & ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK)
41210 /*! @} */
41211 
41212 /*! @name MAC_RX_LPI_USEC_CNTR - Microseconds Rx LPI Sampled */
41213 /*! @{ */
41214 
41215 #define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK (0xFFFFFFFFU)
41216 #define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT (0U)
41217 /*! RXLPIUSC - Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted. */
41218 #define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT)) & ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK)
41219 /*! @} */
41220 
41221 /*! @name MAC_RX_LPI_TRAN_CNTR - Number of Times Rx LPI Entered */
41222 /*! @{ */
41223 
41224 #define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK (0xFFFFFFFFU)
41225 #define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT (0U)
41226 /*! RXLPITRC - Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred. */
41227 #define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT)) & ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK)
41228 /*! @} */
41229 
41230 /*! @name MAC_MMC_IPC_RX_INTERRUPT_MASK - MMC IPC Receive Interrupt Mask */
41231 /*! @{ */
41232 
41233 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK (0x1U)
41234 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT (0U)
41235 /*! RXIPV4GPIM - MMC Receive IPV4 Good Packet Counter Interrupt Mask Setting this bit masks the
41236  *    interrupt when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value.
41237  *  0b0..MMC Receive IPV4 Good Packet Counter Interrupt Mask is disabled
41238  *  0b1..MMC Receive IPV4 Good Packet Counter Interrupt Mask is enabled
41239  */
41240 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK)
41241 
41242 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK (0x2U)
41243 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT (1U)
41244 /*! RXIPV4HERPIM - MMC Receive IPV4 Header Error Packet Counter Interrupt Mask Setting this bit
41245  *    masks the interrupt when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the
41246  *    maximum value.
41247  *  0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is disabled
41248  *  0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is enabled
41249  */
41250 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK)
41251 
41252 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK (0x4U)
41253 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT (2U)
41254 /*! RXIPV4NOPAYPIM - MMC Receive IPV4 No Payload Packet Counter Interrupt Mask Setting this bit
41255  *    masks the interrupt when the rxipv4_nopay_pkts counter reaches half of the maximum value or the
41256  *    maximum value.
41257  *  0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is disabled
41258  *  0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is enabled
41259  */
41260 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK)
41261 
41262 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK (0x8U)
41263 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT (3U)
41264 /*! RXIPV4FRAGPIM - MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask Setting this bit masks
41265  *    the interrupt when the rxipv4_frag_pkts counter reaches half of the maximum value or the
41266  *    maximum value.
41267  *  0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is disabled
41268  *  0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is enabled
41269  */
41270 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK)
41271 
41272 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK (0x10U)
41273 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT (4U)
41274 /*! RXIPV4UDSBLPIM - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask Setting
41275  *    this bit masks the interrupt when the rxipv4_udsbl_pkts counter reaches half of the maximum
41276  *    value or the maximum value.
41277  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is disabled
41278  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is enabled
41279  */
41280 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK)
41281 
41282 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK (0x20U)
41283 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT (5U)
41284 /*! RXIPV6GPIM - MMC Receive IPV6 Good Packet Counter Interrupt Mask Setting this bit masks the
41285  *    interrupt when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value.
41286  *  0b0..MMC Receive IPV6 Good Packet Counter Interrupt Mask is disabled
41287  *  0b1..MMC Receive IPV6 Good Packet Counter Interrupt Mask is enabled
41288  */
41289 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK)
41290 
41291 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK (0x40U)
41292 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT (6U)
41293 /*! RXIPV6HERPIM - MMC Receive IPV6 Header Error Packet Counter Interrupt Mask Setting this bit
41294  *    masks the interrupt when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the
41295  *    maximum value.
41296  *  0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is disabled
41297  *  0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is enabled
41298  */
41299 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK)
41300 
41301 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK (0x80U)
41302 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT (7U)
41303 /*! RXIPV6NOPAYPIM - MMC Receive IPV6 No Payload Packet Counter Interrupt Mask Setting this bit
41304  *    masks the interrupt when the rxipv6_nopay_pkts counter reaches half of the maximum value or the
41305  *    maximum value.
41306  *  0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is disabled
41307  *  0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is enabled
41308  */
41309 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK)
41310 
41311 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK (0x100U)
41312 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT (8U)
41313 /*! RXUDPGPIM - MMC Receive UDP Good Packet Counter Interrupt Mask Setting this bit masks the
41314  *    interrupt when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value.
41315  *  0b0..MMC Receive UDP Good Packet Counter Interrupt Mask is disabled
41316  *  0b1..MMC Receive UDP Good Packet Counter Interrupt Mask is enabled
41317  */
41318 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK)
41319 
41320 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK (0x200U)
41321 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT (9U)
41322 /*! RXUDPERPIM - MMC Receive UDP Error Packet Counter Interrupt Mask Setting this bit masks the
41323  *    interrupt when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value.
41324  *  0b0..MMC Receive UDP Error Packet Counter Interrupt Mask is disabled
41325  *  0b1..MMC Receive UDP Error Packet Counter Interrupt Mask is enabled
41326  */
41327 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK)
41328 
41329 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK (0x400U)
41330 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT (10U)
41331 /*! RXTCPGPIM - MMC Receive TCP Good Packet Counter Interrupt Mask Setting this bit masks the
41332  *    interrupt when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value.
41333  *  0b0..MMC Receive TCP Good Packet Counter Interrupt Mask is disabled
41334  *  0b1..MMC Receive TCP Good Packet Counter Interrupt Mask is enabled
41335  */
41336 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK)
41337 
41338 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK (0x800U)
41339 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT (11U)
41340 /*! RXTCPERPIM - MMC Receive TCP Error Packet Counter Interrupt Mask Setting this bit masks the
41341  *    interrupt when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value.
41342  *  0b0..MMC Receive TCP Error Packet Counter Interrupt Mask is disabled
41343  *  0b1..MMC Receive TCP Error Packet Counter Interrupt Mask is enabled
41344  */
41345 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK)
41346 
41347 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK (0x1000U)
41348 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT (12U)
41349 /*! RXICMPGPIM - MMC Receive ICMP Good Packet Counter Interrupt Mask Setting this bit masks the
41350  *    interrupt when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value.
41351  *  0b0..MMC Receive ICMP Good Packet Counter Interrupt Mask is disabled
41352  *  0b1..MMC Receive ICMP Good Packet Counter Interrupt Mask is enabled
41353  */
41354 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK)
41355 
41356 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK (0x2000U)
41357 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT (13U)
41358 /*! RXICMPERPIM - MMC Receive ICMP Error Packet Counter Interrupt Mask Setting this bit masks the
41359  *    interrupt when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum
41360  *    value.
41361  *  0b0..MMC Receive ICMP Error Packet Counter Interrupt Mask is disabled
41362  *  0b1..MMC Receive ICMP Error Packet Counter Interrupt Mask is enabled
41363  */
41364 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK)
41365 
41366 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK (0x10000U)
41367 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT (16U)
41368 /*! RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask Setting this bit masks the
41369  *    interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.
41370  *  0b0..MMC Receive IPV4 Good Octet Counter Interrupt Mask is disabled
41371  *  0b1..MMC Receive IPV4 Good Octet Counter Interrupt Mask is enabled
41372  */
41373 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK)
41374 
41375 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK (0x20000U)
41376 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT (17U)
41377 /*! RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask Setting this bit masks
41378  *    the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the
41379  *    maximum value.
41380  *  0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is disabled
41381  *  0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is enabled
41382  */
41383 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK)
41384 
41385 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK (0x40000U)
41386 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT (18U)
41387 /*! RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask Setting this bit masks
41388  *    the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the
41389  *    maximum value.
41390  *  0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is disabled
41391  *  0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is enabled
41392  */
41393 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK)
41394 
41395 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK (0x80000U)
41396 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT (19U)
41397 /*! RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask Setting this bit masks
41398  *    the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the
41399  *    maximum value.
41400  *  0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is disabled
41401  *  0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is enabled
41402  */
41403 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK)
41404 
41405 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK (0x100000U)
41406 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT (20U)
41407 /*! RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask Setting
41408  *    this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum
41409  *    value or the maximum value.
41410  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is disabled
41411  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is enabled
41412  */
41413 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK)
41414 
41415 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK (0x200000U)
41416 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT (21U)
41417 /*! RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the
41418  *    interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.
41419  *  0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled
41420  *  0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled
41421  */
41422 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK)
41423 
41424 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK (0x400000U)
41425 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT (22U)
41426 /*! RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the
41427  *    interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum
41428  *    value.
41429  *  0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled
41430  *  0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled
41431  */
41432 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK)
41433 
41434 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK (0x800000U)
41435 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT (23U)
41436 /*! RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask Setting this bit
41437  *    masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the
41438  *    maximum value.
41439  *  0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is disabled
41440  *  0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is enabled
41441  */
41442 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK)
41443 
41444 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK (0x1000000U)
41445 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT (24U)
41446 /*! RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask Setting this bit masks the
41447  *    interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum
41448  *    value.
41449  *  0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is disabled
41450  *  0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is enabled
41451  */
41452 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK)
41453 
41454 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK (0x2000000U)
41455 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT (25U)
41456 /*! RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask Setting this bit masks the
41457  *    interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value.
41458  *  0b0..MMC Receive UDP Good Octet Counter Interrupt Mask is disabled
41459  *  0b1..MMC Receive UDP Good Octet Counter Interrupt Mask is enabled
41460  */
41461 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK)
41462 
41463 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK (0x4000000U)
41464 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT (26U)
41465 /*! RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask Setting this bit masks the
41466  *    interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.
41467  *  0b0..MMC Receive TCP Good Octet Counter Interrupt Mask is disabled
41468  *  0b1..MMC Receive TCP Good Octet Counter Interrupt Mask is enabled
41469  */
41470 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK)
41471 
41472 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK (0x8000000U)
41473 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT (27U)
41474 /*! RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask Setting this bit masks the
41475  *    interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value.
41476  *  0b0..MMC Receive TCP Error Octet Counter Interrupt Mask is disabled
41477  *  0b1..MMC Receive TCP Error Octet Counter Interrupt Mask is enabled
41478  */
41479 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK)
41480 
41481 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK (0x10000000U)
41482 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT (28U)
41483 /*! RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask Setting this bit masks the
41484  *    interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.
41485  *  0b0..MMC Receive ICMP Good Octet Counter Interrupt Mask is disabled
41486  *  0b1..MMC Receive ICMP Good Octet Counter Interrupt Mask is enabled
41487  */
41488 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK)
41489 
41490 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK (0x20000000U)
41491 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT (29U)
41492 /*! RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask Setting this bit masks the
41493  *    interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum
41494  *    value.
41495  *  0b0..MMC Receive ICMP Error Octet Counter Interrupt Mask is disabled
41496  *  0b1..MMC Receive ICMP Error Octet Counter Interrupt Mask is enabled
41497  */
41498 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK)
41499 /*! @} */
41500 
41501 /*! @name MAC_MMC_IPC_RX_INTERRUPT - MMC IPC Receive Interrupt */
41502 /*! @{ */
41503 
41504 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK (0x1U)
41505 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT (0U)
41506 /*! RXIPV4GPIS - MMC Receive IPV4 Good Packet Counter Interrupt Status This bit is set when the
41507  *    rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value.
41508  *  0b1..MMC Receive IPV4 Good Packet Counter Interrupt Status detected
41509  *  0b0..MMC Receive IPV4 Good Packet Counter Interrupt Status not detected
41510  */
41511 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK)
41512 
41513 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK (0x2U)
41514 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT (1U)
41515 /*! RXIPV4HERPIS - MMC Receive IPV4 Header Error Packet Counter Interrupt Status This bit is set
41516  *    when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value.
41517  *  0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Status detected
41518  *  0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Status not detected
41519  */
41520 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK)
41521 
41522 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK (0x4U)
41523 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT (2U)
41524 /*! RXIPV4NOPAYPIS - MMC Receive IPV4 No Payload Packet Counter Interrupt Status This bit is set
41525  *    when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value.
41526  *  0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Status detected
41527  *  0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Status not detected
41528  */
41529 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK)
41530 
41531 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK (0x8U)
41532 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT (3U)
41533 /*! RXIPV4FRAGPIS - MMC Receive IPV4 Fragmented Packet Counter Interrupt Status This bit is set when
41534  *    the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value.
41535  *  0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status detected
41536  *  0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status not detected
41537  */
41538 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK)
41539 
41540 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK (0x10U)
41541 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT (4U)
41542 /*! RXIPV4UDSBLPIS - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status This bit
41543  *    is set when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum
41544  *    value.
41545  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status detected
41546  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status not detected
41547  */
41548 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK)
41549 
41550 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK (0x20U)
41551 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT (5U)
41552 /*! RXIPV6GPIS - MMC Receive IPV6 Good Packet Counter Interrupt Status This bit is set when the
41553  *    rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value.
41554  *  0b1..MMC Receive IPV6 Good Packet Counter Interrupt Status detected
41555  *  0b0..MMC Receive IPV6 Good Packet Counter Interrupt Status not detected
41556  */
41557 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK)
41558 
41559 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK (0x40U)
41560 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT (6U)
41561 /*! RXIPV6HERPIS - MMC Receive IPV6 Header Error Packet Counter Interrupt Status This bit is set
41562  *    when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value.
41563  *  0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Status detected
41564  *  0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Status not detected
41565  */
41566 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK)
41567 
41568 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK (0x80U)
41569 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT (7U)
41570 /*! RXIPV6NOPAYPIS - MMC Receive IPV6 No Payload Packet Counter Interrupt Status This bit is set
41571  *    when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value.
41572  *  0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Status detected
41573  *  0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Status not detected
41574  */
41575 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK)
41576 
41577 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK (0x100U)
41578 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT (8U)
41579 /*! RXUDPGPIS - MC Receive UDP Good Packet Counter Interrupt Status This bit is set when the
41580  *    rxudp_gd_pkts counter reaches half of the maximum value or the maximum value.
41581  *  0b1..MMC Receive UDP Good Packet Counter Interrupt Status detected
41582  *  0b0..MMC Receive UDP Good Packet Counter Interrupt Status not detected
41583  */
41584 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK)
41585 
41586 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK (0x200U)
41587 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT (9U)
41588 /*! RXUDPERPIS - MMC Receive UDP Error Packet Counter Interrupt Status This bit is set when the
41589  *    rxudp_err_pkts counter reaches half of the maximum value or the maximum value.
41590  *  0b1..MMC Receive UDP Error Packet Counter Interrupt Status detected
41591  *  0b0..MMC Receive UDP Error Packet Counter Interrupt Status not detected
41592  */
41593 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK)
41594 
41595 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK (0x400U)
41596 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT (10U)
41597 /*! RXTCPGPIS - MMC Receive TCP Good Packet Counter Interrupt Status This bit is set when the
41598  *    rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value.
41599  *  0b1..MMC Receive TCP Good Packet Counter Interrupt Status detected
41600  *  0b0..MMC Receive TCP Good Packet Counter Interrupt Status not detected
41601  */
41602 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK)
41603 
41604 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK (0x800U)
41605 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT (11U)
41606 /*! RXTCPERPIS - MMC Receive TCP Error Packet Counter Interrupt Status This bit is set when the
41607  *    rxtcp_err_pkts counter reaches half of the maximum value or the maximum value.
41608  *  0b1..MMC Receive TCP Error Packet Counter Interrupt Status detected
41609  *  0b0..MMC Receive TCP Error Packet Counter Interrupt Status not detected
41610  */
41611 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK)
41612 
41613 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK (0x1000U)
41614 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT (12U)
41615 /*! RXICMPGPIS - MMC Receive ICMP Good Packet Counter Interrupt Status This bit is set when the
41616  *    rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value.
41617  *  0b1..MMC Receive ICMP Good Packet Counter Interrupt Status detected
41618  *  0b0..MMC Receive ICMP Good Packet Counter Interrupt Status not detected
41619  */
41620 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK)
41621 
41622 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK (0x2000U)
41623 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT (13U)
41624 /*! RXICMPERPIS - MMC Receive ICMP Error Packet Counter Interrupt Status This bit is set when the
41625  *    rxicmp_err_pkts counter reaches half of the maximum value or the maximum value.
41626  *  0b1..MMC Receive ICMP Error Packet Counter Interrupt Status detected
41627  *  0b0..MMC Receive ICMP Error Packet Counter Interrupt Status not detected
41628  */
41629 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK)
41630 
41631 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK (0x10000U)
41632 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT (16U)
41633 /*! RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the
41634  *    rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.
41635  *  0b1..MMC Receive IPV4 Good Octet Counter Interrupt Status detected
41636  *  0b0..MMC Receive IPV4 Good Octet Counter Interrupt Status not detected
41637  */
41638 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK)
41639 
41640 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK (0x20000U)
41641 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT (17U)
41642 /*! RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when
41643  *    the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value.
41644  *  0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Status detected
41645  *  0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Status not detected
41646  */
41647 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK)
41648 
41649 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK (0x40000U)
41650 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT (18U)
41651 /*! RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when
41652  *    the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value.
41653  *  0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Status detected
41654  *  0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Status not detected
41655  */
41656 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK)
41657 
41658 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK (0x80000U)
41659 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT (19U)
41660 /*! RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when
41661  *    the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value.
41662  *  0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status detected
41663  *  0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status not detected
41664  */
41665 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK)
41666 
41667 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK (0x100000U)
41668 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT (20U)
41669 /*! RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit
41670  *    is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum
41671  *    value.
41672  *  0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status detected
41673  *  0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status not detected
41674  */
41675 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK)
41676 
41677 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK (0x200000U)
41678 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT (21U)
41679 /*! RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the
41680  *    rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.
41681  *  0b1..MMC Receive IPV6 Good Octet Counter Interrupt Status detected
41682  *  0b0..MMC Receive IPV6 Good Octet Counter Interrupt Status not detected
41683  */
41684 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK)
41685 
41686 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK (0x400000U)
41687 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT (22U)
41688 /*! RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when
41689  *    the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value.
41690  *  0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Status detected
41691  *  0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Status not detected
41692  */
41693 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK)
41694 
41695 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK (0x800000U)
41696 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT (23U)
41697 /*! RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when
41698  *    the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value.
41699  *  0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Status detected
41700  *  0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Status not detected
41701  */
41702 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK)
41703 
41704 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK (0x1000000U)
41705 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT (24U)
41706 /*! RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the
41707  *    rxudp_gd_octets counter reaches half of the maximum value or the maximum value.
41708  *  0b1..MMC Receive UDP Good Octet Counter Interrupt Status detected
41709  *  0b0..MMC Receive UDP Good Octet Counter Interrupt Status not detected
41710  */
41711 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK)
41712 
41713 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK (0x2000000U)
41714 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT (25U)
41715 /*! RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the
41716  *    rxudp_err_octets counter reaches half of the maximum value or the maximum value.
41717  *  0b1..MMC Receive UDP Error Octet Counter Interrupt Status detected
41718  *  0b0..MMC Receive UDP Error Octet Counter Interrupt Status not detected
41719  */
41720 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK)
41721 
41722 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK (0x4000000U)
41723 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT (26U)
41724 /*! RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the
41725  *    rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.
41726  *  0b1..MMC Receive TCP Good Octet Counter Interrupt Status detected
41727  *  0b0..MMC Receive TCP Good Octet Counter Interrupt Status not detected
41728  */
41729 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK)
41730 
41731 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK (0x8000000U)
41732 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT (27U)
41733 /*! RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the
41734  *    rxtcp_err_octets counter reaches half of the maximum value or the maximum value.
41735  *  0b1..MMC Receive TCP Error Octet Counter Interrupt Status detected
41736  *  0b0..MMC Receive TCP Error Octet Counter Interrupt Status not detected
41737  */
41738 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK)
41739 
41740 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK (0x10000000U)
41741 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT (28U)
41742 /*! RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the
41743  *    rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.
41744  *  0b1..MMC Receive ICMP Good Octet Counter Interrupt Status detected
41745  *  0b0..MMC Receive ICMP Good Octet Counter Interrupt Status not detected
41746  */
41747 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK)
41748 
41749 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK (0x20000000U)
41750 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT (29U)
41751 /*! RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the
41752  *    rxicmp_err_octets counter reaches half of the maximum value or the maximum value.
41753  *  0b1..MMC Receive ICMP Error Octet Counter Interrupt Status detected
41754  *  0b0..MMC Receive ICMP Error Octet Counter Interrupt Status not detected
41755  */
41756 #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK)
41757 /*! @} */
41758 
41759 /*! @name MAC_RXIPV4_GOOD_PACKETS - Good IPv4 Datagrams Received */
41760 /*! @{ */
41761 
41762 #define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK (0xFFFFFFFFU)
41763 #define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT (0U)
41764 /*! RXIPV4GDPKT - RxIPv4 Good Packets This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload. */
41765 #define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK)
41766 /*! @} */
41767 
41768 /*! @name MAC_RXIPV4_HEADER_ERROR_PACKETS - IPv4 Datagrams Received with Header Errors */
41769 /*! @{ */
41770 
41771 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK (0xFFFFFFFFU)
41772 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT (0U)
41773 /*! RXIPV4HDRERRPKT - RxIPv4 Header Error Packets This field indicates the number of IPv4 datagrams
41774  *    received with header (checksum, length, or version mismatch) errors.
41775  */
41776 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK)
41777 /*! @} */
41778 
41779 /*! @name MAC_RXIPV4_NO_PAYLOAD_PACKETS - IPv4 Datagrams Received with No Payload */
41780 /*! @{ */
41781 
41782 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK (0xFFFFFFFFU)
41783 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT (0U)
41784 /*! RXIPV4NOPAYPKT - RxIPv4 Payload Packets This field indicates the number of IPv4 datagram packets
41785  *    received that did not have a TCP, UDP, or ICMP payload.
41786  */
41787 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK)
41788 /*! @} */
41789 
41790 /*! @name MAC_RXIPV4_FRAGMENTED_PACKETS - IPv4 Datagrams Received with Fragmentation */
41791 /*! @{ */
41792 
41793 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK (0xFFFFFFFFU)
41794 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT (0U)
41795 /*! RXIPV4FRAGPKT - RxIPv4 Fragmented Packets This field indicates the number of good IPv4 datagrams received with fragmentation. */
41796 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK)
41797 /*! @} */
41798 
41799 /*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS - IPv4 Datagrams Received with UDP Checksum Disabled */
41800 /*! @{ */
41801 
41802 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK (0xFFFFFFFFU)
41803 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT (0U)
41804 /*! RXIPV4UDSBLPKT - RxIPv4 UDP Checksum Disabled Packets This field indicates the number of good
41805  *    IPv4 datagrams received that had a UDP payload with checksum disabled.
41806  */
41807 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK)
41808 /*! @} */
41809 
41810 /*! @name MAC_RXIPV6_GOOD_PACKETS - Good IPv6 Datagrams Received */
41811 /*! @{ */
41812 
41813 #define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK (0xFFFFFFFFU)
41814 #define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT (0U)
41815 /*! RXIPV6GDPKT - RxIPv6 Good Packets This field indicates the number of good IPv6 datagrams received with the TCP, UDP, or ICMP payload. */
41816 #define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK)
41817 /*! @} */
41818 
41819 /*! @name MAC_RXIPV6_HEADER_ERROR_PACKETS - IPv6 Datagrams Received with Header Errors */
41820 /*! @{ */
41821 
41822 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK (0xFFFFFFFFU)
41823 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT (0U)
41824 /*! RXIPV6HDRERRPKT - RxIPv6 Header Error Packets This field indicates the number of IPv6 datagrams
41825  *    received with header (length or version mismatch) errors.
41826  */
41827 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK)
41828 /*! @} */
41829 
41830 /*! @name MAC_RXIPV6_NO_PAYLOAD_PACKETS - IPv6 Datagrams Received with No Payload */
41831 /*! @{ */
41832 
41833 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK (0xFFFFFFFFU)
41834 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT (0U)
41835 /*! RXIPV6NOPAYPKT - RxIPv6 Payload Packets This field indicates the number of IPv6 datagram packets
41836  *    received that did not have a TCP, UDP, or ICMP payload.
41837  */
41838 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK)
41839 /*! @} */
41840 
41841 /*! @name MAC_RXUDP_GOOD_PACKETS - IPv6 Datagrams Received with Good UDP */
41842 /*! @{ */
41843 
41844 #define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK (0xFFFFFFFFU)
41845 #define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT (0U)
41846 /*! RXUDPGDPKT - RxUDP Good Packets This field indicates the number of good IP datagrams received with a good UDP payload. */
41847 #define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK)
41848 /*! @} */
41849 
41850 /*! @name MAC_RXUDP_ERROR_PACKETS - IPv6 Datagrams Received with UDP Checksum Error */
41851 /*! @{ */
41852 
41853 #define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK (0xFFFFFFFFU)
41854 #define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT (0U)
41855 /*! RXUDPERRPKT - RxUDP Error Packets This field indicates the number of good IP datagrams received
41856  *    whose UDP payload has a checksum error.
41857  */
41858 #define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK)
41859 /*! @} */
41860 
41861 /*! @name MAC_RXTCP_GOOD_PACKETS - IPv6 Datagrams Received with Good TCP Payload */
41862 /*! @{ */
41863 
41864 #define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK (0xFFFFFFFFU)
41865 #define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT (0U)
41866 /*! RXTCPGDPKT - RxTCP Good Packets This field indicates the number of good IP datagrams received with a good TCP payload. */
41867 #define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK)
41868 /*! @} */
41869 
41870 /*! @name MAC_RXTCP_ERROR_PACKETS - IPv6 Datagrams Received with TCP Checksum Error */
41871 /*! @{ */
41872 
41873 #define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK (0xFFFFFFFFU)
41874 #define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT (0U)
41875 /*! RXTCPERRPKT - RxTCP Error Packets This field indicates the number of good IP datagrams received
41876  *    whose TCP payload has a checksum error.
41877  */
41878 #define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK)
41879 /*! @} */
41880 
41881 /*! @name MAC_RXICMP_GOOD_PACKETS - IPv6 Datagrams Received with Good ICMP Payload */
41882 /*! @{ */
41883 
41884 #define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK (0xFFFFFFFFU)
41885 #define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT (0U)
41886 /*! RXICMPGDPKT - RxICMP Good Packets This field indicates the number of good IP datagrams received with a good ICMP payload. */
41887 #define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK)
41888 /*! @} */
41889 
41890 /*! @name MAC_RXICMP_ERROR_PACKETS - IPv6 Datagrams Received with ICMP Checksum Error */
41891 /*! @{ */
41892 
41893 #define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK (0xFFFFFFFFU)
41894 #define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT (0U)
41895 /*! RXICMPERRPKT - RxICMP Error Packets This field indicates the number of good IP datagrams
41896  *    received whose ICMP payload has a checksum error.
41897  */
41898 #define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK)
41899 /*! @} */
41900 
41901 /*! @name MAC_RXIPV4_GOOD_OCTETS - Good Bytes Received in IPv4 Datagrams */
41902 /*! @{ */
41903 
41904 #define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK (0xFFFFFFFFU)
41905 #define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT (0U)
41906 /*! RXIPV4GDOCT - RxIPv4 Good Octets This field indicates the number of bytes received in good IPv4
41907  *    datagrams encapsulating TCP, UDP, or ICMP data.
41908  */
41909 #define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK)
41910 /*! @} */
41911 
41912 /*! @name MAC_RXIPV4_HEADER_ERROR_OCTETS - Bytes Received in IPv4 Datagrams with Header Errors */
41913 /*! @{ */
41914 
41915 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK (0xFFFFFFFFU)
41916 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT (0U)
41917 /*! RXIPV4HDRERROCT - RxIPv4 Header Error Octets This field indicates the number of bytes received
41918  *    in IPv4 datagrams with header errors (checksum, length, version mismatch).
41919  */
41920 #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK)
41921 /*! @} */
41922 
41923 /*! @name MAC_RXIPV4_NO_PAYLOAD_OCTETS - Bytes Received in IPv4 Datagrams with No Payload */
41924 /*! @{ */
41925 
41926 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK (0xFFFFFFFFU)
41927 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT (0U)
41928 /*! RXIPV4NOPAYOCT - RxIPv4 Payload Octets This field indicates the number of bytes received in IPv4
41929  *    datagrams that did not have a TCP, UDP, or ICMP payload.
41930  */
41931 #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK)
41932 /*! @} */
41933 
41934 /*! @name MAC_RXIPV4_FRAGMENTED_OCTETS - Bytes Received in Fragmented IPv4 Datagrams */
41935 /*! @{ */
41936 
41937 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK (0xFFFFFFFFU)
41938 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT (0U)
41939 /*! RXIPV4FRAGOCT - RxIPv4 Fragmented Octets This field indicates the number of bytes received in fragmented IPv4 datagrams. */
41940 #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK)
41941 /*! @} */
41942 
41943 /*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS - Bytes Received with UDP Checksum Disabled */
41944 /*! @{ */
41945 
41946 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK (0xFFFFFFFFU)
41947 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT (0U)
41948 /*! RXIPV4UDSBLOCT - RxIPv4 UDP Checksum Disable Octets This field indicates the number of bytes
41949  *    received in a UDP segment that had the UDP checksum disabled.
41950  */
41951 #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK)
41952 /*! @} */
41953 
41954 /*! @name MAC_RXIPV6_GOOD_OCTETS - Bytes Received in Good IPv6 Datagrams */
41955 /*! @{ */
41956 
41957 #define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK (0xFFFFFFFFU)
41958 #define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT (0U)
41959 /*! RXIPV6GDOCT - RxIPv6 Good Octets This field indicates the number of bytes received in good IPv6
41960  *    datagrams encapsulating TCP, UDP, or ICMP data.
41961  */
41962 #define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK)
41963 /*! @} */
41964 
41965 /*! @name MAC_RXIPV6_HEADER_ERROR_OCTETS - Bytes Received in IPv6 Datagrams with Data Errors */
41966 /*! @{ */
41967 
41968 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK (0xFFFFFFFFU)
41969 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT (0U)
41970 /*! RXIPV6HDRERROCT - RxIPv6 Header Error Octets This field indicates the number of bytes received
41971  *    in IPv6 datagrams with header errors (length, version mismatch).
41972  */
41973 #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK)
41974 /*! @} */
41975 
41976 /*! @name MAC_RXIPV6_NO_PAYLOAD_OCTETS - Bytes Received in IPv6 Datagrams with No Payload */
41977 /*! @{ */
41978 
41979 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK (0xFFFFFFFFU)
41980 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT (0U)
41981 /*! RXIPV6NOPAYOCT - RxIPv6 Payload Octets This field indicates the number of bytes received in IPv6
41982  *    datagrams that did not have a TCP, UDP, or ICMP payload.
41983  */
41984 #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK)
41985 /*! @} */
41986 
41987 /*! @name MAC_RXUDP_GOOD_OCTETS - Bytes Received in Good UDP Segment */
41988 /*! @{ */
41989 
41990 #define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK (0xFFFFFFFFU)
41991 #define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT (0U)
41992 /*! RXUDPGDOCT - RxUDP Good Octets This field indicates the number of bytes received in a good UDP segment. */
41993 #define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK)
41994 /*! @} */
41995 
41996 /*! @name MAC_RXUDP_ERROR_OCTETS - Bytes Received in UDP Segment with Checksum Errors */
41997 /*! @{ */
41998 
41999 #define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK (0xFFFFFFFFU)
42000 #define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT (0U)
42001 /*! RXUDPERROCT - RxUDP Error Octets This field indicates the number of bytes received in a UDP segment that had checksum errors. */
42002 #define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK)
42003 /*! @} */
42004 
42005 /*! @name MAC_RXTCP_GOOD_OCTETS - Bytes Received in Good TCP Segment */
42006 /*! @{ */
42007 
42008 #define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK (0xFFFFFFFFU)
42009 #define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT (0U)
42010 /*! RXTCPGDOCT - RxTCP Good Octets This field indicates the number of bytes received in a good TCP segment. */
42011 #define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK)
42012 /*! @} */
42013 
42014 /*! @name MAC_RXTCP_ERROR_OCTETS - Bytes Received in TCP Segment with Checksum Errors */
42015 /*! @{ */
42016 
42017 #define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK (0xFFFFFFFFU)
42018 #define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT (0U)
42019 /*! RXTCPERROCT - RxTCP Error Octets This field indicates the number of bytes received in a TCP segment that had checksum errors. */
42020 #define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK)
42021 /*! @} */
42022 
42023 /*! @name MAC_RXICMP_GOOD_OCTETS - Bytes Received in Good ICMP Segment */
42024 /*! @{ */
42025 
42026 #define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK (0xFFFFFFFFU)
42027 #define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT (0U)
42028 /*! RXICMPGDOCT - RxICMP Good Octets This field indicates the number of bytes received in a good ICMP segment. */
42029 #define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK)
42030 /*! @} */
42031 
42032 /*! @name MAC_RXICMP_ERROR_OCTETS - Bytes Received in ICMP Segment with Checksum Errors */
42033 /*! @{ */
42034 
42035 #define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK (0xFFFFFFFFU)
42036 #define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT (0U)
42037 /*! RXICMPERROCT - RxICMP Error Octets This field indicates the number of bytes received in a ICMP segment that had checksum errors. */
42038 #define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK)
42039 /*! @} */
42040 
42041 /*! @name MAC_MMC_FPE_TX_INTERRUPT - MMC FPE Transmit Interrupt */
42042 /*! @{ */
42043 
42044 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK (0x1U)
42045 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT (0U)
42046 /*! FCIS - MMC Tx FPE Fragment Counter Interrupt status This bit is set when the
42047  *    Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
42048  *  0b1..MMC Tx FPE Fragment Counter Interrupt status detected
42049  *  0b0..MMC Tx FPE Fragment Counter Interrupt status not detected
42050  */
42051 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK)
42052 
42053 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK (0x2U)
42054 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT (1U)
42055 /*! HRCIS - MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr
42056  *    counter reaches half of the maximum value or the maximum value.
42057  *  0b1..MMC Tx Hold Request Counter Interrupt Status detected
42058  *  0b0..MMC Tx Hold Request Counter Interrupt Status not detected
42059  */
42060 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK)
42061 /*! @} */
42062 
42063 /*! @name MAC_MMC_FPE_TX_INTERRUPT_MASK - MMC FPE Transmit Mask Interrupt */
42064 /*! @{ */
42065 
42066 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK (0x1U)
42067 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT (0U)
42068 /*! FCIM - MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when
42069  *    the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
42070  *  0b0..MMC Transmit Fragment Counter Interrupt Mask is disabled
42071  *  0b1..MMC Transmit Fragment Counter Interrupt Mask is enabled
42072  */
42073 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK)
42074 
42075 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK (0x2U)
42076 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT (1U)
42077 /*! HRCIM - MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt
42078  *    when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value.
42079  *  0b0..MMC Transmit Hold Request Counter Interrupt Mask is disabled
42080  *  0b1..MMC Transmit Hold Request Counter Interrupt Mask is enabled
42081  */
42082 #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK)
42083 /*! @} */
42084 
42085 /*! @name MAC_MMC_TX_FPE_FRAGMENT_CNTR - MMC FPE Transmitted Fragment Counter */
42086 /*! @{ */
42087 
42088 #define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xFFFFFFFFU)
42089 #define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT (0U)
42090 /*! TXFFC - Tx FPE Fragment counter This field indicates the number of additional mPackets that has
42091  *    been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled
42092  *    during FPE Enabled configuration.
42093  */
42094 #define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT)) & ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK)
42095 /*! @} */
42096 
42097 /*! @name MAC_MMC_TX_HOLD_REQ_CNTR - MMC FPE Transmitted Hold Request Counter */
42098 /*! @{ */
42099 
42100 #define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xFFFFFFFFU)
42101 #define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT (0U)
42102 /*! TXHRC - Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC. */
42103 #define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT)) & ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK)
42104 /*! @} */
42105 
42106 /*! @name MAC_MMC_FPE_RX_INTERRUPT - MMC FPE Receive Interrupt */
42107 /*! @{ */
42108 
42109 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK (0x1U)
42110 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT (0U)
42111 /*! PAECIS - MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the
42112  *    Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value.
42113  *  0b1..MMC Rx Packet Assembly Error Counter Interrupt Status detected
42114  *  0b0..MMC Rx Packet Assembly Error Counter Interrupt Status not detected
42115  */
42116 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK)
42117 
42118 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK (0x2U)
42119 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT (1U)
42120 /*! PSECIS - MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the
42121  *    Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value.
42122  *  0b1..MMC Rx Packet SMD Error Counter Interrupt Status detected
42123  *  0b0..MMC Rx Packet SMD Error Counter Interrupt Status not detected
42124  */
42125 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK)
42126 
42127 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK (0x4U)
42128 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT (2U)
42129 /*! PAOCIS - MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the
42130  *    Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value.
42131  *  0b1..MMC Rx Packet Assembly OK Counter Interrupt Status detected
42132  *  0b0..MMC Rx Packet Assembly OK Counter Interrupt Status not detected
42133  */
42134 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK)
42135 
42136 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK (0x8U)
42137 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT (3U)
42138 /*! FCIS - MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the
42139  *    Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
42140  *  0b1..MMC Rx FPE Fragment Counter Interrupt Status detected
42141  *  0b0..MMC Rx FPE Fragment Counter Interrupt Status not detected
42142  */
42143 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK)
42144 /*! @} */
42145 
42146 /*! @name MAC_MMC_FPE_RX_INTERRUPT_MASK - MMC FPE Receive Interrupt Mask */
42147 /*! @{ */
42148 
42149 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK (0x1U)
42150 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT (0U)
42151 /*! PAECIM - MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the
42152  *    interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the
42153  *    maximum value.
42154  *  0b0..MMC Rx Packet Assembly Error Counter Interrupt Mask is disabled
42155  *  0b1..MMC Rx Packet Assembly Error Counter Interrupt Mask is enabled
42156  */
42157 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK)
42158 
42159 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK (0x2U)
42160 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT (1U)
42161 /*! PSECIM - MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt
42162  *    when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value.
42163  *  0b0..MMC Rx Packet SMD Error Counter Interrupt Mask is disabled
42164  *  0b1..MMC Rx Packet SMD Error Counter Interrupt Mask is enabled
42165  */
42166 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK)
42167 
42168 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK (0x4U)
42169 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT (2U)
42170 /*! PAOCIM - MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt
42171  *    when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum
42172  *    value.
42173  *  0b0..MMC Rx Packet Assembly OK Counter Interrupt Mask is disabled
42174  *  0b1..MMC Rx Packet Assembly OK Counter Interrupt Mask is enabled
42175  */
42176 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK)
42177 
42178 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK (0x8U)
42179 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT (3U)
42180 /*! FCIM - MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the
42181  *    Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
42182  *  0b0..MMC Rx FPE Fragment Counter Interrupt Mask is disabled
42183  *  0b1..MMC Rx FPE Fragment Counter Interrupt Mask is enabled
42184  */
42185 #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK)
42186 /*! @} */
42187 
42188 /*! @name MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR - MMC Receive Packet Reassembly Error Counter */
42189 /*! @{ */
42190 
42191 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xFFFFFFFFU)
42192 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT (0U)
42193 /*! PAEC - Rx Packet Assembly Error Counter This field indicates the number of MAC frames with
42194  *    reassembly errors on the Receiver, due to mismatch in the Fragment Count value.
42195  */
42196 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK)
42197 /*! @} */
42198 
42199 /*! @name MAC_MMC_RX_PACKET_SMD_ERR_CNTR - MMC Receive Packet SMD Error Counter */
42200 /*! @{ */
42201 
42202 #define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xFFFFFFFFU)
42203 #define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT (0U)
42204 /*! PSEC - Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to
42205  *    unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there
42206  *    was no preceding preempted frame.
42207  */
42208 #define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK)
42209 /*! @} */
42210 
42211 /*! @name MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR - MMC Receive Packet Successful Reassembly Counter */
42212 /*! @{ */
42213 
42214 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xFFFFFFFFU)
42215 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT (0U)
42216 /*! PAOC - Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were
42217  *    successfully reassembled and delivered to MAC.
42218  */
42219 #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK)
42220 /*! @} */
42221 
42222 /*! @name MAC_MMC_RX_FPE_FRAGMENT_CNTR - MMC FPE Received Fragment Counter */
42223 /*! @{ */
42224 
42225 #define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xFFFFFFFFU)
42226 #define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT (0U)
42227 /*! FFC - Rx FPE Fragment Counter This field indicates the number of additional mPackets received
42228  *    due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE
42229  *    Enabled configuration.
42230  */
42231 #define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT)) & ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK)
42232 /*! @} */
42233 
42234 /*! @name MAC_L3_L4_CONTROL0 - Layer 3 and Layer 4 Control of Filter 0 */
42235 /*! @{ */
42236 
42237 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK  (0x1U)
42238 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT (0U)
42239 /*! L3PEN0 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
42240  *    Address matching is enabled for IPv6 packets.
42241  *  0b0..Layer 3 Protocol is disabled
42242  *  0b1..Layer 3 Protocol is enabled
42243  */
42244 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK)
42245 
42246 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK  (0x4U)
42247 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT (2U)
42248 /*! L3SAM0 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
42249  *  0b0..Layer 3 IP SA Match is disabled
42250  *  0b1..Layer 3 IP SA Match is enabled
42251  */
42252 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK)
42253 
42254 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK (0x8U)
42255 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT (3U)
42256 /*! L3SAIM0 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
42257  *    field is enabled for inverse matching.
42258  *  0b0..Layer 3 IP SA Inverse Match is disabled
42259  *  0b1..Layer 3 IP SA Inverse Match is enabled
42260  */
42261 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK)
42262 
42263 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK  (0x10U)
42264 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT (4U)
42265 /*! L3DAM0 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
42266  *  0b0..Layer 3 IP DA Match is disabled
42267  *  0b1..Layer 3 IP DA Match is enabled
42268  */
42269 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK)
42270 
42271 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK (0x20U)
42272 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT (5U)
42273 /*! L3DAIM0 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
42274  *    Address field is enabled for inverse matching.
42275  *  0b0..Layer 3 IP DA Inverse Match is disabled
42276  *  0b1..Layer 3 IP DA Inverse Match is enabled
42277  */
42278 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK)
42279 
42280 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x7C0U)
42281 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT (6U)
42282 /*! L3HSBM0 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
42283  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
42284  */
42285 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK)
42286 
42287 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0xF800U)
42288 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT (11U)
42289 /*! L3HDBM0 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
42290  *    bits of IP Destination Address that are matched in the IPv4 packets.
42291  */
42292 #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK)
42293 
42294 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK  (0x10000U)
42295 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT (16U)
42296 /*! L4PEN0 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
42297  *    fields of UDP packets are used for matching.
42298  *  0b0..Layer 4 Protocol is disabled
42299  *  0b1..Layer 4 Protocol is enabled
42300  */
42301 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK)
42302 
42303 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK  (0x40000U)
42304 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT (18U)
42305 /*! L4SPM0 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
42306  *  0b0..Layer 4 Source Port Match is disabled
42307  *  0b1..Layer 4 Source Port Match is enabled
42308  */
42309 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK)
42310 
42311 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK (0x80000U)
42312 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT (19U)
42313 /*! L4SPIM0 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
42314  *    number field is enabled for inverse matching.
42315  *  0b0..Layer 4 Source Port Inverse Match is disabled
42316  *  0b1..Layer 4 Source Port Inverse Match is enabled
42317  */
42318 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK)
42319 
42320 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK  (0x100000U)
42321 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT (20U)
42322 /*! L4DPM0 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
42323  *    Port number field is enabled for matching.
42324  *  0b0..Layer 4 Destination Port Match is disabled
42325  *  0b1..Layer 4 Destination Port Match is enabled
42326  */
42327 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK)
42328 
42329 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK (0x200000U)
42330 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT (21U)
42331 /*! L4DPIM0 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
42332  *    Destination Port number field is enabled for inverse matching.
42333  *  0b0..Layer 4 Destination Port Inverse Match is disabled
42334  *  0b1..Layer 4 Destination Port Inverse Match is enabled
42335  */
42336 #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK)
42337 
42338 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK  (0x7000000U)
42339 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT (24U)
42340 /*! DMCHN0 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
42341  *    to which the packet passed by this filter is routed.
42342  */
42343 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK)
42344 
42345 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK (0x10000000U)
42346 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT (28U)
42347 /*! DMCHEN0 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
42348  *    number for the packet that is passed by this L3_L4 filter.
42349  *  0b0..DMA Channel Select is disabled
42350  *  0b1..DMA Channel Select is enabled
42351  */
42352 #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK)
42353 /*! @} */
42354 
42355 /*! @name MAC_LAYER4_ADDRESS0 - Layer 4 Address 0 */
42356 /*! @{ */
42357 
42358 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK  (0xFFFFU)
42359 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT (0U)
42360 /*! L4SP0 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
42361  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
42362  *    Source Port Number field in the IPv4 or IPv6 packets.
42363  */
42364 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK)
42365 
42366 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK  (0xFFFF0000U)
42367 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT (16U)
42368 /*! L4DP0 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
42369  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
42370  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
42371  */
42372 #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK)
42373 /*! @} */
42374 
42375 /*! @name MAC_LAYER3_ADDR0_REG0 - Layer 3 Address 0 Register 0 */
42376 /*! @{ */
42377 
42378 #define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xFFFFFFFFU)
42379 #define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT (0U)
42380 /*! L3A00 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
42381  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
42382  *    Address field in the IPv6 packets.
42383  */
42384 #define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK)
42385 /*! @} */
42386 
42387 /*! @name MAC_LAYER3_ADDR1_REG0 - Layer 3 Address 1 Register 0 */
42388 /*! @{ */
42389 
42390 #define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xFFFFFFFFU)
42391 #define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT (0U)
42392 /*! L3A10 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
42393  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
42394  *    Address field in the IPv6 packets.
42395  */
42396 #define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK)
42397 /*! @} */
42398 
42399 /*! @name MAC_LAYER3_ADDR2_REG0 - Layer 3 Address 2 Register 0 */
42400 /*! @{ */
42401 
42402 #define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xFFFFFFFFU)
42403 #define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT (0U)
42404 /*! L3A20 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
42405  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
42406  *    Address field in the IPv6 packets.
42407  */
42408 #define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK)
42409 /*! @} */
42410 
42411 /*! @name MAC_LAYER3_ADDR3_REG0 - Layer 3 Address 3 Register 0 */
42412 /*! @{ */
42413 
42414 #define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xFFFFFFFFU)
42415 #define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT (0U)
42416 /*! L3A30 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
42417  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
42418  *    Address field in the IPv6 packets.
42419  */
42420 #define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK)
42421 /*! @} */
42422 
42423 /*! @name MAC_L3_L4_CONTROL1 - Layer 3 and Layer 4 Control of Filter 1 */
42424 /*! @{ */
42425 
42426 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK  (0x1U)
42427 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT (0U)
42428 /*! L3PEN1 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
42429  *    Address matching is enabled for IPv6 packets.
42430  *  0b0..Layer 3 Protocol is disabled
42431  *  0b1..Layer 3 Protocol is enabled
42432  */
42433 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK)
42434 
42435 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK  (0x4U)
42436 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT (2U)
42437 /*! L3SAM1 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
42438  *  0b0..Layer 3 IP SA Match is disabled
42439  *  0b1..Layer 3 IP SA Match is enabled
42440  */
42441 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK)
42442 
42443 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK (0x8U)
42444 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT (3U)
42445 /*! L3SAIM1 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
42446  *    field is enabled for inverse matching.
42447  *  0b0..Layer 3 IP SA Inverse Match is disabled
42448  *  0b1..Layer 3 IP SA Inverse Match is enabled
42449  */
42450 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK)
42451 
42452 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK  (0x10U)
42453 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT (4U)
42454 /*! L3DAM1 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
42455  *  0b0..Layer 3 IP DA Match is disabled
42456  *  0b1..Layer 3 IP DA Match is enabled
42457  */
42458 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK)
42459 
42460 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK (0x20U)
42461 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT (5U)
42462 /*! L3DAIM1 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
42463  *    Address field is enabled for inverse matching.
42464  *  0b0..Layer 3 IP DA Inverse Match is disabled
42465  *  0b1..Layer 3 IP DA Inverse Match is enabled
42466  */
42467 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK)
42468 
42469 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x7C0U)
42470 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT (6U)
42471 /*! L3HSBM1 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
42472  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
42473  */
42474 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK)
42475 
42476 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0xF800U)
42477 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT (11U)
42478 /*! L3HDBM1 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
42479  *    bits of IP Destination Address that are matched in the IPv4 packets.
42480  */
42481 #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK)
42482 
42483 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK  (0x10000U)
42484 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT (16U)
42485 /*! L4PEN1 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
42486  *    fields of UDP packets are used for matching.
42487  *  0b0..Layer 4 Protocol is disabled
42488  *  0b1..Layer 4 Protocol is enabled
42489  */
42490 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK)
42491 
42492 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK  (0x40000U)
42493 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT (18U)
42494 /*! L4SPM1 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
42495  *  0b0..Layer 4 Source Port Match is disabled
42496  *  0b1..Layer 4 Source Port Match is enabled
42497  */
42498 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK)
42499 
42500 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK (0x80000U)
42501 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT (19U)
42502 /*! L4SPIM1 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
42503  *    number field is enabled for inverse matching.
42504  *  0b0..Layer 4 Source Port Inverse Match is disabled
42505  *  0b1..Layer 4 Source Port Inverse Match is enabled
42506  */
42507 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK)
42508 
42509 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK  (0x100000U)
42510 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT (20U)
42511 /*! L4DPM1 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
42512  *    Port number field is enabled for matching.
42513  *  0b0..Layer 4 Destination Port Match is disabled
42514  *  0b1..Layer 4 Destination Port Match is enabled
42515  */
42516 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK)
42517 
42518 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK (0x200000U)
42519 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT (21U)
42520 /*! L4DPIM1 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
42521  *    Destination Port number field is enabled for inverse matching.
42522  *  0b0..Layer 4 Destination Port Inverse Match is disabled
42523  *  0b1..Layer 4 Destination Port Inverse Match is enabled
42524  */
42525 #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK)
42526 
42527 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK  (0x7000000U)
42528 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT (24U)
42529 /*! DMCHN1 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
42530  *    to which the packet passed by this filter is routed.
42531  */
42532 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK)
42533 
42534 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK (0x10000000U)
42535 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT (28U)
42536 /*! DMCHEN1 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
42537  *    number for the packet that is passed by this L3_L4 filter.
42538  *  0b0..DMA Channel Select is disabled
42539  *  0b1..DMA Channel Select is enabled
42540  */
42541 #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK)
42542 /*! @} */
42543 
42544 /*! @name MAC_LAYER4_ADDRESS1 - Layer 4 Address 0 */
42545 /*! @{ */
42546 
42547 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK  (0xFFFFU)
42548 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT (0U)
42549 /*! L4SP1 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
42550  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
42551  *    Source Port Number field in the IPv4 or IPv6 packets.
42552  */
42553 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK)
42554 
42555 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK  (0xFFFF0000U)
42556 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT (16U)
42557 /*! L4DP1 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
42558  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
42559  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
42560  */
42561 #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK)
42562 /*! @} */
42563 
42564 /*! @name MAC_LAYER3_ADDR0_REG1 - Layer 3 Address 0 Register 1 */
42565 /*! @{ */
42566 
42567 #define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xFFFFFFFFU)
42568 #define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT (0U)
42569 /*! L3A01 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
42570  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
42571  *    Address field in the IPv6 packets.
42572  */
42573 #define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK)
42574 /*! @} */
42575 
42576 /*! @name MAC_LAYER3_ADDR1_REG1 - Layer 3 Address 1 Register 1 */
42577 /*! @{ */
42578 
42579 #define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xFFFFFFFFU)
42580 #define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT (0U)
42581 /*! L3A11 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
42582  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
42583  *    Address field in the IPv6 packets.
42584  */
42585 #define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK)
42586 /*! @} */
42587 
42588 /*! @name MAC_LAYER3_ADDR2_REG1 - Layer 3 Address 2 Register 1 */
42589 /*! @{ */
42590 
42591 #define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xFFFFFFFFU)
42592 #define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT (0U)
42593 /*! L3A21 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
42594  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
42595  *    Address field in the IPv6 packets.
42596  */
42597 #define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK)
42598 /*! @} */
42599 
42600 /*! @name MAC_LAYER3_ADDR3_REG1 - Layer 3 Address 3 Register 1 */
42601 /*! @{ */
42602 
42603 #define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xFFFFFFFFU)
42604 #define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT (0U)
42605 /*! L3A31 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
42606  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
42607  *    Address field in the IPv6 packets.
42608  */
42609 #define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK)
42610 /*! @} */
42611 
42612 /*! @name MAC_L3_L4_CONTROL2 - Layer 3 and Layer 4 Control of Filter 2 */
42613 /*! @{ */
42614 
42615 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK  (0x1U)
42616 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT (0U)
42617 /*! L3PEN2 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
42618  *    Address matching is enabled for IPv6 packets.
42619  *  0b0..Layer 3 Protocol is disabled
42620  *  0b1..Layer 3 Protocol is enabled
42621  */
42622 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK)
42623 
42624 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK  (0x4U)
42625 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT (2U)
42626 /*! L3SAM2 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
42627  *  0b0..Layer 3 IP SA Match is disabled
42628  *  0b1..Layer 3 IP SA Match is enabled
42629  */
42630 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK)
42631 
42632 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK (0x8U)
42633 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT (3U)
42634 /*! L3SAIM2 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
42635  *    field is enabled for inverse matching.
42636  *  0b0..Layer 3 IP SA Inverse Match is disabled
42637  *  0b1..Layer 3 IP SA Inverse Match is enabled
42638  */
42639 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK)
42640 
42641 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK  (0x10U)
42642 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT (4U)
42643 /*! L3DAM2 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
42644  *  0b0..Layer 3 IP DA Match is disabled
42645  *  0b1..Layer 3 IP DA Match is enabled
42646  */
42647 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK)
42648 
42649 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK (0x20U)
42650 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT (5U)
42651 /*! L3DAIM2 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
42652  *    Address field is enabled for inverse matching.
42653  *  0b0..Layer 3 IP DA Inverse Match is disabled
42654  *  0b1..Layer 3 IP DA Inverse Match is enabled
42655  */
42656 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK)
42657 
42658 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x7C0U)
42659 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT (6U)
42660 /*! L3HSBM2 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
42661  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
42662  */
42663 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK)
42664 
42665 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0xF800U)
42666 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT (11U)
42667 /*! L3HDBM2 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
42668  *    bits of IP Destination Address that are matched in the IPv4 packets.
42669  */
42670 #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK)
42671 
42672 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK  (0x10000U)
42673 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT (16U)
42674 /*! L4PEN2 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
42675  *    fields of UDP packets are used for matching.
42676  *  0b0..Layer 4 Protocol is disabled
42677  *  0b1..Layer 4 Protocol is enabled
42678  */
42679 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK)
42680 
42681 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK  (0x40000U)
42682 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT (18U)
42683 /*! L4SPM2 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
42684  *  0b0..Layer 4 Source Port Match is disabled
42685  *  0b1..Layer 4 Source Port Match is enabled
42686  */
42687 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK)
42688 
42689 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK (0x80000U)
42690 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT (19U)
42691 /*! L4SPIM2 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
42692  *    number field is enabled for inverse matching.
42693  *  0b0..Layer 4 Source Port Inverse Match is disabled
42694  *  0b1..Layer 4 Source Port Inverse Match is enabled
42695  */
42696 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK)
42697 
42698 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK  (0x100000U)
42699 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT (20U)
42700 /*! L4DPM2 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
42701  *    Port number field is enabled for matching.
42702  *  0b0..Layer 4 Destination Port Match is disabled
42703  *  0b1..Layer 4 Destination Port Match is enabled
42704  */
42705 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK)
42706 
42707 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK (0x200000U)
42708 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT (21U)
42709 /*! L4DPIM2 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
42710  *    Destination Port number field is enabled for inverse matching.
42711  *  0b0..Layer 4 Destination Port Inverse Match is disabled
42712  *  0b1..Layer 4 Destination Port Inverse Match is enabled
42713  */
42714 #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK)
42715 
42716 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK  (0x7000000U)
42717 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT (24U)
42718 /*! DMCHN2 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
42719  *    to which the packet passed by this filter is routed.
42720  */
42721 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK)
42722 
42723 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK (0x10000000U)
42724 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT (28U)
42725 /*! DMCHEN2 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
42726  *    number for the packet that is passed by this L3_L4 filter.
42727  *  0b0..DMA Channel Select is disabled
42728  *  0b1..DMA Channel Select is enabled
42729  */
42730 #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK)
42731 /*! @} */
42732 
42733 /*! @name MAC_LAYER4_ADDRESS2 - Layer 4 Address 2 */
42734 /*! @{ */
42735 
42736 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK  (0xFFFFU)
42737 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT (0U)
42738 /*! L4SP2 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
42739  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
42740  *    Source Port Number field in the IPv4 or IPv6 packets.
42741  */
42742 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK)
42743 
42744 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK  (0xFFFF0000U)
42745 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT (16U)
42746 /*! L4DP2 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
42747  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
42748  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
42749  */
42750 #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK)
42751 /*! @} */
42752 
42753 /*! @name MAC_LAYER3_ADDR0_REG2 - Layer 3 Address 0 Register 2 */
42754 /*! @{ */
42755 
42756 #define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xFFFFFFFFU)
42757 #define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT (0U)
42758 /*! L3A02 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
42759  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
42760  *    Address field in the IPv6 packets.
42761  */
42762 #define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK)
42763 /*! @} */
42764 
42765 /*! @name MAC_LAYER3_ADDR1_REG2 - Layer 3 Address 0 Register 2 */
42766 /*! @{ */
42767 
42768 #define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xFFFFFFFFU)
42769 #define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT (0U)
42770 /*! L3A12 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
42771  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
42772  *    Address field in the IPv6 packets.
42773  */
42774 #define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK)
42775 /*! @} */
42776 
42777 /*! @name MAC_LAYER3_ADDR2_REG2 - Layer 3 Address 2 Register 2 */
42778 /*! @{ */
42779 
42780 #define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xFFFFFFFFU)
42781 #define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT (0U)
42782 /*! L3A22 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
42783  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
42784  *    Address field in the IPv6 packets.
42785  */
42786 #define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK)
42787 /*! @} */
42788 
42789 /*! @name MAC_LAYER3_ADDR3_REG2 - Layer 3 Address 3 Register 2 */
42790 /*! @{ */
42791 
42792 #define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xFFFFFFFFU)
42793 #define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT (0U)
42794 /*! L3A32 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
42795  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
42796  *    Address field in the IPv6 packets.
42797  */
42798 #define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK)
42799 /*! @} */
42800 
42801 /*! @name MAC_L3_L4_CONTROL3 - Layer 3 and Layer 4 Control of Filter 3 */
42802 /*! @{ */
42803 
42804 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK  (0x1U)
42805 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT (0U)
42806 /*! L3PEN3 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
42807  *    Address matching is enabled for IPv6 packets.
42808  *  0b0..Layer 3 Protocol is disabled
42809  *  0b1..Layer 3 Protocol is enabled
42810  */
42811 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK)
42812 
42813 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK  (0x4U)
42814 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT (2U)
42815 /*! L3SAM3 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
42816  *  0b0..Layer 3 IP SA Match is disabled
42817  *  0b1..Layer 3 IP SA Match is enabled
42818  */
42819 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK)
42820 
42821 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK (0x8U)
42822 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT (3U)
42823 /*! L3SAIM3 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
42824  *    field is enabled for inverse matching.
42825  *  0b0..Layer 3 IP SA Inverse Match is disabled
42826  *  0b1..Layer 3 IP SA Inverse Match is enabled
42827  */
42828 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK)
42829 
42830 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK  (0x10U)
42831 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT (4U)
42832 /*! L3DAM3 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
42833  *  0b0..Layer 3 IP DA Match is disabled
42834  *  0b1..Layer 3 IP DA Match is enabled
42835  */
42836 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK)
42837 
42838 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK (0x20U)
42839 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT (5U)
42840 /*! L3DAIM3 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
42841  *    Address field is enabled for inverse matching.
42842  *  0b0..Layer 3 IP DA Inverse Match is disabled
42843  *  0b1..Layer 3 IP DA Inverse Match is enabled
42844  */
42845 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK)
42846 
42847 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x7C0U)
42848 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT (6U)
42849 /*! L3HSBM3 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
42850  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
42851  */
42852 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK)
42853 
42854 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0xF800U)
42855 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT (11U)
42856 /*! L3HDBM3 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
42857  *    bits of IP Destination Address that are matched in the IPv4 packets.
42858  */
42859 #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK)
42860 
42861 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK  (0x10000U)
42862 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT (16U)
42863 /*! L4PEN3 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
42864  *    fields of UDP packets are used for matching.
42865  *  0b0..Layer 4 Protocol is disabled
42866  *  0b1..Layer 4 Protocol is enabled
42867  */
42868 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK)
42869 
42870 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK  (0x40000U)
42871 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT (18U)
42872 /*! L4SPM3 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
42873  *  0b0..Layer 4 Source Port Match is disabled
42874  *  0b1..Layer 4 Source Port Match is enabled
42875  */
42876 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK)
42877 
42878 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK (0x80000U)
42879 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT (19U)
42880 /*! L4SPIM3 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
42881  *    number field is enabled for inverse matching.
42882  *  0b0..Layer 4 Source Port Inverse Match is disabled
42883  *  0b1..Layer 4 Source Port Inverse Match is enabled
42884  */
42885 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK)
42886 
42887 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK  (0x100000U)
42888 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT (20U)
42889 /*! L4DPM3 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
42890  *    Port number field is enabled for matching.
42891  *  0b0..Layer 4 Destination Port Match is disabled
42892  *  0b1..Layer 4 Destination Port Match is enabled
42893  */
42894 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK)
42895 
42896 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK (0x200000U)
42897 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT (21U)
42898 /*! L4DPIM3 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
42899  *    Destination Port number field is enabled for inverse matching.
42900  *  0b0..Layer 4 Destination Port Inverse Match is disabled
42901  *  0b1..Layer 4 Destination Port Inverse Match is enabled
42902  */
42903 #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK)
42904 
42905 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK  (0x7000000U)
42906 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT (24U)
42907 /*! DMCHN3 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
42908  *    to which the packet passed by this filter is routed.
42909  */
42910 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK)
42911 
42912 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK (0x10000000U)
42913 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT (28U)
42914 /*! DMCHEN3 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
42915  *    number for the packet that is passed by this L3_L4 filter.
42916  *  0b0..DMA Channel Select is disabled
42917  *  0b1..DMA Channel Select is enabled
42918  */
42919 #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK)
42920 /*! @} */
42921 
42922 /*! @name MAC_LAYER4_ADDRESS3 - Layer 4 Address 3 */
42923 /*! @{ */
42924 
42925 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK  (0xFFFFU)
42926 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT (0U)
42927 /*! L4SP3 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
42928  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
42929  *    Source Port Number field in the IPv4 or IPv6 packets.
42930  */
42931 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK)
42932 
42933 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK  (0xFFFF0000U)
42934 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT (16U)
42935 /*! L4DP3 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
42936  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
42937  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
42938  */
42939 #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK)
42940 /*! @} */
42941 
42942 /*! @name MAC_LAYER3_ADDR0_REG3 - Layer 3 Address 0 Register 3 */
42943 /*! @{ */
42944 
42945 #define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xFFFFFFFFU)
42946 #define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT (0U)
42947 /*! L3A03 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
42948  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
42949  *    Address field in the IPv6 packets.
42950  */
42951 #define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK)
42952 /*! @} */
42953 
42954 /*! @name MAC_LAYER3_ADDR1_REG3 - Layer 3 Address 1 Register 3 */
42955 /*! @{ */
42956 
42957 #define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xFFFFFFFFU)
42958 #define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT (0U)
42959 /*! L3A13 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
42960  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
42961  *    Address field in the IPv6 packets.
42962  */
42963 #define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK)
42964 /*! @} */
42965 
42966 /*! @name MAC_LAYER3_ADDR2_REG3 - Layer 3 Address 2 Register 3 */
42967 /*! @{ */
42968 
42969 #define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xFFFFFFFFU)
42970 #define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT (0U)
42971 /*! L3A23 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
42972  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
42973  *    Address field in the IPv6 packets.
42974  */
42975 #define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK)
42976 /*! @} */
42977 
42978 /*! @name MAC_LAYER3_ADDR3_REG3 - Layer 3 Address 3 Register 3 */
42979 /*! @{ */
42980 
42981 #define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xFFFFFFFFU)
42982 #define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT (0U)
42983 /*! L3A33 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
42984  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
42985  *    Address field in the IPv6 packets.
42986  */
42987 #define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK)
42988 /*! @} */
42989 
42990 /*! @name MAC_L3_L4_CONTROL4 - Layer 3 and Layer 4 Control of Filter 4 */
42991 /*! @{ */
42992 
42993 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK  (0x1U)
42994 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT (0U)
42995 /*! L3PEN4 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
42996  *    Address matching is enabled for IPv6 packets.
42997  *  0b0..Layer 3 Protocol is disabled
42998  *  0b1..Layer 3 Protocol is enabled
42999  */
43000 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK)
43001 
43002 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK  (0x4U)
43003 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT (2U)
43004 /*! L3SAM4 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
43005  *  0b0..Layer 3 IP SA Match is disabled
43006  *  0b1..Layer 3 IP SA Match is enabled
43007  */
43008 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK)
43009 
43010 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK (0x8U)
43011 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT (3U)
43012 /*! L3SAIM4 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
43013  *    field is enabled for inverse matching.
43014  *  0b0..Layer 3 IP SA Inverse Match is disabled
43015  *  0b1..Layer 3 IP SA Inverse Match is enabled
43016  */
43017 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK)
43018 
43019 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK  (0x10U)
43020 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT (4U)
43021 /*! L3DAM4 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
43022  *  0b0..Layer 3 IP DA Match is disabled
43023  *  0b1..Layer 3 IP DA Match is enabled
43024  */
43025 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK)
43026 
43027 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK (0x20U)
43028 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT (5U)
43029 /*! L3DAIM4 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
43030  *    Address field is enabled for inverse matching.
43031  *  0b0..Layer 3 IP DA Inverse Match is disabled
43032  *  0b1..Layer 3 IP DA Inverse Match is enabled
43033  */
43034 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK)
43035 
43036 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK (0x7C0U)
43037 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT (6U)
43038 /*! L3HSBM4 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
43039  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
43040  */
43041 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK)
43042 
43043 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK (0xF800U)
43044 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT (11U)
43045 /*! L3HDBM4 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
43046  *    bits of IP Destination Address that are matched in the IPv4 packets.
43047  */
43048 #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK)
43049 
43050 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK  (0x10000U)
43051 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT (16U)
43052 /*! L4PEN4 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
43053  *    fields of UDP packets are used for matching.
43054  *  0b0..Layer 4 Protocol is disabled
43055  *  0b1..Layer 4 Protocol is enabled
43056  */
43057 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK)
43058 
43059 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK  (0x40000U)
43060 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT (18U)
43061 /*! L4SPM4 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
43062  *  0b0..Layer 4 Source Port Match is disabled
43063  *  0b1..Layer 4 Source Port Match is enabled
43064  */
43065 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK)
43066 
43067 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK (0x80000U)
43068 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT (19U)
43069 /*! L4SPIM4 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
43070  *    number field is enabled for inverse matching.
43071  *  0b0..Layer 4 Source Port Inverse Match is disabled
43072  *  0b1..Layer 4 Source Port Inverse Match is enabled
43073  */
43074 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK)
43075 
43076 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK  (0x100000U)
43077 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT (20U)
43078 /*! L4DPM4 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
43079  *    Port number field is enabled for matching.
43080  *  0b0..Layer 4 Destination Port Match is disabled
43081  *  0b1..Layer 4 Destination Port Match is enabled
43082  */
43083 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK)
43084 
43085 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK (0x200000U)
43086 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT (21U)
43087 /*! L4DPIM4 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
43088  *    Destination Port number field is enabled for inverse matching.
43089  *  0b0..Layer 4 Destination Port Inverse Match is disabled
43090  *  0b1..Layer 4 Destination Port Inverse Match is enabled
43091  */
43092 #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK)
43093 
43094 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK  (0x7000000U)
43095 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT (24U)
43096 /*! DMCHN4 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
43097  *    to which the packet passed by this filter is routed.
43098  */
43099 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK)
43100 
43101 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK (0x10000000U)
43102 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT (28U)
43103 /*! DMCHEN4 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
43104  *    number for the packet that is passed by this L3_L4 filter.
43105  *  0b0..DMA Channel Select is disabled
43106  *  0b1..DMA Channel Select is enabled
43107  */
43108 #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK)
43109 /*! @} */
43110 
43111 /*! @name MAC_LAYER4_ADDRESS4 - Layer 4 Address 4 */
43112 /*! @{ */
43113 
43114 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK  (0xFFFFU)
43115 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT (0U)
43116 /*! L4SP4 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
43117  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
43118  *    Source Port Number field in the IPv4 or IPv6 packets.
43119  */
43120 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK)
43121 
43122 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK  (0xFFFF0000U)
43123 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT (16U)
43124 /*! L4DP4 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
43125  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
43126  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
43127  */
43128 #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK)
43129 /*! @} */
43130 
43131 /*! @name MAC_LAYER3_ADDR0_REG4 - Layer 3 Address 0 Register 4 */
43132 /*! @{ */
43133 
43134 #define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK (0xFFFFFFFFU)
43135 #define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT (0U)
43136 /*! L3A04 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
43137  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
43138  *    Address field in the IPv6 packets.
43139  */
43140 #define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK)
43141 /*! @} */
43142 
43143 /*! @name MAC_LAYER3_ADDR1_REG4 - Layer 3 Address 1 Register 4 */
43144 /*! @{ */
43145 
43146 #define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK (0xFFFFFFFFU)
43147 #define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT (0U)
43148 /*! L3A14 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
43149  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
43150  *    Address field in the IPv6 packets.
43151  */
43152 #define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK)
43153 /*! @} */
43154 
43155 /*! @name MAC_LAYER3_ADDR2_REG4 - Layer 3 Address 2 Register 4 */
43156 /*! @{ */
43157 
43158 #define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK (0xFFFFFFFFU)
43159 #define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT (0U)
43160 /*! L3A24 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
43161  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
43162  *    Address field in the IPv6 packets.
43163  */
43164 #define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK)
43165 /*! @} */
43166 
43167 /*! @name MAC_LAYER3_ADDR3_REG4 - Layer 3 Address 3 Register 4 */
43168 /*! @{ */
43169 
43170 #define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK (0xFFFFFFFFU)
43171 #define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT (0U)
43172 /*! L3A34 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
43173  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
43174  *    Address field in the IPv6 packets.
43175  */
43176 #define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK)
43177 /*! @} */
43178 
43179 /*! @name MAC_L3_L4_CONTROL5 - Layer 3 and Layer 4 Control of Filter 5 */
43180 /*! @{ */
43181 
43182 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK  (0x1U)
43183 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT (0U)
43184 /*! L3PEN5 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
43185  *    Address matching is enabled for IPv6 packets.
43186  *  0b0..Layer 3 Protocol is disabled
43187  *  0b1..Layer 3 Protocol is enabled
43188  */
43189 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK)
43190 
43191 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK  (0x4U)
43192 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT (2U)
43193 /*! L3SAM5 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
43194  *  0b0..Layer 3 IP SA Match is disabled
43195  *  0b1..Layer 3 IP SA Match is enabled
43196  */
43197 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK)
43198 
43199 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK (0x8U)
43200 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT (3U)
43201 /*! L3SAIM5 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
43202  *    field is enabled for inverse matching.
43203  *  0b0..Layer 3 IP SA Inverse Match is disabled
43204  *  0b1..Layer 3 IP SA Inverse Match is enabled
43205  */
43206 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK)
43207 
43208 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK  (0x10U)
43209 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT (4U)
43210 /*! L3DAM5 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
43211  *  0b0..Layer 3 IP DA Match is disabled
43212  *  0b1..Layer 3 IP DA Match is enabled
43213  */
43214 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK)
43215 
43216 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK (0x20U)
43217 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT (5U)
43218 /*! L3DAIM5 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
43219  *    Address field is enabled for inverse matching.
43220  *  0b0..Layer 3 IP DA Inverse Match is disabled
43221  *  0b1..Layer 3 IP DA Inverse Match is enabled
43222  */
43223 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK)
43224 
43225 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK (0x7C0U)
43226 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT (6U)
43227 /*! L3HSBM5 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
43228  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
43229  */
43230 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK)
43231 
43232 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK (0xF800U)
43233 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT (11U)
43234 /*! L3HDBM5 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
43235  *    bits of IP Destination Address that are matched in the IPv4 packets.
43236  */
43237 #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK)
43238 
43239 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK  (0x10000U)
43240 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT (16U)
43241 /*! L4PEN5 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
43242  *    fields of UDP packets are used for matching.
43243  *  0b0..Layer 4 Protocol is disabled
43244  *  0b1..Layer 4 Protocol is enabled
43245  */
43246 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK)
43247 
43248 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK  (0x40000U)
43249 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT (18U)
43250 /*! L4SPM5 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
43251  *  0b0..Layer 4 Source Port Match is disabled
43252  *  0b1..Layer 4 Source Port Match is enabled
43253  */
43254 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK)
43255 
43256 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK (0x80000U)
43257 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT (19U)
43258 /*! L4SPIM5 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
43259  *    number field is enabled for inverse matching.
43260  *  0b0..Layer 4 Source Port Inverse Match is disabled
43261  *  0b1..Layer 4 Source Port Inverse Match is enabled
43262  */
43263 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK)
43264 
43265 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK  (0x100000U)
43266 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT (20U)
43267 /*! L4DPM5 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
43268  *    Port number field is enabled for matching.
43269  *  0b0..Layer 4 Destination Port Match is disabled
43270  *  0b1..Layer 4 Destination Port Match is enabled
43271  */
43272 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK)
43273 
43274 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK (0x200000U)
43275 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT (21U)
43276 /*! L4DPIM5 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
43277  *    Destination Port number field is enabled for inverse matching.
43278  *  0b0..Layer 4 Destination Port Inverse Match is disabled
43279  *  0b1..Layer 4 Destination Port Inverse Match is enabled
43280  */
43281 #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK)
43282 
43283 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK  (0x7000000U)
43284 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT (24U)
43285 /*! DMCHN5 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
43286  *    to which the packet passed by this filter is routed.
43287  */
43288 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK)
43289 
43290 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK (0x10000000U)
43291 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT (28U)
43292 /*! DMCHEN5 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
43293  *    number for the packet that is passed by this L3_L4 filter.
43294  *  0b0..DMA Channel Select is disabled
43295  *  0b1..DMA Channel Select is enabled
43296  */
43297 #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK)
43298 /*! @} */
43299 
43300 /*! @name MAC_LAYER4_ADDRESS5 - Layer 4 Address 5 */
43301 /*! @{ */
43302 
43303 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK  (0xFFFFU)
43304 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT (0U)
43305 /*! L4SP5 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
43306  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
43307  *    Source Port Number field in the IPv4 or IPv6 packets.
43308  */
43309 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK)
43310 
43311 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK  (0xFFFF0000U)
43312 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT (16U)
43313 /*! L4DP5 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
43314  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
43315  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
43316  */
43317 #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK)
43318 /*! @} */
43319 
43320 /*! @name MAC_LAYER3_ADDR0_REG5 - Layer 3 Address 0 Register 5 */
43321 /*! @{ */
43322 
43323 #define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK (0xFFFFFFFFU)
43324 #define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT (0U)
43325 /*! L3A05 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
43326  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
43327  *    Address field in the IPv6 packets.
43328  */
43329 #define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK)
43330 /*! @} */
43331 
43332 /*! @name MAC_LAYER3_ADDR1_REG5 - Layer 3 Address 1 Register 5 */
43333 /*! @{ */
43334 
43335 #define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK (0xFFFFFFFFU)
43336 #define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT (0U)
43337 /*! L3A15 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
43338  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
43339  *    Address field in the IPv6 packets.
43340  */
43341 #define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK)
43342 /*! @} */
43343 
43344 /*! @name MAC_LAYER3_ADDR2_REG5 - Layer 3 Address 2 Register 5 */
43345 /*! @{ */
43346 
43347 #define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK (0xFFFFFFFFU)
43348 #define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT (0U)
43349 /*! L3A25 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
43350  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
43351  *    Address field in the IPv6 packets.
43352  */
43353 #define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK)
43354 /*! @} */
43355 
43356 /*! @name MAC_LAYER3_ADDR3_REG5 - Layer 3 Address 3 Register 5 */
43357 /*! @{ */
43358 
43359 #define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK (0xFFFFFFFFU)
43360 #define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT (0U)
43361 /*! L3A35 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
43362  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
43363  *    Address field in the IPv6 packets.
43364  */
43365 #define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK)
43366 /*! @} */
43367 
43368 /*! @name MAC_L3_L4_CONTROL6 - Layer 3 and Layer 4 Control of Filter 6 */
43369 /*! @{ */
43370 
43371 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK  (0x1U)
43372 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT (0U)
43373 /*! L3PEN6 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
43374  *    Address matching is enabled for IPv6 packets.
43375  *  0b0..Layer 3 Protocol is disabled
43376  *  0b1..Layer 3 Protocol is enabled
43377  */
43378 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK)
43379 
43380 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK  (0x4U)
43381 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT (2U)
43382 /*! L3SAM6 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
43383  *  0b0..Layer 3 IP SA Match is disabled
43384  *  0b1..Layer 3 IP SA Match is enabled
43385  */
43386 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK)
43387 
43388 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK (0x8U)
43389 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT (3U)
43390 /*! L3SAIM6 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
43391  *    field is enabled for inverse matching.
43392  *  0b0..Layer 3 IP SA Inverse Match is disabled
43393  *  0b1..Layer 3 IP SA Inverse Match is enabled
43394  */
43395 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK)
43396 
43397 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK  (0x10U)
43398 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT (4U)
43399 /*! L3DAM6 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
43400  *  0b0..Layer 3 IP DA Match is disabled
43401  *  0b1..Layer 3 IP DA Match is enabled
43402  */
43403 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK)
43404 
43405 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK (0x20U)
43406 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT (5U)
43407 /*! L3DAIM6 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
43408  *    Address field is enabled for inverse matching.
43409  *  0b0..Layer 3 IP DA Inverse Match is disabled
43410  *  0b1..Layer 3 IP DA Inverse Match is enabled
43411  */
43412 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK)
43413 
43414 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK (0x7C0U)
43415 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT (6U)
43416 /*! L3HSBM6 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
43417  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
43418  */
43419 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK)
43420 
43421 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK (0xF800U)
43422 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT (11U)
43423 /*! L3HDBM6 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
43424  *    bits of IP Destination Address that are matched in the IPv4 packets.
43425  */
43426 #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK)
43427 
43428 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK  (0x10000U)
43429 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT (16U)
43430 /*! L4PEN6 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
43431  *    fields of UDP packets are used for matching.
43432  *  0b0..Layer 4 Protocol is disabled
43433  *  0b1..Layer 4 Protocol is enabled
43434  */
43435 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK)
43436 
43437 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK  (0x40000U)
43438 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT (18U)
43439 /*! L4SPM6 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
43440  *  0b0..Layer 4 Source Port Match is disabled
43441  *  0b1..Layer 4 Source Port Match is enabled
43442  */
43443 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK)
43444 
43445 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK (0x80000U)
43446 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT (19U)
43447 /*! L4SPIM6 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
43448  *    number field is enabled for inverse matching.
43449  *  0b0..Layer 4 Source Port Inverse Match is disabled
43450  *  0b1..Layer 4 Source Port Inverse Match is enabled
43451  */
43452 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK)
43453 
43454 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK  (0x100000U)
43455 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT (20U)
43456 /*! L4DPM6 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
43457  *    Port number field is enabled for matching.
43458  *  0b0..Layer 4 Destination Port Match is disabled
43459  *  0b1..Layer 4 Destination Port Match is enabled
43460  */
43461 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK)
43462 
43463 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK (0x200000U)
43464 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT (21U)
43465 /*! L4DPIM6 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
43466  *    Destination Port number field is enabled for inverse matching.
43467  *  0b0..Layer 4 Destination Port Inverse Match is disabled
43468  *  0b1..Layer 4 Destination Port Inverse Match is enabled
43469  */
43470 #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK)
43471 
43472 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK  (0x7000000U)
43473 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT (24U)
43474 /*! DMCHN6 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
43475  *    to which the packet passed by this filter is routed.
43476  */
43477 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK)
43478 
43479 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK (0x10000000U)
43480 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT (28U)
43481 /*! DMCHEN6 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
43482  *    number for the packet that is passed by this L3_L4 filter.
43483  *  0b0..DMA Channel Select is disabled
43484  *  0b1..DMA Channel Select is enabled
43485  */
43486 #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK)
43487 /*! @} */
43488 
43489 /*! @name MAC_LAYER4_ADDRESS6 - Layer 4 Address 6 */
43490 /*! @{ */
43491 
43492 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK  (0xFFFFU)
43493 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT (0U)
43494 /*! L4SP6 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
43495  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
43496  *    Source Port Number field in the IPv4 or IPv6 packets.
43497  */
43498 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK)
43499 
43500 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK  (0xFFFF0000U)
43501 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT (16U)
43502 /*! L4DP6 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
43503  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
43504  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
43505  */
43506 #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK)
43507 /*! @} */
43508 
43509 /*! @name MAC_LAYER3_ADDR0_REG6 - Layer 3 Address 0 Register 6 */
43510 /*! @{ */
43511 
43512 #define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK (0xFFFFFFFFU)
43513 #define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT (0U)
43514 /*! L3A06 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
43515  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
43516  *    Address field in the IPv6 packets.
43517  */
43518 #define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK)
43519 /*! @} */
43520 
43521 /*! @name MAC_LAYER3_ADDR1_REG6 - Layer 3 Address 1 Register 6 */
43522 /*! @{ */
43523 
43524 #define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK (0xFFFFFFFFU)
43525 #define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT (0U)
43526 /*! L3A16 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
43527  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
43528  *    Address field in the IPv6 packets.
43529  */
43530 #define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK)
43531 /*! @} */
43532 
43533 /*! @name MAC_LAYER3_ADDR2_REG6 - Layer 3 Address 2 Register 6 */
43534 /*! @{ */
43535 
43536 #define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK (0xFFFFFFFFU)
43537 #define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT (0U)
43538 /*! L3A26 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
43539  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
43540  *    Address field in the IPv6 packets.
43541  */
43542 #define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK)
43543 /*! @} */
43544 
43545 /*! @name MAC_LAYER3_ADDR3_REG6 - Layer 3 Address 3 Register 6 */
43546 /*! @{ */
43547 
43548 #define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK (0xFFFFFFFFU)
43549 #define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT (0U)
43550 /*! L3A36 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
43551  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
43552  *    Address field in the IPv6 packets.
43553  */
43554 #define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK)
43555 /*! @} */
43556 
43557 /*! @name MAC_L3_L4_CONTROL7 - Layer 3 and Layer 4 Control of Filter 0 */
43558 /*! @{ */
43559 
43560 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK  (0x1U)
43561 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT (0U)
43562 /*! L3PEN7 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
43563  *    Address matching is enabled for IPv6 packets.
43564  *  0b0..Layer 3 Protocol is disabled
43565  *  0b1..Layer 3 Protocol is enabled
43566  */
43567 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK)
43568 
43569 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK  (0x4U)
43570 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT (2U)
43571 /*! L3SAM7 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
43572  *  0b0..Layer 3 IP SA Match is disabled
43573  *  0b1..Layer 3 IP SA Match is enabled
43574  */
43575 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK)
43576 
43577 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK (0x8U)
43578 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT (3U)
43579 /*! L3SAIM7 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
43580  *    field is enabled for inverse matching.
43581  *  0b0..Layer 3 IP SA Inverse Match is disabled
43582  *  0b1..Layer 3 IP SA Inverse Match is enabled
43583  */
43584 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK)
43585 
43586 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK  (0x10U)
43587 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT (4U)
43588 /*! L3DAM7 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
43589  *  0b0..Layer 3 IP DA Match is disabled
43590  *  0b1..Layer 3 IP DA Match is enabled
43591  */
43592 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK)
43593 
43594 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK (0x20U)
43595 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT (5U)
43596 /*! L3DAIM7 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
43597  *    Address field is enabled for inverse matching.
43598  *  0b0..Layer 3 IP DA Inverse Match is disabled
43599  *  0b1..Layer 3 IP DA Inverse Match is enabled
43600  */
43601 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK)
43602 
43603 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK (0x7C0U)
43604 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT (6U)
43605 /*! L3HSBM7 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
43606  *    bits of IP Source Address that are masked for matching in the IPv4 packets.
43607  */
43608 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK)
43609 
43610 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK (0xF800U)
43611 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT (11U)
43612 /*! L3HDBM7 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
43613  *    bits of IP Destination Address that are matched in the IPv4 packets.
43614  */
43615 #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK)
43616 
43617 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK  (0x10000U)
43618 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT (16U)
43619 /*! L4PEN7 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
43620  *    fields of UDP packets are used for matching.
43621  *  0b0..Layer 4 Protocol is disabled
43622  *  0b1..Layer 4 Protocol is enabled
43623  */
43624 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK)
43625 
43626 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK  (0x40000U)
43627 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT (18U)
43628 /*! L4SPM7 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
43629  *  0b0..Layer 4 Source Port Match is disabled
43630  *  0b1..Layer 4 Source Port Match is enabled
43631  */
43632 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK)
43633 
43634 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK (0x80000U)
43635 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT (19U)
43636 /*! L4SPIM7 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
43637  *    number field is enabled for inverse matching.
43638  *  0b0..Layer 4 Source Port Inverse Match is disabled
43639  *  0b1..Layer 4 Source Port Inverse Match is enabled
43640  */
43641 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK)
43642 
43643 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK  (0x100000U)
43644 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT (20U)
43645 /*! L4DPM7 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
43646  *    Port number field is enabled for matching.
43647  *  0b0..Layer 4 Destination Port Match is disabled
43648  *  0b1..Layer 4 Destination Port Match is enabled
43649  */
43650 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK)
43651 
43652 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK (0x200000U)
43653 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT (21U)
43654 /*! L4DPIM7 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
43655  *    Destination Port number field is enabled for inverse matching.
43656  *  0b0..Layer 4 Destination Port Inverse Match is disabled
43657  *  0b1..Layer 4 Destination Port Inverse Match is enabled
43658  */
43659 #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK)
43660 
43661 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK  (0x7000000U)
43662 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT (24U)
43663 /*! DMCHN7 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
43664  *    to which the packet passed by this filter is routed.
43665  */
43666 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK)
43667 
43668 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK (0x10000000U)
43669 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT (28U)
43670 /*! DMCHEN7 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
43671  *    number for the packet that is passed by this L3_L4 filter.
43672  *  0b0..DMA Channel Select is disabled
43673  *  0b1..DMA Channel Select is enabled
43674  */
43675 #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK)
43676 /*! @} */
43677 
43678 /*! @name MAC_LAYER4_ADDRESS7 - Layer 4 Address 7 */
43679 /*! @{ */
43680 
43681 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK  (0xFFFFU)
43682 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT (0U)
43683 /*! L4SP7 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
43684  *    in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
43685  *    Source Port Number field in the IPv4 or IPv6 packets.
43686  */
43687 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK)
43688 
43689 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK  (0xFFFF0000U)
43690 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT (16U)
43691 /*! L4DP7 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
43692  *    set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
43693  *    TCP Destination Port Number field in the IPv4 or IPv6 packets.
43694  */
43695 #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK)
43696 /*! @} */
43697 
43698 /*! @name MAC_LAYER3_ADDR0_REG7 - Layer 3 Address 0 Register 7 */
43699 /*! @{ */
43700 
43701 #define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK (0xFFFFFFFFU)
43702 #define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT (0U)
43703 /*! L3A07 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
43704  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
43705  *    Address field in the IPv6 packets.
43706  */
43707 #define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK)
43708 /*! @} */
43709 
43710 /*! @name MAC_LAYER3_ADDR1_REG7 - Layer 3 Address 1 Register 7 */
43711 /*! @{ */
43712 
43713 #define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK (0xFFFFFFFFU)
43714 #define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT (0U)
43715 /*! L3A17 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
43716  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
43717  *    Address field in the IPv6 packets.
43718  */
43719 #define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK)
43720 /*! @} */
43721 
43722 /*! @name MAC_LAYER3_ADDR2_REG7 - Layer 3 Address 2 Register 7 */
43723 /*! @{ */
43724 
43725 #define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK (0xFFFFFFFFU)
43726 #define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT (0U)
43727 /*! L3A27 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
43728  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
43729  *    Address field in the IPv6 packets.
43730  */
43731 #define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK)
43732 /*! @} */
43733 
43734 /*! @name MAC_LAYER3_ADDR3_REG7 - Layer 3 Address 3 Register 7 */
43735 /*! @{ */
43736 
43737 #define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK (0xFFFFFFFFU)
43738 #define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT (0U)
43739 /*! L3A37 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
43740  *    MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
43741  *    Address field in the IPv6 packets.
43742  */
43743 #define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK)
43744 /*! @} */
43745 
43746 /*! @name MAC_TIMESTAMP_CONTROL - Timestamp Control */
43747 /*! @{ */
43748 
43749 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK (0x1U)
43750 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT (0U)
43751 /*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets.
43752  *  0b0..Timestamp is disabled
43753  *  0b1..Timestamp is enabled
43754  */
43755 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK)
43756 
43757 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK (0x2U)
43758 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT (1U)
43759 /*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp.
43760  *  0b0..Coarse method is used to update system timestamp
43761  *  0b1..Fine method is used to update system timestamp
43762  */
43763 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK)
43764 
43765 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK (0x4U)
43766 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT (2U)
43767 /*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten)
43768  *    with the value specified in the MAC_System_Time_Seconds_Update and
43769  *    MAC_System_Time_Nanoseconds_Update registers.
43770  *  0b0..Timestamp is not initialized
43771  *  0b1..Timestamp is initialized
43772  */
43773 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)
43774 
43775 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK (0x8U)
43776 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT (3U)
43777 /*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted)
43778  *    with the value specified in MAC_System_Time_Seconds_Update and
43779  *    MAC_System_Time_Nanoseconds_Update registers.
43780  *  0b0..Timestamp is not updated
43781  *  0b1..Timestamp is updated
43782  */
43783 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK)
43784 
43785 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK (0x20U)
43786 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT (5U)
43787 /*! TSADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend
43788  *    register is updated in the PTP block for fine correction.
43789  *  0b0..Addend Register is not updated
43790  *  0b1..Addend Register is updated
43791  */
43792 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK)
43793 
43794 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK (0x40U)
43795 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT (6U)
43796 /*! PTGE - Presentation Time Generation Enable When this bit is set the Presentation Time generation will be enabled.
43797  *  0b0..Presentation Time Generation is disabled
43798  *  0b1..Presentation Time Generation is enabled
43799  */
43800 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK)
43801 
43802 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK (0x100U)
43803 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT (8U)
43804 /*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is
43805  *    enabled for all packets received by the MAC.
43806  *  0b0..Timestamp for All Packets disabled
43807  *  0b1..Timestamp for All Packets enabled
43808  */
43809 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK)
43810 
43811 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x200U)
43812 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U)
43813 /*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low
43814  *    register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments
43815  *    the timestamp (High) seconds.
43816  *  0b0..Timestamp Digital or Binary Rollover Control is disabled
43817  *  0b1..Timestamp Digital or Binary Rollover Control is enabled
43818  */
43819 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK)
43820 
43821 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK (0x400U)
43822 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT (10U)
43823 /*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE
43824  *    1588 version 2 format is used to process the PTP packets.
43825  *  0b0..PTP Packet Processing for Version 2 Format is disabled
43826  *  0b1..PTP Packet Processing for Version 2 Format is enabled
43827  */
43828 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK)
43829 
43830 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK (0x800U)
43831 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT (11U)
43832 /*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver
43833  *    processes the PTP packets encapsulated directly in the Ethernet packets.
43834  *  0b0..Processing of PTP over Ethernet Packets is disabled
43835  *  0b1..Processing of PTP over Ethernet Packets is enabled
43836  */
43837 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK)
43838 
43839 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK (0x1000U)
43840 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT (12U)
43841 /*! TSIPV6ENA - Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set, the MAC
43842  *    receiver processes the PTP packets encapsulated in IPv6-UDP packets.
43843  *  0b0..Processing of PTP Packets Sent over IPv6-UDP is disabled
43844  *  0b1..Processing of PTP Packets Sent over IPv6-UDP is enabled
43845  */
43846 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK)
43847 
43848 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK (0x2000U)
43849 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT (13U)
43850 /*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC
43851  *    receiver processes the PTP packets encapsulated in IPv4-UDP packets.
43852  *  0b0..Processing of PTP Packets Sent over IPv4-UDP is disabled
43853  *  0b1..Processing of PTP Packets Sent over IPv4-UDP is enabled
43854  */
43855 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK)
43856 
43857 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK (0x4000U)
43858 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT (14U)
43859 /*! TSEVNTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp
43860  *    snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).
43861  *  0b0..Timestamp Snapshot for Event Messages is disabled
43862  *  0b1..Timestamp Snapshot for Event Messages is enabled
43863  */
43864 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK)
43865 
43866 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK (0x8000U)
43867 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT (15U)
43868 /*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot
43869  *    is taken only for the messages that are relevant to the master node.
43870  *  0b0..Snapshot for Messages Relevant to Master is disabled
43871  *  0b1..Snapshot for Messages Relevant to Master is enabled
43872  */
43873 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK)
43874 
43875 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x30000U)
43876 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16U)
43877 /*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14,
43878  *    decide the set of PTP packet types for which snapshot needs to be taken.
43879  */
43880 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK)
43881 
43882 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK (0x40000U)
43883 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT (18U)
43884 /*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC
43885  *    address (that matches any MAC Address register) is used to filter the PTP packets when PTP is
43886  *    directly sent over Ethernet.
43887  *  0b0..MAC Address for PTP Packet Filtering is disabled
43888  *  0b1..MAC Address for PTP Packet Filtering is enabled
43889  */
43890 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK)
43891 
43892 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK  (0x80000U)
43893 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT (19U)
43894 /*! CSC - Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set,
43895  *    the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum
43896  *    correct, for changes made to origin timestamp and/or correction field as part of one step timestamp
43897  *    operation.
43898  *  0b0..checksum correction during OST for PTP over UDP/IPv4 packets is disabled
43899  *  0b1..checksum correction during OST for PTP over UDP/IPv4 packets is enabled
43900  */
43901 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK)
43902 
43903 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK (0x100000U)
43904 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT (20U)
43905 /*! ESTI - External System Time Input When this bit is set, the MAC uses the external 64-bit
43906  *    reference System Time input for the following: - To take the timestamp provided as status - To insert
43907  *    the timestamp in transmit PTP packets when One-step Timestamp or Timestamp Offload feature is
43908  *    enabled.
43909  *  0b0..External System Time Input is disabled
43910  *  0b1..External System Time Input is enabled
43911  */
43912 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK)
43913 
43914 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK (0x1000000U)
43915 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT (24U)
43916 /*! TXTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier
43917  *    transmit timestamp status even if it is not read by the software.
43918  *  0b0..Transmit Timestamp Status Mode is disabled
43919  *  0b1..Transmit Timestamp Status Mode is enabled
43920  */
43921 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK)
43922 
43923 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK (0x10000000U)
43924 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT (28U)
43925 /*! AV8021ASMEN - AV 802.
43926  *  0b0..AV 802.1AS Mode is disabled
43927  *  0b1..AV 802.1AS Mode is enabled
43928  */
43929 #define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK)
43930 /*! @} */
43931 
43932 /*! @name MAC_SUB_SECOND_INCREMENT - Subsecond Increment */
43933 /*! @{ */
43934 
43935 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF00U)
43936 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (8U)
43937 /*! SNSINC - Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value,
43938  *    represented in nanoseconds multiplied by 2^8.
43939  */
43940 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK)
43941 
43942 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFF0000U)
43943 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16U)
43944 /*! SSINC - Sub-second Increment Value The value programmed in this field is accumulated every clock
43945  *    cycle (of clk_ptp_i) with the contents of the sub-second register.
43946  */
43947 #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK)
43948 /*! @} */
43949 
43950 /*! @name MAC_SYSTEM_TIME_SECONDS - System Time Seconds */
43951 /*! @{ */
43952 
43953 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xFFFFFFFFU)
43954 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT (0U)
43955 /*! TSS - Timestamp Second The value in this field indicates the current value in seconds of the
43956  *    System Time maintained by the MAC.
43957  */
43958 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK)
43959 /*! @} */
43960 
43961 /*! @name MAC_SYSTEM_TIME_NANOSECONDS - System Time Nanoseconds */
43962 /*! @{ */
43963 
43964 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFFU)
43965 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0U)
43966 /*! TSSS - Timestamp Sub Seconds The value in this field has the sub-second representation of time, with an accuracy of 0. */
43967 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK)
43968 /*! @} */
43969 
43970 /*! @name MAC_SYSTEM_TIME_SECONDS_UPDATE - System Time Seconds Update */
43971 /*! @{ */
43972 
43973 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFFU)
43974 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0U)
43975 /*! TSS - Timestamp Seconds The value in this field is the seconds part of the update. */
43976 #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK)
43977 /*! @} */
43978 
43979 /*! @name MAC_SYSTEM_TIME_NANOSECONDS_UPDATE - System Time Nanoseconds Update */
43980 /*! @{ */
43981 
43982 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFFU)
43983 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0U)
43984 /*! TSSS - Timestamp Sub Seconds The value in this field is the sub-seconds part of the update. */
43985 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK)
43986 
43987 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK (0x80000000U)
43988 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT (31U)
43989 /*! ADDSUB - Add or Subtract Time When this bit is set, the time value is subtracted with the contents of the update register.
43990  *  0b0..Add time
43991  *  0b1..Subtract time
43992  */
43993 #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK)
43994 /*! @} */
43995 
43996 /*! @name MAC_TIMESTAMP_ADDEND - Timestamp Addend */
43997 /*! @{ */
43998 
43999 #define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK  (0xFFFFFFFFU)
44000 #define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0U)
44001 /*! TSAR - Timestamp Addend Register This field indicates the 32-bit time value to be added to the
44002  *    Accumulator register to achieve time synchronization.
44003  */
44004 #define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK)
44005 /*! @} */
44006 
44007 /*! @name MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS - System Time - Higher Word Seconds */
44008 /*! @{ */
44009 
44010 #define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xFFFFU)
44011 #define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT (0U)
44012 /*! TSHWR - Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value. */
44013 #define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK)
44014 /*! @} */
44015 
44016 /*! @name MAC_TIMESTAMP_STATUS - Timestamp Status */
44017 /*! @{ */
44018 
44019 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK (0x1U)
44020 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT (0U)
44021 /*! TSSOVF - Timestamp Seconds Overflow When this bit is set, it indicates that the seconds value of
44022  *    the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF.
44023  *  0b1..Timestamp Seconds Overflow status detected
44024  *  0b0..Timestamp Seconds Overflow status not detected
44025  */
44026 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK)
44027 
44028 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK (0x2U)
44029 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT (1U)
44030 /*! TSTARGT0 - Timestamp Target Time Reached When set, this bit indicates that the value of system
44031  *    time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and
44032  *    MAC_PPS0_Target_Time_Nanoseconds registers.
44033  *  0b1..Timestamp Target Time Reached status detected
44034  *  0b0..Timestamp Target Time Reached status not detected
44035  */
44036 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK)
44037 
44038 #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK (0x4U)
44039 #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT (2U)
44040 /*! AUXTSTRIG - Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO.
44041  *  0b1..Auxiliary Timestamp Trigger Snapshot status detected
44042  *  0b0..Auxiliary Timestamp Trigger Snapshot status not detected
44043  */
44044 #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK)
44045 
44046 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK (0x8U)
44047 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT (3U)
44048 /*! TSTRGTERR0 - Timestamp Target Time Error This bit is set when the latest target time programmed
44049  *    in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses.
44050  *  0b1..Timestamp Target Time Error status detected
44051  *  0b0..Timestamp Target Time Error status not detected
44052  */
44053 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK)
44054 
44055 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK (0x10U)
44056 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT (4U)
44057 /*! TSTARGT1 - Timestamp Target Time Reached for Target Time PPS1 When set, this bit indicates that
44058  *    the value of system time is greater than or equal to the value specified in the
44059  *    MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers.
44060  *  0b1..Timestamp Target Time Reached for Target Time PPS1 status detected
44061  *  0b0..Timestamp Target Time Reached for Target Time PPS1 status not detected
44062  */
44063 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK)
44064 
44065 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK (0x20U)
44066 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT (5U)
44067 /*! TSTRGTERR1 - Timestamp Target Time Error This bit is set when the latest target time programmed
44068  *    in the MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers elapses.
44069  *  0b1..Timestamp Target Time Error status detected
44070  *  0b0..Timestamp Target Time Error status not detected
44071  */
44072 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK)
44073 
44074 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK (0x40U)
44075 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT (6U)
44076 /*! TSTARGT2 - Timestamp Target Time Reached for Target Time PPS2 When set, this bit indicates that
44077  *    the value of system time is greater than or equal to the value specified in the
44078  *    MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers.
44079  *  0b1..Timestamp Target Time Reached for Target Time PPS2 status detected
44080  *  0b0..Timestamp Target Time Reached for Target Time PPS2 status not detected
44081  */
44082 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK)
44083 
44084 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK (0x80U)
44085 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT (7U)
44086 /*! TSTRGTERR2 - Timestamp Target Time Error This bit is set when the latest target time programmed
44087  *    in the MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers elapses.
44088  *  0b1..Timestamp Target Time Error status detected
44089  *  0b0..Timestamp Target Time Error status not detected
44090  */
44091 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK)
44092 
44093 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK (0x100U)
44094 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT (8U)
44095 /*! TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 When this bit is set, it indicates
44096  *    that the value of system time is greater than or equal to the value specified in the
44097  *    MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers.
44098  *  0b1..Timestamp Target Time Reached for Target Time PPS3 status detected
44099  *  0b0..Timestamp Target Time Reached for Target Time PPS3 status not detected
44100  */
44101 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK)
44102 
44103 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK (0x200U)
44104 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT (9U)
44105 /*! TSTRGTERR3 - Timestamp Target Time Error This bit is set when the latest target time programmed
44106  *    in the MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers elapses.
44107  *  0b1..Timestamp Target Time Error status detected
44108  *  0b0..Timestamp Target Time Error status not detected
44109  */
44110 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK)
44111 
44112 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK (0x8000U)
44113 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT (15U)
44114 /*! TXTSSIS - Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop
44115  *    transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in
44116  *    the MAC_TX_TIMESTAMP_STATUS_NANOSECONDS and MAC_TX_TIMESTAMP_STATUS_SECONDS registers.
44117  *  0b1..Tx Timestamp Status Interrupt status detected
44118  *  0b0..Tx Timestamp Status Interrupt status not detected
44119  */
44120 #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK)
44121 
44122 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK (0xF0000U)
44123 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT (16U)
44124 /*! ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary
44125  *    trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable.
44126  */
44127 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK)
44128 
44129 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK (0x1000000U)
44130 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT (24U)
44131 /*! ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary
44132  *    timestamp snapshot FIFO is full and external trigger was set.
44133  *  0b1..Auxiliary Timestamp Snapshot Trigger Missed status detected
44134  *  0b0..Auxiliary Timestamp Snapshot Trigger Missed status not detected
44135  */
44136 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK)
44137 
44138 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK (0x3E000000U)
44139 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT (25U)
44140 /*! ATSNS - Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO. */
44141 #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK)
44142 /*! @} */
44143 
44144 /*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Transmit Timestamp Status Nanoseconds */
44145 /*! @{ */
44146 
44147 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFFU)
44148 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0U)
44149 /*! TXTSSLO - Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field
44150  *    of the Transmit packet's captured timestamp.
44151  */
44152 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK)
44153 
44154 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK (0x80000000U)
44155 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT (31U)
44156 /*! TXTSSMIS - Transmit Timestamp Status Missed When this bit is set, it indicates one of the
44157  *    following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the TIMESTAMP_CONTROL
44158  *    register is reset - The timestamp of the previous packet is overwritten with timestamp of the
44159  *    current packet if TXTSSTSM bit of the MAC_TIMESTAMP_CONTROL register is set.
44160  *  0b1..Transmit Timestamp Status Missed status detected
44161  *  0b0..Transmit Timestamp Status Missed status not detected
44162  */
44163 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK)
44164 /*! @} */
44165 
44166 /*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Transmit Timestamp Status Seconds */
44167 /*! @{ */
44168 
44169 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFFU)
44170 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0U)
44171 /*! TXTSSHI - Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds
44172  *    field of Transmit packet's captured timestamp.
44173  */
44174 #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK)
44175 /*! @} */
44176 
44177 /*! @name MAC_AUXILIARY_CONTROL - Auxiliary Timestamp Control */
44178 /*! @{ */
44179 
44180 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK (0x1U)
44181 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT (0U)
44182 /*! ATSFC - Auxiliary Snapshot FIFO Clear When set, this bit resets the pointers of the Auxiliary Snapshot FIFO.
44183  *  0b0..Auxiliary Snapshot FIFO Clear is disabled
44184  *  0b1..Auxiliary Snapshot FIFO Clear is enabled
44185  */
44186 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK)
44187 
44188 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK (0x10U)
44189 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT (4U)
44190 /*! ATSEN0 - Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0.
44191  *  0b0..Auxiliary Snapshot $i is disabled
44192  *  0b1..Auxiliary Snapshot $i is enabled
44193  */
44194 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK)
44195 
44196 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK (0x20U)
44197 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT (5U)
44198 /*! ATSEN1 - Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1.
44199  *  0b0..Auxiliary Snapshot $i is disabled
44200  *  0b1..Auxiliary Snapshot $i is enabled
44201  */
44202 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK)
44203 
44204 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK (0x40U)
44205 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT (6U)
44206 /*! ATSEN2 - Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2.
44207  *  0b0..Auxiliary Snapshot $i is disabled
44208  *  0b1..Auxiliary Snapshot $i is enabled
44209  */
44210 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK)
44211 
44212 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK (0x80U)
44213 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT (7U)
44214 /*! ATSEN3 - Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3.
44215  *  0b0..Auxiliary Snapshot $i is disabled
44216  *  0b1..Auxiliary Snapshot $i is enabled
44217  */
44218 #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK)
44219 /*! @} */
44220 
44221 /*! @name MAC_AUXILIARY_TIMESTAMP_NANOSECONDS - Auxiliary Timestamp Nanoseconds */
44222 /*! @{ */
44223 
44224 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK (0x7FFFFFFFU)
44225 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT (0U)
44226 /*! AUXTSLO - Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp. */
44227 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK)
44228 /*! @} */
44229 
44230 /*! @name MAC_AUXILIARY_TIMESTAMP_SECONDS - Auxiliary Timestamp Seconds */
44231 /*! @{ */
44232 
44233 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK (0xFFFFFFFFU)
44234 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT (0U)
44235 /*! AUXTSHI - Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. */
44236 #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK)
44237 /*! @} */
44238 
44239 /*! @name MAC_TIMESTAMP_INGRESS_ASYM_CORR - Timestamp Ingress Asymmetry Correction */
44240 /*! @{ */
44241 
44242 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xFFFFFFFFU)
44243 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT (0U)
44244 /*! OSTIAC - One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path
44245  *    asymmetry value to be added to correctionField of Pdelay_Resp PTP packet.
44246  */
44247 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK)
44248 /*! @} */
44249 
44250 /*! @name MAC_TIMESTAMP_EGRESS_ASYM_CORR - imestamp Egress Asymmetry Correction */
44251 /*! @{ */
44252 
44253 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xFFFFFFFFU)
44254 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT (0U)
44255 /*! OSTEAC - One-Step Timestamp Egress Asymmetry Correction This field contains the egress path
44256  *    asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet.
44257  */
44258 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK)
44259 /*! @} */
44260 
44261 /*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp Ingress Correction Nanosecond */
44262 /*! @{ */
44263 
44264 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
44265 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
44266 /*! TSIC - Timestamp Ingress Correction This field contains the ingress path correction value as
44267  *    defined by the Ingress Correction expression.
44268  */
44269 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
44270 /*! @} */
44271 
44272 /*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp Egress Correction Nanosecond */
44273 /*! @{ */
44274 
44275 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
44276 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
44277 /*! TSEC - Timestamp Egress Correction This field contains the nanoseconds part of the egress path
44278  *    correction value as defined by the Egress Correction expression.
44279  */
44280 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
44281 /*! @} */
44282 
44283 /*! @name MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC - Timestamp Ingress Correction Subnanosecond */
44284 /*! @{ */
44285 
44286 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xFF00U)
44287 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT (8U)
44288 /*! TSICSNS - Timestamp Ingress Correction, sub-nanoseconds This field contains the sub-nanoseconds
44289  *    part of the ingress path correction value as defined by the "Ingress Correction" expression.
44290  */
44291 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK)
44292 /*! @} */
44293 
44294 /*! @name MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC - Timestamp Egress Correction Subnanosecond */
44295 /*! @{ */
44296 
44297 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xFF00U)
44298 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT (8U)
44299 /*! TSECSNS - Timestamp Egress Correction, sub-nanoseconds This field contains the sub-nanoseconds
44300  *    part of the egress path correction value as defined by the "Egress Correction" expression.
44301  */
44302 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK)
44303 /*! @} */
44304 
44305 /*! @name MAC_TIMESTAMP_INGRESS_LATENCY - Timestamp Ingress Latency */
44306 /*! @{ */
44307 
44308 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF00U)
44309 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8U)
44310 /*! ITLSNS - Ingress Timestamp Latency, in nanoseconds This register holds the average latency in
44311  *    nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the
44312  *    ingress timestamp is taken.
44313  */
44314 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK)
44315 
44316 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF0000U)
44317 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16U)
44318 /*! ITLNS - Ingress Timestamp Latency, in sub-nanoseconds This register holds the average latency in
44319  *    sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII)
44320  *    where the ingress timestamp is taken.
44321  */
44322 #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK)
44323 /*! @} */
44324 
44325 /*! @name MAC_TIMESTAMP_EGRESS_LATENCY - Timestamp Egress Latency */
44326 /*! @{ */
44327 
44328 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF00U)
44329 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8U)
44330 /*! ETLSNS - Egress Timestamp Latency, in sub-nanoseconds This register holds the average latency in
44331  *    sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and
44332  *    the output ports (phy_txd_o) of the MAC.
44333  */
44334 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK)
44335 
44336 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF0000U)
44337 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16U)
44338 /*! ETLNS - Egress Timestamp Latency, in nanoseconds This register holds the average latency in
44339  *    nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output
44340  *    ports (phy_txd_o) of the MAC.
44341  */
44342 #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK)
44343 /*! @} */
44344 
44345 /*! @name MAC_PPS_CONTROL - PPS Control */
44346 /*! @{ */
44347 
44348 #define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xFU)
44349 #define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0U)
44350 /*! PPSCTRL_PPSCMD - PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. */
44351 #define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK)
44352 
44353 #define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK     (0x10U)
44354 #define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT    (4U)
44355 /*! PPSEN0 - Flexible PPS Output Mode Enable When this bit is set, Bits[3:0] function as PPSCMD.
44356  *  0b0..Flexible PPS Output Mode is disabled
44357  *  0b1..Flexible PPS Output Mode is enabled
44358  */
44359 #define ENET_QOS_MAC_PPS_CONTROL_PPSEN0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK)
44360 
44361 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK (0x60U)
44362 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT (5U)
44363 /*! TRGTMODSEL0 - Target Time Register Mode for PPS0 Output This field indicates the Target Time
44364  *    registers (MAC_PPS0_TARGET_TIME_SECONDS and MAC_PPS0_TARGET_TIME_NANOSECONDS) mode for PPS0
44365  *    output signal:
44366  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
44367  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
44368  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
44369  *        ptp_pps_o output port
44370  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
44371  *  0b01..Reserved
44372  */
44373 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK)
44374 
44375 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK    (0x80U)
44376 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT   (7U)
44377 /*! MCGREN0 - MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode.
44378  *  0b1..0th PPS instance is enabled to operate in MCGR mode
44379  *  0b0..0th PPS instance is enabled to operate in PPS mode
44380  */
44381 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK)
44382 
44383 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK    (0xF00U)
44384 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT   (8U)
44385 /*! PPSCMD1 - Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. */
44386 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK)
44387 
44388 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK (0x6000U)
44389 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT (13U)
44390 /*! TRGTMODSEL1 - Target Time Register Mode for PPS1 Output This field indicates the Target Time
44391  *    registers (MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS) mode for PPS1
44392  *    output signal.
44393  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
44394  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
44395  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
44396  *        ptp_pps_o output port
44397  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
44398  *  0b01..Reserved
44399  */
44400 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK)
44401 
44402 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK    (0x8000U)
44403 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT   (15U)
44404 /*! MCGREN1 - MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode.
44405  *  0b0..1st PPS instance is disabled to operate in PPS or MCGR mode
44406  *  0b1..1st PPS instance is enabled to operate in PPS or MCGR mode
44407  */
44408 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN1(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK)
44409 
44410 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK    (0xF0000U)
44411 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT   (16U)
44412 /*! PPSCMD2 - Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. */
44413 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK)
44414 
44415 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK (0x600000U)
44416 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT (21U)
44417 /*! TRGTMODSEL2 - Target Time Register Mode for PPS2 Output This field indicates the Target Time
44418  *    registers (MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS) mode for PPS2
44419  *    output signal.
44420  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
44421  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
44422  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
44423  *        ptp_pps_o output port
44424  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
44425  *  0b01..Reserved
44426  */
44427 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK)
44428 
44429 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK    (0x800000U)
44430 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT   (23U)
44431 /*! MCGREN2 - MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode.
44432  *  0b0..2nd PPS instance is disabled to operate in PPS or MCGR mode
44433  *  0b1..2nd PPS instance is enabled to operate in PPS or MCGR mode
44434  */
44435 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN2(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK)
44436 
44437 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK    (0xF000000U)
44438 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT   (24U)
44439 /*! PPSCMD3 - Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. */
44440 #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK)
44441 
44442 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK (0x60000000U)
44443 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT (29U)
44444 /*! TRGTMODSEL3 - Target Time Register Mode for PPS3 Output This field indicates the Target Time
44445  *    registers (MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS) mode for PPS3
44446  *    output signal.
44447  *  0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
44448  *  0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
44449  *        must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
44450  *        ptp_pps_o output port
44451  *  0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
44452  *  0b01..Reserved
44453  */
44454 #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK)
44455 
44456 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK    (0x80000000U)
44457 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT   (31U)
44458 /*! MCGREN3 - MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode. */
44459 #define ENET_QOS_MAC_PPS_CONTROL_MCGREN3(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK)
44460 /*! @} */
44461 
44462 /*! @name MAC_PPS0_TARGET_TIME_SECONDS - PPS0 Target Time Seconds */
44463 /*! @{ */
44464 
44465 #define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFFU)
44466 #define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0U)
44467 /*! TSTRH0 - PPS Target Time Seconds Register This field stores the time in seconds. */
44468 #define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK)
44469 /*! @} */
44470 
44471 /*! @name MAC_PPS0_TARGET_TIME_NANOSECONDS - PPS0 Target Time Nanoseconds */
44472 /*! @{ */
44473 
44474 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFFU)
44475 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0U)
44476 /*! TTSL0 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */
44477 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK)
44478 
44479 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK (0x80000000U)
44480 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT (31U)
44481 /*! TRGTBUSY0 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
44482  *    PPS_CONTROL register is programmed to 010 or 011.
44483  *  0b1..PPS Target Time Register Busy is detected
44484  *  0b0..PPS Target Time Register Busy status is not detected
44485  */
44486 #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK)
44487 /*! @} */
44488 
44489 /*! @name MAC_PPS0_INTERVAL - PPS0 Interval */
44490 /*! @{ */
44491 
44492 #define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK  (0xFFFFFFFFU)
44493 #define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT (0U)
44494 /*! PPSINT0 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. */
44495 #define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT)) & ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK)
44496 /*! @} */
44497 
44498 /*! @name MAC_PPS0_WIDTH - PPS0 Width */
44499 /*! @{ */
44500 
44501 #define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK   (0xFFFFFFFFU)
44502 #define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT  (0U)
44503 /*! PPSWIDTH0 - PPS Output Signal Width These bits store the width between the rising edge and
44504  *    corresponding falling edge of PPS0 signal output.
44505  */
44506 #define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT)) & ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK)
44507 /*! @} */
44508 
44509 /*! @name MAC_PPS1_TARGET_TIME_SECONDS - PPS1 Target Time Seconds */
44510 /*! @{ */
44511 
44512 #define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xFFFFFFFFU)
44513 #define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT (0U)
44514 /*! TSTRH1 - PPS Target Time Seconds Register This field stores the time in seconds. */
44515 #define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK)
44516 /*! @} */
44517 
44518 /*! @name MAC_PPS1_TARGET_TIME_NANOSECONDS - PPS1 Target Time Nanoseconds */
44519 /*! @{ */
44520 
44521 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7FFFFFFFU)
44522 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT (0U)
44523 /*! TTSL1 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */
44524 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK)
44525 
44526 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK (0x80000000U)
44527 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT (31U)
44528 /*! TRGTBUSY1 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
44529  *    PPS_CONTROL register is programmed to 010 or 011.
44530  *  0b1..PPS Target Time Register Busy is detected
44531  *  0b0..PPS Target Time Register Busy status is not detected
44532  */
44533 #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK)
44534 /*! @} */
44535 
44536 /*! @name MAC_PPS1_INTERVAL - PPS1 Interval */
44537 /*! @{ */
44538 
44539 #define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK  (0xFFFFFFFFU)
44540 #define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT (0U)
44541 /*! PPSINT1 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. */
44542 #define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT)) & ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK)
44543 /*! @} */
44544 
44545 /*! @name MAC_PPS1_WIDTH - PPS1 Width */
44546 /*! @{ */
44547 
44548 #define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK   (0xFFFFFFFFU)
44549 #define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT  (0U)
44550 /*! PPSWIDTH1 - PPS Output Signal Width These bits store the width between the rising edge and
44551  *    corresponding falling edge of PPS0 signal output.
44552  */
44553 #define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT)) & ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK)
44554 /*! @} */
44555 
44556 /*! @name MAC_PPS2_TARGET_TIME_SECONDS - PPS2 Target Time Seconds */
44557 /*! @{ */
44558 
44559 #define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xFFFFFFFFU)
44560 #define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT (0U)
44561 /*! TSTRH2 - PPS Target Time Seconds Register This field stores the time in seconds. */
44562 #define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK)
44563 /*! @} */
44564 
44565 /*! @name MAC_PPS2_TARGET_TIME_NANOSECONDS - PPS2 Target Time Nanoseconds */
44566 /*! @{ */
44567 
44568 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7FFFFFFFU)
44569 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT (0U)
44570 /*! TTSL2 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */
44571 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK)
44572 
44573 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK (0x80000000U)
44574 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT (31U)
44575 /*! TRGTBUSY2 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
44576  *    PPS_CONTROL register is programmed to 010 or 011.
44577  *  0b1..PPS Target Time Register Busy is detected
44578  *  0b0..PPS Target Time Register Busy status is not detected
44579  */
44580 #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK)
44581 /*! @} */
44582 
44583 /*! @name MAC_PPS2_INTERVAL - PPS2 Interval */
44584 /*! @{ */
44585 
44586 #define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK  (0xFFFFFFFFU)
44587 #define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT (0U)
44588 /*! PPSINT2 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. */
44589 #define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT)) & ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK)
44590 /*! @} */
44591 
44592 /*! @name MAC_PPS2_WIDTH - PPS2 Width */
44593 /*! @{ */
44594 
44595 #define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK   (0xFFFFFFFFU)
44596 #define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT  (0U)
44597 /*! PPSWIDTH2 - PPS Output Signal Width These bits store the width between the rising edge and
44598  *    corresponding falling edge of PPS0 signal output.
44599  */
44600 #define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT)) & ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK)
44601 /*! @} */
44602 
44603 /*! @name MAC_PPS3_TARGET_TIME_SECONDS - PPS3 Target Time Seconds */
44604 /*! @{ */
44605 
44606 #define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xFFFFFFFFU)
44607 #define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT (0U)
44608 /*! TSTRH3 - PPS Target Time Seconds Register This field stores the time in seconds. */
44609 #define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK)
44610 /*! @} */
44611 
44612 /*! @name MAC_PPS3_TARGET_TIME_NANOSECONDS - PPS3 Target Time Nanoseconds */
44613 /*! @{ */
44614 
44615 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7FFFFFFFU)
44616 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT (0U)
44617 /*! TTSL3 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */
44618 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK)
44619 
44620 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK (0x80000000U)
44621 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT (31U)
44622 /*! TRGTBUSY3 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
44623  *    PPS_CONTROL register is programmed to 010 or 011.
44624  *  0b1..PPS Target Time Register Busy is detected
44625  *  0b0..PPS Target Time Register Busy status is not detected
44626  */
44627 #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK)
44628 /*! @} */
44629 
44630 /*! @name MAC_PPS3_INTERVAL - PPS3 Interval */
44631 /*! @{ */
44632 
44633 #define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK  (0xFFFFFFFFU)
44634 #define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT (0U)
44635 /*! PPSINT3 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. */
44636 #define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT)) & ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK)
44637 /*! @} */
44638 
44639 /*! @name MAC_PPS3_WIDTH - PPS3 Width */
44640 /*! @{ */
44641 
44642 #define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK   (0xFFFFFFFFU)
44643 #define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT  (0U)
44644 /*! PPSWIDTH3 - PPS Output Signal Width These bits store the width between the rising edge and
44645  *    corresponding falling edge of PPS0 signal output.
44646  */
44647 #define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT)) & ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK)
44648 /*! @} */
44649 
44650 /*! @name MAC_PTO_CONTROL - PTP Offload Engine Control */
44651 /*! @{ */
44652 
44653 #define ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK      (0x1U)
44654 #define ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT     (0U)
44655 /*! PTOEN - PTP Offload Enable When this bit is set, the PTP Offload feature is enabled.
44656  *  0b0..PTP Offload feature is disabled
44657  *  0b1..PTP Offload feature is enabled
44658  */
44659 #define ENET_QOS_MAC_PTO_CONTROL_PTOEN(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK)
44660 
44661 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK    (0x2U)
44662 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT   (1U)
44663 /*! ASYNCEN - Automatic PTP SYNC message Enable When this bit is set, PTP SYNC message is generated
44664  *    periodically based on interval programmed or trigger from application, when the MAC is
44665  *    programmed to be in Clock Master mode.
44666  *  0b0..Automatic PTP SYNC message is disabled
44667  *  0b1..Automatic PTP SYNC message is enabled
44668  */
44669 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK)
44670 
44671 #define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK   (0x4U)
44672 #define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT  (2U)
44673 /*! APDREQEN - Automatic PTP Pdelay_Req message Enable When this bit is set, PTP Pdelay_Req message
44674  *    is generated periodically based on interval programmed or trigger from application, when the
44675  *    MAC is programmed to be in Peer-to-Peer Transparent mode.
44676  *  0b0..Automatic PTP Pdelay_Req message is disabled
44677  *  0b1..Automatic PTP Pdelay_Req message is enabled
44678  */
44679 #define ENET_QOS_MAC_PTO_CONTROL_APDREQEN(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK)
44680 
44681 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK  (0x10U)
44682 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT (4U)
44683 /*! ASYNCTRIG - Automatic PTP SYNC message Trigger When this bit is set, one PTP SYNC message is transmitted.
44684  *  0b0..Automatic PTP SYNC message Trigger is disabled
44685  *  0b1..Automatic PTP SYNC message Trigger is enabled
44686  */
44687 #define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK)
44688 
44689 #define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK (0x20U)
44690 #define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT (5U)
44691 /*! APDREQTRIG - Automatic PTP Pdelay_Req message Trigger When this bit is set, one PTP Pdelay_Req message is transmitted.
44692  *  0b0..Automatic PTP Pdelay_Req message Trigger is disabled
44693  *  0b1..Automatic PTP Pdelay_Req message Trigger is enabled
44694  */
44695 #define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK)
44696 
44697 #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK     (0x40U)
44698 #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT    (6U)
44699 /*! DRRDIS - Disable PTO Delay Request/Response response generation When this bit is set, the Delay
44700  *    Request and Delay response is not generated for received SYNC and Delay request packet
44701  *    respectively, as required by the programmed mode.
44702  *  0b1..PTO Delay Request/Response response generation is disabled
44703  *  0b0..PTO Delay Request/Response response generation is enabled
44704  */
44705 #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK)
44706 
44707 #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK     (0x80U)
44708 #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT    (7U)
44709 /*! PDRDIS - Disable Peer Delay Response response generation When this bit is set, the Peer Delay
44710  *    Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req)
44711  *    request packet, as required by the programmed mode.
44712  *  0b1..Peer Delay Response response generation is disabled
44713  *  0b0..Peer Delay Response response generation is enabled
44714  */
44715 #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK)
44716 
44717 #define ENET_QOS_MAC_PTO_CONTROL_DN_MASK         (0xFF00U)
44718 #define ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT        (8U)
44719 /*! DN - Domain Number This field indicates the domain Number in which the PTP node is operating. */
44720 #define ENET_QOS_MAC_PTO_CONTROL_DN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DN_MASK)
44721 /*! @} */
44722 
44723 /*! @name MAC_SOURCE_PORT_IDENTITY0 - Source Port Identity 0 */
44724 /*! @{ */
44725 
44726 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK (0xFFFFFFFFU)
44727 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT (0U)
44728 /*! SPI0 - Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node. */
44729 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK)
44730 /*! @} */
44731 
44732 /*! @name MAC_SOURCE_PORT_IDENTITY1 - Source Port Identity 1 */
44733 /*! @{ */
44734 
44735 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK (0xFFFFFFFFU)
44736 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT (0U)
44737 /*! SPI1 - Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node. */
44738 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK)
44739 /*! @} */
44740 
44741 /*! @name MAC_SOURCE_PORT_IDENTITY2 - Source Port Identity 2 */
44742 /*! @{ */
44743 
44744 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK (0xFFFFU)
44745 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT (0U)
44746 /*! SPI2 - Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node. */
44747 #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK)
44748 /*! @} */
44749 
44750 /*! @name MAC_LOG_MESSAGE_INTERVAL - Log Message Interval */
44751 /*! @{ */
44752 
44753 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK (0xFFU)
44754 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT (0U)
44755 /*! LSI - Log Sync Interval This field indicates the periodicity of the automatically generated SYNC
44756  *    message when the PTP node is Master.
44757  */
44758 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK)
44759 
44760 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK (0x700U)
44761 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT (8U)
44762 /*! DRSYNCR - Delay_Req to SYNC Ratio In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted.
44763  *  0b110..Reserved
44764  *  0b000..DelayReq generated for every received SYNC
44765  *  0b100..for every 16 SYNC messages
44766  *  0b001..DelayReq generated every alternate reception of SYNC
44767  *  0b101..for every 32 SYNC messages
44768  *  0b010..for every 4 SYNC messages
44769  *  0b011..for every 8 SYNC messages
44770  */
44771 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK)
44772 
44773 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK (0xFF000000U)
44774 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT (24U)
44775 /*! LMPDRI - Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node. */
44776 #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK)
44777 /*! @} */
44778 
44779 /*! @name MTL_OPERATION_MODE - MTL Operation Mode */
44780 /*! @{ */
44781 
44782 #define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK  (0x2U)
44783 #define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT (1U)
44784 /*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL.
44785  *  0b0..Drop Transmit Status is disabled
44786  *  0b1..Drop Transmit Status is enabled
44787  */
44788 #define ENET_QOS_MTL_OPERATION_MODE_DTXSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK)
44789 
44790 #define ENET_QOS_MTL_OPERATION_MODE_RAA_MASK     (0x4U)
44791 #define ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT    (2U)
44792 /*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side.
44793  *  0b0..Strict priority (SP)
44794  *  0b1..Weighted Strict Priority (WSP)
44795  */
44796 #define ENET_QOS_MTL_OPERATION_MODE_RAA(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_RAA_MASK)
44797 
44798 #define ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK  (0x60U)
44799 #define ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT (5U)
44800 /*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling:
44801  *  0b10..DWRR algorithm when DCB feature is selected.Otherwise, Reserved
44802  *  0b11..Strict priority algorithm
44803  *  0b01..WFQ algorithm when DCB feature is selected.Otherwise, Reserved
44804  *  0b00..WRR algorithm
44805  */
44806 #define ENET_QOS_MTL_OPERATION_MODE_SCHALG(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK)
44807 
44808 #define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK (0x100U)
44809 #define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT (8U)
44810 /*! CNTPRST - Counters Preset When this bit is set, - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0.
44811  *  0b0..Counters Preset is disabled
44812  *  0b1..Counters Preset is enabled
44813  */
44814 #define ENET_QOS_MTL_OPERATION_MODE_CNTPRST(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK)
44815 
44816 #define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK  (0x200U)
44817 #define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT (9U)
44818 /*! CNTCLR - Counters Reset When this bit is set, all counters are reset.
44819  *  0b0..Counters are not reset
44820  *  0b1..All counters are reset
44821  */
44822 #define ENET_QOS_MTL_OPERATION_MODE_CNTCLR(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK)
44823 
44824 #define ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK    (0x8000U)
44825 #define ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT   (15U)
44826 /*! FRPE - Flexible Rx parser Enable When this bit is set to 1, the Programmable Rx Parser functionality is enabled.
44827  *  0b0..Flexible Rx parser is disabled
44828  *  0b1..Flexible Rx parser is enabled
44829  */
44830 #define ENET_QOS_MTL_OPERATION_MODE_FRPE(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK)
44831 /*! @} */
44832 
44833 /*! @name MTL_DBG_CTL - FIFO Debug Access Control and Status */
44834 /*! @{ */
44835 
44836 #define ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK         (0x1U)
44837 #define ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT        (0U)
44838 /*! FDBGEN - FIFO Debug Access Enable When this bit is set, it indicates that the debug mode access to the FIFO is enabled.
44839  *  0b0..FIFO Debug Access is disabled
44840  *  0b1..FIFO Debug Access is enabled
44841  */
44842 #define ENET_QOS_MTL_DBG_CTL_FDBGEN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK)
44843 
44844 #define ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK         (0x2U)
44845 #define ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT        (1U)
44846 /*! DBGMOD - Debug Mode Access to FIFO When this bit is set, it indicates that the current access to
44847  *    the FIFO is read, write, and debug access.
44848  *  0b0..Debug Mode Access to FIFO is disabled
44849  *  0b1..Debug Mode Access to FIFO is enabled
44850  */
44851 #define ENET_QOS_MTL_DBG_CTL_DBGMOD(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT)) & ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK)
44852 
44853 #define ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK         (0xCU)
44854 #define ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT        (2U)
44855 /*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Write operation.
44856  *  0b11..All four bytes are valid
44857  *  0b10..Byte 0, Byte 1, and Byte 2 are valid
44858  *  0b01..Byte 0 and Byte 1 are valid
44859  *  0b00..Byte 0 valid
44860  */
44861 #define ENET_QOS_MTL_DBG_CTL_BYTEEN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK)
44862 
44863 #define ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK       (0x60U)
44864 #define ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT      (5U)
44865 /*! PKTSTATE - Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO.
44866  *  0b01..Control Word/Normal Status
44867  *  0b11..EOP Data/EOP
44868  *  0b00..Packet Data
44869  *  0b10..SOP Data/Last Status
44870  */
44871 #define ENET_QOS_MTL_DBG_CTL_PKTSTATE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK)
44872 
44873 #define ENET_QOS_MTL_DBG_CTL_RSTALL_MASK         (0x100U)
44874 #define ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT        (8U)
44875 /*! RSTALL - Reset All Pointers When this bit is set, the pointers of all FIFOs are reset when FIFO Debug Access is enabled.
44876  *  0b0..Reset All Pointers is disabled
44877  *  0b1..Reset All Pointers is enabled
44878  */
44879 #define ENET_QOS_MTL_DBG_CTL_RSTALL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTALL_MASK)
44880 
44881 #define ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK         (0x200U)
44882 #define ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT        (9U)
44883 /*! RSTSEL - Reset Pointers of Selected FIFO When this bit is set, the pointers of the
44884  *    currently-selected FIFO are reset when FIFO Debug Access is enabled.
44885  *  0b0..Reset Pointers of Selected FIFO is disabled
44886  *  0b1..Reset Pointers of Selected FIFO is enabled
44887  */
44888 #define ENET_QOS_MTL_DBG_CTL_RSTSEL(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK)
44889 
44890 #define ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK       (0x400U)
44891 #define ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT      (10U)
44892 /*! FIFORDEN - FIFO Read Enable When this bit is set, it enables the Read operation on selected FIFO when FIFO Debug Access is enabled.
44893  *  0b0..FIFO Read is disabled
44894  *  0b1..FIFO Read is enabled
44895  */
44896 #define ENET_QOS_MTL_DBG_CTL_FIFORDEN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK)
44897 
44898 #define ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK       (0x800U)
44899 #define ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT      (11U)
44900 /*! FIFOWREN - FIFO Write Enable When this bit is set, it enables the Write operation on selected
44901  *    FIFO when FIFO Debug Access is enabled.
44902  *  0b0..FIFO Write is disabled
44903  *  0b1..FIFO Write is enabled
44904  */
44905 #define ENET_QOS_MTL_DBG_CTL_FIFOWREN(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK)
44906 
44907 #define ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK        (0x3000U)
44908 #define ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT       (12U)
44909 /*! FIFOSEL - FIFO Selected for Access This field indicates the FIFO selected for debug access:
44910  *  0b11..Rx FIFO
44911  *  0b10..TSO FIFO (cannot be accessed when SLVMOD is set)
44912  *  0b00..Tx FIFO
44913  *  0b01..Tx Status FIFO (only read access when SLVMOD is set)
44914  */
44915 #define ENET_QOS_MTL_DBG_CTL_FIFOSEL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK)
44916 
44917 #define ENET_QOS_MTL_DBG_CTL_PKTIE_MASK          (0x4000U)
44918 #define ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT         (14U)
44919 /*! PKTIE - Receive Packet Available Interrupt Status Enable When this bit is set, an interrupt is
44920  *    generated when EOP of received packet is written to the Rx FIFO.
44921  *  0b0..Receive Packet Available Interrupt Status is disabled
44922  *  0b1..Receive Packet Available Interrupt Status is enabled
44923  */
44924 #define ENET_QOS_MTL_DBG_CTL_PKTIE(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTIE_MASK)
44925 
44926 #define ENET_QOS_MTL_DBG_CTL_STSIE_MASK          (0x8000U)
44927 #define ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT         (15U)
44928 /*! STSIE - Transmit Status Available Interrupt Status Enable When this bit is set, an interrupt is
44929  *    generated when Transmit status is available in slave mode.
44930  *  0b0..Transmit Packet Available Interrupt Status is disabled
44931  *  0b1..Transmit Packet Available Interrupt Status is enabled
44932  */
44933 #define ENET_QOS_MTL_DBG_CTL_STSIE(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_STSIE_MASK)
44934 /*! @} */
44935 
44936 /*! @name MTL_DBG_STS - FIFO Debug Status */
44937 /*! @{ */
44938 
44939 #define ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK       (0x1U)
44940 #define ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT      (0U)
44941 /*! FIFOBUSY - FIFO Busy When set, this bit indicates that a FIFO operation is in progress in the
44942  *    MAC and content of the following fields is not valid: - All other fields of this register - All
44943  *    fields of the MTL_FIFO_DEBUG_DATA register
44944  *  0b1..FIFO Busy detected
44945  *  0b0..FIFO Busy not detected
44946  */
44947 #define ENET_QOS_MTL_DBG_STS_FIFOBUSY(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT)) & ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK)
44948 
44949 #define ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK       (0x6U)
44950 #define ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT      (1U)
44951 /*! PKTSTATE - Encoded Packet State This field is used to get the control or status information of the selected FIFO.
44952  *  0b01..Control Word/Normal Status
44953  *  0b11..EOP Data/EOP
44954  *  0b00..Packet Data
44955  *  0b10..SOP Data/Last Status
44956  */
44957 #define ENET_QOS_MTL_DBG_STS_PKTSTATE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK)
44958 
44959 #define ENET_QOS_MTL_DBG_STS_BYTEEN_MASK         (0x18U)
44960 #define ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT        (3U)
44961 /*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Read operation.
44962  *  0b11..All four bytes are valid
44963  *  0b10..Byte 0, Byte 1, and Byte 2 are valid
44964  *  0b01..Byte 0 and Byte 1 are valid
44965  *  0b00..Byte 0 valid
44966  */
44967 #define ENET_QOS_MTL_DBG_STS_BYTEEN(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_STS_BYTEEN_MASK)
44968 
44969 #define ENET_QOS_MTL_DBG_STS_PKTI_MASK           (0x100U)
44970 #define ENET_QOS_MTL_DBG_STS_PKTI_SHIFT          (8U)
44971 /*! PKTI - Receive Packet Available Interrupt Status When set, this bit indicates that MAC layer has
44972  *    written the EOP of received packet to the Rx FIFO.
44973  *  0b1..Receive Packet Available Interrupt Status detected
44974  *  0b0..Receive Packet Available Interrupt Status not detected
44975  */
44976 #define ENET_QOS_MTL_DBG_STS_PKTI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTI_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTI_MASK)
44977 
44978 #define ENET_QOS_MTL_DBG_STS_STSI_MASK           (0x200U)
44979 #define ENET_QOS_MTL_DBG_STS_STSI_SHIFT          (9U)
44980 /*! STSI - Transmit Status Available Interrupt Status When set, this bit indicates that the Slave
44981  *    mode Tx packet is transmitted, and the status is available in Tx Status FIFO.
44982  *  0b1..Transmit Status Available Interrupt Status detected
44983  *  0b0..Transmit Status Available Interrupt Status not detected
44984  */
44985 #define ENET_QOS_MTL_DBG_STS_STSI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_STSI_SHIFT)) & ENET_QOS_MTL_DBG_STS_STSI_MASK)
44986 
44987 #define ENET_QOS_MTL_DBG_STS_LOCR_MASK           (0xFFFF8000U)
44988 #define ENET_QOS_MTL_DBG_STS_LOCR_SHIFT          (15U)
44989 /*! LOCR - Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO. */
44990 #define ENET_QOS_MTL_DBG_STS_LOCR(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_LOCR_SHIFT)) & ENET_QOS_MTL_DBG_STS_LOCR_MASK)
44991 /*! @} */
44992 
44993 /*! @name MTL_FIFO_DEBUG_DATA - FIFO Debug Data */
44994 /*! @{ */
44995 
44996 #define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFFU)
44997 #define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0U)
44998 /*! FDBGDATA - FIFO Debug Data During debug or slave access write operation, this field contains the
44999  *    data to be written to the Tx FIFO, Rx FIFO, or TSO FIFO.
45000  */
45001 #define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT)) & ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK)
45002 /*! @} */
45003 
45004 /*! @name MTL_INTERRUPT_STATUS - MTL Interrupt Status */
45005 /*! @{ */
45006 
45007 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK  (0x1U)
45008 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT (0U)
45009 /*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0.
45010  *  0b1..Queue 0 Interrupt status detected
45011  *  0b0..Queue 0 Interrupt status not detected
45012  */
45013 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK)
45014 
45015 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK  (0x2U)
45016 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT (1U)
45017 /*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1.
45018  *  0b1..Queue 1 Interrupt status detected
45019  *  0b0..Queue 1 Interrupt status not detected
45020  */
45021 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK)
45022 
45023 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK  (0x4U)
45024 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT (2U)
45025 /*! Q2IS - Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2.
45026  *  0b1..Queue 2 Interrupt status detected
45027  *  0b0..Queue 2 Interrupt status not detected
45028  */
45029 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK)
45030 
45031 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK  (0x8U)
45032 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT (3U)
45033 /*! Q3IS - Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3.
45034  *  0b1..Queue 3 Interrupt status detected
45035  *  0b0..Queue 3 Interrupt status not detected
45036  */
45037 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK)
45038 
45039 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK  (0x10U)
45040 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT (4U)
45041 /*! Q4IS - Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4.
45042  *  0b1..Queue 4 Interrupt status detected
45043  *  0b0..Queue 4 Interrupt status not detected
45044  */
45045 #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK)
45046 
45047 #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK (0x20000U)
45048 #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT (17U)
45049 /*! DBGIS - Debug Interrupt status This bit indicates an interrupt event during the slave access.
45050  *  0b1..Debug Interrupt status detected
45051  *  0b0..Debug Interrupt status not detected
45052  */
45053 #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK)
45054 
45055 #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK (0x40000U)
45056 #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT (18U)
45057 /*! ESTIS - EST (TAS- 802.
45058  *  0b1..EST (TAS- 802.1Qbv) Interrupt status detected
45059  *  0b0..EST (TAS- 802.1Qbv) Interrupt status not detected
45060  */
45061 #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK)
45062 
45063 #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK (0x800000U)
45064 #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT (23U)
45065 /*! MTLPIS - MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block.
45066  *  0b1..MTL Rx Parser Interrupt status detected
45067  *  0b0..MTL Rx Parser Interrupt status not detected
45068  */
45069 #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK)
45070 /*! @} */
45071 
45072 /*! @name MTL_RXQ_DMA_MAP0 - Receive Queue and DMA Channel Mapping 0 */
45073 /*! @{ */
45074 
45075 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK  (0x7U)
45076 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT (0U)
45077 /*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received
45078  *    in Queue 0 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
45079  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
45080  *    field is valid when the Q0DDMACH field is reset.
45081  */
45082 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK)
45083 
45084 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK  (0x10U)
45085 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT (4U)
45086 /*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
45087  *    the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC
45088  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
45089  *    Ethernet DA address.
45090  *  0b0..Queue 0 disabled for DA-based DMA Channel Selection
45091  *  0b1..Queue 0 enabled for DA-based DMA Channel Selection
45092  */
45093 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK)
45094 
45095 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK  (0x700U)
45096 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT (8U)
45097 /*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet
45098  *    in Queue 1 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
45099  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
45100  *    field is valid when the Q1DDMACH field is reset.
45101  */
45102 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK)
45103 
45104 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK  (0x1000U)
45105 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT (12U)
45106 /*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
45107  *    the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC
45108  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
45109  *    Ethernet DA address.
45110  *  0b0..Queue 1 disabled for DA-based DMA Channel Selection
45111  *  0b1..Queue 1 enabled for DA-based DMA Channel Selection
45112  */
45113 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK)
45114 
45115 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK  (0x70000U)
45116 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT (16U)
45117 /*! Q2MDMACH - Queue 2 Mapped to DMA Channel This field controls the routing of the received packet
45118  *    in Queue 2 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
45119  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
45120  *    field is valid when the Q2DDMACH field is reset.
45121  */
45122 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK)
45123 
45124 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK  (0x100000U)
45125 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT (20U)
45126 /*! Q2DDMACH - Queue 2 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
45127  *    the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC
45128  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
45129  *    Ethernet DA address.
45130  *  0b0..Queue 2 disabled for DA-based DMA Channel Selection
45131  *  0b1..Queue 2 enabled for DA-based DMA Channel Selection
45132  */
45133 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK)
45134 
45135 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK  (0x7000000U)
45136 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT (24U)
45137 /*! Q3MDMACH - Queue 3 Mapped to DMA Channel This field controls the routing of the received packet
45138  *    in Queue 3 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
45139  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
45140  *    field is valid when the Q3DDMACH field is reset.
45141  */
45142 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK)
45143 
45144 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK  (0x10000000U)
45145 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT (28U)
45146 /*! Q3DDMACH - Queue 3 Enabled for Dynamic (per packet) DMA Channel Selection When set, this bit
45147  *    indicates that the packets received in Queue 3 are routed to a particular DMA channel as decided
45148  *    in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers,
45149  *    or the Ethernet DA address.
45150  *  0b0..Queue 3 disabled for DA-based DMA Channel Selection
45151  *  0b1..Queue 3 enabled for DA-based DMA Channel Selection
45152  */
45153 #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK)
45154 /*! @} */
45155 
45156 /*! @name MTL_RXQ_DMA_MAP1 - Receive Queue and DMA Channel Mapping 1 */
45157 /*! @{ */
45158 
45159 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK  (0x7U)
45160 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT (0U)
45161 /*! Q4MDMACH - Queue 4 Mapped to DMA Channel This field controls the routing of the packet received
45162  *    in Queue 4 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
45163  *    - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
45164  *    field is valid when the Q4DDMACH field is reset.
45165  */
45166 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK)
45167 
45168 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK  (0x10U)
45169 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT (4U)
45170 /*! Q4DDMACH - Queue 4 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
45171  *    the packets received in Queue 4 are routed to a particular DMA channel as decided in the MAC
45172  *    Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
45173  *    Ethernet DA address.
45174  *  0b0..Queue 4 disabled for DA-based DMA Channel Selection
45175  *  0b1..Queue 4 enabled for DA-based DMA Channel Selection
45176  */
45177 #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK)
45178 /*! @} */
45179 
45180 /*! @name MTL_TBS_CTRL - Time Based Scheduling Control */
45181 /*! @{ */
45182 
45183 #define ENET_QOS_MTL_TBS_CTRL_ESTM_MASK          (0x1U)
45184 #define ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT         (0U)
45185 /*! ESTM - EST offset Mode When this bit is set, the Launch Time value used in Time Based Scheduling
45186  *    is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the
45187  *    current list.
45188  *  0b0..EST offset Mode is disabled
45189  *  0b1..EST offset Mode is enabled
45190  */
45191 #define ENET_QOS_MTL_TBS_CTRL_ESTM(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_ESTM_MASK)
45192 
45193 #define ENET_QOS_MTL_TBS_CTRL_LEOV_MASK          (0x2U)
45194 #define ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT         (1U)
45195 /*! LEOV - Launch Expiry Offset Valid When set indicates the LEOS field is valid.
45196  *  0b0..LEOS field is invalid
45197  *  0b1..LEOS field is valid
45198  */
45199 #define ENET_QOS_MTL_TBS_CTRL_LEOV(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOV_MASK)
45200 
45201 #define ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK         (0x70U)
45202 #define ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT        (4U)
45203 /*! LEGOS - Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time. */
45204 #define ENET_QOS_MTL_TBS_CTRL_LEGOS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK)
45205 
45206 #define ENET_QOS_MTL_TBS_CTRL_LEOS_MASK          (0xFFFFFF00U)
45207 #define ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT         (8U)
45208 /*! LEOS - Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the
45209  *    Launch time to compute the Launch Expiry time.
45210  */
45211 #define ENET_QOS_MTL_TBS_CTRL_LEOS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOS_MASK)
45212 /*! @} */
45213 
45214 /*! @name MTL_EST_CONTROL - Enhancements to Scheduled Transmission Control */
45215 /*! @{ */
45216 
45217 #define ENET_QOS_MTL_EST_CONTROL_EEST_MASK       (0x1U)
45218 #define ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT      (0U)
45219 /*! EEST - Enable EST When reset, the gate control list processing is halted and all gates are assumed to be in Open state.
45220  *  0b0..EST is disabled
45221  *  0b1..EST is enabled
45222  */
45223 #define ENET_QOS_MTL_EST_CONTROL_EEST(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_EEST_MASK)
45224 
45225 #define ENET_QOS_MTL_EST_CONTROL_SSWL_MASK       (0x2U)
45226 #define ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT      (1U)
45227 /*! SSWL - Switch to S/W owned list When set indicates that the software has programmed that list
45228  *    that it currently owns (SWOL) and the hardware should switch to the new list based on the new
45229  *    BTR.
45230  *  0b0..Switch to S/W owned list is disabled
45231  *  0b1..Switch to S/W owned list is enabled
45232  */
45233 #define ENET_QOS_MTL_EST_CONTROL_SSWL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_SSWL_MASK)
45234 
45235 #define ENET_QOS_MTL_EST_CONTROL_DDBF_MASK       (0x10U)
45236 #define ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT      (4U)
45237 /*! DDBF - Do not Drop frames during Frame Size Error When set, frames are not be dropped during
45238  *    Head-of-Line blocking due to Frame Size Error (HLBF field of MTL_EST_STATUS register).
45239  *  0b1..Do not Drop frames during Frame Size Error
45240  *  0b0..Drop frames during Frame Size Error
45241  */
45242 #define ENET_QOS_MTL_EST_CONTROL_DDBF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DDBF_MASK)
45243 
45244 #define ENET_QOS_MTL_EST_CONTROL_DFBS_MASK       (0x20U)
45245 #define ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT      (5U)
45246 /*! DFBS - Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due
45247  *    to not getting scheduled (HLBS field of EST_STATUS register) after 4,8,16,32 (based on LCSE
45248  *    field of this register) GCL iterations are dropped.
45249  *  0b0..Do not Drop Frames causing Scheduling Error
45250  *  0b1..Drop Frames causing Scheduling Error
45251  */
45252 #define ENET_QOS_MTL_EST_CONTROL_DFBS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DFBS_MASK)
45253 
45254 #define ENET_QOS_MTL_EST_CONTROL_LCSE_MASK       (0xC0U)
45255 #define ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT      (6U)
45256 /*! LCSE - Loop Count to report Scheduling Error Programmable number of GCL list iterations before
45257  *    reporting an HLBS error defined in EST_STATUS register.
45258  *  0b10..16 iterations
45259  *  0b11..32 iterations
45260  *  0b00..4 iterations
45261  *  0b01..8 iterations
45262  */
45263 #define ENET_QOS_MTL_EST_CONTROL_LCSE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_LCSE_MASK)
45264 
45265 #define ENET_QOS_MTL_EST_CONTROL_TILS_MASK       (0x700U)
45266 #define ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT      (8U)
45267 /*! TILS - Time Interval Left Shift Amount This field provides the left shift amount for the
45268  *    programmed Time Interval values used in the Gate Control Lists.
45269  */
45270 #define ENET_QOS_MTL_EST_CONTROL_TILS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_TILS_MASK)
45271 
45272 #define ENET_QOS_MTL_EST_CONTROL_CTOV_MASK       (0xFFF000U)
45273 #define ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT      (12U)
45274 /*! CTOV - Current Time Offset Value Provides a 12 bit time offset value in nano second that is
45275  *    added to the current time to compensate for all the implementation pipeline delays such as the CDC
45276  *    sync delay, buffering delays, data path delays etc.
45277  */
45278 #define ENET_QOS_MTL_EST_CONTROL_CTOV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_CTOV_MASK)
45279 
45280 #define ENET_QOS_MTL_EST_CONTROL_PTOV_MASK       (0xFF000000U)
45281 #define ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT      (24U)
45282 /*! PTOV - PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds. */
45283 #define ENET_QOS_MTL_EST_CONTROL_PTOV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_PTOV_MASK)
45284 /*! @} */
45285 
45286 /*! @name MTL_EST_STATUS - Enhancements to Scheduled Transmission Status */
45287 /*! @{ */
45288 
45289 #define ENET_QOS_MTL_EST_STATUS_SWLC_MASK        (0x1U)
45290 #define ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT       (0U)
45291 /*! SWLC - Switch to S/W owned list Complete When "1" indicates the hardware has successfully
45292  *    switched to the SWOL, and the SWOL bit has been updated to that effect.
45293  *  0b1..Switch to S/W owned list Complete detected
45294  *  0b0..Switch to S/W owned list Complete not detected
45295  */
45296 #define ENET_QOS_MTL_EST_STATUS_SWLC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWLC_MASK)
45297 
45298 #define ENET_QOS_MTL_EST_STATUS_BTRE_MASK        (0x2U)
45299 #define ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT       (1U)
45300 /*! BTRE - BTR Error When "1" indicates a programming error in the BTR of SWOL where the programmed
45301  *    value is less than current time.
45302  *  0b1..BTR Error detected
45303  *  0b0..BTR Error not detected
45304  */
45305 #define ENET_QOS_MTL_EST_STATUS_BTRE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRE_MASK)
45306 
45307 #define ENET_QOS_MTL_EST_STATUS_HLBF_MASK        (0x4U)
45308 #define ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT       (2U)
45309 /*! HLBF - Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more
45310  *    Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or
45311  *    equal to the duration needed for frame size (or frame fragment size when preemption is
45312  *    enabled) transmission.
45313  *  0b1..Head-Of-Line Blocking due to Frame Size detected
45314  *  0b0..Head-Of-Line Blocking due to Frame Size not detected
45315  */
45316 #define ENET_QOS_MTL_EST_STATUS_HLBF(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBF_MASK)
45317 
45318 #define ENET_QOS_MTL_EST_STATUS_HLBS_MASK        (0x8U)
45319 #define ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT       (3U)
45320 /*! HLBS - Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration
45321  *    and get scheduled even after 4 iterations of the GCL.
45322  *  0b1..Head-Of-Line Blocking due to Scheduling detected
45323  *  0b0..Head-Of-Line Blocking due to Scheduling not detected
45324  */
45325 #define ENET_QOS_MTL_EST_STATUS_HLBS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBS_MASK)
45326 
45327 #define ENET_QOS_MTL_EST_STATUS_CGCE_MASK        (0x10U)
45328 #define ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT       (4U)
45329 /*! CGCE - Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the
45330  *    programmed Time Interval (TI) value after the optional Left Shifting is less than or equal to the
45331  *    Cycle Time (CTR).
45332  *  0b1..Constant Gate Control Error detected
45333  *  0b0..Constant Gate Control Error not detected
45334  */
45335 #define ENET_QOS_MTL_EST_STATUS_CGCE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGCE_MASK)
45336 
45337 #define ENET_QOS_MTL_EST_STATUS_SWOL_MASK        (0x80U)
45338 #define ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT       (7U)
45339 /*! SWOL - S/W owned list When '0' indicates Gate control list number "0" is owned by software and
45340  *    when "1" indicates the Gate Control list "1" is owned by the software.
45341  *  0b1..Gate control list number "1" is owned by software
45342  *  0b0..Gate control list number "0" is owned by software
45343  */
45344 #define ENET_QOS_MTL_EST_STATUS_SWOL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWOL_MASK)
45345 
45346 #define ENET_QOS_MTL_EST_STATUS_BTRL_MASK        (0xF00U)
45347 #define ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT       (8U)
45348 /*! BTRL - BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time
45349  *    =< New BTR + (N * New Cycle Time) becomes true.
45350  */
45351 #define ENET_QOS_MTL_EST_STATUS_BTRL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRL_MASK)
45352 
45353 #define ENET_QOS_MTL_EST_STATUS_CGSN_MASK        (0xF0000U)
45354 #define ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT       (16U)
45355 /*! CGSN - Current GCL Slot Number Indicates the slot number of the GCL list. */
45356 #define ENET_QOS_MTL_EST_STATUS_CGSN(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGSN_MASK)
45357 /*! @} */
45358 
45359 /*! @name MTL_EST_SCH_ERROR - EST Scheduling Error */
45360 /*! @{ */
45361 
45362 #define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK     (0x1FU)
45363 #define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT    (0U)
45364 /*! SEQN - Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced
45365  *    error/timeout described in HLBS field of status register.
45366  */
45367 #define ENET_QOS_MTL_EST_SCH_ERROR_SEQN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT)) & ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK)
45368 /*! @} */
45369 
45370 /*! @name MTL_EST_FRM_SIZE_ERROR - EST Frame Size Error */
45371 /*! @{ */
45372 
45373 #define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK (0x1FU)
45374 #define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT (0U)
45375 /*! FEQN - Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced
45376  *    error described in HLBF field of status register.
45377  */
45378 #define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK)
45379 /*! @} */
45380 
45381 /*! @name MTL_EST_FRM_SIZE_CAPTURE - EST Frame Size Capture */
45382 /*! @{ */
45383 
45384 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7FFFU)
45385 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT (0U)
45386 /*! HBFS - Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number
45387  *    indicated in HBFQ field of this register.
45388  */
45389 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK)
45390 
45391 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK (0x70000U)
45392 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT (16U)
45393 /*! HBFQ - Queue Number of HLBF Captures the binary value of the of the first Queue (number)
45394  *    experiencing HLBF error (see HLBF field of status register).
45395  */
45396 #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK)
45397 /*! @} */
45398 
45399 /*! @name MTL_EST_INTR_ENABLE - EST Interrupt Enable */
45400 /*! @{ */
45401 
45402 #define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK   (0x1U)
45403 #define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT  (0U)
45404 /*! IECC - Interrupt Enable for Switch List When set, generates interrupt when the configuration
45405  *    change is successful and the hardware has switched to the new list.
45406  *  0b0..Interrupt for Switch List is disabled
45407  *  0b1..Interrupt for Switch List is enabled
45408  */
45409 #define ENET_QOS_MTL_EST_INTR_ENABLE_IECC(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK)
45410 
45411 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK   (0x2U)
45412 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT  (1U)
45413 /*! IEBE - Interrupt Enable for BTR Error When set, generates interrupt when the BTR Error occurs and is indicated in the status.
45414  *  0b0..Interrupt for BTR Error is disabled
45415  *  0b1..Interrupt for BTR Error is enabled
45416  */
45417 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK)
45418 
45419 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK   (0x4U)
45420 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT  (2U)
45421 /*! IEHF - Interrupt Enable for HLBF When set, generates interrupt when the Head-of-Line Blocking
45422  *    due to Frame Size error occurs and is indicated in the status.
45423  *  0b0..Interrupt for HLBF is disabled
45424  *  0b1..Interrupt for HLBF is enabled
45425  */
45426 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK)
45427 
45428 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK   (0x8U)
45429 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT  (3U)
45430 /*! IEHS - Interrupt Enable for HLBS When set, generates interrupt when the Head-of-Line Blocking
45431  *    due to Scheduling issue and is indicated in the status.
45432  *  0b0..Interrupt for HLBS is disabled
45433  *  0b1..Interrupt for HLBS is enabled
45434  */
45435 #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK)
45436 
45437 #define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK   (0x10U)
45438 #define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT  (4U)
45439 /*! CGCE - Interrupt Enable for CGCE When set, generates interrupt when the Constant Gate Control
45440  *    Error occurs and is indicated in the status.
45441  *  0b0..Interrupt for CGCE is disabled
45442  *  0b1..Interrupt for CGCE is enabled
45443  */
45444 #define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK)
45445 /*! @} */
45446 
45447 /*! @name MTL_EST_GCL_CONTROL - EST GCL Control */
45448 /*! @{ */
45449 
45450 #define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK   (0x1U)
45451 #define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT  (0U)
45452 /*! SRWO - Start Read/Write Op When set indicates a Read/Write Op has started and is in progress.
45453  *  0b0..Start Read/Write Op disabled
45454  *  0b1..Start Read/Write Op enabled
45455  */
45456 #define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK)
45457 
45458 #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK   (0x2U)
45459 #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT  (1U)
45460 /*! R1W0 - Read '1', Write '0': When set to '1': Read Operation When set to '0': Write Operation.
45461  *  0b1..Read Operation
45462  *  0b0..Write Operation
45463  */
45464 #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK)
45465 
45466 #define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK   (0x4U)
45467 #define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT  (2U)
45468 /*! GCRR - Gate Control Related Registers When set to "1" indicates the R/W access is for the GCL
45469  *    related registers (BTR, CTR, TER, LLR) whose address is provided by GCRA.
45470  *  0b0..Gate Control Related Registers are disabled
45471  *  0b1..Gate Control Related Registers are enabled
45472  */
45473 #define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK)
45474 
45475 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK   (0x10U)
45476 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT  (4U)
45477 /*! DBGM - Debug Mode When set to "1" indicates R/W in debug mode where the memory bank (for GCL and
45478  *    Time related registers) is explicitly provided by DBGB value, when set to "0" SWOL bit is
45479  *    used to determine which bank to use.
45480  *  0b0..Debug Mode is disabled
45481  *  0b1..Debug Mode is enabled
45482  */
45483 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK)
45484 
45485 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK   (0x20U)
45486 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT  (5U)
45487 /*! DBGB - Debug Mode Bank Select When set to "0" indicates R/W in debug mode should be directed to
45488  *    Bank 0 (GCL0 and corresponding Time related registers).
45489  *  0b0..R/W in debug mode should be directed to Bank 0
45490  *  0b1..R/W in debug mode should be directed to Bank 1
45491  */
45492 #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK)
45493 
45494 #define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK   (0x1FF00U)
45495 #define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT  (8U)
45496 /*! ADDR - Gate Control List Address: (GCLA when GCRR is "0"). */
45497 #define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK)
45498 
45499 #define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK   (0x100000U)
45500 #define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT  (20U)
45501 /*! ERR0 - When set indicates the last write operation was aborted as software writes to GCL and GCL
45502  *    registers is prohibited when SSWL bit of MTL_EST_CONTROL Register is set.
45503  *  0b0..ERR0 is disabled
45504  *  0b1..ERR1 is enabled
45505  */
45506 #define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK)
45507 
45508 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK (0x200000U)
45509 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT (21U)
45510 /*! ESTEIEE - EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_CONTROL register,
45511  *    enables the ECC error injection feature.
45512  *  0b0..EST ECC Inject Error is disabled
45513  *  0b1..EST ECC Inject Error is enabled
45514  */
45515 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK)
45516 
45517 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK (0xC00000U)
45518 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT (22U)
45519 /*! ESTEIEC - ECC Inject Error Control for EST Memory When EIEE bit of this register is set,
45520  *    following are the errors inserted based on the value encoded in this field.
45521  *  0b00..Insert 1 bit error
45522  *  0b11..Insert 1 bit error in address field
45523  *  0b01..Insert 2 bit errors
45524  *  0b10..Insert 3 bit errors
45525  */
45526 #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK)
45527 /*! @} */
45528 
45529 /*! @name MTL_EST_GCL_DATA - EST GCL Data */
45530 /*! @{ */
45531 
45532 #define ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK       (0xFFFFFFFFU)
45533 #define ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT      (0U)
45534 /*! GCD - Gate Control Data The data corresponding to the address selected in the MTL_GCL_CONTROL register. */
45535 #define ENET_QOS_MTL_EST_GCL_DATA_GCD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT)) & ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK)
45536 /*! @} */
45537 
45538 /*! @name MTL_FPE_CTRL_STS - Frame Preemption Control and Status */
45539 /*! @{ */
45540 
45541 #define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK      (0x3U)
45542 #define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT     (0U)
45543 /*! AFSZ - Additional Fragment Size used to indicate, in units of 64 bytes, the minimum number of
45544  *    bytes over 64 bytes required in non-final fragments of preempted frames.
45545  */
45546 #define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK)
45547 
45548 #define ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK       (0x1F00U)
45549 #define ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT      (8U)
45550 /*! PEC - Preemption Classification When set indicates the corresponding Queue must be classified as
45551  *    preemptable, when '0' Queue is classified as express.
45552  */
45553 #define ENET_QOS_MTL_FPE_CTRL_STS_PEC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK)
45554 
45555 #define ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK       (0x10000000U)
45556 #define ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT      (28U)
45557 /*! HRS - Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State.
45558  *  0b1..Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State
45559  *  0b0..Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State
45560  */
45561 #define ENET_QOS_MTL_FPE_CTRL_STS_HRS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK)
45562 /*! @} */
45563 
45564 /*! @name MTL_FPE_ADVANCE - Frame Preemption Hold and Release Advance */
45565 /*! @{ */
45566 
45567 #define ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK       (0xFFFFU)
45568 #define ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT      (0U)
45569 /*! HADV - Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to
45570  *    the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of
45571  *    transmission or any preemptable frames that are queued for transmission.
45572  */
45573 #define ENET_QOS_MTL_FPE_ADVANCE_HADV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK)
45574 
45575 #define ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK       (0xFFFF0000U)
45576 #define ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT      (16U)
45577 /*! RADV - Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE
45578  *    to the MAC and the MAC being ready to resume transmission of preemptable frames, in the
45579  *    absence of there being any express frames available for transmission.
45580  */
45581 #define ENET_QOS_MTL_FPE_ADVANCE_RADV(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK)
45582 /*! @} */
45583 
45584 /*! @name MTL_RXP_CONTROL_STATUS - RXP Control Status */
45585 /*! @{ */
45586 
45587 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK (0xFFU)
45588 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT (0U)
45589 /*! NVE - Number of valid entries in the Instruction table This control indicates the number of
45590  *    valid entries in the Instruction Memory.
45591  */
45592 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK)
45593 
45594 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK (0xFF0000U)
45595 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT (16U)
45596 /*! NPE - Number of parsable entries in the Instruction table This control indicates the number of
45597  *    parsable entries in the Instruction Memory.
45598  */
45599 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK)
45600 
45601 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK (0x80000000U)
45602 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT (31U)
45603 /*! RXPI - RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State
45604  *    and waiting for a new packet for processing.
45605  *  0b1..RX Parser in Idle state
45606  *  0b0..RX Parser not in Idle state
45607  */
45608 #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK)
45609 /*! @} */
45610 
45611 /*! @name MTL_RXP_INTERRUPT_CONTROL_STATUS - RXP Interrupt Control Status */
45612 /*! @{ */
45613 
45614 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK (0x1U)
45615 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT (0U)
45616 /*! NVEOVIS - Number of Valid Entries Overflow Interrupt Status While parsing if the Instruction
45617  *    address found to be more than NVE (Number of Valid Entries in MTL_RXP_CONTROL register), then
45618  *    this bit is set to 1.
45619  *  0b1..Number of Valid Entries Overflow Interrupt Status detected
45620  *  0b0..Number of Valid Entries Overflow Interrupt Status not detected
45621  */
45622 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK)
45623 
45624 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK (0x2U)
45625 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT (1U)
45626 /*! NPEOVIS - Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the
45627  *    number of parsed entries found to be more than NPE[] (Number of Parseable Entries in
45628  *    MTL_RXP_CONTROL register),then this bit is set to 1.
45629  *  0b1..Number of Parsable Entries Overflow Interrupt Status detected
45630  *  0b0..Number of Parsable Entries Overflow Interrupt Status not detected
45631  */
45632 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK)
45633 
45634 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK (0x4U)
45635 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT (2U)
45636 /*! FOOVIS - Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's
45637  *    'Frame Offset' found to be more than EOF offset, then then this bit is set.
45638  *  0b1..Frame Offset Overflow Interrupt Status detected
45639  *  0b0..Frame Offset Overflow Interrupt Status not detected
45640  */
45641 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK)
45642 
45643 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK (0x8U)
45644 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT (3U)
45645 /*! PDRFIS - Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the
45646  *    packet by setting RF=1 in the instruction memory, then this bit is set to 1.
45647  *  0b1..Packet Dropped due to RF Interrupt Status detected
45648  *  0b0..Packet Dropped due to RF Interrupt Status not detected
45649  */
45650 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK)
45651 
45652 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK (0x10000U)
45653 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT (16U)
45654 /*! NVEOVIE - Number of Valid Entries Overflow Interrupt Enable When this bit is set, the NVEOVIS interrupt is enabled.
45655  *  0b0..Number of Valid Entries Overflow Interrupt is disabled
45656  *  0b1..Number of Valid Entries Overflow Interrupt is enabled
45657  */
45658 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK)
45659 
45660 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK (0x20000U)
45661 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT (17U)
45662 /*! NPEOVIE - Number of Parsable Entries Overflow Interrupt Enable When this bit is set, the NPEOVIS interrupt is enabled.
45663  *  0b0..Number of Parsable Entries Overflow Interrupt is disabled
45664  *  0b1..Number of Parsable Entries Overflow Interrupt is enabled
45665  */
45666 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK)
45667 
45668 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK (0x40000U)
45669 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT (18U)
45670 /*! FOOVIE - Frame Offset Overflow Interrupt Enable When this bit is set, the FOOVIS interrupt is enabled.
45671  *  0b0..Frame Offset Overflow Interrupt is disabled
45672  *  0b1..Frame Offset Overflow Interrupt is enabled
45673  */
45674 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK)
45675 
45676 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK (0x80000U)
45677 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT (19U)
45678 /*! PDRFIE - Packet Drop due to RF Interrupt Enable When this bit is set, the PDRFIS interrupt is enabled.
45679  *  0b0..Packet Drop due to RF Interrupt is disabled
45680  *  0b1..Packet Drop due to RF Interrupt is enabled
45681  */
45682 #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK)
45683 /*! @} */
45684 
45685 /*! @name MTL_RXP_DROP_CNT - RXP Drop Count */
45686 /*! @{ */
45687 
45688 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK     (0x7FFFFFFFU)
45689 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT    (0U)
45690 /*! RXPDC - Rx Parser Drop count This 31-bit counter is implemented whenever a Rx Parser Drops a packet due to RF =1. */
45691 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK)
45692 
45693 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK  (0x80000000U)
45694 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT (31U)
45695 /*! RXPDCOVF - Rx Parser Drop Counter Overflow Bit When set, this bit indicates that the
45696  *    MTL_RXP_DROP_CNT (RXPDC) Counter field crossed the maximum limit.
45697  *  0b1..Rx Parser Drop count overflow occurred
45698  *  0b0..Rx Parser Drop count overflow not occurred
45699  */
45700 #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK)
45701 /*! @} */
45702 
45703 /*! @name MTL_RXP_ERROR_CNT - RXP Error Count */
45704 /*! @{ */
45705 
45706 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK    (0x7FFFFFFFU)
45707 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT   (0U)
45708 /*! RXPEC - Rx Parser Error count This 31-bit counter is implemented whenever a Rx Parser encounters
45709  *    following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry
45710  *    address > EOF data entry address The counter is cleared when the register is read.
45711  */
45712 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK)
45713 
45714 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK (0x80000000U)
45715 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT (31U)
45716 /*! RXPECOVF - Rx Parser Error Counter Overflow Bit When set, this bit indicates that the
45717  *    MTL_RXP_ERROR_CNT (RXPEC) Counter field crossed the maximum limit.
45718  *  0b1..Rx Parser Error count overflow occurred
45719  *  0b0..Rx Parser Error count overflow not occurred
45720  */
45721 #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK)
45722 /*! @} */
45723 
45724 /*! @name MTL_RXP_INDIRECT_ACC_CONTROL_STATUS - RXP Indirect Access Control and Status */
45725 /*! @{ */
45726 
45727 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0x3FFU)
45728 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT (0U)
45729 /*! ADDR - FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table. */
45730 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK)
45731 
45732 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK (0x10000U)
45733 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT (16U)
45734 /*! WRRDN - Read Write Control When this bit is set to 1 indicates the write operation to the Rx Parser Memory.
45735  *  0b0..Read operation to the Rx Parser Memory
45736  *  0b1..Write operation to the Rx Parser Memory
45737  */
45738 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK)
45739 
45740 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK (0x80000000U)
45741 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT (31U)
45742 /*! STARTBUSY - FRP Instruction Table Access Busy When this bit is set to 1 by the software then it
45743  *    indicates to start the Read/Write operation from/to the Rx Parser Memory.
45744  *  0b1..hardware is busy (Read/Write operation from/to the Rx Parser Memory)
45745  *  0b0..hardware not busy
45746  */
45747 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK)
45748 /*! @} */
45749 
45750 /*! @name MTL_RXP_INDIRECT_ACC_DATA - RXP Indirect Access Data */
45751 /*! @{ */
45752 
45753 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xFFFFFFFFU)
45754 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT (0U)
45755 /*! DATA - FRP Instruction Table Write/Read Data Software should write this register before issuing any write command. */
45756 #define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK)
45757 /*! @} */
45758 
45759 /*! @name MTL_TXQX_OP_MODE - Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode */
45760 /*! @{ */
45761 
45762 #define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK       (0x1U)
45763 #define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT      (0U)
45764 /*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values.
45765  *  0b0..Flush Transmit Queue is disabled
45766  *  0b1..Flush Transmit Queue is enabled
45767  */
45768 #define ENET_QOS_MTL_TXQX_OP_MODE_FTQ(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK)
45769 
45770 #define ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK       (0x2U)
45771 #define ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT      (1U)
45772 /*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue.
45773  *  0b0..Transmit Store and Forward is disabled
45774  *  0b1..Transmit Store and Forward is enabled
45775  */
45776 #define ENET_QOS_MTL_TXQX_OP_MODE_TSF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK)
45777 
45778 #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK     (0xCU)
45779 #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT    (2U)
45780 /*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0.
45781  *  0b00..Not enabled
45782  *  0b10..Enabled
45783  *  0b01..Enable in AV mode (Reserved in non-AV)
45784  *  0b11..Reserved
45785  */
45786 #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK)
45787 
45788 #define ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK       (0x70U)
45789 #define ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT      (4U)
45790 /*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue.
45791  *  0b011..128
45792  *  0b100..192
45793  *  0b101..256
45794  *  0b000..32
45795  *  0b110..384
45796  *  0b111..512
45797  *  0b001..64
45798  *  0b010..96
45799  */
45800 #define ENET_QOS_MTL_TXQX_OP_MODE_TTC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK)
45801 
45802 #define ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK       (0x1F0000U)
45803 #define ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT      (16U)
45804 /*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. */
45805 #define ENET_QOS_MTL_TXQX_OP_MODE_TQS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK)
45806 /*! @} */
45807 
45808 /* The count of ENET_QOS_MTL_TXQX_OP_MODE */
45809 #define ENET_QOS_MTL_TXQX_OP_MODE_COUNT          (5U)
45810 
45811 /*! @name MTL_TXQX_UNDRFLW - Queue 0 Underflow Counter..Queue 4 Underflow Counter */
45812 /*! @{ */
45813 
45814 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK  (0x7FFU)
45815 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
45816 /*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the
45817  *    controller because of Tx Queue Underflow.
45818  */
45819 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
45820 
45821 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK  (0x800U)
45822 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
45823 /*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue
45824  *    Underflow Packet Counter field overflows, that is, it has crossed the maximum count.
45825  *  0b1..Overflow detected for Underflow Packet Counter
45826  *  0b0..Overflow not detected for Underflow Packet Counter
45827  */
45828 #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
45829 /*! @} */
45830 
45831 /* The count of ENET_QOS_MTL_TXQX_UNDRFLW */
45832 #define ENET_QOS_MTL_TXQX_UNDRFLW_COUNT          (5U)
45833 
45834 /*! @name MTL_TXQX_DBG - Queue 0 Transmit Debug..Queue 4 Transmit Debug */
45835 /*! @{ */
45836 
45837 #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK     (0x1U)
45838 #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT    (0U)
45839 /*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it
45840  *    indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because
45841  *    of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue
45842  *    when PFC is enabled - Reception of 802.
45843  *  0b1..Transmit Queue in Pause status is detected
45844  *  0b0..Transmit Queue in Pause status is not detected
45845  */
45846 #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK)
45847 
45848 #define ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK        (0x6U)
45849 #define ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT       (1U)
45850 /*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:
45851  *  0b11..Flushing the Tx queue because of the Packet Abort request from the MAC
45852  *  0b00..Idle state
45853  *  0b01..Read state (transferring data to the MAC transmitter)
45854  *  0b10..Waiting for pending Tx Status from the MAC transmitter
45855  */
45856 #define ENET_QOS_MTL_TXQX_DBG_TRCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK)
45857 
45858 #define ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK        (0x8U)
45859 #define ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT       (3U)
45860 /*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx
45861  *    Queue Write Controller is active, and it is transferring the data to the Tx Queue.
45862  *  0b1..MTL Tx Queue Write Controller status is detected
45863  *  0b0..MTL Tx Queue Write Controller status is not detected
45864  */
45865 #define ENET_QOS_MTL_TXQX_DBG_TWCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK)
45866 
45867 #define ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK        (0x10U)
45868 #define ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT       (4U)
45869 /*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue
45870  *    is not empty and some data is left for transmission.
45871  *  0b1..MTL Tx Queue Not Empty status is detected
45872  *  0b0..MTL Tx Queue Not Empty status is not detected
45873  */
45874 #define ENET_QOS_MTL_TXQX_DBG_TXQSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK)
45875 
45876 #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK     (0x20U)
45877 #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT    (5U)
45878 /*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full.
45879  *  0b1..MTL Tx Status FIFO Full status is detected
45880  *  0b0..MTL Tx Status FIFO Full status is not detected
45881  */
45882 #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK)
45883 
45884 #define ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK          (0x70000U)
45885 #define ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT         (16U)
45886 /*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. */
45887 #define ENET_QOS_MTL_TXQX_DBG_PTXQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK)
45888 
45889 #define ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK       (0x700000U)
45890 #define ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT      (20U)
45891 /*! STXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current
45892  *    number of status in the Tx Status FIFO of this queue.
45893  */
45894 #define ENET_QOS_MTL_TXQX_DBG_STXSTSF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK)
45895 /*! @} */
45896 
45897 /* The count of ENET_QOS_MTL_TXQX_DBG */
45898 #define ENET_QOS_MTL_TXQX_DBG_COUNT              (5U)
45899 
45900 /*! @name MTL_TXQX_ETS_CTRL - Queue 1 ETS Control..Queue 4 ETS Control */
45901 /*! @{ */
45902 
45903 #define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK    (0x4U)
45904 #define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT   (2U)
45905 /*! AVALG - AV Algorithm When Queue 1 is programmed for AV, this field configures the scheduling
45906  *    algorithm for this queue: This bit when set, indicates credit based shaper algorithm (CBS) is
45907  *    selected for Queue 1 traffic.
45908  *  0b0..CBS Algorithm is disabled
45909  *  0b1..CBS Algorithm is enabled
45910  */
45911 #define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK)
45912 
45913 #define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK       (0x8U)
45914 #define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT      (3U)
45915 /*! CC - Credit Control When this bit is set, the accumulated credit parameter in the credit-based
45916  *    shaper algorithm logic is not reset to zero when there is positive credit and no packet to
45917  *    transmit in Channel 1.
45918  *  0b0..Credit Control is disabled
45919  *  0b1..Credit Control is enabled
45920  */
45921 #define ENET_QOS_MTL_TXQX_ETS_CTRL_CC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK)
45922 
45923 #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK      (0x70U)
45924 #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT     (4U)
45925 /*! SLC - Slot Count If the credit-based shaper algorithm is enabled, the software can program the
45926  *    number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the
45927  *    average transmitted bits per slot, provided in the MTL_TXQ[N]_ETS_STATUS register, need to be
45928  *    computed for Queue.
45929  *  0b100..16 slots
45930  *  0b000..1 slot
45931  *  0b001..2 slots
45932  *  0b010..4 slots
45933  *  0b011..8 slots
45934  *  0b101..Reserved
45935  */
45936 #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK)
45937 /*! @} */
45938 
45939 /* The count of ENET_QOS_MTL_TXQX_ETS_CTRL */
45940 #define ENET_QOS_MTL_TXQX_ETS_CTRL_COUNT         (5U)
45941 
45942 /*! @name MTL_TXQX_ETS_STAT - Queue 0 ETS Status..Queue 4 ETS Status */
45943 /*! @{ */
45944 
45945 #define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK      (0xFFFFFFU)
45946 #define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT     (0U)
45947 /*! ABS - Average Bits per Slot This field contains the average transmitted bits per slot. */
45948 #define ENET_QOS_MTL_TXQX_ETS_STAT_ABS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK)
45949 /*! @} */
45950 
45951 /* The count of ENET_QOS_MTL_TXQX_ETS_STAT */
45952 #define ENET_QOS_MTL_TXQX_ETS_STAT_COUNT         (5U)
45953 
45954 /*! @name MTL_TXQX_QNTM_WGHT - Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights */
45955 /*! @{ */
45956 
45957 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK   (0x1FFFFFU)
45958 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT  (0U)
45959 /*! ISCQW - Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0
45960  *    traffic, this field contains the quantum value in bytes to be added to credit during every queue
45961  *    scanning cycle.
45962  */
45963 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
45964 /*! @} */
45965 
45966 /* The count of ENET_QOS_MTL_TXQX_QNTM_WGHT */
45967 #define ENET_QOS_MTL_TXQX_QNTM_WGHT_COUNT        (5U)
45968 
45969 /*! @name MTL_TXQX_SNDSLP_CRDT - Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit */
45970 /*! @{ */
45971 
45972 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK   (0x3FFFU)
45973 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT  (0U)
45974 /*! SSC - sendSlopeCredit Value When AV operation is enabled, this field contains the
45975  *    sendSlopeCredit value required for credit-based shaper algorithm for Queue 1.
45976  */
45977 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
45978 /*! @} */
45979 
45980 /* The count of ENET_QOS_MTL_TXQX_SNDSLP_CRDT */
45981 #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_COUNT      (5U)
45982 
45983 /*! @name MTL_TXQX_HI_CRDT - Queue 1 hiCredit..Queue 4 hiCredit */
45984 /*! @{ */
45985 
45986 #define ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK        (0x1FFFFFFFU)
45987 #define ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT       (0U)
45988 /*! HC - hiCredit Value When the AV feature is enabled, this field contains the hiCredit value
45989  *    required for the credit-based shaper algorithm.
45990  */
45991 #define ENET_QOS_MTL_TXQX_HI_CRDT_HC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK)
45992 /*! @} */
45993 
45994 /* The count of ENET_QOS_MTL_TXQX_HI_CRDT */
45995 #define ENET_QOS_MTL_TXQX_HI_CRDT_COUNT          (5U)
45996 
45997 /*! @name MTL_TXQX_LO_CRDT - Queue 1 loCredit..Queue 4 loCredit */
45998 /*! @{ */
45999 
46000 #define ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK        (0x1FFFFFFFU)
46001 #define ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT       (0U)
46002 /*! LC - loCredit Value When AV operation is enabled, this field contains the loCredit value
46003  *    required for the credit-based shaper algorithm.
46004  */
46005 #define ENET_QOS_MTL_TXQX_LO_CRDT_LC(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK)
46006 /*! @} */
46007 
46008 /* The count of ENET_QOS_MTL_TXQX_LO_CRDT */
46009 #define ENET_QOS_MTL_TXQX_LO_CRDT_COUNT          (5U)
46010 
46011 /*! @name MTL_TXQX_INTCTRL_STAT - Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status */
46012 /*! @{ */
46013 
46014 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
46015 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
46016 /*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue
46017  *    had an underflow while transmitting the packet.
46018  *  0b1..Transmit Queue Underflow Interrupt Status detected
46019  *  0b0..Transmit Queue Underflow Interrupt Status not detected
46020  */
46021 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
46022 
46023 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
46024 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
46025 /*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value.
46026  *  0b1..Average Bits Per Slot Interrupt Status detected
46027  *  0b0..Average Bits Per Slot Interrupt Status not detected
46028  */
46029 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
46030 
46031 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
46032 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
46033 /*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled.
46034  *  0b0..Transmit Queue Underflow Interrupt Status is disabled
46035  *  0b1..Transmit Queue Underflow Interrupt Status is enabled
46036  */
46037 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
46038 
46039 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
46040 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
46041 /*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the
46042  *    sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated.
46043  *  0b0..Average Bits Per Slot Interrupt is disabled
46044  *  0b1..Average Bits Per Slot Interrupt is enabled
46045  */
46046 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
46047 
46048 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
46049 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
46050 /*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had
46051  *    an overflow while receiving the packet.
46052  *  0b1..Receive Queue Overflow Interrupt Status detected
46053  *  0b0..Receive Queue Overflow Interrupt Status not detected
46054  */
46055 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
46056 
46057 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
46058 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
46059 /*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled.
46060  *  0b0..Receive Queue Overflow Interrupt is disabled
46061  *  0b1..Receive Queue Overflow Interrupt is enabled
46062  */
46063 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
46064 /*! @} */
46065 
46066 /* The count of ENET_QOS_MTL_TXQX_INTCTRL_STAT */
46067 #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_COUNT     (5U)
46068 
46069 /*! @name MTL_RXQX_OP_MODE - Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode */
46070 /*! @{ */
46071 
46072 #define ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK       (0x3U)
46073 #define ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT      (0U)
46074 /*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue
46075  *    (in bytes): The received packet is transferred to the application or DMA when the packet size
46076  *    within the MTL Rx queue is larger than the threshold.
46077  *  0b11..128
46078  *  0b01..32
46079  *  0b00..64
46080  *  0b10..96
46081  */
46082 #define ENET_QOS_MTL_RXQX_OP_MODE_RTC(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK)
46083 
46084 #define ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK       (0x8U)
46085 #define ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT      (3U)
46086 /*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized
46087  *    good packets (packets with no error and length less than 64 bytes), including pad-bytes and
46088  *    CRC.
46089  *  0b0..Forward Undersized Good Packets is disabled
46090  *  0b1..Forward Undersized Good Packets is enabled
46091  */
46092 #define ENET_QOS_MTL_RXQX_OP_MODE_FUP(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK)
46093 
46094 #define ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK       (0x10U)
46095 #define ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT      (4U)
46096 /*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status
46097  *    (CRC error, GMII_ER, watchdog timeout, or overflow).
46098  *  0b0..Forward Error Packets is disabled
46099  *  0b1..Forward Error Packets is enabled
46100  */
46101 #define ENET_QOS_MTL_RXQX_OP_MODE_FEP(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK)
46102 
46103 #define ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK       (0x20U)
46104 #define ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT      (5U)
46105 /*! RSF - Receive Queue Store and Forward When this bit is set, the DWC_ether_qos reads a packet
46106  *    from the Rx queue only after the complete packet has been written to it, ignoring the RTC field
46107  *    of this register.
46108  *  0b0..Receive Queue Store and Forward is disabled
46109  *  0b1..Receive Queue Store and Forward is enabled
46110  */
46111 #define ENET_QOS_MTL_RXQX_OP_MODE_RSF(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK)
46112 
46113 #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
46114 #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
46115 /*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC
46116  *    does not drop the packets which only have the errors detected by the Receive Checksum Offload
46117  *    engine.
46118  *  0b1..Dropping of TCP/IP Checksum Error Packets is disabled
46119  *  0b0..Dropping of TCP/IP Checksum Error Packets is enabled
46120  */
46121 #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
46122 
46123 #define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK      (0x80U)
46124 #define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT     (7U)
46125 /*! EHFC - Enable Hardware Flow Control When this bit is set, the flow control signal operation,
46126  *    based on the fill-level of Rx queue, is enabled.
46127  *  0b0..Hardware Flow Control is disabled
46128  *  0b1..Hardware Flow Control is enabled
46129  */
46130 #define ENET_QOS_MTL_RXQX_OP_MODE_EHFC(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK)
46131 
46132 #define ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK       (0xF00U)
46133 #define ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT      (8U)
46134 /*! RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control
46135  *    the threshold (fill-level of Rx queue) at which the flow control is activated: For more
46136  *    information on encoding for this field, see RFD.
46137  */
46138 #define ENET_QOS_MTL_RXQX_OP_MODE_RFA(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK)
46139 
46140 #define ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK       (0x3C000U)
46141 #define ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT      (14U)
46142 /*! RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits
46143  *    control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after
46144  *    activation: - 0: Full minus 1 KB, that is, FULL 1 KB - 1: Full minus 1.
46145  */
46146 #define ENET_QOS_MTL_RXQX_OP_MODE_RFD(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK)
46147 
46148 #define ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK       (0x1F00000U)
46149 #define ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT      (20U)
46150 /*! RQS - Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. */
46151 #define ENET_QOS_MTL_RXQX_OP_MODE_RQS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK)
46152 /*! @} */
46153 
46154 /* The count of ENET_QOS_MTL_RXQX_OP_MODE */
46155 #define ENET_QOS_MTL_RXQX_OP_MODE_COUNT          (5U)
46156 
46157 /*! @name MTL_RXQX_MISSPKT_OVRFLW_CNT - Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter */
46158 /*! @{ */
46159 
46160 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
46161 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
46162 /*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the
46163  *    DWC_ether_qos because of Receive queue overflow.
46164  */
46165 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
46166 
46167 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
46168 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
46169 /*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue
46170  *    Overflow Packet Counter field crossed the maximum limit.
46171  *  0b1..Overflow Counter overflow detected
46172  *  0b0..Overflow Counter overflow not detected
46173  */
46174 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
46175 
46176 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK (0x7FF0000U)
46177 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT (16U)
46178 /*! MISPKTCNT - Missed Packet Counter This field indicates the number of packets missed by the
46179  *    DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue.
46180  */
46181 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK)
46182 
46183 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK (0x8000000U)
46184 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT (27U)
46185 /*! MISCNTOVF - Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue
46186  *    Missed Packet Counter crossed the maximum limit.
46187  *  0b1..Missed Packet Counter overflow detected
46188  *  0b0..Missed Packet Counter overflow not detected
46189  */
46190 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK)
46191 /*! @} */
46192 
46193 /* The count of ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT */
46194 #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (5U)
46195 
46196 /*! @name MTL_RXQX_DBG - Queue 0 Receive Debug..Queue 4 Receive Debug */
46197 /*! @{ */
46198 
46199 #define ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK        (0x1U)
46200 #define ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT       (0U)
46201 /*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL
46202  *    Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.
46203  *  0b1..MTL Rx Queue Write Controller Active Status detected
46204  *  0b0..MTL Rx Queue Write Controller Active Status not detected
46205  */
46206 #define ENET_QOS_MTL_RXQX_DBG_RWCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK)
46207 
46208 #define ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK        (0x6U)
46209 #define ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT       (1U)
46210 /*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:
46211  *  0b11..Flushing the packet data and status
46212  *  0b00..Idle state
46213  *  0b01..Reading packet data
46214  *  0b10..Reading packet status (or timestamp)
46215  */
46216 #define ENET_QOS_MTL_RXQX_DBG_RRCSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK)
46217 
46218 #define ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK        (0x30U)
46219 #define ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT       (4U)
46220 /*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:
46221  *  0b10..Rx Queue fill-level above flow-control activate threshold
46222  *  0b01..Rx Queue fill-level below flow-control deactivate threshold
46223  *  0b00..Rx Queue empty
46224  *  0b11..Rx Queue full
46225  */
46226 #define ENET_QOS_MTL_RXQX_DBG_RXQSTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK)
46227 
46228 #define ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK          (0x3FFF0000U)
46229 #define ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT         (16U)
46230 /*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. */
46231 #define ENET_QOS_MTL_RXQX_DBG_PRXQ(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK)
46232 /*! @} */
46233 
46234 /* The count of ENET_QOS_MTL_RXQX_DBG */
46235 #define ENET_QOS_MTL_RXQX_DBG_COUNT              (5U)
46236 
46237 /*! @name MTL_RXQX_CTRL - Queue 0 Receive Control..Queue 4 Receive Control */
46238 /*! @{ */
46239 
46240 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK     (0x7U)
46241 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT    (0U)
46242 /*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. */
46243 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
46244 
46245 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
46246 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
46247 /*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the DWC_ether_qos drives
46248  *    the packet data to the ARI interface such that the entire packet data of currently-selected
46249  *    queue is transmitted before switching to other queue.
46250  *  0b0..Receive Queue Packet Arbitration is disabled
46251  *  0b1..Receive Queue Packet Arbitration is enabled
46252  */
46253 #define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
46254 /*! @} */
46255 
46256 /* The count of ENET_QOS_MTL_RXQX_CTRL */
46257 #define ENET_QOS_MTL_RXQX_CTRL_COUNT             (5U)
46258 
46259 /*! @name DMA_MODE - DMA Bus Mode */
46260 /*! @{ */
46261 
46262 #define ENET_QOS_DMA_MODE_SWR_MASK               (0x1U)
46263 #define ENET_QOS_DMA_MODE_SWR_SHIFT              (0U)
46264 /*! SWR - Software Reset When this bit is set, the MAC and the DMA controller reset the logic and
46265  *    all internal registers of the DMA, MTL, and MAC.
46266  *  0b0..Software Reset is disabled
46267  *  0b1..Software Reset is enabled
46268  */
46269 #define ENET_QOS_DMA_MODE_SWR(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_SWR_SHIFT)) & ENET_QOS_DMA_MODE_SWR_MASK)
46270 
46271 #define ENET_QOS_DMA_MODE_DSPW_MASK              (0x100U)
46272 #define ENET_QOS_DMA_MODE_DSPW_SHIFT             (8U)
46273 /*! DSPW - Descriptor Posted Write When this bit is set to 0, the descriptor writes are always non-posted.
46274  *  0b0..Descriptor Posted Write is disabled
46275  *  0b1..Descriptor Posted Write is enabled
46276  */
46277 #define ENET_QOS_DMA_MODE_DSPW(x)                (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_DSPW_SHIFT)) & ENET_QOS_DMA_MODE_DSPW_MASK)
46278 
46279 #define ENET_QOS_DMA_MODE_INTM_MASK              (0x30000U)
46280 #define ENET_QOS_DMA_MODE_INTM_SHIFT             (16U)
46281 /*! INTM - Interrupt Mode This field defines the interrupt mode of DWC_ether_qos.
46282  *  0b00..See above description
46283  *  0b01..See above description
46284  *  0b10..See above description
46285  *  0b11..Reserved
46286  */
46287 #define ENET_QOS_DMA_MODE_INTM(x)                (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_INTM_SHIFT)) & ENET_QOS_DMA_MODE_INTM_MASK)
46288 /*! @} */
46289 
46290 /*! @name DMA_SYSBUS_MODE - DMA System Bus Mode */
46291 /*! @{ */
46292 
46293 #define ENET_QOS_DMA_SYSBUS_MODE_FB_MASK         (0x1U)
46294 #define ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT        (0U)
46295 /*! FB - Fixed Burst Length When this bit is set to 1, the EQOS-AXI master initiates burst transfers
46296  *    of specified lengths as given below.
46297  *  0b0..Fixed Burst Length is disabled
46298  *  0b1..Fixed Burst Length is enabled
46299  */
46300 #define ENET_QOS_DMA_SYSBUS_MODE_FB(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_FB_MASK)
46301 
46302 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK      (0x2U)
46303 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT     (1U)
46304 /*! BLEN4 - AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
46305  *    master can select a burst length of 4 on the AXI interface.
46306  *  0b0..No effect
46307  *  0b1..AXI Burst Length 4
46308  */
46309 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN4(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK)
46310 
46311 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK      (0x4U)
46312 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT     (2U)
46313 /*! BLEN8 - AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
46314  *    master can select a burst length of 8 on the AXI interface.
46315  *  0b0..No effect
46316  *  0b1..AXI Burst Length 8
46317  */
46318 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN8(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK)
46319 
46320 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK     (0x8U)
46321 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT    (3U)
46322 /*! BLEN16 - AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
46323  *    master can select a burst length of 16 on the AXI interface.
46324  *  0b0..No effect
46325  *  0b1..AXI Burst Length 16
46326  */
46327 #define ENET_QOS_DMA_SYSBUS_MODE_BLEN16(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK)
46328 
46329 #define ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK       (0x400U)
46330 #define ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT      (10U)
46331 /*! AALE - Automatic AXI LPI enable When set to 1, enables the AXI master to enter into LPI state
46332  *    when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in
46333  *    the LPIEI field of DMA_AXI_LPI_ENTRY_INTERVAL register.
46334  *  0b0..Automatic AXI LPI is disabled
46335  *  0b1..Automatic AXI LPI is enabled
46336  */
46337 #define ENET_QOS_DMA_SYSBUS_MODE_AALE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK)
46338 
46339 #define ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK        (0x1000U)
46340 #define ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT       (12U)
46341 /*! AAL - Address-Aligned Beats When this bit is set to 1, the EQOS-AXI or EQOS-AHB master performs
46342  *    address-aligned burst transfers on Read and Write channels.
46343  *  0b0..Address-Aligned Beats is disabled
46344  *  0b1..Address-Aligned Beats is enabled
46345  */
46346 #define ENET_QOS_DMA_SYSBUS_MODE_AAL(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK)
46347 
46348 #define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK    (0x2000U)
46349 #define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT   (13U)
46350 /*! ONEKBBE - 1 KB Boundary Crossing Enable for the EQOS-AXI Master When set, the burst transfers
46351  *    performed by the EQOS-AXI master do not cross 1 KB boundary.
46352  *  0b0..1 KB Boundary Crossing for the EQOS-AXI Master Beats is disabled
46353  *  0b1..1 KB Boundary Crossing for the EQOS-AXI Master Beats is enabled
46354  */
46355 #define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK)
46356 
46357 #define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0xF0000U)
46358 #define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT (16U)
46359 /*! RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface. */
46360 #define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK)
46361 
46362 #define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0xF000000U)
46363 #define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT (24U)
46364 /*! WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit This value limits the maximum
46365  *    outstanding request on the AXI write interface.
46366  */
46367 #define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK)
46368 
46369 #define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK (0x40000000U)
46370 #define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT (30U)
46371 /*! LPI_XIT_PKT - Unlock on Magic Packet or Remote Wake-Up Packet When set to 1, this bit enables
46372  *    the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet
46373  *    is received.
46374  *  0b0..Unlock on Magic Packet or Remote Wake-Up Packet is disabled
46375  *  0b1..Unlock on Magic Packet or Remote Wake-Up Packet is enabled
46376  */
46377 #define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK)
46378 
46379 #define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK     (0x80000000U)
46380 #define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT    (31U)
46381 /*! EN_LPI - Enable Low Power Interface (LPI) When set to 1, this bit enables the LPI mode supported
46382  *    by the EQOS-AXI configuration and accepts the LPI request from the AXI System Clock
46383  *    controller.
46384  *  0b0..Low Power Interface (LPI) is disabled
46385  *  0b1..Low Power Interface (LPI) is enabled
46386  */
46387 #define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK)
46388 /*! @} */
46389 
46390 /*! @name DMA_INTERRUPT_STATUS - DMA Interrupt Status */
46391 /*! @{ */
46392 
46393 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U)
46394 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U)
46395 /*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0.
46396  *  0b1..DMA Channel 0 Interrupt Status detected
46397  *  0b0..DMA Channel 0 Interrupt Status not detected
46398  */
46399 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK)
46400 
46401 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK (0x2U)
46402 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT (1U)
46403 /*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1.
46404  *  0b1..DMA Channel 1 Interrupt Status detected
46405  *  0b0..DMA Channel 1 Interrupt Status not detected
46406  */
46407 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK)
46408 
46409 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U)
46410 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT (2U)
46411 /*! DC2IS - DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2.
46412  *  0b1..DMA Channel 2 Interrupt Status detected
46413  *  0b0..DMA Channel 2 Interrupt Status not detected
46414  */
46415 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK)
46416 
46417 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK (0x8U)
46418 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT (3U)
46419 /*! DC3IS - DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3.
46420  *  0b1..DMA Channel 3 Interrupt Status detected
46421  *  0b0..DMA Channel 3 Interrupt Status not detected
46422  */
46423 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK)
46424 
46425 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK (0x10U)
46426 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT (4U)
46427 /*! DC4IS - DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4.
46428  *  0b1..DMA Channel 4 Interrupt Status detected
46429  *  0b0..DMA Channel 4 Interrupt Status not detected
46430  */
46431 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK)
46432 
46433 #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x10000U)
46434 #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U)
46435 /*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL.
46436  *  0b1..MTL Interrupt Status detected
46437  *  0b0..MTL Interrupt Status not detected
46438  */
46439 #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK)
46440 
46441 #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK (0x20000U)
46442 #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U)
46443 /*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC.
46444  *  0b1..MAC Interrupt Status detected
46445  *  0b0..MAC Interrupt Status not detected
46446  */
46447 #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK)
46448 /*! @} */
46449 
46450 /*! @name DMA_DEBUG_STATUS0 - DMA Debug Status 0 */
46451 /*! @{ */
46452 
46453 #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK  (0x1U)
46454 #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U)
46455 /*! AXWHSTS - AXI Master Write Channel When high, this bit indicates that the write channel of the
46456  *    AXI master is active, and it is transferring data.
46457  *  0b1..AXI Master Write Channel or AHB Master Status detected
46458  *  0b0..AXI Master Write Channel or AHB Master Status not detected
46459  */
46460 #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK)
46461 
46462 #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK  (0x2U)
46463 #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT (1U)
46464 /*! AXRHSTS - AXI Master Read Channel Status When high, this bit indicates that the read channel of
46465  *    the AXI master is active, and it is transferring the data.
46466  *  0b1..AXI Master Read Channel Status detected
46467  *  0b0..AXI Master Read Channel Status not detected
46468  */
46469 #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK)
46470 
46471 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK     (0xF00U)
46472 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT    (8U)
46473 /*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0.
46474  *  0b0010..Reserved for future use
46475  *  0b0101..Running (Closing the Rx Descriptor)
46476  *  0b0001..Running (Fetching Rx Transfer Descriptor)
46477  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
46478  *  0b0011..Running (Waiting for Rx packet)
46479  *  0b0000..Stopped (Reset or Stop Receive Command issued)
46480  *  0b0100..Suspended (Rx Descriptor Unavailable)
46481  *  0b0110..Timestamp write state
46482  */
46483 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK)
46484 
46485 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK     (0xF000U)
46486 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT    (12U)
46487 /*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0.
46488  *  0b0101..Reserved for future use
46489  *  0b0111..Running (Closing Tx Descriptor)
46490  *  0b0001..Running (Fetching Tx Transfer Descriptor)
46491  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
46492  *  0b0010..Running (Waiting for status)
46493  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
46494  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
46495  *  0b0100..Timestamp write state
46496  */
46497 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK)
46498 
46499 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK     (0xF0000U)
46500 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT    (16U)
46501 /*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1.
46502  *  0b0010..Reserved for future use
46503  *  0b0101..Running (Closing the Rx Descriptor)
46504  *  0b0001..Running (Fetching Rx Transfer Descriptor)
46505  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
46506  *  0b0011..Running (Waiting for Rx packet)
46507  *  0b0000..Stopped (Reset or Stop Receive Command issued)
46508  *  0b0100..Suspended (Rx Descriptor Unavailable)
46509  *  0b0110..Timestamp write state
46510  */
46511 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK)
46512 
46513 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK     (0xF00000U)
46514 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT    (20U)
46515 /*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1.
46516  *  0b0101..Reserved for future use
46517  *  0b0111..Running (Closing Tx Descriptor)
46518  *  0b0001..Running (Fetching Tx Transfer Descriptor)
46519  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
46520  *  0b0010..Running (Waiting for status)
46521  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
46522  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
46523  *  0b0100..Timestamp write state
46524  */
46525 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK)
46526 
46527 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK     (0xF000000U)
46528 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT    (24U)
46529 /*! RPS2 - DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2.
46530  *  0b0010..Reserved for future use
46531  *  0b0101..Running (Closing the Rx Descriptor)
46532  *  0b0001..Running (Fetching Rx Transfer Descriptor)
46533  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
46534  *  0b0011..Running (Waiting for Rx packet)
46535  *  0b0000..Stopped (Reset or Stop Receive Command issued)
46536  *  0b0100..Suspended (Rx Descriptor Unavailable)
46537  *  0b0110..Timestamp write state
46538  */
46539 #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK)
46540 
46541 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK     (0xF0000000U)
46542 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT    (28U)
46543 /*! TPS2 - DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2.
46544  *  0b0101..Reserved for future use
46545  *  0b0111..Running (Closing Tx Descriptor)
46546  *  0b0001..Running (Fetching Tx Transfer Descriptor)
46547  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
46548  *  0b0010..Running (Waiting for status)
46549  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
46550  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
46551  *  0b0100..Timestamp write state
46552  */
46553 #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK)
46554 /*! @} */
46555 
46556 /*! @name DMA_DEBUG_STATUS1 - DMA Debug Status 1 */
46557 /*! @{ */
46558 
46559 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK     (0xFU)
46560 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT    (0U)
46561 /*! RPS3 - DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3.
46562  *  0b0010..Reserved for future use
46563  *  0b0101..Running (Closing the Rx Descriptor)
46564  *  0b0001..Running (Fetching Rx Transfer Descriptor)
46565  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
46566  *  0b0011..Running (Waiting for Rx packet)
46567  *  0b0000..Stopped (Reset or Stop Receive Command issued)
46568  *  0b0100..Suspended (Rx Descriptor Unavailable)
46569  *  0b0110..Timestamp write state
46570  */
46571 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK)
46572 
46573 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK     (0xF0U)
46574 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT    (4U)
46575 /*! TPS3 - DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3.
46576  *  0b0101..Reserved for future use
46577  *  0b0111..Running (Closing Tx Descriptor)
46578  *  0b0001..Running (Fetching Tx Transfer Descriptor)
46579  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
46580  *  0b0010..Running (Waiting for status)
46581  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
46582  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
46583  *  0b0100..Timestamp write state
46584  */
46585 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK)
46586 
46587 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK     (0xF00U)
46588 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT    (8U)
46589 /*! RPS4 - DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4.
46590  *  0b0010..Reserved for future use
46591  *  0b0101..Running (Closing the Rx Descriptor)
46592  *  0b0001..Running (Fetching Rx Transfer Descriptor)
46593  *  0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
46594  *  0b0011..Running (Waiting for Rx packet)
46595  *  0b0000..Stopped (Reset or Stop Receive Command issued)
46596  *  0b0100..Suspended (Rx Descriptor Unavailable)
46597  *  0b0110..Timestamp write state
46598  */
46599 #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK)
46600 
46601 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK     (0xF000U)
46602 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT    (12U)
46603 /*! TPS4 - DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4.
46604  *  0b0101..Reserved for future use
46605  *  0b0111..Running (Closing Tx Descriptor)
46606  *  0b0001..Running (Fetching Tx Transfer Descriptor)
46607  *  0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
46608  *  0b0010..Running (Waiting for status)
46609  *  0b0000..Stopped (Reset or Stop Transmit Command issued)
46610  *  0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
46611  *  0b0100..Timestamp write state
46612  */
46613 #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4(x)       (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK)
46614 /*! @} */
46615 
46616 /*! @name DMA_AXI_LPI_ENTRY_INTERVAL - AXI LPI Entry Interval Control */
46617 /*! @{ */
46618 
46619 #define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK (0xFU)
46620 #define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT (0U)
46621 /*! LPIEI - LPI Entry Interval Contains the number of system clock cycles, multiplied by 64, to wait
46622  *    for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64
46623  *    clock cycles
46624  */
46625 #define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT)) & ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK)
46626 /*! @} */
46627 
46628 /*! @name DMA_TBS_CTRL - TBS Control */
46629 /*! @{ */
46630 
46631 #define ENET_QOS_DMA_TBS_CTRL_FTOV_MASK          (0x1U)
46632 #define ENET_QOS_DMA_TBS_CTRL_FTOV_SHIFT         (0U)
46633 /*! FTOV - Fetch Time Offset Valid When set indicates the FTOS field is valid.
46634  *  0b0..Fetch Time Offset is invalid
46635  *  0b1..Fetch Time Offset is valid
46636  */
46637 #define ENET_QOS_DMA_TBS_CTRL_FTOV(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FTOV_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FTOV_MASK)
46638 
46639 #define ENET_QOS_DMA_TBS_CTRL_FGOS_MASK          (0x70U)
46640 #define ENET_QOS_DMA_TBS_CTRL_FGOS_SHIFT         (4U)
46641 /*! FGOS - Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN. */
46642 #define ENET_QOS_DMA_TBS_CTRL_FGOS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FGOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FGOS_MASK)
46643 
46644 #define ENET_QOS_DMA_TBS_CTRL_FTOS_MASK          (0xFFFFFF00U)
46645 #define ENET_QOS_DMA_TBS_CTRL_FTOS_SHIFT         (8U)
46646 /*! FTOS - Fetch Time Offset The value in units of 256 nanoseconds, that has to be deducted from the
46647  *    Launch time to compute the Fetch Time.
46648  */
46649 #define ENET_QOS_DMA_TBS_CTRL_FTOS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FTOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FTOS_MASK)
46650 /*! @} */
46651 
46652 /*! @name DMA_CHX_CTRL - DMA Channel 0 Control..DMA Channel 4 Control */
46653 /*! @{ */
46654 
46655 #define ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK         (0x10000U)
46656 #define ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT        (16U)
46657 /*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in
46658  *    DMA_CH4_TX_CONTROL and Bits[21:16] in DMA_CH4_RX_CONTROL is multiplied by eight times.
46659  *  0b0..8xPBL mode is disabled
46660  *  0b1..8xPBL mode is enabled
46661  */
46662 #define ENET_QOS_DMA_CHX_CTRL_PBLx8(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK)
46663 
46664 #define ENET_QOS_DMA_CHX_CTRL_DSL_MASK           (0x1C0000U)
46665 #define ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT          (18U)
46666 /*! DSL - Descriptor Skip Length This bit specifies the Word, Dword, or Lword number (depending on
46667  *    the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors.
46668  */
46669 #define ENET_QOS_DMA_CHX_CTRL_DSL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_DSL_MASK)
46670 /*! @} */
46671 
46672 /* The count of ENET_QOS_DMA_CHX_CTRL */
46673 #define ENET_QOS_DMA_CHX_CTRL_COUNT              (5U)
46674 
46675 /*! @name DMA_CHX_TX_CTRL - DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control */
46676 /*! @{ */
46677 
46678 #define ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK         (0x1U)
46679 #define ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT        (0U)
46680 /*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state.
46681  *  0b1..Start Transmission Command
46682  *  0b0..Stop Transmission Command
46683  */
46684 #define ENET_QOS_DMA_CHX_TX_CTRL_ST(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK)
46685 
46686 #define ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK        (0x10U)
46687 #define ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT       (4U)
46688 /*! OSF - Operate on Second Packet When this bit is set, it instructs the DMA to process the second
46689  *    packet of the Transmit data even before the status for the first packet is obtained.
46690  *  0b0..Operate on Second Packet disabled
46691  *  0b1..Operate on Second Packet enabled
46692  */
46693 #define ENET_QOS_DMA_CHX_TX_CTRL_OSF(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK)
46694 
46695 #define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK       (0x8000U)
46696 #define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT      (15U)
46697 /*! IPBL - Ignore PBL Requirement When this bit is set, the DMA does not check for PBL number of
46698  *    locations in the MTL before initiating a transfer.
46699  *  0b0..Ignore PBL Requirement is disabled
46700  *  0b1..Ignore PBL Requirement is enabled
46701  */
46702 #define ENET_QOS_DMA_CHX_TX_CTRL_IPBL(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK)
46703 
46704 #define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK      (0x3F0000U)
46705 #define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT     (16U)
46706 /*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be
46707  *    transferred in one DMA block data transfer.
46708  */
46709 #define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK)
46710 
46711 #define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK       (0x10000000U)
46712 #define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT      (28U)
46713 /*! EDSE - Enhanced Descriptor Enable When this bit is set, the corresponding channel uses Enhanced
46714  *    Descriptors that are 32 Bytes for both Normal and Context Descriptors.
46715  *  0b0..Enhanced Descriptor is disabled
46716  *  0b1..Enhanced Descriptor is enabled
46717  */
46718 #define ENET_QOS_DMA_CHX_TX_CTRL_EDSE(x)         (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK)
46719 /*! @} */
46720 
46721 /* The count of ENET_QOS_DMA_CHX_TX_CTRL */
46722 #define ENET_QOS_DMA_CHX_TX_CTRL_COUNT           (5U)
46723 
46724 /*! @name DMA_CHX_RX_CTRL - DMA Channel 0 Receive Control..DMA Channel 4 Receive Control */
46725 /*! @{ */
46726 
46727 #define ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK         (0x1U)
46728 #define ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT        (0U)
46729 /*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from
46730  *    the Receive list and processes the incoming packets.
46731  *  0b1..Start Receive
46732  *  0b0..Stop Receive
46733  */
46734 #define ENET_QOS_DMA_CHX_RX_CTRL_SR(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK)
46735 
46736 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK   (0xEU)
46737 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT  (1U)
46738 /*! RBSZ_x_0 - Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. */
46739 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0(x)     (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK)
46740 
46741 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK  (0x7FF0U)
46742 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT (4U)
46743 /*! RBSZ_13_y - Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. */
46744 #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y(x)    (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK)
46745 
46746 #define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK      (0x3F0000U)
46747 #define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT     (16U)
46748 /*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be
46749  *    transferred in one DMA block data transfer.
46750  */
46751 #define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL(x)        (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK)
46752 
46753 #define ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK        (0x80000000U)
46754 #define ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT       (31U)
46755 /*! RPF - Rx Packet Flush.
46756  *  0b0..Rx Packet Flush is disabled
46757  *  0b1..Rx Packet Flush is enabled
46758  */
46759 #define ENET_QOS_DMA_CHX_RX_CTRL_RPF(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK)
46760 /*! @} */
46761 
46762 /* The count of ENET_QOS_DMA_CHX_RX_CTRL */
46763 #define ENET_QOS_DMA_CHX_RX_CTRL_COUNT           (5U)
46764 
46765 /*! @name DMA_CHX_TXDESC_LIST_ADDR - Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address */
46766 /*! @{ */
46767 
46768 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFF8U)
46769 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT (3U)
46770 /*! TDESLA - Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. */
46771 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK)
46772 /*! @} */
46773 
46774 /* The count of ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR */
46775 #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_COUNT  (5U)
46776 
46777 /*! @name DMA_CHX_RXDESC_LIST_ADDR - Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address */
46778 /*! @{ */
46779 
46780 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFF8U)
46781 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT (3U)
46782 /*! RDESLA - Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. */
46783 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK)
46784 /*! @} */
46785 
46786 /* The count of ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR */
46787 #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_COUNT  (5U)
46788 
46789 /*! @name DMA_CHX_TXDESC_TAIL_PTR - Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer */
46790 /*! @{ */
46791 
46792 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFF8U)
46793 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (3U)
46794 /*! TDTP - Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. */
46795 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
46796 /*! @} */
46797 
46798 /* The count of ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR */
46799 #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_COUNT   (5U)
46800 
46801 /*! @name DMA_CHX_RXDESC_TAIL_PTR - Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer */
46802 /*! @{ */
46803 
46804 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFF8U)
46805 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (3U)
46806 /*! RDTP - Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. */
46807 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
46808 /*! @} */
46809 
46810 /* The count of ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR */
46811 #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_COUNT   (5U)
46812 
46813 /*! @name DMA_CHX_TXDESC_RING_LENGTH - Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length */
46814 /*! @{ */
46815 
46816 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
46817 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
46818 /*! TDRL - Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. */
46819 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
46820 /*! @} */
46821 
46822 /* The count of ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH */
46823 #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_COUNT (5U)
46824 
46825 /*! @name DMA_CHX_RXDESC_RING_LENGTH - Channel 0 Rx Descriptor Ring Length..Channel 4 Rx Descriptor Ring Length */
46826 /*! @{ */
46827 
46828 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
46829 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
46830 /*! RDRL - Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. */
46831 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
46832 /*! @} */
46833 
46834 /* The count of ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH */
46835 #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_COUNT (5U)
46836 
46837 /*! @name DMA_CHX_INT_EN - Channel 0 Interrupt Enable..Channel 4 Interrupt Enable */
46838 /*! @{ */
46839 
46840 #define ENET_QOS_DMA_CHX_INT_EN_TIE_MASK         (0x1U)
46841 #define ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT        (0U)
46842 /*! TIE - Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled.
46843  *  0b0..Transmit Interrupt is disabled
46844  *  0b1..Transmit Interrupt is enabled
46845  */
46846 #define ENET_QOS_DMA_CHX_INT_EN_TIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TIE_MASK)
46847 
46848 #define ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK        (0x2U)
46849 #define ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT       (1U)
46850 /*! TXSE - Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled.
46851  *  0b0..Transmit Stopped is disabled
46852  *  0b1..Transmit Stopped is enabled
46853  */
46854 #define ENET_QOS_DMA_CHX_INT_EN_TXSE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK)
46855 
46856 #define ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK        (0x4U)
46857 #define ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT       (2U)
46858 /*! TBUE - Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the
46859  *    Transmit Buffer Unavailable interrupt is enabled.
46860  *  0b0..Transmit Buffer Unavailable is disabled
46861  *  0b1..Transmit Buffer Unavailable is enabled
46862  */
46863 #define ENET_QOS_DMA_CHX_INT_EN_TBUE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK)
46864 
46865 #define ENET_QOS_DMA_CHX_INT_EN_RIE_MASK         (0x40U)
46866 #define ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT        (6U)
46867 /*! RIE - Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled.
46868  *  0b0..Receive Interrupt is disabled
46869  *  0b1..Receive Interrupt is enabled
46870  */
46871 #define ENET_QOS_DMA_CHX_INT_EN_RIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RIE_MASK)
46872 
46873 #define ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK        (0x80U)
46874 #define ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT       (7U)
46875 /*! RBUE - Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the
46876  *    Receive Buffer Unavailable interrupt is enabled.
46877  *  0b0..Receive Buffer Unavailable is disabled
46878  *  0b1..Receive Buffer Unavailable is enabled
46879  */
46880 #define ENET_QOS_DMA_CHX_INT_EN_RBUE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK)
46881 
46882 #define ENET_QOS_DMA_CHX_INT_EN_RSE_MASK         (0x100U)
46883 #define ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT        (8U)
46884 /*! RSE - Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled.
46885  *  0b0..Receive Stopped is disabled
46886  *  0b1..Receive Stopped is enabled
46887  */
46888 #define ENET_QOS_DMA_CHX_INT_EN_RSE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RSE_MASK)
46889 
46890 #define ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK        (0x200U)
46891 #define ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT       (9U)
46892 /*! RWTE - Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive
46893  *    Watchdog Timeout interrupt is enabled.
46894  *  0b0..Receive Watchdog Timeout is disabled
46895  *  0b1..Receive Watchdog Timeout is enabled
46896  */
46897 #define ENET_QOS_DMA_CHX_INT_EN_RWTE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK)
46898 
46899 #define ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK        (0x400U)
46900 #define ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT       (10U)
46901 /*! ETIE - Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled.
46902  *  0b0..Early Transmit Interrupt is disabled
46903  *  0b1..Early Transmit Interrupt is enabled
46904  */
46905 #define ENET_QOS_DMA_CHX_INT_EN_ETIE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK)
46906 
46907 #define ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK        (0x800U)
46908 #define ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT       (11U)
46909 /*! ERIE - Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled.
46910  *  0b0..Early Receive Interrupt is disabled
46911  *  0b1..Early Receive Interrupt is enabled
46912  */
46913 #define ENET_QOS_DMA_CHX_INT_EN_ERIE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK)
46914 
46915 #define ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK        (0x1000U)
46916 #define ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT       (12U)
46917 /*! FBEE - Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled.
46918  *  0b0..Fatal Bus Error is disabled
46919  *  0b1..Fatal Bus Error is enabled
46920  */
46921 #define ENET_QOS_DMA_CHX_INT_EN_FBEE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK)
46922 
46923 #define ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK        (0x2000U)
46924 #define ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT       (13U)
46925 /*! CDEE - Context Descriptor Error Enable When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled.
46926  *  0b0..Context Descriptor Error is disabled
46927  *  0b1..Context Descriptor Error is enabled
46928  */
46929 #define ENET_QOS_DMA_CHX_INT_EN_CDEE(x)          (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK)
46930 
46931 #define ENET_QOS_DMA_CHX_INT_EN_AIE_MASK         (0x4000U)
46932 #define ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT        (14U)
46933 /*! AIE - Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled.
46934  *  0b0..Abnormal Interrupt Summary is disabled
46935  *  0b1..Abnormal Interrupt Summary is enabled
46936  */
46937 #define ENET_QOS_DMA_CHX_INT_EN_AIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_AIE_MASK)
46938 
46939 #define ENET_QOS_DMA_CHX_INT_EN_NIE_MASK         (0x8000U)
46940 #define ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT        (15U)
46941 /*! NIE - Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled.
46942  *  0b0..Normal Interrupt Summary is disabled
46943  *  0b1..Normal Interrupt Summary is enabled
46944  */
46945 #define ENET_QOS_DMA_CHX_INT_EN_NIE(x)           (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_NIE_MASK)
46946 /*! @} */
46947 
46948 /* The count of ENET_QOS_DMA_CHX_INT_EN */
46949 #define ENET_QOS_DMA_CHX_INT_EN_COUNT            (5U)
46950 
46951 /*! @name DMA_CHX_RX_INT_WDTIMER - Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer */
46952 /*! @{ */
46953 
46954 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK (0xFFU)
46955 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT (0U)
46956 /*! RWT - Receive Interrupt Watchdog Timer Count This field indicates the number of system clock
46957  *    cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set.
46958  */
46959 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK)
46960 
46961 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK (0x30000U)
46962 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT (16U)
46963 /*! RWTU - Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system
46964  *    clock cycles corresponding to one unit in RWT field.
46965  */
46966 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK)
46967 /*! @} */
46968 
46969 /* The count of ENET_QOS_DMA_CHX_RX_INT_WDTIMER */
46970 #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_COUNT    (5U)
46971 
46972 /*! @name DMA_CHX_SLOT_FUNC_CTRL_STAT - Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status */
46973 /*! @{ */
46974 
46975 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
46976 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
46977 /*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers
46978  *    programmed in the Tx descriptor with the current reference given in the RSN field.
46979  *  0b0..Slot Comparison is disabled
46980  *  0b1..Slot Comparison is enabled
46981  */
46982 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
46983 
46984 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
46985 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
46986 /*! ASC - Advance Slot Check When set, this bit enables the DMA to fetch the data from the buffer
46987  *    when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot
46988  *    number given in the RSN field or - ahead of the reference slot number by up to two slots This
46989  *    bit is applicable only when the ESC bit is set.
46990  *  0b0..Advance Slot Check is disabled
46991  *  0b1..Advance Slot Check is enabled
46992  */
46993 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
46994 
46995 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK (0xFFF0U)
46996 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT (4U)
46997 /*! SIV - Slot Interval Value This field controls the period of the slot interval in which the TxDMA
46998  *    fetches the scheduled packets.
46999  */
47000 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK)
47001 
47002 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
47003 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
47004 /*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA. */
47005 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
47006 /*! @} */
47007 
47008 /* The count of ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT */
47009 #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (5U)
47010 
47011 /*! @name DMA_CHX_CUR_HST_TXDESC - Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor */
47012 /*! @{ */
47013 
47014 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU)
47015 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT (0U)
47016 /*! CURTDESAPTR - Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. */
47017 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK)
47018 /*! @} */
47019 
47020 /* The count of ENET_QOS_DMA_CHX_CUR_HST_TXDESC */
47021 #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_COUNT    (5U)
47022 
47023 /*! @name DMA_CHX_CUR_HST_RXDESC - Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor */
47024 /*! @{ */
47025 
47026 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU)
47027 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT (0U)
47028 /*! CURRDESAPTR - Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. */
47029 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK)
47030 /*! @} */
47031 
47032 /* The count of ENET_QOS_DMA_CHX_CUR_HST_RXDESC */
47033 #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_COUNT    (5U)
47034 
47035 /*! @name DMA_CHX_CUR_HST_TXBUF - Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address */
47036 /*! @{ */
47037 
47038 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK (0xFFFFFFFFU)
47039 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT (0U)
47040 /*! CURTBUFAPTR - Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. */
47041 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK)
47042 /*! @} */
47043 
47044 /* The count of ENET_QOS_DMA_CHX_CUR_HST_TXBUF */
47045 #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_COUNT     (5U)
47046 
47047 /*! @name DMA_CHX_CUR_HST_RXBUF - Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address */
47048 /*! @{ */
47049 
47050 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK (0xFFFFFFFFU)
47051 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT (0U)
47052 /*! CURRBUFAPTR - Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. */
47053 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK)
47054 /*! @} */
47055 
47056 /* The count of ENET_QOS_DMA_CHX_CUR_HST_RXBUF */
47057 #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_COUNT     (5U)
47058 
47059 /*! @name DMA_CHX_STAT - DMA Channel 0 Status..DMA Channel 4 Status */
47060 /*! @{ */
47061 
47062 #define ENET_QOS_DMA_CHX_STAT_TI_MASK            (0x1U)
47063 #define ENET_QOS_DMA_CHX_STAT_TI_SHIFT           (0U)
47064 /*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete.
47065  *  0b1..Transmit Interrupt status detected
47066  *  0b0..Transmit Interrupt status not detected
47067  */
47068 #define ENET_QOS_DMA_CHX_STAT_TI(x)              (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TI_MASK)
47069 
47070 #define ENET_QOS_DMA_CHX_STAT_TPS_MASK           (0x2U)
47071 #define ENET_QOS_DMA_CHX_STAT_TPS_SHIFT          (1U)
47072 /*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped.
47073  *  0b1..Transmit Process Stopped status detected
47074  *  0b0..Transmit Process Stopped status not detected
47075  */
47076 #define ENET_QOS_DMA_CHX_STAT_TPS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TPS_MASK)
47077 
47078 #define ENET_QOS_DMA_CHX_STAT_TBU_MASK           (0x4U)
47079 #define ENET_QOS_DMA_CHX_STAT_TBU_SHIFT          (2U)
47080 /*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next
47081  *    descriptor in the Transmit list, and the DMA cannot acquire it.
47082  *  0b1..Transmit Buffer Unavailable status detected
47083  *  0b0..Transmit Buffer Unavailable status not detected
47084  */
47085 #define ENET_QOS_DMA_CHX_STAT_TBU(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TBU_MASK)
47086 
47087 #define ENET_QOS_DMA_CHX_STAT_RI_MASK            (0x40U)
47088 #define ENET_QOS_DMA_CHX_STAT_RI_SHIFT           (6U)
47089 /*! RI - Receive Interrupt This bit indicates that the packet reception is complete.
47090  *  0b1..Receive Interrupt status detected
47091  *  0b0..Receive Interrupt status not detected
47092  */
47093 #define ENET_QOS_DMA_CHX_STAT_RI(x)              (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RI_MASK)
47094 
47095 #define ENET_QOS_DMA_CHX_STAT_RBU_MASK           (0x80U)
47096 #define ENET_QOS_DMA_CHX_STAT_RBU_SHIFT          (7U)
47097 /*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next
47098  *    descriptor in the Receive list, and the DMA cannot acquire it.
47099  *  0b1..Receive Buffer Unavailable status detected
47100  *  0b0..Receive Buffer Unavailable status not detected
47101  */
47102 #define ENET_QOS_DMA_CHX_STAT_RBU(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RBU_MASK)
47103 
47104 #define ENET_QOS_DMA_CHX_STAT_RPS_MASK           (0x100U)
47105 #define ENET_QOS_DMA_CHX_STAT_RPS_SHIFT          (8U)
47106 /*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state.
47107  *  0b1..Receive Process Stopped status detected
47108  *  0b0..Receive Process Stopped status not detected
47109  */
47110 #define ENET_QOS_DMA_CHX_STAT_RPS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RPS_MASK)
47111 
47112 #define ENET_QOS_DMA_CHX_STAT_RWT_MASK           (0x200U)
47113 #define ENET_QOS_DMA_CHX_STAT_RWT_SHIFT          (9U)
47114 /*! RWT - Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048
47115  *    bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.
47116  *  0b1..Receive Watchdog Timeout status detected
47117  *  0b0..Receive Watchdog Timeout status not detected
47118  */
47119 #define ENET_QOS_DMA_CHX_STAT_RWT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RWT_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RWT_MASK)
47120 
47121 #define ENET_QOS_DMA_CHX_STAT_ETI_MASK           (0x400U)
47122 #define ENET_QOS_DMA_CHX_STAT_ETI_SHIFT          (10U)
47123 /*! ETI - Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the
47124  *    transfer of packet data to the MTL TXFIFO memory.
47125  *  0b1..Early Transmit Interrupt status detected
47126  *  0b0..Early Transmit Interrupt status not detected
47127  */
47128 #define ENET_QOS_DMA_CHX_STAT_ETI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ETI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ETI_MASK)
47129 
47130 #define ENET_QOS_DMA_CHX_STAT_ERI_MASK           (0x800U)
47131 #define ENET_QOS_DMA_CHX_STAT_ERI_SHIFT          (11U)
47132 /*! ERI - Early Receive Interrupt This bit when set indicates that the RxDMA has completed the
47133  *    transfer of packet data to the memory.
47134  *  0b1..Early Receive Interrupt status detected
47135  *  0b0..Early Receive Interrupt status not detected
47136  */
47137 #define ENET_QOS_DMA_CHX_STAT_ERI(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ERI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ERI_MASK)
47138 
47139 #define ENET_QOS_DMA_CHX_STAT_FBE_MASK           (0x1000U)
47140 #define ENET_QOS_DMA_CHX_STAT_FBE_SHIFT          (12U)
47141 /*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field).
47142  *  0b1..Fatal Bus Error status detected
47143  *  0b0..Fatal Bus Error status not detected
47144  */
47145 #define ENET_QOS_DMA_CHX_STAT_FBE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_FBE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_FBE_MASK)
47146 
47147 #define ENET_QOS_DMA_CHX_STAT_CDE_MASK           (0x2000U)
47148 #define ENET_QOS_DMA_CHX_STAT_CDE_SHIFT          (13U)
47149 /*! CDE - Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a
47150  *    descriptor error, which indicates invalid context in the middle of packet flow ( intermediate
47151  *    descriptor) or all one's descriptor in Tx case and on Rx side it indicates DMA has read a descriptor
47152  *    with either of the buffer address as ones which is considered to be invalid.
47153  *  0b1..Context Descriptor Error status detected
47154  *  0b0..Context Descriptor Error status not detected
47155  */
47156 #define ENET_QOS_DMA_CHX_STAT_CDE(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_CDE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_CDE_MASK)
47157 
47158 #define ENET_QOS_DMA_CHX_STAT_AIS_MASK           (0x4000U)
47159 #define ENET_QOS_DMA_CHX_STAT_AIS_SHIFT          (14U)
47160 /*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the
47161  *    following when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE
47162  *    register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive
47163  *    Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context
47164  *    Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit.
47165  *  0b1..Abnormal Interrupt Summary status detected
47166  *  0b0..Abnormal Interrupt Summary status not detected
47167  */
47168 #define ENET_QOS_DMA_CHX_STAT_AIS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_AIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_AIS_MASK)
47169 
47170 #define ENET_QOS_DMA_CHX_STAT_NIS_MASK           (0x8000U)
47171 #define ENET_QOS_DMA_CHX_STAT_NIS_SHIFT          (15U)
47172 /*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the
47173  *    following bits when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE
47174  *    register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive
47175  *    Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt
47176  *    enable is set in DMA_CH3_INTERRUPT_ENABLE register) affect the Normal Interrupt Summary bit.
47177  *  0b1..Normal Interrupt Summary status detected
47178  *  0b0..Normal Interrupt Summary status not detected
47179  */
47180 #define ENET_QOS_DMA_CHX_STAT_NIS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_NIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_NIS_MASK)
47181 
47182 #define ENET_QOS_DMA_CHX_STAT_TEB_MASK           (0x70000U)
47183 #define ENET_QOS_DMA_CHX_STAT_TEB_SHIFT          (16U)
47184 /*! TEB - Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. */
47185 #define ENET_QOS_DMA_CHX_STAT_TEB(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TEB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TEB_MASK)
47186 
47187 #define ENET_QOS_DMA_CHX_STAT_REB_MASK           (0x380000U)
47188 #define ENET_QOS_DMA_CHX_STAT_REB_SHIFT          (19U)
47189 /*! REB - Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. */
47190 #define ENET_QOS_DMA_CHX_STAT_REB(x)             (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_REB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_REB_MASK)
47191 /*! @} */
47192 
47193 /* The count of ENET_QOS_DMA_CHX_STAT */
47194 #define ENET_QOS_DMA_CHX_STAT_COUNT              (5U)
47195 
47196 /*! @name DMA_CHX_MISS_FRAME_CNT - Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter */
47197 /*! @{ */
47198 
47199 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU)
47200 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U)
47201 /*! MFC - Dropped Packet Counters This counter indicates the number of packet counters that are
47202  *    dropped by the DMA either because of bus error or because of programming RPF field in
47203  *    DMA_CH2_RX_CONTROL register.
47204  */
47205 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC(x)   (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK)
47206 
47207 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U)
47208 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U)
47209 /*! MFCO - Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further.
47210  *  0b1..Miss Frame Counter overflow occurred
47211  *  0b0..Miss Frame Counter overflow not occurred
47212  */
47213 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO(x)  (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK)
47214 /*! @} */
47215 
47216 /* The count of ENET_QOS_DMA_CHX_MISS_FRAME_CNT */
47217 #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_COUNT    (5U)
47218 
47219 /*! @name DMA_CHX_RXP_ACCEPT_CNT - Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter */
47220 /*! @{ */
47221 
47222 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFFU)
47223 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT (0U)
47224 /*! RXPAC - Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. */
47225 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK)
47226 
47227 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK (0x80000000U)
47228 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT (31U)
47229 /*! RXPACOF - Rx Parser Accept Counter Overflow Bit When set, this bit indicates that the RXPAC
47230  *    Counter field crossed the maximum limit.
47231  *  0b1..Rx Parser Accept Counter overflow occurred
47232  *  0b0..Rx Parser Accept Counter overflow not occurred
47233  */
47234 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK)
47235 /*! @} */
47236 
47237 /* The count of ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT */
47238 #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_COUNT    (5U)
47239 
47240 /*! @name DMA_CHX_RX_ERI_CNT - Channel 0 Receive ERI Counter..Channel 4 Receive ERI Counter */
47241 /*! @{ */
47242 
47243 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_MASK    (0xFFFU)
47244 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT   (0U)
47245 /*! ECNT - ERI Counter When ERIC bit of DMA_CH4_RX_CONTROL register is set, this counter increments
47246  *    for burst transfer completed by the Rx DMA from the start of packet transfer.
47247  */
47248 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT(x)      (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT)) & ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_MASK)
47249 /*! @} */
47250 
47251 /* The count of ENET_QOS_DMA_CHX_RX_ERI_CNT */
47252 #define ENET_QOS_DMA_CHX_RX_ERI_CNT_COUNT        (5U)
47253 
47254 
47255 /*!
47256  * @}
47257  */ /* end of group ENET_QOS_Register_Masks */
47258 
47259 
47260 /* ENET_QOS - Peripheral instance base addresses */
47261 /** Peripheral ENET_QOS base address */
47262 #define ENET_QOS_BASE                            (0x4043C000u)
47263 /** Peripheral ENET_QOS base pointer */
47264 #define ENET_QOS                                 ((ENET_QOS_Type *)ENET_QOS_BASE)
47265 /** Array initializer of ENET_QOS peripheral base addresses */
47266 #define ENET_QOS_BASE_ADDRS                      { ENET_QOS_BASE }
47267 /** Array initializer of ENET_QOS peripheral base pointers */
47268 #define ENET_QOS_BASE_PTRS                       { ENET_QOS }
47269 /** Interrupt vectors for the ENET_QOS peripheral type */
47270 #define ENET_QOS_IRQS                            { ENET_QOS_IRQn }
47271 #define ENET_QOS_PMT_IRQS                        { ENET_QOS_PMT_IRQn }
47272 
47273 /*!
47274  * @}
47275  */ /* end of group ENET_QOS_Peripheral_Access_Layer */
47276 
47277 
47278 /* ----------------------------------------------------------------------------
47279    -- ETHERNET_PLL Peripheral Access Layer
47280    ---------------------------------------------------------------------------- */
47281 
47282 /*!
47283  * @addtogroup ETHERNET_PLL_Peripheral_Access_Layer ETHERNET_PLL Peripheral Access Layer
47284  * @{
47285  */
47286 
47287 /** ETHERNET_PLL - Register Layout Typedef */
47288 typedef struct {
47289   struct {                                         /* offset: 0x0 */
47290     __IO uint32_t RW;                                /**< Fractional PLL Control Register, offset: 0x0 */
47291     __IO uint32_t SET;                               /**< Fractional PLL Control Register, offset: 0x4 */
47292     __IO uint32_t CLR;                               /**< Fractional PLL Control Register, offset: 0x8 */
47293     __IO uint32_t TOG;                               /**< Fractional PLL Control Register, offset: 0xC */
47294   } CTRL0;
47295   struct {                                         /* offset: 0x10 */
47296     __IO uint32_t RW;                                /**< Fractional PLL Spread Spectrum Control Register, offset: 0x10 */
47297     __IO uint32_t SET;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x14 */
47298     __IO uint32_t CLR;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x18 */
47299     __IO uint32_t TOG;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x1C */
47300   } SPREAD_SPECTRUM;
47301   struct {                                         /* offset: 0x20 */
47302     __IO uint32_t RW;                                /**< Fractional PLL Numerator Control Register, offset: 0x20 */
47303     __IO uint32_t SET;                               /**< Fractional PLL Numerator Control Register, offset: 0x24 */
47304     __IO uint32_t CLR;                               /**< Fractional PLL Numerator Control Register, offset: 0x28 */
47305     __IO uint32_t TOG;                               /**< Fractional PLL Numerator Control Register, offset: 0x2C */
47306   } NUMERATOR;
47307   struct {                                         /* offset: 0x30 */
47308     __IO uint32_t RW;                                /**< Fractional PLL Denominator Control Register, offset: 0x30 */
47309     __IO uint32_t SET;                               /**< Fractional PLL Denominator Control Register, offset: 0x34 */
47310     __IO uint32_t CLR;                               /**< Fractional PLL Denominator Control Register, offset: 0x38 */
47311     __IO uint32_t TOG;                               /**< Fractional PLL Denominator Control Register, offset: 0x3C */
47312   } DENOMINATOR;
47313 } ETHERNET_PLL_Type;
47314 
47315 /* ----------------------------------------------------------------------------
47316    -- ETHERNET_PLL Register Masks
47317    ---------------------------------------------------------------------------- */
47318 
47319 /*!
47320  * @addtogroup ETHERNET_PLL_Register_Masks ETHERNET_PLL Register Masks
47321  * @{
47322  */
47323 
47324 /*! @name CTRL0 - Fractional PLL Control Register */
47325 /*! @{ */
47326 
47327 #define ETHERNET_PLL_CTRL0_DIV_SELECT_MASK       (0x7FU)
47328 #define ETHERNET_PLL_CTRL0_DIV_SELECT_SHIFT      (0U)
47329 /*! DIV_SELECT - DIV_SELECT */
47330 #define ETHERNET_PLL_CTRL0_DIV_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DIV_SELECT_SHIFT)) & ETHERNET_PLL_CTRL0_DIV_SELECT_MASK)
47331 
47332 #define ETHERNET_PLL_CTRL0_ENABLE_ALT_MASK       (0x100U)
47333 #define ETHERNET_PLL_CTRL0_ENABLE_ALT_SHIFT      (8U)
47334 /*! ENABLE_ALT - ENABLE_ALT
47335  *  0b0..Disable the alternate clock output
47336  *  0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed
47337  */
47338 #define ETHERNET_PLL_CTRL0_ENABLE_ALT(x)         (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_ENABLE_ALT_SHIFT)) & ETHERNET_PLL_CTRL0_ENABLE_ALT_MASK)
47339 
47340 #define ETHERNET_PLL_CTRL0_HOLD_RING_OFF_MASK    (0x2000U)
47341 #define ETHERNET_PLL_CTRL0_HOLD_RING_OFF_SHIFT   (13U)
47342 /*! HOLD_RING_OFF - PLL Start up initialization
47343  *  0b0..Normal operation
47344  *  0b1..Initialize PLL start up
47345  */
47346 #define ETHERNET_PLL_CTRL0_HOLD_RING_OFF(x)      (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & ETHERNET_PLL_CTRL0_HOLD_RING_OFF_MASK)
47347 
47348 #define ETHERNET_PLL_CTRL0_POWERUP_MASK          (0x4000U)
47349 #define ETHERNET_PLL_CTRL0_POWERUP_SHIFT         (14U)
47350 /*! POWERUP - POWERUP
47351  *  0b1..Power Up the PLL
47352  *  0b0..Power down the PLL
47353  */
47354 #define ETHERNET_PLL_CTRL0_POWERUP(x)            (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_POWERUP_SHIFT)) & ETHERNET_PLL_CTRL0_POWERUP_MASK)
47355 
47356 #define ETHERNET_PLL_CTRL0_ENABLE_MASK           (0x8000U)
47357 #define ETHERNET_PLL_CTRL0_ENABLE_SHIFT          (15U)
47358 /*! ENABLE - ENABLE
47359  *  0b1..Enable the clock output
47360  *  0b0..Disable the clock output
47361  */
47362 #define ETHERNET_PLL_CTRL0_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_ENABLE_SHIFT)) & ETHERNET_PLL_CTRL0_ENABLE_MASK)
47363 
47364 #define ETHERNET_PLL_CTRL0_BYPASS_MASK           (0x10000U)
47365 #define ETHERNET_PLL_CTRL0_BYPASS_SHIFT          (16U)
47366 /*! BYPASS - BYPASS
47367  *  0b1..Bypass the PLL
47368  *  0b0..No Bypass
47369  */
47370 #define ETHERNET_PLL_CTRL0_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BYPASS_SHIFT)) & ETHERNET_PLL_CTRL0_BYPASS_MASK)
47371 
47372 #define ETHERNET_PLL_CTRL0_DITHER_EN_MASK        (0x20000U)
47373 #define ETHERNET_PLL_CTRL0_DITHER_EN_SHIFT       (17U)
47374 /*! DITHER_EN - DITHER_EN
47375  *  0b0..Disable Dither
47376  *  0b1..Enable Dither
47377  */
47378 #define ETHERNET_PLL_CTRL0_DITHER_EN(x)          (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DITHER_EN_SHIFT)) & ETHERNET_PLL_CTRL0_DITHER_EN_MASK)
47379 
47380 #define ETHERNET_PLL_CTRL0_BIAS_TRIM_MASK        (0x380000U)
47381 #define ETHERNET_PLL_CTRL0_BIAS_TRIM_SHIFT       (19U)
47382 /*! BIAS_TRIM - BIAS_TRIM */
47383 #define ETHERNET_PLL_CTRL0_BIAS_TRIM(x)          (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BIAS_TRIM_SHIFT)) & ETHERNET_PLL_CTRL0_BIAS_TRIM_MASK)
47384 
47385 #define ETHERNET_PLL_CTRL0_PLL_REG_EN_MASK       (0x400000U)
47386 #define ETHERNET_PLL_CTRL0_PLL_REG_EN_SHIFT      (22U)
47387 /*! PLL_REG_EN - PLL_REG_EN */
47388 #define ETHERNET_PLL_CTRL0_PLL_REG_EN(x)         (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_PLL_REG_EN_SHIFT)) & ETHERNET_PLL_CTRL0_PLL_REG_EN_MASK)
47389 
47390 #define ETHERNET_PLL_CTRL0_POST_DIV_SEL_MASK     (0xE000000U)
47391 #define ETHERNET_PLL_CTRL0_POST_DIV_SEL_SHIFT    (25U)
47392 /*! POST_DIV_SEL - Post Divide Select
47393  *  0b000..Divide by 1
47394  *  0b001..Divide by 2
47395  *  0b010..Divide by 4
47396  *  0b011..Divide by 8
47397  *  0b100..Divide by 16
47398  *  0b101..Divide by 32
47399  */
47400 #define ETHERNET_PLL_CTRL0_POST_DIV_SEL(x)       (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & ETHERNET_PLL_CTRL0_POST_DIV_SEL_MASK)
47401 
47402 #define ETHERNET_PLL_CTRL0_BIAS_SELECT_MASK      (0x20000000U)
47403 #define ETHERNET_PLL_CTRL0_BIAS_SELECT_SHIFT     (29U)
47404 /*! BIAS_SELECT - BIAS_SELECT
47405  *  0b0..Used in SoCs with a bias current of 10uA
47406  *  0b1..Used in SoCs with a bias current of 2uA
47407  */
47408 #define ETHERNET_PLL_CTRL0_BIAS_SELECT(x)        (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BIAS_SELECT_SHIFT)) & ETHERNET_PLL_CTRL0_BIAS_SELECT_MASK)
47409 /*! @} */
47410 
47411 /*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */
47412 /*! @{ */
47413 
47414 #define ETHERNET_PLL_SPREAD_SPECTRUM_STEP_MASK   (0x7FFFU)
47415 #define ETHERNET_PLL_SPREAD_SPECTRUM_STEP_SHIFT  (0U)
47416 /*! STEP - Step */
47417 #define ETHERNET_PLL_SPREAD_SPECTRUM_STEP(x)     (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_STEP_MASK)
47418 
47419 #define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U)
47420 #define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U)
47421 /*! ENABLE - Enable */
47422 #define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_MASK)
47423 
47424 #define ETHERNET_PLL_SPREAD_SPECTRUM_STOP_MASK   (0xFFFF0000U)
47425 #define ETHERNET_PLL_SPREAD_SPECTRUM_STOP_SHIFT  (16U)
47426 /*! STOP - Stop */
47427 #define ETHERNET_PLL_SPREAD_SPECTRUM_STOP(x)     (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_STOP_MASK)
47428 /*! @} */
47429 
47430 /*! @name NUMERATOR - Fractional PLL Numerator Control Register */
47431 /*! @{ */
47432 
47433 #define ETHERNET_PLL_NUMERATOR_NUM_MASK          (0x3FFFFFFFU)
47434 #define ETHERNET_PLL_NUMERATOR_NUM_SHIFT         (0U)
47435 /*! NUM - Numerator */
47436 #define ETHERNET_PLL_NUMERATOR_NUM(x)            (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_NUMERATOR_NUM_SHIFT)) & ETHERNET_PLL_NUMERATOR_NUM_MASK)
47437 /*! @} */
47438 
47439 /*! @name DENOMINATOR - Fractional PLL Denominator Control Register */
47440 /*! @{ */
47441 
47442 #define ETHERNET_PLL_DENOMINATOR_DENOM_MASK      (0x3FFFFFFFU)
47443 #define ETHERNET_PLL_DENOMINATOR_DENOM_SHIFT     (0U)
47444 /*! DENOM - Denominator */
47445 #define ETHERNET_PLL_DENOMINATOR_DENOM(x)        (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_DENOMINATOR_DENOM_SHIFT)) & ETHERNET_PLL_DENOMINATOR_DENOM_MASK)
47446 /*! @} */
47447 
47448 
47449 /*!
47450  * @}
47451  */ /* end of group ETHERNET_PLL_Register_Masks */
47452 
47453 
47454 /* ETHERNET_PLL - Peripheral instance base addresses */
47455 /** Peripheral ETHERNET_PLL base address */
47456 #define ETHERNET_PLL_BASE                        (0u)
47457 /** Peripheral ETHERNET_PLL base pointer */
47458 #define ETHERNET_PLL                             ((ETHERNET_PLL_Type *)ETHERNET_PLL_BASE)
47459 /** Array initializer of ETHERNET_PLL peripheral base addresses */
47460 #define ETHERNET_PLL_BASE_ADDRS                  { ETHERNET_PLL_BASE }
47461 /** Array initializer of ETHERNET_PLL peripheral base pointers */
47462 #define ETHERNET_PLL_BASE_PTRS                   { ETHERNET_PLL }
47463 
47464 /*!
47465  * @}
47466  */ /* end of group ETHERNET_PLL_Peripheral_Access_Layer */
47467 
47468 
47469 /* ----------------------------------------------------------------------------
47470    -- EWM Peripheral Access Layer
47471    ---------------------------------------------------------------------------- */
47472 
47473 /*!
47474  * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
47475  * @{
47476  */
47477 
47478 /** EWM - Register Layout Typedef */
47479 typedef struct {
47480   __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
47481   __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
47482   __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
47483   __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
47484   __IO uint8_t CLKCTRL;                            /**< Clock Control Register, offset: 0x4 */
47485   __IO uint8_t CLKPRESCALER;                       /**< Clock Prescaler Register, offset: 0x5 */
47486 } EWM_Type;
47487 
47488 /* ----------------------------------------------------------------------------
47489    -- EWM Register Masks
47490    ---------------------------------------------------------------------------- */
47491 
47492 /*!
47493  * @addtogroup EWM_Register_Masks EWM Register Masks
47494  * @{
47495  */
47496 
47497 /*! @name CTRL - Control Register */
47498 /*! @{ */
47499 
47500 #define EWM_CTRL_EWMEN_MASK                      (0x1U)
47501 #define EWM_CTRL_EWMEN_SHIFT                     (0U)
47502 /*! EWMEN - EWM enable.
47503  *  0b0..EWM module is disabled.
47504  *  0b1..EWM module is enabled.
47505  */
47506 #define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
47507 
47508 #define EWM_CTRL_ASSIN_MASK                      (0x2U)
47509 #define EWM_CTRL_ASSIN_SHIFT                     (1U)
47510 /*! ASSIN - EWM_in's Assertion State Select.
47511  *  0b0..Default assert state of the EWM_in signal.
47512  *  0b1..Inverts the assert state of EWM_in signal.
47513  */
47514 #define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
47515 
47516 #define EWM_CTRL_INEN_MASK                       (0x4U)
47517 #define EWM_CTRL_INEN_SHIFT                      (2U)
47518 /*! INEN - Input Enable.
47519  *  0b0..EWM_in port is disabled.
47520  *  0b1..EWM_in port is enabled.
47521  */
47522 #define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
47523 
47524 #define EWM_CTRL_INTEN_MASK                      (0x8U)
47525 #define EWM_CTRL_INTEN_SHIFT                     (3U)
47526 /*! INTEN - Interrupt Enable.
47527  *  0b1..Generates an interrupt request, when EWM_OUT_b is asserted.
47528  *  0b0..Deasserts the interrupt request.
47529  */
47530 #define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
47531 /*! @} */
47532 
47533 /*! @name SERV - Service Register */
47534 /*! @{ */
47535 
47536 #define EWM_SERV_SERVICE_MASK                    (0xFFU)
47537 #define EWM_SERV_SERVICE_SHIFT                   (0U)
47538 /*! SERVICE - SERVICE */
47539 #define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
47540 /*! @} */
47541 
47542 /*! @name CMPL - Compare Low Register */
47543 /*! @{ */
47544 
47545 #define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
47546 #define EWM_CMPL_COMPAREL_SHIFT                  (0U)
47547 /*! COMPAREL - COMPAREL */
47548 #define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
47549 /*! @} */
47550 
47551 /*! @name CMPH - Compare High Register */
47552 /*! @{ */
47553 
47554 #define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
47555 #define EWM_CMPH_COMPAREH_SHIFT                  (0U)
47556 /*! COMPAREH - COMPAREH */
47557 #define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
47558 /*! @} */
47559 
47560 /*! @name CLKCTRL - Clock Control Register */
47561 /*! @{ */
47562 
47563 #define EWM_CLKCTRL_CLKSEL_MASK                  (0x3U)
47564 #define EWM_CLKCTRL_CLKSEL_SHIFT                 (0U)
47565 /*! CLKSEL - CLKSEL */
47566 #define EWM_CLKCTRL_CLKSEL(x)                    (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
47567 /*! @} */
47568 
47569 /*! @name CLKPRESCALER - Clock Prescaler Register */
47570 /*! @{ */
47571 
47572 #define EWM_CLKPRESCALER_CLK_DIV_MASK            (0xFFU)
47573 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT           (0U)
47574 /*! CLK_DIV - CLK_DIV */
47575 #define EWM_CLKPRESCALER_CLK_DIV(x)              (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
47576 /*! @} */
47577 
47578 
47579 /*!
47580  * @}
47581  */ /* end of group EWM_Register_Masks */
47582 
47583 
47584 /* EWM - Peripheral instance base addresses */
47585 /** Peripheral EWM base address */
47586 #define EWM_BASE                                 (0x4002C000u)
47587 /** Peripheral EWM base pointer */
47588 #define EWM                                      ((EWM_Type *)EWM_BASE)
47589 /** Array initializer of EWM peripheral base addresses */
47590 #define EWM_BASE_ADDRS                           { EWM_BASE }
47591 /** Array initializer of EWM peripheral base pointers */
47592 #define EWM_BASE_PTRS                            { EWM }
47593 /** Interrupt vectors for the EWM peripheral type */
47594 #define EWM_IRQS                                 { EWM_IRQn }
47595 
47596 /*!
47597  * @}
47598  */ /* end of group EWM_Peripheral_Access_Layer */
47599 
47600 
47601 /* ----------------------------------------------------------------------------
47602    -- FLEXIO Peripheral Access Layer
47603    ---------------------------------------------------------------------------- */
47604 
47605 /*!
47606  * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
47607  * @{
47608  */
47609 
47610 /** FLEXIO - Register Layout Typedef */
47611 typedef struct {
47612   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
47613   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
47614   __IO uint32_t CTRL;                              /**< FlexIO Control Register, offset: 0x8 */
47615   __I  uint32_t PIN;                               /**< Pin State Register, offset: 0xC */
47616   __IO uint32_t SHIFTSTAT;                         /**< Shifter Status Register, offset: 0x10 */
47617   __IO uint32_t SHIFTERR;                          /**< Shifter Error Register, offset: 0x14 */
47618   __IO uint32_t TIMSTAT;                           /**< Timer Status Register, offset: 0x18 */
47619        uint8_t RESERVED_0[4];
47620   __IO uint32_t SHIFTSIEN;                         /**< Shifter Status Interrupt Enable, offset: 0x20 */
47621   __IO uint32_t SHIFTEIEN;                         /**< Shifter Error Interrupt Enable, offset: 0x24 */
47622   __IO uint32_t TIMIEN;                            /**< Timer Interrupt Enable Register, offset: 0x28 */
47623        uint8_t RESERVED_1[4];
47624   __IO uint32_t SHIFTSDEN;                         /**< Shifter Status DMA Enable, offset: 0x30 */
47625        uint8_t RESERVED_2[4];
47626   __IO uint32_t TIMERSDEN;                         /**< Timer Status DMA Enable, offset: 0x38 */
47627        uint8_t RESERVED_3[4];
47628   __IO uint32_t SHIFTSTATE;                        /**< Shifter State Register, offset: 0x40 */
47629        uint8_t RESERVED_4[60];
47630   __IO uint32_t SHIFTCTL[8];                       /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
47631        uint8_t RESERVED_5[96];
47632   __IO uint32_t SHIFTCFG[8];                       /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
47633        uint8_t RESERVED_6[224];
47634   __IO uint32_t SHIFTBUF[8];                       /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
47635        uint8_t RESERVED_7[96];
47636   __IO uint32_t SHIFTBUFBIS[8];                    /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
47637        uint8_t RESERVED_8[96];
47638   __IO uint32_t SHIFTBUFBYS[8];                    /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
47639        uint8_t RESERVED_9[96];
47640   __IO uint32_t SHIFTBUFBBS[8];                    /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
47641        uint8_t RESERVED_10[96];
47642   __IO uint32_t TIMCTL[8];                         /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
47643        uint8_t RESERVED_11[96];
47644   __IO uint32_t TIMCFG[8];                         /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
47645        uint8_t RESERVED_12[96];
47646   __IO uint32_t TIMCMP[8];                         /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
47647        uint8_t RESERVED_13[352];
47648   __IO uint32_t SHIFTBUFNBS[8];                    /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
47649        uint8_t RESERVED_14[96];
47650   __IO uint32_t SHIFTBUFHWS[8];                    /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
47651        uint8_t RESERVED_15[96];
47652   __IO uint32_t SHIFTBUFNIS[8];                    /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
47653        uint8_t RESERVED_16[96];
47654   __IO uint32_t SHIFTBUFOES[8];                    /**< Shifter Buffer N Odd Even Swapped Register, array offset: 0x800, array step: 0x4 */
47655        uint8_t RESERVED_17[96];
47656   __IO uint32_t SHIFTBUFEOS[8];                    /**< Shifter Buffer N Even Odd Swapped Register, array offset: 0x880, array step: 0x4 */
47657 } FLEXIO_Type;
47658 
47659 /* ----------------------------------------------------------------------------
47660    -- FLEXIO Register Masks
47661    ---------------------------------------------------------------------------- */
47662 
47663 /*!
47664  * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
47665  * @{
47666  */
47667 
47668 /*! @name VERID - Version ID Register */
47669 /*! @{ */
47670 
47671 #define FLEXIO_VERID_FEATURE_MASK                (0xFFFFU)
47672 #define FLEXIO_VERID_FEATURE_SHIFT               (0U)
47673 /*! FEATURE - Feature Specification Number
47674  *  0b0000000000000000..Standard features implemented.
47675  *  0b0000000000000001..Supports state, logic and parallel modes.
47676  *  0b0000000000000010..Supports pin control registers.
47677  *  0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers.
47678  */
47679 #define FLEXIO_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
47680 
47681 #define FLEXIO_VERID_MINOR_MASK                  (0xFF0000U)
47682 #define FLEXIO_VERID_MINOR_SHIFT                 (16U)
47683 /*! MINOR - Minor Version Number */
47684 #define FLEXIO_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
47685 
47686 #define FLEXIO_VERID_MAJOR_MASK                  (0xFF000000U)
47687 #define FLEXIO_VERID_MAJOR_SHIFT                 (24U)
47688 /*! MAJOR - Major Version Number */
47689 #define FLEXIO_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
47690 /*! @} */
47691 
47692 /*! @name PARAM - Parameter Register */
47693 /*! @{ */
47694 
47695 #define FLEXIO_PARAM_SHIFTER_MASK                (0xFFU)
47696 #define FLEXIO_PARAM_SHIFTER_SHIFT               (0U)
47697 /*! SHIFTER - Shifter Number */
47698 #define FLEXIO_PARAM_SHIFTER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
47699 
47700 #define FLEXIO_PARAM_TIMER_MASK                  (0xFF00U)
47701 #define FLEXIO_PARAM_TIMER_SHIFT                 (8U)
47702 /*! TIMER - Timer Number */
47703 #define FLEXIO_PARAM_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
47704 
47705 #define FLEXIO_PARAM_PIN_MASK                    (0xFF0000U)
47706 #define FLEXIO_PARAM_PIN_SHIFT                   (16U)
47707 /*! PIN - Pin Number */
47708 #define FLEXIO_PARAM_PIN(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
47709 
47710 #define FLEXIO_PARAM_TRIGGER_MASK                (0xFF000000U)
47711 #define FLEXIO_PARAM_TRIGGER_SHIFT               (24U)
47712 /*! TRIGGER - Trigger Number */
47713 #define FLEXIO_PARAM_TRIGGER(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
47714 /*! @} */
47715 
47716 /*! @name CTRL - FlexIO Control Register */
47717 /*! @{ */
47718 
47719 #define FLEXIO_CTRL_FLEXEN_MASK                  (0x1U)
47720 #define FLEXIO_CTRL_FLEXEN_SHIFT                 (0U)
47721 /*! FLEXEN - FlexIO Enable
47722  *  0b0..FlexIO module is disabled.
47723  *  0b1..FlexIO module is enabled.
47724  */
47725 #define FLEXIO_CTRL_FLEXEN(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
47726 
47727 #define FLEXIO_CTRL_SWRST_MASK                   (0x2U)
47728 #define FLEXIO_CTRL_SWRST_SHIFT                  (1U)
47729 /*! SWRST - Software Reset
47730  *  0b0..Software reset is disabled
47731  *  0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
47732  */
47733 #define FLEXIO_CTRL_SWRST(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
47734 
47735 #define FLEXIO_CTRL_FASTACC_MASK                 (0x4U)
47736 #define FLEXIO_CTRL_FASTACC_SHIFT                (2U)
47737 /*! FASTACC - Fast Access
47738  *  0b0..Configures for normal register accesses to FlexIO
47739  *  0b1..Configures for fast register accesses to FlexIO
47740  */
47741 #define FLEXIO_CTRL_FASTACC(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
47742 
47743 #define FLEXIO_CTRL_DBGE_MASK                    (0x40000000U)
47744 #define FLEXIO_CTRL_DBGE_SHIFT                   (30U)
47745 /*! DBGE - Debug Enable
47746  *  0b0..FlexIO is disabled in debug modes.
47747  *  0b1..FlexIO is enabled in debug modes
47748  */
47749 #define FLEXIO_CTRL_DBGE(x)                      (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
47750 
47751 #define FLEXIO_CTRL_DOZEN_MASK                   (0x80000000U)
47752 #define FLEXIO_CTRL_DOZEN_SHIFT                  (31U)
47753 /*! DOZEN - Doze Enable
47754  *  0b0..FlexIO enabled in Doze modes.
47755  *  0b1..FlexIO disabled in Doze modes.
47756  */
47757 #define FLEXIO_CTRL_DOZEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
47758 /*! @} */
47759 
47760 /*! @name PIN - Pin State Register */
47761 /*! @{ */
47762 
47763 #define FLEXIO_PIN_PDI_MASK                      (0xFFFFFFFFU)
47764 #define FLEXIO_PIN_PDI_SHIFT                     (0U)
47765 /*! PDI - Pin Data Input */
47766 #define FLEXIO_PIN_PDI(x)                        (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
47767 /*! @} */
47768 
47769 /*! @name SHIFTSTAT - Shifter Status Register */
47770 /*! @{ */
47771 
47772 #define FLEXIO_SHIFTSTAT_SSF_MASK                (0xFFU)
47773 #define FLEXIO_SHIFTSTAT_SSF_SHIFT               (0U)
47774 /*! SSF - Shifter Status Flag */
47775 #define FLEXIO_SHIFTSTAT_SSF(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
47776 /*! @} */
47777 
47778 /*! @name SHIFTERR - Shifter Error Register */
47779 /*! @{ */
47780 
47781 #define FLEXIO_SHIFTERR_SEF_MASK                 (0xFFU)
47782 #define FLEXIO_SHIFTERR_SEF_SHIFT                (0U)
47783 /*! SEF - Shifter Error Flags */
47784 #define FLEXIO_SHIFTERR_SEF(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
47785 /*! @} */
47786 
47787 /*! @name TIMSTAT - Timer Status Register */
47788 /*! @{ */
47789 
47790 #define FLEXIO_TIMSTAT_TSF_MASK                  (0xFFU)
47791 #define FLEXIO_TIMSTAT_TSF_SHIFT                 (0U)
47792 /*! TSF - Timer Status Flags */
47793 #define FLEXIO_TIMSTAT_TSF(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
47794 /*! @} */
47795 
47796 /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
47797 /*! @{ */
47798 
47799 #define FLEXIO_SHIFTSIEN_SSIE_MASK               (0xFFU)
47800 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT              (0U)
47801 /*! SSIE - Shifter Status Interrupt Enable */
47802 #define FLEXIO_SHIFTSIEN_SSIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
47803 /*! @} */
47804 
47805 /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
47806 /*! @{ */
47807 
47808 #define FLEXIO_SHIFTEIEN_SEIE_MASK               (0xFFU)
47809 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT              (0U)
47810 /*! SEIE - Shifter Error Interrupt Enable */
47811 #define FLEXIO_SHIFTEIEN_SEIE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
47812 /*! @} */
47813 
47814 /*! @name TIMIEN - Timer Interrupt Enable Register */
47815 /*! @{ */
47816 
47817 #define FLEXIO_TIMIEN_TEIE_MASK                  (0xFFU)
47818 #define FLEXIO_TIMIEN_TEIE_SHIFT                 (0U)
47819 /*! TEIE - Timer Status Interrupt Enable */
47820 #define FLEXIO_TIMIEN_TEIE(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
47821 /*! @} */
47822 
47823 /*! @name SHIFTSDEN - Shifter Status DMA Enable */
47824 /*! @{ */
47825 
47826 #define FLEXIO_SHIFTSDEN_SSDE_MASK               (0xFFU)
47827 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT              (0U)
47828 /*! SSDE - Shifter Status DMA Enable */
47829 #define FLEXIO_SHIFTSDEN_SSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
47830 /*! @} */
47831 
47832 /*! @name TIMERSDEN - Timer Status DMA Enable */
47833 /*! @{ */
47834 
47835 #define FLEXIO_TIMERSDEN_TSDE_MASK               (0xFFU)
47836 #define FLEXIO_TIMERSDEN_TSDE_SHIFT              (0U)
47837 /*! TSDE - Timer Status DMA Enable */
47838 #define FLEXIO_TIMERSDEN_TSDE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)
47839 /*! @} */
47840 
47841 /*! @name SHIFTSTATE - Shifter State Register */
47842 /*! @{ */
47843 
47844 #define FLEXIO_SHIFTSTATE_STATE_MASK             (0x7U)
47845 #define FLEXIO_SHIFTSTATE_STATE_SHIFT            (0U)
47846 /*! STATE - Current State Pointer */
47847 #define FLEXIO_SHIFTSTATE_STATE(x)               (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
47848 /*! @} */
47849 
47850 /*! @name SHIFTCTL - Shifter Control N Register */
47851 /*! @{ */
47852 
47853 #define FLEXIO_SHIFTCTL_SMOD_MASK                (0x7U)
47854 #define FLEXIO_SHIFTCTL_SMOD_SHIFT               (0U)
47855 /*! SMOD - Shifter Mode
47856  *  0b000..Disabled.
47857  *  0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
47858  *  0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
47859  *  0b011..Reserved.
47860  *  0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
47861  *  0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
47862  *  0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
47863  *  0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
47864  */
47865 #define FLEXIO_SHIFTCTL_SMOD(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
47866 
47867 #define FLEXIO_SHIFTCTL_PINPOL_MASK              (0x80U)
47868 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT             (7U)
47869 /*! PINPOL - Shifter Pin Polarity
47870  *  0b0..Pin is active high
47871  *  0b1..Pin is active low
47872  */
47873 #define FLEXIO_SHIFTCTL_PINPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
47874 
47875 #define FLEXIO_SHIFTCTL_PINSEL_MASK              (0x1F00U)
47876 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT             (8U)
47877 /*! PINSEL - Shifter Pin Select */
47878 #define FLEXIO_SHIFTCTL_PINSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
47879 
47880 #define FLEXIO_SHIFTCTL_PINCFG_MASK              (0x30000U)
47881 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT             (16U)
47882 /*! PINCFG - Shifter Pin Configuration
47883  *  0b00..Shifter pin output disabled
47884  *  0b01..Shifter pin open drain or bidirectional output enable
47885  *  0b10..Shifter pin bidirectional output data
47886  *  0b11..Shifter pin output
47887  */
47888 #define FLEXIO_SHIFTCTL_PINCFG(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
47889 
47890 #define FLEXIO_SHIFTCTL_TIMPOL_MASK              (0x800000U)
47891 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT             (23U)
47892 /*! TIMPOL - Timer Polarity
47893  *  0b0..Shift on posedge of Shift clock
47894  *  0b1..Shift on negedge of Shift clock
47895  */
47896 #define FLEXIO_SHIFTCTL_TIMPOL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
47897 
47898 #define FLEXIO_SHIFTCTL_TIMSEL_MASK              (0x7000000U)
47899 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT             (24U)
47900 /*! TIMSEL - Timer Select */
47901 #define FLEXIO_SHIFTCTL_TIMSEL(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
47902 /*! @} */
47903 
47904 /* The count of FLEXIO_SHIFTCTL */
47905 #define FLEXIO_SHIFTCTL_COUNT                    (8U)
47906 
47907 /*! @name SHIFTCFG - Shifter Configuration N Register */
47908 /*! @{ */
47909 
47910 #define FLEXIO_SHIFTCFG_SSTART_MASK              (0x3U)
47911 #define FLEXIO_SHIFTCFG_SSTART_SHIFT             (0U)
47912 /*! SSTART - Shifter Start bit
47913  *  0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
47914  *  0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
47915  *  0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
47916  *  0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
47917  */
47918 #define FLEXIO_SHIFTCFG_SSTART(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
47919 
47920 #define FLEXIO_SHIFTCFG_SSTOP_MASK               (0x30U)
47921 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT              (4U)
47922 /*! SSTOP - Shifter Stop bit
47923  *  0b00..Stop bit disabled for transmitter/receiver/match store
47924  *  0b01..Reserved for transmitter/receiver/match store
47925  *  0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
47926  *  0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
47927  */
47928 #define FLEXIO_SHIFTCFG_SSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
47929 
47930 #define FLEXIO_SHIFTCFG_INSRC_MASK               (0x100U)
47931 #define FLEXIO_SHIFTCFG_INSRC_SHIFT              (8U)
47932 /*! INSRC - Input Source
47933  *  0b0..Pin
47934  *  0b1..Shifter N+1 Output
47935  */
47936 #define FLEXIO_SHIFTCFG_INSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
47937 
47938 #define FLEXIO_SHIFTCFG_LATST_MASK               (0x200U)
47939 #define FLEXIO_SHIFTCFG_LATST_SHIFT              (9U)
47940 /*! LATST - Late Store
47941  *  0b0..Shift register stores the pre-shift register state.
47942  *  0b1..Shift register stores the post-shift register state.
47943  */
47944 #define FLEXIO_SHIFTCFG_LATST(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)
47945 
47946 #define FLEXIO_SHIFTCFG_PWIDTH_MASK              (0x1F0000U)
47947 #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT             (16U)
47948 /*! PWIDTH - Parallel Width */
47949 #define FLEXIO_SHIFTCFG_PWIDTH(x)                (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
47950 /*! @} */
47951 
47952 /* The count of FLEXIO_SHIFTCFG */
47953 #define FLEXIO_SHIFTCFG_COUNT                    (8U)
47954 
47955 /*! @name SHIFTBUF - Shifter Buffer N Register */
47956 /*! @{ */
47957 
47958 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK            (0xFFFFFFFFU)
47959 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT           (0U)
47960 /*! SHIFTBUF - Shift Buffer */
47961 #define FLEXIO_SHIFTBUF_SHIFTBUF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
47962 /*! @} */
47963 
47964 /* The count of FLEXIO_SHIFTBUF */
47965 #define FLEXIO_SHIFTBUF_COUNT                    (8U)
47966 
47967 /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
47968 /*! @{ */
47969 
47970 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK      (0xFFFFFFFFU)
47971 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT     (0U)
47972 /*! SHIFTBUFBIS - Shift Buffer */
47973 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
47974 /*! @} */
47975 
47976 /* The count of FLEXIO_SHIFTBUFBIS */
47977 #define FLEXIO_SHIFTBUFBIS_COUNT                 (8U)
47978 
47979 /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
47980 /*! @{ */
47981 
47982 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK      (0xFFFFFFFFU)
47983 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT     (0U)
47984 /*! SHIFTBUFBYS - Shift Buffer */
47985 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
47986 /*! @} */
47987 
47988 /* The count of FLEXIO_SHIFTBUFBYS */
47989 #define FLEXIO_SHIFTBUFBYS_COUNT                 (8U)
47990 
47991 /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
47992 /*! @{ */
47993 
47994 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK      (0xFFFFFFFFU)
47995 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT     (0U)
47996 /*! SHIFTBUFBBS - Shift Buffer */
47997 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
47998 /*! @} */
47999 
48000 /* The count of FLEXIO_SHIFTBUFBBS */
48001 #define FLEXIO_SHIFTBUFBBS_COUNT                 (8U)
48002 
48003 /*! @name TIMCTL - Timer Control N Register */
48004 /*! @{ */
48005 
48006 #define FLEXIO_TIMCTL_TIMOD_MASK                 (0x7U)
48007 #define FLEXIO_TIMCTL_TIMOD_SHIFT                (0U)
48008 /*! TIMOD - Timer Mode
48009  *  0b000..Timer Disabled.
48010  *  0b001..Dual 8-bit counters baud mode.
48011  *  0b010..Dual 8-bit counters PWM high mode.
48012  *  0b011..Single 16-bit counter mode.
48013  *  0b100..Single 16-bit counter disable mode.
48014  *  0b101..Dual 8-bit counters word mode.
48015  *  0b110..Dual 8-bit counters PWM low mode.
48016  *  0b111..Single 16-bit input capture mode.
48017  */
48018 #define FLEXIO_TIMCTL_TIMOD(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
48019 
48020 #define FLEXIO_TIMCTL_ONETIM_MASK                (0x20U)
48021 #define FLEXIO_TIMCTL_ONETIM_SHIFT               (5U)
48022 /*! ONETIM - Timer One Time Operation
48023  *  0b0..The timer enable event is generated as normal.
48024  *  0b1..The timer enable event is blocked unless timer status flag is clear.
48025  */
48026 #define FLEXIO_TIMCTL_ONETIM(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)
48027 
48028 #define FLEXIO_TIMCTL_PININS_MASK                (0x40U)
48029 #define FLEXIO_TIMCTL_PININS_SHIFT               (6U)
48030 /*! PININS - Timer Pin Input Select
48031  *  0b0..Timer pin input and output are selected by PINSEL.
48032  *  0b1..Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL.
48033  */
48034 #define FLEXIO_TIMCTL_PININS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)
48035 
48036 #define FLEXIO_TIMCTL_PINPOL_MASK                (0x80U)
48037 #define FLEXIO_TIMCTL_PINPOL_SHIFT               (7U)
48038 /*! PINPOL - Timer Pin Polarity
48039  *  0b0..Pin is active high
48040  *  0b1..Pin is active low
48041  */
48042 #define FLEXIO_TIMCTL_PINPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
48043 
48044 #define FLEXIO_TIMCTL_PINSEL_MASK                (0x1F00U)
48045 #define FLEXIO_TIMCTL_PINSEL_SHIFT               (8U)
48046 /*! PINSEL - Timer Pin Select */
48047 #define FLEXIO_TIMCTL_PINSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
48048 
48049 #define FLEXIO_TIMCTL_PINCFG_MASK                (0x30000U)
48050 #define FLEXIO_TIMCTL_PINCFG_SHIFT               (16U)
48051 /*! PINCFG - Timer Pin Configuration
48052  *  0b00..Timer pin output disabled
48053  *  0b01..Timer pin open drain or bidirectional output enable
48054  *  0b10..Timer pin bidirectional output data
48055  *  0b11..Timer pin output
48056  */
48057 #define FLEXIO_TIMCTL_PINCFG(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
48058 
48059 #define FLEXIO_TIMCTL_TRGSRC_MASK                (0x400000U)
48060 #define FLEXIO_TIMCTL_TRGSRC_SHIFT               (22U)
48061 /*! TRGSRC - Trigger Source
48062  *  0b0..External trigger selected
48063  *  0b1..Internal trigger selected
48064  */
48065 #define FLEXIO_TIMCTL_TRGSRC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
48066 
48067 #define FLEXIO_TIMCTL_TRGPOL_MASK                (0x800000U)
48068 #define FLEXIO_TIMCTL_TRGPOL_SHIFT               (23U)
48069 /*! TRGPOL - Trigger Polarity
48070  *  0b0..Trigger active high
48071  *  0b1..Trigger active low
48072  */
48073 #define FLEXIO_TIMCTL_TRGPOL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
48074 
48075 #define FLEXIO_TIMCTL_TRGSEL_MASK                (0x3F000000U)
48076 #define FLEXIO_TIMCTL_TRGSEL_SHIFT               (24U)
48077 /*! TRGSEL - Trigger Select */
48078 #define FLEXIO_TIMCTL_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
48079 /*! @} */
48080 
48081 /* The count of FLEXIO_TIMCTL */
48082 #define FLEXIO_TIMCTL_COUNT                      (8U)
48083 
48084 /*! @name TIMCFG - Timer Configuration N Register */
48085 /*! @{ */
48086 
48087 #define FLEXIO_TIMCFG_TSTART_MASK                (0x2U)
48088 #define FLEXIO_TIMCFG_TSTART_SHIFT               (1U)
48089 /*! TSTART - Timer Start Bit
48090  *  0b0..Start bit disabled
48091  *  0b1..Start bit enabled
48092  */
48093 #define FLEXIO_TIMCFG_TSTART(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
48094 
48095 #define FLEXIO_TIMCFG_TSTOP_MASK                 (0x30U)
48096 #define FLEXIO_TIMCFG_TSTOP_SHIFT                (4U)
48097 /*! TSTOP - Timer Stop Bit
48098  *  0b00..Stop bit disabled
48099  *  0b01..Stop bit is enabled on timer compare
48100  *  0b10..Stop bit is enabled on timer disable
48101  *  0b11..Stop bit is enabled on timer compare and timer disable
48102  */
48103 #define FLEXIO_TIMCFG_TSTOP(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
48104 
48105 #define FLEXIO_TIMCFG_TIMENA_MASK                (0x700U)
48106 #define FLEXIO_TIMCFG_TIMENA_SHIFT               (8U)
48107 /*! TIMENA - Timer Enable
48108  *  0b000..Timer always enabled
48109  *  0b001..Timer enabled on Timer N-1 enable
48110  *  0b010..Timer enabled on Trigger high
48111  *  0b011..Timer enabled on Trigger high and Pin high
48112  *  0b100..Timer enabled on Pin rising edge
48113  *  0b101..Timer enabled on Pin rising edge and Trigger high
48114  *  0b110..Timer enabled on Trigger rising edge
48115  *  0b111..Timer enabled on Trigger rising or falling edge
48116  */
48117 #define FLEXIO_TIMCFG_TIMENA(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
48118 
48119 #define FLEXIO_TIMCFG_TIMDIS_MASK                (0x7000U)
48120 #define FLEXIO_TIMCFG_TIMDIS_SHIFT               (12U)
48121 /*! TIMDIS - Timer Disable
48122  *  0b000..Timer never disabled
48123  *  0b001..Timer disabled on Timer N-1 disable
48124  *  0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
48125  *  0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
48126  *  0b100..Timer disabled on Pin rising or falling edge
48127  *  0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
48128  *  0b110..Timer disabled on Trigger falling edge
48129  *  0b111..Reserved
48130  */
48131 #define FLEXIO_TIMCFG_TIMDIS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
48132 
48133 #define FLEXIO_TIMCFG_TIMRST_MASK                (0x70000U)
48134 #define FLEXIO_TIMCFG_TIMRST_SHIFT               (16U)
48135 /*! TIMRST - Timer Reset
48136  *  0b000..Timer never reset
48137  *  0b001..Timer reset on Timer Output high.
48138  *  0b010..Timer reset on Timer Pin equal to Timer Output
48139  *  0b011..Timer reset on Timer Trigger equal to Timer Output
48140  *  0b100..Timer reset on Timer Pin rising edge
48141  *  0b101..Reserved
48142  *  0b110..Timer reset on Trigger rising edge
48143  *  0b111..Timer reset on Trigger rising or falling edge
48144  */
48145 #define FLEXIO_TIMCFG_TIMRST(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
48146 
48147 #define FLEXIO_TIMCFG_TIMDEC_MASK                (0x700000U)
48148 #define FLEXIO_TIMCFG_TIMDEC_SHIFT               (20U)
48149 /*! TIMDEC - Timer Decrement
48150  *  0b000..Decrement counter on FlexIO clock, Shift clock equals Timer output.
48151  *  0b001..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
48152  *  0b010..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
48153  *  0b011..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
48154  *  0b100..Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output.
48155  *  0b101..Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output.
48156  *  0b110..Decrement counter on Pin input (rising edge), Shift clock equals Pin input.
48157  *  0b111..Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input.
48158  */
48159 #define FLEXIO_TIMCFG_TIMDEC(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
48160 
48161 #define FLEXIO_TIMCFG_TIMOUT_MASK                (0x3000000U)
48162 #define FLEXIO_TIMCFG_TIMOUT_SHIFT               (24U)
48163 /*! TIMOUT - Timer Output
48164  *  0b00..Timer output is logic one when enabled and is not affected by timer reset
48165  *  0b01..Timer output is logic zero when enabled and is not affected by timer reset
48166  *  0b10..Timer output is logic one when enabled and on timer reset
48167  *  0b11..Timer output is logic zero when enabled and on timer reset
48168  */
48169 #define FLEXIO_TIMCFG_TIMOUT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
48170 /*! @} */
48171 
48172 /* The count of FLEXIO_TIMCFG */
48173 #define FLEXIO_TIMCFG_COUNT                      (8U)
48174 
48175 /*! @name TIMCMP - Timer Compare N Register */
48176 /*! @{ */
48177 
48178 #define FLEXIO_TIMCMP_CMP_MASK                   (0xFFFFU)
48179 #define FLEXIO_TIMCMP_CMP_SHIFT                  (0U)
48180 /*! CMP - Timer Compare Value */
48181 #define FLEXIO_TIMCMP_CMP(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
48182 /*! @} */
48183 
48184 /* The count of FLEXIO_TIMCMP */
48185 #define FLEXIO_TIMCMP_COUNT                      (8U)
48186 
48187 /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
48188 /*! @{ */
48189 
48190 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK      (0xFFFFFFFFU)
48191 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT     (0U)
48192 /*! SHIFTBUFNBS - Shift Buffer */
48193 #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
48194 /*! @} */
48195 
48196 /* The count of FLEXIO_SHIFTBUFNBS */
48197 #define FLEXIO_SHIFTBUFNBS_COUNT                 (8U)
48198 
48199 /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
48200 /*! @{ */
48201 
48202 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK      (0xFFFFFFFFU)
48203 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT     (0U)
48204 /*! SHIFTBUFHWS - Shift Buffer */
48205 #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
48206 /*! @} */
48207 
48208 /* The count of FLEXIO_SHIFTBUFHWS */
48209 #define FLEXIO_SHIFTBUFHWS_COUNT                 (8U)
48210 
48211 /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
48212 /*! @{ */
48213 
48214 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK      (0xFFFFFFFFU)
48215 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT     (0U)
48216 /*! SHIFTBUFNIS - Shift Buffer */
48217 #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
48218 /*! @} */
48219 
48220 /* The count of FLEXIO_SHIFTBUFNIS */
48221 #define FLEXIO_SHIFTBUFNIS_COUNT                 (8U)
48222 
48223 /*! @name SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register */
48224 /*! @{ */
48225 
48226 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK      (0xFFFFFFFFU)
48227 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT     (0U)
48228 /*! SHIFTBUFOES - Shift Buffer */
48229 #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)
48230 /*! @} */
48231 
48232 /* The count of FLEXIO_SHIFTBUFOES */
48233 #define FLEXIO_SHIFTBUFOES_COUNT                 (8U)
48234 
48235 /*! @name SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register */
48236 /*! @{ */
48237 
48238 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK      (0xFFFFFFFFU)
48239 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT     (0U)
48240 /*! SHIFTBUFEOS - Shift Buffer */
48241 #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x)        (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)
48242 /*! @} */
48243 
48244 /* The count of FLEXIO_SHIFTBUFEOS */
48245 #define FLEXIO_SHIFTBUFEOS_COUNT                 (8U)
48246 
48247 
48248 /*!
48249  * @}
48250  */ /* end of group FLEXIO_Register_Masks */
48251 
48252 
48253 /* FLEXIO - Peripheral instance base addresses */
48254 /** Peripheral FLEXIO1 base address */
48255 #define FLEXIO1_BASE                             (0x400AC000u)
48256 /** Peripheral FLEXIO1 base pointer */
48257 #define FLEXIO1                                  ((FLEXIO_Type *)FLEXIO1_BASE)
48258 /** Peripheral FLEXIO2 base address */
48259 #define FLEXIO2_BASE                             (0x400B0000u)
48260 /** Peripheral FLEXIO2 base pointer */
48261 #define FLEXIO2                                  ((FLEXIO_Type *)FLEXIO2_BASE)
48262 /** Array initializer of FLEXIO peripheral base addresses */
48263 #define FLEXIO_BASE_ADDRS                        { 0u, FLEXIO1_BASE, FLEXIO2_BASE }
48264 /** Array initializer of FLEXIO peripheral base pointers */
48265 #define FLEXIO_BASE_PTRS                         { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }
48266 /** Interrupt vectors for the FLEXIO peripheral type */
48267 #define FLEXIO_IRQS                              { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn }
48268 
48269 /*!
48270  * @}
48271  */ /* end of group FLEXIO_Peripheral_Access_Layer */
48272 
48273 
48274 /* ----------------------------------------------------------------------------
48275    -- FLEXRAM Peripheral Access Layer
48276    ---------------------------------------------------------------------------- */
48277 
48278 /*!
48279  * @addtogroup FLEXRAM_Peripheral_Access_Layer FLEXRAM Peripheral Access Layer
48280  * @{
48281  */
48282 
48283 /** FLEXRAM - Register Layout Typedef */
48284 typedef struct {
48285   __IO uint32_t TCM_CTRL;                          /**< TCM CRTL Register, offset: 0x0 */
48286   __IO uint32_t OCRAM_MAGIC_ADDR;                  /**< OCRAM Magic Address Register, offset: 0x4 */
48287   __IO uint32_t DTCM_MAGIC_ADDR;                   /**< DTCM Magic Address Register, offset: 0x8 */
48288   __IO uint32_t ITCM_MAGIC_ADDR;                   /**< ITCM Magic Address Register, offset: 0xC */
48289   __IO uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0x10 */
48290   __IO uint32_t INT_STAT_EN;                       /**< Interrupt Status Enable Register, offset: 0x14 */
48291   __IO uint32_t INT_SIG_EN;                        /**< Interrupt Enable Register, offset: 0x18 */
48292   __I  uint32_t OCRAM_ECC_SINGLE_ERROR_INFO;       /**< OCRAM single-bit ECC Error Information Register, offset: 0x1C */
48293   __I  uint32_t OCRAM_ECC_SINGLE_ERROR_ADDR;       /**< OCRAM single-bit ECC Error Address Register, offset: 0x20 */
48294   __I  uint32_t OCRAM_ECC_SINGLE_ERROR_DATA_LSB;   /**< OCRAM single-bit ECC Error Data Register, offset: 0x24 */
48295   __I  uint32_t OCRAM_ECC_SINGLE_ERROR_DATA_MSB;   /**< OCRAM single-bit ECC Error Data Register, offset: 0x28 */
48296   __I  uint32_t OCRAM_ECC_MULTI_ERROR_INFO;        /**< OCRAM multi-bit ECC Error Information Register, offset: 0x2C */
48297   __I  uint32_t OCRAM_ECC_MULTI_ERROR_ADDR;        /**< OCRAM multi-bit ECC Error Address Register, offset: 0x30 */
48298   __I  uint32_t OCRAM_ECC_MULTI_ERROR_DATA_LSB;    /**< OCRAM multi-bit ECC Error Data Register, offset: 0x34 */
48299   __I  uint32_t OCRAM_ECC_MULTI_ERROR_DATA_MSB;    /**< OCRAM multi-bit ECC Error Data Register, offset: 0x38 */
48300   __I  uint32_t ITCM_ECC_SINGLE_ERROR_INFO;        /**< ITCM single-bit ECC Error Information Register, offset: 0x3C */
48301   __I  uint32_t ITCM_ECC_SINGLE_ERROR_ADDR;        /**< ITCM single-bit ECC Error Address Register, offset: 0x40 */
48302   __I  uint32_t ITCM_ECC_SINGLE_ERROR_DATA_LSB;    /**< ITCM single-bit ECC Error Data Register, offset: 0x44 */
48303   __I  uint32_t ITCM_ECC_SINGLE_ERROR_DATA_MSB;    /**< ITCM single-bit ECC Error Data Register, offset: 0x48 */
48304   __I  uint32_t ITCM_ECC_MULTI_ERROR_INFO;         /**< ITCM multi-bit ECC Error Information Register, offset: 0x4C */
48305   __I  uint32_t ITCM_ECC_MULTI_ERROR_ADDR;         /**< ITCM multi-bit ECC Error Address Register, offset: 0x50 */
48306   __I  uint32_t ITCM_ECC_MULTI_ERROR_DATA_LSB;     /**< ITCM multi-bit ECC Error Data Register, offset: 0x54 */
48307   __I  uint32_t ITCM_ECC_MULTI_ERROR_DATA_MSB;     /**< ITCM multi-bit ECC Error Data Register, offset: 0x58 */
48308   __I  uint32_t D0TCM_ECC_SINGLE_ERROR_INFO;       /**< D0TCM single-bit ECC Error Information Register, offset: 0x5C */
48309   __I  uint32_t D0TCM_ECC_SINGLE_ERROR_ADDR;       /**< D0TCM single-bit ECC Error Address Register, offset: 0x60 */
48310   __I  uint32_t D0TCM_ECC_SINGLE_ERROR_DATA;       /**< D0TCM single-bit ECC Error Data Register, offset: 0x64 */
48311   __I  uint32_t D0TCM_ECC_MULTI_ERROR_INFO;        /**< D0TCM multi-bit ECC Error Information Register, offset: 0x68 */
48312   __I  uint32_t D0TCM_ECC_MULTI_ERROR_ADDR;        /**< D0TCM multi-bit ECC Error Address Register, offset: 0x6C */
48313   __I  uint32_t D0TCM_ECC_MULTI_ERROR_DATA;        /**< D0TCM multi-bit ECC Error Data Register, offset: 0x70 */
48314   __I  uint32_t D1TCM_ECC_SINGLE_ERROR_INFO;       /**< D1TCM single-bit ECC Error Information Register, offset: 0x74 */
48315   __I  uint32_t D1TCM_ECC_SINGLE_ERROR_ADDR;       /**< D1TCM single-bit ECC Error Address Register, offset: 0x78 */
48316   __I  uint32_t D1TCM_ECC_SINGLE_ERROR_DATA;       /**< D1TCM single-bit ECC Error Data Register, offset: 0x7C */
48317   __I  uint32_t D1TCM_ECC_MULTI_ERROR_INFO;        /**< D1TCM multi-bit ECC Error Information Register, offset: 0x80 */
48318   __I  uint32_t D1TCM_ECC_MULTI_ERROR_ADDR;        /**< D1TCM multi-bit ECC Error Address Register, offset: 0x84 */
48319   __I  uint32_t D1TCM_ECC_MULTI_ERROR_DATA;        /**< D1TCM multi-bit ECC Error Data Register, offset: 0x88 */
48320        uint8_t RESERVED_0[124];
48321   __IO uint32_t FLEXRAM_CTRL;                      /**< FlexRAM feature Control register, offset: 0x108 */
48322   __I  uint32_t OCRAM_PIPELINE_STATUS;             /**< OCRAM Pipeline Status register, offset: 0x10C */
48323 } FLEXRAM_Type;
48324 
48325 /* ----------------------------------------------------------------------------
48326    -- FLEXRAM Register Masks
48327    ---------------------------------------------------------------------------- */
48328 
48329 /*!
48330  * @addtogroup FLEXRAM_Register_Masks FLEXRAM Register Masks
48331  * @{
48332  */
48333 
48334 /*! @name TCM_CTRL - TCM CRTL Register */
48335 /*! @{ */
48336 
48337 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK       (0x1U)
48338 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT      (0U)
48339 /*! TCM_WWAIT_EN - TCM Write Wait Mode Enable
48340  *  0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle.
48341  *  0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles.
48342  */
48343 #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
48344 
48345 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK       (0x2U)
48346 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT      (1U)
48347 /*! TCM_RWAIT_EN - TCM Read Wait Mode Enable
48348  *  0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle.
48349  *  0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles.
48350  */
48351 #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
48352 
48353 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK       (0x4U)
48354 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT      (2U)
48355 /*! FORCE_CLK_ON - Force RAM Clock Always On */
48356 #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)
48357 
48358 #define FLEXRAM_TCM_CTRL_Reserved_MASK           (0xFFFFFFF8U)
48359 #define FLEXRAM_TCM_CTRL_Reserved_SHIFT          (3U)
48360 /*! Reserved - Reserved */
48361 #define FLEXRAM_TCM_CTRL_Reserved(x)             (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK)
48362 /*! @} */
48363 
48364 /*! @name OCRAM_MAGIC_ADDR - OCRAM Magic Address Register */
48365 /*! @{ */
48366 
48367 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U)
48368 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U)
48369 /*! OCRAM_WR_RD_SEL - OCRAM Write Read Select
48370  *  0b0..When OCRAM read access hits magic address, it will generate interrupt.
48371  *  0b1..When OCRAM write access hits magic address, it will generate interrupt.
48372  */
48373 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK)
48374 
48375 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x3FFFEU)
48376 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U)
48377 /*! OCRAM_MAGIC_ADDR - OCRAM Magic Address */
48378 #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK)
48379 
48380 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK   (0xFFFC0000U)
48381 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT  (18U)
48382 /*! Reserved - Reserved */
48383 #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x)     (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
48384 /*! @} */
48385 
48386 /*! @name DTCM_MAGIC_ADDR - DTCM Magic Address Register */
48387 /*! @{ */
48388 
48389 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U)
48390 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U)
48391 /*! DTCM_WR_RD_SEL - DTCM Write Read Select
48392  *  0b0..When DTCM read access hits magic address, it will generate interrupt.
48393  *  0b1..When DTCM write access hits magic address, it will generate interrupt.
48394  */
48395 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK)
48396 
48397 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU)
48398 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U)
48399 /*! DTCM_MAGIC_ADDR - DTCM Magic Address */
48400 #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK)
48401 
48402 #define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK    (0xFFFE0000U)
48403 #define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT   (17U)
48404 /*! Reserved - Reserved */
48405 #define FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x)      (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK)
48406 /*! @} */
48407 
48408 /*! @name ITCM_MAGIC_ADDR - ITCM Magic Address Register */
48409 /*! @{ */
48410 
48411 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U)
48412 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U)
48413 /*! ITCM_WR_RD_SEL - ITCM Write Read Select
48414  *  0b0..When ITCM read access hits magic address, it will generate interrupt.
48415  *  0b1..When ITCM write access hits magic address, it will generate interrupt.
48416  */
48417 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK)
48418 
48419 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU)
48420 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U)
48421 /*! ITCM_MAGIC_ADDR - ITCM Magic Address */
48422 #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK)
48423 
48424 #define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK    (0xFFFE0000U)
48425 #define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT   (17U)
48426 /*! Reserved - Reserved */
48427 #define FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x)      (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK)
48428 /*! @} */
48429 
48430 /*! @name INT_STATUS - Interrupt Status Register */
48431 /*! @{ */
48432 
48433 #define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK  (0x1U)
48434 #define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U)
48435 /*! ITCM_MAM_STATUS - ITCM Magic Address Match Status
48436  *  0b0..ITCM did not access magic address.
48437  *  0b1..ITCM accessed magic address.
48438  */
48439 #define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK)
48440 
48441 #define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK  (0x2U)
48442 #define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U)
48443 /*! DTCM_MAM_STATUS - DTCM Magic Address Match Status
48444  *  0b0..DTCM did not access magic address.
48445  *  0b1..DTCM accessed magic address.
48446  */
48447 #define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK)
48448 
48449 #define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U)
48450 #define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U)
48451 /*! OCRAM_MAM_STATUS - OCRAM Magic Address Match Status
48452  *  0b0..OCRAM did not access magic address.
48453  *  0b1..OCRAM accessed magic address.
48454  */
48455 #define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK)
48456 
48457 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK  (0x8U)
48458 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
48459 /*! ITCM_ERR_STATUS - ITCM Access Error Status
48460  *  0b0..ITCM access error does not happen
48461  *  0b1..ITCM access error happens.
48462  */
48463 #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
48464 
48465 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK  (0x10U)
48466 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
48467 /*! DTCM_ERR_STATUS - DTCM Access Error Status
48468  *  0b0..DTCM access error does not happen
48469  *  0b1..DTCM access error happens.
48470  */
48471 #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
48472 
48473 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
48474 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
48475 /*! OCRAM_ERR_STATUS - OCRAM Access Error Status
48476  *  0b0..OCRAM access error does not happen
48477  *  0b1..OCRAM access error happens.
48478  */
48479 #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
48480 
48481 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK (0x40U)
48482 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_SHIFT (6U)
48483 /*! OCRAM_ECC_ERRM_INT - OCRAM access multi-bit ECC Error Interrupt Status
48484  *  0b0..OCRAM multi-bit ECC error does not happen
48485  *  0b1..OCRAM multi-bit ECC error happens.
48486  */
48487 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK)
48488 
48489 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK (0x80U)
48490 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_SHIFT (7U)
48491 /*! OCRAM_ECC_ERRS_INT - OCRAM access single-bit ECC Error Interrupt Status
48492  *  0b0..OCRAM single-bit ECC error does not happen
48493  *  0b1..OCRAM single-bit ECC error happens.
48494  */
48495 #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK)
48496 
48497 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK (0x100U)
48498 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_SHIFT (8U)
48499 /*! ITCM_ECC_ERRM_INT - ITCM Access multi-bit ECC Error Interrupt Status
48500  *  0b0..ITCM multi-bit ECC error does not happen
48501  *  0b1..ITCM multi-bit ECC error happens.
48502  */
48503 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK)
48504 
48505 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK (0x200U)
48506 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_SHIFT (9U)
48507 /*! ITCM_ECC_ERRS_INT - ITCM access single-bit ECC Error Interrupt Status
48508  *  0b0..ITCM single-bit ECC error does not happen
48509  *  0b1..ITCM single-bit ECC error happens.
48510  */
48511 #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK)
48512 
48513 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK (0x400U)
48514 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_SHIFT (10U)
48515 /*! D0TCM_ECC_ERRM_INT - D0TCM access multi-bit ECC Error Interrupt Status
48516  *  0b0..D0TCM multi-bit ECC error does not happen
48517  *  0b1..D0TCM multi-bit ECC error happens.
48518  */
48519 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK)
48520 
48521 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK (0x800U)
48522 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_SHIFT (11U)
48523 /*! D0TCM_ECC_ERRS_INT - D0TCM access single-bit ECC Error Interrupt Status
48524  *  0b0..D0TCM single-bit ECC error does not happen
48525  *  0b1..D0TCM single-bit ECC error happens.
48526  */
48527 #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK)
48528 
48529 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK (0x1000U)
48530 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_SHIFT (12U)
48531 /*! D1TCM_ECC_ERRM_INT - D1TCM access multi-bit ECC Error Interrupt Status
48532  *  0b0..D1TCM multi-bit ECC error does not happen
48533  *  0b1..D1TCM multi-bit ECC error happens.
48534  */
48535 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK)
48536 
48537 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK (0x2000U)
48538 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_SHIFT (13U)
48539 /*! D1TCM_ECC_ERRS_INT - D1TCM access single-bit ECC Error Interrupt Status
48540  *  0b0..D1TCM single-bit ECC error does not happen
48541  *  0b1..D1TCM single-bit ECC error happens.
48542  */
48543 #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK)
48544 
48545 #define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_MASK (0x4000U)
48546 #define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_SHIFT (14U)
48547 /*! ITCM_PARTIAL_WR_INT_S - ITCM Partial Write Interrupt Status
48548  *  0b0..ITCM Partial Write does not happen
48549  *  0b1..ITCM Partial Write happens.
48550  */
48551 #define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_MASK)
48552 
48553 #define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_MASK (0x8000U)
48554 #define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_SHIFT (15U)
48555 /*! D0TCM_PARTIAL_WR_INT_S - D0TCM Partial Write Interrupt Status
48556  *  0b0..D0TCM Partial Write does not happen
48557  *  0b1..D0TCM Partial Write happens.
48558  */
48559 #define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_MASK)
48560 
48561 #define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_MASK (0x10000U)
48562 #define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_SHIFT (16U)
48563 /*! D1TCM_PARTIAL_WR_INT_S - D1TCM Partial Write Interrupt Status
48564  *  0b0..D1TCM Partial Write does not happen
48565  *  0b1..D1TCM Partial Write happens.
48566  */
48567 #define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_MASK)
48568 
48569 #define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_MASK (0x20000U)
48570 #define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_SHIFT (17U)
48571 /*! OCRAM_PARTIAL_WR_INT_S - OCRAM Partial Write Interrupt Status
48572  *  0b0..OCRAM Partial Write does not happen
48573  *  0b1..OCRAM Partial Write happens.
48574  */
48575 #define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_MASK)
48576 
48577 #define FLEXRAM_INT_STATUS_Reserved_MASK         (0xFFFC0000U)
48578 #define FLEXRAM_INT_STATUS_Reserved_SHIFT        (18U)
48579 /*! Reserved - Reserved */
48580 #define FLEXRAM_INT_STATUS_Reserved(x)           (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK)
48581 /*! @} */
48582 
48583 /*! @name INT_STAT_EN - Interrupt Status Enable Register */
48584 /*! @{ */
48585 
48586 #define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U)
48587 #define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U)
48588 /*! ITCM_MAM_STAT_EN - ITCM Magic Address Match Status Enable
48589  *  0b0..Masked
48590  *  0b1..Enabled
48591  */
48592 #define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK)
48593 
48594 #define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U)
48595 #define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U)
48596 /*! DTCM_MAM_STAT_EN - DTCM Magic Address Match Status Enable
48597  *  0b0..Masked
48598  *  0b1..Enabled
48599  */
48600 #define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK)
48601 
48602 #define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U)
48603 #define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U)
48604 /*! OCRAM_MAM_STAT_EN - OCRAM Magic Address Match Status Enable
48605  *  0b0..Masked
48606  *  0b1..Enabled
48607  */
48608 #define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK)
48609 
48610 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
48611 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
48612 /*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable
48613  *  0b0..Masked
48614  *  0b1..Enabled
48615  */
48616 #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
48617 
48618 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
48619 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
48620 /*! DTCM_ERR_STAT_EN - DTCM Access Error Status Enable
48621  *  0b0..Masked
48622  *  0b1..Enabled
48623  */
48624 #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
48625 
48626 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
48627 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
48628 /*! OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable
48629  *  0b0..Masked
48630  *  0b1..Enabled
48631  */
48632 #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)
48633 
48634 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_MASK (0x40U)
48635 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_SHIFT (6U)
48636 /*! OCRAM_ERRM_INT_EN - OCRAM Access multi-bit ECC Error Interrupt Status Enable
48637  *  0b0..Masked
48638  *  0b1..Enabled
48639  */
48640 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_MASK)
48641 
48642 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_MASK (0x80U)
48643 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_SHIFT (7U)
48644 /*! OCRAM_ERRS_INT_EN - OCRAM Access single-bit ECC Error Interrupt Status Enable
48645  *  0b0..Masked
48646  *  0b1..Enabled
48647  */
48648 #define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_MASK)
48649 
48650 #define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_MASK (0x100U)
48651 #define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_SHIFT (8U)
48652 /*! ITCM_ERRM_INT_EN - ITCM Access multi-bit ECC Error Interrupt Status Enable
48653  *  0b0..Masked
48654  *  0b1..Enabled
48655  */
48656 #define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_MASK)
48657 
48658 #define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_MASK (0x200U)
48659 #define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_SHIFT (9U)
48660 /*! ITCM_ERRS_INT_EN - ITCM Access single-bit ECC Error Interrupt Status Enable
48661  *  0b0..Masked
48662  *  0b1..Enabled
48663  */
48664 #define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN(x)  (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_MASK)
48665 
48666 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_MASK (0x400U)
48667 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_SHIFT (10U)
48668 /*! D0TCM_ERRM_INT_EN - D0TCM Access multi-bit ECC Error Interrupt Status Enable
48669  *  0b0..Masked
48670  *  0b1..Enabled
48671  */
48672 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_MASK)
48673 
48674 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_MASK (0x800U)
48675 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_SHIFT (11U)
48676 /*! D0TCM_ERRS_INT_EN - D0TCM Access single-bit ECC Error Interrupt Status Enable
48677  *  0b0..Masked
48678  *  0b1..Enabled
48679  */
48680 #define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_MASK)
48681 
48682 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_MASK (0x1000U)
48683 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_SHIFT (12U)
48684 /*! D1TCM_ERRM_INT_EN - D1TCM Access multi-bit ECC Error Interrupt Status Enable
48685  *  0b0..Masked
48686  *  0b1..Enabled
48687  */
48688 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_MASK)
48689 
48690 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_MASK (0x2000U)
48691 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_SHIFT (13U)
48692 /*! D1TCM_ERRS_INT_EN - D1TCM Access single-bit ECC Error Interrupt Status Enable
48693  *  0b0..Masked
48694  *  0b1..Enabled
48695  */
48696 #define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_MASK)
48697 
48698 #define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_MASK (0x4000U)
48699 #define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_SHIFT (14U)
48700 /*! ITCM_PARTIAL_WR_INT_S_EN - ITCM Partial Write Interrupt Status Enable
48701  *  0b0..Masked
48702  *  0b1..Enabled
48703  */
48704 #define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_MASK)
48705 
48706 #define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_MASK (0x8000U)
48707 #define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_SHIFT (15U)
48708 /*! D0TCM_PARTIAL_WR_INT_S_EN - D0TCM Partial Write Interrupt Status Enable
48709  *  0b0..Masked
48710  *  0b1..Enabled
48711  */
48712 #define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_MASK)
48713 
48714 #define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_MASK (0x10000U)
48715 #define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_SHIFT (16U)
48716 /*! D1TCM_PARTIAL_WR_INT_S_EN - D1TCM Partial Write Interrupt Status EN
48717  *  0b0..Masked
48718  *  0b1..Enbaled
48719  */
48720 #define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_MASK)
48721 
48722 #define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_MASK (0x20000U)
48723 #define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_SHIFT (17U)
48724 /*! OCRAM_PARTIAL_WR_INT_S_EN - OCRAM Partial Write Interrupt Status
48725  *  0b0..Masked
48726  *  0b1..Enabled
48727  */
48728 #define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_MASK)
48729 
48730 #define FLEXRAM_INT_STAT_EN_Reserved_MASK        (0xFFFC0000U)
48731 #define FLEXRAM_INT_STAT_EN_Reserved_SHIFT       (18U)
48732 /*! Reserved - Reserved */
48733 #define FLEXRAM_INT_STAT_EN_Reserved(x)          (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK)
48734 /*! @} */
48735 
48736 /*! @name INT_SIG_EN - Interrupt Enable Register */
48737 /*! @{ */
48738 
48739 #define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK  (0x1U)
48740 #define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U)
48741 /*! ITCM_MAM_SIG_EN - ITCM Magic Address Match Interrupt Enable
48742  *  0b0..Masked
48743  *  0b1..Enabled
48744  */
48745 #define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK)
48746 
48747 #define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK  (0x2U)
48748 #define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U)
48749 /*! DTCM_MAM_SIG_EN - DTCM Magic Address Match Interrupt Enable
48750  *  0b0..Masked
48751  *  0b1..Enabled
48752  */
48753 #define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK)
48754 
48755 #define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U)
48756 #define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U)
48757 /*! OCRAM_MAM_SIG_EN - OCRAM Magic Address Match Interrupt Enable
48758  *  0b0..Masked
48759  *  0b1..Enabled
48760  */
48761 #define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK)
48762 
48763 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK  (0x8U)
48764 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
48765 /*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable
48766  *  0b0..Masked
48767  *  0b1..Enabled
48768  */
48769 #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
48770 
48771 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK  (0x10U)
48772 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
48773 /*! DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable
48774  *  0b0..Masked
48775  *  0b1..Enabled
48776  */
48777 #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
48778 
48779 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
48780 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
48781 /*! OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable
48782  *  0b0..Masked
48783  *  0b1..Enabled
48784  */
48785 #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)
48786 
48787 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_MASK (0x40U)
48788 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_SHIFT (6U)
48789 /*! OCRAM_ERRM_INT_SIG_EN - OCRAM Access multi-bit ECC Error Interrupt Signal Enable
48790  *  0b0..Masked
48791  *  0b1..Enabled
48792  */
48793 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_MASK)
48794 
48795 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_MASK (0x80U)
48796 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_SHIFT (7U)
48797 /*! OCRAM_ERRS_INT_SIG_EN - OCRAM Access single-bit ECC Error Interrupt Signal Enable
48798  *  0b0..Masked
48799  *  0b1..Enabled
48800  */
48801 #define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_MASK)
48802 
48803 #define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_MASK (0x100U)
48804 #define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_SHIFT (8U)
48805 /*! ITCM_ERRM_INT_SIG_EN - ITCM Access multi-bit ECC Error Interrupt Signal Enable
48806  *  0b0..Masked
48807  *  0b1..Enabled
48808  */
48809 #define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_MASK)
48810 
48811 #define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_MASK (0x200U)
48812 #define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_SHIFT (9U)
48813 /*! ITCM_ERRS_INT_SIG_EN - ITCM Access single-bit ECC Error Interrupt Signal Enable
48814  *  0b0..Masked
48815  *  0b1..Enabled
48816  */
48817 #define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_MASK)
48818 
48819 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_MASK (0x400U)
48820 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_SHIFT (10U)
48821 /*! D0TCM_ERRM_INT_SIG_EN - D0TCM Access multi-bit ECC Error Interrupt Signal Enable
48822  *  0b0..Masked
48823  *  0b1..Enabled
48824  */
48825 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_MASK)
48826 
48827 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_MASK (0x800U)
48828 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_SHIFT (11U)
48829 /*! D0TCM_ERRS_INT_SIG_EN - D0TCM Access single-bit ECC Error Interrupt Signal Enable
48830  *  0b0..Masked
48831  *  0b1..Enabled
48832  */
48833 #define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_MASK)
48834 
48835 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_MASK (0x1000U)
48836 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_SHIFT (12U)
48837 /*! D1TCM_ERRM_INT_SIG_EN - D1TCM Access multi-bit ECC Error Interrupt Signal Enable
48838  *  0b0..Masked
48839  *  0b1..Enabled
48840  */
48841 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_MASK)
48842 
48843 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_MASK (0x2000U)
48844 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_SHIFT (13U)
48845 /*! D1TCM_ERRS_INT_SIG_EN - D1TCM Access single-bit ECC Error Interrupt Signal Enable
48846  *  0b0..Masked
48847  *  0b1..Enabled
48848  */
48849 #define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_MASK)
48850 
48851 #define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_MASK (0x4000U)
48852 #define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_SHIFT (14U)
48853 /*! ITCM_PARTIAL_WR_INT_SIG_EN - ITCM Partial Write Interrupt Signal Enable Enable
48854  *  0b0..Masked
48855  *  0b1..Enabled
48856  */
48857 #define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_MASK)
48858 
48859 #define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_MASK (0x8000U)
48860 #define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_SHIFT (15U)
48861 /*! D0TCM_PARTIAL_WR_INT_SIG_EN - D0TCM Partial Write Interrupt Signal Enable Enable
48862  *  0b0..Masked
48863  *  0b1..Enabled
48864  */
48865 #define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_MASK)
48866 
48867 #define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_MASK (0x10000U)
48868 #define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_SHIFT (16U)
48869 /*! D1TCM_PARTIAL_WR_INT_SIG_EN - D1TCM Partial Write Interrupt Signal Enable EN
48870  *  0b0..Masked
48871  *  0b1..Enbaled
48872  */
48873 #define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_MASK)
48874 
48875 #define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_MASK (0x20000U)
48876 #define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_SHIFT (17U)
48877 /*! OCRAM_PARTIAL_WR_INT_SIG_EN - OCRAM Partial Write Interrupt Signal Enable
48878  *  0b0..Masked
48879  *  0b1..Enabled
48880  */
48881 #define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_MASK)
48882 
48883 #define FLEXRAM_INT_SIG_EN_Reserved_MASK         (0xFFFC0000U)
48884 #define FLEXRAM_INT_SIG_EN_Reserved_SHIFT        (18U)
48885 /*! Reserved - Reserved */
48886 #define FLEXRAM_INT_SIG_EN_Reserved(x)           (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK)
48887 /*! @} */
48888 
48889 /*! @name OCRAM_ECC_SINGLE_ERROR_INFO - OCRAM single-bit ECC Error Information Register */
48890 /*! @{ */
48891 
48892 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK (0xFFU)
48893 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT (0U)
48894 /*! OCRAM_ECCS_ERRED_ECC - corresponding ECC cipher of OCRAM single-bit ECC error */
48895 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK)
48896 
48897 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK (0xFF00U)
48898 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT (8U)
48899 /*! OCRAM_ECCS_ERRED_SYN - corresponding ECC syndrome of OCRAM single-bit ECC error */
48900 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK)
48901 
48902 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFFF0000U)
48903 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (16U)
48904 /*! Reserved - Reserved */
48905 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
48906 /*! @} */
48907 
48908 /*! @name OCRAM_ECC_SINGLE_ERROR_ADDR - OCRAM single-bit ECC Error Address Register */
48909 /*! @{ */
48910 
48911 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
48912 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_SHIFT (0U)
48913 /*! OCRAM_ECCS_ERRED_ADDR - OCRAM single-bit ECC error address */
48914 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_MASK)
48915 /*! @} */
48916 
48917 /*! @name OCRAM_ECC_SINGLE_ERROR_DATA_LSB - OCRAM single-bit ECC Error Data Register */
48918 /*! @{ */
48919 
48920 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
48921 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_SHIFT (0U)
48922 /*! OCRAM_ECCS_ERRED_DATA_LSB - OCRAM single-bit ECC error data [31:0] */
48923 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_MASK)
48924 /*! @} */
48925 
48926 /*! @name OCRAM_ECC_SINGLE_ERROR_DATA_MSB - OCRAM single-bit ECC Error Data Register */
48927 /*! @{ */
48928 
48929 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
48930 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_SHIFT (0U)
48931 /*! OCRAM_ECCS_ERRED_DATA_MSB - OCRAM single-bit ECC error data [63:32] */
48932 #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_MASK)
48933 /*! @} */
48934 
48935 /*! @name OCRAM_ECC_MULTI_ERROR_INFO - OCRAM multi-bit ECC Error Information Register */
48936 /*! @{ */
48937 
48938 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK (0xFFU)
48939 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT (0U)
48940 /*! OCRAM_ECCM_ERRED_ECC - OCRAM multi-bit ECC error corresponding ECC value */
48941 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK)
48942 
48943 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFFFFF00U)
48944 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (8U)
48945 /*! Reserved - Reserved */
48946 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
48947 /*! @} */
48948 
48949 /*! @name OCRAM_ECC_MULTI_ERROR_ADDR - OCRAM multi-bit ECC Error Address Register */
48950 /*! @{ */
48951 
48952 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
48953 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_SHIFT (0U)
48954 /*! OCRAM_ECCM_ERRED_ADDR - OCRAM multi-bit ECC error address */
48955 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_MASK)
48956 /*! @} */
48957 
48958 /*! @name OCRAM_ECC_MULTI_ERROR_DATA_LSB - OCRAM multi-bit ECC Error Data Register */
48959 /*! @{ */
48960 
48961 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
48962 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_SHIFT (0U)
48963 /*! OCRAM_ECCM_ERRED_DATA_LSB - OCRAM multi-bit ECC error data [31:0] */
48964 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_MASK)
48965 /*! @} */
48966 
48967 /*! @name OCRAM_ECC_MULTI_ERROR_DATA_MSB - OCRAM multi-bit ECC Error Data Register */
48968 /*! @{ */
48969 
48970 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
48971 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_SHIFT (0U)
48972 /*! OCRAM_ECCM_ERRED_DATA_MSB - OCRAM multi-bit ECC error data [63:32] */
48973 #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_MASK)
48974 /*! @} */
48975 
48976 /*! @name ITCM_ECC_SINGLE_ERROR_INFO - ITCM single-bit ECC Error Information Register */
48977 /*! @{ */
48978 
48979 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK (0x1U)
48980 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT (0U)
48981 /*! ITCM_ECCS_EFW - ITCM single-bit ECC error corresponding TCM_WR value. */
48982 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK)
48983 
48984 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK (0xEU)
48985 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT (1U)
48986 /*! ITCM_ECCS_EFSIZ - ITCM single-bit ECC error corresponding TCM size */
48987 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK)
48988 
48989 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK (0xF0U)
48990 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT (4U)
48991 /*! ITCM_ECCS_EFMST - ITCM single-bit ECC error corresponding TCM_MASTER. */
48992 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK)
48993 
48994 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK (0xF00U)
48995 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT (8U)
48996 /*! ITCM_ECCS_EFPRT - ITCM single-bit ECC error corresponding TCM_PRIV. */
48997 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK)
48998 
48999 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK (0xFF000U)
49000 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT (12U)
49001 /*! ITCM_ECCS_EFSYN - ITCM single-bit ECC error corresponding syndrome */
49002 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK)
49003 
49004 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF00000U)
49005 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (20U)
49006 /*! Reserved - Reserved */
49007 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
49008 /*! @} */
49009 
49010 /*! @name ITCM_ECC_SINGLE_ERROR_ADDR - ITCM single-bit ECC Error Address Register */
49011 /*! @{ */
49012 
49013 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
49014 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT (0U)
49015 /*! ITCM_ECCS_ERRED_ADDR - ITCM single-bit ECC error address */
49016 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK)
49017 /*! @} */
49018 
49019 /*! @name ITCM_ECC_SINGLE_ERROR_DATA_LSB - ITCM single-bit ECC Error Data Register */
49020 /*! @{ */
49021 
49022 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
49023 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT (0U)
49024 /*! ITCM_ECCS_ERRED_DATA_LSB - ITCM single-bit ECC error data [31:0] */
49025 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK)
49026 /*! @} */
49027 
49028 /*! @name ITCM_ECC_SINGLE_ERROR_DATA_MSB - ITCM single-bit ECC Error Data Register */
49029 /*! @{ */
49030 
49031 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
49032 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT (0U)
49033 /*! ITCM_ECCS_ERRED_DATA_MSB - ITCM single-bit ECC error data [63:32] */
49034 #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK)
49035 /*! @} */
49036 
49037 /*! @name ITCM_ECC_MULTI_ERROR_INFO - ITCM multi-bit ECC Error Information Register */
49038 /*! @{ */
49039 
49040 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK (0x1U)
49041 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT (0U)
49042 /*! ITCM_ECCM_EFW - ITCM multi-bit ECC error corresponding TCM_WR value */
49043 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK)
49044 
49045 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK (0xEU)
49046 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT (1U)
49047 /*! ITCM_ECCM_EFSIZ - ITCM multi-bit ECC error corresponding tcm access size */
49048 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK)
49049 
49050 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK (0xF0U)
49051 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT (4U)
49052 /*! ITCM_ECCM_EFMST - ITCM multi-bit ECC error corresponding TCM_MASTER */
49053 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK)
49054 
49055 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK (0xF00U)
49056 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT (8U)
49057 /*! ITCM_ECCM_EFPRT - ITCM multi-bit ECC error corresponding TCM_PRIV */
49058 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK)
49059 
49060 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_MASK (0xFF000U)
49061 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_SHIFT (12U)
49062 /*! ITCM_ECCM_EFSYN - ITCM multi-bit ECC error corresponding syndrome */
49063 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_MASK)
49064 
49065 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF00000U)
49066 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (20U)
49067 /*! Reserved - Reserved */
49068 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
49069 /*! @} */
49070 
49071 /*! @name ITCM_ECC_MULTI_ERROR_ADDR - ITCM multi-bit ECC Error Address Register */
49072 /*! @{ */
49073 
49074 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
49075 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT (0U)
49076 /*! ITCM_ECCM_ERRED_ADDR - ITCM multi-bit ECC error address */
49077 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK)
49078 /*! @} */
49079 
49080 /*! @name ITCM_ECC_MULTI_ERROR_DATA_LSB - ITCM multi-bit ECC Error Data Register */
49081 /*! @{ */
49082 
49083 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
49084 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT (0U)
49085 /*! ITCM_ECCM_ERRED_DATA_LSB - ITCM multi-bit ECC error data [31:0] */
49086 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK)
49087 /*! @} */
49088 
49089 /*! @name ITCM_ECC_MULTI_ERROR_DATA_MSB - ITCM multi-bit ECC Error Data Register */
49090 /*! @{ */
49091 
49092 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
49093 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT (0U)
49094 /*! ITCM_ECCM_ERRED_DATA_MSB - ITCM multi-bit ECC error data [63:32] */
49095 #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK)
49096 /*! @} */
49097 
49098 /*! @name D0TCM_ECC_SINGLE_ERROR_INFO - D0TCM single-bit ECC Error Information Register */
49099 /*! @{ */
49100 
49101 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK (0x1U)
49102 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT (0U)
49103 /*! D0TCM_ECCS_EFW - D0TCM single-bit ECC error corresponding TCM_WR value */
49104 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK)
49105 
49106 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK (0xEU)
49107 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT (1U)
49108 /*! D0TCM_ECCS_EFSIZ - D0TCM single-bit ECC error corresponding tcm access size */
49109 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK)
49110 
49111 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK (0xF0U)
49112 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT (4U)
49113 /*! D0TCM_ECCS_EFMST - D0TCM single-bit ECC error corresponding TCM_MASTER */
49114 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK)
49115 
49116 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK (0xF00U)
49117 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT (8U)
49118 /*! D0TCM_ECCS_EFPRT - D0TCM single-bit ECC error corresponding TCM_PRIV */
49119 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK)
49120 
49121 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK (0x7F000U)
49122 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT (12U)
49123 /*! D0TCM_ECCS_EFSYN - D0TCM single-bit ECC error corresponding syndrome */
49124 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK)
49125 
49126 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U)
49127 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U)
49128 /*! Reserved - Reserved */
49129 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
49130 /*! @} */
49131 
49132 /*! @name D0TCM_ECC_SINGLE_ERROR_ADDR - D0TCM single-bit ECC Error Address Register */
49133 /*! @{ */
49134 
49135 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
49136 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT (0U)
49137 /*! D0TCM_ECCS_ERRED_ADDR - D0TCM single-bit ECC error address */
49138 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK)
49139 /*! @} */
49140 
49141 /*! @name D0TCM_ECC_SINGLE_ERROR_DATA - D0TCM single-bit ECC Error Data Register */
49142 /*! @{ */
49143 
49144 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU)
49145 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT (0U)
49146 /*! D0TCM_ECCS_ERRED_DATA - D0TCM single-bit ECC error data */
49147 #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK)
49148 /*! @} */
49149 
49150 /*! @name D0TCM_ECC_MULTI_ERROR_INFO - D0TCM multi-bit ECC Error Information Register */
49151 /*! @{ */
49152 
49153 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK (0x1U)
49154 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT (0U)
49155 /*! D0TCM_ECCM_EFW - D0TCM multi-bit ECC error corresponding TCM_WR value */
49156 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK)
49157 
49158 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK (0xEU)
49159 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT (1U)
49160 /*! D0TCM_ECCM_EFSIZ - D0TCM multi-bit ECC error corresponding tcm access size */
49161 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK)
49162 
49163 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK (0xF0U)
49164 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT (4U)
49165 /*! D0TCM_ECCM_EFMST - D0TCM multi-bit ECC error corresponding TCM_MASTER */
49166 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK)
49167 
49168 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK (0xF00U)
49169 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT (8U)
49170 /*! D0TCM_ECCM_EFPRT - D0TCM multi-bit ECC error corresponding TCM_PRIV */
49171 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK)
49172 
49173 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_MASK (0x7F000U)
49174 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_SHIFT (12U)
49175 /*! D0TCM_ECCM_EFSYN - D0TCM multi-bit ECC error corresponding syndrome */
49176 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_MASK)
49177 
49178 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U)
49179 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U)
49180 /*! Reserved - Reserved */
49181 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
49182 /*! @} */
49183 
49184 /*! @name D0TCM_ECC_MULTI_ERROR_ADDR - D0TCM multi-bit ECC Error Address Register */
49185 /*! @{ */
49186 
49187 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
49188 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT (0U)
49189 /*! D0TCM_ECCM_ERRED_ADDR - D0TCM multi-bit ECC error address */
49190 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK)
49191 /*! @} */
49192 
49193 /*! @name D0TCM_ECC_MULTI_ERROR_DATA - D0TCM multi-bit ECC Error Data Register */
49194 /*! @{ */
49195 
49196 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU)
49197 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT (0U)
49198 /*! D0TCM_ECCM_ERRED_DATA - D0TCM multi-bit ECC error data */
49199 #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK)
49200 /*! @} */
49201 
49202 /*! @name D1TCM_ECC_SINGLE_ERROR_INFO - D1TCM single-bit ECC Error Information Register */
49203 /*! @{ */
49204 
49205 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK (0x1U)
49206 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT (0U)
49207 /*! D1TCM_ECCS_EFW - D1TCM single-bit ECC error corresponding TCM_WR value */
49208 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK)
49209 
49210 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK (0xEU)
49211 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT (1U)
49212 /*! D1TCM_ECCS_EFSIZ - D1TCM single-bit ECC error corresponding tcm access size */
49213 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK)
49214 
49215 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK (0xF0U)
49216 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT (4U)
49217 /*! D1TCM_ECCS_EFMST - D1TCM single-bit ECC error corresponding TCM_MASTER */
49218 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK)
49219 
49220 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK (0xF00U)
49221 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT (8U)
49222 /*! D1TCM_ECCS_EFPRT - D1TCM single-bit ECC error corresponding TCM_PRIV */
49223 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK)
49224 
49225 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK (0x7F000U)
49226 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT (12U)
49227 /*! D1TCM_ECCS_EFSYN - D1TCM single-bit ECC error corresponding syndrome */
49228 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK)
49229 
49230 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U)
49231 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U)
49232 /*! Reserved - Reserved */
49233 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
49234 /*! @} */
49235 
49236 /*! @name D1TCM_ECC_SINGLE_ERROR_ADDR - D1TCM single-bit ECC Error Address Register */
49237 /*! @{ */
49238 
49239 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
49240 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT (0U)
49241 /*! D1TCM_ECCS_ERRED_ADDR - D1TCM single-bit ECC error address */
49242 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK)
49243 /*! @} */
49244 
49245 /*! @name D1TCM_ECC_SINGLE_ERROR_DATA - D1TCM single-bit ECC Error Data Register */
49246 /*! @{ */
49247 
49248 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU)
49249 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT (0U)
49250 /*! D1TCM_ECCS_ERRED_DATA - D1TCM single-bit ECC error data */
49251 #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK)
49252 /*! @} */
49253 
49254 /*! @name D1TCM_ECC_MULTI_ERROR_INFO - D1TCM multi-bit ECC Error Information Register */
49255 /*! @{ */
49256 
49257 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK (0x1U)
49258 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT (0U)
49259 /*! D1TCM_ECCM_EFW - D1TCM multi-bit ECC error corresponding TCM_WR value */
49260 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK)
49261 
49262 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK (0xEU)
49263 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT (1U)
49264 /*! D1TCM_ECCM_EFSIZ - D1TCM multi-bit ECC error corresponding tcm access size */
49265 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK)
49266 
49267 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK (0xF0U)
49268 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT (4U)
49269 /*! D1TCM_ECCM_EFMST - D1TCM multi-bit ECC error corresponding TCM_MASTER */
49270 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK)
49271 
49272 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK (0xF00U)
49273 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT (8U)
49274 /*! D1TCM_ECCM_EFPRT - D1TCM multi-bit ECC error corresponding TCM_PRIV */
49275 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK)
49276 
49277 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_MASK (0x7F000U)
49278 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_SHIFT (12U)
49279 /*! D1TCM_ECCM_EFSYN - D1TCM multi-bit ECC error corresponding syndrome */
49280 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_MASK)
49281 
49282 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U)
49283 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U)
49284 /*! Reserved - Reserved */
49285 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
49286 /*! @} */
49287 
49288 /*! @name D1TCM_ECC_MULTI_ERROR_ADDR - D1TCM multi-bit ECC Error Address Register */
49289 /*! @{ */
49290 
49291 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
49292 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT (0U)
49293 /*! D1TCM_ECCM_ERRED_ADDR - D1TCM multi-bit ECC error address */
49294 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK)
49295 /*! @} */
49296 
49297 /*! @name D1TCM_ECC_MULTI_ERROR_DATA - D1TCM multi-bit ECC Error Data Register */
49298 /*! @{ */
49299 
49300 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU)
49301 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT (0U)
49302 /*! D1TCM_ECCM_ERRED_DATA - D1TCM multi-bit ECC error data */
49303 #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK)
49304 /*! @} */
49305 
49306 /*! @name FLEXRAM_CTRL - FlexRAM feature Control register */
49307 /*! @{ */
49308 
49309 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_MASK (0x1U)
49310 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_SHIFT (0U)
49311 /*! OCRAM_RDATA_WAIT_EN - Read Data Wait Enable */
49312 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_MASK)
49313 
49314 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_MASK (0x2U)
49315 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_SHIFT (1U)
49316 /*! OCRAM_RADDR_PIPELINE_EN - Read Address Pipeline Enable */
49317 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_MASK)
49318 
49319 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_MASK (0x4U)
49320 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_SHIFT (2U)
49321 /*! OCRAM_WRDATA_PIPELINE_EN - Write Data Pipeline Enable */
49322 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_MASK)
49323 
49324 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_MASK (0x8U)
49325 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_SHIFT (3U)
49326 /*! OCRAM_WRADDR_PIPELINE_EN - Write Address Pipeline Enable */
49327 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_MASK)
49328 
49329 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK   (0x10U)
49330 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_SHIFT  (4U)
49331 /*! OCRAM_ECC_EN - OCRAM ECC enable */
49332 #define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN(x)     (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK)
49333 
49334 #define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK     (0x20U)
49335 #define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_SHIFT    (5U)
49336 /*! TCM_ECC_EN - TCM ECC enable */
49337 #define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN(x)       (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK)
49338 
49339 #define FLEXRAM_FLEXRAM_CTRL_Reserved_MASK       (0xFFFFFFC0U)
49340 #define FLEXRAM_FLEXRAM_CTRL_Reserved_SHIFT      (6U)
49341 /*! Reserved - Reserved */
49342 #define FLEXRAM_FLEXRAM_CTRL_Reserved(x)         (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_Reserved_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_Reserved_MASK)
49343 /*! @} */
49344 
49345 /*! @name OCRAM_PIPELINE_STATUS - OCRAM Pipeline Status register */
49346 /*! @{ */
49347 
49348 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_MASK (0x1U)
49349 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_SHIFT (0U)
49350 /*! OCRAM_RDATA_WAIT_EN_UPDATA_PENDING - Read Data Wait Enable Pending */
49351 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_MASK)
49352 
49353 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_MASK (0x2U)
49354 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT (1U)
49355 /*! OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING - Read Address Pipeline Enable Pending */
49356 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_MASK)
49357 
49358 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_MASK (0x4U)
49359 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_SHIFT (2U)
49360 /*! OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING - Write Data Pipeline Enable Pending */
49361 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_MASK)
49362 
49363 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_MASK (0x8U)
49364 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT (3U)
49365 /*! OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING - Write Address Pipeline Enable Pending */
49366 #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_MASK)
49367 
49368 #define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_MASK (0xFFFFFFF0U)
49369 #define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_SHIFT (4U)
49370 /*! Reserved - Reserved */
49371 #define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_MASK)
49372 /*! @} */
49373 
49374 
49375 /*!
49376  * @}
49377  */ /* end of group FLEXRAM_Register_Masks */
49378 
49379 
49380 /* FLEXRAM - Peripheral instance base addresses */
49381 /** Peripheral FLEXRAM base address */
49382 #define FLEXRAM_BASE                             (0x40028000u)
49383 /** Peripheral FLEXRAM base pointer */
49384 #define FLEXRAM                                  ((FLEXRAM_Type *)FLEXRAM_BASE)
49385 /** Array initializer of FLEXRAM peripheral base addresses */
49386 #define FLEXRAM_BASE_ADDRS                       { FLEXRAM_BASE }
49387 /** Array initializer of FLEXRAM peripheral base pointers */
49388 #define FLEXRAM_BASE_PTRS                        { FLEXRAM }
49389 /** Interrupt vectors for the FLEXRAM peripheral type */
49390 #define FLEXRAM_IRQS                             { FLEXRAM_IRQn }
49391 #define FLEXRAM_ECC_IRQS                         { FLEXRAM_ECC_IRQn }
49392 
49393 /*!
49394  * @}
49395  */ /* end of group FLEXRAM_Peripheral_Access_Layer */
49396 
49397 
49398 /* ----------------------------------------------------------------------------
49399    -- FLEXSPI Peripheral Access Layer
49400    ---------------------------------------------------------------------------- */
49401 
49402 /*!
49403  * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
49404  * @{
49405  */
49406 
49407 /** FLEXSPI - Register Layout Typedef */
49408 typedef struct {
49409   __IO uint32_t MCR0;                              /**< Module Control 0, offset: 0x0 */
49410   __IO uint32_t MCR1;                              /**< Module Control 1, offset: 0x4 */
49411   __IO uint32_t MCR2;                              /**< Module Control 2, offset: 0x8 */
49412   __IO uint32_t AHBCR;                             /**< AHB Bus Control, offset: 0xC */
49413   __IO uint32_t INTEN;                             /**< Interrupt Enable, offset: 0x10 */
49414   __IO uint32_t INTR;                              /**< Interrupt, offset: 0x14 */
49415   __IO uint32_t LUTKEY;                            /**< LUT Key, offset: 0x18 */
49416   __IO uint32_t LUTCR;                             /**< LUT Control, offset: 0x1C */
49417   __IO uint32_t AHBRXBUFCR0[8];                    /**< AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0, array offset: 0x20, array step: 0x4 */
49418        uint8_t RESERVED_0[32];
49419   __IO uint32_t FLSHCR0[4];                        /**< Flash Control 0, array offset: 0x60, array step: 0x4 */
49420   __IO uint32_t FLSHCR1[4];                        /**< Flash Control 1, array offset: 0x70, array step: 0x4 */
49421   __IO uint32_t FLSHCR2[4];                        /**< Flash Control 2, array offset: 0x80, array step: 0x4 */
49422        uint8_t RESERVED_1[4];
49423   __IO uint32_t FLSHCR4;                           /**< Flash Control 4, offset: 0x94 */
49424        uint8_t RESERVED_2[8];
49425   __IO uint32_t IPCR0;                             /**< IP Control 0, offset: 0xA0 */
49426   __IO uint32_t IPCR1;                             /**< IP Control 1, offset: 0xA4 */
49427        uint8_t RESERVED_3[8];
49428   __O  uint32_t IPCMD;                             /**< IP Command, offset: 0xB0 */
49429        uint8_t RESERVED_4[4];
49430   __IO uint32_t IPRXFCR;                           /**< IP Receive FIFO Control, offset: 0xB8 */
49431   __IO uint32_t IPTXFCR;                           /**< IP Transmit FIFO Control, offset: 0xBC */
49432   __IO uint32_t DLLCR[2];                          /**< DLL Control 0, array offset: 0xC0, array step: 0x4 */
49433        uint8_t RESERVED_5[8];
49434   __I  uint32_t MISCCR4;                           /**< Misc Control 4, offset: 0xD0 */
49435   __I  uint32_t MISCCR5;                           /**< Miscellaneous Control 5, offset: 0xD4 */
49436   __I  uint32_t MISCCR6;                           /**< Miscellaneous Control 6, offset: 0xD8 */
49437   __I  uint32_t MISCCR7;                           /**< Miscellaneous Control 7, offset: 0xDC */
49438   __I  uint32_t STS0;                              /**< Status 0, offset: 0xE0 */
49439   __I  uint32_t STS1;                              /**< Status 1, offset: 0xE4 */
49440   __I  uint32_t STS2;                              /**< Status 2, offset: 0xE8 */
49441   __I  uint32_t AHBSPNDSTS;                        /**< AHB Suspend Status, offset: 0xEC */
49442   __I  uint32_t IPRXFSTS;                          /**< IP Receive FIFO Status, offset: 0xF0 */
49443   __I  uint32_t IPTXFSTS;                          /**< IP Transmit FIFO Status, offset: 0xF4 */
49444        uint8_t RESERVED_6[8];
49445   __I  uint32_t RFDR[32];                          /**< IP Receive FIFO Data 0..IP Receive FIFO Data 31, array offset: 0x100, array step: 0x4 */
49446   __O  uint32_t TFDR[32];                          /**< IP TX FIFO Data 0..IP TX FIFO Data 31, array offset: 0x180, array step: 0x4 */
49447   __IO uint32_t LUT[64];                           /**< Lookup Table 0..Lookup Table 63, array offset: 0x200, array step: 0x4 */
49448        uint8_t RESERVED_7[256];
49449   __IO uint32_t HMSTRCR[8];                        /**< AHB Controller ID 0 Control..AHB Controller ID 7 Control, array offset: 0x400, array step: 0x4 */
49450   __IO uint32_t HADDRSTART;                        /**< HADDR REMAP Start Address, offset: 0x420 */
49451   __IO uint32_t HADDREND;                          /**< HADDR REMAP END ADDR, offset: 0x424 */
49452   __IO uint32_t HADDROFFSET;                       /**< HADDR Remap Offset, offset: 0x428 */
49453 } FLEXSPI_Type;
49454 
49455 /* ----------------------------------------------------------------------------
49456    -- FLEXSPI Register Masks
49457    ---------------------------------------------------------------------------- */
49458 
49459 /*!
49460  * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
49461  * @{
49462  */
49463 
49464 /*! @name MCR0 - Module Control 0 */
49465 /*! @{ */
49466 
49467 #define FLEXSPI_MCR0_SWRESET_MASK                (0x1U)
49468 #define FLEXSPI_MCR0_SWRESET_SHIFT               (0U)
49469 /*! SWRESET - Software Reset
49470  *  0b0..No impact
49471  *  0b1..Software reset
49472  */
49473 #define FLEXSPI_MCR0_SWRESET(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
49474 
49475 #define FLEXSPI_MCR0_MDIS_MASK                   (0x2U)
49476 #define FLEXSPI_MCR0_MDIS_SHIFT                  (1U)
49477 /*! MDIS - Module Disable
49478  *  0b0..No impact
49479  *  0b1..Module disable
49480  */
49481 #define FLEXSPI_MCR0_MDIS(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
49482 
49483 #define FLEXSPI_MCR0_RXCLKSRC_MASK               (0x30U)
49484 #define FLEXSPI_MCR0_RXCLKSRC_SHIFT              (4U)
49485 /*! RXCLKSRC - Sample Clock Source for Flash Reading
49486  *  0b00..Dummy Read strobe that FlexSPI generates, looped back internally
49487  *  0b01..Dummy Read strobe that FlexSPI generates, looped back from DQS pad
49488  *  0b10..Reserved
49489  *  0b11..Flash-memory-provided read strobe and input from DQS pad
49490  */
49491 #define FLEXSPI_MCR0_RXCLKSRC(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
49492 
49493 #define FLEXSPI_MCR0_ARDFEN_MASK                 (0x40U)
49494 #define FLEXSPI_MCR0_ARDFEN_SHIFT                (6U)
49495 /*! ARDFEN - AHB Read Access to IP Receive FIFO Enable
49496  *  0b0..AHB read access disabled. IP bus reads IP receive FIFO. AHB Bus read access to IP receive FIFO memory space produces bus error.
49497  *  0b1..AHB read access enabled. AHB bus reads IP receive FIFO. IP Bus read access to IP receive FIFO memory
49498  *       space returns data zero and causes no bus error.
49499  */
49500 #define FLEXSPI_MCR0_ARDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
49501 
49502 #define FLEXSPI_MCR0_ATDFEN_MASK                 (0x80U)
49503 #define FLEXSPI_MCR0_ATDFEN_SHIFT                (7U)
49504 /*! ATDFEN - AHB Write Access to IP Transmit FIFO Enable
49505  *  0b0..AHB write access disabled. IP bus writes to IP transmit FIFO. AHB bus write access to IP transmit FIFO memory space produces bus error.
49506  *  0b1..AHB write access enabled. AHB bus writes to IP transmit FIFO. IP Bus write access to IP transmit FIFO
49507  *       memory space is ignored and causes no bus error.
49508  */
49509 #define FLEXSPI_MCR0_ATDFEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
49510 
49511 #define FLEXSPI_MCR0_SERCLKDIV_MASK              (0x700U)
49512 #define FLEXSPI_MCR0_SERCLKDIV_SHIFT             (8U)
49513 /*! SERCLKDIV - Serial Root Clock Divider
49514  *  0b000..Divided by 1
49515  *  0b001..Divided by 2
49516  *  0b010..Divided by 3
49517  *  0b011..Divided by 4
49518  *  0b100..Divided by 5
49519  *  0b101..Divided by 6
49520  *  0b110..Divided by 7
49521  *  0b111..Divided by 8
49522  */
49523 #define FLEXSPI_MCR0_SERCLKDIV(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
49524 
49525 #define FLEXSPI_MCR0_HSEN_MASK                   (0x800U)
49526 #define FLEXSPI_MCR0_HSEN_SHIFT                  (11U)
49527 /*! HSEN - Half Speed Serial Flash Memory Access Enable
49528  *  0b0..Disable
49529  *  0b1..Enable
49530  */
49531 #define FLEXSPI_MCR0_HSEN(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
49532 
49533 #define FLEXSPI_MCR0_DOZEEN_MASK                 (0x1000U)
49534 #define FLEXSPI_MCR0_DOZEEN_SHIFT                (12U)
49535 /*! DOZEEN - Doze Mode Enable
49536  *  0b0..Disable
49537  *  0b1..Enable
49538  */
49539 #define FLEXSPI_MCR0_DOZEEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
49540 
49541 #define FLEXSPI_MCR0_COMBINATIONEN_MASK          (0x2000U)
49542 #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT         (13U)
49543 /*! COMBINATIONEN - Combination Mode Enable
49544  *  0b0..Disable
49545  *  0b1..Enable
49546  */
49547 #define FLEXSPI_MCR0_COMBINATIONEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
49548 
49549 #define FLEXSPI_MCR0_SCKFREERUNEN_MASK           (0x4000U)
49550 #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT          (14U)
49551 /*! SCKFREERUNEN - SCLK Free-running Enable
49552  *  0b0..Disable
49553  *  0b1..Enable
49554  */
49555 #define FLEXSPI_MCR0_SCKFREERUNEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
49556 
49557 #define FLEXSPI_MCR0_IPGRANTWAIT_MASK            (0xFF0000U)
49558 #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT           (16U)
49559 /*! IPGRANTWAIT - Timeout Wait Cycle for IP Command Grant */
49560 #define FLEXSPI_MCR0_IPGRANTWAIT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
49561 
49562 #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK           (0xFF000000U)
49563 #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT          (24U)
49564 /*! AHBGRANTWAIT - Timeouts Wait Cycle for AHB command Grant */
49565 #define FLEXSPI_MCR0_AHBGRANTWAIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
49566 /*! @} */
49567 
49568 /*! @name MCR1 - Module Control 1 */
49569 /*! @{ */
49570 
49571 #define FLEXSPI_MCR1_AHBBUSWAIT_MASK             (0xFFFFU)
49572 #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT            (0U)
49573 /*! AHBBUSWAIT - AHB Bus Wait */
49574 #define FLEXSPI_MCR1_AHBBUSWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
49575 
49576 #define FLEXSPI_MCR1_SEQWAIT_MASK                (0xFFFF0000U)
49577 #define FLEXSPI_MCR1_SEQWAIT_SHIFT               (16U)
49578 /*! SEQWAIT - Command Sequence Wait */
49579 #define FLEXSPI_MCR1_SEQWAIT(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
49580 /*! @} */
49581 
49582 /*! @name MCR2 - Module Control 2 */
49583 /*! @{ */
49584 
49585 #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK           (0x800U)
49586 #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT          (11U)
49587 /*! CLRAHBBUFOPT - Clear AHB Buffer
49588  *  0b0..Not cleared automatically
49589  *  0b1..Cleared automatically
49590  */
49591 #define FLEXSPI_MCR2_CLRAHBBUFOPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
49592 
49593 #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK           (0x8000U)
49594 #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT          (15U)
49595 /*! SAMEDEVICEEN - Same Device Enable
49596  *  0b0..In Individual mode, FLSHA1CRx and FLSHA2CRx, FLSHB1CRx and FLSHB2CRx settings are applied to Flash A1,
49597  *       A2, B1, B2 separately. In Parallel mode, FLSHA1CRx register setting is applied to Flash A1 and B1, FLSHA2CRx
49598  *       register setting is applied to Flash A2 and B2. FLSHB1CRx and FLSHB2CRx register settings are ignored.
49599  *  0b1..FLSHA1CR0, FLSHA1CR1, and FLSHA1CR2 register settings are applied to Flash A1, A2, B1, B2. FLSHA2CRx,
49600  *       FLSHB1CRx, and FLSHB2CRx settings are ignored.
49601  */
49602 #define FLEXSPI_MCR2_SAMEDEVICEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
49603 
49604 #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK            (0x80000U)
49605 #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT           (19U)
49606 /*! SCKBDIFFOPT - SCLK Port B Differential Output
49607  *  0b1..Use B_SCLK pad as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash memory access is not available.
49608  *  0b0..Use B_SCLK pad as port B SCLK clock output. Port B flash memory access is available.
49609  */
49610 #define FLEXSPI_MCR2_SCKBDIFFOPT(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
49611 
49612 #define FLEXSPI_MCR2_RESUMEWAIT_MASK             (0xFF000000U)
49613 #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT            (24U)
49614 /*! RESUMEWAIT - Resume Wait Duration */
49615 #define FLEXSPI_MCR2_RESUMEWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
49616 /*! @} */
49617 
49618 /*! @name AHBCR - AHB Bus Control */
49619 /*! @{ */
49620 
49621 #define FLEXSPI_AHBCR_APAREN_MASK                (0x1U)
49622 #define FLEXSPI_AHBCR_APAREN_SHIFT               (0U)
49623 /*! APAREN - AHB Parallel Mode Enable
49624  *  0b0..Flash is accessed in Individual mode.
49625  *  0b1..Flash is accessed in Parallel mode.
49626  */
49627 #define FLEXSPI_AHBCR_APAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
49628 
49629 #define FLEXSPI_AHBCR_CLRAHBRXBUF_MASK           (0x2U)
49630 #define FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT          (1U)
49631 /*! CLRAHBRXBUF - Clear AHB Receive Buffer
49632  *  0b0..No impact.
49633  *  0b1..Enable clear operation.
49634  */
49635 #define FLEXSPI_AHBCR_CLRAHBRXBUF(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK)
49636 
49637 #define FLEXSPI_AHBCR_CACHABLEEN_MASK            (0x8U)
49638 #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT           (3U)
49639 /*! CACHABLEEN - Cacheable Read Access Enable
49640  *  0b0..Disabled. When an AHB bus cacheable read access occurs, FlexSPI does not check whether it hit the AHB transmit buffer.
49641  *  0b1..Enabled. When an AHB bus cacheable read access occurs, FlexSPI first checks whether the access hit the AHB transmit buffer.
49642  */
49643 #define FLEXSPI_AHBCR_CACHABLEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
49644 
49645 #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK          (0x10U)
49646 #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT         (4U)
49647 /*! BUFFERABLEEN - Bufferable Write Access Enable
49648  *  0b0..Disabled. For all AHB write accesses (bufferable or nonbufferable), FlexSPI returns AHB Bus Ready after
49649  *       transmitting all data and finishing command.
49650  *  0b1..Enabled. For AHB bufferable write access, FlexSPI returns AHB Bus Ready when the arbitrator grants the
49651  *       AHB command. FlexSPI does not wait for the AHB command to finish.
49652  */
49653 #define FLEXSPI_AHBCR_BUFFERABLEEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
49654 
49655 #define FLEXSPI_AHBCR_PREFETCHEN_MASK            (0x20U)
49656 #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT           (5U)
49657 /*! PREFETCHEN - AHB Read Prefetch Enable
49658  *  0b0..Disable
49659  *  0b1..Enable
49660  */
49661 #define FLEXSPI_AHBCR_PREFETCHEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
49662 
49663 #define FLEXSPI_AHBCR_READADDROPT_MASK           (0x40U)
49664 #define FLEXSPI_AHBCR_READADDROPT_SHIFT          (6U)
49665 /*! READADDROPT - AHB Read Address Option
49666  *  0b0..AHB read burst start address alignment is limited when flash memory is accessed in parallel mode or flash is word-addressable.
49667  *  0b1..AHB read burst start address alignment is not limited. FlexSPI fetches more data than the AHB burst requires for address alignment.
49668  */
49669 #define FLEXSPI_AHBCR_READADDROPT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
49670 
49671 #define FLEXSPI_AHBCR_READSZALIGN_MASK           (0x400U)
49672 #define FLEXSPI_AHBCR_READSZALIGN_SHIFT          (10U)
49673 /*! READSZALIGN - AHB Read Size Alignment
49674  *  0b0..Register settings such as PREFETCH_EN and OTFAD_EN determine AHB read size.
49675  *  0b1..AHB read size to up size to 8 bytes aligned, no prefetching
49676  */
49677 #define FLEXSPI_AHBCR_READSZALIGN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK)
49678 
49679 #define FLEXSPI_AHBCR_ECCEN_MASK                 (0x800U)
49680 #define FLEXSPI_AHBCR_ECCEN_SHIFT                (11U)
49681 /*! ECCEN - AHB Read ECC Enable
49682  *  0b0..Disable
49683  *  0b1..Enable
49684  */
49685 #define FLEXSPI_AHBCR_ECCEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCEN_SHIFT)) & FLEXSPI_AHBCR_ECCEN_MASK)
49686 
49687 #define FLEXSPI_AHBCR_SPLITEN_MASK               (0x1000U)
49688 #define FLEXSPI_AHBCR_SPLITEN_SHIFT              (12U)
49689 /*! SPLITEN - AHB Transaction Split Enable
49690  *  0b0..Disable
49691  *  0b1..Enable
49692  */
49693 #define FLEXSPI_AHBCR_SPLITEN(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLITEN_SHIFT)) & FLEXSPI_AHBCR_SPLITEN_MASK)
49694 
49695 #define FLEXSPI_AHBCR_SPLIT_LIMIT_MASK           (0x6000U)
49696 #define FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT          (13U)
49697 /*! SPLIT_LIMIT - AHB Split Limit Size
49698  *  0b00..8 bytes
49699  *  0b01..16 bytes
49700  *  0b10..32 bytes
49701  *  0b11..64 bytes
49702  */
49703 #define FLEXSPI_AHBCR_SPLIT_LIMIT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT)) & FLEXSPI_AHBCR_SPLIT_LIMIT_MASK)
49704 
49705 #define FLEXSPI_AHBCR_KEYECCEN_MASK              (0x8000U)
49706 #define FLEXSPI_AHBCR_KEYECCEN_SHIFT             (15U)
49707 /*! KEYECCEN - OTFAD Key Blob ECC Enable
49708  *  0b0..Disable
49709  *  0b1..Enable
49710  */
49711 #define FLEXSPI_AHBCR_KEYECCEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_KEYECCEN_SHIFT)) & FLEXSPI_AHBCR_KEYECCEN_MASK)
49712 
49713 #define FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK       (0x10000U)
49714 #define FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT      (16U)
49715 /*! ECCSINGLEERRCLR - AHB ECC Single-Bit Error Clear
49716  *  0b0..No function
49717  *  0b1..Clear
49718  */
49719 #define FLEXSPI_AHBCR_ECCSINGLEERRCLR(x)         (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK)
49720 
49721 #define FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK        (0x20000U)
49722 #define FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT       (17U)
49723 /*! ECCMULTIERRCLR - AHB ECC Multibit Error Clear
49724  *  0b0..No function
49725  *  0b1..Clear
49726  */
49727 #define FLEXSPI_AHBCR_ECCMULTIERRCLR(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK)
49728 
49729 #define FLEXSPI_AHBCR_HMSTRIDREMAP_MASK          (0x40000U)
49730 #define FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT         (18U)
49731 /*! HMSTRIDREMAP - AHB Controller ID Remapping Enable
49732  *  0b0..Disable
49733  *  0b1..Enable
49734  */
49735 #define FLEXSPI_AHBCR_HMSTRIDREMAP(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT)) & FLEXSPI_AHBCR_HMSTRIDREMAP_MASK)
49736 
49737 #define FLEXSPI_AHBCR_ECCSWAPEN_MASK             (0x80000U)
49738 #define FLEXSPI_AHBCR_ECCSWAPEN_SHIFT            (19U)
49739 /*! ECCSWAPEN - ECC Read Data Swap Enable
49740  *  0b0..Disable
49741  *  0b1..Enable
49742  */
49743 #define FLEXSPI_AHBCR_ECCSWAPEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSWAPEN_SHIFT)) & FLEXSPI_AHBCR_ECCSWAPEN_MASK)
49744 /*! @} */
49745 
49746 /*! @name INTEN - Interrupt Enable */
49747 /*! @{ */
49748 
49749 #define FLEXSPI_INTEN_IPCMDDONEEN_MASK           (0x1U)
49750 #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT          (0U)
49751 /*! IPCMDDONEEN - IP-Triggered Command Sequences Execution Finished Interrupt Enable
49752  *  0b0..Disable interrupt or no impact
49753  *  0b1..Enable interrupt
49754  */
49755 #define FLEXSPI_INTEN_IPCMDDONEEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
49756 
49757 #define FLEXSPI_INTEN_IPCMDGEEN_MASK             (0x2U)
49758 #define FLEXSPI_INTEN_IPCMDGEEN_SHIFT            (1U)
49759 /*! IPCMDGEEN - IP-Triggered Command Sequences Grant Timeout Interrupt Enable
49760  *  0b0..Disable interrupt or no impact
49761  *  0b1..Enable interrupt
49762  */
49763 #define FLEXSPI_INTEN_IPCMDGEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
49764 
49765 #define FLEXSPI_INTEN_AHBCMDGEEN_MASK            (0x4U)
49766 #define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT           (2U)
49767 /*! AHBCMDGEEN - AHB-Triggered Command Sequences Grant Timeout Interrupt Enable.
49768  *  0b0..Disable interrupt or no impact
49769  *  0b1..Enable interrupt
49770  */
49771 #define FLEXSPI_INTEN_AHBCMDGEEN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
49772 
49773 #define FLEXSPI_INTEN_IPCMDERREN_MASK            (0x8U)
49774 #define FLEXSPI_INTEN_IPCMDERREN_SHIFT           (3U)
49775 /*! IPCMDERREN - IP-Triggered Command Sequences Error Detected Interrupt Enable
49776  *  0b0..Disable interrupt or no impact
49777  *  0b1..Enable interrupt
49778  */
49779 #define FLEXSPI_INTEN_IPCMDERREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
49780 
49781 #define FLEXSPI_INTEN_AHBCMDERREN_MASK           (0x10U)
49782 #define FLEXSPI_INTEN_AHBCMDERREN_SHIFT          (4U)
49783 /*! AHBCMDERREN - AHB-Triggered Command Sequences Error Detected Interrupt Enable
49784  *  0b0..Disable interrupt or no impact
49785  *  0b1..Enable interrupt
49786  */
49787 #define FLEXSPI_INTEN_AHBCMDERREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
49788 
49789 #define FLEXSPI_INTEN_IPRXWAEN_MASK              (0x20U)
49790 #define FLEXSPI_INTEN_IPRXWAEN_SHIFT             (5U)
49791 /*! IPRXWAEN - IP Receive FIFO Watermark Available Interrupt Enable
49792  *  0b0..Disable interrupt or no impact
49793  *  0b1..Enable interrupt
49794  */
49795 #define FLEXSPI_INTEN_IPRXWAEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
49796 
49797 #define FLEXSPI_INTEN_IPTXWEEN_MASK              (0x40U)
49798 #define FLEXSPI_INTEN_IPTXWEEN_SHIFT             (6U)
49799 /*! IPTXWEEN - IP Transmit FIFO Watermark Empty Interrupt Enable
49800  *  0b0..Disable interrupt or no impact
49801  *  0b1..Enable interrupt
49802  */
49803 #define FLEXSPI_INTEN_IPTXWEEN(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
49804 
49805 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK         (0x100U)
49806 #define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT        (8U)
49807 /*! SCKSTOPBYRDEN - SCLK Stopped By Read Interrupt Enable
49808  *  0b0..Disable interrupt or no impact
49809  *  0b1..Enable interrupt
49810  */
49811 #define FLEXSPI_INTEN_SCKSTOPBYRDEN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
49812 
49813 #define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK         (0x200U)
49814 #define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT        (9U)
49815 /*! SCKSTOPBYWREN - SCLK Stopped By Write Interrupt Enable
49816  *  0b0..Disable interrupt or no impact
49817  *  0b1..Enable interrupt
49818  */
49819 #define FLEXSPI_INTEN_SCKSTOPBYWREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
49820 
49821 #define FLEXSPI_INTEN_AHBBUSERROREN_MASK         (0x400U)
49822 #define FLEXSPI_INTEN_AHBBUSERROREN_SHIFT        (10U)
49823 /*! AHBBUSERROREN - AHB Bus Error Interrupt Enable
49824  *  0b0..Disable interrupt or no impact
49825  *  0b1..Enable interrupt
49826  */
49827 #define FLEXSPI_INTEN_AHBBUSERROREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK)
49828 
49829 #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK          (0x800U)
49830 #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT         (11U)
49831 /*! SEQTIMEOUTEN - Sequence execution Timeout Interrupt Enable
49832  *  0b0..Disable interrupt or no impact
49833  *  0b1..Enable interrupt
49834  */
49835 #define FLEXSPI_INTEN_SEQTIMEOUTEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
49836 
49837 #define FLEXSPI_INTEN_KEYDONEEN_MASK             (0x1000U)
49838 #define FLEXSPI_INTEN_KEYDONEEN_SHIFT            (12U)
49839 /*! KEYDONEEN - OTFAD Key Blob Processing Done Interrupt Enable
49840  *  0b0..Disable interrupt or no impact
49841  *  0b1..Enable interrupt
49842  */
49843 #define FLEXSPI_INTEN_KEYDONEEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK)
49844 
49845 #define FLEXSPI_INTEN_KEYERROREN_MASK            (0x2000U)
49846 #define FLEXSPI_INTEN_KEYERROREN_SHIFT           (13U)
49847 /*! KEYERROREN - OTFAD Key Blob Processing Error Interrupt Enable
49848  *  0b0..Disable interrupt or no impact
49849  *  0b1..Enable interrupt
49850  */
49851 #define FLEXSPI_INTEN_KEYERROREN(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK)
49852 
49853 #define FLEXSPI_INTEN_ECCMULTIERREN_MASK         (0x4000U)
49854 #define FLEXSPI_INTEN_ECCMULTIERREN_SHIFT        (14U)
49855 /*! ECCMULTIERREN - ECC Multibit Error Interrupt Enable
49856  *  0b0..Disable interrupt or no impact
49857  *  0b1..Enable interrupt
49858  */
49859 #define FLEXSPI_INTEN_ECCMULTIERREN(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCMULTIERREN_SHIFT)) & FLEXSPI_INTEN_ECCMULTIERREN_MASK)
49860 
49861 #define FLEXSPI_INTEN_ECCSINGLEERREN_MASK        (0x8000U)
49862 #define FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT       (15U)
49863 /*! ECCSINGLEERREN - ECC Single-Bit Error Interrupt Enable
49864  *  0b0..Disable interrupt or no impact
49865  *  0b1..Enable interrupt
49866  */
49867 #define FLEXSPI_INTEN_ECCSINGLEERREN(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT)) & FLEXSPI_INTEN_ECCSINGLEERREN_MASK)
49868 /*! @} */
49869 
49870 /*! @name INTR - Interrupt */
49871 /*! @{ */
49872 
49873 #define FLEXSPI_INTR_IPCMDDONE_MASK              (0x1U)
49874 #define FLEXSPI_INTR_IPCMDDONE_SHIFT             (0U)
49875 /*! IPCMDDONE - IP-Triggered Command Sequences Execution Finished
49876  *  0b0..Interrupt condition has not occurred
49877  *  0b1..Interrupt condition has occurred
49878  *  0b0..No effect
49879  *  0b1..Clear the flag
49880  */
49881 #define FLEXSPI_INTR_IPCMDDONE(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
49882 
49883 #define FLEXSPI_INTR_IPCMDGE_MASK                (0x2U)
49884 #define FLEXSPI_INTR_IPCMDGE_SHIFT               (1U)
49885 /*! IPCMDGE - IP-Triggered Command Sequences Grant Timeout
49886  *  0b0..Interrupt condition has not occurred
49887  *  0b1..Interrupt condition has occurred
49888  *  0b0..No effect
49889  *  0b1..Clear the flag
49890  */
49891 #define FLEXSPI_INTR_IPCMDGE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
49892 
49893 #define FLEXSPI_INTR_AHBCMDGE_MASK               (0x4U)
49894 #define FLEXSPI_INTR_AHBCMDGE_SHIFT              (2U)
49895 /*! AHBCMDGE - AHB-Triggered Command Sequences Grant Timeout
49896  *  0b0..Interrupt condition has not occurred
49897  *  0b1..Interrupt condition has occurred
49898  *  0b0..No effect
49899  *  0b1..Clear the flag
49900  */
49901 #define FLEXSPI_INTR_AHBCMDGE(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
49902 
49903 #define FLEXSPI_INTR_IPCMDERR_MASK               (0x8U)
49904 #define FLEXSPI_INTR_IPCMDERR_SHIFT              (3U)
49905 /*! IPCMDERR - IP-Triggered Command Sequences Error
49906  *  0b0..Interrupt condition has not occurred
49907  *  0b1..Interrupt condition has occurred
49908  *  0b0..No effect
49909  *  0b1..Clear the flag
49910  */
49911 #define FLEXSPI_INTR_IPCMDERR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
49912 
49913 #define FLEXSPI_INTR_AHBCMDERR_MASK              (0x10U)
49914 #define FLEXSPI_INTR_AHBCMDERR_SHIFT             (4U)
49915 /*! AHBCMDERR - AHB-Triggered Command Sequences Error
49916  *  0b0..Interrupt condition has not occurred
49917  *  0b1..Interrupt condition has occurred
49918  *  0b0..No effect
49919  *  0b1..Clear the flag
49920  */
49921 #define FLEXSPI_INTR_AHBCMDERR(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
49922 
49923 #define FLEXSPI_INTR_IPRXWA_MASK                 (0x20U)
49924 #define FLEXSPI_INTR_IPRXWA_SHIFT                (5U)
49925 /*! IPRXWA - IP Receive FIFO Watermark Available
49926  *  0b0..Interrupt condition has not occurred
49927  *  0b1..Interrupt condition has occurred
49928  *  0b0..No effect
49929  *  0b1..Clear the flag
49930  */
49931 #define FLEXSPI_INTR_IPRXWA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
49932 
49933 #define FLEXSPI_INTR_IPTXWE_MASK                 (0x40U)
49934 #define FLEXSPI_INTR_IPTXWE_SHIFT                (6U)
49935 /*! IPTXWE - IP Transmit FIFO Watermark Empty
49936  *  0b0..Interrupt condition has not occurred
49937  *  0b1..Interrupt condition has occurred
49938  *  0b0..No effect
49939  *  0b1..Clear the flag
49940  */
49941 #define FLEXSPI_INTR_IPTXWE(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
49942 
49943 #define FLEXSPI_INTR_SCKSTOPBYRD_MASK            (0x100U)
49944 #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT           (8U)
49945 /*! SCKSTOPBYRD - SCLK Stopped Due To Full Receive FIFO
49946  *  0b0..Interrupt condition has not occurred
49947  *  0b1..Interrupt condition has occurred
49948  *  0b0..No effect
49949  *  0b1..Clear the flag
49950  */
49951 #define FLEXSPI_INTR_SCKSTOPBYRD(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
49952 
49953 #define FLEXSPI_INTR_SCKSTOPBYWR_MASK            (0x200U)
49954 #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT           (9U)
49955 /*! SCKSTOPBYWR - SCLK Stopped Due To Empty Transmit FIFO
49956  *  0b0..Interrupt condition has not occurred
49957  *  0b1..Interrupt condition has occurred
49958  *  0b0..No effect
49959  *  0b1..Clear the flag
49960  */
49961 #define FLEXSPI_INTR_SCKSTOPBYWR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
49962 
49963 #define FLEXSPI_INTR_AHBBUSERROR_MASK            (0x400U)
49964 #define FLEXSPI_INTR_AHBBUSERROR_SHIFT           (10U)
49965 /*! AHBBUSERROR - AHB Bus Error
49966  *  0b0..Interrupt condition has not occurred
49967  *  0b1..Interrupt condition has occurred
49968  *  0b0..No effect
49969  *  0b1..Clear the flag
49970  */
49971 #define FLEXSPI_INTR_AHBBUSERROR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK)
49972 
49973 #define FLEXSPI_INTR_SEQTIMEOUT_MASK             (0x800U)
49974 #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT            (11U)
49975 /*! SEQTIMEOUT - Sequence Execution Timeout
49976  *  0b0..Interrupt condition has not occurred
49977  *  0b1..Interrupt condition has occurred
49978  *  0b0..No effect
49979  *  0b1..Clear the flag
49980  */
49981 #define FLEXSPI_INTR_SEQTIMEOUT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
49982 
49983 #define FLEXSPI_INTR_KEYDONE_MASK                (0x1000U)
49984 #define FLEXSPI_INTR_KEYDONE_SHIFT               (12U)
49985 /*! KEYDONE - OTFAD key blob processing done interrupt. */
49986 #define FLEXSPI_INTR_KEYDONE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK)
49987 
49988 #define FLEXSPI_INTR_KEYERROR_MASK               (0x2000U)
49989 #define FLEXSPI_INTR_KEYERROR_SHIFT              (13U)
49990 /*! KEYERROR - OTFAD Key Blob Processing Error
49991  *  0b0..Interrupt condition has not occurred
49992  *  0b1..Interrupt condition has occurred
49993  *  0b0..No effect
49994  *  0b1..Clear the flag
49995  */
49996 #define FLEXSPI_INTR_KEYERROR(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK)
49997 
49998 #define FLEXSPI_INTR_ECCMULTIERR_MASK            (0x4000U)
49999 #define FLEXSPI_INTR_ECCMULTIERR_SHIFT           (14U)
50000 /*! ECCMULTIERR - ECC Multibit Error
50001  *  0b0..Interrupt condition has not occurred
50002  *  0b1..Interrupt condition has occurred
50003  *  0b0..No effect
50004  *  0b1..Clear the flag
50005  */
50006 #define FLEXSPI_INTR_ECCMULTIERR(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCMULTIERR_SHIFT)) & FLEXSPI_INTR_ECCMULTIERR_MASK)
50007 
50008 #define FLEXSPI_INTR_ECCSINGLEERR_MASK           (0x8000U)
50009 #define FLEXSPI_INTR_ECCSINGLEERR_SHIFT          (15U)
50010 /*! ECCSINGLEERR - ECC Single-Bit Error
50011  *  0b0..Interrupt condition has not occurred
50012  *  0b1..Interrupt condition has occurred
50013  *  0b0..No effect
50014  *  0b1..Clear the flag
50015  */
50016 #define FLEXSPI_INTR_ECCSINGLEERR(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCSINGLEERR_SHIFT)) & FLEXSPI_INTR_ECCSINGLEERR_MASK)
50017 /*! @} */
50018 
50019 /*! @name LUTKEY - LUT Key */
50020 /*! @{ */
50021 
50022 #define FLEXSPI_LUTKEY_KEY_MASK                  (0xFFFFFFFFU)
50023 #define FLEXSPI_LUTKEY_KEY_SHIFT                 (0U)
50024 /*! KEY - LUT Key */
50025 #define FLEXSPI_LUTKEY_KEY(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
50026 /*! @} */
50027 
50028 /*! @name LUTCR - LUT Control */
50029 /*! @{ */
50030 
50031 #define FLEXSPI_LUTCR_LOCK_MASK                  (0x1U)
50032 #define FLEXSPI_LUTCR_LOCK_SHIFT                 (0U)
50033 /*! LOCK - Lock LUT
50034  *  0b0..LUT is unlocked (LUTCR[UNLOCK] must be 1)
50035  *  0b1..LUT is locked and cannot be written
50036  */
50037 #define FLEXSPI_LUTCR_LOCK(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
50038 
50039 #define FLEXSPI_LUTCR_UNLOCK_MASK                (0x2U)
50040 #define FLEXSPI_LUTCR_UNLOCK_SHIFT               (1U)
50041 /*! UNLOCK - Unlock LUT
50042  *  0b0..LUT is locked (LUTCR[LOCK] must be 1)
50043  *  0b1..LUT is unlocked and can be written
50044  */
50045 #define FLEXSPI_LUTCR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
50046 /*! @} */
50047 
50048 /*! @name AHBRXBUFCR0 - AHB Receive Buffer 0 Control 0..AHB Receive Buffer 7 Control 0 */
50049 /*! @{ */
50050 
50051 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK           (0x3FFU)
50052 #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT          (0U)
50053 /*! BUFSZ - AHB Receive Buffer Size */
50054 #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
50055 
50056 #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK          (0xF0000U)
50057 #define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT         (16U)
50058 /*! MSTRID - AHB Controller ID */
50059 #define FLEXSPI_AHBRXBUFCR0_MSTRID(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
50060 
50061 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK        (0x7000000U)
50062 #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT       (24U)
50063 /*! PRIORITY - AHB Controller Read Priority */
50064 #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
50065 
50066 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK      (0x80000000U)
50067 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT     (31U)
50068 /*! PREFETCHEN - AHB Read Prefetch Enable
50069  *  0b0..Disabled
50070  *  0b1..Enabled when is enabled.
50071  */
50072 #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
50073 /*! @} */
50074 
50075 /* The count of FLEXSPI_AHBRXBUFCR0 */
50076 #define FLEXSPI_AHBRXBUFCR0_COUNT                (8U)
50077 
50078 /*! @name FLSHCR0 - Flash Control 0 */
50079 /*! @{ */
50080 
50081 #define FLEXSPI_FLSHCR0_FLSHSZ_MASK              (0x7FFFFFU)
50082 #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT             (0U)
50083 /*! FLSHSZ - Flash Size in KB */
50084 #define FLEXSPI_FLSHCR0_FLSHSZ(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
50085 
50086 #define FLEXSPI_FLSHCR0_SPLITWREN_MASK           (0x40000000U)
50087 #define FLEXSPI_FLSHCR0_SPLITWREN_SHIFT          (30U)
50088 /*! SPLITWREN - AHB Write Access Split Function Enable
50089  *  0b0..Disable
50090  *  0b1..Enable
50091  */
50092 #define FLEXSPI_FLSHCR0_SPLITWREN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK)
50093 
50094 #define FLEXSPI_FLSHCR0_SPLITRDEN_MASK           (0x80000000U)
50095 #define FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT          (31U)
50096 /*! SPLITRDEN - AHB Read Access Split Function Enable
50097  *  0b0..Disable
50098  *  0b1..Enable
50099  */
50100 #define FLEXSPI_FLSHCR0_SPLITRDEN(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK)
50101 /*! @} */
50102 
50103 /* The count of FLEXSPI_FLSHCR0 */
50104 #define FLEXSPI_FLSHCR0_COUNT                    (4U)
50105 
50106 /*! @name FLSHCR1 - Flash Control 1 */
50107 /*! @{ */
50108 
50109 #define FLEXSPI_FLSHCR1_TCSS_MASK                (0x1FU)
50110 #define FLEXSPI_FLSHCR1_TCSS_SHIFT               (0U)
50111 /*! TCSS - Serial Flash CS Setup Time */
50112 #define FLEXSPI_FLSHCR1_TCSS(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
50113 
50114 #define FLEXSPI_FLSHCR1_TCSH_MASK                (0x3E0U)
50115 #define FLEXSPI_FLSHCR1_TCSH_SHIFT               (5U)
50116 /*! TCSH - Serial Flash CS Hold Time */
50117 #define FLEXSPI_FLSHCR1_TCSH(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
50118 
50119 #define FLEXSPI_FLSHCR1_WA_MASK                  (0x400U)
50120 #define FLEXSPI_FLSHCR1_WA_SHIFT                 (10U)
50121 /*! WA - Word-Addressable
50122  *  0b0..Byte-addressable
50123  *  0b1..Word-addressable
50124  */
50125 #define FLEXSPI_FLSHCR1_WA(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
50126 
50127 #define FLEXSPI_FLSHCR1_CAS_MASK                 (0x7800U)
50128 #define FLEXSPI_FLSHCR1_CAS_SHIFT                (11U)
50129 /*! CAS - Column Address Size */
50130 #define FLEXSPI_FLSHCR1_CAS(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
50131 
50132 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK      (0x8000U)
50133 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT     (15U)
50134 /*! CSINTERVALUNIT - Chip Select Interval Unit
50135  *  0b0..1 serial clock cycle
50136  *  0b1..256 serial clock cycles
50137  */
50138 #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
50139 
50140 #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK          (0xFFFF0000U)
50141 #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT         (16U)
50142 /*! CSINTERVAL - Chip Select Interval */
50143 #define FLEXSPI_FLSHCR1_CSINTERVAL(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
50144 /*! @} */
50145 
50146 /* The count of FLEXSPI_FLSHCR1 */
50147 #define FLEXSPI_FLSHCR1_COUNT                    (4U)
50148 
50149 /*! @name FLSHCR2 - Flash Control 2 */
50150 /*! @{ */
50151 
50152 #define FLEXSPI_FLSHCR2_ARDSEQID_MASK            (0xFU)
50153 #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT           (0U)
50154 /*! ARDSEQID - Sequence Index for AHB Read-Triggered Command in LUT */
50155 #define FLEXSPI_FLSHCR2_ARDSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
50156 
50157 #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK           (0xE0U)
50158 #define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT          (5U)
50159 /*! ARDSEQNUM - Sequence Number for AHB Read-Triggered Command */
50160 #define FLEXSPI_FLSHCR2_ARDSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
50161 
50162 #define FLEXSPI_FLSHCR2_AWRSEQID_MASK            (0xF00U)
50163 #define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT           (8U)
50164 /*! AWRSEQID - Sequence Index for AHB Write-Triggered Command */
50165 #define FLEXSPI_FLSHCR2_AWRSEQID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
50166 
50167 #define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK           (0xE000U)
50168 #define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT          (13U)
50169 /*! AWRSEQNUM - Sequence Number for AHB Write-Triggered Command */
50170 #define FLEXSPI_FLSHCR2_AWRSEQNUM(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
50171 
50172 #define FLEXSPI_FLSHCR2_AWRWAIT_MASK             (0xFFF0000U)
50173 #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT            (16U)
50174 /*! AWRWAIT - AHB Write Wait */
50175 #define FLEXSPI_FLSHCR2_AWRWAIT(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
50176 
50177 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK         (0x70000000U)
50178 #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT        (28U)
50179 /*! AWRWAITUNIT - AWRWAIT Unit
50180  *  0b000..2
50181  *  0b001..8
50182  *  0b010..32
50183  *  0b011..128
50184  *  0b100..512
50185  *  0b101..2048
50186  *  0b110..8192
50187  *  0b111..32768
50188  */
50189 #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
50190 
50191 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK         (0x80000000U)
50192 #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT        (31U)
50193 #define FLEXSPI_FLSHCR2_CLRINSTRPTR(x)           (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
50194 /*! @} */
50195 
50196 /* The count of FLEXSPI_FLSHCR2 */
50197 #define FLEXSPI_FLSHCR2_COUNT                    (4U)
50198 
50199 /*! @name FLSHCR4 - Flash Control 4 */
50200 /*! @{ */
50201 
50202 #define FLEXSPI_FLSHCR4_WMOPT1_MASK              (0x1U)
50203 #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT             (0U)
50204 /*! WMOPT1 - Write Mask Option 1
50205  *  0b0..When writing to an external device, DQS pin is used as write mask. When flash memory is accessed in
50206  *       individual mode, AHB or IP write burst start address alignment is not limited.
50207  *  0b1..When writing to an external device, DQS pin is not used as write mask. When flash memory is accessed in
50208  *       individual mode, AHB or IP write burst start address alignment is limited.
50209  */
50210 #define FLEXSPI_FLSHCR4_WMOPT1(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
50211 
50212 #define FLEXSPI_FLSHCR4_WMOPT2_MASK              (0x2U)
50213 #define FLEXSPI_FLSHCR4_WMOPT2_SHIFT             (1U)
50214 /*! WMOPT2 - Write Mask Option 2
50215  *  0b0..When writing to an external device, DQS pin is used as write mask. When flash memory is accessed in
50216  *       individual mode, AHB or IP write burst length is not limited.
50217  *  0b1..When writing to an external device, DQS pin is not used as write mask. When flash memory is accessed in
50218  *       individual mode, AHB or IP write burst length is limited. The minimum write burst length should be 4.
50219  */
50220 #define FLEXSPI_FLSHCR4_WMOPT2(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK)
50221 
50222 #define FLEXSPI_FLSHCR4_WMENA_MASK               (0x4U)
50223 #define FLEXSPI_FLSHCR4_WMENA_SHIFT              (2U)
50224 /*! WMENA - Write Mask Enable for Port A
50225  *  0b0..Disabled. When writing to external device, DQS(RWDS) pin is not driven.
50226  *  0b1..Enabled. When writing to external device, FlexSPI drives DQS(RWDS) pin as write mask output.
50227  */
50228 #define FLEXSPI_FLSHCR4_WMENA(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
50229 
50230 #define FLEXSPI_FLSHCR4_WMENB_MASK               (0x8U)
50231 #define FLEXSPI_FLSHCR4_WMENB_SHIFT              (3U)
50232 /*! WMENB - Write Mask Enable for Port B
50233  *  0b0..Disabled. When writing to external device, DQS(RWDS) pin is not driven.
50234  *  0b1..Enabled. When writing to external device, FlexSPI drives DQS(RWDS) pin as write mask output.
50235  */
50236 #define FLEXSPI_FLSHCR4_WMENB(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
50237 /*! @} */
50238 
50239 /*! @name IPCR0 - IP Control 0 */
50240 /*! @{ */
50241 
50242 #define FLEXSPI_IPCR0_SFAR_MASK                  (0xFFFFFFFFU)
50243 #define FLEXSPI_IPCR0_SFAR_SHIFT                 (0U)
50244 /*! SFAR - Serial Flash Address */
50245 #define FLEXSPI_IPCR0_SFAR(x)                    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
50246 /*! @} */
50247 
50248 /*! @name IPCR1 - IP Control 1 */
50249 /*! @{ */
50250 
50251 #define FLEXSPI_IPCR1_IDATSZ_MASK                (0xFFFFU)
50252 #define FLEXSPI_IPCR1_IDATSZ_SHIFT               (0U)
50253 /*! IDATSZ - Flash Read/Program Data Size (in bytes) for IP command. */
50254 #define FLEXSPI_IPCR1_IDATSZ(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
50255 
50256 #define FLEXSPI_IPCR1_ISEQID_MASK                (0xF0000U)
50257 #define FLEXSPI_IPCR1_ISEQID_SHIFT               (16U)
50258 /*! ISEQID - Sequence Index in LUT for IP command. */
50259 #define FLEXSPI_IPCR1_ISEQID(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
50260 
50261 #define FLEXSPI_IPCR1_ISEQNUM_MASK               (0x7000000U)
50262 #define FLEXSPI_IPCR1_ISEQNUM_SHIFT              (24U)
50263 /*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. */
50264 #define FLEXSPI_IPCR1_ISEQNUM(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
50265 
50266 #define FLEXSPI_IPCR1_IPAREN_MASK                (0x80000000U)
50267 #define FLEXSPI_IPCR1_IPAREN_SHIFT               (31U)
50268 /*! IPAREN - Parallel Mode Enable for IP Commands
50269  *  0b0..Disabled. Flash memory is accessed in Individual mode.
50270  *  0b1..Enabled. Flash memory is accessed in Parallel mode.
50271  */
50272 #define FLEXSPI_IPCR1_IPAREN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
50273 /*! @} */
50274 
50275 /*! @name IPCMD - IP Command */
50276 /*! @{ */
50277 
50278 #define FLEXSPI_IPCMD_TRG_MASK                   (0x1U)
50279 #define FLEXSPI_IPCMD_TRG_SHIFT                  (0U)
50280 /*! TRG - Command Trigger
50281  *  0b0..No action
50282  *  0b1..Start the IP command that the IPCR0 and IPCR1 registers define.
50283  */
50284 #define FLEXSPI_IPCMD_TRG(x)                     (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
50285 /*! @} */
50286 
50287 /*! @name IPRXFCR - IP Receive FIFO Control */
50288 /*! @{ */
50289 
50290 #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK            (0x1U)
50291 #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT           (0U)
50292 /*! CLRIPRXF - Clear IP Receive FIFO
50293  *  0b0..No function
50294  *  0b1..A clock cycle pulse clears all valid data entries in IP receive FIFO.
50295  */
50296 #define FLEXSPI_IPRXFCR_CLRIPRXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
50297 
50298 #define FLEXSPI_IPRXFCR_RXDMAEN_MASK             (0x2U)
50299 #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT            (1U)
50300 /*! RXDMAEN - IP Receive FIFO Reading by DMA Enable
50301  *  0b0..Disabled. The processor reads the FIFO.
50302  *  0b1..Enabled. DMA reads the FIFO.
50303  */
50304 #define FLEXSPI_IPRXFCR_RXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
50305 
50306 #define FLEXSPI_IPRXFCR_RXWMRK_MASK              (0x7CU)
50307 #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT             (2U)
50308 /*! RXWMRK - IP Receive FIFO Watermark Level */
50309 #define FLEXSPI_IPRXFCR_RXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
50310 /*! @} */
50311 
50312 /*! @name IPTXFCR - IP Transmit FIFO Control */
50313 /*! @{ */
50314 
50315 #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK            (0x1U)
50316 #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT           (0U)
50317 /*! CLRIPTXF - Clear IP Transmit FIFO
50318  *  0b0..No function
50319  *  0b1..A clock cycle pulse clears all valid data entries in the IP transmit FIFO.
50320  */
50321 #define FLEXSPI_IPTXFCR_CLRIPTXF(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
50322 
50323 #define FLEXSPI_IPTXFCR_TXDMAEN_MASK             (0x2U)
50324 #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT            (1U)
50325 /*! TXDMAEN - Transmit FIFO DMA Enable
50326  *  0b0..Processor
50327  *  0b1..DMA
50328  */
50329 #define FLEXSPI_IPTXFCR_TXDMAEN(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
50330 
50331 #define FLEXSPI_IPTXFCR_TXWMRK_MASK              (0x7CU)
50332 #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT             (2U)
50333 /*! TXWMRK - Transmit Watermark Level */
50334 #define FLEXSPI_IPTXFCR_TXWMRK(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
50335 /*! @} */
50336 
50337 /*! @name DLLCR - DLL Control 0 */
50338 /*! @{ */
50339 
50340 #define FLEXSPI_DLLCR_DLLEN_MASK                 (0x1U)
50341 #define FLEXSPI_DLLCR_DLLEN_SHIFT                (0U)
50342 /*! DLLEN - DLL Calibration Enable
50343  *  0b0..Disable
50344  *  0b1..Enable
50345  */
50346 #define FLEXSPI_DLLCR_DLLEN(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
50347 
50348 #define FLEXSPI_DLLCR_DLLRESET_MASK              (0x2U)
50349 #define FLEXSPI_DLLCR_DLLRESET_SHIFT             (1U)
50350 /*! DLLRESET - DLL reset
50351  *  0b0..No function
50352  *  0b1..Force DLL reset.
50353  */
50354 #define FLEXSPI_DLLCR_DLLRESET(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
50355 
50356 #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK          (0x78U)
50357 #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT         (3U)
50358 /*! SLVDLYTARGET - Target Delay Line */
50359 #define FLEXSPI_DLLCR_SLVDLYTARGET(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
50360 
50361 #define FLEXSPI_DLLCR_OVRDEN_MASK                (0x100U)
50362 #define FLEXSPI_DLLCR_OVRDEN_SHIFT               (8U)
50363 /*! OVRDEN - Target Clock Delay Line Override Value Enable
50364  *  0b0..Disable
50365  *  0b1..Enable
50366  */
50367 #define FLEXSPI_DLLCR_OVRDEN(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
50368 
50369 #define FLEXSPI_DLLCR_OVRDVAL_MASK               (0x7E00U)
50370 #define FLEXSPI_DLLCR_OVRDVAL_SHIFT              (9U)
50371 /*! OVRDVAL - Target Clock Delay Line Override Value */
50372 #define FLEXSPI_DLLCR_OVRDVAL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
50373 
50374 #define FLEXSPI_DLLCR_REFPHASEGAP_MASK           (0x18000U)
50375 #define FLEXSPI_DLLCR_REFPHASEGAP_SHIFT          (15U)
50376 /*! REFPHASEGAP - Reference Clock Delay Line Phase Adjust Gap. REFPHASEGAP setting of 2h is recommended if DLLEN is set. */
50377 #define FLEXSPI_DLLCR_REFPHASEGAP(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_REFPHASEGAP_SHIFT)) & FLEXSPI_DLLCR_REFPHASEGAP_MASK)
50378 /*! @} */
50379 
50380 /* The count of FLEXSPI_DLLCR */
50381 #define FLEXSPI_DLLCR_COUNT                      (2U)
50382 
50383 /*! @name MISCCR4 - Misc Control 4 */
50384 /*! @{ */
50385 
50386 #define FLEXSPI_MISCCR4_AHBADDRESS_MASK          (0xFFFFFFFFU)
50387 #define FLEXSPI_MISCCR4_AHBADDRESS_SHIFT         (0U)
50388 /*! AHBADDRESS - AHB Address */
50389 #define FLEXSPI_MISCCR4_AHBADDRESS(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR4_AHBADDRESS_SHIFT)) & FLEXSPI_MISCCR4_AHBADDRESS_MASK)
50390 /*! @} */
50391 
50392 /*! @name MISCCR5 - Miscellaneous Control 5 */
50393 /*! @{ */
50394 
50395 #define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK  (0xFFFFFFFFU)
50396 #define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT (0U)
50397 /*! ECCSINGLEERRORCORR - ECC Single-Bit Error Correction Indicator */
50398 #define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR(x)    (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT)) & FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK)
50399 /*! @} */
50400 
50401 /*! @name MISCCR6 - Miscellaneous Control 6 */
50402 /*! @{ */
50403 
50404 #define FLEXSPI_MISCCR6_VALID_MASK               (0x1U)
50405 #define FLEXSPI_MISCCR6_VALID_SHIFT              (0U)
50406 /*! VALID - ECC Single-Bit Error Information Valid
50407  *  0b0..Invalid
50408  *  0b1..Valid
50409  */
50410 #define FLEXSPI_MISCCR6_VALID(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_VALID_SHIFT)) & FLEXSPI_MISCCR6_VALID_MASK)
50411 
50412 #define FLEXSPI_MISCCR6_HIT_MASK                 (0x2U)
50413 #define FLEXSPI_MISCCR6_HIT_SHIFT                (1U)
50414 /*! HIT - ECC Single-Bit Error Information Hit
50415  *  0b0..Address not hit
50416  *  0b1..Address hit
50417  */
50418 #define FLEXSPI_MISCCR6_HIT(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_HIT_SHIFT)) & FLEXSPI_MISCCR6_HIT_MASK)
50419 
50420 #define FLEXSPI_MISCCR6_ADDRESS_MASK             (0xFFFFFFFCU)
50421 #define FLEXSPI_MISCCR6_ADDRESS_SHIFT            (2U)
50422 /*! ADDRESS - ECC Single-Bit Error Address */
50423 #define FLEXSPI_MISCCR6_ADDRESS(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_ADDRESS_SHIFT)) & FLEXSPI_MISCCR6_ADDRESS_MASK)
50424 /*! @} */
50425 
50426 /*! @name MISCCR7 - Miscellaneous Control 7 */
50427 /*! @{ */
50428 
50429 #define FLEXSPI_MISCCR7_VALID_MASK               (0x1U)
50430 #define FLEXSPI_MISCCR7_VALID_SHIFT              (0U)
50431 /*! VALID - ECC Multibit Error Information Valid */
50432 #define FLEXSPI_MISCCR7_VALID(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_VALID_SHIFT)) & FLEXSPI_MISCCR7_VALID_MASK)
50433 
50434 #define FLEXSPI_MISCCR7_HIT_MASK                 (0x2U)
50435 #define FLEXSPI_MISCCR7_HIT_SHIFT                (1U)
50436 /*! HIT - ECC Multibit Error Information Hit
50437  *  0b0..Address not hit
50438  *  0b1..Address hit
50439  */
50440 #define FLEXSPI_MISCCR7_HIT(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_HIT_SHIFT)) & FLEXSPI_MISCCR7_HIT_MASK)
50441 
50442 #define FLEXSPI_MISCCR7_ADDRESS_MASK             (0xFFFFFFFCU)
50443 #define FLEXSPI_MISCCR7_ADDRESS_SHIFT            (2U)
50444 /*! ADDRESS - ECC multi error address */
50445 #define FLEXSPI_MISCCR7_ADDRESS(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_ADDRESS_SHIFT)) & FLEXSPI_MISCCR7_ADDRESS_MASK)
50446 /*! @} */
50447 
50448 /*! @name STS0 - Status 0 */
50449 /*! @{ */
50450 
50451 #define FLEXSPI_STS0_SEQIDLE_MASK                (0x1U)
50452 #define FLEXSPI_STS0_SEQIDLE_SHIFT               (0U)
50453 /*! SEQIDLE - SEQ_CTL State Machine Idle
50454  *  0b0..Not idle
50455  *  0b1..Idle
50456  */
50457 #define FLEXSPI_STS0_SEQIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
50458 
50459 #define FLEXSPI_STS0_ARBIDLE_MASK                (0x2U)
50460 #define FLEXSPI_STS0_ARBIDLE_SHIFT               (1U)
50461 /*! ARBIDLE - ARB_CTL State Machine Idle
50462  *  0b0..Not idle
50463  *  0b1..Idle
50464  */
50465 #define FLEXSPI_STS0_ARBIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
50466 
50467 #define FLEXSPI_STS0_ARBCMDSRC_MASK              (0xCU)
50468 #define FLEXSPI_STS0_ARBCMDSRC_SHIFT             (2U)
50469 /*! ARBCMDSRC - ARB Command Source
50470  *  0b00..Trigger source is AHB read command.
50471  *  0b01..Trigger source is AHB write command.
50472  *  0b10..Trigger source is IP command (by writing 1 to IPCMD[TRG]).
50473  *  0b11..Trigger source is a suspended command that has resumed.
50474  */
50475 #define FLEXSPI_STS0_ARBCMDSRC(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
50476 /*! @} */
50477 
50478 /*! @name STS1 - Status 1 */
50479 /*! @{ */
50480 
50481 #define FLEXSPI_STS1_AHBCMDERRID_MASK            (0xFU)
50482 #define FLEXSPI_STS1_AHBCMDERRID_SHIFT           (0U)
50483 /*! AHBCMDERRID - AHB Command Error ID */
50484 #define FLEXSPI_STS1_AHBCMDERRID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
50485 
50486 #define FLEXSPI_STS1_AHBCMDERRCODE_MASK          (0xF00U)
50487 #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT         (8U)
50488 /*! AHBCMDERRCODE - AHB Command Error Code
50489  *  0b0000..No error
50490  *  0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence
50491  *  0b0011..Unknown instruction opcode in the sequence
50492  *  0b0100..DUMMY_SDR or DUMMY_RWDS_SDR instruction used in DDR sequence
50493  *  0b0101..DUMMY_DDR or DUMMY_RWDS_DDR instruction used in SDR sequence
50494  *  0b1110..Sequence execution timeout
50495  */
50496 #define FLEXSPI_STS1_AHBCMDERRCODE(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
50497 
50498 #define FLEXSPI_STS1_IPCMDERRID_MASK             (0xF0000U)
50499 #define FLEXSPI_STS1_IPCMDERRID_SHIFT            (16U)
50500 /*! IPCMDERRID - IP Command Error ID */
50501 #define FLEXSPI_STS1_IPCMDERRID(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
50502 
50503 #define FLEXSPI_STS1_IPCMDERRCODE_MASK           (0xF000000U)
50504 #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT          (24U)
50505 /*! IPCMDERRCODE - IP Command Error Code
50506  *  0b0000..No error
50507  *  0b0010..IP command with JMP_ON_CS instruction used in the sequence
50508  *  0b0011..Unknown instruction opcode in the sequence
50509  *  0b0100..DUMMY_SDR or DUMMY_RWDS_SDR instruction used in DDR sequence
50510  *  0b0101..DUMMY_DDR or DUMMY_RWDS_DDR instruction used in SDR sequence
50511  *  0b0110..Flash memory access start address exceeds entire flash address range (A1, A2, B1, and B2)
50512  *  0b1110..Sequence execution timeout
50513  *  0b1111..Flash boundary crossed
50514  */
50515 #define FLEXSPI_STS1_IPCMDERRCODE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
50516 /*! @} */
50517 
50518 /*! @name STS2 - Status 2 */
50519 /*! @{ */
50520 
50521 #define FLEXSPI_STS2_ASLVLOCK_MASK               (0x1U)
50522 #define FLEXSPI_STS2_ASLVLOCK_SHIFT              (0U)
50523 /*! ASLVLOCK - Flash A Sample Target Delay Line Locked
50524  *  0b0..Not locked
50525  *  0b1..Locked
50526  */
50527 #define FLEXSPI_STS2_ASLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
50528 
50529 #define FLEXSPI_STS2_AREFLOCK_MASK               (0x2U)
50530 #define FLEXSPI_STS2_AREFLOCK_SHIFT              (1U)
50531 /*! AREFLOCK - Flash A Sample Clock Reference Delay Line Locked
50532  *  0b0..Not locked
50533  *  0b1..Locked
50534  */
50535 #define FLEXSPI_STS2_AREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
50536 
50537 #define FLEXSPI_STS2_ASLVSEL_MASK                (0xFCU)
50538 #define FLEXSPI_STS2_ASLVSEL_SHIFT               (2U)
50539 /*! ASLVSEL - Flash A Sample Clock Target Delay Line Delay Cell Number */
50540 #define FLEXSPI_STS2_ASLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
50541 
50542 #define FLEXSPI_STS2_AREFSEL_MASK                (0x3F00U)
50543 #define FLEXSPI_STS2_AREFSEL_SHIFT               (8U)
50544 /*! AREFSEL - Flash A Sample Clock Reference Delay Line Delay Cell Number */
50545 #define FLEXSPI_STS2_AREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
50546 
50547 #define FLEXSPI_STS2_BSLVLOCK_MASK               (0x10000U)
50548 #define FLEXSPI_STS2_BSLVLOCK_SHIFT              (16U)
50549 /*! BSLVLOCK - Flash B Sample Target Reference Delay Line Locked
50550  *  0b0..Not locked
50551  *  0b1..Locked
50552  */
50553 #define FLEXSPI_STS2_BSLVLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
50554 
50555 #define FLEXSPI_STS2_BREFLOCK_MASK               (0x20000U)
50556 #define FLEXSPI_STS2_BREFLOCK_SHIFT              (17U)
50557 /*! BREFLOCK - Flash B Sample Clock Reference Delay Line Locked
50558  *  0b0..Not locked
50559  *  0b1..Locked
50560  */
50561 #define FLEXSPI_STS2_BREFLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
50562 
50563 #define FLEXSPI_STS2_BSLVSEL_MASK                (0xFC0000U)
50564 #define FLEXSPI_STS2_BSLVSEL_SHIFT               (18U)
50565 /*! BSLVSEL - Flash B Sample Clock Target Delay Line Delay Cell Number */
50566 #define FLEXSPI_STS2_BSLVSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
50567 
50568 #define FLEXSPI_STS2_BREFSEL_MASK                (0x3F000000U)
50569 #define FLEXSPI_STS2_BREFSEL_SHIFT               (24U)
50570 /*! BREFSEL - Flash B Sample Clock Reference Delay Line Delay Cell Number */
50571 #define FLEXSPI_STS2_BREFSEL(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
50572 /*! @} */
50573 
50574 /*! @name AHBSPNDSTS - AHB Suspend Status */
50575 /*! @{ */
50576 
50577 #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK           (0x1U)
50578 #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT          (0U)
50579 /*! ACTIVE - Active AHB Read Prefetch Suspended
50580  *  0b0..No suspended AHB read prefetch command.
50581  *  0b1..An AHB read prefetch command sequence has been suspended.
50582  */
50583 #define FLEXSPI_AHBSPNDSTS_ACTIVE(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
50584 
50585 #define FLEXSPI_AHBSPNDSTS_BUFID_MASK            (0xEU)
50586 #define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT           (1U)
50587 /*! BUFID - AHB Receive Buffer ID for Suspended Command Sequence */
50588 #define FLEXSPI_AHBSPNDSTS_BUFID(x)              (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
50589 
50590 #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK           (0xFFFF0000U)
50591 #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT          (16U)
50592 /*! DATLFT - Data Left */
50593 #define FLEXSPI_AHBSPNDSTS_DATLFT(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
50594 /*! @} */
50595 
50596 /*! @name IPRXFSTS - IP Receive FIFO Status */
50597 /*! @{ */
50598 
50599 #define FLEXSPI_IPRXFSTS_FILL_MASK               (0xFFU)
50600 #define FLEXSPI_IPRXFSTS_FILL_SHIFT              (0U)
50601 /*! FILL - Fill Level of IP Receive FIFO */
50602 #define FLEXSPI_IPRXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
50603 
50604 #define FLEXSPI_IPRXFSTS_RDCNTR_MASK             (0xFFFF0000U)
50605 #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT            (16U)
50606 /*! RDCNTR - Read Data Counter */
50607 #define FLEXSPI_IPRXFSTS_RDCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
50608 /*! @} */
50609 
50610 /*! @name IPTXFSTS - IP Transmit FIFO Status */
50611 /*! @{ */
50612 
50613 #define FLEXSPI_IPTXFSTS_FILL_MASK               (0xFFU)
50614 #define FLEXSPI_IPTXFSTS_FILL_SHIFT              (0U)
50615 /*! FILL - Fill Level of IP Transmit FIFO */
50616 #define FLEXSPI_IPTXFSTS_FILL(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
50617 
50618 #define FLEXSPI_IPTXFSTS_WRCNTR_MASK             (0xFFFF0000U)
50619 #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT            (16U)
50620 /*! WRCNTR - Write Data Counter */
50621 #define FLEXSPI_IPTXFSTS_WRCNTR(x)               (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
50622 /*! @} */
50623 
50624 /*! @name RFDR - IP Receive FIFO Data 0..IP Receive FIFO Data 31 */
50625 /*! @{ */
50626 
50627 #define FLEXSPI_RFDR_RXDATA_MASK                 (0xFFFFFFFFU)
50628 #define FLEXSPI_RFDR_RXDATA_SHIFT                (0U)
50629 /*! RXDATA - Receive Data */
50630 #define FLEXSPI_RFDR_RXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
50631 /*! @} */
50632 
50633 /* The count of FLEXSPI_RFDR */
50634 #define FLEXSPI_RFDR_COUNT                       (32U)
50635 
50636 /*! @name TFDR - IP TX FIFO Data 0..IP TX FIFO Data 31 */
50637 /*! @{ */
50638 
50639 #define FLEXSPI_TFDR_TXDATA_MASK                 (0xFFFFFFFFU)
50640 #define FLEXSPI_TFDR_TXDATA_SHIFT                (0U)
50641 /*! TXDATA - Transmit Data */
50642 #define FLEXSPI_TFDR_TXDATA(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
50643 /*! @} */
50644 
50645 /* The count of FLEXSPI_TFDR */
50646 #define FLEXSPI_TFDR_COUNT                       (32U)
50647 
50648 /*! @name LUT - Lookup Table 0..Lookup Table 63 */
50649 /*! @{ */
50650 
50651 #define FLEXSPI_LUT_OPERAND0_MASK                (0xFFU)
50652 #define FLEXSPI_LUT_OPERAND0_SHIFT               (0U)
50653 /*! OPERAND0 - OPERAND0 */
50654 #define FLEXSPI_LUT_OPERAND0(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
50655 
50656 #define FLEXSPI_LUT_NUM_PADS0_MASK               (0x300U)
50657 #define FLEXSPI_LUT_NUM_PADS0_SHIFT              (8U)
50658 /*! NUM_PADS0 - NUM_PADS0 */
50659 #define FLEXSPI_LUT_NUM_PADS0(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
50660 
50661 #define FLEXSPI_LUT_OPCODE0_MASK                 (0xFC00U)
50662 #define FLEXSPI_LUT_OPCODE0_SHIFT                (10U)
50663 /*! OPCODE0 - OPCODE */
50664 #define FLEXSPI_LUT_OPCODE0(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
50665 
50666 #define FLEXSPI_LUT_OPERAND1_MASK                (0xFF0000U)
50667 #define FLEXSPI_LUT_OPERAND1_SHIFT               (16U)
50668 /*! OPERAND1 - OPERAND1 */
50669 #define FLEXSPI_LUT_OPERAND1(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
50670 
50671 #define FLEXSPI_LUT_NUM_PADS1_MASK               (0x3000000U)
50672 #define FLEXSPI_LUT_NUM_PADS1_SHIFT              (24U)
50673 /*! NUM_PADS1 - NUM_PADS1 */
50674 #define FLEXSPI_LUT_NUM_PADS1(x)                 (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
50675 
50676 #define FLEXSPI_LUT_OPCODE1_MASK                 (0xFC000000U)
50677 #define FLEXSPI_LUT_OPCODE1_SHIFT                (26U)
50678 /*! OPCODE1 - OPCODE1 */
50679 #define FLEXSPI_LUT_OPCODE1(x)                   (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
50680 /*! @} */
50681 
50682 /* The count of FLEXSPI_LUT */
50683 #define FLEXSPI_LUT_COUNT                        (64U)
50684 
50685 /*! @name HMSTRCR - AHB Controller ID 0 Control..AHB Controller ID 7 Control */
50686 /*! @{ */
50687 
50688 #define FLEXSPI_HMSTRCR_MASK_MASK                (0xFFFFU)
50689 #define FLEXSPI_HMSTRCR_MASK_SHIFT               (0U)
50690 /*! MASK - Mask bits for AHB Controller ID.
50691  *  0b0000000000000000..Mask
50692  *  0b0000000000000001..Unmask
50693  */
50694 #define FLEXSPI_HMSTRCR_MASK(x)                  (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MASK_SHIFT)) & FLEXSPI_HMSTRCR_MASK_MASK)
50695 
50696 #define FLEXSPI_HMSTRCR_MSTRID_MASK              (0xFFFF0000U)
50697 #define FLEXSPI_HMSTRCR_MSTRID_SHIFT             (16U)
50698 /*! MSTRID - Controller ID */
50699 #define FLEXSPI_HMSTRCR_MSTRID(x)                (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MSTRID_SHIFT)) & FLEXSPI_HMSTRCR_MSTRID_MASK)
50700 /*! @} */
50701 
50702 /* The count of FLEXSPI_HMSTRCR */
50703 #define FLEXSPI_HMSTRCR_COUNT                    (8U)
50704 
50705 /*! @name HADDRSTART - HADDR REMAP Start Address */
50706 /*! @{ */
50707 
50708 #define FLEXSPI_HADDRSTART_REMAPEN_MASK          (0x1U)
50709 #define FLEXSPI_HADDRSTART_REMAPEN_SHIFT         (0U)
50710 /*! REMAPEN - AHB Bus Address Remap Enable
50711  *  0b0..HADDR REMAP Disabled
50712  *  0b1..HADDR REMAP Enabled
50713  */
50714 #define FLEXSPI_HADDRSTART_REMAPEN(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK)
50715 
50716 #define FLEXSPI_HADDRSTART_KBINECC_MASK          (0x2U)
50717 #define FLEXSPI_HADDRSTART_KBINECC_SHIFT         (1U)
50718 /*! KBINECC - OTFAD Keyblob in ECC
50719  *  0b0..FlexSPI fetches keyblob at base address + offset
50720  *  0b1..FlexSPI fetches keyblob at base address + offset * 2
50721  */
50722 #define FLEXSPI_HADDRSTART_KBINECC(x)            (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_KBINECC_SHIFT)) & FLEXSPI_HADDRSTART_KBINECC_MASK)
50723 
50724 #define FLEXSPI_HADDRSTART_ADDRSTART_MASK        (0xFFFFF000U)
50725 #define FLEXSPI_HADDRSTART_ADDRSTART_SHIFT       (12U)
50726 /*! ADDRSTART - HADDR Start Address */
50727 #define FLEXSPI_HADDRSTART_ADDRSTART(x)          (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_ADDRSTART_SHIFT)) & FLEXSPI_HADDRSTART_ADDRSTART_MASK)
50728 /*! @} */
50729 
50730 /*! @name HADDREND - HADDR REMAP END ADDR */
50731 /*! @{ */
50732 
50733 #define FLEXSPI_HADDREND_ENDSTART_MASK           (0xFFFFF000U)
50734 #define FLEXSPI_HADDREND_ENDSTART_SHIFT          (12U)
50735 /*! ENDSTART - End Address of HADDR Remap Range */
50736 #define FLEXSPI_HADDREND_ENDSTART(x)             (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDREND_ENDSTART_SHIFT)) & FLEXSPI_HADDREND_ENDSTART_MASK)
50737 /*! @} */
50738 
50739 /*! @name HADDROFFSET - HADDR Remap Offset */
50740 /*! @{ */
50741 
50742 #define FLEXSPI_HADDROFFSET_ADDROFFSET_MASK      (0xFFFFF000U)
50743 #define FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT     (12U)
50744 /*! ADDROFFSET - HADDR Offset */
50745 #define FLEXSPI_HADDROFFSET_ADDROFFSET(x)        (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT)) & FLEXSPI_HADDROFFSET_ADDROFFSET_MASK)
50746 /*! @} */
50747 
50748 
50749 /*!
50750  * @}
50751  */ /* end of group FLEXSPI_Register_Masks */
50752 
50753 
50754 /* FLEXSPI - Peripheral instance base addresses */
50755 /** Peripheral FLEXSPI1 base address */
50756 #define FLEXSPI1_BASE                            (0x400CC000u)
50757 /** Peripheral FLEXSPI1 base pointer */
50758 #define FLEXSPI1                                 ((FLEXSPI_Type *)FLEXSPI1_BASE)
50759 /** Peripheral FLEXSPI2 base address */
50760 #define FLEXSPI2_BASE                            (0x400D0000u)
50761 /** Peripheral FLEXSPI2 base pointer */
50762 #define FLEXSPI2                                 ((FLEXSPI_Type *)FLEXSPI2_BASE)
50763 /** Array initializer of FLEXSPI peripheral base addresses */
50764 #define FLEXSPI_BASE_ADDRS                       { 0u, FLEXSPI1_BASE, FLEXSPI2_BASE }
50765 /** Array initializer of FLEXSPI peripheral base pointers */
50766 #define FLEXSPI_BASE_PTRS                        { (FLEXSPI_Type *)0u, FLEXSPI1, FLEXSPI2 }
50767 /** Interrupt vectors for the FLEXSPI peripheral type */
50768 #define FLEXSPI_IRQS                             { NotAvail_IRQn, FLEXSPI1_IRQn, FLEXSPI2_IRQn }
50769 /* FlexSPI1 AMBA address. */
50770 #define FlexSPI1_AMBA_BASE                       (0x30000000U)
50771 /* FlexSPI1 ASFM address. */
50772 #define FlexSPI1_ASFM_BASE                       (0x30000000U)
50773 /* Base Address of AHB address space mapped to IP RX FIFO. */
50774 #define FlexSPI1_ARDF_BASE                       (0x2FC00000U)
50775 /* Base Address of AHB address space mapped to IP TX FIFO. */
50776 #define FlexSPI1_ATDF_BASE                       (0x2F800000U)
50777 /* FlexSPI1 alias base address. */
50778 #define FlexSPI1_ALIAS_BASE                      (0x8000000U)
50779 /* FlexSPI2 AMBA address. */
50780 #define FlexSPI2_AMBA_BASE                       (0x60000000U)
50781 /* FlexSPI ASFM address. */
50782 #define FlexSPI2_ASFM_BASE                       (0x60000000U)
50783 /* Base Address of AHB address space mapped to IP RX FIFO. */
50784 #define FlexSPI2_ARDF_BASE                       (0x7FC00000U)
50785 /* Base Address of AHB address space mapped to IP TX FIFO. */
50786 #define FlexSPI2_ATDF_BASE                       (0x7F800000U)
50787 
50788 
50789 /*!
50790  * @}
50791  */ /* end of group FLEXSPI_Peripheral_Access_Layer */
50792 
50793 
50794 /* ----------------------------------------------------------------------------
50795    -- GPC_CPU_MODE_CTRL Peripheral Access Layer
50796    ---------------------------------------------------------------------------- */
50797 
50798 /*!
50799  * @addtogroup GPC_CPU_MODE_CTRL_Peripheral_Access_Layer GPC_CPU_MODE_CTRL Peripheral Access Layer
50800  * @{
50801  */
50802 
50803 /** GPC_CPU_MODE_CTRL - Register Layout Typedef */
50804 typedef struct {
50805        uint8_t RESERVED_0[4];
50806   __IO uint32_t CM_AUTHEN_CTRL;                    /**< CM Authentication Control, offset: 0x4 */
50807   __IO uint32_t CM_INT_CTRL;                       /**< CM Interrupt Control, offset: 0x8 */
50808   __IO uint32_t CM_MISC;                           /**< Miscellaneous, offset: 0xC */
50809   __IO uint32_t CM_MODE_CTRL;                      /**< CPU mode control, offset: 0x10 */
50810   __I  uint32_t CM_MODE_STAT;                      /**< CM CPU mode Status, offset: 0x14 */
50811        uint8_t RESERVED_1[232];
50812   __IO uint32_t CM_IRQ_WAKEUP_MASK[8];             /**< CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask, array offset: 0x100, array step: 0x4 */
50813        uint8_t RESERVED_2[32];
50814   __IO uint32_t CM_NON_IRQ_WAKEUP_MASK;            /**< CM non-irq wakeup mask, offset: 0x140 */
50815        uint8_t RESERVED_3[12];
50816   __I  uint32_t CM_IRQ_WAKEUP_STAT[8];             /**< CM IRQ0~31 wakeup status..CM IRQ224~255 wakeup status, array offset: 0x150, array step: 0x4 */
50817        uint8_t RESERVED_4[32];
50818   __I  uint32_t CM_NON_IRQ_WAKEUP_STAT;            /**< CM non-irq wakeup status, offset: 0x190 */
50819        uint8_t RESERVED_5[108];
50820   __IO uint32_t CM_SLEEP_SSAR_CTRL;                /**< CM sleep SSAR control, offset: 0x200 */
50821        uint8_t RESERVED_6[4];
50822   __IO uint32_t CM_SLEEP_LPCG_CTRL;                /**< CM sleep LPCG control, offset: 0x208 */
50823        uint8_t RESERVED_7[4];
50824   __IO uint32_t CM_SLEEP_PLL_CTRL;                 /**< CM sleep PLL control, offset: 0x210 */
50825        uint8_t RESERVED_8[4];
50826   __IO uint32_t CM_SLEEP_ISO_CTRL;                 /**< CM sleep isolation control, offset: 0x218 */
50827        uint8_t RESERVED_9[4];
50828   __IO uint32_t CM_SLEEP_RESET_CTRL;               /**< CM sleep reset control, offset: 0x220 */
50829        uint8_t RESERVED_10[4];
50830   __IO uint32_t CM_SLEEP_POWER_CTRL;               /**< CM sleep power control, offset: 0x228 */
50831        uint8_t RESERVED_11[100];
50832   __IO uint32_t CM_WAKEUP_POWER_CTRL;              /**< CM wakeup power control, offset: 0x290 */
50833        uint8_t RESERVED_12[4];
50834   __IO uint32_t CM_WAKEUP_RESET_CTRL;              /**< CM wakeup reset control, offset: 0x298 */
50835        uint8_t RESERVED_13[4];
50836   __IO uint32_t CM_WAKEUP_ISO_CTRL;                /**< CM wakeup isolation control, offset: 0x2A0 */
50837        uint8_t RESERVED_14[4];
50838   __IO uint32_t CM_WAKEUP_PLL_CTRL;                /**< CM wakeup PLL control, offset: 0x2A8 */
50839        uint8_t RESERVED_15[4];
50840   __IO uint32_t CM_WAKEUP_LPCG_CTRL;               /**< CM wakeup LPCG control, offset: 0x2B0 */
50841        uint8_t RESERVED_16[4];
50842   __IO uint32_t CM_WAKEUP_SSAR_CTRL;               /**< CM wakeup SSAR control, offset: 0x2B8 */
50843        uint8_t RESERVED_17[68];
50844   __IO uint32_t CM_SP_CTRL;                        /**< CM Setpoint Control, offset: 0x300 */
50845   __I  uint32_t CM_SP_STAT;                        /**< CM Setpoint Status, offset: 0x304 */
50846        uint8_t RESERVED_18[8];
50847   __IO uint32_t CM_RUN_MODE_MAPPING;               /**< CM Run Mode Setpoint Allowed, offset: 0x310 */
50848   __IO uint32_t CM_WAIT_MODE_MAPPING;              /**< CM Wait Mode Setpoint Allowed, offset: 0x314 */
50849   __IO uint32_t CM_STOP_MODE_MAPPING;              /**< CM Stop Mode Setpoint Allowed, offset: 0x318 */
50850   __IO uint32_t CM_SUSPEND_MODE_MAPPING;           /**< CM Suspend Mode Setpoint Allowed, offset: 0x31C */
50851   __IO uint32_t CM_SP_MAPPING[16];                 /**< CM Setpoint 0 Mapping..CM Setpoint 15 Mapping, array offset: 0x320, array step: 0x4 */
50852        uint8_t RESERVED_19[32];
50853   __IO uint32_t CM_STBY_CTRL;                      /**< CM standby control, offset: 0x380 */
50854 } GPC_CPU_MODE_CTRL_Type;
50855 
50856 /* ----------------------------------------------------------------------------
50857    -- GPC_CPU_MODE_CTRL Register Masks
50858    ---------------------------------------------------------------------------- */
50859 
50860 /*!
50861  * @addtogroup GPC_CPU_MODE_CTRL_Register_Masks GPC_CPU_MODE_CTRL Register Masks
50862  * @{
50863  */
50864 
50865 /*! @name CM_AUTHEN_CTRL - CM Authentication Control */
50866 /*! @{ */
50867 
50868 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_MASK (0x1U)
50869 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_SHIFT (0U)
50870 /*! USER - Allow user mode access
50871  *  0b0..Allow only privilege mode to access CPU mode control registers
50872  *  0b1..Allow both privilege and user mode to access CPU mode control registers
50873  */
50874 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_MASK)
50875 
50876 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
50877 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
50878 /*! NONSECURE - Allow non-secure mode access
50879  *  0b0..Allow only secure mode to access CPU mode control registers
50880  *  0b1..Allow both secure and non-secure mode to access CPU mode control registers
50881  */
50882 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK)
50883 
50884 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
50885 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
50886 /*! LOCK_SETTING - Lock NONSECURE and USER */
50887 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK)
50888 
50889 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
50890 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
50891 /*! WHITE_LIST - Domain ID white list */
50892 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK)
50893 
50894 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
50895 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
50896 /*! LOCK_LIST - White list lock */
50897 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK)
50898 
50899 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
50900 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
50901 /*! LOCK_CFG - Configuration lock */
50902 #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK)
50903 /*! @} */
50904 
50905 /*! @name CM_INT_CTRL - CM Interrupt Control */
50906 /*! @{ */
50907 
50908 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_MASK (0x1U)
50909 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_SHIFT (0U)
50910 /*! SP_REQ_NOT_ALLOWED_SLEEP_INT_EN - sp_req_not_allowed_for_sleep interrupt enable
50911  *  0b0..Interrupt disable
50912  *  0b1..Interrupt enable
50913  */
50914 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_MASK)
50915 
50916 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_MASK (0x2U)
50917 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_SHIFT (1U)
50918 /*! SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN - sp_req_not_allowed_for_wakeup interrupt enable
50919  *  0b0..Interrupt disable
50920  *  0b1..Interrupt enable
50921  */
50922 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_MASK)
50923 
50924 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_MASK (0x4U)
50925 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_SHIFT (2U)
50926 /*! SP_REQ_NOT_ALLOWED_SOFT_INT_EN - sp_req_not_allowed_for_soft interrupt enable
50927  *  0b0..Interrupt disable
50928  *  0b1..Interrupt enable
50929  */
50930 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_MASK)
50931 
50932 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK (0x10000U)
50933 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_SHIFT (16U)
50934 /*! SP_REQ_NOT_ALLOWED_SLEEP_INT - sp_req_not_allowed_for_sleep interrupt status and clear register */
50935 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK)
50936 
50937 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK (0x20000U)
50938 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_SHIFT (17U)
50939 /*! SP_REQ_NOT_ALLOWED_WAKEUP_INT - sp_req_not_allowed_for_wakeup interrupt status and clear register */
50940 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK)
50941 
50942 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK (0x40000U)
50943 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_SHIFT (18U)
50944 /*! SP_REQ_NOT_ALLOWED_SOFT_INT - sp_req_not_allowed_for_soft interrupt status and clear register */
50945 #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK)
50946 /*! @} */
50947 
50948 /*! @name CM_MISC - Miscellaneous */
50949 /*! @{ */
50950 
50951 #define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_MASK  (0x1U)
50952 #define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_SHIFT (0U)
50953 /*! NMI_STAT - Non-masked interrupt status
50954  *  0b0..NMI is not asserting
50955  *  0b1..NMI is asserting
50956  */
50957 #define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT(x)    (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_MASK)
50958 
50959 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK (0x2U)
50960 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT (1U)
50961 /*! SLEEP_HOLD_EN - Allow cpu_sleep_hold_req assert during CPU low power status
50962  *  0b0..Disable cpu_sleep_hold_req
50963  *  0b1..Allow cpu_sleep_hold_req assert during CPU low power status
50964  */
50965 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK)
50966 
50967 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK (0x4U)
50968 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT (2U)
50969 /*! SLEEP_HOLD_STAT - Status of cpu_sleep_hold_ack_b */
50970 #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK)
50971 
50972 #define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_MASK (0x10U)
50973 #define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_SHIFT (4U)
50974 /*! MASTER_CPU - Master CPU */
50975 #define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU(x)  (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_MASK)
50976 /*! @} */
50977 
50978 /*! @name CM_MODE_CTRL - CPU mode control */
50979 /*! @{ */
50980 
50981 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK (0x3U)
50982 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT (0U)
50983 /*! CPU_MODE_TARGET - The CPU mode the CPU platform should transit to on next sleep event
50984  *  0b00..Stay in RUN mode
50985  *  0b01..Transit to WAIT mode
50986  *  0b10..Transit to STOP mode
50987  *  0b11..Transit to SUSPEND mode
50988  */
50989 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK)
50990 
50991 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_MASK (0x10U)
50992 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT (4U)
50993 /*! WFE_EN - WFE assertion can be sleep event
50994  *  0b0..WFE assertion can not trigger low power
50995  *  0b1..WFE assertion can trigger low power
50996  */
50997 #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_MASK)
50998 /*! @} */
50999 
51000 /*! @name CM_MODE_STAT - CM CPU mode Status */
51001 /*! @{ */
51002 
51003 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK (0x3U)
51004 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT (0U)
51005 /*! CPU_MODE_CURRENT - Current CPU mode
51006  *  0b00..CPU is currently in RUN mode
51007  *  0b01..CPU is currently in WAIT mode
51008  *  0b10..CPU is currently in STOP mode
51009  *  0b11..CPU is currently in SUSPEND mode
51010  */
51011 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK)
51012 
51013 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK (0xCU)
51014 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT (2U)
51015 /*! CPU_MODE_PREVIOUS - Previous CPU mode
51016  *  0b00..CPU was previously in RUN mode
51017  *  0b01..CPU was previously in WAIT mode
51018  *  0b10..CPU was previously in STOP mode
51019  *  0b11..CPU was previously in SUSPEND mode
51020  */
51021 #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK)
51022 /*! @} */
51023 
51024 /*! @name CM_IRQ_WAKEUP_MASK - CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask */
51025 /*! @{ */
51026 
51027 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_MASK (0xFFFFFFFFU)
51028 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_SHIFT (0U)
51029 /*! IRQ_WAKEUP_MASK_0_31 - "1" means the IRQ cannot wakeup CPU platform */
51030 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_MASK)
51031 
51032 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_MASK (0xFFFFFFFFU)
51033 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_SHIFT (0U)
51034 /*! IRQ_WAKEUP_MASK_32_63 - "1" means the IRQ cannot wakeup CPU platform */
51035 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_MASK)
51036 
51037 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_MASK (0xFFFFFFFFU)
51038 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_SHIFT (0U)
51039 /*! IRQ_WAKEUP_MASK_64_95 - "1" means the IRQ cannot wakeup CPU platform */
51040 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_MASK)
51041 
51042 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_MASK (0xFFFFFFFFU)
51043 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_SHIFT (0U)
51044 /*! IRQ_WAKEUP_MASK_96_127 - "1" means the IRQ cannot wakeup CPU platform */
51045 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_MASK)
51046 
51047 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_MASK (0xFFFFFFFFU)
51048 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_SHIFT (0U)
51049 /*! IRQ_WAKEUP_MASK_128_159 - "1" means the IRQ cannot wakeup CPU platform */
51050 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_MASK)
51051 
51052 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_MASK (0xFFFFFFFFU)
51053 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_SHIFT (0U)
51054 /*! IRQ_WAKEUP_MASK_160_191 - "1" means the IRQ cannot wakeup CPU platform */
51055 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_MASK)
51056 
51057 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_MASK (0xFFFFFFFFU)
51058 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_SHIFT (0U)
51059 /*! IRQ_WAKEUP_MASK_192_223 - "1" means the IRQ cannot wakeup CPU platform */
51060 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_MASK)
51061 
51062 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU)
51063 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_SHIFT (0U)
51064 /*! IRQ_WAKEUP_MASK_224_255 - "1" means the IRQ cannot wakeup CPU platform */
51065 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_MASK)
51066 /*! @} */
51067 
51068 /* The count of GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK */
51069 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_COUNT (8U)
51070 
51071 /*! @name CM_NON_IRQ_WAKEUP_MASK - CM non-irq wakeup mask */
51072 /*! @{ */
51073 
51074 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK (0x1U)
51075 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT (0U)
51076 /*! EVENT_WAKEUP_MASK - There are 256 interrupts and 1 event as a wakeup source for GPC. This field masks the 1 event wakeup source.
51077  *  0b1..The event cannot wakeup CPU platform
51078  */
51079 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK)
51080 
51081 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK (0x2U)
51082 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT (1U)
51083 /*! DEBUG_WAKEUP_MASK - "1" means the debug_wakeup_request cannot wakeup CPU platform */
51084 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK)
51085 /*! @} */
51086 
51087 /*! @name CM_IRQ_WAKEUP_STAT - CM IRQ0~31 wakeup status..CM IRQ224~255 wakeup status */
51088 /*! @{ */
51089 
51090 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU)
51091 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_SHIFT (0U)
51092 /*! IRQ_WAKEUP_MASK_224_255 - IRQ status
51093  *  0b00000000000000000000000000000000..None
51094  *  0b00000000000000000000000000000001..Valid
51095  */
51096 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_MASK)
51097 
51098 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_MASK (0xFFFFFFFFU)
51099 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_SHIFT (0U)
51100 /*! IRQ_WAKEUP_STAT_0_31 - IRQ status
51101  *  0b00000000000000000000000000000000..None
51102  *  0b00000000000000000000000000000001..Valid
51103  */
51104 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_MASK)
51105 
51106 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_MASK (0xFFFFFFFFU)
51107 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_SHIFT (0U)
51108 /*! IRQ_WAKEUP_STAT_32_63 - IRQ status
51109  *  0b00000000000000000000000000000000..None
51110  *  0b00000000000000000000000000000001..Valid
51111  */
51112 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_MASK)
51113 
51114 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_MASK (0xFFFFFFFFU)
51115 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_SHIFT (0U)
51116 /*! IRQ_WAKEUP_STAT_64_95 - IRQ status
51117  *  0b00000000000000000000000000000000..None
51118  *  0b00000000000000000000000000000001..Valid
51119  */
51120 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_MASK)
51121 
51122 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_MASK (0xFFFFFFFFU)
51123 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_SHIFT (0U)
51124 /*! IRQ_WAKEUP_STAT_96_127 - IRQ status
51125  *  0b00000000000000000000000000000000..None
51126  *  0b00000000000000000000000000000001..Valid
51127  */
51128 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_MASK)
51129 
51130 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_MASK (0xFFFFFFFFU)
51131 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_SHIFT (0U)
51132 /*! IRQ_WAKEUP_STAT_128_159 - IRQ status
51133  *  0b00000000000000000000000000000000..None
51134  *  0b00000000000000000000000000000001..Valid
51135  */
51136 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_MASK)
51137 
51138 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_MASK (0xFFFFFFFFU)
51139 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_SHIFT (0U)
51140 /*! IRQ_WAKEUP_STAT_160_191 - IRQ status
51141  *  0b00000000000000000000000000000000..None
51142  *  0b00000000000000000000000000000001..Valid
51143  */
51144 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_MASK)
51145 
51146 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_MASK (0xFFFFFFFFU)
51147 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_SHIFT (0U)
51148 /*! IRQ_WAKEUP_STAT_192_223 - IRQ status
51149  *  0b00000000000000000000000000000000..None
51150  *  0b00000000000000000000000000000001..Valid
51151  */
51152 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_MASK)
51153 /*! @} */
51154 
51155 /* The count of GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT */
51156 #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_COUNT (8U)
51157 
51158 /*! @name CM_NON_IRQ_WAKEUP_STAT - CM non-irq wakeup status */
51159 /*! @{ */
51160 
51161 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK (0x1U)
51162 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT (0U)
51163 /*! EVENT_WAKEUP_STAT - Event wakeup status
51164  *  0b1..Interrupt is asserting (pending)
51165  */
51166 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK)
51167 
51168 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK (0x2U)
51169 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT (1U)
51170 /*! DEBUG_WAKEUP_STAT - Debug wakeup status */
51171 #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK)
51172 /*! @} */
51173 
51174 /*! @name CM_SLEEP_SSAR_CTRL - CM sleep SSAR control */
51175 /*! @{ */
51176 
51177 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFU)
51178 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT (0U)
51179 /*! STEP_CNT - Step count, useage is depending on CNT_MODE. */
51180 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK)
51181 
51182 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U)
51183 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT (28U)
51184 /*! CNT_MODE - Count mode
51185  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
51186  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
51187  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
51188  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
51189  */
51190 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK)
51191 
51192 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK (0x80000000U)
51193 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT (31U)
51194 /*! DISABLE - Disable this step */
51195 #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK)
51196 /*! @} */
51197 
51198 /*! @name CM_SLEEP_LPCG_CTRL - CM sleep LPCG control */
51199 /*! @{ */
51200 
51201 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFU)
51202 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT (0U)
51203 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
51204 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK)
51205 
51206 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U)
51207 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT (28U)
51208 /*! CNT_MODE - Count mode
51209  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
51210  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
51211  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
51212  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
51213  */
51214 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK)
51215 
51216 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK (0x80000000U)
51217 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT (31U)
51218 /*! DISABLE - Disable this step */
51219 #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK)
51220 /*! @} */
51221 
51222 /*! @name CM_SLEEP_PLL_CTRL - CM sleep PLL control */
51223 /*! @{ */
51224 
51225 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK (0xFFFFU)
51226 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT (0U)
51227 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
51228 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK)
51229 
51230 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK (0x30000000U)
51231 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT (28U)
51232 /*! CNT_MODE - Count mode
51233  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
51234  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
51235  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
51236  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
51237  */
51238 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK)
51239 
51240 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK (0x80000000U)
51241 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT (31U)
51242 /*! DISABLE - Disable this step */
51243 #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK)
51244 /*! @} */
51245 
51246 /*! @name CM_SLEEP_ISO_CTRL - CM sleep isolation control */
51247 /*! @{ */
51248 
51249 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK (0xFFFFU)
51250 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT (0U)
51251 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
51252 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK)
51253 
51254 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK (0x30000000U)
51255 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT (28U)
51256 /*! CNT_MODE - Count mode
51257  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
51258  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
51259  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
51260  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
51261  */
51262 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK)
51263 
51264 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK (0x80000000U)
51265 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT (31U)
51266 /*! DISABLE - Disable this step */
51267 #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK)
51268 /*! @} */
51269 
51270 /*! @name CM_SLEEP_RESET_CTRL - CM sleep reset control */
51271 /*! @{ */
51272 
51273 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK (0xFFFFU)
51274 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT (0U)
51275 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
51276 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK)
51277 
51278 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK (0x30000000U)
51279 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT (28U)
51280 /*! CNT_MODE - Count mode
51281  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
51282  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
51283  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
51284  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
51285  */
51286 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK)
51287 
51288 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK (0x80000000U)
51289 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT (31U)
51290 /*! DISABLE - Disable this step */
51291 #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK)
51292 /*! @} */
51293 
51294 /*! @name CM_SLEEP_POWER_CTRL - CM sleep power control */
51295 /*! @{ */
51296 
51297 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK (0xFFFFU)
51298 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT (0U)
51299 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
51300 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK)
51301 
51302 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK (0x30000000U)
51303 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT (28U)
51304 /*! CNT_MODE - Count mode
51305  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
51306  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
51307  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
51308  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
51309  */
51310 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK)
51311 
51312 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK (0x80000000U)
51313 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT (31U)
51314 /*! DISABLE - Disable this step */
51315 #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK)
51316 /*! @} */
51317 
51318 /*! @name CM_WAKEUP_POWER_CTRL - CM wakeup power control */
51319 /*! @{ */
51320 
51321 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK (0xFFFFU)
51322 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT (0U)
51323 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
51324 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK)
51325 
51326 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK (0x30000000U)
51327 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT (28U)
51328 /*! CNT_MODE - Count mode
51329  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
51330  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
51331  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
51332  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
51333  */
51334 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK)
51335 
51336 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK (0x80000000U)
51337 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT (31U)
51338 /*! DISABLE - Disable this step */
51339 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK)
51340 /*! @} */
51341 
51342 /*! @name CM_WAKEUP_RESET_CTRL - CM wakeup reset control */
51343 /*! @{ */
51344 
51345 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK (0xFFFFU)
51346 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT (0U)
51347 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
51348 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK)
51349 
51350 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK (0x30000000U)
51351 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT (28U)
51352 /*! CNT_MODE - Count mode
51353  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
51354  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
51355  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
51356  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
51357  */
51358 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK)
51359 
51360 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK (0x80000000U)
51361 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT (31U)
51362 /*! DISABLE - Disable this step */
51363 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK)
51364 /*! @} */
51365 
51366 /*! @name CM_WAKEUP_ISO_CTRL - CM wakeup isolation control */
51367 /*! @{ */
51368 
51369 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK (0xFFFFU)
51370 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT (0U)
51371 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
51372 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK)
51373 
51374 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK (0x30000000U)
51375 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT (28U)
51376 /*! CNT_MODE - Count mode
51377  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
51378  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
51379  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
51380  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
51381  */
51382 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK)
51383 
51384 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK (0x80000000U)
51385 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT (31U)
51386 /*! DISABLE - Disable this step */
51387 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK)
51388 /*! @} */
51389 
51390 /*! @name CM_WAKEUP_PLL_CTRL - CM wakeup PLL control */
51391 /*! @{ */
51392 
51393 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK (0xFFFFU)
51394 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT (0U)
51395 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
51396 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK)
51397 
51398 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK (0x30000000U)
51399 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT (28U)
51400 /*! CNT_MODE - Count mode
51401  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
51402  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
51403  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
51404  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
51405  */
51406 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK)
51407 
51408 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK (0x80000000U)
51409 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT (31U)
51410 /*! DISABLE - Disable this step */
51411 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK)
51412 /*! @} */
51413 
51414 /*! @name CM_WAKEUP_LPCG_CTRL - CM wakeup LPCG control */
51415 /*! @{ */
51416 
51417 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFU)
51418 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT (0U)
51419 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
51420 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK)
51421 
51422 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U)
51423 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT (28U)
51424 /*! CNT_MODE - Count mode
51425  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
51426  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
51427  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
51428  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
51429  */
51430 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK)
51431 
51432 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK (0x80000000U)
51433 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT (31U)
51434 /*! DISABLE - Disable this step */
51435 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK)
51436 /*! @} */
51437 
51438 /*! @name CM_WAKEUP_SSAR_CTRL - CM wakeup SSAR control */
51439 /*! @{ */
51440 
51441 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFU)
51442 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT (0U)
51443 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
51444 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK)
51445 
51446 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U)
51447 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT (28U)
51448 /*! CNT_MODE - Count mode
51449  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
51450  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
51451  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
51452  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
51453  */
51454 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK)
51455 
51456 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK (0x80000000U)
51457 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT (31U)
51458 /*! DISABLE - Disable this step */
51459 #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK)
51460 /*! @} */
51461 
51462 /*! @name CM_SP_CTRL - CM Setpoint Control */
51463 /*! @{ */
51464 
51465 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK (0x1U)
51466 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_SHIFT (0U)
51467 /*! CPU_SP_RUN_EN - Request a Setpoint transition when this bit is set */
51468 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK)
51469 
51470 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK (0x1EU)
51471 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_SHIFT (1U)
51472 /*! CPU_SP_RUN - The Setpoint that CPU want the system to transit to when CPU_SP_RUN_EN is set */
51473 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK)
51474 
51475 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK (0x20U)
51476 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_SHIFT (5U)
51477 /*! CPU_SP_SLEEP_EN - 1 means enable Setpoint transition on next CPU platform sleep sequence */
51478 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK)
51479 
51480 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK (0x3C0U)
51481 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_SHIFT (6U)
51482 /*! CPU_SP_SLEEP - The Setpoint that CPU want the system to transit to on next CPU platform sleep sequence */
51483 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK)
51484 
51485 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK (0x400U)
51486 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_SHIFT (10U)
51487 /*! CPU_SP_WAKEUP_EN - 1 means enable Setpoint transition on next CPU platform wakeup sequence */
51488 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK)
51489 
51490 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK (0x7800U)
51491 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT (11U)
51492 /*! CPU_SP_WAKEUP - The Setpoint that CPU want the system to transit to on next CPU platform wakeup sequence */
51493 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK)
51494 
51495 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK (0x8000U)
51496 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_SHIFT (15U)
51497 /*! CPU_SP_WAKEUP_SEL - Select the Setpoint transiton on the next CPU platform wakeup sequence
51498  *  0b0..Request SP transition to CPU_SP_WAKEUP
51499  *  0b1..Request SP transition to the Setpoint when the sleep event happens, which is captured in CPU_SP_PREVIOUS
51500  */
51501 #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK)
51502 /*! @} */
51503 
51504 /*! @name CM_SP_STAT - CM Setpoint Status */
51505 /*! @{ */
51506 
51507 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_MASK (0xFU)
51508 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT (0U)
51509 /*! CPU_SP_CURRENT - The current Setpoint of the system */
51510 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_MASK)
51511 
51512 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_MASK (0xF0U)
51513 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_SHIFT (4U)
51514 /*! CPU_SP_PREVIOUS - The previous Setpoint of the system */
51515 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_MASK)
51516 
51517 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_MASK (0xF00U)
51518 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_SHIFT (8U)
51519 /*! CPU_SP_TARGET - The requested Setpoint from the CPU platform */
51520 #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_MASK)
51521 /*! @} */
51522 
51523 /*! @name CM_RUN_MODE_MAPPING - CM Run Mode Setpoint Allowed */
51524 /*! @{ */
51525 
51526 #define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_MASK (0xFFFFU)
51527 #define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_SHIFT (0U)
51528 /*! CPU_RUN_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters RUN mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG field */
51529 #define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_MASK)
51530 /*! @} */
51531 
51532 /*! @name CM_WAIT_MODE_MAPPING - CM Wait Mode Setpoint Allowed */
51533 /*! @{ */
51534 
51535 #define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_MASK (0xFFFFU)
51536 #define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_SHIFT (0U)
51537 /*! CPU_WAIT_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters WAIT mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG */
51538 #define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_MASK)
51539 /*! @} */
51540 
51541 /*! @name CM_STOP_MODE_MAPPING - CM Stop Mode Setpoint Allowed */
51542 /*! @{ */
51543 
51544 #define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_MASK (0xFFFFU)
51545 #define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_SHIFT (0U)
51546 /*! CPU_STOP_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters STOP mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG */
51547 #define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_MASK)
51548 /*! @} */
51549 
51550 /*! @name CM_SUSPEND_MODE_MAPPING - CM Suspend Mode Setpoint Allowed */
51551 /*! @{ */
51552 
51553 #define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_MASK (0xFFFFU)
51554 #define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_SHIFT (0U)
51555 /*! CPU_SUSPEND_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters SUSPEND mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG */
51556 #define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_MASK)
51557 /*! @} */
51558 
51559 /*! @name CM_SP_MAPPING - CM Setpoint 0 Mapping..CM Setpoint 15 Mapping */
51560 /*! @{ */
51561 
51562 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_MASK (0xFFFFU)
51563 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_SHIFT (0U)
51564 /*! CPU_SP0_MAPPING - Defines when SP0 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51565 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_MASK)
51566 
51567 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_MASK (0xFFFFU)
51568 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_SHIFT (0U)
51569 /*! CPU_SP1_MAPPING - Defines when SP1 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51570 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_MASK)
51571 
51572 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_MASK (0xFFFFU)
51573 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_SHIFT (0U)
51574 /*! CPU_SP2_MAPPING - Defines when SP2 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51575 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_MASK)
51576 
51577 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_MASK (0xFFFFU)
51578 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_SHIFT (0U)
51579 /*! CPU_SP3_MAPPING - Defines when SP3 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51580 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_MASK)
51581 
51582 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_MASK (0xFFFFU)
51583 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_SHIFT (0U)
51584 /*! CPU_SP4_MAPPING - Defines when SP4 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51585 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_MASK)
51586 
51587 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_MASK (0xFFFFU)
51588 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_SHIFT (0U)
51589 /*! CPU_SP5_MAPPING - Defines when SP5 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51590 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_MASK)
51591 
51592 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_MASK (0xFFFFU)
51593 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_SHIFT (0U)
51594 /*! CPU_SP6_MAPPING - Defines when SP6 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51595 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_MASK)
51596 
51597 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_MASK (0xFFFFU)
51598 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_SHIFT (0U)
51599 /*! CPU_SP7_MAPPING - Defines when SP7 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51600 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_MASK)
51601 
51602 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_MASK (0xFFFFU)
51603 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_SHIFT (0U)
51604 /*! CPU_SP8_MAPPING - Defines when SP8 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51605 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_MASK)
51606 
51607 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_MASK (0xFFFFU)
51608 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_SHIFT (0U)
51609 /*! CPU_SP9_MAPPING - Defines when SP9 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51610 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_MASK)
51611 
51612 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_MASK (0xFFFFU)
51613 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_SHIFT (0U)
51614 /*! CPU_SP10_MAPPING - Defines when SP10 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51615 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_MASK)
51616 
51617 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_MASK (0xFFFFU)
51618 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_SHIFT (0U)
51619 /*! CPU_SP11_MAPPING - Defines when SP11 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51620 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_MASK)
51621 
51622 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_MASK (0xFFFFU)
51623 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_SHIFT (0U)
51624 /*! CPU_SP12_MAPPING - Defines when SP12 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51625 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_MASK)
51626 
51627 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_MASK (0xFFFFU)
51628 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_SHIFT (0U)
51629 /*! CPU_SP13_MAPPING - Defines when SP13 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51630 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_MASK)
51631 
51632 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_MASK (0xFFFFU)
51633 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_SHIFT (0U)
51634 /*! CPU_SP14_MAPPING - Defines when SP14 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51635 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_MASK)
51636 
51637 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_MASK (0xFFFFU)
51638 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_SHIFT (0U)
51639 /*! CPU_SP15_MAPPING - Defines when SP15 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */
51640 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_MASK)
51641 /*! @} */
51642 
51643 /* The count of GPC_CPU_MODE_CTRL_CM_SP_MAPPING */
51644 #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_COUNT    (16U)
51645 
51646 /*! @name CM_STBY_CTRL - CM standby control */
51647 /*! @{ */
51648 
51649 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK (0x1U)
51650 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_SHIFT (0U)
51651 /*! STBY_WAIT - 0x1: Request the chip into standby mode when CPU entering WAIT mode, locked by LOCK_CFG field. */
51652 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK)
51653 
51654 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK (0x2U)
51655 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_SHIFT (1U)
51656 /*! STBY_STOP - 0x1: Request the chip into standby mode when CPU entering STOP mode, locked by LOCK_CFG field. */
51657 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK)
51658 
51659 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK (0x4U)
51660 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_SHIFT (2U)
51661 /*! STBY_SUSPEND - 0x1: Request the chip into standby mode when CPU entering SUSPEND mode, locked by LOCK_CFG field. */
51662 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK)
51663 
51664 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK (0x10000U)
51665 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT (16U)
51666 /*! STBY_SLEEP_BUSY - Indicate the CPU is busy entering standby mode. */
51667 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK)
51668 
51669 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK (0x20000U)
51670 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT (17U)
51671 /*! STBY_WAKEUP_BUSY - Indicate the CPU is busy exiting standby mode. */
51672 #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK)
51673 /*! @} */
51674 
51675 
51676 /*!
51677  * @}
51678  */ /* end of group GPC_CPU_MODE_CTRL_Register_Masks */
51679 
51680 
51681 /* GPC_CPU_MODE_CTRL - Peripheral instance base addresses */
51682 /** Peripheral GPC_CPU_MODE_CTRL_0 base address */
51683 #define GPC_CPU_MODE_CTRL_0_BASE                 (0x40C00000u)
51684 /** Peripheral GPC_CPU_MODE_CTRL_0 base pointer */
51685 #define GPC_CPU_MODE_CTRL_0                      ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_0_BASE)
51686 /** Peripheral GPC_CPU_MODE_CTRL_1 base address */
51687 #define GPC_CPU_MODE_CTRL_1_BASE                 (0x40C00800u)
51688 /** Peripheral GPC_CPU_MODE_CTRL_1 base pointer */
51689 #define GPC_CPU_MODE_CTRL_1                      ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
51690 /** Array initializer of GPC_CPU_MODE_CTRL peripheral base addresses */
51691 #define GPC_CPU_MODE_CTRL_BASE_ADDRS             { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
51692 /** Array initializer of GPC_CPU_MODE_CTRL peripheral base pointers */
51693 #define GPC_CPU_MODE_CTRL_BASE_PTRS              { GPC_CPU_MODE_CTRL_0, GPC_CPU_MODE_CTRL_1 }
51694 
51695 /*!
51696  * @}
51697  */ /* end of group GPC_CPU_MODE_CTRL_Peripheral_Access_Layer */
51698 
51699 
51700 /* ----------------------------------------------------------------------------
51701    -- GPC_SET_POINT_CTRL Peripheral Access Layer
51702    ---------------------------------------------------------------------------- */
51703 
51704 /*!
51705  * @addtogroup GPC_SET_POINT_CTRL_Peripheral_Access_Layer GPC_SET_POINT_CTRL Peripheral Access Layer
51706  * @{
51707  */
51708 
51709 /** GPC_SET_POINT_CTRL - Register Layout Typedef */
51710 typedef struct {
51711        uint8_t RESERVED_0[4];
51712   __IO uint32_t SP_AUTHEN_CTRL;                    /**< SP Authentication Control, offset: 0x4 */
51713   __IO uint32_t SP_INT_CTRL;                       /**< SP Interrupt Control, offset: 0x8 */
51714        uint8_t RESERVED_1[4];
51715   __I  uint32_t SP_CPU_REQ;                        /**< CPU SP Request, offset: 0x10 */
51716   __I  uint32_t SP_SYS_STAT;                       /**< SP System Status, offset: 0x14 */
51717        uint8_t RESERVED_2[4];
51718   __IO uint32_t SP_ROSC_CTRL;                      /**< SP ROSC Control, offset: 0x1C */
51719        uint8_t RESERVED_3[32];
51720   __IO uint32_t SP_PRIORITY_0_7;                   /**< SP0~7 Priority, offset: 0x40 */
51721   __IO uint32_t SP_PRIORITY_8_15;                  /**< SP8~15 Priority, offset: 0x44 */
51722        uint8_t RESERVED_4[184];
51723   __IO uint32_t SP_SSAR_SAVE_CTRL;                 /**< SP SSAR save control, offset: 0x100 */
51724        uint8_t RESERVED_5[12];
51725   __IO uint32_t SP_LPCG_OFF_CTRL;                  /**< SP LPCG off control, offset: 0x110 */
51726        uint8_t RESERVED_6[12];
51727   __IO uint32_t SP_GROUP_DOWN_CTRL;                /**< SP group down control, offset: 0x120 */
51728        uint8_t RESERVED_7[12];
51729   __IO uint32_t SP_ROOT_DOWN_CTRL;                 /**< SP root down control, offset: 0x130 */
51730        uint8_t RESERVED_8[12];
51731   __IO uint32_t SP_PLL_OFF_CTRL;                   /**< SP PLL off control, offset: 0x140 */
51732        uint8_t RESERVED_9[12];
51733   __IO uint32_t SP_ISO_ON_CTRL;                    /**< SP ISO on control, offset: 0x150 */
51734        uint8_t RESERVED_10[12];
51735   __IO uint32_t SP_RESET_EARLY_CTRL;               /**< SP reset early control, offset: 0x160 */
51736        uint8_t RESERVED_11[12];
51737   __IO uint32_t SP_POWER_OFF_CTRL;                 /**< SP power off control, offset: 0x170 */
51738        uint8_t RESERVED_12[12];
51739   __IO uint32_t SP_BIAS_OFF_CTRL;                  /**< SP bias off control, offset: 0x180 */
51740        uint8_t RESERVED_13[12];
51741   __IO uint32_t SP_BG_PLDO_OFF_CTRL;               /**< SP bandgap and PLL_LDO off control, offset: 0x190 */
51742        uint8_t RESERVED_14[12];
51743   __IO uint32_t SP_LDO_PRE_CTRL;                   /**< SP LDO pre control, offset: 0x1A0 */
51744        uint8_t RESERVED_15[12];
51745   __IO uint32_t SP_DCDC_DOWN_CTRL;                 /**< SP DCDC down control, offset: 0x1B0 */
51746        uint8_t RESERVED_16[76];
51747   __IO uint32_t SP_DCDC_UP_CTRL;                   /**< SP DCDC up control, offset: 0x200 */
51748        uint8_t RESERVED_17[12];
51749   __IO uint32_t SP_LDO_POST_CTRL;                  /**< SP LDO post control, offset: 0x210 */
51750        uint8_t RESERVED_18[12];
51751   __IO uint32_t SP_BG_PLDO_ON_CTRL;                /**< SP bandgap and PLL_LDO on control, offset: 0x220 */
51752        uint8_t RESERVED_19[12];
51753   __IO uint32_t SP_BIAS_ON_CTRL;                   /**< SP bias on control, offset: 0x230 */
51754        uint8_t RESERVED_20[12];
51755   __IO uint32_t SP_POWER_ON_CTRL;                  /**< SP power on control, offset: 0x240 */
51756        uint8_t RESERVED_21[12];
51757   __IO uint32_t SP_RESET_LATE_CTRL;                /**< SP reset late control, offset: 0x250 */
51758        uint8_t RESERVED_22[12];
51759   __IO uint32_t SP_ISO_OFF_CTRL;                   /**< SP ISO off control, offset: 0x260 */
51760        uint8_t RESERVED_23[12];
51761   __IO uint32_t SP_PLL_ON_CTRL;                    /**< SP PLL on control, offset: 0x270 */
51762        uint8_t RESERVED_24[12];
51763   __IO uint32_t SP_ROOT_UP_CTRL;                   /**< SP root up control, offset: 0x280 */
51764        uint8_t RESERVED_25[12];
51765   __IO uint32_t SP_GROUP_UP_CTRL;                  /**< SP group up control, offset: 0x290 */
51766        uint8_t RESERVED_26[12];
51767   __IO uint32_t SP_LPCG_ON_CTRL;                   /**< SP LPCG on control, offset: 0x2A0 */
51768        uint8_t RESERVED_27[12];
51769   __IO uint32_t SP_SSAR_RESTORE_CTRL;              /**< SP SSAR restore control, offset: 0x2B0 */
51770 } GPC_SET_POINT_CTRL_Type;
51771 
51772 /* ----------------------------------------------------------------------------
51773    -- GPC_SET_POINT_CTRL Register Masks
51774    ---------------------------------------------------------------------------- */
51775 
51776 /*!
51777  * @addtogroup GPC_SET_POINT_CTRL_Register_Masks GPC_SET_POINT_CTRL Register Masks
51778  * @{
51779  */
51780 
51781 /*! @name SP_AUTHEN_CTRL - SP Authentication Control */
51782 /*! @{ */
51783 
51784 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_MASK (0x1U)
51785 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_SHIFT (0U)
51786 /*! USER - Allow user mode access
51787  *  0b0..Allow only privilege mode to access setpoint control registers
51788  *  0b1..Allow both privilege and user mode to access setpoint control registers
51789  */
51790 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_MASK)
51791 
51792 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
51793 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
51794 /*! NONSECURE - Allow non-secure mode access
51795  *  0b0..Allow only secure mode to access setpoint control registers
51796  *  0b1..Allow both secure and non-secure mode to access setpoint control registers
51797  */
51798 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_MASK)
51799 
51800 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
51801 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
51802 /*! LOCK_SETTING - Lock NONSECURE and USER */
51803 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_MASK)
51804 
51805 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
51806 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
51807 /*! WHITE_LIST - Domain ID white list */
51808 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_MASK)
51809 
51810 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
51811 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
51812 /*! LOCK_LIST - White list lock */
51813 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_MASK)
51814 
51815 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
51816 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
51817 /*! LOCK_CFG - Configuration lock */
51818 #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_MASK)
51819 /*! @} */
51820 
51821 /*! @name SP_INT_CTRL - SP Interrupt Control */
51822 /*! @{ */
51823 
51824 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_MASK (0x1U)
51825 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_SHIFT (0U)
51826 /*! NO_ALLOWED_SP_INT_EN - no_allowed_set_point interrupt enable */
51827 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_SHIFT)) & GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_MASK)
51828 
51829 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_MASK (0x2U)
51830 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_SHIFT (1U)
51831 /*! NO_ALLOWED_SP_INT - no_allowed_set_point interrupt */
51832 #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_SHIFT)) & GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_MASK)
51833 /*! @} */
51834 
51835 /*! @name SP_CPU_REQ - CPU SP Request */
51836 /*! @{ */
51837 
51838 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_MASK (0xFU)
51839 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_SHIFT (0U)
51840 /*! SP_REQ_CPU0 - Setpoint requested by CPU0 */
51841 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_MASK)
51842 
51843 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_MASK (0xF0U)
51844 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_SHIFT (4U)
51845 /*! SP_REQ_CPU1 - Setpoint requested by CPU1 */
51846 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_MASK)
51847 
51848 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_MASK (0xF00U)
51849 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_SHIFT (8U)
51850 /*! SP_REQ_CPU2 - Setpoint requested by CPU2 */
51851 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_MASK)
51852 
51853 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_MASK (0xF000U)
51854 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_SHIFT (12U)
51855 /*! SP_REQ_CPU3 - Setpoint requested by CPU3 */
51856 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_MASK)
51857 
51858 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_MASK (0xF0000U)
51859 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_SHIFT (16U)
51860 /*! SP_ACCEPTED_CPU0 - CPU0 Setpoint accepted by SP controller */
51861 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_MASK)
51862 
51863 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_MASK (0xF00000U)
51864 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_SHIFT (20U)
51865 /*! SP_ACCEPTED_CPU1 - CPU1 Setpoint accepted by SP controller */
51866 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_MASK)
51867 
51868 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_MASK (0xF000000U)
51869 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_SHIFT (24U)
51870 /*! SP_ACCEPTED_CPU2 - CPU2 Setpoint accepted by SP controller */
51871 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_MASK)
51872 
51873 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_MASK (0xF0000000U)
51874 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_SHIFT (28U)
51875 /*! SP_ACCEPTED_CPU3 - CPU3 Setpoint accepted by SP controller */
51876 #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_MASK)
51877 /*! @} */
51878 
51879 /*! @name SP_SYS_STAT - SP System Status */
51880 /*! @{ */
51881 
51882 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_MASK (0xFFFFU)
51883 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_SHIFT (0U)
51884 /*! SYS_SP_ALLOWED - Allowed Setpoints by all current CPU Setpoint requests */
51885 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_MASK)
51886 
51887 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK (0xF0000U)
51888 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT (16U)
51889 /*! SYS_SP_TARGET - The Setpoint chosen as the target setpoint */
51890 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK)
51891 
51892 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK (0xF00000U)
51893 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT (20U)
51894 /*! SYS_SP_CURRENT - Current Setpoint, only valid when not SP trans busy */
51895 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK)
51896 
51897 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK (0xF000000U)
51898 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT (24U)
51899 /*! SYS_SP_PREVIOUS - Previous Setpoint, only valid when not SP trans busy */
51900 #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK)
51901 /*! @} */
51902 
51903 /*! @name SP_ROSC_CTRL - SP ROSC Control */
51904 /*! @{ */
51905 
51906 #define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_MASK (0xFFFFU)
51907 #define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_SHIFT (0U)
51908 /*! SP_ALLOW_ROSC_OFF - Allow shutting off the ROSC */
51909 #define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_MASK)
51910 /*! @} */
51911 
51912 /*! @name SP_PRIORITY_0_7 - SP0~7 Priority */
51913 /*! @{ */
51914 
51915 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_MASK (0xFU)
51916 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_SHIFT (0U)
51917 /*! SYS_SP0_PRIORITY - priority of Setpoint 0 */
51918 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_MASK)
51919 
51920 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_MASK (0xF0U)
51921 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_SHIFT (4U)
51922 /*! SYS_SP1_PRIORITY - priority of Setpoint 1 */
51923 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_MASK)
51924 
51925 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_MASK (0xF00U)
51926 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_SHIFT (8U)
51927 /*! SYS_SP2_PRIORITY - priority of Setpoint 2 */
51928 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_MASK)
51929 
51930 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_MASK (0xF000U)
51931 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_SHIFT (12U)
51932 /*! SYS_SP3_PRIORITY - priority of Setpoint 3 */
51933 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_MASK)
51934 
51935 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_MASK (0xF0000U)
51936 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_SHIFT (16U)
51937 /*! SYS_SP4_PRIORITY - priority of Setpoint 4 */
51938 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_MASK)
51939 
51940 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_MASK (0xF00000U)
51941 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_SHIFT (20U)
51942 /*! SYS_SP5_PRIORITY - priority of Setpoint 5 */
51943 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_MASK)
51944 
51945 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_MASK (0xF000000U)
51946 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_SHIFT (24U)
51947 /*! SYS_SP6_PRIORITY - priority of Setpoint 6 */
51948 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_MASK)
51949 
51950 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_MASK (0xF0000000U)
51951 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_SHIFT (28U)
51952 /*! SYS_SP7_PRIORITY - priority of Setpoint 7 */
51953 #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_MASK)
51954 /*! @} */
51955 
51956 /*! @name SP_PRIORITY_8_15 - SP8~15 Priority */
51957 /*! @{ */
51958 
51959 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_MASK (0xFU)
51960 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_SHIFT (0U)
51961 /*! SYS_SP8_PRIORITY - priority of Setpoint 8 */
51962 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_MASK)
51963 
51964 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_MASK (0xF0U)
51965 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_SHIFT (4U)
51966 /*! SYS_SP9_PRIORITY - priority of Setpoint 9 */
51967 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_MASK)
51968 
51969 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_MASK (0xF00U)
51970 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_SHIFT (8U)
51971 /*! SYS_SP10_PRIORITY - priority of Setpoint 10 */
51972 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_MASK)
51973 
51974 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_MASK (0xF000U)
51975 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_SHIFT (12U)
51976 /*! SYS_SP11_PRIORITY - priority of Setpoint 11 */
51977 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_MASK)
51978 
51979 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_MASK (0xF0000U)
51980 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_SHIFT (16U)
51981 /*! SYS_SP12_PRIORITY - priority of Setpoint 12 */
51982 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_MASK)
51983 
51984 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_MASK (0xF00000U)
51985 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_SHIFT (20U)
51986 /*! SYS_SP13_PRIORITY - priority of Setpoint 13 */
51987 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_MASK)
51988 
51989 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_MASK (0xF000000U)
51990 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_SHIFT (24U)
51991 /*! SYS_SP14_PRIORITY - priority of Setpoint 14 */
51992 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_MASK)
51993 
51994 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK (0xF0000000U)
51995 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT (28U)
51996 /*! SYS_SP15_PRIORITY - priority of Setpoint 15 */
51997 #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK)
51998 /*! @} */
51999 
52000 /*! @name SP_SSAR_SAVE_CTRL - SP SSAR save control */
52001 /*! @{ */
52002 
52003 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK (0xFFFFU)
52004 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT (0U)
52005 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52006 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK)
52007 
52008 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK (0x30000000U)
52009 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT (28U)
52010 /*! CNT_MODE - Count mode
52011  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52012  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52013  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52014  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52015  */
52016 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK)
52017 
52018 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK (0x80000000U)
52019 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_SHIFT (31U)
52020 /*! DISABLE - Disable this step */
52021 #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK)
52022 /*! @} */
52023 
52024 /*! @name SP_LPCG_OFF_CTRL - SP LPCG off control */
52025 /*! @{ */
52026 
52027 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
52028 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT (0U)
52029 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52030 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK)
52031 
52032 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
52033 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT (28U)
52034 /*! CNT_MODE - Count mode
52035  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52036  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52037  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52038  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52039  */
52040 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_MASK)
52041 
52042 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_MASK (0x80000000U)
52043 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_SHIFT (31U)
52044 /*! DISABLE - Disable this step */
52045 #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_MASK)
52046 /*! @} */
52047 
52048 /*! @name SP_GROUP_DOWN_CTRL - SP group down control */
52049 /*! @{ */
52050 
52051 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU)
52052 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT (0U)
52053 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52054 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK)
52055 
52056 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_MASK (0x30000000U)
52057 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT (28U)
52058 /*! CNT_MODE - Count mode
52059  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52060  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52061  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52062  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52063  */
52064 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_MASK)
52065 
52066 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_MASK (0x80000000U)
52067 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_SHIFT (31U)
52068 /*! DISABLE - Disable this step */
52069 #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_MASK)
52070 /*! @} */
52071 
52072 /*! @name SP_ROOT_DOWN_CTRL - SP root down control */
52073 /*! @{ */
52074 
52075 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU)
52076 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT (0U)
52077 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52078 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK)
52079 
52080 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_MASK (0x30000000U)
52081 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT (28U)
52082 /*! CNT_MODE - Count mode
52083  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52084  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52085  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52086  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52087  */
52088 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_MASK)
52089 
52090 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_MASK (0x80000000U)
52091 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_SHIFT (31U)
52092 /*! DISABLE - Disable this step */
52093 #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_MASK)
52094 /*! @} */
52095 
52096 /*! @name SP_PLL_OFF_CTRL - SP PLL off control */
52097 /*! @{ */
52098 
52099 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
52100 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT (0U)
52101 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52102 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK)
52103 
52104 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
52105 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT (28U)
52106 /*! CNT_MODE - Count mode
52107  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52108  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52109  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52110  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52111  */
52112 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_MASK)
52113 
52114 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_MASK (0x80000000U)
52115 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_SHIFT (31U)
52116 /*! DISABLE - Disable this step */
52117 #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_MASK)
52118 /*! @} */
52119 
52120 /*! @name SP_ISO_ON_CTRL - SP ISO on control */
52121 /*! @{ */
52122 
52123 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
52124 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT (0U)
52125 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52126 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK)
52127 
52128 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_MASK (0x30000000U)
52129 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT (28U)
52130 /*! CNT_MODE - Count mode
52131  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52132  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52133  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52134  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52135  */
52136 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_MASK)
52137 
52138 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_MASK (0x80000000U)
52139 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_SHIFT (31U)
52140 /*! DISABLE - Disable this step */
52141 #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_MASK)
52142 /*! @} */
52143 
52144 /*! @name SP_RESET_EARLY_CTRL - SP reset early control */
52145 /*! @{ */
52146 
52147 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK (0xFFFFU)
52148 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT (0U)
52149 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52150 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK)
52151 
52152 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_MASK (0x30000000U)
52153 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT (28U)
52154 /*! CNT_MODE - Count mode
52155  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52156  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52157  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52158  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52159  */
52160 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_MASK)
52161 
52162 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_MASK (0x80000000U)
52163 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_SHIFT (31U)
52164 /*! DISABLE - Disable this step */
52165 #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_MASK)
52166 /*! @} */
52167 
52168 /*! @name SP_POWER_OFF_CTRL - SP power off control */
52169 /*! @{ */
52170 
52171 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
52172 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT (0U)
52173 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52174 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK)
52175 
52176 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
52177 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT (28U)
52178 /*! CNT_MODE - Count mode
52179  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52180  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52181  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52182  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52183  */
52184 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_MASK)
52185 
52186 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_MASK (0x80000000U)
52187 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_SHIFT (31U)
52188 /*! DISABLE - Disable this step */
52189 #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_MASK)
52190 /*! @} */
52191 
52192 /*! @name SP_BIAS_OFF_CTRL - SP bias off control */
52193 /*! @{ */
52194 
52195 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
52196 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT (0U)
52197 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52198 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK)
52199 
52200 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
52201 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT (28U)
52202 /*! CNT_MODE - Count mode
52203  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52204  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52205  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52206  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52207  */
52208 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_MASK)
52209 
52210 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_MASK (0x80000000U)
52211 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_SHIFT (31U)
52212 /*! DISABLE - Disable this step */
52213 #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_MASK)
52214 /*! @} */
52215 
52216 /*! @name SP_BG_PLDO_OFF_CTRL - SP bandgap and PLL_LDO off control */
52217 /*! @{ */
52218 
52219 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
52220 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT (0U)
52221 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52222 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK)
52223 
52224 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
52225 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT (28U)
52226 /*! CNT_MODE - Count mode
52227  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52228  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52229  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52230  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52231  */
52232 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_MASK)
52233 
52234 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_MASK (0x80000000U)
52235 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_SHIFT (31U)
52236 /*! DISABLE - Disable this step */
52237 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_MASK)
52238 /*! @} */
52239 
52240 /*! @name SP_LDO_PRE_CTRL - SP LDO pre control */
52241 /*! @{ */
52242 
52243 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK (0xFFFFU)
52244 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT (0U)
52245 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52246 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK)
52247 
52248 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_MASK (0x30000000U)
52249 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT (28U)
52250 /*! CNT_MODE - Count mode
52251  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52252  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52253  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52254  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52255  */
52256 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_MASK)
52257 
52258 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_MASK (0x80000000U)
52259 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_SHIFT (31U)
52260 /*! DISABLE - Disable this step */
52261 #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_MASK)
52262 /*! @} */
52263 
52264 /*! @name SP_DCDC_DOWN_CTRL - SP DCDC down control */
52265 /*! @{ */
52266 
52267 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU)
52268 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT (0U)
52269 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52270 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK)
52271 
52272 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_MASK (0x30000000U)
52273 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT (28U)
52274 /*! CNT_MODE - Count mode
52275  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52276  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52277  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52278  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52279  */
52280 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_MASK)
52281 
52282 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_MASK (0x80000000U)
52283 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_SHIFT (31U)
52284 /*! DISABLE - Disable this step */
52285 #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_MASK)
52286 /*! @} */
52287 
52288 /*! @name SP_DCDC_UP_CTRL - SP DCDC up control */
52289 /*! @{ */
52290 
52291 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK (0xFFFFU)
52292 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT (0U)
52293 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52294 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK)
52295 
52296 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_MASK (0x30000000U)
52297 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT (28U)
52298 /*! CNT_MODE - Count mode
52299  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52300  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52301  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52302  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52303  */
52304 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_MASK)
52305 
52306 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_MASK (0x80000000U)
52307 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_SHIFT (31U)
52308 /*! DISABLE - Disable this step */
52309 #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_MASK)
52310 /*! @} */
52311 
52312 /*! @name SP_LDO_POST_CTRL - SP LDO post control */
52313 /*! @{ */
52314 
52315 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK (0xFFFFU)
52316 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT (0U)
52317 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52318 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK)
52319 
52320 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_MASK (0x30000000U)
52321 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT (28U)
52322 /*! CNT_MODE - Count mode
52323  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52324  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52325  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52326  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52327  */
52328 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_MASK)
52329 
52330 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_MASK (0x80000000U)
52331 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_SHIFT (31U)
52332 /*! DISABLE - Disable this step */
52333 #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_MASK)
52334 /*! @} */
52335 
52336 /*! @name SP_BG_PLDO_ON_CTRL - SP bandgap and PLL_LDO on control */
52337 /*! @{ */
52338 
52339 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
52340 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT (0U)
52341 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52342 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK)
52343 
52344 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_MASK (0x30000000U)
52345 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT (28U)
52346 /*! CNT_MODE - Count mode
52347  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52348  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52349  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52350  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52351  */
52352 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_MASK)
52353 
52354 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_MASK (0x80000000U)
52355 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_SHIFT (31U)
52356 /*! DISABLE - Disable this step */
52357 #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_MASK)
52358 /*! @} */
52359 
52360 /*! @name SP_BIAS_ON_CTRL - SP bias on control */
52361 /*! @{ */
52362 
52363 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
52364 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT (0U)
52365 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52366 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK)
52367 
52368 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_MASK (0x30000000U)
52369 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT (28U)
52370 /*! CNT_MODE - Count mode
52371  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52372  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52373  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52374  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52375  */
52376 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_MASK)
52377 
52378 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_MASK (0x80000000U)
52379 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_SHIFT (31U)
52380 /*! DISABLE - Disable this step */
52381 #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_MASK)
52382 /*! @} */
52383 
52384 /*! @name SP_POWER_ON_CTRL - SP power on control */
52385 /*! @{ */
52386 
52387 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
52388 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT (0U)
52389 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52390 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK)
52391 
52392 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_MASK (0x30000000U)
52393 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT (28U)
52394 /*! CNT_MODE - Count mode
52395  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52396  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52397  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52398  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52399  */
52400 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_MASK)
52401 
52402 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_MASK (0x80000000U)
52403 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_SHIFT (31U)
52404 /*! DISABLE - Disable this step */
52405 #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_MASK)
52406 /*! @} */
52407 
52408 /*! @name SP_RESET_LATE_CTRL - SP reset late control */
52409 /*! @{ */
52410 
52411 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK (0xFFFFU)
52412 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT (0U)
52413 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52414 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK)
52415 
52416 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_MASK (0x30000000U)
52417 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT (28U)
52418 /*! CNT_MODE - Count mode
52419  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52420  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52421  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52422  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52423  */
52424 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_MASK)
52425 
52426 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_MASK (0x80000000U)
52427 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_SHIFT (31U)
52428 /*! DISABLE - Disable this step */
52429 #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_MASK)
52430 /*! @} */
52431 
52432 /*! @name SP_ISO_OFF_CTRL - SP ISO off control */
52433 /*! @{ */
52434 
52435 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
52436 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT (0U)
52437 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52438 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK)
52439 
52440 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
52441 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT (28U)
52442 /*! CNT_MODE - Count mode
52443  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52444  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52445  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52446  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52447  */
52448 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_MASK)
52449 
52450 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_MASK (0x80000000U)
52451 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_SHIFT (31U)
52452 /*! DISABLE - Disable this step */
52453 #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_MASK)
52454 /*! @} */
52455 
52456 /*! @name SP_PLL_ON_CTRL - SP PLL on control */
52457 /*! @{ */
52458 
52459 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
52460 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT (0U)
52461 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52462 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK)
52463 
52464 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_MASK (0x30000000U)
52465 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT (28U)
52466 /*! CNT_MODE - Count mode
52467  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52468  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52469  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52470  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52471  */
52472 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_MASK)
52473 
52474 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_MASK (0x80000000U)
52475 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_SHIFT (31U)
52476 /*! DISABLE - Disable this step */
52477 #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_MASK)
52478 /*! @} */
52479 
52480 /*! @name SP_ROOT_UP_CTRL - SP root up control */
52481 /*! @{ */
52482 
52483 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK (0xFFFFU)
52484 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT (0U)
52485 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52486 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK)
52487 
52488 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_MASK (0x30000000U)
52489 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT (28U)
52490 /*! CNT_MODE - Count mode
52491  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52492  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52493  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52494  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52495  */
52496 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_MASK)
52497 
52498 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_MASK (0x80000000U)
52499 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_SHIFT (31U)
52500 /*! DISABLE - Disable this step */
52501 #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_MASK)
52502 /*! @} */
52503 
52504 /*! @name SP_GROUP_UP_CTRL - SP group up control */
52505 /*! @{ */
52506 
52507 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK (0xFFFFU)
52508 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT (0U)
52509 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52510 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK)
52511 
52512 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_MASK (0x30000000U)
52513 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT (28U)
52514 /*! CNT_MODE - Count mode
52515  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52516  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52517  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52518  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52519  */
52520 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_MASK)
52521 
52522 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_MASK (0x80000000U)
52523 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_SHIFT (31U)
52524 /*! DISABLE - Disable this step */
52525 #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_MASK)
52526 /*! @} */
52527 
52528 /*! @name SP_LPCG_ON_CTRL - SP LPCG on control */
52529 /*! @{ */
52530 
52531 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
52532 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT (0U)
52533 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52534 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK)
52535 
52536 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_MASK (0x30000000U)
52537 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT (28U)
52538 /*! CNT_MODE - Count mode
52539  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52540  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52541  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52542  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52543  */
52544 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_MASK)
52545 
52546 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_MASK (0x80000000U)
52547 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_SHIFT (31U)
52548 /*! DISABLE - Disable this step */
52549 #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_MASK)
52550 /*! @} */
52551 
52552 /*! @name SP_SSAR_RESTORE_CTRL - SP SSAR restore control */
52553 /*! @{ */
52554 
52555 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK (0xFFFFU)
52556 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT (0U)
52557 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52558 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK)
52559 
52560 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_MASK (0x30000000U)
52561 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT (28U)
52562 /*! CNT_MODE - Count mode
52563  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52564  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52565  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52566  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52567  */
52568 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_MASK)
52569 
52570 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_MASK (0x80000000U)
52571 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_SHIFT (31U)
52572 /*! DISABLE - Disable this step */
52573 #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_MASK)
52574 /*! @} */
52575 
52576 
52577 /*!
52578  * @}
52579  */ /* end of group GPC_SET_POINT_CTRL_Register_Masks */
52580 
52581 
52582 /* GPC_SET_POINT_CTRL - Peripheral instance base addresses */
52583 /** Peripheral GPC_SET_POINT_CTRL base address */
52584 #define GPC_SET_POINT_CTRL_BASE                  (0x40C02000u)
52585 /** Peripheral GPC_SET_POINT_CTRL base pointer */
52586 #define GPC_SET_POINT_CTRL                       ((GPC_SET_POINT_CTRL_Type *)GPC_SET_POINT_CTRL_BASE)
52587 /** Array initializer of GPC_SET_POINT_CTRL peripheral base addresses */
52588 #define GPC_SET_POINT_CTRL_BASE_ADDRS            { GPC_SET_POINT_CTRL_BASE }
52589 /** Array initializer of GPC_SET_POINT_CTRL peripheral base pointers */
52590 #define GPC_SET_POINT_CTRL_BASE_PTRS             { GPC_SET_POINT_CTRL }
52591 
52592 /*!
52593  * @}
52594  */ /* end of group GPC_SET_POINT_CTRL_Peripheral_Access_Layer */
52595 
52596 
52597 /* ----------------------------------------------------------------------------
52598    -- GPC_STBY_CTRL Peripheral Access Layer
52599    ---------------------------------------------------------------------------- */
52600 
52601 /*!
52602  * @addtogroup GPC_STBY_CTRL_Peripheral_Access_Layer GPC_STBY_CTRL Peripheral Access Layer
52603  * @{
52604  */
52605 
52606 /** GPC_STBY_CTRL - Register Layout Typedef */
52607 typedef struct {
52608        uint8_t RESERVED_0[4];
52609   __IO uint32_t STBY_AUTHEN_CTRL;                  /**< Standby Authentication Control, offset: 0x4 */
52610        uint8_t RESERVED_1[4];
52611   __IO uint32_t STBY_MISC;                         /**< STBY Misc, offset: 0xC */
52612        uint8_t RESERVED_2[224];
52613   __IO uint32_t STBY_LPCG_IN_CTRL;                 /**< STBY lpcg_in control, offset: 0xF0 */
52614        uint8_t RESERVED_3[12];
52615   __IO uint32_t STBY_PLL_IN_CTRL;                  /**< STBY pll_in control, offset: 0x100 */
52616        uint8_t RESERVED_4[12];
52617   __IO uint32_t STBY_BIAS_IN_CTRL;                 /**< STBY bias_in control, offset: 0x110 */
52618        uint8_t RESERVED_5[12];
52619   __IO uint32_t STBY_PLDO_IN_CTRL;                 /**< STBY pldo_in control, offset: 0x120 */
52620        uint8_t RESERVED_6[4];
52621   __IO uint32_t STBY_BANDGAP_IN_CTRL;              /**< STBY bandgap_in control, offset: 0x128 */
52622        uint8_t RESERVED_7[4];
52623   __IO uint32_t STBY_LDO_IN_CTRL;                  /**< STBY ldo_in control, offset: 0x130 */
52624        uint8_t RESERVED_8[12];
52625   __IO uint32_t STBY_DCDC_IN_CTRL;                 /**< STBY dcdc_in control, offset: 0x140 */
52626        uint8_t RESERVED_9[12];
52627   __IO uint32_t STBY_PMIC_IN_CTRL;                 /**< STBY PMIC in control, offset: 0x150 */
52628        uint8_t RESERVED_10[172];
52629   __IO uint32_t STBY_PMIC_OUT_CTRL;                /**< STBY PMIC out control, offset: 0x200 */
52630        uint8_t RESERVED_11[12];
52631   __IO uint32_t STBY_DCDC_OUT_CTRL;                /**< STBY DCDC out control, offset: 0x210 */
52632        uint8_t RESERVED_12[12];
52633   __IO uint32_t STBY_LDO_OUT_CTRL;                 /**< STBY LDO out control, offset: 0x220 */
52634        uint8_t RESERVED_13[12];
52635   __IO uint32_t STBY_BANDGAP_OUT_CTRL;             /**< STBY bandgap out control, offset: 0x230 */
52636        uint8_t RESERVED_14[4];
52637   __IO uint32_t STBY_PLDO_OUT_CTRL;                /**< STBY pldo out control, offset: 0x238 */
52638        uint8_t RESERVED_15[4];
52639   __IO uint32_t STBY_BIAS_OUT_CTRL;                /**< STBY bias out control, offset: 0x240 */
52640        uint8_t RESERVED_16[12];
52641   __IO uint32_t STBY_PLL_OUT_CTRL;                 /**< STBY PLL out control, offset: 0x250 */
52642        uint8_t RESERVED_17[12];
52643   __IO uint32_t STBY_LPCG_OUT_CTRL;                /**< STBY LPCG out control, offset: 0x260 */
52644 } GPC_STBY_CTRL_Type;
52645 
52646 /* ----------------------------------------------------------------------------
52647    -- GPC_STBY_CTRL Register Masks
52648    ---------------------------------------------------------------------------- */
52649 
52650 /*!
52651  * @addtogroup GPC_STBY_CTRL_Register_Masks GPC_STBY_CTRL Register Masks
52652  * @{
52653  */
52654 
52655 /*! @name STBY_AUTHEN_CTRL - Standby Authentication Control */
52656 /*! @{ */
52657 
52658 #define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
52659 #define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
52660 /*! LOCK_CFG - Configuration lock */
52661 #define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_MASK)
52662 /*! @} */
52663 
52664 /*! @name STBY_MISC - STBY Misc */
52665 /*! @{ */
52666 
52667 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_MASK (0x1U)
52668 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_SHIFT (0U)
52669 /*! FORCE_CPU0_STBY - Force CPU0 requesting standby mode */
52670 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_MASK)
52671 
52672 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_MASK (0x2U)
52673 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_SHIFT (1U)
52674 /*! FORCE_CPU1_STBY - Force CPU0 requesting standby mode */
52675 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_MASK)
52676 
52677 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_MASK (0x4U)
52678 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_SHIFT (2U)
52679 /*! FORCE_CPU2_STBY - Force CPU2 requesting standby mode */
52680 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_MASK)
52681 
52682 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_MASK (0x8U)
52683 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_SHIFT (3U)
52684 /*! FORCE_CPU3_STBY - Force CPU3 requesting standby mode */
52685 #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_MASK)
52686 /*! @} */
52687 
52688 /*! @name STBY_LPCG_IN_CTRL - STBY lpcg_in control */
52689 /*! @{ */
52690 
52691 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
52692 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT (0U)
52693 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52694 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK)
52695 
52696 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK (0x30000000U)
52697 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT (28U)
52698 /*! CNT_MODE - Count mode
52699  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52700  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52701  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52702  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52703  */
52704 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK)
52705 
52706 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK (0x80000000U)
52707 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_SHIFT (31U)
52708 /*! DISABLE - Disable this step */
52709 #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK)
52710 /*! @} */
52711 
52712 /*! @name STBY_PLL_IN_CTRL - STBY pll_in control */
52713 /*! @{ */
52714 
52715 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
52716 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT (0U)
52717 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52718 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK)
52719 
52720 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_MASK (0x30000000U)
52721 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT (28U)
52722 /*! CNT_MODE - Count mode
52723  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52724  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52725  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52726  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52727  */
52728 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_MASK)
52729 
52730 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_MASK (0x80000000U)
52731 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_SHIFT (31U)
52732 /*! DISABLE - Disable this step */
52733 #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_MASK)
52734 /*! @} */
52735 
52736 /*! @name STBY_BIAS_IN_CTRL - STBY bias_in control */
52737 /*! @{ */
52738 
52739 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
52740 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT (0U)
52741 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52742 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK)
52743 
52744 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_MASK (0x30000000U)
52745 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT (28U)
52746 /*! CNT_MODE - Count mode
52747  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52748  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52749  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52750  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52751  */
52752 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_MASK)
52753 
52754 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_MASK (0x80000000U)
52755 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_SHIFT (31U)
52756 /*! DISABLE - Disable this step */
52757 #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_MASK)
52758 /*! @} */
52759 
52760 /*! @name STBY_PLDO_IN_CTRL - STBY pldo_in control */
52761 /*! @{ */
52762 
52763 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
52764 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT (0U)
52765 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52766 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK)
52767 
52768 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_MASK (0x30000000U)
52769 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT (28U)
52770 /*! CNT_MODE - Count mode
52771  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52772  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52773  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52774  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52775  */
52776 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_MASK)
52777 
52778 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_MASK (0x80000000U)
52779 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_SHIFT (31U)
52780 /*! DISABLE - Disable this step */
52781 #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_MASK)
52782 /*! @} */
52783 
52784 /*! @name STBY_BANDGAP_IN_CTRL - STBY bandgap_in control */
52785 /*! @{ */
52786 
52787 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
52788 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT (0U)
52789 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52790 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK)
52791 
52792 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_MASK (0x30000000U)
52793 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT (28U)
52794 /*! CNT_MODE - Count mode
52795  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52796  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52797  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52798  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52799  */
52800 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_MASK)
52801 
52802 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_MASK (0x80000000U)
52803 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_SHIFT (31U)
52804 /*! DISABLE - Disable this step */
52805 #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_MASK)
52806 /*! @} */
52807 
52808 /*! @name STBY_LDO_IN_CTRL - STBY ldo_in control */
52809 /*! @{ */
52810 
52811 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
52812 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT (0U)
52813 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52814 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK)
52815 
52816 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_MASK (0x30000000U)
52817 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT (28U)
52818 /*! CNT_MODE - Count mode
52819  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52820  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52821  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52822  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52823  */
52824 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_MASK)
52825 
52826 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_MASK (0x80000000U)
52827 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_SHIFT (31U)
52828 /*! DISABLE - Disable this step */
52829 #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_MASK)
52830 /*! @} */
52831 
52832 /*! @name STBY_DCDC_IN_CTRL - STBY dcdc_in control */
52833 /*! @{ */
52834 
52835 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
52836 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT (0U)
52837 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52838 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK)
52839 
52840 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_MASK (0x30000000U)
52841 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT (28U)
52842 /*! CNT_MODE - Count mode
52843  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52844  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52845  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52846  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52847  */
52848 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_MASK)
52849 
52850 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_MASK (0x80000000U)
52851 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_SHIFT (31U)
52852 /*! DISABLE - Disable this step */
52853 #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_MASK)
52854 /*! @} */
52855 
52856 /*! @name STBY_PMIC_IN_CTRL - STBY PMIC in control */
52857 /*! @{ */
52858 
52859 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
52860 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT (0U)
52861 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52862 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK)
52863 
52864 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_MASK (0x30000000U)
52865 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT (28U)
52866 /*! CNT_MODE - Count mode
52867  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52868  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52869  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52870  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52871  */
52872 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_MASK)
52873 
52874 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_MASK (0x80000000U)
52875 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_SHIFT (31U)
52876 /*! DISABLE - Disable this step */
52877 #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_MASK)
52878 /*! @} */
52879 
52880 /*! @name STBY_PMIC_OUT_CTRL - STBY PMIC out control */
52881 /*! @{ */
52882 
52883 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
52884 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT (0U)
52885 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52886 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK)
52887 
52888 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
52889 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT (28U)
52890 /*! CNT_MODE - Count mode
52891  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52892  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52893  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52894  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52895  */
52896 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_MASK)
52897 
52898 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_MASK (0x80000000U)
52899 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_SHIFT (31U)
52900 /*! DISABLE - Disable this step */
52901 #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_MASK)
52902 /*! @} */
52903 
52904 /*! @name STBY_DCDC_OUT_CTRL - STBY DCDC out control */
52905 /*! @{ */
52906 
52907 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
52908 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT (0U)
52909 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52910 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK)
52911 
52912 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
52913 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT (28U)
52914 /*! CNT_MODE - Count mode
52915  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52916  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52917  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52918  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52919  */
52920 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_MASK)
52921 
52922 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_MASK (0x80000000U)
52923 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_SHIFT (31U)
52924 /*! DISABLE - Disable this step */
52925 #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_MASK)
52926 /*! @} */
52927 
52928 /*! @name STBY_LDO_OUT_CTRL - STBY LDO out control */
52929 /*! @{ */
52930 
52931 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
52932 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT (0U)
52933 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52934 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK)
52935 
52936 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
52937 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT (28U)
52938 /*! CNT_MODE - Count mode
52939  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52940  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52941  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52942  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52943  */
52944 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_MASK)
52945 
52946 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_MASK (0x80000000U)
52947 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_SHIFT (31U)
52948 /*! DISABLE - Disable this step */
52949 #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_MASK)
52950 /*! @} */
52951 
52952 /*! @name STBY_BANDGAP_OUT_CTRL - STBY bandgap out control */
52953 /*! @{ */
52954 
52955 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
52956 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT (0U)
52957 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52958 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK)
52959 
52960 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
52961 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT (28U)
52962 /*! CNT_MODE - Count mode
52963  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52964  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52965  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52966  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52967  */
52968 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_MASK)
52969 
52970 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_MASK (0x80000000U)
52971 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_SHIFT (31U)
52972 /*! DISABLE - Disable this step */
52973 #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_MASK)
52974 /*! @} */
52975 
52976 /*! @name STBY_PLDO_OUT_CTRL - STBY pldo out control */
52977 /*! @{ */
52978 
52979 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
52980 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT (0U)
52981 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
52982 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK)
52983 
52984 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
52985 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT (28U)
52986 /*! CNT_MODE - Count mode
52987  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
52988  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
52989  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
52990  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
52991  */
52992 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_MASK)
52993 
52994 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_MASK (0x80000000U)
52995 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_SHIFT (31U)
52996 /*! DISABLE - Disable this step */
52997 #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_MASK)
52998 /*! @} */
52999 
53000 /*! @name STBY_BIAS_OUT_CTRL - STBY bias out control */
53001 /*! @{ */
53002 
53003 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
53004 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT (0U)
53005 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
53006 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK)
53007 
53008 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
53009 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT (28U)
53010 /*! CNT_MODE - Count mode
53011  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53012  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53013  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53014  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53015  */
53016 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_MASK)
53017 
53018 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_MASK (0x80000000U)
53019 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_SHIFT (31U)
53020 /*! DISABLE - Disable this step */
53021 #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_MASK)
53022 /*! @} */
53023 
53024 /*! @name STBY_PLL_OUT_CTRL - STBY PLL out control */
53025 /*! @{ */
53026 
53027 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
53028 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT (0U)
53029 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
53030 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK)
53031 
53032 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
53033 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT (28U)
53034 /*! CNT_MODE - Count mode
53035  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53036  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53037  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53038  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53039  */
53040 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_MASK)
53041 
53042 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_MASK (0x80000000U)
53043 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_SHIFT (31U)
53044 /*! DISABLE - Disable this step */
53045 #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_MASK)
53046 /*! @} */
53047 
53048 /*! @name STBY_LPCG_OUT_CTRL - STBY LPCG out control */
53049 /*! @{ */
53050 
53051 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
53052 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT (0U)
53053 /*! STEP_CNT - Step count, useage is depending on CNT_MODE */
53054 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK)
53055 
53056 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
53057 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT (28U)
53058 /*! CNT_MODE - Count mode
53059  *  0b00..Counter disable mode: not use step counter, step completes once receiving step_done
53060  *  0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
53061  *  0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
53062  *  0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
53063  */
53064 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_MASK)
53065 
53066 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_MASK (0x80000000U)
53067 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_SHIFT (31U)
53068 /*! DISABLE - Disable this step */
53069 #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_MASK)
53070 /*! @} */
53071 
53072 
53073 /*!
53074  * @}
53075  */ /* end of group GPC_STBY_CTRL_Register_Masks */
53076 
53077 
53078 /* GPC_STBY_CTRL - Peripheral instance base addresses */
53079 /** Peripheral GPC_STBY_CTRL base address */
53080 #define GPC_STBY_CTRL_BASE                       (0x40C02800u)
53081 /** Peripheral GPC_STBY_CTRL base pointer */
53082 #define GPC_STBY_CTRL                            ((GPC_STBY_CTRL_Type *)GPC_STBY_CTRL_BASE)
53083 /** Array initializer of GPC_STBY_CTRL peripheral base addresses */
53084 #define GPC_STBY_CTRL_BASE_ADDRS                 { GPC_STBY_CTRL_BASE }
53085 /** Array initializer of GPC_STBY_CTRL peripheral base pointers */
53086 #define GPC_STBY_CTRL_BASE_PTRS                  { GPC_STBY_CTRL }
53087 
53088 /*!
53089  * @}
53090  */ /* end of group GPC_STBY_CTRL_Peripheral_Access_Layer */
53091 
53092 
53093 /* ----------------------------------------------------------------------------
53094    -- GPIO Peripheral Access Layer
53095    ---------------------------------------------------------------------------- */
53096 
53097 /*!
53098  * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
53099  * @{
53100  */
53101 
53102 /** GPIO - Register Layout Typedef */
53103 typedef struct {
53104   __IO uint32_t DR;                                /**< GPIO data register, offset: 0x0 */
53105   __IO uint32_t GDIR;                              /**< GPIO direction register, offset: 0x4 */
53106   __I  uint32_t PSR;                               /**< GPIO pad status register, offset: 0x8 */
53107   __IO uint32_t ICR1;                              /**< GPIO interrupt configuration register1, offset: 0xC */
53108   __IO uint32_t ICR2;                              /**< GPIO interrupt configuration register2, offset: 0x10 */
53109   __IO uint32_t IMR;                               /**< GPIO interrupt mask register, offset: 0x14 */
53110   __IO uint32_t ISR;                               /**< GPIO interrupt status register, offset: 0x18 */
53111   __IO uint32_t EDGE_SEL;                          /**< GPIO edge select register, offset: 0x1C */
53112        uint8_t RESERVED_0[100];
53113   __O  uint32_t DR_SET;                            /**< GPIO data register SET, offset: 0x84 */
53114   __O  uint32_t DR_CLEAR;                          /**< GPIO data register CLEAR, offset: 0x88 */
53115   __O  uint32_t DR_TOGGLE;                         /**< GPIO data register TOGGLE, offset: 0x8C */
53116 } GPIO_Type;
53117 
53118 /* ----------------------------------------------------------------------------
53119    -- GPIO Register Masks
53120    ---------------------------------------------------------------------------- */
53121 
53122 /*!
53123  * @addtogroup GPIO_Register_Masks GPIO Register Masks
53124  * @{
53125  */
53126 
53127 /*! @name DR - GPIO data register */
53128 /*! @{ */
53129 
53130 #define GPIO_DR_DR_MASK                          (0xFFFFFFFFU)
53131 #define GPIO_DR_DR_SHIFT                         (0U)
53132 /*! DR - DR data bits */
53133 #define GPIO_DR_DR(x)                            (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
53134 /*! @} */
53135 
53136 /*! @name GDIR - GPIO direction register */
53137 /*! @{ */
53138 
53139 #define GPIO_GDIR_GDIR_MASK                      (0xFFFFFFFFU)
53140 #define GPIO_GDIR_GDIR_SHIFT                     (0U)
53141 /*! GDIR - GPIO direction bits */
53142 #define GPIO_GDIR_GDIR(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
53143 /*! @} */
53144 
53145 /*! @name PSR - GPIO pad status register */
53146 /*! @{ */
53147 
53148 #define GPIO_PSR_PSR_MASK                        (0xFFFFFFFFU)
53149 #define GPIO_PSR_PSR_SHIFT                       (0U)
53150 /*! PSR - GPIO pad status bits */
53151 #define GPIO_PSR_PSR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
53152 /*! @} */
53153 
53154 /*! @name ICR1 - GPIO interrupt configuration register1 */
53155 /*! @{ */
53156 
53157 #define GPIO_ICR1_ICR0_MASK                      (0x3U)
53158 #define GPIO_ICR1_ICR0_SHIFT                     (0U)
53159 /*! ICR0 - Interrupt configuration field for GPIO interrupt 0
53160  *  0b00..Interrupt 0 is low-level sensitive.
53161  *  0b01..Interrupt 0 is high-level sensitive.
53162  *  0b10..Interrupt 0 is rising-edge sensitive.
53163  *  0b11..Interrupt 0 is falling-edge sensitive.
53164  */
53165 #define GPIO_ICR1_ICR0(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
53166 
53167 #define GPIO_ICR1_ICR1_MASK                      (0xCU)
53168 #define GPIO_ICR1_ICR1_SHIFT                     (2U)
53169 /*! ICR1 - Interrupt configuration field for GPIO interrupt 1
53170  *  0b00..Interrupt 1 is low-level sensitive.
53171  *  0b01..Interrupt 1 is high-level sensitive.
53172  *  0b10..Interrupt 1 is rising-edge sensitive.
53173  *  0b11..Interrupt 1 is falling-edge sensitive.
53174  */
53175 #define GPIO_ICR1_ICR1(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
53176 
53177 #define GPIO_ICR1_ICR2_MASK                      (0x30U)
53178 #define GPIO_ICR1_ICR2_SHIFT                     (4U)
53179 /*! ICR2 - Interrupt configuration field for GPIO interrupt 2
53180  *  0b00..Interrupt 2 is low-level sensitive.
53181  *  0b01..Interrupt 2 is high-level sensitive.
53182  *  0b10..Interrupt 2 is rising-edge sensitive.
53183  *  0b11..Interrupt 2 is falling-edge sensitive.
53184  */
53185 #define GPIO_ICR1_ICR2(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
53186 
53187 #define GPIO_ICR1_ICR3_MASK                      (0xC0U)
53188 #define GPIO_ICR1_ICR3_SHIFT                     (6U)
53189 /*! ICR3 - Interrupt configuration field for GPIO interrupt 3
53190  *  0b00..Interrupt 3 is low-level sensitive.
53191  *  0b01..Interrupt 3 is high-level sensitive.
53192  *  0b10..Interrupt 3 is rising-edge sensitive.
53193  *  0b11..Interrupt 3 is falling-edge sensitive.
53194  */
53195 #define GPIO_ICR1_ICR3(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
53196 
53197 #define GPIO_ICR1_ICR4_MASK                      (0x300U)
53198 #define GPIO_ICR1_ICR4_SHIFT                     (8U)
53199 /*! ICR4 - Interrupt configuration field for GPIO interrupt 4
53200  *  0b00..Interrupt 4 is low-level sensitive.
53201  *  0b01..Interrupt 4 is high-level sensitive.
53202  *  0b10..Interrupt 4 is rising-edge sensitive.
53203  *  0b11..Interrupt 4 is falling-edge sensitive.
53204  */
53205 #define GPIO_ICR1_ICR4(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
53206 
53207 #define GPIO_ICR1_ICR5_MASK                      (0xC00U)
53208 #define GPIO_ICR1_ICR5_SHIFT                     (10U)
53209 /*! ICR5 - Interrupt configuration field for GPIO interrupt 5
53210  *  0b00..Interrupt 5 is low-level sensitive.
53211  *  0b01..Interrupt 5 is high-level sensitive.
53212  *  0b10..Interrupt 5 is rising-edge sensitive.
53213  *  0b11..Interrupt 5 is falling-edge sensitive.
53214  */
53215 #define GPIO_ICR1_ICR5(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
53216 
53217 #define GPIO_ICR1_ICR6_MASK                      (0x3000U)
53218 #define GPIO_ICR1_ICR6_SHIFT                     (12U)
53219 /*! ICR6 - Interrupt configuration field for GPIO interrupt 6
53220  *  0b00..Interrupt 6 is low-level sensitive.
53221  *  0b01..Interrupt 6 is high-level sensitive.
53222  *  0b10..Interrupt 6 is rising-edge sensitive.
53223  *  0b11..Interrupt 6 is falling-edge sensitive.
53224  */
53225 #define GPIO_ICR1_ICR6(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
53226 
53227 #define GPIO_ICR1_ICR7_MASK                      (0xC000U)
53228 #define GPIO_ICR1_ICR7_SHIFT                     (14U)
53229 /*! ICR7 - Interrupt configuration field for GPIO interrupt 7
53230  *  0b00..Interrupt 7 is low-level sensitive.
53231  *  0b01..Interrupt 7 is high-level sensitive.
53232  *  0b10..Interrupt 7 is rising-edge sensitive.
53233  *  0b11..Interrupt 7 is falling-edge sensitive.
53234  */
53235 #define GPIO_ICR1_ICR7(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
53236 
53237 #define GPIO_ICR1_ICR8_MASK                      (0x30000U)
53238 #define GPIO_ICR1_ICR8_SHIFT                     (16U)
53239 /*! ICR8 - Interrupt configuration field for GPIO interrupt 8
53240  *  0b00..Interrupt 8 is low-level sensitive.
53241  *  0b01..Interrupt 8 is high-level sensitive.
53242  *  0b10..Interrupt 8 is rising-edge sensitive.
53243  *  0b11..Interrupt 8 is falling-edge sensitive.
53244  */
53245 #define GPIO_ICR1_ICR8(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
53246 
53247 #define GPIO_ICR1_ICR9_MASK                      (0xC0000U)
53248 #define GPIO_ICR1_ICR9_SHIFT                     (18U)
53249 /*! ICR9 - Interrupt configuration field for GPIO interrupt 9
53250  *  0b00..Interrupt 9 is low-level sensitive.
53251  *  0b01..Interrupt 9 is high-level sensitive.
53252  *  0b10..Interrupt 9 is rising-edge sensitive.
53253  *  0b11..Interrupt 9 is falling-edge sensitive.
53254  */
53255 #define GPIO_ICR1_ICR9(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
53256 
53257 #define GPIO_ICR1_ICR10_MASK                     (0x300000U)
53258 #define GPIO_ICR1_ICR10_SHIFT                    (20U)
53259 /*! ICR10 - Interrupt configuration field for GPIO interrupt 10
53260  *  0b00..Interrupt 10 is low-level sensitive.
53261  *  0b01..Interrupt 10 is high-level sensitive.
53262  *  0b10..Interrupt 10 is rising-edge sensitive.
53263  *  0b11..Interrupt 10 is falling-edge sensitive.
53264  */
53265 #define GPIO_ICR1_ICR10(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
53266 
53267 #define GPIO_ICR1_ICR11_MASK                     (0xC00000U)
53268 #define GPIO_ICR1_ICR11_SHIFT                    (22U)
53269 /*! ICR11 - Interrupt configuration field for GPIO interrupt 11
53270  *  0b00..Interrupt 11 is low-level sensitive.
53271  *  0b01..Interrupt 11 is high-level sensitive.
53272  *  0b10..Interrupt 11 is rising-edge sensitive.
53273  *  0b11..Interrupt 11 is falling-edge sensitive.
53274  */
53275 #define GPIO_ICR1_ICR11(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
53276 
53277 #define GPIO_ICR1_ICR12_MASK                     (0x3000000U)
53278 #define GPIO_ICR1_ICR12_SHIFT                    (24U)
53279 /*! ICR12 - Interrupt configuration field for GPIO interrupt 12
53280  *  0b00..Interrupt 12 is low-level sensitive.
53281  *  0b01..Interrupt 12 is high-level sensitive.
53282  *  0b10..Interrupt 12 is rising-edge sensitive.
53283  *  0b11..Interrupt 12 is falling-edge sensitive.
53284  */
53285 #define GPIO_ICR1_ICR12(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
53286 
53287 #define GPIO_ICR1_ICR13_MASK                     (0xC000000U)
53288 #define GPIO_ICR1_ICR13_SHIFT                    (26U)
53289 /*! ICR13 - Interrupt configuration field for GPIO interrupt 13
53290  *  0b00..Interrupt 13 is low-level sensitive.
53291  *  0b01..Interrupt 13 is high-level sensitive.
53292  *  0b10..Interrupt 13 is rising-edge sensitive.
53293  *  0b11..Interrupt 13 is falling-edge sensitive.
53294  */
53295 #define GPIO_ICR1_ICR13(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
53296 
53297 #define GPIO_ICR1_ICR14_MASK                     (0x30000000U)
53298 #define GPIO_ICR1_ICR14_SHIFT                    (28U)
53299 /*! ICR14 - Interrupt configuration field for GPIO interrupt 14
53300  *  0b00..Interrupt 14 is low-level sensitive.
53301  *  0b01..Interrupt 14 is high-level sensitive.
53302  *  0b10..Interrupt 14 is rising-edge sensitive.
53303  *  0b11..Interrupt 14 is falling-edge sensitive.
53304  */
53305 #define GPIO_ICR1_ICR14(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
53306 
53307 #define GPIO_ICR1_ICR15_MASK                     (0xC0000000U)
53308 #define GPIO_ICR1_ICR15_SHIFT                    (30U)
53309 /*! ICR15 - Interrupt configuration field for GPIO interrupt 15
53310  *  0b00..Interrupt 15 is low-level sensitive.
53311  *  0b01..Interrupt 15 is high-level sensitive.
53312  *  0b10..Interrupt 15 is rising-edge sensitive.
53313  *  0b11..Interrupt 15 is falling-edge sensitive.
53314  */
53315 #define GPIO_ICR1_ICR15(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
53316 /*! @} */
53317 
53318 /*! @name ICR2 - GPIO interrupt configuration register2 */
53319 /*! @{ */
53320 
53321 #define GPIO_ICR2_ICR16_MASK                     (0x3U)
53322 #define GPIO_ICR2_ICR16_SHIFT                    (0U)
53323 /*! ICR16 - Interrupt configuration field for GPIO interrupt 16
53324  *  0b00..Interrupt 16 is low-level sensitive.
53325  *  0b01..Interrupt 16 is high-level sensitive.
53326  *  0b10..Interrupt 16 is rising-edge sensitive.
53327  *  0b11..Interrupt 16 is falling-edge sensitive.
53328  */
53329 #define GPIO_ICR2_ICR16(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
53330 
53331 #define GPIO_ICR2_ICR17_MASK                     (0xCU)
53332 #define GPIO_ICR2_ICR17_SHIFT                    (2U)
53333 /*! ICR17 - Interrupt configuration field for GPIO interrupt 17
53334  *  0b00..Interrupt 17 is low-level sensitive.
53335  *  0b01..Interrupt 17 is high-level sensitive.
53336  *  0b10..Interrupt 17 is rising-edge sensitive.
53337  *  0b11..Interrupt 17 is falling-edge sensitive.
53338  */
53339 #define GPIO_ICR2_ICR17(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
53340 
53341 #define GPIO_ICR2_ICR18_MASK                     (0x30U)
53342 #define GPIO_ICR2_ICR18_SHIFT                    (4U)
53343 /*! ICR18 - Interrupt configuration field for GPIO interrupt 18
53344  *  0b00..Interrupt 18 is low-level sensitive.
53345  *  0b01..Interrupt 18 is high-level sensitive.
53346  *  0b10..Interrupt 18 is rising-edge sensitive.
53347  *  0b11..Interrupt 18 is falling-edge sensitive.
53348  */
53349 #define GPIO_ICR2_ICR18(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
53350 
53351 #define GPIO_ICR2_ICR19_MASK                     (0xC0U)
53352 #define GPIO_ICR2_ICR19_SHIFT                    (6U)
53353 /*! ICR19 - Interrupt configuration field for GPIO interrupt 19
53354  *  0b00..Interrupt 19 is low-level sensitive.
53355  *  0b01..Interrupt 19 is high-level sensitive.
53356  *  0b10..Interrupt 19 is rising-edge sensitive.
53357  *  0b11..Interrupt 19 is falling-edge sensitive.
53358  */
53359 #define GPIO_ICR2_ICR19(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
53360 
53361 #define GPIO_ICR2_ICR20_MASK                     (0x300U)
53362 #define GPIO_ICR2_ICR20_SHIFT                    (8U)
53363 /*! ICR20 - Interrupt configuration field for GPIO interrupt 20
53364  *  0b00..Interrupt 20 is low-level sensitive.
53365  *  0b01..Interrupt 20 is high-level sensitive.
53366  *  0b10..Interrupt 20 is rising-edge sensitive.
53367  *  0b11..Interrupt 20 is falling-edge sensitive.
53368  */
53369 #define GPIO_ICR2_ICR20(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
53370 
53371 #define GPIO_ICR2_ICR21_MASK                     (0xC00U)
53372 #define GPIO_ICR2_ICR21_SHIFT                    (10U)
53373 /*! ICR21 - Interrupt configuration field for GPIO interrupt 21
53374  *  0b00..Interrupt 21 is low-level sensitive.
53375  *  0b01..Interrupt 21 is high-level sensitive.
53376  *  0b10..Interrupt 21 is rising-edge sensitive.
53377  *  0b11..Interrupt 21 is falling-edge sensitive.
53378  */
53379 #define GPIO_ICR2_ICR21(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
53380 
53381 #define GPIO_ICR2_ICR22_MASK                     (0x3000U)
53382 #define GPIO_ICR2_ICR22_SHIFT                    (12U)
53383 /*! ICR22 - Interrupt configuration field for GPIO interrupt 22
53384  *  0b00..Interrupt 22 is low-level sensitive.
53385  *  0b01..Interrupt 22 is high-level sensitive.
53386  *  0b10..Interrupt 22 is rising-edge sensitive.
53387  *  0b11..Interrupt 22 is falling-edge sensitive.
53388  */
53389 #define GPIO_ICR2_ICR22(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
53390 
53391 #define GPIO_ICR2_ICR23_MASK                     (0xC000U)
53392 #define GPIO_ICR2_ICR23_SHIFT                    (14U)
53393 /*! ICR23 - Interrupt configuration field for GPIO interrupt 23
53394  *  0b00..Interrupt 23 is low-level sensitive.
53395  *  0b01..Interrupt 23 is high-level sensitive.
53396  *  0b10..Interrupt 23 is rising-edge sensitive.
53397  *  0b11..Interrupt 23 is falling-edge sensitive.
53398  */
53399 #define GPIO_ICR2_ICR23(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
53400 
53401 #define GPIO_ICR2_ICR24_MASK                     (0x30000U)
53402 #define GPIO_ICR2_ICR24_SHIFT                    (16U)
53403 /*! ICR24 - Interrupt configuration field for GPIO interrupt 24
53404  *  0b00..Interrupt 24 is low-level sensitive.
53405  *  0b01..Interrupt 24 is high-level sensitive.
53406  *  0b10..Interrupt 24 is rising-edge sensitive.
53407  *  0b11..Interrupt 24 is falling-edge sensitive.
53408  */
53409 #define GPIO_ICR2_ICR24(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
53410 
53411 #define GPIO_ICR2_ICR25_MASK                     (0xC0000U)
53412 #define GPIO_ICR2_ICR25_SHIFT                    (18U)
53413 /*! ICR25 - Interrupt configuration field for GPIO interrupt 25
53414  *  0b00..Interrupt 25 is low-level sensitive.
53415  *  0b01..Interrupt 25 is high-level sensitive.
53416  *  0b10..Interrupt 25 is rising-edge sensitive.
53417  *  0b11..Interrupt 25 is falling-edge sensitive.
53418  */
53419 #define GPIO_ICR2_ICR25(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
53420 
53421 #define GPIO_ICR2_ICR26_MASK                     (0x300000U)
53422 #define GPIO_ICR2_ICR26_SHIFT                    (20U)
53423 /*! ICR26 - Interrupt configuration field for GPIO interrupt 26
53424  *  0b00..Interrupt 26 is low-level sensitive.
53425  *  0b01..Interrupt 26 is high-level sensitive.
53426  *  0b10..Interrupt 26 is rising-edge sensitive.
53427  *  0b11..Interrupt 26 is falling-edge sensitive.
53428  */
53429 #define GPIO_ICR2_ICR26(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
53430 
53431 #define GPIO_ICR2_ICR27_MASK                     (0xC00000U)
53432 #define GPIO_ICR2_ICR27_SHIFT                    (22U)
53433 /*! ICR27 - Interrupt configuration field for GPIO interrupt 27
53434  *  0b00..Interrupt 27 is low-level sensitive.
53435  *  0b01..Interrupt 27 is high-level sensitive.
53436  *  0b10..Interrupt 27 is rising-edge sensitive.
53437  *  0b11..Interrupt 27 is falling-edge sensitive.
53438  */
53439 #define GPIO_ICR2_ICR27(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
53440 
53441 #define GPIO_ICR2_ICR28_MASK                     (0x3000000U)
53442 #define GPIO_ICR2_ICR28_SHIFT                    (24U)
53443 /*! ICR28 - Interrupt configuration field for GPIO interrupt 28
53444  *  0b00..Interrupt 28 is low-level sensitive.
53445  *  0b01..Interrupt 28 is high-level sensitive.
53446  *  0b10..Interrupt 28 is rising-edge sensitive.
53447  *  0b11..Interrupt 28 is falling-edge sensitive.
53448  */
53449 #define GPIO_ICR2_ICR28(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
53450 
53451 #define GPIO_ICR2_ICR29_MASK                     (0xC000000U)
53452 #define GPIO_ICR2_ICR29_SHIFT                    (26U)
53453 /*! ICR29 - Interrupt configuration field for GPIO interrupt 29
53454  *  0b00..Interrupt 29 is low-level sensitive.
53455  *  0b01..Interrupt 29 is high-level sensitive.
53456  *  0b10..Interrupt 29 is rising-edge sensitive.
53457  *  0b11..Interrupt 29 is falling-edge sensitive.
53458  */
53459 #define GPIO_ICR2_ICR29(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
53460 
53461 #define GPIO_ICR2_ICR30_MASK                     (0x30000000U)
53462 #define GPIO_ICR2_ICR30_SHIFT                    (28U)
53463 /*! ICR30 - Interrupt configuration field for GPIO interrupt 30
53464  *  0b00..Interrupt 30 is low-level sensitive.
53465  *  0b01..Interrupt 30 is high-level sensitive.
53466  *  0b10..Interrupt 30 is rising-edge sensitive.
53467  *  0b11..Interrupt 30 is falling-edge sensitive.
53468  */
53469 #define GPIO_ICR2_ICR30(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
53470 
53471 #define GPIO_ICR2_ICR31_MASK                     (0xC0000000U)
53472 #define GPIO_ICR2_ICR31_SHIFT                    (30U)
53473 /*! ICR31 - Interrupt configuration field for GPIO interrupt 31
53474  *  0b00..Interrupt 31 is low-level sensitive.
53475  *  0b01..Interrupt 31 is high-level sensitive.
53476  *  0b10..Interrupt 31 is rising-edge sensitive.
53477  *  0b11..Interrupt 31 is falling-edge sensitive.
53478  */
53479 #define GPIO_ICR2_ICR31(x)                       (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
53480 /*! @} */
53481 
53482 /*! @name IMR - GPIO interrupt mask register */
53483 /*! @{ */
53484 
53485 #define GPIO_IMR_IMR_MASK                        (0xFFFFFFFFU)
53486 #define GPIO_IMR_IMR_SHIFT                       (0U)
53487 /*! IMR - Interrupt Mask bits */
53488 #define GPIO_IMR_IMR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
53489 /*! @} */
53490 
53491 /*! @name ISR - GPIO interrupt status register */
53492 /*! @{ */
53493 
53494 #define GPIO_ISR_ISR_MASK                        (0xFFFFFFFFU)
53495 #define GPIO_ISR_ISR_SHIFT                       (0U)
53496 /*! ISR - Interrupt status bits */
53497 #define GPIO_ISR_ISR(x)                          (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
53498 /*! @} */
53499 
53500 /*! @name EDGE_SEL - GPIO edge select register */
53501 /*! @{ */
53502 
53503 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK         (0xFFFFFFFFU)
53504 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT        (0U)
53505 /*! GPIO_EDGE_SEL - Edge select */
53506 #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x)           (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
53507 /*! @} */
53508 
53509 /*! @name DR_SET - GPIO data register SET */
53510 /*! @{ */
53511 
53512 #define GPIO_DR_SET_DR_SET_MASK                  (0xFFFFFFFFU)
53513 #define GPIO_DR_SET_DR_SET_SHIFT                 (0U)
53514 /*! DR_SET - Set */
53515 #define GPIO_DR_SET_DR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
53516 /*! @} */
53517 
53518 /*! @name DR_CLEAR - GPIO data register CLEAR */
53519 /*! @{ */
53520 
53521 #define GPIO_DR_CLEAR_DR_CLEAR_MASK              (0xFFFFFFFFU)
53522 #define GPIO_DR_CLEAR_DR_CLEAR_SHIFT             (0U)
53523 /*! DR_CLEAR - Clear */
53524 #define GPIO_DR_CLEAR_DR_CLEAR(x)                (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
53525 /*! @} */
53526 
53527 /*! @name DR_TOGGLE - GPIO data register TOGGLE */
53528 /*! @{ */
53529 
53530 #define GPIO_DR_TOGGLE_DR_TOGGLE_MASK            (0xFFFFFFFFU)
53531 #define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT           (0U)
53532 /*! DR_TOGGLE - Toggle */
53533 #define GPIO_DR_TOGGLE_DR_TOGGLE(x)              (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)
53534 /*! @} */
53535 
53536 
53537 /*!
53538  * @}
53539  */ /* end of group GPIO_Register_Masks */
53540 
53541 
53542 /* GPIO - Peripheral instance base addresses */
53543 /** Peripheral GPIO1 base address */
53544 #define GPIO1_BASE                               (0x4012C000u)
53545 /** Peripheral GPIO1 base pointer */
53546 #define GPIO1                                    ((GPIO_Type *)GPIO1_BASE)
53547 /** Peripheral GPIO2 base address */
53548 #define GPIO2_BASE                               (0x40130000u)
53549 /** Peripheral GPIO2 base pointer */
53550 #define GPIO2                                    ((GPIO_Type *)GPIO2_BASE)
53551 /** Peripheral GPIO3 base address */
53552 #define GPIO3_BASE                               (0x40134000u)
53553 /** Peripheral GPIO3 base pointer */
53554 #define GPIO3                                    ((GPIO_Type *)GPIO3_BASE)
53555 /** Peripheral GPIO4 base address */
53556 #define GPIO4_BASE                               (0x40138000u)
53557 /** Peripheral GPIO4 base pointer */
53558 #define GPIO4                                    ((GPIO_Type *)GPIO4_BASE)
53559 /** Peripheral GPIO5 base address */
53560 #define GPIO5_BASE                               (0x4013C000u)
53561 /** Peripheral GPIO5 base pointer */
53562 #define GPIO5                                    ((GPIO_Type *)GPIO5_BASE)
53563 /** Peripheral GPIO6 base address */
53564 #define GPIO6_BASE                               (0x40140000u)
53565 /** Peripheral GPIO6 base pointer */
53566 #define GPIO6                                    ((GPIO_Type *)GPIO6_BASE)
53567 /** Peripheral GPIO7 base address */
53568 #define GPIO7_BASE                               (0x40C5C000u)
53569 /** Peripheral GPIO7 base pointer */
53570 #define GPIO7                                    ((GPIO_Type *)GPIO7_BASE)
53571 /** Peripheral GPIO8 base address */
53572 #define GPIO8_BASE                               (0x40C60000u)
53573 /** Peripheral GPIO8 base pointer */
53574 #define GPIO8                                    ((GPIO_Type *)GPIO8_BASE)
53575 /** Peripheral GPIO9 base address */
53576 #define GPIO9_BASE                               (0x40C64000u)
53577 /** Peripheral GPIO9 base pointer */
53578 #define GPIO9                                    ((GPIO_Type *)GPIO9_BASE)
53579 /** Peripheral GPIO10 base address */
53580 #define GPIO10_BASE                              (0x40C68000u)
53581 /** Peripheral GPIO10 base pointer */
53582 #define GPIO10                                   ((GPIO_Type *)GPIO10_BASE)
53583 /** Peripheral GPIO11 base address */
53584 #define GPIO11_BASE                              (0x40C6C000u)
53585 /** Peripheral GPIO11 base pointer */
53586 #define GPIO11                                   ((GPIO_Type *)GPIO11_BASE)
53587 /** Peripheral GPIO12 base address */
53588 #define GPIO12_BASE                              (0x40C70000u)
53589 /** Peripheral GPIO12 base pointer */
53590 #define GPIO12                                   ((GPIO_Type *)GPIO12_BASE)
53591 /** Peripheral GPIO13 base address */
53592 #define GPIO13_BASE                              (0x40CA0000u)
53593 /** Peripheral GPIO13 base pointer */
53594 #define GPIO13                                   ((GPIO_Type *)GPIO13_BASE)
53595 /** Peripheral CM7_GPIO2 base address */
53596 #define CM7_GPIO2_BASE                           (0x42008000u)
53597 /** Peripheral CM7_GPIO2 base pointer */
53598 #define CM7_GPIO2                                ((GPIO_Type *)CM7_GPIO2_BASE)
53599 /** Peripheral CM7_GPIO3 base address */
53600 #define CM7_GPIO3_BASE                           (0x4200C000u)
53601 /** Peripheral CM7_GPIO3 base pointer */
53602 #define CM7_GPIO3                                ((GPIO_Type *)CM7_GPIO3_BASE)
53603 /** Array initializer of GPIO peripheral base addresses */
53604 #define GPIO_BASE_ADDRS                          { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, GPIO8_BASE, GPIO9_BASE, GPIO10_BASE, GPIO11_BASE, GPIO12_BASE, GPIO13_BASE, CM7_GPIO2_BASE, CM7_GPIO3_BASE }
53605 /** Array initializer of GPIO peripheral base pointers */
53606 #define GPIO_BASE_PTRS                           { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, CM7_GPIO2, CM7_GPIO3 }
53607 /** Interrupt vectors for the GPIO peripheral type */
53608 #define GPIO_COMBINED_LOW_IRQS                   { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn, GPIO6_Combined_0_15_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, GPIO13_Combined_0_31_IRQn, CM7_GPIO2_3_IRQn, CM7_GPIO2_3_IRQn }
53609 #define GPIO_COMBINED_HIGH_IRQS                  { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn, GPIO6_Combined_16_31_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, GPIO13_Combined_0_31_IRQn, CM7_GPIO2_3_IRQn, CM7_GPIO2_3_IRQn }
53610 
53611 /*!
53612  * @}
53613  */ /* end of group GPIO_Peripheral_Access_Layer */
53614 
53615 
53616 /* ----------------------------------------------------------------------------
53617    -- GPT Peripheral Access Layer
53618    ---------------------------------------------------------------------------- */
53619 
53620 /*!
53621  * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
53622  * @{
53623  */
53624 
53625 /** GPT - Register Layout Typedef */
53626 typedef struct {
53627   __IO uint32_t CR;                                /**< GPT Control Register, offset: 0x0 */
53628   __IO uint32_t PR;                                /**< GPT Prescaler Register, offset: 0x4 */
53629   __IO uint32_t SR;                                /**< GPT Status Register, offset: 0x8 */
53630   __IO uint32_t IR;                                /**< GPT Interrupt Register, offset: 0xC */
53631   __IO uint32_t OCR[3];                            /**< GPT Output Compare Register, array offset: 0x10, array step: 0x4 */
53632   __I  uint32_t ICR[2];                            /**< GPT Input Capture Register, array offset: 0x1C, array step: 0x4 */
53633   __I  uint32_t CNT;                               /**< GPT Counter Register, offset: 0x24 */
53634 } GPT_Type;
53635 
53636 /* ----------------------------------------------------------------------------
53637    -- GPT Register Masks
53638    ---------------------------------------------------------------------------- */
53639 
53640 /*!
53641  * @addtogroup GPT_Register_Masks GPT Register Masks
53642  * @{
53643  */
53644 
53645 /*! @name CR - GPT Control Register */
53646 /*! @{ */
53647 
53648 #define GPT_CR_EN_MASK                           (0x1U)
53649 #define GPT_CR_EN_SHIFT                          (0U)
53650 /*! EN - GPT Enable
53651  *  0b0..Disable
53652  *  0b1..Enable
53653  */
53654 #define GPT_CR_EN(x)                             (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
53655 
53656 #define GPT_CR_ENMOD_MASK                        (0x2U)
53657 #define GPT_CR_ENMOD_SHIFT                       (1U)
53658 /*! ENMOD - GPT Enable Mode
53659  *  0b0..Restart counting from their frozen values after GPT is enabled (EN=1).
53660  *  0b1..Reset counting from 0 after GPT is enabled (EN=1).
53661  */
53662 #define GPT_CR_ENMOD(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
53663 
53664 #define GPT_CR_DBGEN_MASK                        (0x4U)
53665 #define GPT_CR_DBGEN_SHIFT                       (2U)
53666 /*! DBGEN - GPT Debug Mode Enable
53667  *  0b0..Disable in Debug mode
53668  *  0b1..Enable in Debug mode
53669  */
53670 #define GPT_CR_DBGEN(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
53671 
53672 #define GPT_CR_WAITEN_MASK                       (0x8U)
53673 #define GPT_CR_WAITEN_SHIFT                      (3U)
53674 /*! WAITEN - GPT Wait Mode Enable
53675  *  0b0..Disable in Wait mode
53676  *  0b1..Enable in Wait mode
53677  */
53678 #define GPT_CR_WAITEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
53679 
53680 #define GPT_CR_DOZEEN_MASK                       (0x10U)
53681 #define GPT_CR_DOZEEN_SHIFT                      (4U)
53682 /*! DOZEEN - GPT Doze Mode Enable
53683  *  0b0..Disable in Doze mode
53684  *  0b1..Enable in Doze mode
53685  */
53686 #define GPT_CR_DOZEEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
53687 
53688 #define GPT_CR_STOPEN_MASK                       (0x20U)
53689 #define GPT_CR_STOPEN_SHIFT                      (5U)
53690 /*! STOPEN - GPT Stop Mode Enable
53691  *  0b0..Disable in Stop mode
53692  *  0b1..Enable in Stop mode
53693  */
53694 #define GPT_CR_STOPEN(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
53695 
53696 #define GPT_CR_CLKSRC_MASK                       (0x1C0U)
53697 #define GPT_CR_CLKSRC_SHIFT                      (6U)
53698 /*! CLKSRC - Clock Source Select
53699  *  0b000..No clock
53700  *  0b001..Peripheral Clock (ipg_clk)
53701  *  0b010..High Frequency Reference Clock (ipg_clk_highfreq)
53702  *  0b011..External Clock
53703  *  0b100..Low Frequency Reference Clock (ipg_clk_32k)
53704  *  0b101..Oscillator as Reference Clock (ipg_clk_16M)
53705  */
53706 #define GPT_CR_CLKSRC(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
53707 
53708 #define GPT_CR_FRR_MASK                          (0x200U)
53709 #define GPT_CR_FRR_SHIFT                         (9U)
53710 /*! FRR - Free-Run or Restart Mode
53711  *  0b0..Restart mode. After a compare event, the counter resets to 0x0000_0000 and resumes counting.
53712  *  0b1..Free-Run mode. After a compare event, the counter continues counting until 0xFFFF_FFFF and then rolls over to 0.
53713  */
53714 #define GPT_CR_FRR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
53715 
53716 #define GPT_CR_EN_24M_MASK                       (0x400U)
53717 #define GPT_CR_EN_24M_SHIFT                      (10U)
53718 /*! EN_24M - Enable Oscillator Clock Input
53719  *  0b0..Disable
53720  *  0b1..Enable
53721  */
53722 #define GPT_CR_EN_24M(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
53723 
53724 #define GPT_CR_SWR_MASK                          (0x8000U)
53725 #define GPT_CR_SWR_SHIFT                         (15U)
53726 /*! SWR - Software Reset
53727  *  0b0..GPT is not in software reset state
53728  *  0b1..GPT is in software reset state
53729  */
53730 #define GPT_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
53731 
53732 #define GPT_CR_IM1_MASK                          (0x30000U)
53733 #define GPT_CR_IM1_SHIFT                         (16U)
53734 /*! IM1 - Input Capture Operating Mode for Channel 1
53735  *  0b00..Capture disabled
53736  *  0b01..Capture on rising edge only
53737  *  0b10..Capture on falling edge only
53738  *  0b11..Capture on both edges
53739  */
53740 #define GPT_CR_IM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
53741 
53742 #define GPT_CR_IM2_MASK                          (0xC0000U)
53743 #define GPT_CR_IM2_SHIFT                         (18U)
53744 /*! IM2 - Input Capture Operating Mode for Channel 2
53745  *  0b00..Capture disabled
53746  *  0b01..Capture on rising edge only
53747  *  0b10..Capture on falling edge only
53748  *  0b11..Capture on both edges
53749  */
53750 #define GPT_CR_IM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
53751 
53752 #define GPT_CR_OM1_MASK                          (0x700000U)
53753 #define GPT_CR_OM1_SHIFT                         (20U)
53754 /*! OM1 - Output Compare Operating Mode for Channel 1
53755  *  0b000..Output disabled. No response on pin.
53756  *  0b001..Toggle output pin
53757  *  0b010..Clear output pin
53758  *  0b011..Set output pin
53759  *  0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed
53760  *         as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already).
53761  *         "Input clock" here refers to the clock selected by the CLKSRC field of this register.
53762  */
53763 #define GPT_CR_OM1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
53764 
53765 #define GPT_CR_OM2_MASK                          (0x3800000U)
53766 #define GPT_CR_OM2_SHIFT                         (23U)
53767 /*! OM2 - Output Compare Operating Mode for Channel 2
53768  *  0b000..Output disabled. No response on pin.
53769  *  0b001..Toggle output pin
53770  *  0b010..Clear output pin
53771  *  0b011..Set output pin
53772  *  0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed
53773  *         as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already).
53774  *         "Input clock" here refers to the clock selected by the CLKSRC field of this register.
53775  */
53776 #define GPT_CR_OM2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
53777 
53778 #define GPT_CR_OM3_MASK                          (0x1C000000U)
53779 #define GPT_CR_OM3_SHIFT                         (26U)
53780 /*! OM3 - Output Compare Operating Mode for Channel 3
53781  *  0b000..Output disabled. No response on pin.
53782  *  0b001..Toggle output pin
53783  *  0b010..Clear output pin
53784  *  0b011..Set output pin
53785  *  0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed
53786  *         as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already).
53787  *         "Input clock" here refers to the clock selected by the CLKSRC field of this register.
53788  */
53789 #define GPT_CR_OM3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
53790 
53791 #define GPT_CR_FO1_MASK                          (0x20000000U)
53792 #define GPT_CR_FO1_SHIFT                         (29U)
53793 /*! FO1 - Force Output Compare for Channel 1
53794  *  0b0..No effect
53795  *  0b1..Trigger the programmed response on the pin
53796  */
53797 #define GPT_CR_FO1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
53798 
53799 #define GPT_CR_FO2_MASK                          (0x40000000U)
53800 #define GPT_CR_FO2_SHIFT                         (30U)
53801 /*! FO2 - Force Output Compare for Channel 2
53802  *  0b0..No effect
53803  *  0b1..Trigger the programmed response on the pin
53804  */
53805 #define GPT_CR_FO2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
53806 
53807 #define GPT_CR_FO3_MASK                          (0x80000000U)
53808 #define GPT_CR_FO3_SHIFT                         (31U)
53809 /*! FO3 - Force Output Compare for Channel 3
53810  *  0b0..No effect
53811  *  0b1..Trigger the programmed response on the pin
53812  */
53813 #define GPT_CR_FO3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
53814 /*! @} */
53815 
53816 /*! @name PR - GPT Prescaler Register */
53817 /*! @{ */
53818 
53819 #define GPT_PR_PRESCALER_MASK                    (0xFFFU)
53820 #define GPT_PR_PRESCALER_SHIFT                   (0U)
53821 /*! PRESCALER - Prescaler divide value
53822  *  0b000000000000..Divide by 1
53823  *  0b000000000001..Divide by 2
53824  *  0b111111111111..Divide by 4096
53825  */
53826 #define GPT_PR_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
53827 
53828 #define GPT_PR_PRESCALER24M_MASK                 (0xF000U)
53829 #define GPT_PR_PRESCALER24M_SHIFT                (12U)
53830 /*! PRESCALER24M - Prescaler divide value for the oscillator clock
53831  *  0b0000..Divide by 1
53832  *  0b0001..Divide by 2
53833  *  0b1111..Divide by 16
53834  */
53835 #define GPT_PR_PRESCALER24M(x)                   (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
53836 /*! @} */
53837 
53838 /*! @name SR - GPT Status Register */
53839 /*! @{ */
53840 
53841 #define GPT_SR_OF1_MASK                          (0x1U)
53842 #define GPT_SR_OF1_SHIFT                         (0U)
53843 /*! OF1 - Output Compare Flag for Channel 1
53844  *  0b0..Compare event has not occurred.
53845  *  0b1..Compare event has occurred.
53846  */
53847 #define GPT_SR_OF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
53848 
53849 #define GPT_SR_OF2_MASK                          (0x2U)
53850 #define GPT_SR_OF2_SHIFT                         (1U)
53851 /*! OF2 - Output Compare Flag for Channel 2
53852  *  0b0..Compare event has not occurred.
53853  *  0b1..Compare event has occurred.
53854  */
53855 #define GPT_SR_OF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
53856 
53857 #define GPT_SR_OF3_MASK                          (0x4U)
53858 #define GPT_SR_OF3_SHIFT                         (2U)
53859 /*! OF3 - Output Compare Flag for Channel 3
53860  *  0b0..Compare event has not occurred.
53861  *  0b1..Compare event has occurred.
53862  */
53863 #define GPT_SR_OF3(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
53864 
53865 #define GPT_SR_IF1_MASK                          (0x8U)
53866 #define GPT_SR_IF1_SHIFT                         (3U)
53867 /*! IF1 - Input Capture Flag for Channel 1
53868  *  0b0..Capture event has not occurred.
53869  *  0b1..Capture event has occurred.
53870  */
53871 #define GPT_SR_IF1(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
53872 
53873 #define GPT_SR_IF2_MASK                          (0x10U)
53874 #define GPT_SR_IF2_SHIFT                         (4U)
53875 /*! IF2 - Input Capture Flag for Channel 2
53876  *  0b0..Capture event has not occurred.
53877  *  0b1..Capture event has occurred.
53878  */
53879 #define GPT_SR_IF2(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
53880 
53881 #define GPT_SR_ROV_MASK                          (0x20U)
53882 #define GPT_SR_ROV_SHIFT                         (5U)
53883 /*! ROV - Rollover Flag
53884  *  0b0..Rollover has not occurred.
53885  *  0b1..Rollover has occurred.
53886  */
53887 #define GPT_SR_ROV(x)                            (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
53888 /*! @} */
53889 
53890 /*! @name IR - GPT Interrupt Register */
53891 /*! @{ */
53892 
53893 #define GPT_IR_OF1IE_MASK                        (0x1U)
53894 #define GPT_IR_OF1IE_SHIFT                       (0U)
53895 /*! OF1IE - Output Compare Flag for Channel 1 Interrupt Enable
53896  *  0b0..Disable
53897  *  0b1..Enable
53898  */
53899 #define GPT_IR_OF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
53900 
53901 #define GPT_IR_OF2IE_MASK                        (0x2U)
53902 #define GPT_IR_OF2IE_SHIFT                       (1U)
53903 /*! OF2IE - Output Compare Flag for Channel 2 Interrupt Enable
53904  *  0b0..Disable
53905  *  0b1..Enable
53906  */
53907 #define GPT_IR_OF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
53908 
53909 #define GPT_IR_OF3IE_MASK                        (0x4U)
53910 #define GPT_IR_OF3IE_SHIFT                       (2U)
53911 /*! OF3IE - Output Compare Flag for Channel 3 Interrupt Enable
53912  *  0b0..Disable
53913  *  0b1..Enable
53914  */
53915 #define GPT_IR_OF3IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
53916 
53917 #define GPT_IR_IF1IE_MASK                        (0x8U)
53918 #define GPT_IR_IF1IE_SHIFT                       (3U)
53919 /*! IF1IE - Input Capture Flag for Channel 1 Interrupt Enable
53920  *  0b0..Disable
53921  *  0b1..Enable
53922  */
53923 #define GPT_IR_IF1IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
53924 
53925 #define GPT_IR_IF2IE_MASK                        (0x10U)
53926 #define GPT_IR_IF2IE_SHIFT                       (4U)
53927 /*! IF2IE - Input Capture Flag for Channel 2 Interrupt Enable
53928  *  0b0..Disable
53929  *  0b1..Enable
53930  */
53931 #define GPT_IR_IF2IE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
53932 
53933 #define GPT_IR_ROVIE_MASK                        (0x20U)
53934 #define GPT_IR_ROVIE_SHIFT                       (5U)
53935 /*! ROVIE - Rollover Interrupt Enable
53936  *  0b0..Disable
53937  *  0b1..Enable
53938  */
53939 #define GPT_IR_ROVIE(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
53940 /*! @} */
53941 
53942 /*! @name OCR - GPT Output Compare Register */
53943 /*! @{ */
53944 
53945 #define GPT_OCR_COMP_MASK                        (0xFFFFFFFFU)
53946 #define GPT_OCR_COMP_SHIFT                       (0U)
53947 /*! COMP - Compare Value */
53948 #define GPT_OCR_COMP(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
53949 /*! @} */
53950 
53951 /* The count of GPT_OCR */
53952 #define GPT_OCR_COUNT                            (3U)
53953 
53954 /*! @name ICR - GPT Input Capture Register */
53955 /*! @{ */
53956 
53957 #define GPT_ICR_CAPT_MASK                        (0xFFFFFFFFU)
53958 #define GPT_ICR_CAPT_SHIFT                       (0U)
53959 /*! CAPT - Capture Value */
53960 #define GPT_ICR_CAPT(x)                          (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
53961 /*! @} */
53962 
53963 /* The count of GPT_ICR */
53964 #define GPT_ICR_COUNT                            (2U)
53965 
53966 /*! @name CNT - GPT Counter Register */
53967 /*! @{ */
53968 
53969 #define GPT_CNT_COUNT_MASK                       (0xFFFFFFFFU)
53970 #define GPT_CNT_COUNT_SHIFT                      (0U)
53971 /*! COUNT - Counter Value */
53972 #define GPT_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
53973 /*! @} */
53974 
53975 
53976 /*!
53977  * @}
53978  */ /* end of group GPT_Register_Masks */
53979 
53980 
53981 /* GPT - Peripheral instance base addresses */
53982 /** Peripheral GPT1 base address */
53983 #define GPT1_BASE                                (0x400EC000u)
53984 /** Peripheral GPT1 base pointer */
53985 #define GPT1                                     ((GPT_Type *)GPT1_BASE)
53986 /** Peripheral GPT2 base address */
53987 #define GPT2_BASE                                (0x400F0000u)
53988 /** Peripheral GPT2 base pointer */
53989 #define GPT2                                     ((GPT_Type *)GPT2_BASE)
53990 /** Peripheral GPT3 base address */
53991 #define GPT3_BASE                                (0x400F4000u)
53992 /** Peripheral GPT3 base pointer */
53993 #define GPT3                                     ((GPT_Type *)GPT3_BASE)
53994 /** Peripheral GPT4 base address */
53995 #define GPT4_BASE                                (0x400F8000u)
53996 /** Peripheral GPT4 base pointer */
53997 #define GPT4                                     ((GPT_Type *)GPT4_BASE)
53998 /** Peripheral GPT5 base address */
53999 #define GPT5_BASE                                (0x400FC000u)
54000 /** Peripheral GPT5 base pointer */
54001 #define GPT5                                     ((GPT_Type *)GPT5_BASE)
54002 /** Peripheral GPT6 base address */
54003 #define GPT6_BASE                                (0x40100000u)
54004 /** Peripheral GPT6 base pointer */
54005 #define GPT6                                     ((GPT_Type *)GPT6_BASE)
54006 /** Array initializer of GPT peripheral base addresses */
54007 #define GPT_BASE_ADDRS                           { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE, GPT5_BASE, GPT6_BASE }
54008 /** Array initializer of GPT peripheral base pointers */
54009 #define GPT_BASE_PTRS                            { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6 }
54010 /** Interrupt vectors for the GPT peripheral type */
54011 #define GPT_IRQS                                 { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn, GPT5_IRQn, GPT6_IRQn }
54012 
54013 /*!
54014  * @}
54015  */ /* end of group GPT_Peripheral_Access_Layer */
54016 
54017 
54018 /* ----------------------------------------------------------------------------
54019    -- I2S Peripheral Access Layer
54020    ---------------------------------------------------------------------------- */
54021 
54022 /*!
54023  * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
54024  * @{
54025  */
54026 
54027 /** I2S - Register Layout Typedef */
54028 typedef struct {
54029   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
54030   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
54031   __IO uint32_t TCSR;                              /**< Transmit Control, offset: 0x8 */
54032   __IO uint32_t TCR1;                              /**< Transmit Configuration 1, offset: 0xC */
54033   __IO uint32_t TCR2;                              /**< Transmit Configuration 2, offset: 0x10 */
54034   __IO uint32_t TCR3;                              /**< Transmit Configuration 3, offset: 0x14 */
54035   __IO uint32_t TCR4;                              /**< Transmit Configuration 4, offset: 0x18 */
54036   __IO uint32_t TCR5;                              /**< Transmit Configuration 5, offset: 0x1C */
54037   __O  uint32_t TDR[4];                            /**< Transmit Data, array offset: 0x20, array step: 0x4, irregular array, not all indices are valid */
54038        uint8_t RESERVED_0[16];
54039   __I  uint32_t TFR[4];                            /**< Transmit FIFO, array offset: 0x40, array step: 0x4, irregular array, not all indices are valid */
54040        uint8_t RESERVED_1[16];
54041   __IO uint32_t TMR;                               /**< Transmit Mask, offset: 0x60 */
54042        uint8_t RESERVED_2[36];
54043   __IO uint32_t RCSR;                              /**< Receive Control, offset: 0x88 */
54044   __IO uint32_t RCR1;                              /**< Receive Configuration 1, offset: 0x8C */
54045   __IO uint32_t RCR2;                              /**< Receive Configuration 2, offset: 0x90 */
54046   __IO uint32_t RCR3;                              /**< Receive Configuration 3, offset: 0x94 */
54047   __IO uint32_t RCR4;                              /**< Receive Configuration 4, offset: 0x98 */
54048   __IO uint32_t RCR5;                              /**< Receive Configuration 5, offset: 0x9C */
54049   __I  uint32_t RDR[4];                            /**< Receive Data, array offset: 0xA0, array step: 0x4, irregular array, not all indices are valid */
54050        uint8_t RESERVED_3[16];
54051   __I  uint32_t RFR[4];                            /**< Receive FIFO, array offset: 0xC0, array step: 0x4, irregular array, not all indices are valid */
54052        uint8_t RESERVED_4[16];
54053   __IO uint32_t RMR;                               /**< Receive Mask, offset: 0xE0 */
54054 } I2S_Type;
54055 
54056 /* ----------------------------------------------------------------------------
54057    -- I2S Register Masks
54058    ---------------------------------------------------------------------------- */
54059 
54060 /*!
54061  * @addtogroup I2S_Register_Masks I2S Register Masks
54062  * @{
54063  */
54064 
54065 /*! @name VERID - Version ID */
54066 /*! @{ */
54067 
54068 #define I2S_VERID_FEATURE_MASK                   (0xFFFFU)
54069 #define I2S_VERID_FEATURE_SHIFT                  (0U)
54070 /*! FEATURE - Feature Specification Number
54071  *  0b0000000000000000..Standard feature set.
54072  */
54073 #define I2S_VERID_FEATURE(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
54074 
54075 #define I2S_VERID_MINOR_MASK                     (0xFF0000U)
54076 #define I2S_VERID_MINOR_SHIFT                    (16U)
54077 /*! MINOR - Minor Version Number */
54078 #define I2S_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
54079 
54080 #define I2S_VERID_MAJOR_MASK                     (0xFF000000U)
54081 #define I2S_VERID_MAJOR_SHIFT                    (24U)
54082 /*! MAJOR - Major Version Number */
54083 #define I2S_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
54084 /*! @} */
54085 
54086 /*! @name PARAM - Parameter */
54087 /*! @{ */
54088 
54089 #define I2S_PARAM_DATALINE_MASK                  (0xFU)
54090 #define I2S_PARAM_DATALINE_SHIFT                 (0U)
54091 /*! DATALINE - Number of Datalines */
54092 #define I2S_PARAM_DATALINE(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
54093 
54094 #define I2S_PARAM_FIFO_MASK                      (0xF00U)
54095 #define I2S_PARAM_FIFO_SHIFT                     (8U)
54096 /*! FIFO - FIFO Size */
54097 #define I2S_PARAM_FIFO(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
54098 
54099 #define I2S_PARAM_FRAME_MASK                     (0xF0000U)
54100 #define I2S_PARAM_FRAME_SHIFT                    (16U)
54101 /*! FRAME - Frame Size */
54102 #define I2S_PARAM_FRAME(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
54103 /*! @} */
54104 
54105 /*! @name TCSR - Transmit Control */
54106 /*! @{ */
54107 
54108 #define I2S_TCSR_FRDE_MASK                       (0x1U)
54109 #define I2S_TCSR_FRDE_SHIFT                      (0U)
54110 /*! FRDE - FIFO Request DMA Enable
54111  *  0b0..Disables the DMA request.
54112  *  0b1..Enables the DMA request.
54113  */
54114 #define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
54115 
54116 #define I2S_TCSR_FWDE_MASK                       (0x2U)
54117 #define I2S_TCSR_FWDE_SHIFT                      (1U)
54118 /*! FWDE - FIFO Warning DMA Enable
54119  *  0b0..Disables the DMA request.
54120  *  0b1..Enables the DMA request.
54121  */
54122 #define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
54123 
54124 #define I2S_TCSR_FRIE_MASK                       (0x100U)
54125 #define I2S_TCSR_FRIE_SHIFT                      (8U)
54126 /*! FRIE - FIFO Request Interrupt Enable
54127  *  0b0..Disables the interrupt.
54128  *  0b1..Enables the interrupt.
54129  */
54130 #define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
54131 
54132 #define I2S_TCSR_FWIE_MASK                       (0x200U)
54133 #define I2S_TCSR_FWIE_SHIFT                      (9U)
54134 /*! FWIE - FIFO Warning Interrupt Enable
54135  *  0b0..Disables the interrupt.
54136  *  0b1..Enables the interrupt.
54137  */
54138 #define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
54139 
54140 #define I2S_TCSR_FEIE_MASK                       (0x400U)
54141 #define I2S_TCSR_FEIE_SHIFT                      (10U)
54142 /*! FEIE - FIFO Error Interrupt Enable
54143  *  0b0..Disables the interrupt.
54144  *  0b1..Enables the interrupt.
54145  */
54146 #define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
54147 
54148 #define I2S_TCSR_SEIE_MASK                       (0x800U)
54149 #define I2S_TCSR_SEIE_SHIFT                      (11U)
54150 /*! SEIE - Sync Error Interrupt Enable
54151  *  0b0..Disables interrupt.
54152  *  0b1..Enables interrupt.
54153  */
54154 #define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
54155 
54156 #define I2S_TCSR_WSIE_MASK                       (0x1000U)
54157 #define I2S_TCSR_WSIE_SHIFT                      (12U)
54158 /*! WSIE - Word Start Interrupt Enable
54159  *  0b0..Disables interrupt.
54160  *  0b1..Enables interrupt.
54161  */
54162 #define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
54163 
54164 #define I2S_TCSR_FRF_MASK                        (0x10000U)
54165 #define I2S_TCSR_FRF_SHIFT                       (16U)
54166 /*! FRF - FIFO Request Flag
54167  *  0b0..Transmit FIFO watermark has not been reached.
54168  *  0b1..Transmit FIFO watermark has been reached.
54169  */
54170 #define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
54171 
54172 #define I2S_TCSR_FWF_MASK                        (0x20000U)
54173 #define I2S_TCSR_FWF_SHIFT                       (17U)
54174 /*! FWF - FIFO Warning Flag
54175  *  0b0..No enabled transmit FIFO is empty.
54176  *  0b1..Enabled transmit FIFO is empty.
54177  */
54178 #define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
54179 
54180 #define I2S_TCSR_FEF_MASK                        (0x40000U)
54181 #define I2S_TCSR_FEF_SHIFT                       (18U)
54182 /*! FEF - FIFO Error Flag
54183  *  0b0..Transmit underrun not detected.
54184  *  0b1..Transmit underrun detected.
54185  */
54186 #define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
54187 
54188 #define I2S_TCSR_SEF_MASK                        (0x80000U)
54189 #define I2S_TCSR_SEF_SHIFT                       (19U)
54190 /*! SEF - Sync Error Flag
54191  *  0b0..Sync error not detected.
54192  *  0b1..Frame sync error detected.
54193  */
54194 #define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
54195 
54196 #define I2S_TCSR_WSF_MASK                        (0x100000U)
54197 #define I2S_TCSR_WSF_SHIFT                       (20U)
54198 /*! WSF - Word Start Flag
54199  *  0b0..Start of word not detected.
54200  *  0b1..Start of word detected.
54201  */
54202 #define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
54203 
54204 #define I2S_TCSR_SR_MASK                         (0x1000000U)
54205 #define I2S_TCSR_SR_SHIFT                        (24U)
54206 /*! SR - Software Reset
54207  *  0b0..No effect.
54208  *  0b1..Software reset.
54209  */
54210 #define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
54211 
54212 #define I2S_TCSR_FR_MASK                         (0x2000000U)
54213 #define I2S_TCSR_FR_SHIFT                        (25U)
54214 /*! FR - FIFO Reset
54215  *  0b0..No effect.
54216  *  0b1..FIFO reset.
54217  */
54218 #define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
54219 
54220 #define I2S_TCSR_BCE_MASK                        (0x10000000U)
54221 #define I2S_TCSR_BCE_SHIFT                       (28U)
54222 /*! BCE - Bit Clock Enable
54223  *  0b0..Transmit bit clock is disabled.
54224  *  0b1..Transmit bit clock is enabled.
54225  */
54226 #define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
54227 
54228 #define I2S_TCSR_DBGE_MASK                       (0x20000000U)
54229 #define I2S_TCSR_DBGE_SHIFT                      (29U)
54230 /*! DBGE - Debug Enable
54231  *  0b0..Transmitter is disabled in Debug mode, after completing the current frame.
54232  *  0b1..Transmitter is enabled in Debug mode.
54233  */
54234 #define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
54235 
54236 #define I2S_TCSR_STOPE_MASK                      (0x40000000U)
54237 #define I2S_TCSR_STOPE_SHIFT                     (30U)
54238 /*! STOPE - Stop Enable
54239  *  0b0..Transmitter disabled in Stop mode.
54240  *  0b1..Transmitter enabled in Stop mode.
54241  */
54242 #define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
54243 
54244 #define I2S_TCSR_TE_MASK                         (0x80000000U)
54245 #define I2S_TCSR_TE_SHIFT                        (31U)
54246 /*! TE - Transmitter Enable
54247  *  0b0..Transmitter is disabled.
54248  *  0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
54249  */
54250 #define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
54251 /*! @} */
54252 
54253 /*! @name TCR1 - Transmit Configuration 1 */
54254 /*! @{ */
54255 
54256 #define I2S_TCR1_TFW_MASK                        (0x1FU)
54257 #define I2S_TCR1_TFW_SHIFT                       (0U)
54258 /*! TFW - Transmit FIFO Watermark */
54259 #define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
54260 /*! @} */
54261 
54262 /*! @name TCR2 - Transmit Configuration 2 */
54263 /*! @{ */
54264 
54265 #define I2S_TCR2_DIV_MASK                        (0xFFU)
54266 #define I2S_TCR2_DIV_SHIFT                       (0U)
54267 /*! DIV - Bit Clock Divide */
54268 #define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
54269 
54270 #define I2S_TCR2_BYP_MASK                        (0x800000U)
54271 #define I2S_TCR2_BYP_SHIFT                       (23U)
54272 /*! BYP - Bit Clock Bypass
54273  *  0b0..Internal bit clock is generated from bit clock divider.
54274  *  0b1..Internal bit clock is divide by one of the audio master clock.
54275  */
54276 #define I2S_TCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)
54277 
54278 #define I2S_TCR2_BCD_MASK                        (0x1000000U)
54279 #define I2S_TCR2_BCD_SHIFT                       (24U)
54280 /*! BCD - Bit Clock Direction
54281  *  0b0..Bit clock is generated externally in Slave mode.
54282  *  0b1..Bit clock is generated internally in Master mode.
54283  */
54284 #define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
54285 
54286 #define I2S_TCR2_BCP_MASK                        (0x2000000U)
54287 #define I2S_TCR2_BCP_SHIFT                       (25U)
54288 /*! BCP - Bit Clock Polarity
54289  *  0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
54290  *  0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
54291  */
54292 #define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
54293 
54294 #define I2S_TCR2_MSEL_MASK                       (0xC000000U)
54295 #define I2S_TCR2_MSEL_SHIFT                      (26U)
54296 /*! MSEL - MCLK Select
54297  *  0b00..Bus Clock selected.
54298  *  0b01..Master Clock (MCLK) 1 option selected.
54299  *  0b10..Master Clock (MCLK) 2 option selected.
54300  *  0b11..Master Clock (MCLK) 3 option selected.
54301  */
54302 #define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
54303 
54304 #define I2S_TCR2_BCI_MASK                        (0x10000000U)
54305 #define I2S_TCR2_BCI_SHIFT                       (28U)
54306 /*! BCI - Bit Clock Input
54307  *  0b0..No effect.
54308  *  0b1..Internal logic is clocked as if bit clock was externally generated.
54309  */
54310 #define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
54311 
54312 #define I2S_TCR2_BCS_MASK                        (0x20000000U)
54313 #define I2S_TCR2_BCS_SHIFT                       (29U)
54314 /*! BCS - Bit Clock Swap
54315  *  0b0..Use the normal bit clock source.
54316  *  0b1..Swap the bit clock source.
54317  */
54318 #define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
54319 
54320 #define I2S_TCR2_SYNC_MASK                       (0x40000000U)
54321 #define I2S_TCR2_SYNC_SHIFT                      (30U)
54322 /*! SYNC - Synchronous Mode
54323  *  0b0..Asynchronous mode.
54324  *  0b1..Synchronous with receiver.
54325  */
54326 #define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
54327 /*! @} */
54328 
54329 /*! @name TCR3 - Transmit Configuration 3 */
54330 /*! @{ */
54331 
54332 #define I2S_TCR3_WDFL_MASK                       (0x1FU)
54333 #define I2S_TCR3_WDFL_SHIFT                      (0U)
54334 /*! WDFL - Word Flag Configuration */
54335 #define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
54336 
54337 #define I2S_TCR3_TCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
54338 #define I2S_TCR3_TCE_SHIFT                       (16U)
54339 /*! TCE - Transmit Channel Enable */
54340 #define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
54341 
54342 #define I2S_TCR3_CFR_MASK                        (0xF000000U)
54343 #define I2S_TCR3_CFR_SHIFT                       (24U)
54344 /*! CFR - Channel FIFO Reset */
54345 #define I2S_TCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
54346 /*! @} */
54347 
54348 /*! @name TCR4 - Transmit Configuration 4 */
54349 /*! @{ */
54350 
54351 #define I2S_TCR4_FSD_MASK                        (0x1U)
54352 #define I2S_TCR4_FSD_SHIFT                       (0U)
54353 /*! FSD - Frame Sync Direction
54354  *  0b0..Frame sync is generated externally in Slave mode.
54355  *  0b1..Frame sync is generated internally in Master mode.
54356  */
54357 #define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
54358 
54359 #define I2S_TCR4_FSP_MASK                        (0x2U)
54360 #define I2S_TCR4_FSP_SHIFT                       (1U)
54361 /*! FSP - Frame Sync Polarity
54362  *  0b0..Frame sync is active high.
54363  *  0b1..Frame sync is active low.
54364  */
54365 #define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
54366 
54367 #define I2S_TCR4_ONDEM_MASK                      (0x4U)
54368 #define I2S_TCR4_ONDEM_SHIFT                     (2U)
54369 /*! ONDEM - On Demand Mode
54370  *  0b0..Internal frame sync is generated continuously.
54371  *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
54372  */
54373 #define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
54374 
54375 #define I2S_TCR4_FSE_MASK                        (0x8U)
54376 #define I2S_TCR4_FSE_SHIFT                       (3U)
54377 /*! FSE - Frame Sync Early
54378  *  0b0..Frame sync asserts with the first bit of the frame.
54379  *  0b1..Frame sync asserts one bit before the first bit of the frame.
54380  */
54381 #define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
54382 
54383 #define I2S_TCR4_MF_MASK                         (0x10U)
54384 #define I2S_TCR4_MF_SHIFT                        (4U)
54385 /*! MF - MSB First
54386  *  0b0..LSB is transmitted first.
54387  *  0b1..MSB is transmitted first.
54388  */
54389 #define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
54390 
54391 #define I2S_TCR4_CHMOD_MASK                      (0x20U)
54392 #define I2S_TCR4_CHMOD_SHIFT                     (5U)
54393 /*! CHMOD - Channel Mode
54394  *  0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
54395  *  0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
54396  */
54397 #define I2S_TCR4_CHMOD(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
54398 
54399 #define I2S_TCR4_SYWD_MASK                       (0x1F00U)
54400 #define I2S_TCR4_SYWD_SHIFT                      (8U)
54401 /*! SYWD - Sync Width */
54402 #define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
54403 
54404 #define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)
54405 #define I2S_TCR4_FRSZ_SHIFT                      (16U)
54406 /*! FRSZ - Frame size */
54407 #define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
54408 
54409 #define I2S_TCR4_FPACK_MASK                      (0x3000000U)
54410 #define I2S_TCR4_FPACK_SHIFT                     (24U)
54411 /*! FPACK - FIFO Packing Mode
54412  *  0b00..FIFO packing is disabled.
54413  *  0b01..Reserved
54414  *  0b10..8-bit FIFO packing is enabled.
54415  *  0b11..16-bit FIFO packing is enabled.
54416  */
54417 #define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
54418 
54419 #define I2S_TCR4_FCOMB_MASK                      (0xC000000U)
54420 #define I2S_TCR4_FCOMB_SHIFT                     (26U)
54421 /*! FCOMB - FIFO Combine Mode
54422  *  0b00..FIFO combine mode disabled.
54423  *  0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
54424  *  0b10..FIFO combine mode enabled on FIFO writes (by software).
54425  *  0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
54426  */
54427 #define I2S_TCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
54428 
54429 #define I2S_TCR4_FCONT_MASK                      (0x10000000U)
54430 #define I2S_TCR4_FCONT_SHIFT                     (28U)
54431 /*! FCONT - FIFO Continue on Error
54432  *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
54433  *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
54434  */
54435 #define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
54436 /*! @} */
54437 
54438 /*! @name TCR5 - Transmit Configuration 5 */
54439 /*! @{ */
54440 
54441 #define I2S_TCR5_FBT_MASK                        (0x1F00U)
54442 #define I2S_TCR5_FBT_SHIFT                       (8U)
54443 /*! FBT - First Bit Shifted */
54444 #define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
54445 
54446 #define I2S_TCR5_W0W_MASK                        (0x1F0000U)
54447 #define I2S_TCR5_W0W_SHIFT                       (16U)
54448 /*! W0W - Word 0 Width */
54449 #define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
54450 
54451 #define I2S_TCR5_WNW_MASK                        (0x1F000000U)
54452 #define I2S_TCR5_WNW_SHIFT                       (24U)
54453 /*! WNW - Word N Width */
54454 #define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
54455 /*! @} */
54456 
54457 /*! @name TDR - Transmit Data */
54458 /*! @{ */
54459 
54460 #define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
54461 #define I2S_TDR_TDR_SHIFT                        (0U)
54462 /*! TDR - Transmit Data Register */
54463 #define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
54464 /*! @} */
54465 
54466 /* The count of I2S_TDR */
54467 #define I2S_TDR_COUNT                            (4U)
54468 
54469 /*! @name TFR - Transmit FIFO */
54470 /*! @{ */
54471 
54472 #define I2S_TFR_RFP_MASK                         (0x3FU)
54473 #define I2S_TFR_RFP_SHIFT                        (0U)
54474 /*! RFP - Read FIFO Pointer */
54475 #define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
54476 
54477 #define I2S_TFR_WFP_MASK                         (0x3F0000U)
54478 #define I2S_TFR_WFP_SHIFT                        (16U)
54479 /*! WFP - Write FIFO Pointer */
54480 #define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
54481 
54482 #define I2S_TFR_WCP_MASK                         (0x80000000U)
54483 #define I2S_TFR_WCP_SHIFT                        (31U)
54484 /*! WCP - Write Channel Pointer
54485  *  0b0..No effect.
54486  *  0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
54487  */
54488 #define I2S_TFR_WCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
54489 /*! @} */
54490 
54491 /* The count of I2S_TFR */
54492 #define I2S_TFR_COUNT                            (4U)
54493 
54494 /*! @name TMR - Transmit Mask */
54495 /*! @{ */
54496 
54497 #define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)
54498 #define I2S_TMR_TWM_SHIFT                        (0U)
54499 /*! TWM - Transmit Word Mask
54500  *  0b00000000000000000000000000000000..Word N is enabled.
54501  *  0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
54502  */
54503 #define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
54504 /*! @} */
54505 
54506 /*! @name RCSR - Receive Control */
54507 /*! @{ */
54508 
54509 #define I2S_RCSR_FRDE_MASK                       (0x1U)
54510 #define I2S_RCSR_FRDE_SHIFT                      (0U)
54511 /*! FRDE - FIFO Request DMA Enable
54512  *  0b0..Disables the DMA request.
54513  *  0b1..Enables the DMA request.
54514  */
54515 #define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
54516 
54517 #define I2S_RCSR_FWDE_MASK                       (0x2U)
54518 #define I2S_RCSR_FWDE_SHIFT                      (1U)
54519 /*! FWDE - FIFO Warning DMA Enable
54520  *  0b0..Disables the DMA request.
54521  *  0b1..Enables the DMA request.
54522  */
54523 #define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
54524 
54525 #define I2S_RCSR_FRIE_MASK                       (0x100U)
54526 #define I2S_RCSR_FRIE_SHIFT                      (8U)
54527 /*! FRIE - FIFO Request Interrupt Enable
54528  *  0b0..Disables the interrupt.
54529  *  0b1..Enables the interrupt.
54530  */
54531 #define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
54532 
54533 #define I2S_RCSR_FWIE_MASK                       (0x200U)
54534 #define I2S_RCSR_FWIE_SHIFT                      (9U)
54535 /*! FWIE - FIFO Warning Interrupt Enable
54536  *  0b0..Disables the interrupt.
54537  *  0b1..Enables the interrupt.
54538  */
54539 #define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
54540 
54541 #define I2S_RCSR_FEIE_MASK                       (0x400U)
54542 #define I2S_RCSR_FEIE_SHIFT                      (10U)
54543 /*! FEIE - FIFO Error Interrupt Enable
54544  *  0b0..Disables the interrupt.
54545  *  0b1..Enables the interrupt.
54546  */
54547 #define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
54548 
54549 #define I2S_RCSR_SEIE_MASK                       (0x800U)
54550 #define I2S_RCSR_SEIE_SHIFT                      (11U)
54551 /*! SEIE - Sync Error Interrupt Enable
54552  *  0b0..Disables interrupt.
54553  *  0b1..Enables interrupt.
54554  */
54555 #define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
54556 
54557 #define I2S_RCSR_WSIE_MASK                       (0x1000U)
54558 #define I2S_RCSR_WSIE_SHIFT                      (12U)
54559 /*! WSIE - Word Start Interrupt Enable
54560  *  0b0..Disables interrupt.
54561  *  0b1..Enables interrupt.
54562  */
54563 #define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
54564 
54565 #define I2S_RCSR_FRF_MASK                        (0x10000U)
54566 #define I2S_RCSR_FRF_SHIFT                       (16U)
54567 /*! FRF - FIFO Request Flag
54568  *  0b0..Receive FIFO watermark not reached.
54569  *  0b1..Receive FIFO watermark has been reached.
54570  */
54571 #define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
54572 
54573 #define I2S_RCSR_FWF_MASK                        (0x20000U)
54574 #define I2S_RCSR_FWF_SHIFT                       (17U)
54575 /*! FWF - FIFO Warning Flag
54576  *  0b0..No enabled receive FIFO is full.
54577  *  0b1..Enabled receive FIFO is full.
54578  */
54579 #define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
54580 
54581 #define I2S_RCSR_FEF_MASK                        (0x40000U)
54582 #define I2S_RCSR_FEF_SHIFT                       (18U)
54583 /*! FEF - FIFO Error Flag
54584  *  0b0..Receive overflow not detected.
54585  *  0b1..Receive overflow detected.
54586  */
54587 #define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
54588 
54589 #define I2S_RCSR_SEF_MASK                        (0x80000U)
54590 #define I2S_RCSR_SEF_SHIFT                       (19U)
54591 /*! SEF - Sync Error Flag
54592  *  0b0..Sync error not detected.
54593  *  0b1..Frame sync error detected.
54594  */
54595 #define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
54596 
54597 #define I2S_RCSR_WSF_MASK                        (0x100000U)
54598 #define I2S_RCSR_WSF_SHIFT                       (20U)
54599 /*! WSF - Word Start Flag
54600  *  0b0..Start of word not detected.
54601  *  0b1..Start of word detected.
54602  */
54603 #define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
54604 
54605 #define I2S_RCSR_SR_MASK                         (0x1000000U)
54606 #define I2S_RCSR_SR_SHIFT                        (24U)
54607 /*! SR - Software Reset
54608  *  0b0..No effect.
54609  *  0b1..Software reset.
54610  */
54611 #define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
54612 
54613 #define I2S_RCSR_FR_MASK                         (0x2000000U)
54614 #define I2S_RCSR_FR_SHIFT                        (25U)
54615 /*! FR - FIFO Reset
54616  *  0b0..No effect.
54617  *  0b1..FIFO reset.
54618  */
54619 #define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
54620 
54621 #define I2S_RCSR_BCE_MASK                        (0x10000000U)
54622 #define I2S_RCSR_BCE_SHIFT                       (28U)
54623 /*! BCE - Bit Clock Enable
54624  *  0b0..Receive bit clock is disabled.
54625  *  0b1..Receive bit clock is enabled.
54626  */
54627 #define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
54628 
54629 #define I2S_RCSR_DBGE_MASK                       (0x20000000U)
54630 #define I2S_RCSR_DBGE_SHIFT                      (29U)
54631 /*! DBGE - Debug Enable
54632  *  0b0..Receiver is disabled in Debug mode, after completing the current frame.
54633  *  0b1..Receiver is enabled in Debug mode.
54634  */
54635 #define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
54636 
54637 #define I2S_RCSR_STOPE_MASK                      (0x40000000U)
54638 #define I2S_RCSR_STOPE_SHIFT                     (30U)
54639 /*! STOPE - Stop Enable
54640  *  0b0..Receiver disabled in Stop mode.
54641  *  0b1..Receiver enabled in Stop mode.
54642  */
54643 #define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
54644 
54645 #define I2S_RCSR_RE_MASK                         (0x80000000U)
54646 #define I2S_RCSR_RE_SHIFT                        (31U)
54647 /*! RE - Receiver Enable
54648  *  0b0..Receiver is disabled.
54649  *  0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
54650  */
54651 #define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
54652 /*! @} */
54653 
54654 /*! @name RCR1 - Receive Configuration 1 */
54655 /*! @{ */
54656 
54657 #define I2S_RCR1_RFW_MASK                        (0x1FU)
54658 #define I2S_RCR1_RFW_SHIFT                       (0U)
54659 /*! RFW - Receive FIFO Watermark */
54660 #define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
54661 /*! @} */
54662 
54663 /*! @name RCR2 - Receive Configuration 2 */
54664 /*! @{ */
54665 
54666 #define I2S_RCR2_DIV_MASK                        (0xFFU)
54667 #define I2S_RCR2_DIV_SHIFT                       (0U)
54668 /*! DIV - Bit Clock Divide */
54669 #define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
54670 
54671 #define I2S_RCR2_BYP_MASK                        (0x800000U)
54672 #define I2S_RCR2_BYP_SHIFT                       (23U)
54673 /*! BYP - Bit Clock Bypass
54674  *  0b0..Internal bit clock is generated from bit clock divider.
54675  *  0b1..Internal bit clock is divide by one of the audio master clock.
54676  */
54677 #define I2S_RCR2_BYP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)
54678 
54679 #define I2S_RCR2_BCD_MASK                        (0x1000000U)
54680 #define I2S_RCR2_BCD_SHIFT                       (24U)
54681 /*! BCD - Bit Clock Direction
54682  *  0b0..Bit clock is generated externally in Slave mode.
54683  *  0b1..Bit clock is generated internally in Master mode.
54684  */
54685 #define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
54686 
54687 #define I2S_RCR2_BCP_MASK                        (0x2000000U)
54688 #define I2S_RCR2_BCP_SHIFT                       (25U)
54689 /*! BCP - Bit Clock Polarity
54690  *  0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
54691  *  0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
54692  */
54693 #define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
54694 
54695 #define I2S_RCR2_MSEL_MASK                       (0xC000000U)
54696 #define I2S_RCR2_MSEL_SHIFT                      (26U)
54697 /*! MSEL - MCLK Select
54698  *  0b00..Bus Clock selected.
54699  *  0b01..Master Clock (MCLK) 1 option selected.
54700  *  0b10..Master Clock (MCLK) 2 option selected.
54701  *  0b11..Master Clock (MCLK) 3 option selected.
54702  */
54703 #define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
54704 
54705 #define I2S_RCR2_BCI_MASK                        (0x10000000U)
54706 #define I2S_RCR2_BCI_SHIFT                       (28U)
54707 /*! BCI - Bit Clock Input
54708  *  0b0..No effect.
54709  *  0b1..Internal logic is clocked as if bit clock was externally generated.
54710  */
54711 #define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
54712 
54713 #define I2S_RCR2_BCS_MASK                        (0x20000000U)
54714 #define I2S_RCR2_BCS_SHIFT                       (29U)
54715 /*! BCS - Bit Clock Swap
54716  *  0b0..Use the normal bit clock source.
54717  *  0b1..Swap the bit clock source.
54718  */
54719 #define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
54720 
54721 #define I2S_RCR2_SYNC_MASK                       (0x40000000U)
54722 #define I2S_RCR2_SYNC_SHIFT                      (30U)
54723 /*! SYNC - Synchronous Mode
54724  *  0b0..Asynchronous mode.
54725  *  0b1..Synchronous with transmitter.
54726  */
54727 #define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
54728 /*! @} */
54729 
54730 /*! @name RCR3 - Receive Configuration 3 */
54731 /*! @{ */
54732 
54733 #define I2S_RCR3_WDFL_MASK                       (0x1FU)
54734 #define I2S_RCR3_WDFL_SHIFT                      (0U)
54735 /*! WDFL - Word Flag Configuration */
54736 #define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
54737 
54738 #define I2S_RCR3_RCE_MASK                        (0xF0000U)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
54739 #define I2S_RCR3_RCE_SHIFT                       (16U)
54740 /*! RCE - Receive Channel Enable */
54741 #define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)  /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
54742 
54743 #define I2S_RCR3_CFR_MASK                        (0xF000000U)
54744 #define I2S_RCR3_CFR_SHIFT                       (24U)
54745 /*! CFR - Channel FIFO Reset */
54746 #define I2S_RCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
54747 /*! @} */
54748 
54749 /*! @name RCR4 - Receive Configuration 4 */
54750 /*! @{ */
54751 
54752 #define I2S_RCR4_FSD_MASK                        (0x1U)
54753 #define I2S_RCR4_FSD_SHIFT                       (0U)
54754 /*! FSD - Frame Sync Direction
54755  *  0b0..Frame Sync is generated externally in Slave mode.
54756  *  0b1..Frame Sync is generated internally in Master mode.
54757  */
54758 #define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
54759 
54760 #define I2S_RCR4_FSP_MASK                        (0x2U)
54761 #define I2S_RCR4_FSP_SHIFT                       (1U)
54762 /*! FSP - Frame Sync Polarity
54763  *  0b0..Frame sync is active high.
54764  *  0b1..Frame sync is active low.
54765  */
54766 #define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
54767 
54768 #define I2S_RCR4_ONDEM_MASK                      (0x4U)
54769 #define I2S_RCR4_ONDEM_SHIFT                     (2U)
54770 /*! ONDEM - On Demand Mode
54771  *  0b0..Internal frame sync is generated continuously.
54772  *  0b1..Internal frame sync is generated when the FIFO warning flag is clear.
54773  */
54774 #define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
54775 
54776 #define I2S_RCR4_FSE_MASK                        (0x8U)
54777 #define I2S_RCR4_FSE_SHIFT                       (3U)
54778 /*! FSE - Frame Sync Early
54779  *  0b0..Frame sync asserts with the first bit of the frame.
54780  *  0b1..Frame sync asserts one bit before the first bit of the frame.
54781  */
54782 #define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
54783 
54784 #define I2S_RCR4_MF_MASK                         (0x10U)
54785 #define I2S_RCR4_MF_SHIFT                        (4U)
54786 /*! MF - MSB First
54787  *  0b0..LSB is received first.
54788  *  0b1..MSB is received first.
54789  */
54790 #define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
54791 
54792 #define I2S_RCR4_SYWD_MASK                       (0x1F00U)
54793 #define I2S_RCR4_SYWD_SHIFT                      (8U)
54794 /*! SYWD - Sync Width */
54795 #define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
54796 
54797 #define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)
54798 #define I2S_RCR4_FRSZ_SHIFT                      (16U)
54799 /*! FRSZ - Frame Size */
54800 #define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
54801 
54802 #define I2S_RCR4_FPACK_MASK                      (0x3000000U)
54803 #define I2S_RCR4_FPACK_SHIFT                     (24U)
54804 /*! FPACK - FIFO Packing Mode
54805  *  0b00..FIFO packing is disabled
54806  *  0b01..Reserved.
54807  *  0b10..8-bit FIFO packing is enabled
54808  *  0b11..16-bit FIFO packing is enabled
54809  */
54810 #define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
54811 
54812 #define I2S_RCR4_FCOMB_MASK                      (0xC000000U)
54813 #define I2S_RCR4_FCOMB_SHIFT                     (26U)
54814 /*! FCOMB - FIFO Combine Mode
54815  *  0b00..FIFO combine mode disabled.
54816  *  0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
54817  *  0b10..FIFO combine mode enabled on FIFO reads (by software).
54818  *  0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
54819  */
54820 #define I2S_RCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
54821 
54822 #define I2S_RCR4_FCONT_MASK                      (0x10000000U)
54823 #define I2S_RCR4_FCONT_SHIFT                     (28U)
54824 /*! FCONT - FIFO Continue on Error
54825  *  0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
54826  *  0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
54827  */
54828 #define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
54829 /*! @} */
54830 
54831 /*! @name RCR5 - Receive Configuration 5 */
54832 /*! @{ */
54833 
54834 #define I2S_RCR5_FBT_MASK                        (0x1F00U)
54835 #define I2S_RCR5_FBT_SHIFT                       (8U)
54836 /*! FBT - First Bit Shifted */
54837 #define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
54838 
54839 #define I2S_RCR5_W0W_MASK                        (0x1F0000U)
54840 #define I2S_RCR5_W0W_SHIFT                       (16U)
54841 /*! W0W - Word 0 Width */
54842 #define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
54843 
54844 #define I2S_RCR5_WNW_MASK                        (0x1F000000U)
54845 #define I2S_RCR5_WNW_SHIFT                       (24U)
54846 /*! WNW - Word N Width */
54847 #define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
54848 /*! @} */
54849 
54850 /*! @name RDR - Receive Data */
54851 /*! @{ */
54852 
54853 #define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
54854 #define I2S_RDR_RDR_SHIFT                        (0U)
54855 /*! RDR - Receive Data Register */
54856 #define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
54857 /*! @} */
54858 
54859 /* The count of I2S_RDR */
54860 #define I2S_RDR_COUNT                            (4U)
54861 
54862 /*! @name RFR - Receive FIFO */
54863 /*! @{ */
54864 
54865 #define I2S_RFR_RFP_MASK                         (0x3FU)
54866 #define I2S_RFR_RFP_SHIFT                        (0U)
54867 /*! RFP - Read FIFO Pointer */
54868 #define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
54869 
54870 #define I2S_RFR_RCP_MASK                         (0x8000U)
54871 #define I2S_RFR_RCP_SHIFT                        (15U)
54872 /*! RCP - Receive Channel Pointer
54873  *  0b0..No effect.
54874  *  0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
54875  */
54876 #define I2S_RFR_RCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
54877 
54878 #define I2S_RFR_WFP_MASK                         (0x3F0000U)
54879 #define I2S_RFR_WFP_SHIFT                        (16U)
54880 /*! WFP - Write FIFO Pointer */
54881 #define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
54882 /*! @} */
54883 
54884 /* The count of I2S_RFR */
54885 #define I2S_RFR_COUNT                            (4U)
54886 
54887 /*! @name RMR - Receive Mask */
54888 /*! @{ */
54889 
54890 #define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)
54891 #define I2S_RMR_RWM_SHIFT                        (0U)
54892 /*! RWM - Receive Word Mask
54893  *  0b00000000000000000000000000000000..Word N is enabled.
54894  *  0b00000000000000000000000000000001..Word N is masked.
54895  */
54896 #define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
54897 /*! @} */
54898 
54899 
54900 /*!
54901  * @}
54902  */ /* end of group I2S_Register_Masks */
54903 
54904 
54905 /* I2S - Peripheral instance base addresses */
54906 /** Peripheral SAI1 base address */
54907 #define SAI1_BASE                                (0x40404000u)
54908 /** Peripheral SAI1 base pointer */
54909 #define SAI1                                     ((I2S_Type *)SAI1_BASE)
54910 /** Peripheral SAI2 base address */
54911 #define SAI2_BASE                                (0x40408000u)
54912 /** Peripheral SAI2 base pointer */
54913 #define SAI2                                     ((I2S_Type *)SAI2_BASE)
54914 /** Peripheral SAI3 base address */
54915 #define SAI3_BASE                                (0x4040C000u)
54916 /** Peripheral SAI3 base pointer */
54917 #define SAI3                                     ((I2S_Type *)SAI3_BASE)
54918 /** Peripheral SAI4 base address */
54919 #define SAI4_BASE                                (0x40C40000u)
54920 /** Peripheral SAI4 base pointer */
54921 #define SAI4                                     ((I2S_Type *)SAI4_BASE)
54922 /** Array initializer of I2S peripheral base addresses */
54923 #define I2S_BASE_ADDRS                           { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE }
54924 /** Array initializer of I2S peripheral base pointers */
54925 #define I2S_BASE_PTRS                            { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 }
54926 /** Interrupt vectors for the I2S peripheral type */
54927 #define I2S_RX_IRQS                              { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn, SAI4_RX_IRQn }
54928 #define I2S_TX_IRQS                              { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn, SAI4_TX_IRQn }
54929 
54930 /*!
54931  * @}
54932  */ /* end of group I2S_Peripheral_Access_Layer */
54933 
54934 
54935 /* ----------------------------------------------------------------------------
54936    -- IEE Peripheral Access Layer
54937    ---------------------------------------------------------------------------- */
54938 
54939 /*!
54940  * @addtogroup IEE_Peripheral_Access_Layer IEE Peripheral Access Layer
54941  * @{
54942  */
54943 
54944 /** IEE - Register Layout Typedef */
54945 typedef struct {
54946   __IO uint32_t GCFG;                              /**< IEE Global Configuration, offset: 0x0 */
54947   __I  uint32_t STA;                               /**< IEE Status, offset: 0x4 */
54948   __IO uint32_t TSTMD;                             /**< IEE Test Mode Register, offset: 0x8 */
54949   __O  uint32_t DPAMS;                             /**< AES Mask Generation Seed, offset: 0xC */
54950        uint8_t RESERVED_0[16];
54951   __IO uint32_t PC_S_LT;                           /**< Performance Counter, AES Slave Latency Threshold Value, offset: 0x20 */
54952   __IO uint32_t PC_M_LT;                           /**< Performance Counter, AES Master Latency Threshold, offset: 0x24 */
54953        uint8_t RESERVED_1[24];
54954   __IO uint32_t PC_BLK_ENC;                        /**< Performance Counter, Number of AES Block Encryptions, offset: 0x40 */
54955   __IO uint32_t PC_BLK_DEC;                        /**< Performance Counter, Number of AES Block Decryptions, offset: 0x44 */
54956        uint8_t RESERVED_2[8];
54957   __IO uint32_t PC_SR_TRANS;                       /**< Performance Counter, Number of AXI Slave Read Transactions, offset: 0x50 */
54958   __IO uint32_t PC_SW_TRANS;                       /**< Performance Counter, Number of AXI Slave Write Transactions, offset: 0x54 */
54959   __IO uint32_t PC_MR_TRANS;                       /**< Performance Counter, Number of AXI Master Read Transactions, offset: 0x58 */
54960   __IO uint32_t PC_MW_TRANS;                       /**< Performance Counter, Number of AXI Master Write Transactions, offset: 0x5C */
54961        uint8_t RESERVED_3[4];
54962   __IO uint32_t PC_M_MBR;                          /**< Performance Counter, Number of AXI Master Merge Buffer Read Transactions, offset: 0x64 */
54963        uint8_t RESERVED_4[8];
54964   __IO uint32_t PC_SR_TBC_U;                       /**< Performance Counter, Upper Slave Read Transactions Byte Count, offset: 0x70 */
54965   __IO uint32_t PC_SR_TBC_L;                       /**< Performance Counter, Lower Slave Read Transactions Byte Count, offset: 0x74 */
54966   __IO uint32_t PC_SW_TBC_U;                       /**< Performance Counter, Upper Slave Write Transactions Byte Count, offset: 0x78 */
54967   __IO uint32_t PC_SW_TBC_L;                       /**< Performance Counter, Lower Slave Write Transactions Byte Count, offset: 0x7C */
54968   __IO uint32_t PC_MR_TBC_U;                       /**< Performance Counter, Upper Master Read Transactions Byte Count, offset: 0x80 */
54969   __IO uint32_t PC_MR_TBC_L;                       /**< Performance Counter, Lower Master Read Transactions Byte Count, offset: 0x84 */
54970   __IO uint32_t PC_MW_TBC_U;                       /**< Performance Counter, Upper Master Write Transactions Byte Count, offset: 0x88 */
54971   __IO uint32_t PC_MW_TBC_L;                       /**< Performance Counter, Lower Master Write Transactions Byte Count, offset: 0x8C */
54972   __IO uint32_t PC_SR_TLGTT;                       /**< Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold, offset: 0x90 */
54973   __IO uint32_t PC_SW_TLGTT;                       /**< Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold, offset: 0x94 */
54974   __IO uint32_t PC_MR_TLGTT;                       /**< Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold, offset: 0x98 */
54975   __IO uint32_t PC_MW_TLGTT;                       /**< Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold, offset: 0x9C */
54976   __IO uint32_t PC_SR_TLAT_U;                      /**< Performance Counter, Upper Slave Read Latency Count, offset: 0xA0 */
54977   __IO uint32_t PC_SR_TLAT_L;                      /**< Performance Counter, Lower Slave Read Latency Count, offset: 0xA4 */
54978   __IO uint32_t PC_SW_TLAT_U;                      /**< Performance Counter, Upper Slave Write Latency Count, offset: 0xA8 */
54979   __IO uint32_t PC_SW_TLAT_L;                      /**< Performance Counter, Lower Slave Write Latency Count, offset: 0xAC */
54980   __IO uint32_t PC_MR_TLAT_U;                      /**< Performance Counter, Upper Master Read Latency Count, offset: 0xB0 */
54981   __IO uint32_t PC_MR_TLAT_L;                      /**< Performance Counter, Lower Master Read Latency Count, offset: 0xB4 */
54982   __IO uint32_t PC_MW_TLAT_U;                      /**< Performance Counter, Upper Master Write Latency Count, offset: 0xB8 */
54983   __IO uint32_t PC_MW_TLAT_L;                      /**< Performance Counter, Lower Master Write Latency Count, offset: 0xBC */
54984   __IO uint32_t PC_SR_TNRT_U;                      /**< Performance Counter, Upper Slave Read Total Non-Responding Time, offset: 0xC0 */
54985   __IO uint32_t PC_SR_TNRT_L;                      /**< Performance Counter, Lower Slave Read Total Non-Responding Time, offset: 0xC4 */
54986   __IO uint32_t PC_SW_TNRT_U;                      /**< Performance Counter, Upper Slave Write Total Non-Responding Time, offset: 0xC8 */
54987   __IO uint32_t PC_SW_TNRT_L;                      /**< Performance Counter, Lower Slave Write Total Non-Responding Time, offset: 0xCC */
54988        uint8_t RESERVED_5[32];
54989   __I  uint32_t VIDR1;                             /**< IEE Version ID Register 1, offset: 0xF0 */
54990        uint8_t RESERVED_6[4];
54991   __I  uint32_t AESVID;                            /**< IEE AES Version ID Register, offset: 0xF8 */
54992        uint8_t RESERVED_7[4];
54993   struct {                                         /* offset: 0x100, array step: 0x100 */
54994     __IO uint32_t REGATTR;                           /**< IEE Region 0 Attribute Register...IEE Region 7 Attribute Register., array offset: 0x100, array step: 0x100 */
54995          uint8_t RESERVED_0[4];
54996     __IO uint32_t REGPO;                             /**< IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register, array offset: 0x108, array step: 0x100 */
54997          uint8_t RESERVED_1[52];
54998     __O  uint32_t REGKEY1[8];                        /**< IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register, array offset: 0x140, array step: index*0x100, index2*0x4 */
54999          uint8_t RESERVED_2[32];
55000     __O  uint32_t REGKEY2[8];                        /**< IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register, array offset: 0x180, array step: index*0x100, index2*0x4 */
55001          uint8_t RESERVED_3[96];
55002   } REGX[8];
55003        uint8_t RESERVED_8[1536];
55004   __IO uint32_t AES_TST_DB[32];                    /**< IEE AES Test Mode Data Buffer, array offset: 0xF00, array step: 0x4 */
55005 } IEE_Type;
55006 
55007 /* ----------------------------------------------------------------------------
55008    -- IEE Register Masks
55009    ---------------------------------------------------------------------------- */
55010 
55011 /*!
55012  * @addtogroup IEE_Register_Masks IEE Register Masks
55013  * @{
55014  */
55015 
55016 /*! @name GCFG - IEE Global Configuration */
55017 /*! @{ */
55018 
55019 #define IEE_GCFG_RL0_MASK                        (0x1U)
55020 #define IEE_GCFG_RL0_SHIFT                       (0U)
55021 /*! RL0
55022  *  0b0..Unlocked.
55023  *  0b1..Key, Offset and Attribute registers are locked.
55024  */
55025 #define IEE_GCFG_RL0(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL0_SHIFT)) & IEE_GCFG_RL0_MASK)
55026 
55027 #define IEE_GCFG_RL1_MASK                        (0x2U)
55028 #define IEE_GCFG_RL1_SHIFT                       (1U)
55029 /*! RL1
55030  *  0b0..Unlocked.
55031  *  0b1..Key, Offset and Attribute registers are locked.
55032  */
55033 #define IEE_GCFG_RL1(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL1_SHIFT)) & IEE_GCFG_RL1_MASK)
55034 
55035 #define IEE_GCFG_RL2_MASK                        (0x4U)
55036 #define IEE_GCFG_RL2_SHIFT                       (2U)
55037 /*! RL2
55038  *  0b0..Unlocked.
55039  *  0b1..Key, Offset and Attribute registers are locked.
55040  */
55041 #define IEE_GCFG_RL2(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL2_SHIFT)) & IEE_GCFG_RL2_MASK)
55042 
55043 #define IEE_GCFG_RL3_MASK                        (0x8U)
55044 #define IEE_GCFG_RL3_SHIFT                       (3U)
55045 /*! RL3
55046  *  0b0..Unlocked.
55047  *  0b1..Key, Offset and Attribute registers are locked.
55048  */
55049 #define IEE_GCFG_RL3(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL3_SHIFT)) & IEE_GCFG_RL3_MASK)
55050 
55051 #define IEE_GCFG_RL4_MASK                        (0x10U)
55052 #define IEE_GCFG_RL4_SHIFT                       (4U)
55053 /*! RL4
55054  *  0b0..Unlocked.
55055  *  0b1..Key, Offset and Attribute registers are locked.
55056  */
55057 #define IEE_GCFG_RL4(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL4_SHIFT)) & IEE_GCFG_RL4_MASK)
55058 
55059 #define IEE_GCFG_RL5_MASK                        (0x20U)
55060 #define IEE_GCFG_RL5_SHIFT                       (5U)
55061 /*! RL5
55062  *  0b0..Unlocked.
55063  *  0b1..Key, Offset and Attribute registers are locked.
55064  */
55065 #define IEE_GCFG_RL5(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL5_SHIFT)) & IEE_GCFG_RL5_MASK)
55066 
55067 #define IEE_GCFG_RL6_MASK                        (0x40U)
55068 #define IEE_GCFG_RL6_SHIFT                       (6U)
55069 /*! RL6
55070  *  0b0..Unlocked.
55071  *  0b1..Key, Offset and Attribute registers are locked.
55072  */
55073 #define IEE_GCFG_RL6(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL6_SHIFT)) & IEE_GCFG_RL6_MASK)
55074 
55075 #define IEE_GCFG_RL7_MASK                        (0x80U)
55076 #define IEE_GCFG_RL7_SHIFT                       (7U)
55077 /*! RL7
55078  *  0b0..Unlocked.
55079  *  0b1..Key, Offset and Attribute registers are locked.
55080  */
55081 #define IEE_GCFG_RL7(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL7_SHIFT)) & IEE_GCFG_RL7_MASK)
55082 
55083 #define IEE_GCFG_TME_MASK                        (0x10000U)
55084 #define IEE_GCFG_TME_SHIFT                       (16U)
55085 /*! TME
55086  *  0b0..Disabled.
55087  *  0b1..Enabled.
55088  */
55089 #define IEE_GCFG_TME(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TME_SHIFT)) & IEE_GCFG_TME_MASK)
55090 
55091 #define IEE_GCFG_TMD_MASK                        (0x20000U)
55092 #define IEE_GCFG_TMD_SHIFT                       (17U)
55093 /*! TMD
55094  *  0b0..Test mode is usable.
55095  *  0b1..Test mode is disabled.
55096  */
55097 #define IEE_GCFG_TMD(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TMD_SHIFT)) & IEE_GCFG_TMD_MASK)
55098 
55099 #define IEE_GCFG_KEY_RD_DIS_MASK                 (0x2000000U)
55100 #define IEE_GCFG_KEY_RD_DIS_SHIFT                (25U)
55101 /*! KEY_RD_DIS
55102  *  0b0..Key read enabled. Reading the key registers is allowed.
55103  *  0b1..Key read disabled. Reading the key registers is disabled.
55104  */
55105 #define IEE_GCFG_KEY_RD_DIS(x)                   (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_KEY_RD_DIS_SHIFT)) & IEE_GCFG_KEY_RD_DIS_MASK)
55106 
55107 #define IEE_GCFG_MON_EN_MASK                     (0x10000000U)
55108 #define IEE_GCFG_MON_EN_SHIFT                    (28U)
55109 /*! MON_EN
55110  *  0b0..Performance monitoring disabled. Writing of the performance counter registers is enabled.
55111  *  0b1..Performance monitoring enabled. Writing of the performance counter registers is disabled.
55112  */
55113 #define IEE_GCFG_MON_EN(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_MON_EN_SHIFT)) & IEE_GCFG_MON_EN_MASK)
55114 
55115 #define IEE_GCFG_CLR_MON_MASK                    (0x20000000U)
55116 #define IEE_GCFG_CLR_MON_SHIFT                   (29U)
55117 /*! CLR_MON
55118  *  0b0..Do not reset.
55119  *  0b1..Reset performance counters.
55120  */
55121 #define IEE_GCFG_CLR_MON(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_CLR_MON_SHIFT)) & IEE_GCFG_CLR_MON_MASK)
55122 
55123 #define IEE_GCFG_RST_MASK                        (0x80000000U)
55124 #define IEE_GCFG_RST_SHIFT                       (31U)
55125 /*! RST
55126  *  0b0..Do Not Reset.
55127  *  0b1..Reset IEE.
55128  */
55129 #define IEE_GCFG_RST(x)                          (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RST_SHIFT)) & IEE_GCFG_RST_MASK)
55130 /*! @} */
55131 
55132 /*! @name STA - IEE Status */
55133 /*! @{ */
55134 
55135 #define IEE_STA_DSR_MASK                         (0x1U)
55136 #define IEE_STA_DSR_SHIFT                        (0U)
55137 /*! DSR
55138  *  0b0..No seed request present
55139  *  0b1..Seed request present
55140  */
55141 #define IEE_STA_DSR(x)                           (((uint32_t)(((uint32_t)(x)) << IEE_STA_DSR_SHIFT)) & IEE_STA_DSR_MASK)
55142 
55143 #define IEE_STA_AFD_MASK                         (0x10U)
55144 #define IEE_STA_AFD_SHIFT                        (4U)
55145 /*! AFD
55146  *  0b0..No fault detected
55147  *  0b1..Fault detected
55148  */
55149 #define IEE_STA_AFD(x)                           (((uint32_t)(((uint32_t)(x)) << IEE_STA_AFD_SHIFT)) & IEE_STA_AFD_MASK)
55150 /*! @} */
55151 
55152 /*! @name TSTMD - IEE Test Mode Register */
55153 /*! @{ */
55154 
55155 #define IEE_TSTMD_TMRDY_MASK                     (0x1U)
55156 #define IEE_TSTMD_TMRDY_SHIFT                    (0U)
55157 /*! TMRDY
55158  *  0b0..Not Ready.
55159  *  0b1..Ready.
55160  */
55161 #define IEE_TSTMD_TMRDY(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMRDY_SHIFT)) & IEE_TSTMD_TMRDY_MASK)
55162 
55163 #define IEE_TSTMD_TMR_MASK                       (0x2U)
55164 #define IEE_TSTMD_TMR_SHIFT                      (1U)
55165 /*! TMR
55166  *  0b0..Not running. May be written if IEE_GCFG[TME] = 1
55167  *  0b1..Run AES Test until TMDONE is indicated.
55168  */
55169 #define IEE_TSTMD_TMR(x)                         (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMR_SHIFT)) & IEE_TSTMD_TMR_MASK)
55170 
55171 #define IEE_TSTMD_TMENCR_MASK                    (0x4U)
55172 #define IEE_TSTMD_TMENCR_SHIFT                   (2U)
55173 /*! TMENCR
55174  *  0b0..AES Test mode will do decryption.
55175  *  0b1..AES Test mode will do encryption.
55176  */
55177 #define IEE_TSTMD_TMENCR(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMENCR_SHIFT)) & IEE_TSTMD_TMENCR_MASK)
55178 
55179 #define IEE_TSTMD_TMCONT_MASK                    (0x8U)
55180 #define IEE_TSTMD_TMCONT_SHIFT                   (3U)
55181 /*! TMCONT
55182  *  0b0..Do not continue. This is the last block of data for AES.
55183  *  0b1..Continue. Do not initialize AES after this block.
55184  */
55185 #define IEE_TSTMD_TMCONT(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMCONT_SHIFT)) & IEE_TSTMD_TMCONT_MASK)
55186 
55187 #define IEE_TSTMD_TMDONE_MASK                    (0x10U)
55188 #define IEE_TSTMD_TMDONE_SHIFT                   (4U)
55189 /*! TMDONE
55190  *  0b0..Not Done.
55191  *  0b1..Test Done.
55192  */
55193 #define IEE_TSTMD_TMDONE(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMDONE_SHIFT)) & IEE_TSTMD_TMDONE_MASK)
55194 
55195 #define IEE_TSTMD_TMLEN_MASK                     (0xF00U)
55196 #define IEE_TSTMD_TMLEN_SHIFT                    (8U)
55197 #define IEE_TSTMD_TMLEN(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMLEN_SHIFT)) & IEE_TSTMD_TMLEN_MASK)
55198 /*! @} */
55199 
55200 /*! @name DPAMS - AES Mask Generation Seed */
55201 /*! @{ */
55202 
55203 #define IEE_DPAMS_DPAMS_MASK                     (0xFFFFFFFFU)
55204 #define IEE_DPAMS_DPAMS_SHIFT                    (0U)
55205 #define IEE_DPAMS_DPAMS(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_DPAMS_DPAMS_SHIFT)) & IEE_DPAMS_DPAMS_MASK)
55206 /*! @} */
55207 
55208 /*! @name PC_S_LT - Performance Counter, AES Slave Latency Threshold Value */
55209 /*! @{ */
55210 
55211 #define IEE_PC_S_LT_SW_LT_MASK                   (0xFFFFU)
55212 #define IEE_PC_S_LT_SW_LT_SHIFT                  (0U)
55213 #define IEE_PC_S_LT_SW_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SW_LT_SHIFT)) & IEE_PC_S_LT_SW_LT_MASK)
55214 
55215 #define IEE_PC_S_LT_SR_LT_MASK                   (0xFFFF0000U)
55216 #define IEE_PC_S_LT_SR_LT_SHIFT                  (16U)
55217 #define IEE_PC_S_LT_SR_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SR_LT_SHIFT)) & IEE_PC_S_LT_SR_LT_MASK)
55218 /*! @} */
55219 
55220 /*! @name PC_M_LT - Performance Counter, AES Master Latency Threshold */
55221 /*! @{ */
55222 
55223 #define IEE_PC_M_LT_MW_LT_MASK                   (0xFFFU)
55224 #define IEE_PC_M_LT_MW_LT_SHIFT                  (0U)
55225 #define IEE_PC_M_LT_MW_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MW_LT_SHIFT)) & IEE_PC_M_LT_MW_LT_MASK)
55226 
55227 #define IEE_PC_M_LT_MR_LT_MASK                   (0xFFF0000U)
55228 #define IEE_PC_M_LT_MR_LT_SHIFT                  (16U)
55229 #define IEE_PC_M_LT_MR_LT(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MR_LT_SHIFT)) & IEE_PC_M_LT_MR_LT_MASK)
55230 /*! @} */
55231 
55232 /*! @name PC_BLK_ENC - Performance Counter, Number of AES Block Encryptions */
55233 /*! @{ */
55234 
55235 #define IEE_PC_BLK_ENC_BLK_ENC_MASK              (0xFFFFFFFFU)
55236 #define IEE_PC_BLK_ENC_BLK_ENC_SHIFT             (0U)
55237 #define IEE_PC_BLK_ENC_BLK_ENC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_ENC_BLK_ENC_SHIFT)) & IEE_PC_BLK_ENC_BLK_ENC_MASK)
55238 /*! @} */
55239 
55240 /*! @name PC_BLK_DEC - Performance Counter, Number of AES Block Decryptions */
55241 /*! @{ */
55242 
55243 #define IEE_PC_BLK_DEC_BLK_DEC_MASK              (0xFFFFFFFFU)
55244 #define IEE_PC_BLK_DEC_BLK_DEC_SHIFT             (0U)
55245 #define IEE_PC_BLK_DEC_BLK_DEC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_DEC_BLK_DEC_SHIFT)) & IEE_PC_BLK_DEC_BLK_DEC_MASK)
55246 /*! @} */
55247 
55248 /*! @name PC_SR_TRANS - Performance Counter, Number of AXI Slave Read Transactions */
55249 /*! @{ */
55250 
55251 #define IEE_PC_SR_TRANS_SR_TRANS_MASK            (0xFFFFFFFFU)
55252 #define IEE_PC_SR_TRANS_SR_TRANS_SHIFT           (0U)
55253 #define IEE_PC_SR_TRANS_SR_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TRANS_SR_TRANS_SHIFT)) & IEE_PC_SR_TRANS_SR_TRANS_MASK)
55254 /*! @} */
55255 
55256 /*! @name PC_SW_TRANS - Performance Counter, Number of AXI Slave Write Transactions */
55257 /*! @{ */
55258 
55259 #define IEE_PC_SW_TRANS_SW_TRANS_MASK            (0xFFFFFFFFU)
55260 #define IEE_PC_SW_TRANS_SW_TRANS_SHIFT           (0U)
55261 #define IEE_PC_SW_TRANS_SW_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TRANS_SW_TRANS_SHIFT)) & IEE_PC_SW_TRANS_SW_TRANS_MASK)
55262 /*! @} */
55263 
55264 /*! @name PC_MR_TRANS - Performance Counter, Number of AXI Master Read Transactions */
55265 /*! @{ */
55266 
55267 #define IEE_PC_MR_TRANS_MR_TRANS_MASK            (0xFFFFFFFFU)
55268 #define IEE_PC_MR_TRANS_MR_TRANS_SHIFT           (0U)
55269 #define IEE_PC_MR_TRANS_MR_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TRANS_MR_TRANS_SHIFT)) & IEE_PC_MR_TRANS_MR_TRANS_MASK)
55270 /*! @} */
55271 
55272 /*! @name PC_MW_TRANS - Performance Counter, Number of AXI Master Write Transactions */
55273 /*! @{ */
55274 
55275 #define IEE_PC_MW_TRANS_MW_TRANS_MASK            (0xFFFFFFFFU)
55276 #define IEE_PC_MW_TRANS_MW_TRANS_SHIFT           (0U)
55277 #define IEE_PC_MW_TRANS_MW_TRANS(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TRANS_MW_TRANS_SHIFT)) & IEE_PC_MW_TRANS_MW_TRANS_MASK)
55278 /*! @} */
55279 
55280 /*! @name PC_M_MBR - Performance Counter, Number of AXI Master Merge Buffer Read Transactions */
55281 /*! @{ */
55282 
55283 #define IEE_PC_M_MBR_M_MBR_MASK                  (0xFFFFFFFFU)
55284 #define IEE_PC_M_MBR_M_MBR_SHIFT                 (0U)
55285 #define IEE_PC_M_MBR_M_MBR(x)                    (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_MBR_M_MBR_SHIFT)) & IEE_PC_M_MBR_M_MBR_MASK)
55286 /*! @} */
55287 
55288 /*! @name PC_SR_TBC_U - Performance Counter, Upper Slave Read Transactions Byte Count */
55289 /*! @{ */
55290 
55291 #define IEE_PC_SR_TBC_U_SR_TBC_MASK              (0xFFFFU)
55292 #define IEE_PC_SR_TBC_U_SR_TBC_SHIFT             (0U)
55293 #define IEE_PC_SR_TBC_U_SR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_U_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_U_SR_TBC_MASK)
55294 /*! @} */
55295 
55296 /*! @name PC_SR_TBC_L - Performance Counter, Lower Slave Read Transactions Byte Count */
55297 /*! @{ */
55298 
55299 #define IEE_PC_SR_TBC_L_SR_TBC_MASK              (0xFFFFFFFFU)
55300 #define IEE_PC_SR_TBC_L_SR_TBC_SHIFT             (0U)
55301 #define IEE_PC_SR_TBC_L_SR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_L_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_L_SR_TBC_MASK)
55302 /*! @} */
55303 
55304 /*! @name PC_SW_TBC_U - Performance Counter, Upper Slave Write Transactions Byte Count */
55305 /*! @{ */
55306 
55307 #define IEE_PC_SW_TBC_U_SW_TBC_MASK              (0xFFFFU)
55308 #define IEE_PC_SW_TBC_U_SW_TBC_SHIFT             (0U)
55309 #define IEE_PC_SW_TBC_U_SW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_U_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_U_SW_TBC_MASK)
55310 /*! @} */
55311 
55312 /*! @name PC_SW_TBC_L - Performance Counter, Lower Slave Write Transactions Byte Count */
55313 /*! @{ */
55314 
55315 #define IEE_PC_SW_TBC_L_SW_TBC_MASK              (0xFFFFFFFFU)
55316 #define IEE_PC_SW_TBC_L_SW_TBC_SHIFT             (0U)
55317 #define IEE_PC_SW_TBC_L_SW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_L_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_L_SW_TBC_MASK)
55318 /*! @} */
55319 
55320 /*! @name PC_MR_TBC_U - Performance Counter, Upper Master Read Transactions Byte Count */
55321 /*! @{ */
55322 
55323 #define IEE_PC_MR_TBC_U_MR_TBC_MASK              (0xFFFFU)
55324 #define IEE_PC_MR_TBC_U_MR_TBC_SHIFT             (0U)
55325 #define IEE_PC_MR_TBC_U_MR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_U_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_U_MR_TBC_MASK)
55326 /*! @} */
55327 
55328 /*! @name PC_MR_TBC_L - Performance Counter, Lower Master Read Transactions Byte Count */
55329 /*! @{ */
55330 
55331 #define IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK          (0xFU)
55332 #define IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT         (0U)
55333 #define IEE_PC_MR_TBC_L_MR_TBC_LSB(x)            (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK)
55334 
55335 #define IEE_PC_MR_TBC_L_MR_TBC_MASK              (0xFFFFFFF0U)
55336 #define IEE_PC_MR_TBC_L_MR_TBC_SHIFT             (4U)
55337 #define IEE_PC_MR_TBC_L_MR_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_MASK)
55338 /*! @} */
55339 
55340 /*! @name PC_MW_TBC_U - Performance Counter, Upper Master Write Transactions Byte Count */
55341 /*! @{ */
55342 
55343 #define IEE_PC_MW_TBC_U_MW_TBC_MASK              (0xFFFFU)
55344 #define IEE_PC_MW_TBC_U_MW_TBC_SHIFT             (0U)
55345 #define IEE_PC_MW_TBC_U_MW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_U_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_U_MW_TBC_MASK)
55346 /*! @} */
55347 
55348 /*! @name PC_MW_TBC_L - Performance Counter, Lower Master Write Transactions Byte Count */
55349 /*! @{ */
55350 
55351 #define IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK          (0xFU)
55352 #define IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT         (0U)
55353 #define IEE_PC_MW_TBC_L_MW_TBC_LSB(x)            (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK)
55354 
55355 #define IEE_PC_MW_TBC_L_MW_TBC_MASK              (0xFFFFFFF0U)
55356 #define IEE_PC_MW_TBC_L_MW_TBC_SHIFT             (4U)
55357 #define IEE_PC_MW_TBC_L_MW_TBC(x)                (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_MASK)
55358 /*! @} */
55359 
55360 /*! @name PC_SR_TLGTT - Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold */
55361 /*! @{ */
55362 
55363 #define IEE_PC_SR_TLGTT_SR_TLGTT_MASK            (0xFFFFFFFFU)
55364 #define IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT           (0U)
55365 #define IEE_PC_SR_TLGTT_SR_TLGTT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT)) & IEE_PC_SR_TLGTT_SR_TLGTT_MASK)
55366 /*! @} */
55367 
55368 /*! @name PC_SW_TLGTT - Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold */
55369 /*! @{ */
55370 
55371 #define IEE_PC_SW_TLGTT_SW_TLGTT_MASK            (0xFFFFFFFFU)
55372 #define IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT           (0U)
55373 #define IEE_PC_SW_TLGTT_SW_TLGTT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT)) & IEE_PC_SW_TLGTT_SW_TLGTT_MASK)
55374 /*! @} */
55375 
55376 /*! @name PC_MR_TLGTT - Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold */
55377 /*! @{ */
55378 
55379 #define IEE_PC_MR_TLGTT_MR_TLGTT_MASK            (0xFFFFFFFFU)
55380 #define IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT           (0U)
55381 #define IEE_PC_MR_TLGTT_MR_TLGTT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT)) & IEE_PC_MR_TLGTT_MR_TLGTT_MASK)
55382 /*! @} */
55383 
55384 /*! @name PC_MW_TLGTT - Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold */
55385 /*! @{ */
55386 
55387 #define IEE_PC_MW_TLGTT_MW_TGTT_MASK             (0xFFFFFFFFU)
55388 #define IEE_PC_MW_TLGTT_MW_TGTT_SHIFT            (0U)
55389 #define IEE_PC_MW_TLGTT_MW_TGTT(x)               (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLGTT_MW_TGTT_SHIFT)) & IEE_PC_MW_TLGTT_MW_TGTT_MASK)
55390 /*! @} */
55391 
55392 /*! @name PC_SR_TLAT_U - Performance Counter, Upper Slave Read Latency Count */
55393 /*! @{ */
55394 
55395 #define IEE_PC_SR_TLAT_U_SR_TLAT_MASK            (0xFFFFU)
55396 #define IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT           (0U)
55397 #define IEE_PC_SR_TLAT_U_SR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_U_SR_TLAT_MASK)
55398 /*! @} */
55399 
55400 /*! @name PC_SR_TLAT_L - Performance Counter, Lower Slave Read Latency Count */
55401 /*! @{ */
55402 
55403 #define IEE_PC_SR_TLAT_L_SR_TLAT_MASK            (0xFFFFFFFFU)
55404 #define IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT           (0U)
55405 #define IEE_PC_SR_TLAT_L_SR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_L_SR_TLAT_MASK)
55406 /*! @} */
55407 
55408 /*! @name PC_SW_TLAT_U - Performance Counter, Upper Slave Write Latency Count */
55409 /*! @{ */
55410 
55411 #define IEE_PC_SW_TLAT_U_SW_TLAT_MASK            (0xFFFFU)
55412 #define IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT           (0U)
55413 #define IEE_PC_SW_TLAT_U_SW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_U_SW_TLAT_MASK)
55414 /*! @} */
55415 
55416 /*! @name PC_SW_TLAT_L - Performance Counter, Lower Slave Write Latency Count */
55417 /*! @{ */
55418 
55419 #define IEE_PC_SW_TLAT_L_SW_TLAT_MASK            (0xFFFFFFFFU)
55420 #define IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT           (0U)
55421 #define IEE_PC_SW_TLAT_L_SW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_L_SW_TLAT_MASK)
55422 /*! @} */
55423 
55424 /*! @name PC_MR_TLAT_U - Performance Counter, Upper Master Read Latency Count */
55425 /*! @{ */
55426 
55427 #define IEE_PC_MR_TLAT_U_MR_TLAT_MASK            (0xFFFFU)
55428 #define IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT           (0U)
55429 #define IEE_PC_MR_TLAT_U_MR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_U_MR_TLAT_MASK)
55430 /*! @} */
55431 
55432 /*! @name PC_MR_TLAT_L - Performance Counter, Lower Master Read Latency Count */
55433 /*! @{ */
55434 
55435 #define IEE_PC_MR_TLAT_L_MR_TLAT_MASK            (0xFFFFFFFFU)
55436 #define IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT           (0U)
55437 #define IEE_PC_MR_TLAT_L_MR_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_L_MR_TLAT_MASK)
55438 /*! @} */
55439 
55440 /*! @name PC_MW_TLAT_U - Performance Counter, Upper Master Write Latency Count */
55441 /*! @{ */
55442 
55443 #define IEE_PC_MW_TLAT_U_MW_TLAT_MASK            (0xFFFFU)
55444 #define IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT           (0U)
55445 #define IEE_PC_MW_TLAT_U_MW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_U_MW_TLAT_MASK)
55446 /*! @} */
55447 
55448 /*! @name PC_MW_TLAT_L - Performance Counter, Lower Master Write Latency Count */
55449 /*! @{ */
55450 
55451 #define IEE_PC_MW_TLAT_L_MW_TLAT_MASK            (0xFFFFFFFFU)
55452 #define IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT           (0U)
55453 #define IEE_PC_MW_TLAT_L_MW_TLAT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_L_MW_TLAT_MASK)
55454 /*! @} */
55455 
55456 /*! @name PC_SR_TNRT_U - Performance Counter, Upper Slave Read Total Non-Responding Time */
55457 /*! @{ */
55458 
55459 #define IEE_PC_SR_TNRT_U_SR_TNRT_MASK            (0xFFFFU)
55460 #define IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT           (0U)
55461 #define IEE_PC_SR_TNRT_U_SR_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_U_SR_TNRT_MASK)
55462 /*! @} */
55463 
55464 /*! @name PC_SR_TNRT_L - Performance Counter, Lower Slave Read Total Non-Responding Time */
55465 /*! @{ */
55466 
55467 #define IEE_PC_SR_TNRT_L_SR_TNRT_MASK            (0xFFFFFFFFU)
55468 #define IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT           (0U)
55469 #define IEE_PC_SR_TNRT_L_SR_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_L_SR_TNRT_MASK)
55470 /*! @} */
55471 
55472 /*! @name PC_SW_TNRT_U - Performance Counter, Upper Slave Write Total Non-Responding Time */
55473 /*! @{ */
55474 
55475 #define IEE_PC_SW_TNRT_U_SW_TNRT_MASK            (0xFFFFU)
55476 #define IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT           (0U)
55477 #define IEE_PC_SW_TNRT_U_SW_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_U_SW_TNRT_MASK)
55478 /*! @} */
55479 
55480 /*! @name PC_SW_TNRT_L - Performance Counter, Lower Slave Write Total Non-Responding Time */
55481 /*! @{ */
55482 
55483 #define IEE_PC_SW_TNRT_L_SW_TNRT_MASK            (0xFFFFFFFFU)
55484 #define IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT           (0U)
55485 #define IEE_PC_SW_TNRT_L_SW_TNRT(x)              (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_L_SW_TNRT_MASK)
55486 /*! @} */
55487 
55488 /*! @name VIDR1 - IEE Version ID Register 1 */
55489 /*! @{ */
55490 
55491 #define IEE_VIDR1_MIN_REV_MASK                   (0xFFU)
55492 #define IEE_VIDR1_MIN_REV_SHIFT                  (0U)
55493 #define IEE_VIDR1_MIN_REV(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MIN_REV_SHIFT)) & IEE_VIDR1_MIN_REV_MASK)
55494 
55495 #define IEE_VIDR1_MAJ_REV_MASK                   (0xFF00U)
55496 #define IEE_VIDR1_MAJ_REV_SHIFT                  (8U)
55497 #define IEE_VIDR1_MAJ_REV(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MAJ_REV_SHIFT)) & IEE_VIDR1_MAJ_REV_MASK)
55498 
55499 #define IEE_VIDR1_IP_ID_MASK                     (0xFFFF0000U)
55500 #define IEE_VIDR1_IP_ID_SHIFT                    (16U)
55501 #define IEE_VIDR1_IP_ID(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_IP_ID_SHIFT)) & IEE_VIDR1_IP_ID_MASK)
55502 /*! @} */
55503 
55504 /*! @name AESVID - IEE AES Version ID Register */
55505 /*! @{ */
55506 
55507 #define IEE_AESVID_AESRN_MASK                    (0xFU)
55508 #define IEE_AESVID_AESRN_SHIFT                   (0U)
55509 #define IEE_AESVID_AESRN(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESRN_SHIFT)) & IEE_AESVID_AESRN_MASK)
55510 
55511 #define IEE_AESVID_AESVID_MASK                   (0xF0U)
55512 #define IEE_AESVID_AESVID_SHIFT                  (4U)
55513 #define IEE_AESVID_AESVID(x)                     (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESVID_SHIFT)) & IEE_AESVID_AESVID_MASK)
55514 /*! @} */
55515 
55516 /*! @name REGATTR - IEE Region 0 Attribute Register...IEE Region 7 Attribute Register. */
55517 /*! @{ */
55518 
55519 #define IEE_REGATTR_KS_MASK                      (0x1U)
55520 #define IEE_REGATTR_KS_SHIFT                     (0U)
55521 /*! KS
55522  *  0b0..128 bits (CTR), 256 bits (XTS).
55523  *  0b1..256 bits (CTR), 512 bits (XTS).
55524  */
55525 #define IEE_REGATTR_KS(x)                        (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_KS_SHIFT)) & IEE_REGATTR_KS_MASK)
55526 
55527 #define IEE_REGATTR_MD_MASK                      (0x70U)
55528 #define IEE_REGATTR_MD_SHIFT                     (4U)
55529 /*! MD
55530  *  0b000..None (AXI error if accessed)
55531  *  0b001..XTS
55532  *  0b010..CTR w/ address binding
55533  *  0b011..CTR w/o address binding
55534  *  0b100..CTR keystream only
55535  *  0b101..Undefined, AXI error if used
55536  *  0b110..Undefined, AXI error if used
55537  *  0b111..Undefined, AXI error if used
55538  */
55539 #define IEE_REGATTR_MD(x)                        (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_MD_SHIFT)) & IEE_REGATTR_MD_MASK)
55540 
55541 #define IEE_REGATTR_BYP_MASK                     (0x80U)
55542 #define IEE_REGATTR_BYP_SHIFT                    (7U)
55543 /*! BYP
55544  *  0b0..use MD field
55545  *  0b1..Bypass AES, no encrypt/decrypt
55546  */
55547 #define IEE_REGATTR_BYP(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_BYP_SHIFT)) & IEE_REGATTR_BYP_MASK)
55548 /*! @} */
55549 
55550 /* The count of IEE_REGATTR */
55551 #define IEE_REGATTR_COUNT                        (8U)
55552 
55553 /*! @name REGPO - IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register */
55554 /*! @{ */
55555 
55556 #define IEE_REGPO_PGOFF_MASK                     (0xFFFFFFU)
55557 #define IEE_REGPO_PGOFF_SHIFT                    (0U)
55558 #define IEE_REGPO_PGOFF(x)                       (((uint32_t)(((uint32_t)(x)) << IEE_REGPO_PGOFF_SHIFT)) & IEE_REGPO_PGOFF_MASK)
55559 /*! @} */
55560 
55561 /* The count of IEE_REGPO */
55562 #define IEE_REGPO_COUNT                          (8U)
55563 
55564 /*! @name REGKEY1 - IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register */
55565 /*! @{ */
55566 
55567 #define IEE_REGKEY1_KEY1_MASK                    (0xFFFFFFFFU)
55568 #define IEE_REGKEY1_KEY1_SHIFT                   (0U)
55569 #define IEE_REGKEY1_KEY1(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY1_KEY1_SHIFT)) & IEE_REGKEY1_KEY1_MASK)
55570 /*! @} */
55571 
55572 /* The count of IEE_REGKEY1 */
55573 #define IEE_REGKEY1_COUNT                        (8U)
55574 
55575 /* The count of IEE_REGKEY1 */
55576 #define IEE_REGKEY1_COUNT2                       (8U)
55577 
55578 /*! @name REGKEY2 - IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register */
55579 /*! @{ */
55580 
55581 #define IEE_REGKEY2_KEY2_MASK                    (0xFFFFFFFFU)
55582 #define IEE_REGKEY2_KEY2_SHIFT                   (0U)
55583 #define IEE_REGKEY2_KEY2(x)                      (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY2_KEY2_SHIFT)) & IEE_REGKEY2_KEY2_MASK)
55584 /*! @} */
55585 
55586 /* The count of IEE_REGKEY2 */
55587 #define IEE_REGKEY2_COUNT                        (8U)
55588 
55589 /* The count of IEE_REGKEY2 */
55590 #define IEE_REGKEY2_COUNT2                       (8U)
55591 
55592 /*! @name AES_TST_DB - IEE AES Test Mode Data Buffer */
55593 /*! @{ */
55594 
55595 #define IEE_AES_TST_DB_AES_TST_DB0_MASK          (0xFFFFFFFFU)
55596 #define IEE_AES_TST_DB_AES_TST_DB0_SHIFT         (0U)
55597 #define IEE_AES_TST_DB_AES_TST_DB0(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB0_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB0_MASK)
55598 
55599 #define IEE_AES_TST_DB_AES_TST_DB1_MASK          (0xFFFFFFFFU)
55600 #define IEE_AES_TST_DB_AES_TST_DB1_SHIFT         (0U)
55601 #define IEE_AES_TST_DB_AES_TST_DB1(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB1_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB1_MASK)
55602 
55603 #define IEE_AES_TST_DB_AES_TST_DB2_MASK          (0xFFFFFFFFU)
55604 #define IEE_AES_TST_DB_AES_TST_DB2_SHIFT         (0U)
55605 #define IEE_AES_TST_DB_AES_TST_DB2(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB2_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB2_MASK)
55606 
55607 #define IEE_AES_TST_DB_AES_TST_DB3_MASK          (0xFFFFFFFFU)
55608 #define IEE_AES_TST_DB_AES_TST_DB3_SHIFT         (0U)
55609 #define IEE_AES_TST_DB_AES_TST_DB3(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB3_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB3_MASK)
55610 
55611 #define IEE_AES_TST_DB_AES_TST_DB4_MASK          (0xFFFFFFFFU)
55612 #define IEE_AES_TST_DB_AES_TST_DB4_SHIFT         (0U)
55613 #define IEE_AES_TST_DB_AES_TST_DB4(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB4_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB4_MASK)
55614 
55615 #define IEE_AES_TST_DB_AES_TST_DB5_MASK          (0xFFFFFFFFU)
55616 #define IEE_AES_TST_DB_AES_TST_DB5_SHIFT         (0U)
55617 #define IEE_AES_TST_DB_AES_TST_DB5(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB5_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB5_MASK)
55618 
55619 #define IEE_AES_TST_DB_AES_TST_DB6_MASK          (0xFFFFFFFFU)
55620 #define IEE_AES_TST_DB_AES_TST_DB6_SHIFT         (0U)
55621 #define IEE_AES_TST_DB_AES_TST_DB6(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB6_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB6_MASK)
55622 
55623 #define IEE_AES_TST_DB_AES_TST_DB7_MASK          (0xFFFFFFFFU)
55624 #define IEE_AES_TST_DB_AES_TST_DB7_SHIFT         (0U)
55625 #define IEE_AES_TST_DB_AES_TST_DB7(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB7_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB7_MASK)
55626 
55627 #define IEE_AES_TST_DB_AES_TST_DB8_MASK          (0xFFFFFFFFU)
55628 #define IEE_AES_TST_DB_AES_TST_DB8_SHIFT         (0U)
55629 #define IEE_AES_TST_DB_AES_TST_DB8(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB8_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB8_MASK)
55630 
55631 #define IEE_AES_TST_DB_AES_TST_DB9_MASK          (0xFFFFFFFFU)
55632 #define IEE_AES_TST_DB_AES_TST_DB9_SHIFT         (0U)
55633 #define IEE_AES_TST_DB_AES_TST_DB9(x)            (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB9_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB9_MASK)
55634 
55635 #define IEE_AES_TST_DB_AES_TST_DB10_MASK         (0xFFFFFFFFU)
55636 #define IEE_AES_TST_DB_AES_TST_DB10_SHIFT        (0U)
55637 #define IEE_AES_TST_DB_AES_TST_DB10(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB10_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB10_MASK)
55638 
55639 #define IEE_AES_TST_DB_AES_TST_DB11_MASK         (0xFFFFFFFFU)
55640 #define IEE_AES_TST_DB_AES_TST_DB11_SHIFT        (0U)
55641 #define IEE_AES_TST_DB_AES_TST_DB11(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB11_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB11_MASK)
55642 
55643 #define IEE_AES_TST_DB_AES_TST_DB12_MASK         (0xFFFFFFFFU)
55644 #define IEE_AES_TST_DB_AES_TST_DB12_SHIFT        (0U)
55645 #define IEE_AES_TST_DB_AES_TST_DB12(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB12_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB12_MASK)
55646 
55647 #define IEE_AES_TST_DB_AES_TST_DB13_MASK         (0xFFFFFFFFU)
55648 #define IEE_AES_TST_DB_AES_TST_DB13_SHIFT        (0U)
55649 #define IEE_AES_TST_DB_AES_TST_DB13(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB13_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB13_MASK)
55650 
55651 #define IEE_AES_TST_DB_AES_TST_DB14_MASK         (0xFFFFFFFFU)
55652 #define IEE_AES_TST_DB_AES_TST_DB14_SHIFT        (0U)
55653 #define IEE_AES_TST_DB_AES_TST_DB14(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB14_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB14_MASK)
55654 
55655 #define IEE_AES_TST_DB_AES_TST_DB15_MASK         (0xFFFFFFFFU)
55656 #define IEE_AES_TST_DB_AES_TST_DB15_SHIFT        (0U)
55657 #define IEE_AES_TST_DB_AES_TST_DB15(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB15_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB15_MASK)
55658 
55659 #define IEE_AES_TST_DB_AES_TST_DB16_MASK         (0xFFFFFFFFU)
55660 #define IEE_AES_TST_DB_AES_TST_DB16_SHIFT        (0U)
55661 #define IEE_AES_TST_DB_AES_TST_DB16(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB16_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB16_MASK)
55662 
55663 #define IEE_AES_TST_DB_AES_TST_DB17_MASK         (0xFFFFFFFFU)
55664 #define IEE_AES_TST_DB_AES_TST_DB17_SHIFT        (0U)
55665 #define IEE_AES_TST_DB_AES_TST_DB17(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB17_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB17_MASK)
55666 
55667 #define IEE_AES_TST_DB_AES_TST_DB18_MASK         (0xFFFFFFFFU)
55668 #define IEE_AES_TST_DB_AES_TST_DB18_SHIFT        (0U)
55669 #define IEE_AES_TST_DB_AES_TST_DB18(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB18_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB18_MASK)
55670 
55671 #define IEE_AES_TST_DB_AES_TST_DB19_MASK         (0xFFFFFFFFU)
55672 #define IEE_AES_TST_DB_AES_TST_DB19_SHIFT        (0U)
55673 #define IEE_AES_TST_DB_AES_TST_DB19(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB19_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB19_MASK)
55674 
55675 #define IEE_AES_TST_DB_AES_TST_DB20_MASK         (0xFFFFFFFFU)
55676 #define IEE_AES_TST_DB_AES_TST_DB20_SHIFT        (0U)
55677 #define IEE_AES_TST_DB_AES_TST_DB20(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB20_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB20_MASK)
55678 
55679 #define IEE_AES_TST_DB_AES_TST_DB21_MASK         (0xFFFFFFFFU)
55680 #define IEE_AES_TST_DB_AES_TST_DB21_SHIFT        (0U)
55681 #define IEE_AES_TST_DB_AES_TST_DB21(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB21_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB21_MASK)
55682 
55683 #define IEE_AES_TST_DB_AES_TST_DB22_MASK         (0xFFFFFFFFU)
55684 #define IEE_AES_TST_DB_AES_TST_DB22_SHIFT        (0U)
55685 #define IEE_AES_TST_DB_AES_TST_DB22(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB22_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB22_MASK)
55686 
55687 #define IEE_AES_TST_DB_AES_TST_DB23_MASK         (0xFFFFFFFFU)
55688 #define IEE_AES_TST_DB_AES_TST_DB23_SHIFT        (0U)
55689 #define IEE_AES_TST_DB_AES_TST_DB23(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB23_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB23_MASK)
55690 
55691 #define IEE_AES_TST_DB_AES_TST_DB24_MASK         (0xFFFFFFFFU)
55692 #define IEE_AES_TST_DB_AES_TST_DB24_SHIFT        (0U)
55693 #define IEE_AES_TST_DB_AES_TST_DB24(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB24_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB24_MASK)
55694 
55695 #define IEE_AES_TST_DB_AES_TST_DB25_MASK         (0xFFFFFFFFU)
55696 #define IEE_AES_TST_DB_AES_TST_DB25_SHIFT        (0U)
55697 #define IEE_AES_TST_DB_AES_TST_DB25(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB25_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB25_MASK)
55698 
55699 #define IEE_AES_TST_DB_AES_TST_DB26_MASK         (0xFFFFFFFFU)
55700 #define IEE_AES_TST_DB_AES_TST_DB26_SHIFT        (0U)
55701 #define IEE_AES_TST_DB_AES_TST_DB26(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB26_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB26_MASK)
55702 
55703 #define IEE_AES_TST_DB_AES_TST_DB27_MASK         (0xFFFFFFFFU)
55704 #define IEE_AES_TST_DB_AES_TST_DB27_SHIFT        (0U)
55705 #define IEE_AES_TST_DB_AES_TST_DB27(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB27_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB27_MASK)
55706 
55707 #define IEE_AES_TST_DB_AES_TST_DB28_MASK         (0xFFFFFFFFU)
55708 #define IEE_AES_TST_DB_AES_TST_DB28_SHIFT        (0U)
55709 #define IEE_AES_TST_DB_AES_TST_DB28(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB28_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB28_MASK)
55710 
55711 #define IEE_AES_TST_DB_AES_TST_DB29_MASK         (0xFFFFFFFFU)
55712 #define IEE_AES_TST_DB_AES_TST_DB29_SHIFT        (0U)
55713 #define IEE_AES_TST_DB_AES_TST_DB29(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB29_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB29_MASK)
55714 
55715 #define IEE_AES_TST_DB_AES_TST_DB30_MASK         (0xFFFFFFFFU)
55716 #define IEE_AES_TST_DB_AES_TST_DB30_SHIFT        (0U)
55717 #define IEE_AES_TST_DB_AES_TST_DB30(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB30_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB30_MASK)
55718 
55719 #define IEE_AES_TST_DB_AES_TST_DB31_MASK         (0xFFFFFFFFU)
55720 #define IEE_AES_TST_DB_AES_TST_DB31_SHIFT        (0U)
55721 #define IEE_AES_TST_DB_AES_TST_DB31(x)           (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB31_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB31_MASK)
55722 /*! @} */
55723 
55724 /* The count of IEE_AES_TST_DB */
55725 #define IEE_AES_TST_DB_COUNT                     (32U)
55726 
55727 
55728 /*!
55729  * @}
55730  */ /* end of group IEE_Register_Masks */
55731 
55732 
55733 /* IEE - Peripheral instance base addresses */
55734 /** Peripheral IEE__IEE_RT1170 base address */
55735 #define IEE__IEE_RT1170_BASE                     (0x4006C000u)
55736 /** Peripheral IEE__IEE_RT1170 base pointer */
55737 #define IEE__IEE_RT1170                          ((IEE_Type *)IEE__IEE_RT1170_BASE)
55738 /** Array initializer of IEE peripheral base addresses */
55739 #define IEE_BASE_ADDRS                           { IEE__IEE_RT1170_BASE }
55740 /** Array initializer of IEE peripheral base pointers */
55741 #define IEE_BASE_PTRS                            { IEE__IEE_RT1170 }
55742 
55743 /*!
55744  * @}
55745  */ /* end of group IEE_Peripheral_Access_Layer */
55746 
55747 
55748 /* ----------------------------------------------------------------------------
55749    -- IEE_APC Peripheral Access Layer
55750    ---------------------------------------------------------------------------- */
55751 
55752 /*!
55753  * @addtogroup IEE_APC_Peripheral_Access_Layer IEE_APC Peripheral Access Layer
55754  * @{
55755  */
55756 
55757 /** IEE_APC - Register Layout Typedef */
55758 typedef struct {
55759   __IO uint32_t REGION0_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x0 */
55760   __IO uint32_t REGION0_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x4 */
55761   __IO uint32_t REGION0_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x8 */
55762   __IO uint32_t REGION0_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0xC */
55763   __IO uint32_t REGION1_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x10 */
55764   __IO uint32_t REGION1_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x14 */
55765   __IO uint32_t REGION1_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x18 */
55766   __IO uint32_t REGION1_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x1C */
55767   __IO uint32_t REGION2_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x20 */
55768   __IO uint32_t REGION2_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x24 */
55769   __IO uint32_t REGION2_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x28 */
55770   __IO uint32_t REGION2_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x2C */
55771   __IO uint32_t REGION3_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x30 */
55772   __IO uint32_t REGION3_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x34 */
55773   __IO uint32_t REGION3_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x38 */
55774   __IO uint32_t REGION3_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x3C */
55775   __IO uint32_t REGION4_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x40 */
55776   __IO uint32_t REGION4_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x44 */
55777   __IO uint32_t REGION4_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x48 */
55778   __IO uint32_t REGION4_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x4C */
55779   __IO uint32_t REGION5_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x50 */
55780   __IO uint32_t REGION5_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x54 */
55781   __IO uint32_t REGION5_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x58 */
55782   __IO uint32_t REGION5_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x5C */
55783   __IO uint32_t REGION6_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x60 */
55784   __IO uint32_t REGION6_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x64 */
55785   __IO uint32_t REGION6_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x68 */
55786   __IO uint32_t REGION6_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x6C */
55787   __IO uint32_t REGION7_TOP_ADDR;                  /**< End address of IEE region (n), offset: 0x70 */
55788   __IO uint32_t REGION7_BOT_ADDR;                  /**< Start address of IEE region (n), offset: 0x74 */
55789   __IO uint32_t REGION7_RDC_D0;                    /**< Region control of core domain 0 for region (n), offset: 0x78 */
55790   __IO uint32_t REGION7_RDC_D1;                    /**< Region control of core domain 1 for region (n), offset: 0x7C */
55791 } IEE_APC_Type;
55792 
55793 /* ----------------------------------------------------------------------------
55794    -- IEE_APC Register Masks
55795    ---------------------------------------------------------------------------- */
55796 
55797 /*!
55798  * @addtogroup IEE_APC_Register_Masks IEE_APC Register Masks
55799  * @{
55800  */
55801 
55802 /*! @name REGION0_TOP_ADDR - End address of IEE region (n) */
55803 /*! @{ */
55804 
55805 #define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
55806 #define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
55807 /*! TOP_ADDR - End address of IEE region */
55808 #define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK)
55809 /*! @} */
55810 
55811 /*! @name REGION0_BOT_ADDR - Start address of IEE region (n) */
55812 /*! @{ */
55813 
55814 #define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
55815 #define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
55816 /*! BOT_ADDR - Start address of IEE region */
55817 #define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK)
55818 /*! @} */
55819 
55820 /*! @name REGION0_RDC_D0 - Region control of core domain 0 for region (n) */
55821 /*! @{ */
55822 
55823 #define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
55824 #define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
55825 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
55826  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
55827  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
55828  */
55829 #define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK)
55830 
55831 #define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
55832 #define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
55833 /*! RDC_D0_LOCK - Lock bit for bit 0
55834  *  0b0..Bit 0 is unlocked
55835  *  0b1..Bit 0 is locked
55836  */
55837 #define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK)
55838 /*! @} */
55839 
55840 /*! @name REGION0_RDC_D1 - Region control of core domain 1 for region (n) */
55841 /*! @{ */
55842 
55843 #define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
55844 #define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
55845 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
55846  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
55847  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
55848  */
55849 #define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK)
55850 
55851 #define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
55852 #define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
55853 /*! RDC_D1_LOCK - Lock bit for bit 0
55854  *  0b0..Bit 0 is unlocked
55855  *  0b1..Bit 0 is locked
55856  */
55857 #define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK)
55858 /*! @} */
55859 
55860 /*! @name REGION1_TOP_ADDR - End address of IEE region (n) */
55861 /*! @{ */
55862 
55863 #define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
55864 #define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
55865 /*! TOP_ADDR - End address of IEE region */
55866 #define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK)
55867 /*! @} */
55868 
55869 /*! @name REGION1_BOT_ADDR - Start address of IEE region (n) */
55870 /*! @{ */
55871 
55872 #define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
55873 #define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
55874 /*! BOT_ADDR - Start address of IEE region */
55875 #define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK)
55876 /*! @} */
55877 
55878 /*! @name REGION1_RDC_D0 - Region control of core domain 0 for region (n) */
55879 /*! @{ */
55880 
55881 #define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
55882 #define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
55883 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
55884  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
55885  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
55886  */
55887 #define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK)
55888 
55889 #define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
55890 #define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
55891 /*! RDC_D0_LOCK - Lock bit for bit 0
55892  *  0b0..Bit 0 is unlocked
55893  *  0b1..Bit 0 is locked
55894  */
55895 #define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK)
55896 /*! @} */
55897 
55898 /*! @name REGION1_RDC_D1 - Region control of core domain 1 for region (n) */
55899 /*! @{ */
55900 
55901 #define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
55902 #define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
55903 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
55904  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
55905  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
55906  */
55907 #define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK)
55908 
55909 #define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
55910 #define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
55911 /*! RDC_D1_LOCK - Lock bit for bit 0
55912  *  0b0..Bit 0 is unlocked
55913  *  0b1..Bit 0 is locked
55914  */
55915 #define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK)
55916 /*! @} */
55917 
55918 /*! @name REGION2_TOP_ADDR - End address of IEE region (n) */
55919 /*! @{ */
55920 
55921 #define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
55922 #define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
55923 /*! TOP_ADDR - End address of IEE region */
55924 #define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK)
55925 /*! @} */
55926 
55927 /*! @name REGION2_BOT_ADDR - Start address of IEE region (n) */
55928 /*! @{ */
55929 
55930 #define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
55931 #define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
55932 /*! BOT_ADDR - Start address of IEE region */
55933 #define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK)
55934 /*! @} */
55935 
55936 /*! @name REGION2_RDC_D0 - Region control of core domain 0 for region (n) */
55937 /*! @{ */
55938 
55939 #define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
55940 #define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
55941 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
55942  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
55943  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
55944  */
55945 #define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK)
55946 
55947 #define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
55948 #define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
55949 /*! RDC_D0_LOCK - Lock bit for bit 0
55950  *  0b0..Bit 0 is unlocked
55951  *  0b1..Bit 0 is locked
55952  */
55953 #define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK)
55954 /*! @} */
55955 
55956 /*! @name REGION2_RDC_D1 - Region control of core domain 1 for region (n) */
55957 /*! @{ */
55958 
55959 #define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
55960 #define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
55961 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
55962  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
55963  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
55964  */
55965 #define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK)
55966 
55967 #define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
55968 #define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
55969 /*! RDC_D1_LOCK - Lock bit for bit 0
55970  *  0b0..Bit 0 is unlocked
55971  *  0b1..Bit 0 is locked
55972  */
55973 #define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK)
55974 /*! @} */
55975 
55976 /*! @name REGION3_TOP_ADDR - End address of IEE region (n) */
55977 /*! @{ */
55978 
55979 #define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
55980 #define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
55981 /*! TOP_ADDR - End address of IEE region */
55982 #define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK)
55983 /*! @} */
55984 
55985 /*! @name REGION3_BOT_ADDR - Start address of IEE region (n) */
55986 /*! @{ */
55987 
55988 #define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
55989 #define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
55990 /*! BOT_ADDR - Start address of IEE region */
55991 #define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK)
55992 /*! @} */
55993 
55994 /*! @name REGION3_RDC_D0 - Region control of core domain 0 for region (n) */
55995 /*! @{ */
55996 
55997 #define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
55998 #define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
55999 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
56000  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
56001  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
56002  */
56003 #define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK)
56004 
56005 #define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
56006 #define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
56007 /*! RDC_D0_LOCK - Lock bit for bit 0
56008  *  0b0..Bit 0 is unlocked
56009  *  0b1..Bit 0 is locked
56010  */
56011 #define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK)
56012 /*! @} */
56013 
56014 /*! @name REGION3_RDC_D1 - Region control of core domain 1 for region (n) */
56015 /*! @{ */
56016 
56017 #define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
56018 #define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
56019 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
56020  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
56021  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
56022  */
56023 #define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK)
56024 
56025 #define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
56026 #define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
56027 /*! RDC_D1_LOCK - Lock bit for bit 0
56028  *  0b0..Bit 0 is unlocked
56029  *  0b1..Bit 0 is locked
56030  */
56031 #define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK)
56032 /*! @} */
56033 
56034 /*! @name REGION4_TOP_ADDR - End address of IEE region (n) */
56035 /*! @{ */
56036 
56037 #define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
56038 #define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
56039 /*! TOP_ADDR - End address of IEE region */
56040 #define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK)
56041 /*! @} */
56042 
56043 /*! @name REGION4_BOT_ADDR - Start address of IEE region (n) */
56044 /*! @{ */
56045 
56046 #define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
56047 #define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
56048 /*! BOT_ADDR - Start address of IEE region */
56049 #define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK)
56050 /*! @} */
56051 
56052 /*! @name REGION4_RDC_D0 - Region control of core domain 0 for region (n) */
56053 /*! @{ */
56054 
56055 #define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
56056 #define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
56057 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
56058  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
56059  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
56060  */
56061 #define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK)
56062 
56063 #define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
56064 #define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
56065 /*! RDC_D0_LOCK - Lock bit for bit 0
56066  *  0b0..Bit 0 is unlocked
56067  *  0b1..Bit 0 is locked
56068  */
56069 #define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK)
56070 /*! @} */
56071 
56072 /*! @name REGION4_RDC_D1 - Region control of core domain 1 for region (n) */
56073 /*! @{ */
56074 
56075 #define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
56076 #define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
56077 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
56078  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
56079  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
56080  */
56081 #define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK)
56082 
56083 #define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
56084 #define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
56085 /*! RDC_D1_LOCK - Lock bit for bit 0
56086  *  0b0..Bit 0 is unlocked
56087  *  0b1..Bit 0 is locked
56088  */
56089 #define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK)
56090 /*! @} */
56091 
56092 /*! @name REGION5_TOP_ADDR - End address of IEE region (n) */
56093 /*! @{ */
56094 
56095 #define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
56096 #define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
56097 /*! TOP_ADDR - End address of IEE region */
56098 #define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK)
56099 /*! @} */
56100 
56101 /*! @name REGION5_BOT_ADDR - Start address of IEE region (n) */
56102 /*! @{ */
56103 
56104 #define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
56105 #define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
56106 /*! BOT_ADDR - Start address of IEE region */
56107 #define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK)
56108 /*! @} */
56109 
56110 /*! @name REGION5_RDC_D0 - Region control of core domain 0 for region (n) */
56111 /*! @{ */
56112 
56113 #define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
56114 #define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
56115 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
56116  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
56117  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
56118  */
56119 #define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK)
56120 
56121 #define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
56122 #define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
56123 /*! RDC_D0_LOCK - Lock bit for bit 0
56124  *  0b0..Bit 0 is unlocked
56125  *  0b1..Bit 0 is locked
56126  */
56127 #define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK)
56128 /*! @} */
56129 
56130 /*! @name REGION5_RDC_D1 - Region control of core domain 1 for region (n) */
56131 /*! @{ */
56132 
56133 #define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
56134 #define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
56135 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
56136  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
56137  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
56138  */
56139 #define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK)
56140 
56141 #define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
56142 #define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
56143 /*! RDC_D1_LOCK - Lock bit for bit 0
56144  *  0b0..Bit 0 is unlocked
56145  *  0b1..Bit 0 is locked
56146  */
56147 #define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK)
56148 /*! @} */
56149 
56150 /*! @name REGION6_TOP_ADDR - End address of IEE region (n) */
56151 /*! @{ */
56152 
56153 #define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
56154 #define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
56155 /*! TOP_ADDR - End address of IEE region */
56156 #define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK)
56157 /*! @} */
56158 
56159 /*! @name REGION6_BOT_ADDR - Start address of IEE region (n) */
56160 /*! @{ */
56161 
56162 #define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
56163 #define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
56164 /*! BOT_ADDR - Start address of IEE region */
56165 #define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK)
56166 /*! @} */
56167 
56168 /*! @name REGION6_RDC_D0 - Region control of core domain 0 for region (n) */
56169 /*! @{ */
56170 
56171 #define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
56172 #define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
56173 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
56174  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
56175  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
56176  */
56177 #define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK)
56178 
56179 #define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
56180 #define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
56181 /*! RDC_D0_LOCK - Lock bit for bit 0
56182  *  0b0..Bit 0 is unlocked
56183  *  0b1..Bit 0 is locked
56184  */
56185 #define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK)
56186 /*! @} */
56187 
56188 /*! @name REGION6_RDC_D1 - Region control of core domain 1 for region (n) */
56189 /*! @{ */
56190 
56191 #define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
56192 #define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
56193 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
56194  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
56195  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
56196  */
56197 #define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK)
56198 
56199 #define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
56200 #define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
56201 /*! RDC_D1_LOCK - Lock bit for bit 0
56202  *  0b0..Bit 0 is unlocked
56203  *  0b1..Bit 0 is locked
56204  */
56205 #define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK)
56206 /*! @} */
56207 
56208 /*! @name REGION7_TOP_ADDR - End address of IEE region (n) */
56209 /*! @{ */
56210 
56211 #define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK   (0x1FFFFFFFU)
56212 #define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT  (0U)
56213 /*! TOP_ADDR - End address of IEE region */
56214 #define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK)
56215 /*! @} */
56216 
56217 /*! @name REGION7_BOT_ADDR - Start address of IEE region (n) */
56218 /*! @{ */
56219 
56220 #define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK   (0x1FFFFFFFU)
56221 #define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT  (0U)
56222 /*! BOT_ADDR - Start address of IEE region */
56223 #define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR(x)     (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK)
56224 /*! @} */
56225 
56226 /*! @name REGION7_RDC_D0 - Region control of core domain 0 for region (n) */
56227 /*! @{ */
56228 
56229 #define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
56230 #define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
56231 /*! RDC_D0_WRITE_DIS - Write disable of core domain 1
56232  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
56233  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
56234  */
56235 #define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK)
56236 
56237 #define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK  (0x2U)
56238 #define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
56239 /*! RDC_D0_LOCK - Lock bit for bit 0
56240  *  0b0..Bit 0 is unlocked
56241  *  0b1..Bit 0 is locked
56242  */
56243 #define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK)
56244 /*! @} */
56245 
56246 /*! @name REGION7_RDC_D1 - Region control of core domain 1 for region (n) */
56247 /*! @{ */
56248 
56249 #define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
56250 #define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
56251 /*! RDC_D1_WRITE_DIS - Write disable of core domain 1
56252  *  0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
56253  *  0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
56254  */
56255 #define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK)
56256 
56257 #define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK  (0x2U)
56258 #define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
56259 /*! RDC_D1_LOCK - Lock bit for bit 0
56260  *  0b0..Bit 0 is unlocked
56261  *  0b1..Bit 0 is locked
56262  */
56263 #define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK(x)    (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK)
56264 /*! @} */
56265 
56266 
56267 /*!
56268  * @}
56269  */ /* end of group IEE_APC_Register_Masks */
56270 
56271 
56272 /* IEE_APC - Peripheral instance base addresses */
56273 /** Peripheral IEE_APC base address */
56274 #define IEE_APC_BASE                             (0x40068000u)
56275 /** Peripheral IEE_APC base pointer */
56276 #define IEE_APC                                  ((IEE_APC_Type *)IEE_APC_BASE)
56277 /** Array initializer of IEE_APC peripheral base addresses */
56278 #define IEE_APC_BASE_ADDRS                       { IEE_APC_BASE }
56279 /** Array initializer of IEE_APC peripheral base pointers */
56280 #define IEE_APC_BASE_PTRS                        { IEE_APC }
56281 
56282 /*!
56283  * @}
56284  */ /* end of group IEE_APC_Peripheral_Access_Layer */
56285 
56286 
56287 /* ----------------------------------------------------------------------------
56288    -- IOMUXC Peripheral Access Layer
56289    ---------------------------------------------------------------------------- */
56290 
56291 /*!
56292  * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
56293  * @{
56294  */
56295 
56296 /** IOMUXC - Register Layout Typedef */
56297 typedef struct {
56298        uint8_t RESERVED_0[16];
56299   __IO uint32_t SW_MUX_CTL_PAD[145];               /**< SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register, array offset: 0x10, array step: 0x4 */
56300   __IO uint32_t SW_PAD_CTL_PAD[145];               /**< SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register, array offset: 0x254, array step: 0x4 */
56301   __IO uint32_t SELECT_INPUT[160];                 /**< FLEXCAN1_RX_SELECT_INPUT DAISY Register..XBAR1_IN_SELECT_INPUT_35 DAISY Register, array offset: 0x498, array step: 0x4, valid indices: [0-122, 129-159] */
56302 } IOMUXC_Type;
56303 
56304 /* ----------------------------------------------------------------------------
56305    -- IOMUXC Register Masks
56306    ---------------------------------------------------------------------------- */
56307 
56308 /*!
56309  * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
56310  * @{
56311  */
56312 
56313 /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register */
56314 /*! @{ */
56315 
56316 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK      (0xFU)
56317 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT     (0U)
56318 /*! MUX_MODE - MUX Mode Select Field.
56319  *  0b0000..Select mux mode: ALT0 mux port: SEMC_DATA16 of instance: SEMC
56320  *  0b0001..Select mux mode: ALT1 mux port: CCM_ENET_REF_CLK_25M of instance: CCM
56321  *  0b0010..Select mux mode: ALT2 mux port: TMR3_TIMER1 of instance: TMR3
56322  *  0b0011..Select mux mode: ALT3 mux port: LPUART6_CTS_B of instance: LPUART6
56323  *  0b0100..Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA06 of instance: FLEXSPI2
56324  *  0b0101..Select mux mode: ALT5 mux port: GPIO_MUX2_IO10 of instance: GPIO_MUX2
56325  *  0b0110..Select mux mode: ALT6 mux port: XBAR1_INOUT20 of instance: XBAR1
56326  *  0b0111..Select mux mode: ALT7 mux port: ENET_QOS_1588_EVENT1_OUT of instance: ENET_QOS
56327  *  0b1000..Select mux mode: ALT8 mux port: LPSPI1_SCK of instance: LPSPI1
56328  *  0b1001..Select mux mode: ALT9 mux port: LPI2C2_SCL of instance: LPI2C2
56329  *  0b1010..Select mux mode: ALT10 mux port: GPIO8_IO10 of instance: GPIO8
56330  *  0b1011..Select mux mode: ALT11 mux port: FLEXPWM3_PWM0_A of instance: FLEXPWM3
56331  */
56332 #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
56333 
56334 #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK          (0x10U)
56335 #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT         (4U)
56336 /*! SION - Software Input On Field.
56337  *  0b1..Force input path of pad GPIO_DISP_B1_00
56338  *  0b0..Input Path is determined by functionality
56339  */
56340 #define IOMUXC_SW_MUX_CTL_PAD_SION(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
56341 /*! @} */
56342 
56343 /* The count of IOMUXC_SW_MUX_CTL_PAD */
56344 #define IOMUXC_SW_MUX_CTL_PAD_COUNT              (145U)
56345 
56346 /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register */
56347 /*! @{ */
56348 
56349 #define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK           (0x1U)
56350 #define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT          (0U)
56351 /*! SRE - Slew Rate Field
56352  *  0b0..Slow Slew Rate
56353  *  0b1..Fast Slew Rate
56354  */
56355 #define IOMUXC_SW_PAD_CTL_PAD_SRE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
56356 
56357 #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK           (0x2U)
56358 #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT          (1U)
56359 /*! DSE - Drive Strength Field
56360  *  0b0..normal drive strength
56361  *  0b1..high drive strength
56362  */
56363 #define IOMUXC_SW_PAD_CTL_PAD_DSE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
56364 
56365 #define IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK          (0x2U)
56366 #define IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT         (1U)
56367 /*! PDRV - PDRV Field
56368  *  0b0..high drive strength
56369  *  0b1..normal drive strength
56370  */
56371 #define IOMUXC_SW_PAD_CTL_PAD_PDRV(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK)
56372 
56373 #define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK           (0x4U)
56374 #define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT          (2U)
56375 /*! PUE - Pull / Keep Select Field
56376  *  0b0..Pull Disable
56377  *  0b1..Pull Enable
56378  */
56379 #define IOMUXC_SW_PAD_CTL_PAD_PUE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
56380 
56381 #define IOMUXC_SW_PAD_CTL_PAD_PULL_MASK          (0xCU)
56382 #define IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT         (2U)
56383 /*! PULL - Pull Down Pull Up Field
56384  *  0b00..Forbidden
56385  *  0b01..Internal pullup resistor enabled
56386  *  0b10..Internal pulldown resistor enabled
56387  *  0b11..No Pull
56388  */
56389 #define IOMUXC_SW_PAD_CTL_PAD_PULL(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PULL_MASK)
56390 
56391 #define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK           (0x8U)
56392 #define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT          (3U)
56393 /*! PUS - Pull Up / Down Config. Field
56394  *  0b0..Weak pull down
56395  *  0b1..Weak pull up
56396  */
56397 #define IOMUXC_SW_PAD_CTL_PAD_PUS(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
56398 
56399 #define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK           (0x10U)
56400 #define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT          (4U)
56401 /*! ODE - Open Drain Field
56402  *  0b0..Disabled
56403  *  0b1..Enabled
56404  */
56405 #define IOMUXC_SW_PAD_CTL_PAD_ODE(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
56406 
56407 #define IOMUXC_SW_PAD_CTL_PAD_DWP_MASK           (0x30000000U)
56408 #define IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT          (28U)
56409 /*! DWP - Domain write protection
56410  *  0b00..Both cores are allowed
56411  *  0b01..CM7 is forbidden
56412  *  0b10..CM4 is forbidden
56413  *  0b11..Both cores are forbidden
56414  */
56415 #define IOMUXC_SW_PAD_CTL_PAD_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_MASK)
56416 
56417 #define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK      (0xC0000000U)
56418 #define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT     (30U)
56419 /*! DWP_LOCK - Domain write protection lock
56420  *  0b00..Neither of DWP bits is locked
56421  *  0b01..The lower DWP bit is locked
56422  *  0b10..The higher DWP bit is locked
56423  *  0b11..Both DWP bits are locked
56424  */
56425 #define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK)
56426 /*! @} */
56427 
56428 /* The count of IOMUXC_SW_PAD_CTL_PAD */
56429 #define IOMUXC_SW_PAD_CTL_PAD_COUNT              (145U)
56430 
56431 /*! @name SELECT_INPUT - FLEXCAN1_RX_SELECT_INPUT DAISY Register..XBAR1_IN_SELECT_INPUT_35 DAISY Register */
56432 /*! @{ */
56433 
56434 #define IOMUXC_SELECT_INPUT_DAISY_MASK           (0x3U)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
56435 #define IOMUXC_SELECT_INPUT_DAISY_SHIFT          (0U)
56436 /*! DAISY - Selecting Pads Involved in Daisy Chain.
56437  *  0b00..Selecting Pad: GPIO_EMC_B2_19 for Mode: ALT3
56438  *  0b01..Selecting Pad: GPIO_SD_B2_11 for Mode: ALT3
56439  *  0b10..Selecting Pad: GPIO_DISP_B1_11 for Mode: ALT2
56440  *  0b11..Selecting Pad: GPIO_DISP_B2_14 for Mode: ALT4
56441  */
56442 #define IOMUXC_SELECT_INPUT_DAISY(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
56443 /*! @} */
56444 
56445 /* The count of IOMUXC_SELECT_INPUT */
56446 #define IOMUXC_SELECT_INPUT_COUNT                (160U)
56447 
56448 
56449 /*!
56450  * @}
56451  */ /* end of group IOMUXC_Register_Masks */
56452 
56453 
56454 /* IOMUXC - Peripheral instance base addresses */
56455 /** Peripheral IOMUXC base address */
56456 #define IOMUXC_BASE                              (0x400E8000u)
56457 /** Peripheral IOMUXC base pointer */
56458 #define IOMUXC                                   ((IOMUXC_Type *)IOMUXC_BASE)
56459 /** Array initializer of IOMUXC peripheral base addresses */
56460 #define IOMUXC_BASE_ADDRS                        { IOMUXC_BASE }
56461 /** Array initializer of IOMUXC peripheral base pointers */
56462 #define IOMUXC_BASE_PTRS                         { IOMUXC }
56463 
56464 /*!
56465  * @}
56466  */ /* end of group IOMUXC_Peripheral_Access_Layer */
56467 
56468 
56469 /* ----------------------------------------------------------------------------
56470    -- IOMUXC_GPR Peripheral Access Layer
56471    ---------------------------------------------------------------------------- */
56472 
56473 /*!
56474  * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer
56475  * @{
56476  */
56477 
56478 /** IOMUXC_GPR - Register Layout Typedef */
56479 typedef struct {
56480   __IO uint32_t GPR0;                              /**< GPR0 General Purpose Register, offset: 0x0 */
56481   __IO uint32_t GPR1;                              /**< GPR1 General Purpose Register, offset: 0x4 */
56482   __IO uint32_t GPR2;                              /**< GPR2 General Purpose Register, offset: 0x8 */
56483   __IO uint32_t GPR3;                              /**< GPR3 General Purpose Register, offset: 0xC */
56484   __IO uint32_t GPR4;                              /**< GPR4 General Purpose Register, offset: 0x10 */
56485   __IO uint32_t GPR5;                              /**< GPR5 General Purpose Register, offset: 0x14 */
56486   __IO uint32_t GPR6;                              /**< GPR6 General Purpose Register, offset: 0x18 */
56487   __IO uint32_t GPR7;                              /**< GPR7 General Purpose Register, offset: 0x1C */
56488   __IO uint32_t GPR8;                              /**< GPR8 General Purpose Register, offset: 0x20 */
56489   __IO uint32_t GPR9;                              /**< GPR9 General Purpose Register, offset: 0x24 */
56490   __IO uint32_t GPR10;                             /**< GPR10 General Purpose Register, offset: 0x28 */
56491   __IO uint32_t GPR11;                             /**< GPR11 General Purpose Register, offset: 0x2C */
56492   __IO uint32_t GPR12;                             /**< GPR12 General Purpose Register, offset: 0x30 */
56493   __IO uint32_t GPR13;                             /**< GPR13 General Purpose Register, offset: 0x34 */
56494   __IO uint32_t GPR14;                             /**< GPR14 General Purpose Register, offset: 0x38 */
56495   __IO uint32_t GPR15;                             /**< GPR15 General Purpose Register, offset: 0x3C */
56496   __IO uint32_t GPR16;                             /**< GPR16 General Purpose Register, offset: 0x40 */
56497   __IO uint32_t GPR17;                             /**< GPR17 General Purpose Register, offset: 0x44 */
56498   __IO uint32_t GPR18;                             /**< GPR18 General Purpose Register, offset: 0x48 */
56499        uint8_t RESERVED_0[4];
56500   __IO uint32_t GPR20;                             /**< GPR20 General Purpose Register, offset: 0x50 */
56501   __IO uint32_t GPR21;                             /**< GPR21 General Purpose Register, offset: 0x54 */
56502   __IO uint32_t GPR22;                             /**< GPR22 General Purpose Register, offset: 0x58 */
56503   __IO uint32_t GPR23;                             /**< GPR23 General Purpose Register, offset: 0x5C */
56504   __IO uint32_t GPR24;                             /**< GPR24 General Purpose Register, offset: 0x60 */
56505   __IO uint32_t GPR25;                             /**< GPR25 General Purpose Register, offset: 0x64 */
56506   __IO uint32_t GPR26;                             /**< GPR26 General Purpose Register, offset: 0x68 */
56507   __IO uint32_t GPR27;                             /**< GPR27 General Purpose Register, offset: 0x6C */
56508   __IO uint32_t GPR28;                             /**< GPR28 General Purpose Register, offset: 0x70 */
56509   __IO uint32_t GPR29;                             /**< GPR29 General Purpose Register, offset: 0x74 */
56510   __IO uint32_t GPR30;                             /**< GPR30 General Purpose Register, offset: 0x78 */
56511   __IO uint32_t GPR31;                             /**< GPR31 General Purpose Register, offset: 0x7C */
56512   __IO uint32_t GPR32;                             /**< GPR32 General Purpose Register, offset: 0x80 */
56513   __IO uint32_t GPR33;                             /**< GPR33 General Purpose Register, offset: 0x84 */
56514   __IO uint32_t GPR34;                             /**< GPR34 General Purpose Register, offset: 0x88 */
56515   __IO uint32_t GPR35;                             /**< GPR35 General Purpose Register, offset: 0x8C */
56516   __IO uint32_t GPR36;                             /**< GPR36 General Purpose Register, offset: 0x90 */
56517   __IO uint32_t GPR37;                             /**< GPR37 General Purpose Register, offset: 0x94 */
56518   __IO uint32_t GPR38;                             /**< GPR38 General Purpose Register, offset: 0x98 */
56519   __IO uint32_t GPR39;                             /**< GPR39 General Purpose Register, offset: 0x9C */
56520   __IO uint32_t GPR40;                             /**< GPR40 General Purpose Register, offset: 0xA0 */
56521   __IO uint32_t GPR41;                             /**< GPR41 General Purpose Register, offset: 0xA4 */
56522   __IO uint32_t GPR42;                             /**< GPR42 General Purpose Register, offset: 0xA8 */
56523   __IO uint32_t GPR43;                             /**< GPR43 General Purpose Register, offset: 0xAC */
56524   __IO uint32_t GPR44;                             /**< GPR44 General Purpose Register, offset: 0xB0 */
56525   __IO uint32_t GPR45;                             /**< GPR45 General Purpose Register, offset: 0xB4 */
56526   __IO uint32_t GPR46;                             /**< GPR46 General Purpose Register, offset: 0xB8 */
56527   __IO uint32_t GPR47;                             /**< GPR47 General Purpose Register, offset: 0xBC */
56528   __IO uint32_t GPR48;                             /**< GPR48 General Purpose Register, offset: 0xC0 */
56529   __IO uint32_t GPR49;                             /**< GPR49 General Purpose Register, offset: 0xC4 */
56530   __IO uint32_t GPR50;                             /**< GPR50 General Purpose Register, offset: 0xC8 */
56531   __IO uint32_t GPR51;                             /**< GPR51 General Purpose Register, offset: 0xCC */
56532   __IO uint32_t GPR52;                             /**< GPR52 General Purpose Register, offset: 0xD0 */
56533   __IO uint32_t GPR53;                             /**< GPR53 General Purpose Register, offset: 0xD4 */
56534   __IO uint32_t GPR54;                             /**< GPR54 General Purpose Register, offset: 0xD8 */
56535   __IO uint32_t GPR55;                             /**< GPR55 General Purpose Register, offset: 0xDC */
56536        uint8_t RESERVED_1[12];
56537   __IO uint32_t GPR59;                             /**< GPR59 General Purpose Register, offset: 0xEC */
56538        uint8_t RESERVED_2[8];
56539   __IO uint32_t GPR62;                             /**< GPR62 General Purpose Register, offset: 0xF8 */
56540   __I  uint32_t GPR63;                             /**< GPR63 General Purpose Register, offset: 0xFC */
56541   __IO uint32_t GPR64;                             /**< GPR64 General Purpose Register, offset: 0x100 */
56542   __IO uint32_t GPR65;                             /**< GPR65 General Purpose Register, offset: 0x104 */
56543   __IO uint32_t GPR66;                             /**< GPR66 General Purpose Register, offset: 0x108 */
56544   __IO uint32_t GPR67;                             /**< GPR67 General Purpose Register, offset: 0x10C */
56545   __IO uint32_t GPR68;                             /**< GPR68 General Purpose Register, offset: 0x110 */
56546   __IO uint32_t GPR69;                             /**< GPR69 General Purpose Register, offset: 0x114 */
56547   __IO uint32_t GPR70;                             /**< GPR70 General Purpose Register, offset: 0x118 */
56548   __IO uint32_t GPR71;                             /**< GPR71 General Purpose Register, offset: 0x11C */
56549   __IO uint32_t GPR72;                             /**< GPR72 General Purpose Register, offset: 0x120 */
56550   __IO uint32_t GPR73;                             /**< GPR73 General Purpose Register, offset: 0x124 */
56551   __IO uint32_t GPR74;                             /**< GPR74 General Purpose Register, offset: 0x128 */
56552   __I  uint32_t GPR75;                             /**< GPR75 General Purpose Register, offset: 0x12C */
56553   __I  uint32_t GPR76;                             /**< GPR76 General Purpose Register, offset: 0x130 */
56554 } IOMUXC_GPR_Type;
56555 
56556 /* ----------------------------------------------------------------------------
56557    -- IOMUXC_GPR Register Masks
56558    ---------------------------------------------------------------------------- */
56559 
56560 /*!
56561  * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks
56562  * @{
56563  */
56564 
56565 /*! @name GPR0 - GPR0 General Purpose Register */
56566 /*! @{ */
56567 
56568 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK      (0x7U)
56569 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT     (0U)
56570 /*! SAI1_MCLK1_SEL - SAI1 MCLK1 source select */
56571 #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
56572 
56573 #define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK      (0x38U)
56574 #define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT     (3U)
56575 /*! SAI1_MCLK2_SEL - SAI1 MCLK2 source select */
56576 #define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK)
56577 
56578 #define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK      (0xC0U)
56579 #define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT     (6U)
56580 /*! SAI1_MCLK3_SEL - SAI1 MCLK3 source select */
56581 #define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK)
56582 
56583 #define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK       (0x100U)
56584 #define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT      (8U)
56585 /*! SAI1_MCLK_DIR - SAI1_MCLK signal direction control */
56586 #define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK)
56587 
56588 #define IOMUXC_GPR_GPR0_DWP_MASK                 (0x30000000U)
56589 #define IOMUXC_GPR_GPR0_DWP_SHIFT                (28U)
56590 /*! DWP - Domain write protection
56591  *  0b00..Both cores are allowed
56592  *  0b01..CM7 is forbidden
56593  *  0b10..CM4 is forbidden
56594  *  0b11..Both cores are forbidden
56595  */
56596 #define IOMUXC_GPR_GPR0_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_SHIFT)) & IOMUXC_GPR_GPR0_DWP_MASK)
56597 
56598 #define IOMUXC_GPR_GPR0_DWP_LOCK_MASK            (0xC0000000U)
56599 #define IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT           (30U)
56600 /*! DWP_LOCK - Domain write protection lock
56601  *  0b00..Neither of DWP bits is locked
56602  *  0b01..The lower DWP bit is locked
56603  *  0b10..The higher DWP bit is locked
56604  *  0b11..Both DWP bits are locked
56605  */
56606 #define IOMUXC_GPR_GPR0_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR0_DWP_LOCK_MASK)
56607 /*! @} */
56608 
56609 /*! @name GPR1 - GPR1 General Purpose Register */
56610 /*! @{ */
56611 
56612 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK      (0x3U)
56613 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT     (0U)
56614 /*! SAI2_MCLK3_SEL - SAI2 MCLK3 source select */
56615 #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
56616 
56617 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK       (0x100U)
56618 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT      (8U)
56619 /*! SAI2_MCLK_DIR - SAI2_MCLK signal direction control */
56620 #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
56621 
56622 #define IOMUXC_GPR_GPR1_DWP_MASK                 (0x30000000U)
56623 #define IOMUXC_GPR_GPR1_DWP_SHIFT                (28U)
56624 /*! DWP - Domain write protection
56625  *  0b00..Both cores are allowed
56626  *  0b01..CM7 is forbidden
56627  *  0b10..CM4 is forbidden
56628  *  0b11..Both cores are forbidden
56629  */
56630 #define IOMUXC_GPR_GPR1_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_SHIFT)) & IOMUXC_GPR_GPR1_DWP_MASK)
56631 
56632 #define IOMUXC_GPR_GPR1_DWP_LOCK_MASK            (0xC0000000U)
56633 #define IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT           (30U)
56634 /*! DWP_LOCK - Domain write protection lock
56635  *  0b00..Neither of DWP bits is locked
56636  *  0b01..The lower DWP bit is locked
56637  *  0b10..The higher DWP bit is locked
56638  *  0b11..Both DWP bits are locked
56639  */
56640 #define IOMUXC_GPR_GPR1_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_DWP_LOCK_MASK)
56641 /*! @} */
56642 
56643 /*! @name GPR2 - GPR2 General Purpose Register */
56644 /*! @{ */
56645 
56646 #define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK      (0x3U)
56647 #define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT     (0U)
56648 /*! SAI3_MCLK3_SEL - SAI3 MCLK3 source select */
56649 #define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK)
56650 
56651 #define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK       (0x100U)
56652 #define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT      (8U)
56653 /*! SAI3_MCLK_DIR - SAI3_MCLK signal direction control */
56654 #define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK)
56655 
56656 #define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK       (0x200U)
56657 #define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT      (9U)
56658 /*! SAI4_MCLK_DIR - SAI4_MCLK signal direction control */
56659 #define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK)
56660 
56661 #define IOMUXC_GPR_GPR2_DWP_MASK                 (0x30000000U)
56662 #define IOMUXC_GPR_GPR2_DWP_SHIFT                (28U)
56663 /*! DWP - Domain write protection
56664  *  0b00..Both cores are allowed
56665  *  0b01..CM7 is forbidden
56666  *  0b10..CM4 is forbidden
56667  *  0b11..Both cores are forbidden
56668  */
56669 #define IOMUXC_GPR_GPR2_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_SHIFT)) & IOMUXC_GPR_GPR2_DWP_MASK)
56670 
56671 #define IOMUXC_GPR_GPR2_DWP_LOCK_MASK            (0xC0000000U)
56672 #define IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT           (30U)
56673 /*! DWP_LOCK - Domain write protection lock
56674  *  0b00..Neither of DWP bits is locked
56675  *  0b01..The lower DWP bit is locked
56676  *  0b10..The higher DWP bit is locked
56677  *  0b11..Both DWP bits are locked
56678  */
56679 #define IOMUXC_GPR_GPR2_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR2_DWP_LOCK_MASK)
56680 /*! @} */
56681 
56682 /*! @name GPR3 - GPR3 General Purpose Register */
56683 /*! @{ */
56684 
56685 #define IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK         (0xFFU)
56686 #define IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT        (0U)
56687 /*! MQS_CLK_DIV - Divider ratio control for mclk from hmclk. */
56688 #define IOMUXC_GPR_GPR3_MQS_CLK_DIV(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK)
56689 
56690 #define IOMUXC_GPR_GPR3_MQS_SW_RST_MASK          (0x100U)
56691 #define IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT         (8U)
56692 /*! MQS_SW_RST - MQS software reset */
56693 #define IOMUXC_GPR_GPR3_MQS_SW_RST(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR3_MQS_SW_RST_MASK)
56694 
56695 #define IOMUXC_GPR_GPR3_MQS_EN_MASK              (0x200U)
56696 #define IOMUXC_GPR_GPR3_MQS_EN_SHIFT             (9U)
56697 /*! MQS_EN - MQS enable */
56698 #define IOMUXC_GPR_GPR3_MQS_EN(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR3_MQS_EN_MASK)
56699 
56700 #define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK      (0x400U)
56701 #define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT     (10U)
56702 /*! MQS_OVERSAMPLE - Medium Quality Sound (MQS) Oversample */
56703 #define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK)
56704 
56705 #define IOMUXC_GPR_GPR3_DWP_MASK                 (0x30000000U)
56706 #define IOMUXC_GPR_GPR3_DWP_SHIFT                (28U)
56707 /*! DWP - Domain write protection
56708  *  0b00..Both cores are allowed
56709  *  0b01..CM7 is forbidden
56710  *  0b10..CM4 is forbidden
56711  *  0b11..Both cores are forbidden
56712  */
56713 #define IOMUXC_GPR_GPR3_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_SHIFT)) & IOMUXC_GPR_GPR3_DWP_MASK)
56714 
56715 #define IOMUXC_GPR_GPR3_DWP_LOCK_MASK            (0xC0000000U)
56716 #define IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT           (30U)
56717 /*! DWP_LOCK - Domain write protection lock
56718  *  0b00..Neither of DWP bits is locked
56719  *  0b01..The lower DWP bit is locked
56720  *  0b10..The higher DWP bit is locked
56721  *  0b11..Both DWP bits are locked
56722  */
56723 #define IOMUXC_GPR_GPR3_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR3_DWP_LOCK_MASK)
56724 /*! @} */
56725 
56726 /*! @name GPR4 - GPR4 General Purpose Register */
56727 /*! @{ */
56728 
56729 #define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK     (0x1U)
56730 #define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT    (0U)
56731 /*! ENET_TX_CLK_SEL - ENET TX_CLK select */
56732 #define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK)
56733 
56734 #define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK    (0x2U)
56735 #define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT   (1U)
56736 /*! ENET_REF_CLK_DIR - ENET_REF_CLK direction control */
56737 #define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK)
56738 
56739 #define IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK       (0x4U)
56740 #define IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT      (2U)
56741 /*! ENET_TIME_SEL - ENET master timer source select */
56742 #define IOMUXC_GPR_GPR4_ENET_TIME_SEL(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK)
56743 
56744 #define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK   (0x8U)
56745 #define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT  (3U)
56746 /*! ENET_EVENT0IN_SEL - ENET ENET_1588_EVENT0_IN source select */
56747 #define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK)
56748 
56749 #define IOMUXC_GPR_GPR4_DWP_MASK                 (0x30000000U)
56750 #define IOMUXC_GPR_GPR4_DWP_SHIFT                (28U)
56751 /*! DWP - Domain write protection
56752  *  0b00..Both cores are allowed
56753  *  0b01..CM7 is forbidden
56754  *  0b10..CM4 is forbidden
56755  *  0b11..Both cores are forbidden
56756  */
56757 #define IOMUXC_GPR_GPR4_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_SHIFT)) & IOMUXC_GPR_GPR4_DWP_MASK)
56758 
56759 #define IOMUXC_GPR_GPR4_DWP_LOCK_MASK            (0xC0000000U)
56760 #define IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT           (30U)
56761 /*! DWP_LOCK - Domain write protection lock
56762  *  0b00..Neither of DWP bits is locked
56763  *  0b01..The lower DWP bit is locked
56764  *  0b10..The higher DWP bit is locked
56765  *  0b11..Both DWP bits are locked
56766  */
56767 #define IOMUXC_GPR_GPR4_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR4_DWP_LOCK_MASK)
56768 /*! @} */
56769 
56770 /*! @name GPR5 - GPR5 General Purpose Register */
56771 /*! @{ */
56772 
56773 #define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK   (0x1U)
56774 #define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT  (0U)
56775 /*! ENET1G_TX_CLK_SEL - ENET1G TX_CLK select */
56776 #define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK)
56777 
56778 #define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK  (0x2U)
56779 #define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT (1U)
56780 /*! ENET1G_REF_CLK_DIR - ENET1G_REF_CLK direction control */
56781 #define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK)
56782 
56783 #define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK     (0x4U)
56784 #define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT    (2U)
56785 /*! ENET1G_RGMII_EN - ENET1G RGMII TX clock output enable */
56786 #define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK)
56787 
56788 #define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK     (0x8U)
56789 #define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT    (3U)
56790 /*! ENET1G_TIME_SEL - ENET1G master timer source select */
56791 #define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK)
56792 
56793 #define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK (0x10U)
56794 #define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT (4U)
56795 /*! ENET1G_EVENT0IN_SEL - ENET1G ENET_1588_EVENT0_IN source select */
56796 #define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK)
56797 
56798 #define IOMUXC_GPR_GPR5_DWP_MASK                 (0x30000000U)
56799 #define IOMUXC_GPR_GPR5_DWP_SHIFT                (28U)
56800 /*! DWP - Domain write protection
56801  *  0b00..Both cores are allowed
56802  *  0b01..CM7 is forbidden
56803  *  0b10..CM4 is forbidden
56804  *  0b11..Both cores are forbidden
56805  */
56806 #define IOMUXC_GPR_GPR5_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_SHIFT)) & IOMUXC_GPR_GPR5_DWP_MASK)
56807 
56808 #define IOMUXC_GPR_GPR5_DWP_LOCK_MASK            (0xC0000000U)
56809 #define IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT           (30U)
56810 /*! DWP_LOCK - Domain write protection lock
56811  *  0b00..Neither of DWP bits is locked
56812  *  0b01..The lower DWP bit is locked
56813  *  0b10..The higher DWP bit is locked
56814  *  0b11..Both DWP bits are locked
56815  */
56816 #define IOMUXC_GPR_GPR5_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR5_DWP_LOCK_MASK)
56817 /*! @} */
56818 
56819 /*! @name GPR6 - GPR6 General Purpose Register */
56820 /*! @{ */
56821 
56822 #define IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK (0x1U)
56823 #define IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_SHIFT (0U)
56824 /*! ENET_QOS_REF_CLK_DIR - ENET_QOS_REF_CLK direction control */
56825 #define IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK)
56826 
56827 #define IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK   (0x2U)
56828 #define IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_SHIFT  (1U)
56829 /*! ENET_QOS_RGMII_EN - ENET_QOS RGMII TX clock output enable */
56830 #define IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK)
56831 
56832 #define IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_MASK   (0x4U)
56833 #define IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_SHIFT  (2U)
56834 /*! ENET_QOS_TIME_SEL - ENET_QOS master timer source select */
56835 #define IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_MASK)
56836 
56837 #define IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_MASK   (0x38U)
56838 #define IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_SHIFT  (3U)
56839 /*! ENET_QOS_INTF_SEL - ENET_QOS PHY Interface Select */
56840 #define IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_MASK)
56841 
56842 #define IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_MASK  (0x40U)
56843 #define IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_SHIFT (6U)
56844 /*! ENET_QOS_CLKGEN_EN - ENET_QOS clock generator enable */
56845 #define IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_MASK)
56846 
56847 #define IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_MASK (0x80U)
56848 #define IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_SHIFT (7U)
56849 /*! ENET_QOS_EVENT0IN_SEL - ENET_QOS ENET_1588_EVENT0_IN source select */
56850 #define IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_MASK)
56851 
56852 #define IOMUXC_GPR_GPR6_DWP_MASK                 (0x30000000U)
56853 #define IOMUXC_GPR_GPR6_DWP_SHIFT                (28U)
56854 /*! DWP - Domain write protection
56855  *  0b00..Both cores are allowed
56856  *  0b01..CM7 is forbidden
56857  *  0b10..CM4 is forbidden
56858  *  0b11..Both cores are forbidden
56859  */
56860 #define IOMUXC_GPR_GPR6_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_DWP_SHIFT)) & IOMUXC_GPR_GPR6_DWP_MASK)
56861 
56862 #define IOMUXC_GPR_GPR6_DWP_LOCK_MASK            (0xC0000000U)
56863 #define IOMUXC_GPR_GPR6_DWP_LOCK_SHIFT           (30U)
56864 /*! DWP_LOCK - Domain write protection lock
56865  *  0b00..Neither of DWP bits is locked
56866  *  0b01..The lower DWP bit is locked
56867  *  0b10..The higher DWP bit is locked
56868  *  0b11..Both DWP bits are locked
56869  */
56870 #define IOMUXC_GPR_GPR6_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR6_DWP_LOCK_MASK)
56871 /*! @} */
56872 
56873 /*! @name GPR7 - GPR7 General Purpose Register */
56874 /*! @{ */
56875 
56876 #define IOMUXC_GPR_GPR7_GINT_MASK                (0x1U)
56877 #define IOMUXC_GPR_GPR7_GINT_SHIFT               (0U)
56878 /*! GINT - Global interrupt */
56879 #define IOMUXC_GPR_GPR7_GINT(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GINT_SHIFT)) & IOMUXC_GPR_GPR7_GINT_MASK)
56880 
56881 #define IOMUXC_GPR_GPR7_DWP_MASK                 (0x30000000U)
56882 #define IOMUXC_GPR_GPR7_DWP_SHIFT                (28U)
56883 /*! DWP - Domain write protection
56884  *  0b00..Both cores are allowed
56885  *  0b01..CM7 is forbidden
56886  *  0b10..CM4 is forbidden
56887  *  0b11..Both cores are forbidden
56888  */
56889 #define IOMUXC_GPR_GPR7_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_SHIFT)) & IOMUXC_GPR_GPR7_DWP_MASK)
56890 
56891 #define IOMUXC_GPR_GPR7_DWP_LOCK_MASK            (0xC0000000U)
56892 #define IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT           (30U)
56893 /*! DWP_LOCK - Domain write protection lock
56894  *  0b00..Neither of DWP bits is locked
56895  *  0b01..The lower DWP bit is locked
56896  *  0b10..The higher DWP bit is locked
56897  *  0b11..Both DWP bits are locked
56898  */
56899 #define IOMUXC_GPR_GPR7_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR7_DWP_LOCK_MASK)
56900 /*! @} */
56901 
56902 /*! @name GPR8 - GPR8 General Purpose Register */
56903 /*! @{ */
56904 
56905 #define IOMUXC_GPR_GPR8_WDOG1_MASK_MASK          (0x1U)
56906 #define IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT         (0U)
56907 /*! WDOG1_MASK - WDOG1 timeout mask for WDOG_ANY */
56908 #define IOMUXC_GPR_GPR8_WDOG1_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR8_WDOG1_MASK_MASK)
56909 
56910 #define IOMUXC_GPR_GPR8_DWP_MASK                 (0x30000000U)
56911 #define IOMUXC_GPR_GPR8_DWP_SHIFT                (28U)
56912 /*! DWP - Domain write protection
56913  *  0b00..Both cores are allowed
56914  *  0b01..CM7 is forbidden
56915  *  0b10..CM4 is forbidden
56916  *  0b11..Both cores are forbidden
56917  */
56918 #define IOMUXC_GPR_GPR8_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_SHIFT)) & IOMUXC_GPR_GPR8_DWP_MASK)
56919 
56920 #define IOMUXC_GPR_GPR8_DWP_LOCK_MASK            (0xC0000000U)
56921 #define IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT           (30U)
56922 /*! DWP_LOCK - Domain write protection lock
56923  *  0b00..Neither of DWP bits is locked
56924  *  0b01..The lower DWP bit is locked
56925  *  0b10..The higher DWP bit is locked
56926  *  0b11..Both DWP bits are locked
56927  */
56928 #define IOMUXC_GPR_GPR8_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR8_DWP_LOCK_MASK)
56929 /*! @} */
56930 
56931 /*! @name GPR9 - GPR9 General Purpose Register */
56932 /*! @{ */
56933 
56934 #define IOMUXC_GPR_GPR9_WDOG2_MASK_MASK          (0x1U)
56935 #define IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT         (0U)
56936 /*! WDOG2_MASK - WDOG2 timeout mask for WDOG_ANY */
56937 #define IOMUXC_GPR_GPR9_WDOG2_MASK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR9_WDOG2_MASK_MASK)
56938 
56939 #define IOMUXC_GPR_GPR9_DWP_MASK                 (0x30000000U)
56940 #define IOMUXC_GPR_GPR9_DWP_SHIFT                (28U)
56941 /*! DWP - Domain write protection
56942  *  0b00..Both cores are allowed
56943  *  0b01..CM7 is forbidden
56944  *  0b10..CM4 is forbidden
56945  *  0b11..Both cores are forbidden
56946  */
56947 #define IOMUXC_GPR_GPR9_DWP(x)                   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_SHIFT)) & IOMUXC_GPR_GPR9_DWP_MASK)
56948 
56949 #define IOMUXC_GPR_GPR9_DWP_LOCK_MASK            (0xC0000000U)
56950 #define IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT           (30U)
56951 /*! DWP_LOCK - Domain write protection lock
56952  *  0b00..Neither of DWP bits is locked
56953  *  0b01..The lower DWP bit is locked
56954  *  0b10..The higher DWP bit is locked
56955  *  0b11..Both DWP bits are locked
56956  */
56957 #define IOMUXC_GPR_GPR9_DWP_LOCK(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR9_DWP_LOCK_MASK)
56958 /*! @} */
56959 
56960 /*! @name GPR10 - GPR10 General Purpose Register */
56961 /*! @{ */
56962 
56963 #define IOMUXC_GPR_GPR10_DWP_MASK                (0x30000000U)
56964 #define IOMUXC_GPR_GPR10_DWP_SHIFT               (28U)
56965 /*! DWP - Domain write protection
56966  *  0b00..Both cores are allowed
56967  *  0b01..CM7 is forbidden
56968  *  0b10..CM4 is forbidden
56969  *  0b11..Both cores are forbidden
56970  */
56971 #define IOMUXC_GPR_GPR10_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_SHIFT)) & IOMUXC_GPR_GPR10_DWP_MASK)
56972 
56973 #define IOMUXC_GPR_GPR10_DWP_LOCK_MASK           (0xC0000000U)
56974 #define IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT          (30U)
56975 /*! DWP_LOCK - Domain write protection lock
56976  *  0b00..Neither of DWP bits is locked
56977  *  0b01..The lower DWP bit is locked
56978  *  0b10..The higher DWP bit is locked
56979  *  0b11..Both DWP bits are locked
56980  */
56981 #define IOMUXC_GPR_GPR10_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR10_DWP_LOCK_MASK)
56982 /*! @} */
56983 
56984 /*! @name GPR11 - GPR11 General Purpose Register */
56985 /*! @{ */
56986 
56987 #define IOMUXC_GPR_GPR11_DWP_MASK                (0x30000000U)
56988 #define IOMUXC_GPR_GPR11_DWP_SHIFT               (28U)
56989 /*! DWP - Domain write protection
56990  *  0b00..Both cores are allowed
56991  *  0b01..CM7 is forbidden
56992  *  0b10..CM4 is forbidden
56993  *  0b11..Both cores are forbidden
56994  */
56995 #define IOMUXC_GPR_GPR11_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_SHIFT)) & IOMUXC_GPR_GPR11_DWP_MASK)
56996 
56997 #define IOMUXC_GPR_GPR11_DWP_LOCK_MASK           (0xC0000000U)
56998 #define IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT          (30U)
56999 /*! DWP_LOCK - Domain write protection lock
57000  *  0b00..Neither of DWP bits is locked
57001  *  0b01..The lower DWP bit is locked
57002  *  0b10..The higher DWP bit is locked
57003  *  0b11..Both DWP bits are locked
57004  */
57005 #define IOMUXC_GPR_GPR11_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR11_DWP_LOCK_MASK)
57006 /*! @} */
57007 
57008 /*! @name GPR12 - GPR12 General Purpose Register */
57009 /*! @{ */
57010 
57011 #define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK (0x1U)
57012 #define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT (0U)
57013 /*! QTIMER1_TMR_CNTS_FREEZE - QTIMER1 timer counter freeze */
57014 #define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK)
57015 
57016 #define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK (0x100U)
57017 #define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT (8U)
57018 /*! QTIMER1_TRM0_INPUT_SEL - QTIMER1 TMR0 input select */
57019 #define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK)
57020 
57021 #define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK (0x200U)
57022 #define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT (9U)
57023 /*! QTIMER1_TRM1_INPUT_SEL - QTIMER1 TMR1 input select */
57024 #define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK)
57025 
57026 #define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK (0x400U)
57027 #define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT (10U)
57028 /*! QTIMER1_TRM2_INPUT_SEL - QTIMER1 TMR2 input select */
57029 #define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK)
57030 
57031 #define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK (0x800U)
57032 #define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT (11U)
57033 /*! QTIMER1_TRM3_INPUT_SEL - QTIMER1 TMR3 input select */
57034 #define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK)
57035 
57036 #define IOMUXC_GPR_GPR12_DWP_MASK                (0x30000000U)
57037 #define IOMUXC_GPR_GPR12_DWP_SHIFT               (28U)
57038 /*! DWP - Domain write protection
57039  *  0b00..Both cores are allowed
57040  *  0b01..CM7 is forbidden
57041  *  0b10..CM4 is forbidden
57042  *  0b11..Both cores are forbidden
57043  */
57044 #define IOMUXC_GPR_GPR12_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_SHIFT)) & IOMUXC_GPR_GPR12_DWP_MASK)
57045 
57046 #define IOMUXC_GPR_GPR12_DWP_LOCK_MASK           (0xC0000000U)
57047 #define IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT          (30U)
57048 /*! DWP_LOCK - Domain write protection lock
57049  *  0b00..Neither of DWP bits is locked
57050  *  0b01..The lower DWP bit is locked
57051  *  0b10..The higher DWP bit is locked
57052  *  0b11..Both DWP bits are locked
57053  */
57054 #define IOMUXC_GPR_GPR12_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR12_DWP_LOCK_MASK)
57055 /*! @} */
57056 
57057 /*! @name GPR13 - GPR13 General Purpose Register */
57058 /*! @{ */
57059 
57060 #define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK (0x1U)
57061 #define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT (0U)
57062 /*! QTIMER2_TMR_CNTS_FREEZE - QTIMER2 timer counter freeze */
57063 #define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK)
57064 
57065 #define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK (0x100U)
57066 #define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT (8U)
57067 /*! QTIMER2_TRM0_INPUT_SEL - QTIMER2 TMR0 input select */
57068 #define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK)
57069 
57070 #define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK (0x200U)
57071 #define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT (9U)
57072 /*! QTIMER2_TRM1_INPUT_SEL - QTIMER2 TMR1 input select */
57073 #define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK)
57074 
57075 #define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK (0x400U)
57076 #define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT (10U)
57077 /*! QTIMER2_TRM2_INPUT_SEL - QTIMER2 TMR2 input select */
57078 #define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK)
57079 
57080 #define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK (0x800U)
57081 #define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT (11U)
57082 /*! QTIMER2_TRM3_INPUT_SEL - QTIMER2 TMR3 input select */
57083 #define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK)
57084 
57085 #define IOMUXC_GPR_GPR13_DWP_MASK                (0x30000000U)
57086 #define IOMUXC_GPR_GPR13_DWP_SHIFT               (28U)
57087 /*! DWP - Domain write protection
57088  *  0b00..Both cores are allowed
57089  *  0b01..CM7 is forbidden
57090  *  0b10..CM4 is forbidden
57091  *  0b11..Both cores are forbidden
57092  */
57093 #define IOMUXC_GPR_GPR13_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_SHIFT)) & IOMUXC_GPR_GPR13_DWP_MASK)
57094 
57095 #define IOMUXC_GPR_GPR13_DWP_LOCK_MASK           (0xC0000000U)
57096 #define IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT          (30U)
57097 /*! DWP_LOCK - Domain write protection lock
57098  *  0b00..Neither of DWP bits is locked
57099  *  0b01..The lower DWP bit is locked
57100  *  0b10..The higher DWP bit is locked
57101  *  0b11..Both DWP bits are locked
57102  */
57103 #define IOMUXC_GPR_GPR13_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR13_DWP_LOCK_MASK)
57104 /*! @} */
57105 
57106 /*! @name GPR14 - GPR14 General Purpose Register */
57107 /*! @{ */
57108 
57109 #define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK (0x1U)
57110 #define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT (0U)
57111 /*! QTIMER3_TMR_CNTS_FREEZE - QTIMER3 timer counter freeze */
57112 #define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK)
57113 
57114 #define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)
57115 #define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)
57116 /*! QTIMER3_TRM0_INPUT_SEL - QTIMER3 TMR0 input select */
57117 #define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK)
57118 
57119 #define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)
57120 #define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)
57121 /*! QTIMER3_TRM1_INPUT_SEL - QTIMER3 TMR1 input select */
57122 #define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK)
57123 
57124 #define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)
57125 #define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)
57126 /*! QTIMER3_TRM2_INPUT_SEL - QTIMER3 TMR2 input select */
57127 #define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK)
57128 
57129 #define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)
57130 #define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)
57131 /*! QTIMER3_TRM3_INPUT_SEL - QTIMER3 TMR3 input select */
57132 #define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK)
57133 
57134 #define IOMUXC_GPR_GPR14_DWP_MASK                (0x30000000U)
57135 #define IOMUXC_GPR_GPR14_DWP_SHIFT               (28U)
57136 /*! DWP - Domain write protection
57137  *  0b00..Both cores are allowed
57138  *  0b01..CM7 is forbidden
57139  *  0b10..CM4 is forbidden
57140  *  0b11..Both cores are forbidden
57141  */
57142 #define IOMUXC_GPR_GPR14_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_SHIFT)) & IOMUXC_GPR_GPR14_DWP_MASK)
57143 
57144 #define IOMUXC_GPR_GPR14_DWP_LOCK_MASK           (0xC0000000U)
57145 #define IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT          (30U)
57146 /*! DWP_LOCK - Domain write protection lock
57147  *  0b00..Neither of DWP bits is locked
57148  *  0b01..The lower DWP bit is locked
57149  *  0b10..The higher DWP bit is locked
57150  *  0b11..Both DWP bits are locked
57151  */
57152 #define IOMUXC_GPR_GPR14_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR14_DWP_LOCK_MASK)
57153 /*! @} */
57154 
57155 /*! @name GPR15 - GPR15 General Purpose Register */
57156 /*! @{ */
57157 
57158 #define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK (0x1U)
57159 #define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT (0U)
57160 /*! QTIMER4_TMR_CNTS_FREEZE - QTIMER4 timer counter freeze */
57161 #define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK)
57162 
57163 #define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK (0x100U)
57164 #define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT (8U)
57165 /*! QTIMER4_TRM0_INPUT_SEL - QTIMER4 TMR0 input select */
57166 #define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK)
57167 
57168 #define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK (0x200U)
57169 #define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT (9U)
57170 /*! QTIMER4_TRM1_INPUT_SEL - QTIMER4 TMR1 input select */
57171 #define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK)
57172 
57173 #define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK (0x400U)
57174 #define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT (10U)
57175 /*! QTIMER4_TRM2_INPUT_SEL - QTIMER4 TMR2 input select */
57176 #define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK)
57177 
57178 #define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK (0x800U)
57179 #define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT (11U)
57180 /*! QTIMER4_TRM3_INPUT_SEL - QTIMER4 TMR3 input select */
57181 #define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK)
57182 
57183 #define IOMUXC_GPR_GPR15_DWP_MASK                (0x30000000U)
57184 #define IOMUXC_GPR_GPR15_DWP_SHIFT               (28U)
57185 /*! DWP - Domain write protection
57186  *  0b00..Both cores are allowed
57187  *  0b01..CM7 is forbidden
57188  *  0b10..CM4 is forbidden
57189  *  0b11..Both cores are forbidden
57190  */
57191 #define IOMUXC_GPR_GPR15_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_SHIFT)) & IOMUXC_GPR_GPR15_DWP_MASK)
57192 
57193 #define IOMUXC_GPR_GPR15_DWP_LOCK_MASK           (0xC0000000U)
57194 #define IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT          (30U)
57195 /*! DWP_LOCK - Domain write protection lock
57196  *  0b00..Neither of DWP bits is locked
57197  *  0b01..The lower DWP bit is locked
57198  *  0b10..The higher DWP bit is locked
57199  *  0b11..Both DWP bits are locked
57200  */
57201 #define IOMUXC_GPR_GPR15_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR15_DWP_LOCK_MASK)
57202 /*! @} */
57203 
57204 /*! @name GPR16 - GPR16 General Purpose Register */
57205 /*! @{ */
57206 
57207 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
57208 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
57209 /*! FLEXRAM_BANK_CFG_SEL - FlexRAM bank config source select */
57210 #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
57211 
57212 #define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK  (0x8U)
57213 #define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT (3U)
57214 /*! CM7_FORCE_HCLK_EN - CM7 platform AHB clock enable */
57215 #define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK)
57216 
57217 #define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK   (0x20U)
57218 #define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT  (5U)
57219 /*! M7_GPC_SLEEP_SEL - CM7 sleep request selection */
57220 #define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK)
57221 
57222 #define IOMUXC_GPR_GPR16_DWP_MASK                (0x30000000U)
57223 #define IOMUXC_GPR_GPR16_DWP_SHIFT               (28U)
57224 /*! DWP - Domain write protection
57225  *  0b00..Both cores are allowed
57226  *  0b01..CM7 is forbidden
57227  *  0b10..CM4 is forbidden
57228  *  0b11..Both cores are forbidden
57229  */
57230 #define IOMUXC_GPR_GPR16_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_SHIFT)) & IOMUXC_GPR_GPR16_DWP_MASK)
57231 
57232 #define IOMUXC_GPR_GPR16_DWP_LOCK_MASK           (0xC0000000U)
57233 #define IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT          (30U)
57234 /*! DWP_LOCK - Domain write protection lock
57235  *  0b00..Neither of DWP bits is locked
57236  *  0b01..The lower DWP bit is locked
57237  *  0b10..The higher DWP bit is locked
57238  *  0b11..Both DWP bits are locked
57239  */
57240 #define IOMUXC_GPR_GPR16_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR16_DWP_LOCK_MASK)
57241 /*! @} */
57242 
57243 /*! @name GPR17 - GPR17 General Purpose Register */
57244 /*! @{ */
57245 
57246 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK (0xFFFFU)
57247 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT (0U)
57248 /*! FLEXRAM_BANK_CFG_LOW - FlexRAM bank config value */
57249 #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK)
57250 
57251 #define IOMUXC_GPR_GPR17_DWP_MASK                (0x30000000U)
57252 #define IOMUXC_GPR_GPR17_DWP_SHIFT               (28U)
57253 /*! DWP - Domain write protection
57254  *  0b00..Both cores are allowed
57255  *  0b01..CM7 is forbidden
57256  *  0b10..CM4 is forbidden
57257  *  0b11..Both cores are forbidden
57258  */
57259 #define IOMUXC_GPR_GPR17_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_SHIFT)) & IOMUXC_GPR_GPR17_DWP_MASK)
57260 
57261 #define IOMUXC_GPR_GPR17_DWP_LOCK_MASK           (0xC0000000U)
57262 #define IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT          (30U)
57263 /*! DWP_LOCK - Domain write protection lock
57264  *  0b00..Neither of DWP bits is locked
57265  *  0b01..The lower DWP bit is locked
57266  *  0b10..The higher DWP bit is locked
57267  *  0b11..Both DWP bits are locked
57268  */
57269 #define IOMUXC_GPR_GPR17_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR17_DWP_LOCK_MASK)
57270 /*! @} */
57271 
57272 /*! @name GPR18 - GPR18 General Purpose Register */
57273 /*! @{ */
57274 
57275 #define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK (0xFFFFU)
57276 #define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT (0U)
57277 /*! FLEXRAM_BANK_CFG_HIGH - FlexRAM bank config value */
57278 #define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT)) & IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK)
57279 
57280 #define IOMUXC_GPR_GPR18_DWP_MASK                (0x30000000U)
57281 #define IOMUXC_GPR_GPR18_DWP_SHIFT               (28U)
57282 /*! DWP - Domain write protection
57283  *  0b00..Both cores are allowed
57284  *  0b01..CM7 is forbidden
57285  *  0b10..CM4 is forbidden
57286  *  0b11..Both cores are forbidden
57287  */
57288 #define IOMUXC_GPR_GPR18_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_SHIFT)) & IOMUXC_GPR_GPR18_DWP_MASK)
57289 
57290 #define IOMUXC_GPR_GPR18_DWP_LOCK_MASK           (0xC0000000U)
57291 #define IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT          (30U)
57292 /*! DWP_LOCK - Domain write protection lock
57293  *  0b00..Neither of DWP bits is locked
57294  *  0b01..The lower DWP bit is locked
57295  *  0b10..The higher DWP bit is locked
57296  *  0b11..Both DWP bits are locked
57297  */
57298 #define IOMUXC_GPR_GPR18_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR18_DWP_LOCK_MASK)
57299 /*! @} */
57300 
57301 /*! @name GPR20 - GPR20 General Purpose Register */
57302 /*! @{ */
57303 
57304 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK (0x1U)
57305 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT (0U)
57306 /*! IOMUXC_XBAR_DIR_SEL_4 - IOMUXC XBAR_INOUT4 function direction select */
57307 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK)
57308 
57309 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK (0x2U)
57310 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT (1U)
57311 /*! IOMUXC_XBAR_DIR_SEL_5 - IOMUXC XBAR_INOUT5 function direction select */
57312 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK)
57313 
57314 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK (0x4U)
57315 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT (2U)
57316 /*! IOMUXC_XBAR_DIR_SEL_6 - IOMUXC XBAR_INOUT6 function direction select */
57317 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK)
57318 
57319 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK (0x8U)
57320 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT (3U)
57321 /*! IOMUXC_XBAR_DIR_SEL_7 - IOMUXC XBAR_INOUT7 function direction select */
57322 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK)
57323 
57324 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK (0x10U)
57325 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT (4U)
57326 /*! IOMUXC_XBAR_DIR_SEL_8 - IOMUXC XBAR_INOUT8 function direction select */
57327 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK)
57328 
57329 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK (0x20U)
57330 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT (5U)
57331 /*! IOMUXC_XBAR_DIR_SEL_9 - IOMUXC XBAR_INOUT9 function direction select */
57332 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK)
57333 
57334 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK (0x40U)
57335 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT (6U)
57336 /*! IOMUXC_XBAR_DIR_SEL_10 - IOMUXC XBAR_INOUT10 function direction select */
57337 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK)
57338 
57339 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK (0x80U)
57340 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT (7U)
57341 /*! IOMUXC_XBAR_DIR_SEL_11 - IOMUXC XBAR_INOUT11 function direction select */
57342 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK)
57343 
57344 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK (0x100U)
57345 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT (8U)
57346 /*! IOMUXC_XBAR_DIR_SEL_12 - IOMUXC XBAR_INOUT12 function direction select */
57347 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK)
57348 
57349 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK (0x200U)
57350 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT (9U)
57351 /*! IOMUXC_XBAR_DIR_SEL_13 - IOMUXC XBAR_INOUT13 function direction select */
57352 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK)
57353 
57354 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK (0x400U)
57355 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT (10U)
57356 /*! IOMUXC_XBAR_DIR_SEL_14 - IOMUXC XBAR_INOUT14 function direction select */
57357 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK)
57358 
57359 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK (0x800U)
57360 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT (11U)
57361 /*! IOMUXC_XBAR_DIR_SEL_15 - IOMUXC XBAR_INOUT15 function direction select */
57362 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK)
57363 
57364 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK (0x1000U)
57365 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT (12U)
57366 /*! IOMUXC_XBAR_DIR_SEL_16 - IOMUXC XBAR_INOUT16 function direction select */
57367 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK)
57368 
57369 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK (0x2000U)
57370 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT (13U)
57371 /*! IOMUXC_XBAR_DIR_SEL_17 - IOMUXC XBAR_INOUT17 function direction select */
57372 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK)
57373 
57374 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK (0x4000U)
57375 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT (14U)
57376 /*! IOMUXC_XBAR_DIR_SEL_18 - IOMUXC XBAR_INOUT18 function direction select */
57377 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK)
57378 
57379 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK (0x8000U)
57380 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT (15U)
57381 /*! IOMUXC_XBAR_DIR_SEL_19 - IOMUXC XBAR_INOUT19 function direction select */
57382 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK)
57383 
57384 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK (0x10000U)
57385 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT (16U)
57386 /*! IOMUXC_XBAR_DIR_SEL_20 - IOMUXC XBAR_INOUT20 function direction select */
57387 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK)
57388 
57389 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK (0x20000U)
57390 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT (17U)
57391 /*! IOMUXC_XBAR_DIR_SEL_21 - IOMUXC XBAR_INOUT21 function direction select */
57392 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK)
57393 
57394 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK (0x40000U)
57395 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT (18U)
57396 /*! IOMUXC_XBAR_DIR_SEL_22 - IOMUXC XBAR_INOUT22 function direction select */
57397 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK)
57398 
57399 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK (0x80000U)
57400 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT (19U)
57401 /*! IOMUXC_XBAR_DIR_SEL_23 - IOMUXC XBAR_INOUT23 function direction select */
57402 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK)
57403 
57404 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK (0x100000U)
57405 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT (20U)
57406 /*! IOMUXC_XBAR_DIR_SEL_24 - IOMUXC XBAR_INOUT24 function direction select */
57407 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK)
57408 
57409 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK (0x200000U)
57410 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT (21U)
57411 /*! IOMUXC_XBAR_DIR_SEL_25 - IOMUXC XBAR_INOUT25 function direction select */
57412 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK)
57413 
57414 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK (0x400000U)
57415 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT (22U)
57416 /*! IOMUXC_XBAR_DIR_SEL_26 - IOMUXC XBAR_INOUT26 function direction select */
57417 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK)
57418 
57419 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK (0x800000U)
57420 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT (23U)
57421 /*! IOMUXC_XBAR_DIR_SEL_27 - IOMUXC XBAR_INOUT27 function direction select */
57422 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK)
57423 
57424 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK (0x1000000U)
57425 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT (24U)
57426 /*! IOMUXC_XBAR_DIR_SEL_28 - IOMUXC XBAR_INOUT28 function direction select */
57427 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK)
57428 
57429 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK (0x2000000U)
57430 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT (25U)
57431 /*! IOMUXC_XBAR_DIR_SEL_29 - IOMUXC XBAR_INOUT29 function direction select */
57432 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK)
57433 
57434 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK (0x4000000U)
57435 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT (26U)
57436 /*! IOMUXC_XBAR_DIR_SEL_30 - IOMUXC XBAR_INOUT30 function direction select */
57437 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK)
57438 
57439 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK (0x8000000U)
57440 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT (27U)
57441 /*! IOMUXC_XBAR_DIR_SEL_31 - IOMUXC XBAR_INOUT31 function direction select */
57442 #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK)
57443 
57444 #define IOMUXC_GPR_GPR20_DWP_MASK                (0x30000000U)
57445 #define IOMUXC_GPR_GPR20_DWP_SHIFT               (28U)
57446 /*! DWP - Domain write protection
57447  *  0b00..Both cores are allowed
57448  *  0b01..CM7 is forbidden
57449  *  0b10..CM4 is forbidden
57450  *  0b11..Both cores are forbidden
57451  */
57452 #define IOMUXC_GPR_GPR20_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_SHIFT)) & IOMUXC_GPR_GPR20_DWP_MASK)
57453 
57454 #define IOMUXC_GPR_GPR20_DWP_LOCK_MASK           (0xC0000000U)
57455 #define IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT          (30U)
57456 /*! DWP_LOCK - Domain write protection lock
57457  *  0b00..Neither of DWP bits is locked
57458  *  0b01..The lower DWP bit is locked
57459  *  0b10..The higher DWP bit is locked
57460  *  0b11..Both DWP bits are locked
57461  */
57462 #define IOMUXC_GPR_GPR20_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR20_DWP_LOCK_MASK)
57463 /*! @} */
57464 
57465 /*! @name GPR21 - GPR21 General Purpose Register */
57466 /*! @{ */
57467 
57468 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK (0x1U)
57469 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT (0U)
57470 /*! IOMUXC_XBAR_DIR_SEL_32 - IOMUXC XBAR_INOUT32 function direction select */
57471 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK)
57472 
57473 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK (0x2U)
57474 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT (1U)
57475 /*! IOMUXC_XBAR_DIR_SEL_33 - IOMUXC XBAR_INOUT33 function direction select */
57476 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK)
57477 
57478 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK (0x4U)
57479 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT (2U)
57480 /*! IOMUXC_XBAR_DIR_SEL_34 - IOMUXC XBAR_INOUT34 function direction select */
57481 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK)
57482 
57483 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK (0x8U)
57484 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT (3U)
57485 /*! IOMUXC_XBAR_DIR_SEL_35 - IOMUXC XBAR_INOUT35 function direction select */
57486 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK)
57487 
57488 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK (0x10U)
57489 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT (4U)
57490 /*! IOMUXC_XBAR_DIR_SEL_36 - IOMUXC XBAR_INOUT36 function direction select */
57491 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK)
57492 
57493 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK (0x20U)
57494 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT (5U)
57495 /*! IOMUXC_XBAR_DIR_SEL_37 - IOMUXC XBAR_INOUT37 function direction select */
57496 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK)
57497 
57498 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK (0x40U)
57499 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT (6U)
57500 /*! IOMUXC_XBAR_DIR_SEL_38 - IOMUXC XBAR_INOUT38 function direction select */
57501 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK)
57502 
57503 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK (0x80U)
57504 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT (7U)
57505 /*! IOMUXC_XBAR_DIR_SEL_39 - IOMUXC XBAR_INOUT39 function direction select */
57506 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK)
57507 
57508 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK (0x100U)
57509 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT (8U)
57510 /*! IOMUXC_XBAR_DIR_SEL_40 - IOMUXC XBAR_INOUT40 function direction select */
57511 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK)
57512 
57513 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK (0x200U)
57514 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT (9U)
57515 /*! IOMUXC_XBAR_DIR_SEL_41 - IOMUXC XBAR_INOUT41 function direction select */
57516 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK)
57517 
57518 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK (0x400U)
57519 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT (10U)
57520 /*! IOMUXC_XBAR_DIR_SEL_42 - IOMUXC XBAR_INOUT42 function direction select */
57521 #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK)
57522 
57523 #define IOMUXC_GPR_GPR21_DWP_MASK                (0x30000000U)
57524 #define IOMUXC_GPR_GPR21_DWP_SHIFT               (28U)
57525 /*! DWP - Domain write protection
57526  *  0b00..Both cores are allowed
57527  *  0b01..CM7 is forbidden
57528  *  0b10..CM4 is forbidden
57529  *  0b11..Both cores are forbidden
57530  */
57531 #define IOMUXC_GPR_GPR21_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_SHIFT)) & IOMUXC_GPR_GPR21_DWP_MASK)
57532 
57533 #define IOMUXC_GPR_GPR21_DWP_LOCK_MASK           (0xC0000000U)
57534 #define IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT          (30U)
57535 /*! DWP_LOCK - Domain write protection lock
57536  *  0b00..Neither of DWP bits is locked
57537  *  0b01..The lower DWP bit is locked
57538  *  0b10..The higher DWP bit is locked
57539  *  0b11..Both DWP bits are locked
57540  */
57541 #define IOMUXC_GPR_GPR21_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR21_DWP_LOCK_MASK)
57542 /*! @} */
57543 
57544 /*! @name GPR22 - GPR22 General Purpose Register */
57545 /*! @{ */
57546 
57547 #define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK    (0x1U)
57548 #define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT   (0U)
57549 /*! REF_1M_CLK_GPT1 - GPT1 1 MHz clock source select */
57550 #define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK)
57551 
57552 #define IOMUXC_GPR_GPR22_DWP_MASK                (0x30000000U)
57553 #define IOMUXC_GPR_GPR22_DWP_SHIFT               (28U)
57554 /*! DWP - Domain write protection
57555  *  0b00..Both cores are allowed
57556  *  0b01..CM7 is forbidden
57557  *  0b10..CM4 is forbidden
57558  *  0b11..Both cores are forbidden
57559  */
57560 #define IOMUXC_GPR_GPR22_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_SHIFT)) & IOMUXC_GPR_GPR22_DWP_MASK)
57561 
57562 #define IOMUXC_GPR_GPR22_DWP_LOCK_MASK           (0xC0000000U)
57563 #define IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT          (30U)
57564 /*! DWP_LOCK - Domain write protection lock
57565  *  0b00..Neither of DWP bits is locked
57566  *  0b01..The lower DWP bit is locked
57567  *  0b10..The higher DWP bit is locked
57568  *  0b11..Both DWP bits are locked
57569  */
57570 #define IOMUXC_GPR_GPR22_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR22_DWP_LOCK_MASK)
57571 /*! @} */
57572 
57573 /*! @name GPR23 - GPR23 General Purpose Register */
57574 /*! @{ */
57575 
57576 #define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK    (0x1U)
57577 #define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT   (0U)
57578 /*! REF_1M_CLK_GPT2 - GPT2 1 MHz clock source select */
57579 #define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK)
57580 
57581 #define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK    (0x2U)
57582 #define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT   (1U)
57583 /*! GPT2_CAPIN1_SEL - GPT2 input capture channel 1 source select */
57584 #define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK)
57585 
57586 #define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK    (0x4U)
57587 #define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT   (2U)
57588 /*! GPT2_CAPIN2_SEL - GPT2 input capture channel 2 source select */
57589 #define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK)
57590 
57591 #define IOMUXC_GPR_GPR23_DWP_MASK                (0x30000000U)
57592 #define IOMUXC_GPR_GPR23_DWP_SHIFT               (28U)
57593 /*! DWP - Domain write protection
57594  *  0b00..Both cores are allowed
57595  *  0b01..CM7 is forbidden
57596  *  0b10..CM4 is forbidden
57597  *  0b11..Both cores are forbidden
57598  */
57599 #define IOMUXC_GPR_GPR23_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_SHIFT)) & IOMUXC_GPR_GPR23_DWP_MASK)
57600 
57601 #define IOMUXC_GPR_GPR23_DWP_LOCK_MASK           (0xC0000000U)
57602 #define IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT          (30U)
57603 /*! DWP_LOCK - Domain write protection lock
57604  *  0b00..Neither of DWP bits is locked
57605  *  0b01..The lower DWP bit is locked
57606  *  0b10..The higher DWP bit is locked
57607  *  0b11..Both DWP bits are locked
57608  */
57609 #define IOMUXC_GPR_GPR23_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR23_DWP_LOCK_MASK)
57610 /*! @} */
57611 
57612 /*! @name GPR24 - GPR24 General Purpose Register */
57613 /*! @{ */
57614 
57615 #define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK    (0x1U)
57616 #define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT   (0U)
57617 /*! REF_1M_CLK_GPT3 - GPT3 1 MHz clock source select */
57618 #define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT)) & IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK)
57619 
57620 #define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK    (0x2U)
57621 #define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT   (1U)
57622 /*! GPT3_CAPIN1_SEL - GPT3 input capture channel 1 source select */
57623 #define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK)
57624 
57625 #define IOMUXC_GPR_GPR24_DWP_MASK                (0x30000000U)
57626 #define IOMUXC_GPR_GPR24_DWP_SHIFT               (28U)
57627 /*! DWP - Domain write protection
57628  *  0b00..Both cores are allowed
57629  *  0b01..CM7 is forbidden
57630  *  0b10..CM4 is forbidden
57631  *  0b11..Both cores are forbidden
57632  */
57633 #define IOMUXC_GPR_GPR24_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_SHIFT)) & IOMUXC_GPR_GPR24_DWP_MASK)
57634 
57635 #define IOMUXC_GPR_GPR24_DWP_LOCK_MASK           (0xC0000000U)
57636 #define IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT          (30U)
57637 /*! DWP_LOCK - Domain write protection lock
57638  *  0b00..Neither of DWP bits is locked
57639  *  0b01..The lower DWP bit is locked
57640  *  0b10..The higher DWP bit is locked
57641  *  0b11..Both DWP bits are locked
57642  */
57643 #define IOMUXC_GPR_GPR24_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR24_DWP_LOCK_MASK)
57644 /*! @} */
57645 
57646 /*! @name GPR25 - GPR25 General Purpose Register */
57647 /*! @{ */
57648 
57649 #define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK    (0x1U)
57650 #define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT   (0U)
57651 /*! REF_1M_CLK_GPT4 - GPT4 1 MHz clock source select */
57652 #define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT)) & IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK)
57653 
57654 #define IOMUXC_GPR_GPR25_DWP_MASK                (0x30000000U)
57655 #define IOMUXC_GPR_GPR25_DWP_SHIFT               (28U)
57656 /*! DWP - Domain write protection
57657  *  0b00..Both cores are allowed
57658  *  0b01..CM7 is forbidden
57659  *  0b10..CM4 is forbidden
57660  *  0b11..Both cores are forbidden
57661  */
57662 #define IOMUXC_GPR_GPR25_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_SHIFT)) & IOMUXC_GPR_GPR25_DWP_MASK)
57663 
57664 #define IOMUXC_GPR_GPR25_DWP_LOCK_MASK           (0xC0000000U)
57665 #define IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT          (30U)
57666 /*! DWP_LOCK - Domain write protection lock
57667  *  0b00..Neither of DWP bits is locked
57668  *  0b01..The lower DWP bit is locked
57669  *  0b10..The higher DWP bit is locked
57670  *  0b11..Both DWP bits are locked
57671  */
57672 #define IOMUXC_GPR_GPR25_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR25_DWP_LOCK_MASK)
57673 /*! @} */
57674 
57675 /*! @name GPR26 - GPR26 General Purpose Register */
57676 /*! @{ */
57677 
57678 #define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK    (0x1U)
57679 #define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT   (0U)
57680 /*! REF_1M_CLK_GPT5 - GPT5 1 MHz clock source select */
57681 #define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT)) & IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK)
57682 
57683 #define IOMUXC_GPR_GPR26_DWP_MASK                (0x30000000U)
57684 #define IOMUXC_GPR_GPR26_DWP_SHIFT               (28U)
57685 /*! DWP - Domain write protection
57686  *  0b00..Both cores are allowed
57687  *  0b01..CM7 is forbidden
57688  *  0b10..CM4 is forbidden
57689  *  0b11..Both cores are forbidden
57690  */
57691 #define IOMUXC_GPR_GPR26_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_SHIFT)) & IOMUXC_GPR_GPR26_DWP_MASK)
57692 
57693 #define IOMUXC_GPR_GPR26_DWP_LOCK_MASK           (0xC0000000U)
57694 #define IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT          (30U)
57695 /*! DWP_LOCK - Domain write protection lock
57696  *  0b00..Neither of DWP bits is locked
57697  *  0b01..The lower DWP bit is locked
57698  *  0b10..The higher DWP bit is locked
57699  *  0b11..Both DWP bits are locked
57700  */
57701 #define IOMUXC_GPR_GPR26_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR26_DWP_LOCK_MASK)
57702 /*! @} */
57703 
57704 /*! @name GPR27 - GPR27 General Purpose Register */
57705 /*! @{ */
57706 
57707 #define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK    (0x1U)
57708 #define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT   (0U)
57709 /*! REF_1M_CLK_GPT6 - GPT6 1 MHz clock source select */
57710 #define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT)) & IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK)
57711 
57712 #define IOMUXC_GPR_GPR27_DWP_MASK                (0x30000000U)
57713 #define IOMUXC_GPR_GPR27_DWP_SHIFT               (28U)
57714 /*! DWP - Domain write protection
57715  *  0b00..Both cores are allowed
57716  *  0b01..CM7 is forbidden
57717  *  0b10..CM4 is forbidden
57718  *  0b11..Both cores are forbidden
57719  */
57720 #define IOMUXC_GPR_GPR27_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_SHIFT)) & IOMUXC_GPR_GPR27_DWP_MASK)
57721 
57722 #define IOMUXC_GPR_GPR27_DWP_LOCK_MASK           (0xC0000000U)
57723 #define IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT          (30U)
57724 /*! DWP_LOCK - Domain write protection lock
57725  *  0b00..Neither of DWP bits is locked
57726  *  0b01..The lower DWP bit is locked
57727  *  0b10..The higher DWP bit is locked
57728  *  0b11..Both DWP bits are locked
57729  */
57730 #define IOMUXC_GPR_GPR27_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR27_DWP_LOCK_MASK)
57731 /*! @} */
57732 
57733 /*! @name GPR28 - GPR28 General Purpose Register */
57734 /*! @{ */
57735 
57736 #define IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK      (0x1U)
57737 #define IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT     (0U)
57738 /*! ARCACHE_USDHC - uSDHC block cacheable attribute value of AXI read transactions */
57739 #define IOMUXC_GPR_GPR28_ARCACHE_USDHC(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK)
57740 
57741 #define IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK      (0x2U)
57742 #define IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT     (1U)
57743 /*! AWCACHE_USDHC - uSDHC block cacheable attribute value of AXI write transactions */
57744 #define IOMUXC_GPR_GPR28_AWCACHE_USDHC(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK)
57745 
57746 #define IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK       (0x20U)
57747 #define IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT      (5U)
57748 #define IOMUXC_GPR_GPR28_CACHE_ENET1G(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK)
57749 
57750 #define IOMUXC_GPR_GPR28_CACHE_ENET_MASK         (0x80U)
57751 #define IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT        (7U)
57752 /*! CACHE_ENET - ENET block cacheable attribute value of AXI transactions */
57753 #define IOMUXC_GPR_GPR28_CACHE_ENET(x)           (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET_MASK)
57754 
57755 #define IOMUXC_GPR_GPR28_CACHE_USB_MASK          (0x2000U)
57756 #define IOMUXC_GPR_GPR28_CACHE_USB_SHIFT         (13U)
57757 /*! CACHE_USB - USB block cacheable attribute value of AXI transactions */
57758 #define IOMUXC_GPR_GPR28_CACHE_USB(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_USB_MASK)
57759 
57760 #define IOMUXC_GPR_GPR28_DWP_MASK                (0x30000000U)
57761 #define IOMUXC_GPR_GPR28_DWP_SHIFT               (28U)
57762 /*! DWP - Domain write protection
57763  *  0b00..Both cores are allowed
57764  *  0b01..CM7 is forbidden
57765  *  0b10..CM4 is forbidden
57766  *  0b11..Both cores are forbidden
57767  */
57768 #define IOMUXC_GPR_GPR28_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_SHIFT)) & IOMUXC_GPR_GPR28_DWP_MASK)
57769 
57770 #define IOMUXC_GPR_GPR28_DWP_LOCK_MASK           (0xC0000000U)
57771 #define IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT          (30U)
57772 /*! DWP_LOCK - Domain write protection lock
57773  *  0b00..Neither of DWP bits is locked
57774  *  0b01..The lower DWP bit is locked
57775  *  0b10..The higher DWP bit is locked
57776  *  0b11..Both DWP bits are locked
57777  */
57778 #define IOMUXC_GPR_GPR28_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR28_DWP_LOCK_MASK)
57779 /*! @} */
57780 
57781 /*! @name GPR29 - GPR29 General Purpose Register */
57782 /*! @{ */
57783 
57784 #define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK (0x1U)
57785 #define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT (0U)
57786 /*! USBPHY1_IPG_CLK_ACTIVE - USBPHY1 register access clock enable */
57787 #define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK)
57788 
57789 #define IOMUXC_GPR_GPR29_DWP_MASK                (0x30000000U)
57790 #define IOMUXC_GPR_GPR29_DWP_SHIFT               (28U)
57791 /*! DWP - Domain write protection
57792  *  0b00..Both cores are allowed
57793  *  0b01..CM7 is forbidden
57794  *  0b10..CM4 is forbidden
57795  *  0b11..Both cores are forbidden
57796  */
57797 #define IOMUXC_GPR_GPR29_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_SHIFT)) & IOMUXC_GPR_GPR29_DWP_MASK)
57798 
57799 #define IOMUXC_GPR_GPR29_DWP_LOCK_MASK           (0xC0000000U)
57800 #define IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT          (30U)
57801 /*! DWP_LOCK - Domain write protection lock
57802  *  0b00..Neither of DWP bits is locked
57803  *  0b01..The lower DWP bit is locked
57804  *  0b10..The higher DWP bit is locked
57805  *  0b11..Both DWP bits are locked
57806  */
57807 #define IOMUXC_GPR_GPR29_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR29_DWP_LOCK_MASK)
57808 /*! @} */
57809 
57810 /*! @name GPR30 - GPR30 General Purpose Register */
57811 /*! @{ */
57812 
57813 #define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK (0x1U)
57814 #define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT (0U)
57815 /*! USBPHY2_IPG_CLK_ACTIVE - USBPHY2 register access clock enable */
57816 #define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK)
57817 
57818 #define IOMUXC_GPR_GPR30_DWP_MASK                (0x30000000U)
57819 #define IOMUXC_GPR_GPR30_DWP_SHIFT               (28U)
57820 /*! DWP - Domain write protection
57821  *  0b00..Both cores are allowed
57822  *  0b01..CM7 is forbidden
57823  *  0b10..CM4 is forbidden
57824  *  0b11..Both cores are forbidden
57825  */
57826 #define IOMUXC_GPR_GPR30_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_SHIFT)) & IOMUXC_GPR_GPR30_DWP_MASK)
57827 
57828 #define IOMUXC_GPR_GPR30_DWP_LOCK_MASK           (0xC0000000U)
57829 #define IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT          (30U)
57830 /*! DWP_LOCK - Domain write protection lock
57831  *  0b00..Neither of DWP bits is locked
57832  *  0b01..The lower DWP bit is locked
57833  *  0b10..The higher DWP bit is locked
57834  *  0b11..Both DWP bits are locked
57835  */
57836 #define IOMUXC_GPR_GPR30_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR30_DWP_LOCK_MASK)
57837 /*! @} */
57838 
57839 /*! @name GPR31 - GPR31 General Purpose Register */
57840 /*! @{ */
57841 
57842 #define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK (0x1U)
57843 #define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT (0U)
57844 /*! RMW2_WAIT_BVALID_CPL - OCRAM M7 RMW wait enable */
57845 #define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK)
57846 
57847 #define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK (0x4U)
57848 #define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT (2U)
57849 /*! OCRAM_M7_CLK_GATING - OCRAM M7 clock gating enable */
57850 #define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT)) & IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK)
57851 
57852 #define IOMUXC_GPR_GPR31_DWP_MASK                (0x30000000U)
57853 #define IOMUXC_GPR_GPR31_DWP_SHIFT               (28U)
57854 /*! DWP - Domain write protection
57855  *  0b00..Both cores are allowed
57856  *  0b01..CM7 is forbidden
57857  *  0b10..CM4 is forbidden
57858  *  0b11..Both cores are forbidden
57859  */
57860 #define IOMUXC_GPR_GPR31_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_SHIFT)) & IOMUXC_GPR_GPR31_DWP_MASK)
57861 
57862 #define IOMUXC_GPR_GPR31_DWP_LOCK_MASK           (0xC0000000U)
57863 #define IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT          (30U)
57864 /*! DWP_LOCK - Domain write protection lock
57865  *  0b00..Neither of DWP bits is locked
57866  *  0b01..The lower DWP bit is locked
57867  *  0b10..The higher DWP bit is locked
57868  *  0b11..Both DWP bits are locked
57869  */
57870 #define IOMUXC_GPR_GPR31_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR31_DWP_LOCK_MASK)
57871 /*! @} */
57872 
57873 /*! @name GPR32 - GPR32 General Purpose Register */
57874 /*! @{ */
57875 
57876 #define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK (0x1U)
57877 #define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT (0U)
57878 /*! RMW1_WAIT_BVALID_CPL - OCRAM1 RMW wait enable */
57879 #define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK)
57880 
57881 #define IOMUXC_GPR_GPR32_DWP_MASK                (0x30000000U)
57882 #define IOMUXC_GPR_GPR32_DWP_SHIFT               (28U)
57883 /*! DWP - Domain write protection
57884  *  0b00..Both cores are allowed
57885  *  0b01..CM7 is forbidden
57886  *  0b10..CM4 is forbidden
57887  *  0b11..Both cores are forbidden
57888  */
57889 #define IOMUXC_GPR_GPR32_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_SHIFT)) & IOMUXC_GPR_GPR32_DWP_MASK)
57890 
57891 #define IOMUXC_GPR_GPR32_DWP_LOCK_MASK           (0xC0000000U)
57892 #define IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT          (30U)
57893 /*! DWP_LOCK - Domain write protection lock
57894  *  0b00..Neither of DWP bits is locked
57895  *  0b01..The lower DWP bit is locked
57896  *  0b10..The higher DWP bit is locked
57897  *  0b11..Both DWP bits are locked
57898  */
57899 #define IOMUXC_GPR_GPR32_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR32_DWP_LOCK_MASK)
57900 /*! @} */
57901 
57902 /*! @name GPR33 - GPR33 General Purpose Register */
57903 /*! @{ */
57904 
57905 #define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK (0x1U)
57906 #define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT (0U)
57907 /*! RMW2_WAIT_BVALID_CPL - OCRAM2 RMW wait enable */
57908 #define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK)
57909 
57910 #define IOMUXC_GPR_GPR33_DWP_MASK                (0x30000000U)
57911 #define IOMUXC_GPR_GPR33_DWP_SHIFT               (28U)
57912 /*! DWP - Domain write protection
57913  *  0b00..Both cores are allowed
57914  *  0b01..CM7 is forbidden
57915  *  0b10..CM4 is forbidden
57916  *  0b11..Both cores are forbidden
57917  */
57918 #define IOMUXC_GPR_GPR33_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_SHIFT)) & IOMUXC_GPR_GPR33_DWP_MASK)
57919 
57920 #define IOMUXC_GPR_GPR33_DWP_LOCK_MASK           (0xC0000000U)
57921 #define IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT          (30U)
57922 /*! DWP_LOCK - Domain write protection lock
57923  *  0b00..Neither of DWP bits is locked
57924  *  0b01..The lower DWP bit is locked
57925  *  0b10..The higher DWP bit is locked
57926  *  0b11..Both DWP bits are locked
57927  */
57928 #define IOMUXC_GPR_GPR33_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR33_DWP_LOCK_MASK)
57929 /*! @} */
57930 
57931 /*! @name GPR34 - GPR34 General Purpose Register */
57932 /*! @{ */
57933 
57934 #define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK (0x1U)
57935 #define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT (0U)
57936 /*! XECC_FLEXSPI1_WAIT_BVALID_CPL - XECC_FLEXSPI1 RMW wait enable */
57937 #define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK)
57938 
57939 #define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK  (0x2U)
57940 #define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT (1U)
57941 /*! FLEXSPI1_OTFAD_EN - FlexSPI1 OTFAD enable */
57942 #define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK)
57943 
57944 #define IOMUXC_GPR_GPR34_DWP_MASK                (0x30000000U)
57945 #define IOMUXC_GPR_GPR34_DWP_SHIFT               (28U)
57946 /*! DWP - Domain write protection
57947  *  0b00..Both cores are allowed
57948  *  0b01..CM7 is forbidden
57949  *  0b10..CM4 is forbidden
57950  *  0b11..Both cores are forbidden
57951  */
57952 #define IOMUXC_GPR_GPR34_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_SHIFT)) & IOMUXC_GPR_GPR34_DWP_MASK)
57953 
57954 #define IOMUXC_GPR_GPR34_DWP_LOCK_MASK           (0xC0000000U)
57955 #define IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT          (30U)
57956 /*! DWP_LOCK - Domain write protection lock
57957  *  0b00..Neither of DWP bits is locked
57958  *  0b01..The lower DWP bit is locked
57959  *  0b10..The higher DWP bit is locked
57960  *  0b11..Both DWP bits are locked
57961  */
57962 #define IOMUXC_GPR_GPR34_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR34_DWP_LOCK_MASK)
57963 /*! @} */
57964 
57965 /*! @name GPR35 - GPR35 General Purpose Register */
57966 /*! @{ */
57967 
57968 #define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK (0x1U)
57969 #define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT (0U)
57970 /*! XECC_FLEXSPI2_WAIT_BVALID_CPL - XECC_FLEXSPI2 RMW wait enable */
57971 #define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK)
57972 
57973 #define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK  (0x2U)
57974 #define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT (1U)
57975 /*! FLEXSPI2_OTFAD_EN - FlexSPI2 OTFAD enable */
57976 #define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK)
57977 
57978 #define IOMUXC_GPR_GPR35_DWP_MASK                (0x30000000U)
57979 #define IOMUXC_GPR_GPR35_DWP_SHIFT               (28U)
57980 /*! DWP - Domain write protection
57981  *  0b00..Both cores are allowed
57982  *  0b01..CM7 is forbidden
57983  *  0b10..CM4 is forbidden
57984  *  0b11..Both cores are forbidden
57985  */
57986 #define IOMUXC_GPR_GPR35_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_SHIFT)) & IOMUXC_GPR_GPR35_DWP_MASK)
57987 
57988 #define IOMUXC_GPR_GPR35_DWP_LOCK_MASK           (0xC0000000U)
57989 #define IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT          (30U)
57990 /*! DWP_LOCK - Domain write protection lock
57991  *  0b00..Neither of DWP bits is locked
57992  *  0b01..The lower DWP bit is locked
57993  *  0b10..The higher DWP bit is locked
57994  *  0b11..Both DWP bits are locked
57995  */
57996 #define IOMUXC_GPR_GPR35_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR35_DWP_LOCK_MASK)
57997 /*! @} */
57998 
57999 /*! @name GPR36 - GPR36 General Purpose Register */
58000 /*! @{ */
58001 
58002 #define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK (0x1U)
58003 #define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT (0U)
58004 /*! XECC_SEMC_WAIT_BVALID_CPL - XECC_SEMC RMW wait enable */
58005 #define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK)
58006 
58007 #define IOMUXC_GPR_GPR36_DWP_MASK                (0x30000000U)
58008 #define IOMUXC_GPR_GPR36_DWP_SHIFT               (28U)
58009 /*! DWP - Domain write protection
58010  *  0b00..Both cores are allowed
58011  *  0b01..CM7 is forbidden
58012  *  0b10..CM4 is forbidden
58013  *  0b11..Both cores are forbidden
58014  */
58015 #define IOMUXC_GPR_GPR36_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_SHIFT)) & IOMUXC_GPR_GPR36_DWP_MASK)
58016 
58017 #define IOMUXC_GPR_GPR36_DWP_LOCK_MASK           (0xC0000000U)
58018 #define IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT          (30U)
58019 /*! DWP_LOCK - Domain write protection lock
58020  *  0b00..Neither of DWP bits is locked
58021  *  0b01..The lower DWP bit is locked
58022  *  0b10..The higher DWP bit is locked
58023  *  0b11..Both DWP bits are locked
58024  */
58025 #define IOMUXC_GPR_GPR36_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR36_DWP_LOCK_MASK)
58026 /*! @} */
58027 
58028 /*! @name GPR37 - GPR37 General Purpose Register */
58029 /*! @{ */
58030 
58031 #define IOMUXC_GPR_GPR37_NIDEN_MASK              (0x1U)
58032 #define IOMUXC_GPR_GPR37_NIDEN_SHIFT             (0U)
58033 /*! NIDEN - ARM non-secure (non-invasive) debug enable */
58034 #define IOMUXC_GPR_GPR37_NIDEN(x)                (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_NIDEN_SHIFT)) & IOMUXC_GPR_GPR37_NIDEN_MASK)
58035 
58036 #define IOMUXC_GPR_GPR37_DBG_EN_MASK             (0x2U)
58037 #define IOMUXC_GPR_GPR37_DBG_EN_SHIFT            (1U)
58038 /*! DBG_EN - ARM invasive debug enable */
58039 #define IOMUXC_GPR_GPR37_DBG_EN(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR37_DBG_EN_MASK)
58040 
58041 #define IOMUXC_GPR_GPR37_EXC_MON_MASK            (0x8U)
58042 #define IOMUXC_GPR_GPR37_EXC_MON_SHIFT           (3U)
58043 /*! EXC_MON - Exclusive monitor response select of illegal command */
58044 #define IOMUXC_GPR_GPR37_EXC_MON(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR37_EXC_MON_MASK)
58045 
58046 #define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK    (0x20U)
58047 #define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT   (5U)
58048 /*! M7_DBG_ACK_MASK - CM7 debug halt mask */
58049 #define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK)
58050 
58051 #define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK    (0x40U)
58052 #define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT   (6U)
58053 /*! M4_DBG_ACK_MASK - CM4 debug halt mask */
58054 #define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK)
58055 
58056 #define IOMUXC_GPR_GPR37_DWP_MASK                (0x30000000U)
58057 #define IOMUXC_GPR_GPR37_DWP_SHIFT               (28U)
58058 /*! DWP - Domain write protection
58059  *  0b00..Both cores are allowed
58060  *  0b01..CM7 is forbidden
58061  *  0b10..CM4 is forbidden
58062  *  0b11..Both cores are forbidden
58063  */
58064 #define IOMUXC_GPR_GPR37_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_SHIFT)) & IOMUXC_GPR_GPR37_DWP_MASK)
58065 
58066 #define IOMUXC_GPR_GPR37_DWP_LOCK_MASK           (0xC0000000U)
58067 #define IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT          (30U)
58068 /*! DWP_LOCK - Domain write protection lock
58069  *  0b00..Neither of DWP bits is locked
58070  *  0b01..The lower DWP bit is locked
58071  *  0b10..The higher DWP bit is locked
58072  *  0b11..Both DWP bits are locked
58073  */
58074 #define IOMUXC_GPR_GPR37_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR37_DWP_LOCK_MASK)
58075 /*! @} */
58076 
58077 /*! @name GPR38 - GPR38 General Purpose Register */
58078 /*! @{ */
58079 
58080 #define IOMUXC_GPR_GPR38_DWP_MASK                (0x30000000U)
58081 #define IOMUXC_GPR_GPR38_DWP_SHIFT               (28U)
58082 /*! DWP - Domain write protection
58083  *  0b00..Both cores are allowed
58084  *  0b01..CM7 is forbidden
58085  *  0b10..CM4 is forbidden
58086  *  0b11..Both cores are forbidden
58087  */
58088 #define IOMUXC_GPR_GPR38_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_SHIFT)) & IOMUXC_GPR_GPR38_DWP_MASK)
58089 
58090 #define IOMUXC_GPR_GPR38_DWP_LOCK_MASK           (0xC0000000U)
58091 #define IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT          (30U)
58092 /*! DWP_LOCK - Domain write protection lock
58093  *  0b00..Neither of DWP bits is locked
58094  *  0b01..The lower DWP bit is locked
58095  *  0b10..The higher DWP bit is locked
58096  *  0b11..Both DWP bits are locked
58097  */
58098 #define IOMUXC_GPR_GPR38_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR38_DWP_LOCK_MASK)
58099 /*! @} */
58100 
58101 /*! @name GPR39 - GPR39 General Purpose Register */
58102 /*! @{ */
58103 
58104 #define IOMUXC_GPR_GPR39_DWP_MASK                (0x30000000U)
58105 #define IOMUXC_GPR_GPR39_DWP_SHIFT               (28U)
58106 /*! DWP - Domain write protection
58107  *  0b00..Both cores are allowed
58108  *  0b01..CM7 is forbidden
58109  *  0b10..CM4 is forbidden
58110  *  0b11..Both cores are forbidden
58111  */
58112 #define IOMUXC_GPR_GPR39_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_SHIFT)) & IOMUXC_GPR_GPR39_DWP_MASK)
58113 
58114 #define IOMUXC_GPR_GPR39_DWP_LOCK_MASK           (0xC0000000U)
58115 #define IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT          (30U)
58116 /*! DWP_LOCK - Domain write protection lock
58117  *  0b00..Neither of DWP bits is locked
58118  *  0b01..The lower DWP bit is locked
58119  *  0b10..The higher DWP bit is locked
58120  *  0b11..Both DWP bits are locked
58121  */
58122 #define IOMUXC_GPR_GPR39_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR39_DWP_LOCK_MASK)
58123 /*! @} */
58124 
58125 /*! @name GPR40 - GPR40 General Purpose Register */
58126 /*! @{ */
58127 
58128 #define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK (0xFFFFU)
58129 #define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT (0U)
58130 /*! GPIO_MUX2_GPIO_SEL_LOW - GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function. */
58131 #define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK)
58132 
58133 #define IOMUXC_GPR_GPR40_DWP_MASK                (0x30000000U)
58134 #define IOMUXC_GPR_GPR40_DWP_SHIFT               (28U)
58135 /*! DWP - Domain write protection
58136  *  0b00..Both cores are allowed
58137  *  0b01..CM7 is forbidden
58138  *  0b10..CM4 is forbidden
58139  *  0b11..Both cores are forbidden
58140  */
58141 #define IOMUXC_GPR_GPR40_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_SHIFT)) & IOMUXC_GPR_GPR40_DWP_MASK)
58142 
58143 #define IOMUXC_GPR_GPR40_DWP_LOCK_MASK           (0xC0000000U)
58144 #define IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT          (30U)
58145 /*! DWP_LOCK - Domain write protection lock
58146  *  0b00..Neither of DWP bits is locked
58147  *  0b01..The lower DWP bit is locked
58148  *  0b10..The higher DWP bit is locked
58149  *  0b11..Both DWP bits are locked
58150  */
58151 #define IOMUXC_GPR_GPR40_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR40_DWP_LOCK_MASK)
58152 /*! @} */
58153 
58154 /*! @name GPR41 - GPR41 General Purpose Register */
58155 /*! @{ */
58156 
58157 #define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK (0xFFFFU)
58158 #define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT (0U)
58159 /*! GPIO_MUX2_GPIO_SEL_HIGH - GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function. */
58160 #define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK)
58161 
58162 #define IOMUXC_GPR_GPR41_DWP_MASK                (0x30000000U)
58163 #define IOMUXC_GPR_GPR41_DWP_SHIFT               (28U)
58164 /*! DWP - Domain write protection
58165  *  0b00..Both cores are allowed
58166  *  0b01..CM7 is forbidden
58167  *  0b10..CM4 is forbidden
58168  *  0b11..Both cores are forbidden
58169  */
58170 #define IOMUXC_GPR_GPR41_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_SHIFT)) & IOMUXC_GPR_GPR41_DWP_MASK)
58171 
58172 #define IOMUXC_GPR_GPR41_DWP_LOCK_MASK           (0xC0000000U)
58173 #define IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT          (30U)
58174 /*! DWP_LOCK - Domain write protection lock
58175  *  0b00..Neither of DWP bits is locked
58176  *  0b01..The lower DWP bit is locked
58177  *  0b10..The higher DWP bit is locked
58178  *  0b11..Both DWP bits are locked
58179  */
58180 #define IOMUXC_GPR_GPR41_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR41_DWP_LOCK_MASK)
58181 /*! @} */
58182 
58183 /*! @name GPR42 - GPR42 General Purpose Register */
58184 /*! @{ */
58185 
58186 #define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK (0xFFFFU)
58187 #define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT (0U)
58188 /*! GPIO_MUX3_GPIO_SEL_LOW - GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function. */
58189 #define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK)
58190 
58191 #define IOMUXC_GPR_GPR42_DWP_MASK                (0x30000000U)
58192 #define IOMUXC_GPR_GPR42_DWP_SHIFT               (28U)
58193 /*! DWP - Domain write protection
58194  *  0b00..Both cores are allowed
58195  *  0b01..CM7 is forbidden
58196  *  0b10..CM4 is forbidden
58197  *  0b11..Both cores are forbidden
58198  */
58199 #define IOMUXC_GPR_GPR42_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_SHIFT)) & IOMUXC_GPR_GPR42_DWP_MASK)
58200 
58201 #define IOMUXC_GPR_GPR42_DWP_LOCK_MASK           (0xC0000000U)
58202 #define IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT          (30U)
58203 /*! DWP_LOCK - Domain write protection lock
58204  *  0b00..Neither of DWP bits is locked
58205  *  0b01..The lower DWP bit is locked
58206  *  0b10..The higher DWP bit is locked
58207  *  0b11..Both DWP bits are locked
58208  */
58209 #define IOMUXC_GPR_GPR42_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR42_DWP_LOCK_MASK)
58210 /*! @} */
58211 
58212 /*! @name GPR43 - GPR43 General Purpose Register */
58213 /*! @{ */
58214 
58215 #define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK (0xFFFFU)
58216 #define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT (0U)
58217 /*! GPIO_MUX3_GPIO_SEL_HIGH - GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function. */
58218 #define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK)
58219 
58220 #define IOMUXC_GPR_GPR43_DWP_MASK                (0x30000000U)
58221 #define IOMUXC_GPR_GPR43_DWP_SHIFT               (28U)
58222 /*! DWP - Domain write protection
58223  *  0b00..Both cores are allowed
58224  *  0b01..CM7 is forbidden
58225  *  0b10..CM4 is forbidden
58226  *  0b11..Both cores are forbidden
58227  */
58228 #define IOMUXC_GPR_GPR43_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_SHIFT)) & IOMUXC_GPR_GPR43_DWP_MASK)
58229 
58230 #define IOMUXC_GPR_GPR43_DWP_LOCK_MASK           (0xC0000000U)
58231 #define IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT          (30U)
58232 /*! DWP_LOCK - Domain write protection lock
58233  *  0b00..Neither of DWP bits is locked
58234  *  0b01..The lower DWP bit is locked
58235  *  0b10..The higher DWP bit is locked
58236  *  0b11..Both DWP bits are locked
58237  */
58238 #define IOMUXC_GPR_GPR43_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR43_DWP_LOCK_MASK)
58239 /*! @} */
58240 
58241 /*! @name GPR44 - GPR44 General Purpose Register */
58242 /*! @{ */
58243 
58244 #define IOMUXC_GPR_GPR44_DWP_MASK                (0x30000000U)
58245 #define IOMUXC_GPR_GPR44_DWP_SHIFT               (28U)
58246 /*! DWP - Domain write protection
58247  *  0b00..Both cores are allowed
58248  *  0b01..CM7 is forbidden
58249  *  0b10..CM4 is forbidden
58250  *  0b11..Both cores are forbidden
58251  */
58252 #define IOMUXC_GPR_GPR44_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_SHIFT)) & IOMUXC_GPR_GPR44_DWP_MASK)
58253 
58254 #define IOMUXC_GPR_GPR44_DWP_LOCK_MASK           (0xC0000000U)
58255 #define IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT          (30U)
58256 /*! DWP_LOCK - Domain write protection lock
58257  *  0b00..Neither of DWP bits is locked
58258  *  0b01..The lower DWP bit is locked
58259  *  0b10..The higher DWP bit is locked
58260  *  0b11..Both DWP bits are locked
58261  */
58262 #define IOMUXC_GPR_GPR44_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR44_DWP_LOCK_MASK)
58263 /*! @} */
58264 
58265 /*! @name GPR45 - GPR45 General Purpose Register */
58266 /*! @{ */
58267 
58268 #define IOMUXC_GPR_GPR45_DWP_MASK                (0x30000000U)
58269 #define IOMUXC_GPR_GPR45_DWP_SHIFT               (28U)
58270 /*! DWP - Domain write protection
58271  *  0b00..Both cores are allowed
58272  *  0b01..CM7 is forbidden
58273  *  0b10..CM4 is forbidden
58274  *  0b11..Both cores are forbidden
58275  */
58276 #define IOMUXC_GPR_GPR45_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_SHIFT)) & IOMUXC_GPR_GPR45_DWP_MASK)
58277 
58278 #define IOMUXC_GPR_GPR45_DWP_LOCK_MASK           (0xC0000000U)
58279 #define IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT          (30U)
58280 /*! DWP_LOCK - Domain write protection lock
58281  *  0b00..Neither of DWP bits is locked
58282  *  0b01..The lower DWP bit is locked
58283  *  0b10..The higher DWP bit is locked
58284  *  0b11..Both DWP bits are locked
58285  */
58286 #define IOMUXC_GPR_GPR45_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR45_DWP_LOCK_MASK)
58287 /*! @} */
58288 
58289 /*! @name GPR46 - GPR46 General Purpose Register */
58290 /*! @{ */
58291 
58292 #define IOMUXC_GPR_GPR46_DWP_MASK                (0x30000000U)
58293 #define IOMUXC_GPR_GPR46_DWP_SHIFT               (28U)
58294 /*! DWP - Domain write protection
58295  *  0b00..Both cores are allowed
58296  *  0b01..CM7 is forbidden
58297  *  0b10..CM4 is forbidden
58298  *  0b11..Both cores are forbidden
58299  */
58300 #define IOMUXC_GPR_GPR46_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_SHIFT)) & IOMUXC_GPR_GPR46_DWP_MASK)
58301 
58302 #define IOMUXC_GPR_GPR46_DWP_LOCK_MASK           (0xC0000000U)
58303 #define IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT          (30U)
58304 /*! DWP_LOCK - Domain write protection lock
58305  *  0b00..Neither of DWP bits is locked
58306  *  0b01..The lower DWP bit is locked
58307  *  0b10..The higher DWP bit is locked
58308  *  0b11..Both DWP bits are locked
58309  */
58310 #define IOMUXC_GPR_GPR46_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR46_DWP_LOCK_MASK)
58311 /*! @} */
58312 
58313 /*! @name GPR47 - GPR47 General Purpose Register */
58314 /*! @{ */
58315 
58316 #define IOMUXC_GPR_GPR47_DWP_MASK                (0x30000000U)
58317 #define IOMUXC_GPR_GPR47_DWP_SHIFT               (28U)
58318 /*! DWP - Domain write protection
58319  *  0b00..Both cores are allowed
58320  *  0b01..CM7 is forbidden
58321  *  0b10..CM4 is forbidden
58322  *  0b11..Both cores are forbidden
58323  */
58324 #define IOMUXC_GPR_GPR47_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_SHIFT)) & IOMUXC_GPR_GPR47_DWP_MASK)
58325 
58326 #define IOMUXC_GPR_GPR47_DWP_LOCK_MASK           (0xC0000000U)
58327 #define IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT          (30U)
58328 /*! DWP_LOCK - Domain write protection lock
58329  *  0b00..Neither of DWP bits is locked
58330  *  0b01..The lower DWP bit is locked
58331  *  0b10..The higher DWP bit is locked
58332  *  0b11..Both DWP bits are locked
58333  */
58334 #define IOMUXC_GPR_GPR47_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR47_DWP_LOCK_MASK)
58335 /*! @} */
58336 
58337 /*! @name GPR48 - GPR48 General Purpose Register */
58338 /*! @{ */
58339 
58340 #define IOMUXC_GPR_GPR48_DWP_MASK                (0x30000000U)
58341 #define IOMUXC_GPR_GPR48_DWP_SHIFT               (28U)
58342 /*! DWP - Domain write protection
58343  *  0b00..Both cores are allowed
58344  *  0b01..CM7 is forbidden
58345  *  0b10..CM4 is forbidden
58346  *  0b11..Both cores are forbidden
58347  */
58348 #define IOMUXC_GPR_GPR48_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_SHIFT)) & IOMUXC_GPR_GPR48_DWP_MASK)
58349 
58350 #define IOMUXC_GPR_GPR48_DWP_LOCK_MASK           (0xC0000000U)
58351 #define IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT          (30U)
58352 /*! DWP_LOCK - Domain write protection lock
58353  *  0b00..Neither of DWP bits is locked
58354  *  0b01..The lower DWP bit is locked
58355  *  0b10..The higher DWP bit is locked
58356  *  0b11..Both DWP bits are locked
58357  */
58358 #define IOMUXC_GPR_GPR48_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR48_DWP_LOCK_MASK)
58359 /*! @} */
58360 
58361 /*! @name GPR49 - GPR49 General Purpose Register */
58362 /*! @{ */
58363 
58364 #define IOMUXC_GPR_GPR49_DWP_MASK                (0x30000000U)
58365 #define IOMUXC_GPR_GPR49_DWP_SHIFT               (28U)
58366 /*! DWP - Domain write protection
58367  *  0b00..Both cores are allowed
58368  *  0b01..CM7 is forbidden
58369  *  0b10..CM4 is forbidden
58370  *  0b11..Both cores are forbidden
58371  */
58372 #define IOMUXC_GPR_GPR49_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_SHIFT)) & IOMUXC_GPR_GPR49_DWP_MASK)
58373 
58374 #define IOMUXC_GPR_GPR49_DWP_LOCK_MASK           (0xC0000000U)
58375 #define IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT          (30U)
58376 /*! DWP_LOCK - Domain write protection lock
58377  *  0b00..Neither of DWP bits is locked
58378  *  0b01..The lower DWP bit is locked
58379  *  0b10..The higher DWP bit is locked
58380  *  0b11..Both DWP bits are locked
58381  */
58382 #define IOMUXC_GPR_GPR49_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR49_DWP_LOCK_MASK)
58383 /*! @} */
58384 
58385 /*! @name GPR50 - GPR50 General Purpose Register */
58386 /*! @{ */
58387 
58388 #define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK       (0x1FU)
58389 #define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT      (0U)
58390 /*! CAAM_IPS_MGR - CAAM manager processor identifier */
58391 #define IOMUXC_GPR_GPR50_CAAM_IPS_MGR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT)) & IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK)
58392 
58393 #define IOMUXC_GPR_GPR50_DWP_MASK                (0x30000000U)
58394 #define IOMUXC_GPR_GPR50_DWP_SHIFT               (28U)
58395 /*! DWP - Domain write protection
58396  *  0b00..Both cores are allowed
58397  *  0b01..CM7 is forbidden
58398  *  0b10..CM4 is forbidden
58399  *  0b11..Both cores are forbidden
58400  */
58401 #define IOMUXC_GPR_GPR50_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_SHIFT)) & IOMUXC_GPR_GPR50_DWP_MASK)
58402 
58403 #define IOMUXC_GPR_GPR50_DWP_LOCK_MASK           (0xC0000000U)
58404 #define IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT          (30U)
58405 /*! DWP_LOCK - Domain write protection lock
58406  *  0b00..Neither of DWP bits is locked
58407  *  0b01..The lower DWP bit is locked
58408  *  0b10..The higher DWP bit is locked
58409  *  0b11..Both DWP bits are locked
58410  */
58411 #define IOMUXC_GPR_GPR50_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR50_DWP_LOCK_MASK)
58412 /*! @} */
58413 
58414 /*! @name GPR51 - GPR51 General Purpose Register */
58415 /*! @{ */
58416 
58417 #define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK       (0x1U)
58418 #define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT      (0U)
58419 /*! M7_NMI_CLEAR - Clear CM7 NMI holding register */
58420 #define IOMUXC_GPR_GPR51_M7_NMI_CLEAR(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT)) & IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK)
58421 
58422 #define IOMUXC_GPR_GPR51_DWP_MASK                (0x30000000U)
58423 #define IOMUXC_GPR_GPR51_DWP_SHIFT               (28U)
58424 /*! DWP - Domain write protection
58425  *  0b00..Both cores are allowed
58426  *  0b01..CM7 is forbidden
58427  *  0b10..CM4 is forbidden
58428  *  0b11..Both cores are forbidden
58429  */
58430 #define IOMUXC_GPR_GPR51_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_SHIFT)) & IOMUXC_GPR_GPR51_DWP_MASK)
58431 
58432 #define IOMUXC_GPR_GPR51_DWP_LOCK_MASK           (0xC0000000U)
58433 #define IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT          (30U)
58434 /*! DWP_LOCK - Domain write protection lock
58435  *  0b00..Neither of DWP bits is locked
58436  *  0b01..The lower DWP bit is locked
58437  *  0b10..The higher DWP bit is locked
58438  *  0b11..Both DWP bits are locked
58439  */
58440 #define IOMUXC_GPR_GPR51_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR51_DWP_LOCK_MASK)
58441 /*! @} */
58442 
58443 /*! @name GPR52 - GPR52 General Purpose Register */
58444 /*! @{ */
58445 
58446 #define IOMUXC_GPR_GPR52_DWP_MASK                (0x30000000U)
58447 #define IOMUXC_GPR_GPR52_DWP_SHIFT               (28U)
58448 /*! DWP - Domain write protection
58449  *  0b00..Both cores are allowed
58450  *  0b01..CM7 is forbidden
58451  *  0b10..CM4 is forbidden
58452  *  0b11..Both cores are forbidden
58453  */
58454 #define IOMUXC_GPR_GPR52_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_SHIFT)) & IOMUXC_GPR_GPR52_DWP_MASK)
58455 
58456 #define IOMUXC_GPR_GPR52_DWP_LOCK_MASK           (0xC0000000U)
58457 #define IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT          (30U)
58458 /*! DWP_LOCK - Domain write protection lock
58459  *  0b00..Neither of DWP bits is locked
58460  *  0b01..The lower DWP bit is locked
58461  *  0b10..The higher DWP bit is locked
58462  *  0b11..Both DWP bits are locked
58463  */
58464 #define IOMUXC_GPR_GPR52_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR52_DWP_LOCK_MASK)
58465 /*! @} */
58466 
58467 /*! @name GPR53 - GPR53 General Purpose Register */
58468 /*! @{ */
58469 
58470 #define IOMUXC_GPR_GPR53_DWP_MASK                (0x30000000U)
58471 #define IOMUXC_GPR_GPR53_DWP_SHIFT               (28U)
58472 /*! DWP - Domain write protection
58473  *  0b00..Both cores are allowed
58474  *  0b01..CM7 is forbidden
58475  *  0b10..CM4 is forbidden
58476  *  0b11..Both cores are forbidden
58477  */
58478 #define IOMUXC_GPR_GPR53_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_SHIFT)) & IOMUXC_GPR_GPR53_DWP_MASK)
58479 
58480 #define IOMUXC_GPR_GPR53_DWP_LOCK_MASK           (0xC0000000U)
58481 #define IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT          (30U)
58482 /*! DWP_LOCK - Domain write protection lock
58483  *  0b00..Neither of DWP bits is locked
58484  *  0b01..The lower DWP bit is locked
58485  *  0b10..The higher DWP bit is locked
58486  *  0b11..Both DWP bits are locked
58487  */
58488 #define IOMUXC_GPR_GPR53_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR53_DWP_LOCK_MASK)
58489 /*! @} */
58490 
58491 /*! @name GPR54 - GPR54 General Purpose Register */
58492 /*! @{ */
58493 
58494 #define IOMUXC_GPR_GPR54_DWP_MASK                (0x30000000U)
58495 #define IOMUXC_GPR_GPR54_DWP_SHIFT               (28U)
58496 /*! DWP - Domain write protection
58497  *  0b00..Both cores are allowed
58498  *  0b01..CM7 is forbidden
58499  *  0b10..CM4 is forbidden
58500  *  0b11..Both cores are forbidden
58501  */
58502 #define IOMUXC_GPR_GPR54_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_SHIFT)) & IOMUXC_GPR_GPR54_DWP_MASK)
58503 
58504 #define IOMUXC_GPR_GPR54_DWP_LOCK_MASK           (0xC0000000U)
58505 #define IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT          (30U)
58506 /*! DWP_LOCK - Domain write protection lock
58507  *  0b00..Neither of DWP bits is locked
58508  *  0b01..The lower DWP bit is locked
58509  *  0b10..The higher DWP bit is locked
58510  *  0b11..Both DWP bits are locked
58511  */
58512 #define IOMUXC_GPR_GPR54_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR54_DWP_LOCK_MASK)
58513 /*! @} */
58514 
58515 /*! @name GPR55 - GPR55 General Purpose Register */
58516 /*! @{ */
58517 
58518 #define IOMUXC_GPR_GPR55_DWP_MASK                (0x30000000U)
58519 #define IOMUXC_GPR_GPR55_DWP_SHIFT               (28U)
58520 /*! DWP - Domain write protection
58521  *  0b00..Both cores are allowed
58522  *  0b01..CM7 is forbidden
58523  *  0b10..CM4 is forbidden
58524  *  0b11..Both cores are forbidden
58525  */
58526 #define IOMUXC_GPR_GPR55_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_SHIFT)) & IOMUXC_GPR_GPR55_DWP_MASK)
58527 
58528 #define IOMUXC_GPR_GPR55_DWP_LOCK_MASK           (0xC0000000U)
58529 #define IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT          (30U)
58530 /*! DWP_LOCK - Domain write protection lock
58531  *  0b00..Neither of DWP bits is locked
58532  *  0b01..The lower DWP bit is locked
58533  *  0b10..The higher DWP bit is locked
58534  *  0b11..Both DWP bits are locked
58535  */
58536 #define IOMUXC_GPR_GPR55_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR55_DWP_LOCK_MASK)
58537 /*! @} */
58538 
58539 /*! @name GPR59 - GPR59 General Purpose Register */
58540 /*! @{ */
58541 
58542 #define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK (0x1U)
58543 #define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT (0U)
58544 /*! MIPI_CSI_AUTO_PD_EN - Powers down inactive lanes reported by CSI2X_CFG_NUM_LANES. */
58545 #define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK)
58546 
58547 #define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK (0x2U)
58548 #define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT (1U)
58549 /*! MIPI_CSI_SOFT_RST_N - MIPI CSI APB clock domain and User interface clock domain software reset bit
58550  *  0b0..Assert reset
58551  *  0b1..De-assert reset
58552  */
58553 #define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK)
58554 
58555 #define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK (0x4U)
58556 #define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT (2U)
58557 /*! MIPI_CSI_CONT_CLK_MODE - Enables the slave clock lane feature to maintain HS reception state
58558  *    during continuous clock mode operation, despite line glitches.
58559  */
58560 #define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK)
58561 
58562 #define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK (0x8U)
58563 #define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT (3U)
58564 /*! MIPI_CSI_DDRCLK_EN - When high, enables received DDR clock on CLK_DRXHS */
58565 #define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK)
58566 
58567 #define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK     (0x10U)
58568 #define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT    (4U)
58569 /*! MIPI_CSI_PD_RX - Power Down input for MIPI CSI PHY. */
58570 #define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK)
58571 
58572 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK (0x20U)
58573 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT (5U)
58574 /*! MIPI_CSI_RX_ENABLE - Assert to enable MIPI CSI Receive Enable */
58575 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)
58576 
58577 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK   (0xC0U)
58578 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT  (6U)
58579 /*! MIPI_CSI_RX_RCAL - MIPI CSI PHY on-chip termination control bits */
58580 #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK)
58581 
58582 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK    (0x300U)
58583 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT   (8U)
58584 /*! MIPI_CSI_RXCDRP - Programming bits that adjust the threshold voltage of LP-CD, default setting 2'b01
58585  *  0b00..344mV
58586  *  0b01..325mV (Default)
58587  *  0b10..307mV
58588  *  0b11..Invalid
58589  */
58590 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK)
58591 
58592 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK    (0xC00U)
58593 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT   (10U)
58594 /*! MIPI_CSI_RXLPRP - Programming bits that adjust the threshold voltage of LP-RX, default setting 2'b01 */
58595 #define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK)
58596 
58597 #define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK (0x3F000U)
58598 #define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT (12U)
58599 /*! MIPI_CSI_S_PRG_RXHS_SETTLE - Bits used to program T_HS_SETTLE. */
58600 #define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)
58601 
58602 #define IOMUXC_GPR_GPR59_DWP_MASK                (0x30000000U)
58603 #define IOMUXC_GPR_GPR59_DWP_SHIFT               (28U)
58604 /*! DWP - Domain write protection
58605  *  0b00..Both cores are allowed
58606  *  0b01..CM7 is forbidden
58607  *  0b10..CM4 is forbidden
58608  *  0b11..Both cores are forbidden
58609  */
58610 #define IOMUXC_GPR_GPR59_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_SHIFT)) & IOMUXC_GPR_GPR59_DWP_MASK)
58611 
58612 #define IOMUXC_GPR_GPR59_DWP_LOCK_MASK           (0xC0000000U)
58613 #define IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT          (30U)
58614 /*! DWP_LOCK - Domain write protection lock
58615  *  0b00..Neither of DWP bits is locked
58616  *  0b01..The lower DWP bit is locked
58617  *  0b10..The higher DWP bit is locked
58618  *  0b11..Both DWP bits are locked
58619  */
58620 #define IOMUXC_GPR_GPR59_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR59_DWP_LOCK_MASK)
58621 /*! @} */
58622 
58623 /*! @name GPR62 - GPR62 General Purpose Register */
58624 /*! @{ */
58625 
58626 #define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK    (0x7U)
58627 #define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT   (0U)
58628 /*! MIPI_DSI_CLK_TM - MIPI DSI Clock Lane triming bits */
58629 #define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK)
58630 
58631 #define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK     (0x38U)
58632 #define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT    (3U)
58633 /*! MIPI_DSI_D0_TM - MIPI DSI Data Lane 0 triming bits */
58634 #define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK)
58635 
58636 #define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK     (0x1C0U)
58637 #define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT    (6U)
58638 /*! MIPI_DSI_D1_TM - MIPI DSI Data Lane 1 triming bits */
58639 #define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK)
58640 
58641 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK   (0x600U)
58642 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT  (9U)
58643 /*! MIPI_DSI_TX_RCAL - MIPI DSI PHY on-chip termination control bits */
58644 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK)
58645 
58646 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK (0x3800U)
58647 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT (11U)
58648 /*! MIPI_DSI_TX_ULPS_ENABLE - DSI transmit ULPS mode enable */
58649 #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK)
58650 
58651 #define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK (0x10000U)
58652 #define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT (16U)
58653 /*! MIPI_DSI_PCLK_SOFT_RESET_N - MIPI DSI APB clock domain software reset bit
58654  *  0b0..Assert reset
58655  *  0b1..De-assert reset
58656  */
58657 #define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK)
58658 
58659 #define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK (0x20000U)
58660 #define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT (17U)
58661 /*! MIPI_DSI_BYTE_SOFT_RESET_N - MIPI DSI Byte clock domain software reset bit
58662  *  0b0..Assert reset
58663  *  0b1..De-assert reset
58664  */
58665 #define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK)
58666 
58667 #define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK (0x40000U)
58668 #define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT (18U)
58669 /*! MIPI_DSI_DPI_SOFT_RESET_N - MIPI DSI Pixel clock domain software reset bit
58670  *  0b0..Assert reset
58671  *  0b1..De-assert reset
58672  */
58673 #define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK)
58674 
58675 #define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK (0x80000U)
58676 #define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT (19U)
58677 /*! MIPI_DSI_ESC_SOFT_RESET_N - MIPI DSI Escape clock domain software reset bit
58678  *  0b0..Assert reset
58679  *  0b1..De-assert reset
58680  */
58681 #define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK)
58682 
58683 #define IOMUXC_GPR_GPR62_DWP_MASK                (0x30000000U)
58684 #define IOMUXC_GPR_GPR62_DWP_SHIFT               (28U)
58685 /*! DWP - Domain write protection
58686  *  0b00..Both cores are allowed
58687  *  0b01..CM7 is forbidden
58688  *  0b10..CM4 is forbidden
58689  *  0b11..Both cores are forbidden
58690  */
58691 #define IOMUXC_GPR_GPR62_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_SHIFT)) & IOMUXC_GPR_GPR62_DWP_MASK)
58692 
58693 #define IOMUXC_GPR_GPR62_DWP_LOCK_MASK           (0xC0000000U)
58694 #define IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT          (30U)
58695 /*! DWP_LOCK - Domain write protection lock
58696  *  0b00..Neither of DWP bits is locked
58697  *  0b01..The lower DWP bit is locked
58698  *  0b10..The higher DWP bit is locked
58699  *  0b11..Both DWP bits are locked
58700  */
58701 #define IOMUXC_GPR_GPR62_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR62_DWP_LOCK_MASK)
58702 /*! @} */
58703 
58704 /*! @name GPR63 - GPR63 General Purpose Register */
58705 /*! @{ */
58706 
58707 #define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK (0x7U)
58708 #define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT (0U)
58709 /*! MIPI_DSI_TX_ULPS_ACTIVE - DSI transmit ULPS mode active flag */
58710 #define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK)
58711 /*! @} */
58712 
58713 /*! @name GPR64 - GPR64 General Purpose Register */
58714 /*! @{ */
58715 
58716 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK  (0x1U)
58717 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT (0U)
58718 /*! GPIO_DISP1_FREEZE - Compensation code freeze */
58719 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK)
58720 
58721 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK  (0x2U)
58722 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT (1U)
58723 /*! GPIO_DISP1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */
58724 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK)
58725 
58726 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK  (0x4U)
58727 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT (2U)
58728 /*! GPIO_DISP1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */
58729 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK)
58730 
58731 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK (0x8U)
58732 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT (3U)
58733 /*! GPIO_DISP1_FASTFRZ_EN - Compensation code fast freeze */
58734 #define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK)
58735 
58736 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK  (0xF0U)
58737 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT (4U)
58738 /*! GPIO_DISP1_RASRCP - GPIO_DISP_B1 IO bank's 4-bit PMOS compensation codes from core */
58739 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK)
58740 
58741 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK  (0xF00U)
58742 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT (8U)
58743 /*! GPIO_DISP1_RASRCN - GPIO_DISP_B1 IO bank's 4-bit NMOS compensation codes from core */
58744 #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK)
58745 
58746 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK (0x1000U)
58747 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT (12U)
58748 /*! GPIO_DISP1_SELECT_NASRC - GPIO_DISP1_NASRC selection */
58749 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK)
58750 
58751 #define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK (0x2000U)
58752 #define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT (13U)
58753 /*! GPIO_DISP1_REFGEN_SLEEP - GPIO_DISP_B1 IO bank reference voltage generator cell sleep enable */
58754 #define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK)
58755 
58756 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK (0x4000U)
58757 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT (14U)
58758 /*! GPIO_DISP1_SUPLYDET_LATCH - GPIO_DISP_B1 IO bank power supply mode latch enable */
58759 #define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK)
58760 
58761 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK  (0x100000U)
58762 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT (20U)
58763 /*! GPIO_DISP1_COMPOK - GPIO_DISP_B1 IO bank compensation OK flag */
58764 #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK)
58765 
58766 #define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK   (0x1E00000U)
58767 #define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT  (21U)
58768 /*! GPIO_DISP1_NASRC - GPIO_DISP_B1 IO bank compensation codes */
58769 #define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK)
58770 
58771 #define IOMUXC_GPR_GPR64_DWP_MASK                (0x30000000U)
58772 #define IOMUXC_GPR_GPR64_DWP_SHIFT               (28U)
58773 /*! DWP - Domain write protection
58774  *  0b00..Both cores are allowed
58775  *  0b01..CM7 is forbidden
58776  *  0b10..CM4 is forbidden
58777  *  0b11..Both cores are forbidden
58778  */
58779 #define IOMUXC_GPR_GPR64_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_SHIFT)) & IOMUXC_GPR_GPR64_DWP_MASK)
58780 
58781 #define IOMUXC_GPR_GPR64_DWP_LOCK_MASK           (0xC0000000U)
58782 #define IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT          (30U)
58783 /*! DWP_LOCK - Domain write protection lock
58784  *  0b00..Neither of DWP bits is locked
58785  *  0b01..The lower DWP bit is locked
58786  *  0b10..The higher DWP bit is locked
58787  *  0b11..Both DWP bits are locked
58788  */
58789 #define IOMUXC_GPR_GPR64_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR64_DWP_LOCK_MASK)
58790 /*! @} */
58791 
58792 /*! @name GPR65 - GPR65 General Purpose Register */
58793 /*! @{ */
58794 
58795 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK   (0x1U)
58796 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT  (0U)
58797 /*! GPIO_EMC1_FREEZE - Compensation code freeze */
58798 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK)
58799 
58800 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK   (0x2U)
58801 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT  (1U)
58802 /*! GPIO_EMC1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */
58803 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK)
58804 
58805 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK   (0x4U)
58806 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT  (2U)
58807 /*! GPIO_EMC1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */
58808 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK)
58809 
58810 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK (0x8U)
58811 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT (3U)
58812 /*! GPIO_EMC1_FASTFRZ_EN - Compensation code fast freeze */
58813 #define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK)
58814 
58815 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK   (0xF0U)
58816 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT  (4U)
58817 /*! GPIO_EMC1_RASRCP - GPIO_EMC_B1 IO bank's 4-bit PMOS compensation codes from core */
58818 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK)
58819 
58820 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK   (0xF00U)
58821 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT  (8U)
58822 /*! GPIO_EMC1_RASRCN - GPIO_EMC_B1 IO bank's 4-bit NMOS compensation codes from core */
58823 #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK)
58824 
58825 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK (0x1000U)
58826 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT (12U)
58827 /*! GPIO_EMC1_SELECT_NASRC - GPIO_EMC1_NASRC selection */
58828 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK)
58829 
58830 #define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK (0x2000U)
58831 #define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT (13U)
58832 /*! GPIO_EMC1_REFGEN_SLEEP - GPIO_EMC_B1 IO bank reference voltage generator cell sleep enable */
58833 #define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK)
58834 
58835 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK (0x4000U)
58836 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT (14U)
58837 /*! GPIO_EMC1_SUPLYDET_LATCH - GPIO_EMC_B1 IO bank power supply mode latch enable */
58838 #define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK)
58839 
58840 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK   (0x100000U)
58841 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT  (20U)
58842 /*! GPIO_EMC1_COMPOK - GPIO_EMC_B1 IO bank compensation OK flag */
58843 #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK)
58844 
58845 #define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK    (0x1E00000U)
58846 #define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT   (21U)
58847 /*! GPIO_EMC1_NASRC - GPIO_EMC_B1 IO bank compensation codes */
58848 #define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK)
58849 
58850 #define IOMUXC_GPR_GPR65_DWP_MASK                (0x30000000U)
58851 #define IOMUXC_GPR_GPR65_DWP_SHIFT               (28U)
58852 /*! DWP - Domain write protection
58853  *  0b00..Both cores are allowed
58854  *  0b01..CM7 is forbidden
58855  *  0b10..CM4 is forbidden
58856  *  0b11..Both cores are forbidden
58857  */
58858 #define IOMUXC_GPR_GPR65_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_SHIFT)) & IOMUXC_GPR_GPR65_DWP_MASK)
58859 
58860 #define IOMUXC_GPR_GPR65_DWP_LOCK_MASK           (0xC0000000U)
58861 #define IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT          (30U)
58862 /*! DWP_LOCK - Domain write protection lock
58863  *  0b00..Neither of DWP bits is locked
58864  *  0b01..The lower DWP bit is locked
58865  *  0b10..The higher DWP bit is locked
58866  *  0b11..Both DWP bits are locked
58867  */
58868 #define IOMUXC_GPR_GPR65_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR65_DWP_LOCK_MASK)
58869 /*! @} */
58870 
58871 /*! @name GPR66 - GPR66 General Purpose Register */
58872 /*! @{ */
58873 
58874 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK   (0x1U)
58875 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT  (0U)
58876 /*! GPIO_EMC2_FREEZE - Compensation code freeze */
58877 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK)
58878 
58879 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK   (0x2U)
58880 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT  (1U)
58881 /*! GPIO_EMC2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */
58882 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK)
58883 
58884 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK   (0x4U)
58885 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT  (2U)
58886 /*! GPIO_EMC2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */
58887 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK)
58888 
58889 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK (0x8U)
58890 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT (3U)
58891 /*! GPIO_EMC2_FASTFRZ_EN - Compensation code fast freeze */
58892 #define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK)
58893 
58894 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK   (0xF0U)
58895 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT  (4U)
58896 /*! GPIO_EMC2_RASRCP - GPIO_EMC_B2 IO bank's 4-bit PMOS compensation codes from core */
58897 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK)
58898 
58899 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK   (0xF00U)
58900 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT  (8U)
58901 /*! GPIO_EMC2_RASRCN - GPIO_EMC_B2 IO bank's 4-bit NMOS compensation codes from core */
58902 #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK)
58903 
58904 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK (0x1000U)
58905 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT (12U)
58906 /*! GPIO_EMC2_SELECT_NASRC - GPIO_EMC2_NASRC selection */
58907 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK)
58908 
58909 #define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK (0x2000U)
58910 #define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT (13U)
58911 /*! GPIO_EMC2_REFGEN_SLEEP - GPIO_EMC_B2 IO bank reference voltage generator cell sleep enable */
58912 #define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK)
58913 
58914 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK (0x4000U)
58915 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT (14U)
58916 /*! GPIO_EMC2_SUPLYDET_LATCH - GPIO_EMC_B2 IO bank power supply mode latch enable */
58917 #define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK)
58918 
58919 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK   (0x100000U)
58920 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT  (20U)
58921 /*! GPIO_EMC2_COMPOK - GPIO_EMC_B2 IO bank compensation OK flag */
58922 #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK)
58923 
58924 #define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK    (0x1E00000U)
58925 #define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT   (21U)
58926 /*! GPIO_EMC2_NASRC - GPIO_EMC_B2 IO bank compensation codes */
58927 #define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK)
58928 
58929 #define IOMUXC_GPR_GPR66_DWP_MASK                (0x30000000U)
58930 #define IOMUXC_GPR_GPR66_DWP_SHIFT               (28U)
58931 /*! DWP - Domain write protection
58932  *  0b00..Both cores are allowed
58933  *  0b01..CM7 is forbidden
58934  *  0b10..CM4 is forbidden
58935  *  0b11..Both cores are forbidden
58936  */
58937 #define IOMUXC_GPR_GPR66_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_SHIFT)) & IOMUXC_GPR_GPR66_DWP_MASK)
58938 
58939 #define IOMUXC_GPR_GPR66_DWP_LOCK_MASK           (0xC0000000U)
58940 #define IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT          (30U)
58941 /*! DWP_LOCK - Domain write protection lock
58942  *  0b00..Neither of DWP bits is locked
58943  *  0b01..The lower DWP bit is locked
58944  *  0b10..The higher DWP bit is locked
58945  *  0b11..Both DWP bits are locked
58946  */
58947 #define IOMUXC_GPR_GPR66_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR66_DWP_LOCK_MASK)
58948 /*! @} */
58949 
58950 /*! @name GPR67 - GPR67 General Purpose Register */
58951 /*! @{ */
58952 
58953 #define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK    (0x1U)
58954 #define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT   (0U)
58955 /*! GPIO_SD1_FREEZE - Compensation code freeze */
58956 #define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK)
58957 
58958 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK    (0x2U)
58959 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT   (1U)
58960 /*! GPIO_SD1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */
58961 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK)
58962 
58963 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK    (0x4U)
58964 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT   (2U)
58965 /*! GPIO_SD1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */
58966 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK)
58967 
58968 #define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK (0x8U)
58969 #define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT (3U)
58970 /*! GPIO_SD1_FASTFRZ_EN - Compensation code fast freeze */
58971 #define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK)
58972 
58973 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK    (0xF0U)
58974 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT   (4U)
58975 /*! GPIO_SD1_RASRCP - GPIO_SD_B1 IO bank's 4-bit PMOS compensation codes from core */
58976 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK)
58977 
58978 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK    (0xF00U)
58979 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT   (8U)
58980 /*! GPIO_SD1_RASRCN - GPIO_SD_B1 IO bank's 4-bit NMOS compensation codes from core */
58981 #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK)
58982 
58983 #define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK (0x1000U)
58984 #define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT (12U)
58985 /*! GPIO_SD1_SELECT_NASRC - GPIO_SD1_NASRC selection */
58986 #define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK)
58987 
58988 #define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK (0x2000U)
58989 #define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT (13U)
58990 /*! GPIO_SD1_REFGEN_SLEEP - GPIO_SD_B1 IO bank reference voltage generator cell sleep enable */
58991 #define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK)
58992 
58993 #define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK (0x4000U)
58994 #define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT (14U)
58995 /*! GPIO_SD1_SUPLYDET_LATCH - GPIO_SD_B1 IO bank power supply mode latch enable */
58996 #define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK)
58997 
58998 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK    (0x100000U)
58999 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT   (20U)
59000 /*! GPIO_SD1_COMPOK - GPIO_SD_B1 IO bank compensation OK flag */
59001 #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK)
59002 
59003 #define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK     (0x1E00000U)
59004 #define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT    (21U)
59005 /*! GPIO_SD1_NASRC - GPIO_SD_B1 IO bank compensation codes */
59006 #define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK)
59007 
59008 #define IOMUXC_GPR_GPR67_DWP_MASK                (0x30000000U)
59009 #define IOMUXC_GPR_GPR67_DWP_SHIFT               (28U)
59010 /*! DWP - Domain write protection
59011  *  0b00..Both cores are allowed
59012  *  0b01..CM7 is forbidden
59013  *  0b10..CM4 is forbidden
59014  *  0b11..Both cores are forbidden
59015  */
59016 #define IOMUXC_GPR_GPR67_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_SHIFT)) & IOMUXC_GPR_GPR67_DWP_MASK)
59017 
59018 #define IOMUXC_GPR_GPR67_DWP_LOCK_MASK           (0xC0000000U)
59019 #define IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT          (30U)
59020 /*! DWP_LOCK - Domain write protection lock
59021  *  0b00..Neither of DWP bits is locked
59022  *  0b01..The lower DWP bit is locked
59023  *  0b10..The higher DWP bit is locked
59024  *  0b11..Both DWP bits are locked
59025  */
59026 #define IOMUXC_GPR_GPR67_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR67_DWP_LOCK_MASK)
59027 /*! @} */
59028 
59029 /*! @name GPR68 - GPR68 General Purpose Register */
59030 /*! @{ */
59031 
59032 #define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK    (0x1U)
59033 #define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT   (0U)
59034 /*! GPIO_SD2_FREEZE - Compensation code freeze */
59035 #define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK)
59036 
59037 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK    (0x2U)
59038 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT   (1U)
59039 /*! GPIO_SD2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */
59040 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK)
59041 
59042 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK    (0x4U)
59043 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT   (2U)
59044 /*! GPIO_SD2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */
59045 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK)
59046 
59047 #define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK (0x8U)
59048 #define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT (3U)
59049 /*! GPIO_SD2_FASTFRZ_EN - Compensation code fast freeze */
59050 #define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK)
59051 
59052 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK    (0xF0U)
59053 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT   (4U)
59054 /*! GPIO_SD2_RASRCP - GPIO_SD_B2 IO bank's 4-bit PMOS compensation codes from core */
59055 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK)
59056 
59057 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK    (0xF00U)
59058 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT   (8U)
59059 /*! GPIO_SD2_RASRCN - GPIO_SD_B2 IO bank's 4-bit NMOS compensation codes from core */
59060 #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK)
59061 
59062 #define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK (0x1000U)
59063 #define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT (12U)
59064 /*! GPIO_SD2_SELECT_NASRC - GPIO_SD2_NASRC selection */
59065 #define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK)
59066 
59067 #define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK (0x2000U)
59068 #define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT (13U)
59069 /*! GPIO_SD2_REFGEN_SLEEP - GPIO_SD_B2 IO bank reference voltage generator cell sleep enable */
59070 #define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK)
59071 
59072 #define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK (0x4000U)
59073 #define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT (14U)
59074 /*! GPIO_SD2_SUPLYDET_LATCH - GPIO_SD_B2 IO bank power supply mode latch enable */
59075 #define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK)
59076 
59077 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK    (0x100000U)
59078 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT   (20U)
59079 /*! GPIO_SD2_COMPOK - GPIO_SD_B2 IO bank compensation OK flag */
59080 #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK)
59081 
59082 #define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK     (0x1E00000U)
59083 #define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT    (21U)
59084 /*! GPIO_SD2_NASRC - GPIO_SD_B2 IO bank compensation codes */
59085 #define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK)
59086 
59087 #define IOMUXC_GPR_GPR68_DWP_MASK                (0x30000000U)
59088 #define IOMUXC_GPR_GPR68_DWP_SHIFT               (28U)
59089 /*! DWP - Domain write protection
59090  *  0b00..Both cores are allowed
59091  *  0b01..CM7 is forbidden
59092  *  0b10..CM4 is forbidden
59093  *  0b11..Both cores are forbidden
59094  */
59095 #define IOMUXC_GPR_GPR68_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_SHIFT)) & IOMUXC_GPR_GPR68_DWP_MASK)
59096 
59097 #define IOMUXC_GPR_GPR68_DWP_LOCK_MASK           (0xC0000000U)
59098 #define IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT          (30U)
59099 /*! DWP_LOCK - Domain write protection lock
59100  *  0b00..Neither of DWP bits is locked
59101  *  0b01..The lower DWP bit is locked
59102  *  0b10..The higher DWP bit is locked
59103  *  0b11..Both DWP bits are locked
59104  */
59105 #define IOMUXC_GPR_GPR68_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR68_DWP_LOCK_MASK)
59106 /*! @} */
59107 
59108 /*! @name GPR69 - GPR69 General Purpose Register */
59109 /*! @{ */
59110 
59111 #define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK (0x2U)
59112 #define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT (1U)
59113 /*! GPIO_DISP2_HIGH_RANGE - GPIO_DISP_B2 IO bank supply voltage range selection */
59114 #define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK)
59115 
59116 #define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK (0x4U)
59117 #define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT (2U)
59118 /*! GPIO_DISP2_LOW_RANGE - GPIO_DISP_B2 IO bank supply voltage range selection */
59119 #define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK)
59120 
59121 #define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK (0x10U)
59122 #define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT (4U)
59123 /*! GPIO_AD0_HIGH_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17 */
59124 #define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK)
59125 
59126 #define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK (0x20U)
59127 #define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT (5U)
59128 /*! GPIO_AD0_LOW_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17 */
59129 #define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK)
59130 
59131 #define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK (0x80U)
59132 #define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT (7U)
59133 /*! GPIO_AD1_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35 */
59134 #define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK)
59135 
59136 #define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK (0x100U)
59137 #define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT (8U)
59138 /*! GPIO_AD1_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35 */
59139 #define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK)
59140 
59141 #define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK (0x200U)
59142 #define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT (9U)
59143 /*! SUPLYDET_DISP1_SLEEP - GPIO_DISP_B1 IO bank supply voltage detector sleep mode enable */
59144 #define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK)
59145 
59146 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK (0x400U)
59147 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT (10U)
59148 /*! SUPLYDET_EMC1_SLEEP - GPIO_EMC_B1 IO bank supply voltage detector sleep mode enable */
59149 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK)
59150 
59151 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK (0x800U)
59152 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT (11U)
59153 /*! SUPLYDET_EMC2_SLEEP - GPIO_EMC_B2 IO bank supply voltage detector sleep mode enable */
59154 #define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK)
59155 
59156 #define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK (0x1000U)
59157 #define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT (12U)
59158 /*! SUPLYDET_SD1_SLEEP - GPIO_SD_B1 IO bank supply voltage detector sleep mode enable */
59159 #define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK)
59160 
59161 #define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK (0x2000U)
59162 #define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT (13U)
59163 /*! SUPLYDET_SD2_SLEEP - GPIO_SD_B2 IO bank supply voltage detector sleep mode enable */
59164 #define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK)
59165 
59166 #define IOMUXC_GPR_GPR69_DWP_MASK                (0x30000000U)
59167 #define IOMUXC_GPR_GPR69_DWP_SHIFT               (28U)
59168 /*! DWP - Domain write protection
59169  *  0b00..Both cores are allowed
59170  *  0b01..CM7 is forbidden
59171  *  0b10..CM4 is forbidden
59172  *  0b11..Both cores are forbidden
59173  */
59174 #define IOMUXC_GPR_GPR69_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_SHIFT)) & IOMUXC_GPR_GPR69_DWP_MASK)
59175 
59176 #define IOMUXC_GPR_GPR69_DWP_LOCK_MASK           (0xC0000000U)
59177 #define IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT          (30U)
59178 /*! DWP_LOCK - Domain write protection lock
59179  *  0b00..Neither of DWP bits is locked
59180  *  0b01..The lower DWP bit is locked
59181  *  0b10..The higher DWP bit is locked
59182  *  0b11..Both DWP bits are locked
59183  */
59184 #define IOMUXC_GPR_GPR69_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR69_DWP_LOCK_MASK)
59185 /*! @} */
59186 
59187 /*! @name GPR70 - GPR70 General Purpose Register */
59188 /*! @{ */
59189 
59190 #define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK      (0x1U)
59191 #define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT     (0U)
59192 /*! ADC1_IPG_DOZE - ADC1 doze mode */
59193 #define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK)
59194 
59195 #define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK      (0x2U)
59196 #define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT     (1U)
59197 /*! ADC1_STOP_REQ - ADC1 stop request */
59198 #define IOMUXC_GPR_GPR70_ADC1_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK)
59199 
59200 #define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK (0x4U)
59201 #define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT (2U)
59202 /*! ADC1_IPG_STOP_MODE - ADC1 stop mode selection, cannot change when ADC1_STOP_REQ is asserted.
59203  *  0b0..This module is functional in Stop Mode
59204  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59205  */
59206 #define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK)
59207 
59208 #define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK      (0x8U)
59209 #define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT     (3U)
59210 /*! ADC2_IPG_DOZE - ADC2 doze mode */
59211 #define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK)
59212 
59213 #define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK      (0x10U)
59214 #define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT     (4U)
59215 /*! ADC2_STOP_REQ - ADC2 stop request */
59216 #define IOMUXC_GPR_GPR70_ADC2_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK)
59217 
59218 #define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK (0x20U)
59219 #define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT (5U)
59220 /*! ADC2_IPG_STOP_MODE - ADC2 stop mode selection, cannot change when ADC2_STOP_REQ is asserted.
59221  *  0b0..This module is functional in Stop Mode
59222  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59223  */
59224 #define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK)
59225 
59226 #define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK      (0x40U)
59227 #define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT     (6U)
59228 /*! CAAM_IPG_DOZE - CAN3 doze mode */
59229 #define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK)
59230 
59231 #define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK      (0x80U)
59232 #define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT     (7U)
59233 /*! CAAM_STOP_REQ - CAAM stop request */
59234 #define IOMUXC_GPR_GPR70_CAAM_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK)
59235 
59236 #define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK      (0x100U)
59237 #define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT     (8U)
59238 /*! CAN1_IPG_DOZE - CAN1 doze mode */
59239 #define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK)
59240 
59241 #define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK      (0x200U)
59242 #define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT     (9U)
59243 /*! CAN1_STOP_REQ - CAN1 stop request */
59244 #define IOMUXC_GPR_GPR70_CAN1_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK)
59245 
59246 #define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK      (0x400U)
59247 #define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT     (10U)
59248 /*! CAN2_IPG_DOZE - CAN2 doze mode */
59249 #define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK)
59250 
59251 #define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK      (0x800U)
59252 #define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT     (11U)
59253 /*! CAN2_STOP_REQ - CAN2 stop request */
59254 #define IOMUXC_GPR_GPR70_CAN2_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK)
59255 
59256 #define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK      (0x1000U)
59257 #define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT     (12U)
59258 /*! CAN3_IPG_DOZE - CAN3 doze mode */
59259 #define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK)
59260 
59261 #define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK      (0x2000U)
59262 #define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT     (13U)
59263 /*! CAN3_STOP_REQ - CAN3 stop request */
59264 #define IOMUXC_GPR_GPR70_CAN3_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK)
59265 
59266 #define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK      (0x8000U)
59267 #define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT     (15U)
59268 /*! EDMA_STOP_REQ - EDMA stop request */
59269 #define IOMUXC_GPR_GPR70_EDMA_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK)
59270 
59271 #define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK (0x10000U)
59272 #define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT (16U)
59273 /*! EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request */
59274 #define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK)
59275 
59276 #define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK      (0x20000U)
59277 #define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT     (17U)
59278 /*! ENET_IPG_DOZE - ENET doze mode */
59279 #define IOMUXC_GPR_GPR70_ENET_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK)
59280 
59281 #define IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK      (0x40000U)
59282 #define IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT     (18U)
59283 /*! ENET_STOP_REQ - ENET stop request */
59284 #define IOMUXC_GPR_GPR70_ENET_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK)
59285 
59286 #define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK    (0x80000U)
59287 #define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT   (19U)
59288 /*! ENET1G_IPG_DOZE - ENET1G doze mode */
59289 #define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK)
59290 
59291 #define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK    (0x100000U)
59292 #define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT   (20U)
59293 /*! ENET1G_STOP_REQ - ENET1G stop request */
59294 #define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK)
59295 
59296 #define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK   (0x200000U)
59297 #define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT  (21U)
59298 /*! FLEXIO1_IPG_DOZE - FLEXIO2 doze mode */
59299 #define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK)
59300 
59301 #define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK   (0x400000U)
59302 #define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT  (22U)
59303 /*! FLEXIO2_IPG_DOZE - FLEXIO2 doze mode */
59304 #define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK)
59305 
59306 #define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK  (0x800000U)
59307 #define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT (23U)
59308 /*! FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode */
59309 #define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK)
59310 
59311 #define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK  (0x1000000U)
59312 #define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT (24U)
59313 /*! FLEXSPI1_STOP_REQ - FLEXSPI1 stop request */
59314 #define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK)
59315 
59316 #define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK  (0x2000000U)
59317 #define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT (25U)
59318 /*! FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode */
59319 #define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK)
59320 
59321 #define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK  (0x4000000U)
59322 #define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT (26U)
59323 /*! FLEXSPI2_STOP_REQ - FLEXSPI2 stop request */
59324 #define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK)
59325 
59326 #define IOMUXC_GPR_GPR70_DWP_MASK                (0x30000000U)
59327 #define IOMUXC_GPR_GPR70_DWP_SHIFT               (28U)
59328 /*! DWP - Domain write protection
59329  *  0b00..Both cores are allowed
59330  *  0b01..CM7 is forbidden
59331  *  0b10..CM4 is forbidden
59332  *  0b11..Both cores are forbidden
59333  */
59334 #define IOMUXC_GPR_GPR70_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_SHIFT)) & IOMUXC_GPR_GPR70_DWP_MASK)
59335 
59336 #define IOMUXC_GPR_GPR70_DWP_LOCK_MASK           (0xC0000000U)
59337 #define IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT          (30U)
59338 /*! DWP_LOCK - Domain write protection lock
59339  *  0b00..Neither of DWP bits is locked
59340  *  0b01..The lower DWP bit is locked
59341  *  0b10..The higher DWP bit is locked
59342  *  0b11..Both DWP bits are locked
59343  */
59344 #define IOMUXC_GPR_GPR70_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR70_DWP_LOCK_MASK)
59345 /*! @} */
59346 
59347 /*! @name GPR71 - GPR71 General Purpose Register */
59348 /*! @{ */
59349 
59350 #define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK      (0x1U)
59351 #define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT     (0U)
59352 /*! GPT1_IPG_DOZE - GPT1 doze mode */
59353 #define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK)
59354 
59355 #define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK      (0x2U)
59356 #define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT     (1U)
59357 /*! GPT2_IPG_DOZE - GPT2 doze mode */
59358 #define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK)
59359 
59360 #define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK      (0x4U)
59361 #define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT     (2U)
59362 /*! GPT3_IPG_DOZE - GPT3 doze mode */
59363 #define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK)
59364 
59365 #define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK      (0x8U)
59366 #define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT     (3U)
59367 /*! GPT4_IPG_DOZE - GPT4 doze mode */
59368 #define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK)
59369 
59370 #define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK      (0x10U)
59371 #define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT     (4U)
59372 /*! GPT5_IPG_DOZE - GPT5 doze mode */
59373 #define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK)
59374 
59375 #define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK      (0x20U)
59376 #define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT     (5U)
59377 /*! GPT6_IPG_DOZE - GPT6 doze mode */
59378 #define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK)
59379 
59380 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK    (0x40U)
59381 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT   (6U)
59382 /*! LPI2C1_IPG_DOZE - LPI2C1 doze mode */
59383 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK)
59384 
59385 #define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK    (0x80U)
59386 #define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT   (7U)
59387 /*! LPI2C1_STOP_REQ - LPI2C1 stop request */
59388 #define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK)
59389 
59390 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK (0x100U)
59391 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT (8U)
59392 /*! LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection, cannot change when LPI2C1_STOP_REQ is asserted.
59393  *  0b0..This module is functional in Stop Mode
59394  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59395  */
59396 #define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK)
59397 
59398 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK    (0x200U)
59399 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT   (9U)
59400 /*! LPI2C2_IPG_DOZE - LPI2C2 doze mode */
59401 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK)
59402 
59403 #define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK    (0x400U)
59404 #define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT   (10U)
59405 /*! LPI2C2_STOP_REQ - LPI2C2 stop request */
59406 #define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK)
59407 
59408 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK (0x800U)
59409 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT (11U)
59410 /*! LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection, cannot change when LPI2C2_STOP_REQ is asserted.
59411  *  0b0..This module is functional in Stop Mode
59412  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59413  */
59414 #define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK)
59415 
59416 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK    (0x1000U)
59417 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT   (12U)
59418 /*! LPI2C3_IPG_DOZE - LPI2C3 doze mode */
59419 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK)
59420 
59421 #define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK    (0x2000U)
59422 #define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT   (13U)
59423 /*! LPI2C3_STOP_REQ - LPI2C3 stop request */
59424 #define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK)
59425 
59426 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK (0x4000U)
59427 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT (14U)
59428 /*! LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection, cannot change when LPI2C3_STOP_REQ is asserted.
59429  *  0b0..This module is functional in Stop Mode
59430  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59431  */
59432 #define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK)
59433 
59434 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK    (0x8000U)
59435 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT   (15U)
59436 /*! LPI2C4_IPG_DOZE - LPI2C4 doze mode */
59437 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK)
59438 
59439 #define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK    (0x10000U)
59440 #define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT   (16U)
59441 /*! LPI2C4_STOP_REQ - LPI2C4 stop request */
59442 #define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK)
59443 
59444 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK (0x20000U)
59445 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT (17U)
59446 /*! LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection, cannot change when LPI2C4_STOP_REQ is asserted.
59447  *  0b0..This module is functional in Stop Mode
59448  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59449  */
59450 #define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK)
59451 
59452 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK    (0x40000U)
59453 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT   (18U)
59454 /*! LPI2C5_IPG_DOZE - LPI2C5 doze mode */
59455 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK)
59456 
59457 #define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK    (0x80000U)
59458 #define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT   (19U)
59459 /*! LPI2C5_STOP_REQ - LPI2C5 stop request */
59460 #define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK)
59461 
59462 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK (0x100000U)
59463 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT (20U)
59464 /*! LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection, cannot change when LPI2C5_STOP_REQ is asserted.
59465  *  0b0..This module is functional in Stop Mode
59466  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59467  */
59468 #define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK)
59469 
59470 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK    (0x200000U)
59471 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT   (21U)
59472 /*! LPI2C6_IPG_DOZE - LPI2C6 doze mode */
59473 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK)
59474 
59475 #define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK    (0x400000U)
59476 #define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT   (22U)
59477 /*! LPI2C6_STOP_REQ - LPI2C6 stop request */
59478 #define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK)
59479 
59480 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK (0x800000U)
59481 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT (23U)
59482 /*! LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection, cannot change when LPI2C6_STOP_REQ is asserted.
59483  *  0b0..This module is functional in Stop Mode
59484  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59485  */
59486 #define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK)
59487 
59488 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK    (0x1000000U)
59489 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT   (24U)
59490 /*! LPSPI1_IPG_DOZE - LPSPI1 doze mode */
59491 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK)
59492 
59493 #define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK    (0x2000000U)
59494 #define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT   (25U)
59495 /*! LPSPI1_STOP_REQ - LPSPI1 stop request */
59496 #define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK)
59497 
59498 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U)
59499 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT (26U)
59500 /*! LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection, cannot change when LPSPI1_STOP_REQ is asserted.
59501  *  0b0..This module is functional in Stop Mode
59502  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59503  */
59504 #define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK)
59505 
59506 #define IOMUXC_GPR_GPR71_DWP_MASK                (0x30000000U)
59507 #define IOMUXC_GPR_GPR71_DWP_SHIFT               (28U)
59508 /*! DWP - Domain write protection
59509  *  0b00..Both cores are allowed
59510  *  0b01..CM7 is forbidden
59511  *  0b10..CM4 is forbidden
59512  *  0b11..Both cores are forbidden
59513  */
59514 #define IOMUXC_GPR_GPR71_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_SHIFT)) & IOMUXC_GPR_GPR71_DWP_MASK)
59515 
59516 #define IOMUXC_GPR_GPR71_DWP_LOCK_MASK           (0xC0000000U)
59517 #define IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT          (30U)
59518 /*! DWP_LOCK - Domain write protection lock
59519  *  0b00..Neither of DWP bits is locked
59520  *  0b01..The lower DWP bit is locked
59521  *  0b10..The higher DWP bit is locked
59522  *  0b11..Both DWP bits are locked
59523  */
59524 #define IOMUXC_GPR_GPR71_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR71_DWP_LOCK_MASK)
59525 /*! @} */
59526 
59527 /*! @name GPR72 - GPR72 General Purpose Register */
59528 /*! @{ */
59529 
59530 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK    (0x1U)
59531 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT   (0U)
59532 /*! LPSPI2_IPG_DOZE - LPSPI2 doze mode */
59533 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK)
59534 
59535 #define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK    (0x2U)
59536 #define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT   (1U)
59537 /*! LPSPI2_STOP_REQ - LPSPI2 stop request */
59538 #define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK)
59539 
59540 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK (0x4U)
59541 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT (2U)
59542 /*! LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection, cannot change when LPSPI2_STOP_REQ is asserted.
59543  *  0b0..This module is functional in Stop Mode
59544  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59545  */
59546 #define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK)
59547 
59548 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK    (0x8U)
59549 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT   (3U)
59550 /*! LPSPI3_IPG_DOZE - LPSPI3 doze mode */
59551 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK)
59552 
59553 #define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK    (0x10U)
59554 #define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT   (4U)
59555 /*! LPSPI3_STOP_REQ - LPSPI3 stop request */
59556 #define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK)
59557 
59558 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK (0x20U)
59559 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT (5U)
59560 /*! LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection, cannot change when LPSPI3_STOP_REQ is asserted.
59561  *  0b0..This module is functional in Stop Mode
59562  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59563  */
59564 #define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK)
59565 
59566 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK    (0x40U)
59567 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT   (6U)
59568 /*! LPSPI4_IPG_DOZE - LPSPI4 doze mode */
59569 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK)
59570 
59571 #define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK    (0x80U)
59572 #define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT   (7U)
59573 /*! LPSPI4_STOP_REQ - LPSPI4 stop request */
59574 #define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK)
59575 
59576 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK (0x100U)
59577 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT (8U)
59578 /*! LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection, cannot change when LPSPI4_STOP_REQ is asserted.
59579  *  0b0..This module is functional in Stop Mode
59580  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59581  */
59582 #define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK)
59583 
59584 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK    (0x200U)
59585 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT   (9U)
59586 /*! LPSPI5_IPG_DOZE - LPSPI5 doze mode */
59587 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK)
59588 
59589 #define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK    (0x400U)
59590 #define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT   (10U)
59591 /*! LPSPI5_STOP_REQ - LPSPI5 stop request */
59592 #define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK)
59593 
59594 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK (0x800U)
59595 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT (11U)
59596 /*! LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection, cannot change when LPSPI5_STOP_REQ is asserted.
59597  *  0b0..This module is functional in Stop Mode
59598  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59599  */
59600 #define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK)
59601 
59602 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK    (0x1000U)
59603 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT   (12U)
59604 /*! LPSPI6_IPG_DOZE - LPSPI6 doze mode */
59605 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK)
59606 
59607 #define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK    (0x2000U)
59608 #define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT   (13U)
59609 /*! LPSPI6_STOP_REQ - LPSPI6 stop request */
59610 #define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK)
59611 
59612 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK (0x4000U)
59613 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT (14U)
59614 /*! LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection, cannot change when LPSPI6_STOP_REQ is asserted.
59615  *  0b0..This module is functional in Stop Mode
59616  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59617  */
59618 #define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK)
59619 
59620 #define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK   (0x8000U)
59621 #define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT  (15U)
59622 /*! LPUART1_IPG_DOZE - LPUART1 doze mode */
59623 #define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK)
59624 
59625 #define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK   (0x10000U)
59626 #define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT  (16U)
59627 /*! LPUART1_STOP_REQ - LPUART1 stop request */
59628 #define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK)
59629 
59630 #define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK (0x20000U)
59631 #define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT (17U)
59632 /*! LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection, cannot change when LPUART1_STOP_REQ is asserted.
59633  *  0b0..This module is functional in Stop Mode
59634  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59635  */
59636 #define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK)
59637 
59638 #define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK   (0x40000U)
59639 #define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT  (18U)
59640 /*! LPUART2_IPG_DOZE - LPUART2 doze mode */
59641 #define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK)
59642 
59643 #define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK   (0x80000U)
59644 #define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT  (19U)
59645 /*! LPUART2_STOP_REQ - LPUART2 stop request */
59646 #define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK)
59647 
59648 #define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK (0x100000U)
59649 #define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT (20U)
59650 /*! LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection, cannot change when LPUART2_STOP_REQ is asserted.
59651  *  0b0..This module is functional in Stop Mode
59652  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59653  */
59654 #define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK)
59655 
59656 #define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK   (0x200000U)
59657 #define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT  (21U)
59658 /*! LPUART3_IPG_DOZE - LPUART3 doze mode */
59659 #define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK)
59660 
59661 #define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK   (0x400000U)
59662 #define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT  (22U)
59663 /*! LPUART3_STOP_REQ - LPUART3 stop request */
59664 #define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK)
59665 
59666 #define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK (0x800000U)
59667 #define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT (23U)
59668 /*! LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection, cannot change when LPUART3_STOP_REQ is asserted.
59669  *  0b0..This module is functional in Stop Mode
59670  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59671  */
59672 #define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK)
59673 
59674 #define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK   (0x1000000U)
59675 #define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT  (24U)
59676 /*! LPUART4_IPG_DOZE - LPUART4 doze mode */
59677 #define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK)
59678 
59679 #define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK   (0x2000000U)
59680 #define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT  (25U)
59681 /*! LPUART4_STOP_REQ - LPUART4 stop request */
59682 #define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK)
59683 
59684 #define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK (0x4000000U)
59685 #define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT (26U)
59686 /*! LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection, cannot change when LPUART4_STOP_REQ is asserted.
59687  *  0b0..This module is functional in Stop Mode
59688  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59689  */
59690 #define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK)
59691 
59692 #define IOMUXC_GPR_GPR72_DWP_MASK                (0x30000000U)
59693 #define IOMUXC_GPR_GPR72_DWP_SHIFT               (28U)
59694 /*! DWP - Domain write protection
59695  *  0b00..Both cores are allowed
59696  *  0b01..CM7 is forbidden
59697  *  0b10..CM4 is forbidden
59698  *  0b11..Both cores are forbidden
59699  */
59700 #define IOMUXC_GPR_GPR72_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_SHIFT)) & IOMUXC_GPR_GPR72_DWP_MASK)
59701 
59702 #define IOMUXC_GPR_GPR72_DWP_LOCK_MASK           (0xC0000000U)
59703 #define IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT          (30U)
59704 /*! DWP_LOCK - Domain write protection lock
59705  *  0b00..Neither of DWP bits is locked
59706  *  0b01..The lower DWP bit is locked
59707  *  0b10..The higher DWP bit is locked
59708  *  0b11..Both DWP bits are locked
59709  */
59710 #define IOMUXC_GPR_GPR72_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR72_DWP_LOCK_MASK)
59711 /*! @} */
59712 
59713 /*! @name GPR73 - GPR73 General Purpose Register */
59714 /*! @{ */
59715 
59716 #define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK   (0x1U)
59717 #define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT  (0U)
59718 /*! LPUART5_IPG_DOZE - LPUART5 doze mode */
59719 #define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK)
59720 
59721 #define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK   (0x2U)
59722 #define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT  (1U)
59723 /*! LPUART5_STOP_REQ - LPUART5 stop request */
59724 #define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK)
59725 
59726 #define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK (0x4U)
59727 #define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT (2U)
59728 /*! LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection, cannot change when LPUART5_STOP_REQ is asserted.
59729  *  0b0..This module is functional in Stop Mode
59730  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59731  */
59732 #define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK)
59733 
59734 #define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK   (0x8U)
59735 #define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT  (3U)
59736 /*! LPUART6_IPG_DOZE - LPUART6 doze mode */
59737 #define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK)
59738 
59739 #define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK   (0x10U)
59740 #define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT  (4U)
59741 /*! LPUART6_STOP_REQ - LPUART6 stop request */
59742 #define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK)
59743 
59744 #define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK (0x20U)
59745 #define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT (5U)
59746 /*! LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection, cannot change when LPUART6_STOP_REQ is asserted.
59747  *  0b0..This module is functional in Stop Mode
59748  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59749  */
59750 #define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK)
59751 
59752 #define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK   (0x40U)
59753 #define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT  (6U)
59754 /*! LPUART7_IPG_DOZE - LPUART7 doze mode */
59755 #define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK)
59756 
59757 #define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK   (0x80U)
59758 #define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT  (7U)
59759 /*! LPUART7_STOP_REQ - LPUART7 stop request */
59760 #define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK)
59761 
59762 #define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK (0x100U)
59763 #define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT (8U)
59764 /*! LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection, cannot change when LPUART7_STOP_REQ is asserted.
59765  *  0b0..This module is functional in Stop Mode
59766  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59767  */
59768 #define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK)
59769 
59770 #define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK   (0x200U)
59771 #define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT  (9U)
59772 /*! LPUART8_IPG_DOZE - LPUART8 doze mode */
59773 #define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK)
59774 
59775 #define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK   (0x400U)
59776 #define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT  (10U)
59777 /*! LPUART8_STOP_REQ - LPUART8 stop request */
59778 #define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK)
59779 
59780 #define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK (0x800U)
59781 #define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT (11U)
59782 /*! LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection, cannot change when LPUART8_STOP_REQ is asserted.
59783  *  0b0..This module is functional in Stop Mode
59784  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59785  */
59786 #define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK)
59787 
59788 #define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK   (0x1000U)
59789 #define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT  (12U)
59790 /*! LPUART9_IPG_DOZE - LPUART9 doze mode */
59791 #define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK)
59792 
59793 #define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK   (0x2000U)
59794 #define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT  (13U)
59795 /*! LPUART9_STOP_REQ - LPUART9 stop request */
59796 #define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK)
59797 
59798 #define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK (0x4000U)
59799 #define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT (14U)
59800 /*! LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection, cannot change when LPUART9_STOP_REQ is asserted.
59801  *  0b0..This module is functional in Stop Mode
59802  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59803  */
59804 #define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK)
59805 
59806 #define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK  (0x8000U)
59807 #define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT (15U)
59808 /*! LPUART10_IPG_DOZE - LPUART10 doze mode */
59809 #define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK)
59810 
59811 #define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK  (0x10000U)
59812 #define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT (16U)
59813 /*! LPUART10_STOP_REQ - LPUART10 stop request */
59814 #define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK)
59815 
59816 #define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK (0x20000U)
59817 #define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT (17U)
59818 /*! LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection, cannot change when LPUART10_STOP_REQ is asserted.
59819  *  0b0..This module is functional in Stop Mode
59820  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59821  */
59822 #define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK)
59823 
59824 #define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK  (0x40000U)
59825 #define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT (18U)
59826 /*! LPUART11_IPG_DOZE - LPUART11 doze mode */
59827 #define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK)
59828 
59829 #define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK  (0x80000U)
59830 #define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT (19U)
59831 /*! LPUART11_STOP_REQ - LPUART11 stop request */
59832 #define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK)
59833 
59834 #define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK (0x100000U)
59835 #define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT (20U)
59836 /*! LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection, cannot change when LPUART11_STOP_REQ is asserted.
59837  *  0b0..This module is functional in Stop Mode
59838  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59839  */
59840 #define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK)
59841 
59842 #define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK  (0x200000U)
59843 #define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT (21U)
59844 /*! LPUART12_IPG_DOZE - LPUART12 doze mode */
59845 #define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK)
59846 
59847 #define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK  (0x400000U)
59848 #define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT (22U)
59849 /*! LPUART12_STOP_REQ - LPUART12 stop request */
59850 #define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK)
59851 
59852 #define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK (0x800000U)
59853 #define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT (23U)
59854 /*! LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection, cannot change when LPUART12_STOP_REQ is asserted.
59855  *  0b0..This module is functional in Stop Mode
59856  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59857  */
59858 #define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK)
59859 
59860 #define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK       (0x1000000U)
59861 #define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT      (24U)
59862 /*! MIC_IPG_DOZE - MIC doze mode */
59863 #define IOMUXC_GPR_GPR73_MIC_IPG_DOZE(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK)
59864 
59865 #define IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK       (0x2000000U)
59866 #define IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT      (25U)
59867 /*! MIC_STOP_REQ - MIC stop request */
59868 #define IOMUXC_GPR_GPR73_MIC_STOP_REQ(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK)
59869 
59870 #define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK  (0x4000000U)
59871 #define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT (26U)
59872 /*! MIC_IPG_STOP_MODE - MIC stop mode selection, cannot change when MIC_STOP_REQ is asserted.
59873  *  0b0..This module is functional in Stop Mode
59874  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
59875  */
59876 #define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK)
59877 
59878 #define IOMUXC_GPR_GPR73_DWP_MASK                (0x30000000U)
59879 #define IOMUXC_GPR_GPR73_DWP_SHIFT               (28U)
59880 /*! DWP - Domain write protection
59881  *  0b00..Both cores are allowed
59882  *  0b01..CM7 is forbidden
59883  *  0b10..CM4 is forbidden
59884  *  0b11..Both cores are forbidden
59885  */
59886 #define IOMUXC_GPR_GPR73_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_SHIFT)) & IOMUXC_GPR_GPR73_DWP_MASK)
59887 
59888 #define IOMUXC_GPR_GPR73_DWP_LOCK_MASK           (0xC0000000U)
59889 #define IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT          (30U)
59890 /*! DWP_LOCK - Domain write protection lock
59891  *  0b00..Neither of DWP bits is locked
59892  *  0b01..The lower DWP bit is locked
59893  *  0b10..The higher DWP bit is locked
59894  *  0b11..Both DWP bits are locked
59895  */
59896 #define IOMUXC_GPR_GPR73_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR73_DWP_LOCK_MASK)
59897 /*! @} */
59898 
59899 /*! @name GPR74 - GPR74 General Purpose Register */
59900 /*! @{ */
59901 
59902 #define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK      (0x2U)
59903 #define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT     (1U)
59904 /*! PIT1_STOP_REQ - PIT1 stop request */
59905 #define IOMUXC_GPR_GPR74_PIT1_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK)
59906 
59907 #define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK      (0x4U)
59908 #define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT     (2U)
59909 /*! PIT2_STOP_REQ - PIT2 stop request */
59910 #define IOMUXC_GPR_GPR74_PIT2_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK)
59911 
59912 #define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK      (0x8U)
59913 #define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT     (3U)
59914 /*! SEMC_STOP_REQ - SEMC stop request */
59915 #define IOMUXC_GPR_GPR74_SEMC_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK)
59916 
59917 #define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK      (0x10U)
59918 #define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT     (4U)
59919 /*! SIM1_IPG_DOZE - SIM1 doze mode */
59920 #define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK)
59921 
59922 #define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK      (0x20U)
59923 #define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT     (5U)
59924 /*! SIM2_IPG_DOZE - SIM2 doze mode */
59925 #define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK)
59926 
59927 #define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK   (0x40U)
59928 #define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT  (6U)
59929 /*! SNVS_HP_IPG_DOZE - SNVS_HP doze mode */
59930 #define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK)
59931 
59932 #define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK   (0x80U)
59933 #define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT  (7U)
59934 /*! SNVS_HP_STOP_REQ - SNVS_HP stop request */
59935 #define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK)
59936 
59937 #define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK     (0x100U)
59938 #define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT    (8U)
59939 /*! WDOG1_IPG_DOZE - WDOG1 doze mode */
59940 #define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK)
59941 
59942 #define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK     (0x200U)
59943 #define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT    (9U)
59944 /*! WDOG2_IPG_DOZE - WDOG2 doze mode */
59945 #define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK)
59946 
59947 #define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK      (0x400U)
59948 #define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT     (10U)
59949 /*! SAI1_STOP_REQ - SAI1 stop request */
59950 #define IOMUXC_GPR_GPR74_SAI1_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK)
59951 
59952 #define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK      (0x800U)
59953 #define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT     (11U)
59954 /*! SAI2_STOP_REQ - SAI2 stop request */
59955 #define IOMUXC_GPR_GPR74_SAI2_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK)
59956 
59957 #define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK      (0x1000U)
59958 #define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT     (12U)
59959 /*! SAI3_STOP_REQ - SAI3 stop request */
59960 #define IOMUXC_GPR_GPR74_SAI3_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK)
59961 
59962 #define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK      (0x2000U)
59963 #define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT     (13U)
59964 /*! SAI4_STOP_REQ - SAI4 stop request */
59965 #define IOMUXC_GPR_GPR74_SAI4_STOP_REQ(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK)
59966 
59967 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U)
59968 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT (14U)
59969 /*! FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request */
59970 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK)
59971 
59972 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK (0x8000U)
59973 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT (15U)
59974 /*! FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request */
59975 #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK)
59976 
59977 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U)
59978 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT (16U)
59979 /*! FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request */
59980 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK)
59981 
59982 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK (0x20000U)
59983 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT (17U)
59984 /*! FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request */
59985 #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK)
59986 
59987 #define IOMUXC_GPR_GPR74_DWP_MASK                (0x30000000U)
59988 #define IOMUXC_GPR_GPR74_DWP_SHIFT               (28U)
59989 /*! DWP - Domain write protection
59990  *  0b00..Both cores are allowed
59991  *  0b01..CM7 is forbidden
59992  *  0b10..CM4 is forbidden
59993  *  0b11..Both cores are forbidden
59994  */
59995 #define IOMUXC_GPR_GPR74_DWP(x)                  (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_SHIFT)) & IOMUXC_GPR_GPR74_DWP_MASK)
59996 
59997 #define IOMUXC_GPR_GPR74_DWP_LOCK_MASK           (0xC0000000U)
59998 #define IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT          (30U)
59999 /*! DWP_LOCK - Domain write protection lock
60000  *  0b00..Neither of DWP bits is locked
60001  *  0b01..The lower DWP bit is locked
60002  *  0b10..The higher DWP bit is locked
60003  *  0b11..Both DWP bits are locked
60004  */
60005 #define IOMUXC_GPR_GPR74_DWP_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR74_DWP_LOCK_MASK)
60006 /*! @} */
60007 
60008 /*! @name GPR75 - GPR75 General Purpose Register */
60009 /*! @{ */
60010 
60011 #define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK      (0x1U)
60012 #define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT     (0U)
60013 /*! ADC1_STOP_ACK - ADC1 stop acknowledge */
60014 #define IOMUXC_GPR_GPR75_ADC1_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK)
60015 
60016 #define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK      (0x2U)
60017 #define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT     (1U)
60018 /*! ADC2_STOP_ACK - ADC2 stop acknowledge */
60019 #define IOMUXC_GPR_GPR75_ADC2_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK)
60020 
60021 #define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK      (0x4U)
60022 #define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT     (2U)
60023 /*! CAAM_STOP_ACK - CAAM stop acknowledge */
60024 #define IOMUXC_GPR_GPR75_CAAM_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK)
60025 
60026 #define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK      (0x8U)
60027 #define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT     (3U)
60028 /*! CAN1_STOP_ACK - CAN1 stop acknowledge */
60029 #define IOMUXC_GPR_GPR75_CAN1_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK)
60030 
60031 #define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK      (0x10U)
60032 #define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT     (4U)
60033 /*! CAN2_STOP_ACK - CAN2 stop acknowledge */
60034 #define IOMUXC_GPR_GPR75_CAN2_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK)
60035 
60036 #define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK      (0x20U)
60037 #define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT     (5U)
60038 /*! CAN3_STOP_ACK - CAN3 stop acknowledge */
60039 #define IOMUXC_GPR_GPR75_CAN3_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK)
60040 
60041 #define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK      (0x40U)
60042 #define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT     (6U)
60043 /*! EDMA_STOP_ACK - EDMA stop acknowledge */
60044 #define IOMUXC_GPR_GPR75_EDMA_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK)
60045 
60046 #define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK (0x80U)
60047 #define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT (7U)
60048 /*! EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge */
60049 #define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK)
60050 
60051 #define IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK      (0x100U)
60052 #define IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT     (8U)
60053 /*! ENET_STOP_ACK - ENET stop acknowledge */
60054 #define IOMUXC_GPR_GPR75_ENET_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK)
60055 
60056 #define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK    (0x200U)
60057 #define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT   (9U)
60058 /*! ENET1G_STOP_ACK - ENET1G stop acknowledge */
60059 #define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK)
60060 
60061 #define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK  (0x400U)
60062 #define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT (10U)
60063 /*! FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge */
60064 #define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK)
60065 
60066 #define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK  (0x800U)
60067 #define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT (11U)
60068 /*! FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge */
60069 #define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK)
60070 
60071 #define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK    (0x1000U)
60072 #define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT   (12U)
60073 /*! LPI2C1_STOP_ACK - LPI2C1 stop acknowledge */
60074 #define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK)
60075 
60076 #define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK    (0x2000U)
60077 #define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT   (13U)
60078 /*! LPI2C2_STOP_ACK - LPI2C2 stop acknowledge */
60079 #define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK)
60080 
60081 #define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK    (0x4000U)
60082 #define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT   (14U)
60083 /*! LPI2C3_STOP_ACK - LPI2C3 stop acknowledge */
60084 #define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK)
60085 
60086 #define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK    (0x8000U)
60087 #define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT   (15U)
60088 /*! LPI2C4_STOP_ACK - LPI2C4 stop acknowledge */
60089 #define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK)
60090 
60091 #define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK    (0x10000U)
60092 #define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT   (16U)
60093 /*! LPI2C5_STOP_ACK - LPI2C5 stop acknowledge */
60094 #define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK)
60095 
60096 #define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK    (0x20000U)
60097 #define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT   (17U)
60098 /*! LPI2C6_STOP_ACK - LPI2C6 stop acknowledge */
60099 #define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK)
60100 
60101 #define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK    (0x40000U)
60102 #define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT   (18U)
60103 /*! LPSPI1_STOP_ACK - LPSPI1 stop acknowledge */
60104 #define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK)
60105 
60106 #define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK    (0x80000U)
60107 #define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT   (19U)
60108 /*! LPSPI2_STOP_ACK - LPSPI2 stop acknowledge */
60109 #define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK)
60110 
60111 #define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK    (0x100000U)
60112 #define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT   (20U)
60113 /*! LPSPI3_STOP_ACK - LPSPI3 stop acknowledge */
60114 #define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK)
60115 
60116 #define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK    (0x200000U)
60117 #define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT   (21U)
60118 /*! LPSPI4_STOP_ACK - LPSPI4 stop acknowledge */
60119 #define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK)
60120 
60121 #define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK    (0x400000U)
60122 #define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT   (22U)
60123 /*! LPSPI5_STOP_ACK - LPSPI5 stop acknowledge */
60124 #define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK)
60125 
60126 #define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK    (0x800000U)
60127 #define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT   (23U)
60128 /*! LPSPI6_STOP_ACK - LPSPI6 stop acknowledge */
60129 #define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK(x)      (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK)
60130 
60131 #define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK   (0x1000000U)
60132 #define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT  (24U)
60133 /*! LPUART1_STOP_ACK - LPUART1 stop acknowledge */
60134 #define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK)
60135 
60136 #define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK   (0x2000000U)
60137 #define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT  (25U)
60138 /*! LPUART2_STOP_ACK - LPUART2 stop acknowledge */
60139 #define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK)
60140 
60141 #define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK   (0x4000000U)
60142 #define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT  (26U)
60143 /*! LPUART3_STOP_ACK - LPUART3 stop acknowledge */
60144 #define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK)
60145 
60146 #define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK   (0x8000000U)
60147 #define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT  (27U)
60148 /*! LPUART4_STOP_ACK - LPUART4 stop acknowledge */
60149 #define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK)
60150 
60151 #define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK   (0x10000000U)
60152 #define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT  (28U)
60153 /*! LPUART5_STOP_ACK - LPUART5 stop acknowledge */
60154 #define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK)
60155 
60156 #define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK   (0x20000000U)
60157 #define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT  (29U)
60158 /*! LPUART6_STOP_ACK - LPUART6 stop acknowledge */
60159 #define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK)
60160 
60161 #define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK   (0x40000000U)
60162 #define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT  (30U)
60163 /*! LPUART7_STOP_ACK - LPUART7 stop acknowledge */
60164 #define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK)
60165 
60166 #define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK   (0x80000000U)
60167 #define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT  (31U)
60168 /*! LPUART8_STOP_ACK - LPUART8 stop acknowledge */
60169 #define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK)
60170 /*! @} */
60171 
60172 /*! @name GPR76 - GPR76 General Purpose Register */
60173 /*! @{ */
60174 
60175 #define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK   (0x1U)
60176 #define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT  (0U)
60177 /*! LPUART9_STOP_ACK - LPUART9 stop acknowledge */
60178 #define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK)
60179 
60180 #define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK  (0x2U)
60181 #define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT (1U)
60182 /*! LPUART10_STOP_ACK - LPUART10 stop acknowledge */
60183 #define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK)
60184 
60185 #define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK  (0x4U)
60186 #define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT (2U)
60187 /*! LPUART11_STOP_ACK - LPUART11 stop acknowledge */
60188 #define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK)
60189 
60190 #define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK  (0x8U)
60191 #define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT (3U)
60192 /*! LPUART12_STOP_ACK - LPUART12 stop acknowledge */
60193 #define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK)
60194 
60195 #define IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK       (0x10U)
60196 #define IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT      (4U)
60197 /*! MIC_STOP_ACK - MIC stop acknowledge */
60198 #define IOMUXC_GPR_GPR76_MIC_STOP_ACK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK)
60199 
60200 #define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK      (0x20U)
60201 #define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT     (5U)
60202 /*! PIT1_STOP_ACK - PIT1 stop acknowledge */
60203 #define IOMUXC_GPR_GPR76_PIT1_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK)
60204 
60205 #define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK      (0x40U)
60206 #define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT     (6U)
60207 /*! PIT2_STOP_ACK - PIT2 stop acknowledge */
60208 #define IOMUXC_GPR_GPR76_PIT2_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK)
60209 
60210 #define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK      (0x80U)
60211 #define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT     (7U)
60212 /*! SEMC_STOP_ACK - SEMC stop acknowledge */
60213 #define IOMUXC_GPR_GPR76_SEMC_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK)
60214 
60215 #define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK   (0x100U)
60216 #define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT  (8U)
60217 /*! SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge */
60218 #define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK)
60219 
60220 #define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK      (0x200U)
60221 #define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT     (9U)
60222 /*! SAI1_STOP_ACK - SAI1 stop acknowledge */
60223 #define IOMUXC_GPR_GPR76_SAI1_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK)
60224 
60225 #define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK      (0x400U)
60226 #define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT     (10U)
60227 /*! SAI2_STOP_ACK - SAI2 stop acknowledge */
60228 #define IOMUXC_GPR_GPR76_SAI2_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK)
60229 
60230 #define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK      (0x800U)
60231 #define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT     (11U)
60232 /*! SAI3_STOP_ACK - SAI3 stop acknowledge */
60233 #define IOMUXC_GPR_GPR76_SAI3_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK)
60234 
60235 #define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK      (0x1000U)
60236 #define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT     (12U)
60237 /*! SAI4_STOP_ACK - SAI4 stop acknowledge */
60238 #define IOMUXC_GPR_GPR76_SAI4_STOP_ACK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK)
60239 
60240 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U)
60241 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT (13U)
60242 /*! FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain */
60243 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK)
60244 
60245 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK (0x4000U)
60246 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT (14U)
60247 /*! FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain */
60248 #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK)
60249 
60250 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U)
60251 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT (15U)
60252 /*! FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain */
60253 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK)
60254 
60255 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK (0x10000U)
60256 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT (16U)
60257 /*! FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain */
60258 #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK)
60259 /*! @} */
60260 
60261 
60262 /*!
60263  * @}
60264  */ /* end of group IOMUXC_GPR_Register_Masks */
60265 
60266 
60267 /* IOMUXC_GPR - Peripheral instance base addresses */
60268 /** Peripheral IOMUXC_GPR base address */
60269 #define IOMUXC_GPR_BASE                          (0x400E4000u)
60270 /** Peripheral IOMUXC_GPR base pointer */
60271 #define IOMUXC_GPR                               ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
60272 /** Array initializer of IOMUXC_GPR peripheral base addresses */
60273 #define IOMUXC_GPR_BASE_ADDRS                    { IOMUXC_GPR_BASE }
60274 /** Array initializer of IOMUXC_GPR peripheral base pointers */
60275 #define IOMUXC_GPR_BASE_PTRS                     { IOMUXC_GPR }
60276 
60277 /*!
60278  * @}
60279  */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
60280 
60281 
60282 /* ----------------------------------------------------------------------------
60283    -- IOMUXC_LPSR Peripheral Access Layer
60284    ---------------------------------------------------------------------------- */
60285 
60286 /*!
60287  * @addtogroup IOMUXC_LPSR_Peripheral_Access_Layer IOMUXC_LPSR Peripheral Access Layer
60288  * @{
60289  */
60290 
60291 /** IOMUXC_LPSR - Register Layout Typedef */
60292 typedef struct {
60293   __IO uint32_t SW_MUX_CTL_PAD[16];                /**< SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register, array offset: 0x0, array step: 0x4 */
60294   __IO uint32_t SW_PAD_CTL_PAD[16];                /**< SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register, array offset: 0x40, array step: 0x4 */
60295   __IO uint32_t SELECT_INPUT[24];                  /**< CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register..SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register, array offset: 0x80, array step: 0x4 */
60296 } IOMUXC_LPSR_Type;
60297 
60298 /* ----------------------------------------------------------------------------
60299    -- IOMUXC_LPSR Register Masks
60300    ---------------------------------------------------------------------------- */
60301 
60302 /*!
60303  * @addtogroup IOMUXC_LPSR_Register_Masks IOMUXC_LPSR Register Masks
60304  * @{
60305  */
60306 
60307 /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register */
60308 /*! @{ */
60309 
60310 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU)
60311 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
60312 /*! MUX_MODE - MUX Mode Select Field.
60313  *  0b1010..Select mux mode: ALT10 mux port: GPIO12_IO10 of instance: GPIO12
60314  *  0b0000..Select mux mode: ALT0 mux port: JTAG_MUX_TRSTB of instance: JTAG_MUX
60315  *  0b0001..Select mux mode: ALT1 mux port: LPUART11_CTS_B of instance: LPUART11
60316  *  0b0010..Select mux mode: ALT2 mux port: LPI2C6_SDA of instance: LPI2C6
60317  *  0b0011..Select mux mode: ALT3 mux port: MIC_BITSTREAM1 of instance: MIC
60318  *  0b0100..Select mux mode: ALT4 mux port: LPSPI6_SCK of instance: LPSPI6
60319  *  0b0101..Select mux mode: ALT5 mux port: GPIO_MUX6_IO10 of instance: GPIO_MUX6
60320  *  0b0110..Select mux mode: ALT6 mux port: LPI2C5_SCLS of instance: LPI2C5
60321  *  0b0111..Select mux mode: ALT7 mux port: SAI4_TX_SYNC of instance: SAI4
60322  *  0b1000..Select mux mode: ALT8 mux port: LPUART12_TXD of instance: LPUART12
60323  */
60324 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK)
60325 
60326 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK     (0x10U)
60327 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT    (4U)
60328 /*! SION - Software Input On Field.
60329  *  0b1..Force input path of pad GPIO_LPSR_00
60330  *  0b0..Input Path is determined by functionality
60331  */
60332 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK)
60333 /*! @} */
60334 
60335 /* The count of IOMUXC_LPSR_SW_MUX_CTL_PAD */
60336 #define IOMUXC_LPSR_SW_MUX_CTL_PAD_COUNT         (16U)
60337 
60338 /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register */
60339 /*! @{ */
60340 
60341 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK      (0x1U)
60342 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT     (0U)
60343 /*! SRE - Slew Rate Field
60344  *  0b0..Slow Slew Rate
60345  *  0b1..Fast Slew Rate
60346  */
60347 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK)
60348 
60349 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK      (0x2U)
60350 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT     (1U)
60351 /*! DSE - Drive Strength Field
60352  *  0b0..normal driver
60353  *  0b1..high driver
60354  */
60355 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK)
60356 
60357 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK      (0x4U)
60358 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT     (2U)
60359 /*! PUE - Pull Select Field
60360  *  0b0..Pull Disable
60361  *  0b1..Pull Enable
60362  */
60363 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK)
60364 
60365 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK      (0x8U)
60366 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT     (3U)
60367 /*! PUS - Pull Up / Down Config. Field
60368  *  0b0..Weak pull down
60369  *  0b1..Weak pull up
60370  */
60371 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK)
60372 
60373 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK (0x20U)
60374 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT (5U)
60375 /*! ODE_LPSR - Open Drain LPSR Field
60376  *  0b0..Disabled
60377  *  0b1..Enabled
60378  */
60379 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK)
60380 
60381 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK      (0x30000000U)
60382 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT     (28U)
60383 /*! DWP - Domain write protection
60384  *  0b00..Both cores are allowed
60385  *  0b01..CM7 is forbidden
60386  *  0b10..CM4 is forbidden
60387  *  0b11..Both cores are forbidden
60388  */
60389 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK)
60390 
60391 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK (0xC0000000U)
60392 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT (30U)
60393 /*! DWP_LOCK - Domain write protection lock
60394  *  0b00..Neither of DWP bits is locked
60395  *  0b01..The lower DWP bit is locked
60396  *  0b10..The higher DWP bit is locked
60397  *  0b11..Both DWP bits are locked
60398  */
60399 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK)
60400 /*! @} */
60401 
60402 /* The count of IOMUXC_LPSR_SW_PAD_CTL_PAD */
60403 #define IOMUXC_LPSR_SW_PAD_CTL_PAD_COUNT         (16U)
60404 
60405 /*! @name SELECT_INPUT - CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register..SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register */
60406 /*! @{ */
60407 
60408 #define IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK      (0x3U)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
60409 #define IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT     (0U)
60410 /*! DAISY - Selecting Pads Involved in Daisy Chain.
60411  *  0b00..Selecting Pad: GPIO_LPSR_00 for Mode: ALT6
60412  *  0b01..Selecting Pad: GPIO_LPSR_06 for Mode: ALT3
60413  *  0b10..Selecting Pad: GPIO_LPSR_10 for Mode: ALT8
60414  */
60415 #define IOMUXC_LPSR_SELECT_INPUT_DAISY(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK)  /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
60416 /*! @} */
60417 
60418 /* The count of IOMUXC_LPSR_SELECT_INPUT */
60419 #define IOMUXC_LPSR_SELECT_INPUT_COUNT           (24U)
60420 
60421 
60422 /*!
60423  * @}
60424  */ /* end of group IOMUXC_LPSR_Register_Masks */
60425 
60426 
60427 /* IOMUXC_LPSR - Peripheral instance base addresses */
60428 /** Peripheral IOMUXC_LPSR base address */
60429 #define IOMUXC_LPSR_BASE                         (0x40C08000u)
60430 /** Peripheral IOMUXC_LPSR base pointer */
60431 #define IOMUXC_LPSR                              ((IOMUXC_LPSR_Type *)IOMUXC_LPSR_BASE)
60432 /** Array initializer of IOMUXC_LPSR peripheral base addresses */
60433 #define IOMUXC_LPSR_BASE_ADDRS                   { IOMUXC_LPSR_BASE }
60434 /** Array initializer of IOMUXC_LPSR peripheral base pointers */
60435 #define IOMUXC_LPSR_BASE_PTRS                    { IOMUXC_LPSR }
60436 
60437 /*!
60438  * @}
60439  */ /* end of group IOMUXC_LPSR_Peripheral_Access_Layer */
60440 
60441 
60442 /* ----------------------------------------------------------------------------
60443    -- IOMUXC_LPSR_GPR Peripheral Access Layer
60444    ---------------------------------------------------------------------------- */
60445 
60446 /*!
60447  * @addtogroup IOMUXC_LPSR_GPR_Peripheral_Access_Layer IOMUXC_LPSR_GPR Peripheral Access Layer
60448  * @{
60449  */
60450 
60451 /** IOMUXC_LPSR_GPR - Register Layout Typedef */
60452 typedef struct {
60453   __IO uint32_t GPR0;                              /**< GPR0 General Purpose Register, offset: 0x0 */
60454   __IO uint32_t GPR1;                              /**< GPR1 General Purpose Register, offset: 0x4 */
60455   __IO uint32_t GPR2;                              /**< GPR2 General Purpose Register, offset: 0x8 */
60456   __IO uint32_t GPR3;                              /**< GPR3 General Purpose Register, offset: 0xC */
60457   __IO uint32_t GPR4;                              /**< GPR4 General Purpose Register, offset: 0x10 */
60458   __IO uint32_t GPR5;                              /**< GPR5 General Purpose Register, offset: 0x14 */
60459   __IO uint32_t GPR6;                              /**< GPR6 General Purpose Register, offset: 0x18 */
60460   __IO uint32_t GPR7;                              /**< GPR7 General Purpose Register, offset: 0x1C */
60461   __IO uint32_t GPR8;                              /**< GPR8 General Purpose Register, offset: 0x20 */
60462   __IO uint32_t GPR9;                              /**< GPR9 General Purpose Register, offset: 0x24 */
60463   __IO uint32_t GPR10;                             /**< GPR10 General Purpose Register, offset: 0x28 */
60464   __IO uint32_t GPR11;                             /**< GPR11 General Purpose Register, offset: 0x2C */
60465   __IO uint32_t GPR12;                             /**< GPR12 General Purpose Register, offset: 0x30 */
60466   __IO uint32_t GPR13;                             /**< GPR13 General Purpose Register, offset: 0x34 */
60467   __IO uint32_t GPR14;                             /**< GPR14 General Purpose Register, offset: 0x38 */
60468   __IO uint32_t GPR15;                             /**< GPR15 General Purpose Register, offset: 0x3C */
60469   __IO uint32_t GPR16;                             /**< GPR16 General Purpose Register, offset: 0x40 */
60470   __IO uint32_t GPR17;                             /**< GPR17 General Purpose Register, offset: 0x44 */
60471   __IO uint32_t GPR18;                             /**< GPR18 General Purpose Register, offset: 0x48 */
60472   __IO uint32_t GPR19;                             /**< GPR19 General Purpose Register, offset: 0x4C */
60473   __IO uint32_t GPR20;                             /**< GPR20 General Purpose Register, offset: 0x50 */
60474   __IO uint32_t GPR21;                             /**< GPR21 General Purpose Register, offset: 0x54 */
60475   __IO uint32_t GPR22;                             /**< GPR22 General Purpose Register, offset: 0x58 */
60476   __IO uint32_t GPR23;                             /**< GPR23 General Purpose Register, offset: 0x5C */
60477   __IO uint32_t GPR24;                             /**< GPR24 General Purpose Register, offset: 0x60 */
60478   __IO uint32_t GPR25;                             /**< GPR25 General Purpose Register, offset: 0x64 */
60479   __IO uint32_t GPR26;                             /**< GPR26 General Purpose Register, offset: 0x68 */
60480        uint8_t RESERVED_0[24];
60481   __IO uint32_t GPR33;                             /**< GPR33 General Purpose Register, offset: 0x84 */
60482   __IO uint32_t GPR34;                             /**< GPR34 General Purpose Register, offset: 0x88 */
60483   __IO uint32_t GPR35;                             /**< GPR35 General Purpose Register, offset: 0x8C */
60484   __IO uint32_t GPR36;                             /**< GPR36 General Purpose Register, offset: 0x90 */
60485   __IO uint32_t GPR37;                             /**< GPR37 General Purpose Register, offset: 0x94 */
60486   __IO uint32_t GPR38;                             /**< GPR38 General Purpose Register, offset: 0x98 */
60487   __IO uint32_t GPR39;                             /**< GPR39 General Purpose Register, offset: 0x9C */
60488   __I  uint32_t GPR40;                             /**< GPR40 General Purpose Register, offset: 0xA0 */
60489   __I  uint32_t GPR41;                             /**< GPR41 General Purpose Register, offset: 0xA4 */
60490 } IOMUXC_LPSR_GPR_Type;
60491 
60492 /* ----------------------------------------------------------------------------
60493    -- IOMUXC_LPSR_GPR Register Masks
60494    ---------------------------------------------------------------------------- */
60495 
60496 /*!
60497  * @addtogroup IOMUXC_LPSR_GPR_Register_Masks IOMUXC_LPSR_GPR Register Masks
60498  * @{
60499  */
60500 
60501 /*! @name GPR0 - GPR0 General Purpose Register */
60502 /*! @{ */
60503 
60504 #define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK (0xFFF8U)
60505 #define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT (3U)
60506 /*! CM4_INIT_VTOR_LOW - CM4 Vector table offset value lower bits out of reset */
60507 #define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK)
60508 
60509 #define IOMUXC_LPSR_GPR_GPR0_DWP_MASK            (0x30000000U)
60510 #define IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT           (28U)
60511 /*! DWP - Domain write protection
60512  *  0b00..Both cores are allowed
60513  *  0b01..CM7 is forbidden
60514  *  0b10..CM4 is forbidden
60515  *  0b11..Both cores are forbidden
60516  */
60517 #define IOMUXC_LPSR_GPR_GPR0_DWP(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_MASK)
60518 
60519 #define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK       (0xC0000000U)
60520 #define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT      (30U)
60521 /*! DWP_LOCK - Domain write protection lock
60522  *  0b00..Neither of DWP bits is locked
60523  *  0b01..The lower DWP bit is locked
60524  *  0b10..The higher DWP bit is locked
60525  *  0b11..Both DWP bits are locked
60526  */
60527 #define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK)
60528 /*! @} */
60529 
60530 /*! @name GPR1 - GPR1 General Purpose Register */
60531 /*! @{ */
60532 
60533 #define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK (0xFFFFU)
60534 #define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT (0U)
60535 /*! CM4_INIT_VTOR_HIGH - CM4 Vector table offset value higher bits out of reset */
60536 #define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK)
60537 
60538 #define IOMUXC_LPSR_GPR_GPR1_DWP_MASK            (0x30000000U)
60539 #define IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT           (28U)
60540 /*! DWP - Domain write protection
60541  *  0b00..Both cores are allowed
60542  *  0b01..CM7 is forbidden
60543  *  0b10..CM4 is forbidden
60544  *  0b11..Both cores are forbidden
60545  */
60546 #define IOMUXC_LPSR_GPR_GPR1_DWP(x)              (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_MASK)
60547 
60548 #define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK       (0xC0000000U)
60549 #define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT      (30U)
60550 /*! DWP_LOCK - Domain write protection lock
60551  *  0b00..Neither of DWP bits is locked
60552  *  0b01..The lower DWP bit is locked
60553  *  0b10..The higher DWP bit is locked
60554  *  0b11..Both DWP bits are locked
60555  */
60556 #define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK)
60557 /*! @} */
60558 
60559 /*! @name GPR2 - GPR2 General Purpose Register */
60560 /*! @{ */
60561 
60562 #define IOMUXC_LPSR_GPR_GPR2_LOCK_MASK           (0x1U)
60563 #define IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT          (0U)
60564 /*! LOCK - Lock the write to bit 31:1
60565  *  0b1..Write access to bit 31:1 is blocked
60566  *  0b0..Write access to bit 31:1 is not blocked
60567  */
60568 #define IOMUXC_LPSR_GPR_GPR2_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_LOCK_MASK)
60569 
60570 #define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK  (0xFFFFFFF8U)
60571 #define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT (3U)
60572 /*! APC_AC_R0_BOT - APC start address of memory region-0 */
60573 #define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK)
60574 /*! @} */
60575 
60576 /*! @name GPR3 - GPR3 General Purpose Register */
60577 /*! @{ */
60578 
60579 #define IOMUXC_LPSR_GPR_GPR3_LOCK_MASK           (0x1U)
60580 #define IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT          (0U)
60581 /*! LOCK - Lock the write to bit 31:1
60582  *  0b1..Write access to bit 31:1 is blocked
60583  *  0b0..Write access to bit 31:1 is not blocked
60584  */
60585 #define IOMUXC_LPSR_GPR_GPR3_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_LOCK_MASK)
60586 
60587 #define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK  (0xFFFFFFF8U)
60588 #define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT (3U)
60589 /*! APC_AC_R0_TOP - APC end address of memory region-0 */
60590 #define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK)
60591 /*! @} */
60592 
60593 /*! @name GPR4 - GPR4 General Purpose Register */
60594 /*! @{ */
60595 
60596 #define IOMUXC_LPSR_GPR_GPR4_LOCK_MASK           (0x1U)
60597 #define IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT          (0U)
60598 /*! LOCK - Lock the write to bit 31:1
60599  *  0b1..Write access to bit 31:1 is blocked
60600  *  0b0..Write access to bit 31:1 is not blocked
60601  */
60602 #define IOMUXC_LPSR_GPR_GPR4_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_LOCK_MASK)
60603 
60604 #define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK  (0xFFFFFFF8U)
60605 #define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT (3U)
60606 /*! APC_AC_R1_BOT - APC start address of memory region-1 */
60607 #define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK)
60608 /*! @} */
60609 
60610 /*! @name GPR5 - GPR5 General Purpose Register */
60611 /*! @{ */
60612 
60613 #define IOMUXC_LPSR_GPR_GPR5_LOCK_MASK           (0x1U)
60614 #define IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT          (0U)
60615 /*! LOCK - Lock the write to bit 31:1
60616  *  0b1..Write access to bit 31:1 is blocked
60617  *  0b0..Write access to bit 31:1 is not blocked
60618  */
60619 #define IOMUXC_LPSR_GPR_GPR5_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_LOCK_MASK)
60620 
60621 #define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK  (0xFFFFFFF8U)
60622 #define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT (3U)
60623 /*! APC_AC_R1_TOP - APC end address of memory region-1 */
60624 #define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK)
60625 /*! @} */
60626 
60627 /*! @name GPR6 - GPR6 General Purpose Register */
60628 /*! @{ */
60629 
60630 #define IOMUXC_LPSR_GPR_GPR6_LOCK_MASK           (0x1U)
60631 #define IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT          (0U)
60632 /*! LOCK - Lock the write to bit 31:1
60633  *  0b1..Write access to bit 31:1 is blocked
60634  *  0b0..Write access to bit 31:1 is not blocked
60635  */
60636 #define IOMUXC_LPSR_GPR_GPR6_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_LOCK_MASK)
60637 
60638 #define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK  (0xFFFFFFF8U)
60639 #define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT (3U)
60640 /*! APC_AC_R2_BOT - APC start address of memory region-2 */
60641 #define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK)
60642 /*! @} */
60643 
60644 /*! @name GPR7 - GPR7 General Purpose Register */
60645 /*! @{ */
60646 
60647 #define IOMUXC_LPSR_GPR_GPR7_LOCK_MASK           (0x1U)
60648 #define IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT          (0U)
60649 /*! LOCK - Lock the write to bit 31:1
60650  *  0b1..Write access to bit 31:1 is blocked
60651  *  0b0..Write access to bit 31:1 is not blocked
60652  */
60653 #define IOMUXC_LPSR_GPR_GPR7_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_LOCK_MASK)
60654 
60655 #define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK  (0xFFFFFFF8U)
60656 #define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT (3U)
60657 /*! APC_AC_R2_TOP - APC end address of memory region-2 */
60658 #define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK)
60659 /*! @} */
60660 
60661 /*! @name GPR8 - GPR8 General Purpose Register */
60662 /*! @{ */
60663 
60664 #define IOMUXC_LPSR_GPR_GPR8_LOCK_MASK           (0x1U)
60665 #define IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT          (0U)
60666 /*! LOCK - Lock the write to bit 31:1
60667  *  0b1..Write access to bit 31:1 is blocked
60668  *  0b0..Write access to bit 31:1 is not blocked
60669  */
60670 #define IOMUXC_LPSR_GPR_GPR8_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_LOCK_MASK)
60671 
60672 #define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK  (0xFFFFFFF8U)
60673 #define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT (3U)
60674 /*! APC_AC_R3_BOT - APC start address of memory region-3 */
60675 #define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK)
60676 /*! @} */
60677 
60678 /*! @name GPR9 - GPR9 General Purpose Register */
60679 /*! @{ */
60680 
60681 #define IOMUXC_LPSR_GPR_GPR9_LOCK_MASK           (0x1U)
60682 #define IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT          (0U)
60683 /*! LOCK - Lock the write to bit 31:1
60684  *  0b1..Write access to bit 31:1 is blocked
60685  *  0b0..Write access to bit 31:1 is not blocked
60686  */
60687 #define IOMUXC_LPSR_GPR_GPR9_LOCK(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_LOCK_MASK)
60688 
60689 #define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK  (0xFFFFFFF8U)
60690 #define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT (3U)
60691 /*! APC_AC_R3_TOP - APC end address of memory region-3 */
60692 #define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK)
60693 /*! @} */
60694 
60695 /*! @name GPR10 - GPR10 General Purpose Register */
60696 /*! @{ */
60697 
60698 #define IOMUXC_LPSR_GPR_GPR10_LOCK_MASK          (0x1U)
60699 #define IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT         (0U)
60700 /*! LOCK - Lock the write to bit 31:1
60701  *  0b1..Write access to bit 31:1 is blocked
60702  *  0b0..Write access to bit 31:1 is not blocked
60703  */
60704 #define IOMUXC_LPSR_GPR_GPR10_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_LOCK_MASK)
60705 
60706 #define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK (0xFFFFFFF8U)
60707 #define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT (3U)
60708 /*! APC_AC_R4_BOT - APC start address of memory region-4 */
60709 #define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK)
60710 /*! @} */
60711 
60712 /*! @name GPR11 - GPR11 General Purpose Register */
60713 /*! @{ */
60714 
60715 #define IOMUXC_LPSR_GPR_GPR11_LOCK_MASK          (0x1U)
60716 #define IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT         (0U)
60717 /*! LOCK - Lock the write to bit 31:1
60718  *  0b1..Write access to bit 31:1 is blocked
60719  *  0b0..Write access to bit 31:1 is not blocked
60720  */
60721 #define IOMUXC_LPSR_GPR_GPR11_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_LOCK_MASK)
60722 
60723 #define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK (0xFFFFFFF8U)
60724 #define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT (3U)
60725 /*! APC_AC_R4_TOP - APC end address of memory region-4 */
60726 #define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK)
60727 /*! @} */
60728 
60729 /*! @name GPR12 - GPR12 General Purpose Register */
60730 /*! @{ */
60731 
60732 #define IOMUXC_LPSR_GPR_GPR12_LOCK_MASK          (0x1U)
60733 #define IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT         (0U)
60734 /*! LOCK - Lock the write to bit 31:1
60735  *  0b1..Write access to bit 31:1 is blocked
60736  *  0b0..Write access to bit 31:1 is not blocked
60737  */
60738 #define IOMUXC_LPSR_GPR_GPR12_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_LOCK_MASK)
60739 
60740 #define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK (0xFFFFFFF8U)
60741 #define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT (3U)
60742 /*! APC_AC_R5_BOT - APC start address of memory region-5 */
60743 #define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK)
60744 /*! @} */
60745 
60746 /*! @name GPR13 - GPR13 General Purpose Register */
60747 /*! @{ */
60748 
60749 #define IOMUXC_LPSR_GPR_GPR13_LOCK_MASK          (0x1U)
60750 #define IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT         (0U)
60751 /*! LOCK - Lock the write to bit 31:1
60752  *  0b1..Write access to bit 31:1 is blocked
60753  *  0b0..Write access to bit 31:1 is not blocked
60754  */
60755 #define IOMUXC_LPSR_GPR_GPR13_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_LOCK_MASK)
60756 
60757 #define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK (0xFFFFFFF8U)
60758 #define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT (3U)
60759 /*! APC_AC_R5_TOP - APC end address of memory region-5 */
60760 #define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK)
60761 /*! @} */
60762 
60763 /*! @name GPR14 - GPR14 General Purpose Register */
60764 /*! @{ */
60765 
60766 #define IOMUXC_LPSR_GPR_GPR14_LOCK_MASK          (0x1U)
60767 #define IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT         (0U)
60768 /*! LOCK - Lock the write to bit 31:1
60769  *  0b1..Write access to bit 31:1 is blocked
60770  *  0b0..Write access to bit 31:1 is not blocked
60771  */
60772 #define IOMUXC_LPSR_GPR_GPR14_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_LOCK_MASK)
60773 
60774 #define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK (0xFFFFFFF8U)
60775 #define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT (3U)
60776 /*! APC_AC_R6_BOT - APC start address of memory region-6 */
60777 #define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK)
60778 /*! @} */
60779 
60780 /*! @name GPR15 - GPR15 General Purpose Register */
60781 /*! @{ */
60782 
60783 #define IOMUXC_LPSR_GPR_GPR15_LOCK_MASK          (0x1U)
60784 #define IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT         (0U)
60785 /*! LOCK - Lock the write to bit 31:1
60786  *  0b1..Write access to bit 31:1 is blocked
60787  *  0b0..Write access to bit 31:1 is not blocked
60788  */
60789 #define IOMUXC_LPSR_GPR_GPR15_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_LOCK_MASK)
60790 
60791 #define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK (0xFFFFFFF8U)
60792 #define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT (3U)
60793 /*! APC_AC_R6_TOP - APC end address of memory region-6 */
60794 #define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK)
60795 /*! @} */
60796 
60797 /*! @name GPR16 - GPR16 General Purpose Register */
60798 /*! @{ */
60799 
60800 #define IOMUXC_LPSR_GPR_GPR16_LOCK_MASK          (0x1U)
60801 #define IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT         (0U)
60802 /*! LOCK - Lock the write to bit 31:1
60803  *  0b1..Write access to bit 31:1 is blocked
60804  *  0b0..Write access to bit 31:1 is not blocked
60805  */
60806 #define IOMUXC_LPSR_GPR_GPR16_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_LOCK_MASK)
60807 
60808 #define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK (0xFFFFFFF8U)
60809 #define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT (3U)
60810 /*! APC_AC_R7_BOT - APC start address of memory region-7 */
60811 #define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK)
60812 /*! @} */
60813 
60814 /*! @name GPR17 - GPR17 General Purpose Register */
60815 /*! @{ */
60816 
60817 #define IOMUXC_LPSR_GPR_GPR17_LOCK_MASK          (0x1U)
60818 #define IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT         (0U)
60819 /*! LOCK - Lock the write to bit 31:1
60820  *  0b1..Write access to bit 31:1 is blocked
60821  *  0b0..Write access to bit 31:1 is not blocked
60822  */
60823 #define IOMUXC_LPSR_GPR_GPR17_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_LOCK_MASK)
60824 
60825 #define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK (0xFFFFFFF8U)
60826 #define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT (3U)
60827 /*! APC_AC_R7_TOP - APC end address of memory region-7 */
60828 #define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK)
60829 /*! @} */
60830 
60831 /*! @name GPR18 - GPR18 General Purpose Register */
60832 /*! @{ */
60833 
60834 #define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK (0x10U)
60835 #define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT (4U)
60836 /*! APC_R0_ENCRYPT_ENABLE - APC memory region-0 encryption enable
60837  *  0b1..Encryption enabled
60838  *  0b0..No effect
60839  */
60840 #define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK)
60841 
60842 #define IOMUXC_LPSR_GPR_GPR18_LOCK_MASK          (0xFFFF0000U)
60843 #define IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT         (16U)
60844 /*! LOCK - Lock the write to bit 15:0 */
60845 #define IOMUXC_LPSR_GPR_GPR18_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_LOCK_MASK)
60846 /*! @} */
60847 
60848 /*! @name GPR19 - GPR19 General Purpose Register */
60849 /*! @{ */
60850 
60851 #define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK (0x10U)
60852 #define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT (4U)
60853 /*! APC_R1_ENCRYPT_ENABLE - APC memory region-1 encryption enable
60854  *  0b1..Encryption enabled
60855  *  0b0..No effect
60856  */
60857 #define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK)
60858 
60859 #define IOMUXC_LPSR_GPR_GPR19_LOCK_MASK          (0xFFFF0000U)
60860 #define IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT         (16U)
60861 /*! LOCK - Lock the write to bit 15:0 */
60862 #define IOMUXC_LPSR_GPR_GPR19_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_LOCK_MASK)
60863 /*! @} */
60864 
60865 /*! @name GPR20 - GPR20 General Purpose Register */
60866 /*! @{ */
60867 
60868 #define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK (0x10U)
60869 #define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT (4U)
60870 /*! APC_R2_ENCRYPT_ENABLE - APC memory region-2 encryption enable
60871  *  0b1..Encryption enabled
60872  *  0b0..No effect
60873  */
60874 #define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK)
60875 
60876 #define IOMUXC_LPSR_GPR_GPR20_LOCK_MASK          (0xFFFF0000U)
60877 #define IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT         (16U)
60878 /*! LOCK - Lock the write to bit 15:0 */
60879 #define IOMUXC_LPSR_GPR_GPR20_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_LOCK_MASK)
60880 /*! @} */
60881 
60882 /*! @name GPR21 - GPR21 General Purpose Register */
60883 /*! @{ */
60884 
60885 #define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK (0x10U)
60886 #define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT (4U)
60887 /*! APC_R3_ENCRYPT_ENABLE - APC memory region-3 encryption enable
60888  *  0b1..Encryption enabled
60889  *  0b0..No effect
60890  */
60891 #define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK)
60892 
60893 #define IOMUXC_LPSR_GPR_GPR21_LOCK_MASK          (0xFFFF0000U)
60894 #define IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT         (16U)
60895 /*! LOCK - Lock the write to bit 15:0 */
60896 #define IOMUXC_LPSR_GPR_GPR21_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_LOCK_MASK)
60897 /*! @} */
60898 
60899 /*! @name GPR22 - GPR22 General Purpose Register */
60900 /*! @{ */
60901 
60902 #define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK (0x10U)
60903 #define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT (4U)
60904 /*! APC_R4_ENCRYPT_ENABLE - APC memory region-4 encryption enable
60905  *  0b1..Encryption enabled
60906  *  0b0..No effect
60907  */
60908 #define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK)
60909 
60910 #define IOMUXC_LPSR_GPR_GPR22_LOCK_MASK          (0xFFFF0000U)
60911 #define IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT         (16U)
60912 /*! LOCK - Lock the write to bit 15:0 */
60913 #define IOMUXC_LPSR_GPR_GPR22_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_LOCK_MASK)
60914 /*! @} */
60915 
60916 /*! @name GPR23 - GPR23 General Purpose Register */
60917 /*! @{ */
60918 
60919 #define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK (0x10U)
60920 #define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT (4U)
60921 /*! APC_R5_ENCRYPT_ENABLE - APC memory region-5 encryption enable
60922  *  0b1..Encryption enabled
60923  *  0b0..No effect
60924  */
60925 #define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK)
60926 
60927 #define IOMUXC_LPSR_GPR_GPR23_LOCK_MASK          (0xFFFF0000U)
60928 #define IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT         (16U)
60929 /*! LOCK - Lock the write to bit 15:0 */
60930 #define IOMUXC_LPSR_GPR_GPR23_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_LOCK_MASK)
60931 /*! @} */
60932 
60933 /*! @name GPR24 - GPR24 General Purpose Register */
60934 /*! @{ */
60935 
60936 #define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK (0x10U)
60937 #define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT (4U)
60938 /*! APC_R6_ENCRYPT_ENABLE - APC memory region-6 encryption enable
60939  *  0b1..Encryption enabled
60940  *  0b0..No effect
60941  */
60942 #define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK)
60943 
60944 #define IOMUXC_LPSR_GPR_GPR24_LOCK_MASK          (0xFFFF0000U)
60945 #define IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT         (16U)
60946 /*! LOCK - Lock the write to bit 15:0 */
60947 #define IOMUXC_LPSR_GPR_GPR24_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_LOCK_MASK)
60948 /*! @} */
60949 
60950 /*! @name GPR25 - GPR25 General Purpose Register */
60951 /*! @{ */
60952 
60953 #define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK (0x10U)
60954 #define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT (4U)
60955 /*! APC_R7_ENCRYPT_ENABLE - APC memory region-7 encryption enable
60956  *  0b1..Encryption enabled
60957  *  0b0..No effect
60958  */
60959 #define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK)
60960 
60961 #define IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK     (0x20U)
60962 #define IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT    (5U)
60963 /*! APC_VALID - APC global enable bit
60964  *  0b1..Enable encryption for GPRx[APC_x_ENCRYPT_ENABLE] (valid for GPR2-GPR25)
60965  *  0b0..No effect
60966  */
60967 #define IOMUXC_LPSR_GPR_GPR25_APC_VALID(x)       (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK)
60968 
60969 #define IOMUXC_LPSR_GPR_GPR25_LOCK_MASK          (0xFFFF0000U)
60970 #define IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT         (16U)
60971 /*! LOCK - Lock the write to bit 15:0 */
60972 #define IOMUXC_LPSR_GPR_GPR25_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_LOCK_MASK)
60973 /*! @} */
60974 
60975 /*! @name GPR26 - GPR26 General Purpose Register */
60976 /*! @{ */
60977 
60978 #define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK (0x1FFFFFFU)
60979 #define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT (0U)
60980 /*! CM7_INIT_VTOR - Vector table offset register out of reset. See the ARM v7-M Architecture
60981  *    Reference Manual for more information about the vector table offset register (VTOR).
60982  */
60983 #define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK)
60984 
60985 #define IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK       (0xE000000U)
60986 #define IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT      (25U)
60987 /*! FIELD_0 - General purpose bits */
60988 #define IOMUXC_LPSR_GPR_GPR26_FIELD_0(x)         (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK)
60989 
60990 #define IOMUXC_LPSR_GPR_GPR26_DWP_MASK           (0x30000000U)
60991 #define IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT          (28U)
60992 /*! DWP - Domain write protection
60993  *  0b00..Both cores are allowed
60994  *  0b01..CM7 is forbidden
60995  *  0b10..CM4 is forbidden
60996  *  0b11..Both cores are forbidden
60997  */
60998 #define IOMUXC_LPSR_GPR_GPR26_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_MASK)
60999 
61000 #define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK      (0xC0000000U)
61001 #define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT     (30U)
61002 /*! DWP_LOCK - Domain write protection lock
61003  *  0b00..Neither of DWP bits is locked
61004  *  0b01..The lower DWP bit is locked
61005  *  0b10..The higher DWP bit is locked
61006  *  0b11..Both DWP bits are locked
61007  */
61008 #define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK)
61009 /*! @} */
61010 
61011 /*! @name GPR33 - GPR33 General Purpose Register */
61012 /*! @{ */
61013 
61014 #define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK  (0x1U)
61015 #define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT (0U)
61016 /*! M4_NMI_CLEAR - Clear CM4 NMI holding register */
61017 #define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK)
61018 
61019 #define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK (0x100U)
61020 #define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT (8U)
61021 /*! USBPHY1_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register */
61022 #define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK)
61023 
61024 #define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK (0x200U)
61025 #define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT (9U)
61026 /*! USBPHY2_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register */
61027 #define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK)
61028 
61029 #define IOMUXC_LPSR_GPR_GPR33_DWP_MASK           (0x30000000U)
61030 #define IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT          (28U)
61031 /*! DWP - Domain write protection
61032  *  0b00..Both cores are allowed
61033  *  0b01..CM7 is forbidden
61034  *  0b10..CM4 is forbidden
61035  *  0b11..Both cores are forbidden
61036  */
61037 #define IOMUXC_LPSR_GPR_GPR33_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_MASK)
61038 
61039 #define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK      (0xC0000000U)
61040 #define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT     (30U)
61041 /*! DWP_LOCK - Domain write protection lock
61042  *  0b00..Neither of DWP bits is locked
61043  *  0b01..The lower DWP bit is locked
61044  *  0b10..The higher DWP bit is locked
61045  *  0b11..Both DWP bits are locked
61046  */
61047 #define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK)
61048 /*! @} */
61049 
61050 /*! @name GPR34 - GPR34 General Purpose Register */
61051 /*! @{ */
61052 
61053 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK (0x2U)
61054 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT (1U)
61055 /*! GPIO_LPSR_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection */
61056 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK)
61057 
61058 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK (0x4U)
61059 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT (2U)
61060 /*! GPIO_LPSR_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection */
61061 #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK)
61062 
61063 #define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK   (0x8U)
61064 #define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT  (3U)
61065 /*! M7_NMI_MASK - Mask CM7 NMI pin input
61066  *  0b0..NMI input from IO to CM7 is not blocked
61067  *  0b1..NMI input from IO to CM7 is blocked
61068  */
61069 #define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK)
61070 
61071 #define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK   (0x10U)
61072 #define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT  (4U)
61073 /*! M4_NMI_MASK - Mask CM4 NMI pin input
61074  *  0b0..NMI input from IO to CM4 is not blocked
61075  *  0b1..NMI input from IO to CM4 is blocked
61076  */
61077 #define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK(x)     (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK)
61078 
61079 #define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK (0x20U)
61080 #define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT (5U)
61081 /*! M4_GPC_SLEEP_SEL - CM4 sleep request selection
61082  *  0b0..CM4 SLEEPDEEP is sent to GPC
61083  *  0b1..CM4 SLEEPING is sent to GPC
61084  */
61085 #define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK)
61086 
61087 #define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK  (0x800U)
61088 #define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT (11U)
61089 /*! SEC_ERR_RESP - Security error response enable
61090  *  0b0..OKEY response
61091  *  0b1..SLVError (default)
61092  */
61093 #define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK)
61094 
61095 #define IOMUXC_LPSR_GPR_GPR34_DWP_MASK           (0x30000000U)
61096 #define IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT          (28U)
61097 /*! DWP - Domain write protection
61098  *  0b00..Both cores are allowed
61099  *  0b01..CM7 is forbidden
61100  *  0b10..CM4 is forbidden
61101  *  0b11..Both cores are forbidden
61102  */
61103 #define IOMUXC_LPSR_GPR_GPR34_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_MASK)
61104 
61105 #define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK      (0xC0000000U)
61106 #define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT     (30U)
61107 /*! DWP_LOCK - Domain write protection lock
61108  *  0b00..Neither of DWP bits is locked
61109  *  0b01..The lower DWP bit is locked
61110  *  0b10..The higher DWP bit is locked
61111  *  0b11..Both DWP bits are locked
61112  */
61113 #define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK)
61114 /*! @} */
61115 
61116 /*! @name GPR35 - GPR35 General Purpose Register */
61117 /*! @{ */
61118 
61119 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK (0x1U)
61120 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT (0U)
61121 /*! ADC1_IPG_DOZE - ADC1 doze mode
61122  *  0b0..Not in doze mode
61123  *  0b1..In doze mode
61124  */
61125 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK)
61126 
61127 #define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK (0x2U)
61128 #define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT (1U)
61129 /*! ADC1_STOP_REQ - ADC1 stop request
61130  *  0b0..Stop request off
61131  *  0b1..Stop request on
61132  */
61133 #define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK)
61134 
61135 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK (0x4U)
61136 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT (2U)
61137 /*! ADC1_IPG_STOP_MODE - ADC1 stop mode selection. This bitfield cannot change when ADC1_STOP_REQ is asserted.
61138  *  0b0..This module is functional in Stop Mode
61139  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61140  */
61141 #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK)
61142 
61143 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK (0x8U)
61144 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT (3U)
61145 /*! ADC2_IPG_DOZE - ADC2 doze mode
61146  *  0b0..Not in doze mode
61147  *  0b1..In doze mode
61148  */
61149 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK)
61150 
61151 #define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK (0x10U)
61152 #define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT (4U)
61153 /*! ADC2_STOP_REQ - ADC2 stop request
61154  *  0b0..Stop request off
61155  *  0b1..Stop request on
61156  */
61157 #define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK)
61158 
61159 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK (0x20U)
61160 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT (5U)
61161 /*! ADC2_IPG_STOP_MODE - ADC2 stop mode selection. This bitfield cannot change when ADC2_STOP_REQ is asserted.
61162  *  0b0..This module is functional in Stop Mode
61163  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61164  */
61165 #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK)
61166 
61167 #define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK (0x40U)
61168 #define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT (6U)
61169 /*! CAAM_IPG_DOZE - CAN3 doze mode
61170  *  0b0..Not in doze mode
61171  *  0b1..In doze mode
61172  */
61173 #define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK)
61174 
61175 #define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK (0x80U)
61176 #define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT (7U)
61177 /*! CAAM_STOP_REQ - CAAM stop request
61178  *  0b0..Stop request off
61179  *  0b1..Stop request on
61180  */
61181 #define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK)
61182 
61183 #define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK (0x100U)
61184 #define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT (8U)
61185 /*! CAN1_IPG_DOZE - CAN1 doze mode
61186  *  0b0..Not in doze mode
61187  *  0b1..In doze mode
61188  */
61189 #define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK)
61190 
61191 #define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK (0x200U)
61192 #define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT (9U)
61193 /*! CAN1_STOP_REQ - CAN1 stop request
61194  *  0b0..Stop request off
61195  *  0b1..Stop request on
61196  */
61197 #define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK)
61198 
61199 #define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK (0x400U)
61200 #define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT (10U)
61201 /*! CAN2_IPG_DOZE - CAN2 doze mode
61202  *  0b0..Not in doze mode
61203  *  0b1..In doze mode
61204  */
61205 #define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK)
61206 
61207 #define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK (0x800U)
61208 #define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT (11U)
61209 /*! CAN2_STOP_REQ - CAN2 stop request
61210  *  0b0..Stop request off
61211  *  0b1..Stop request on
61212  */
61213 #define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK)
61214 
61215 #define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK (0x1000U)
61216 #define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT (12U)
61217 /*! CAN3_IPG_DOZE - CAN3 doze mode
61218  *  0b0..Not in doze mode
61219  *  0b1..In doze mode
61220  */
61221 #define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK)
61222 
61223 #define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK (0x2000U)
61224 #define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT (13U)
61225 /*! CAN3_STOP_REQ - CAN3 stop request
61226  *  0b0..Stop request off
61227  *  0b1..Stop request on
61228  */
61229 #define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK)
61230 
61231 #define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK (0x8000U)
61232 #define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT (15U)
61233 /*! EDMA_STOP_REQ - EDMA stop request
61234  *  0b0..Stop request off
61235  *  0b1..Stop request on
61236  */
61237 #define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK)
61238 
61239 #define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK (0x10000U)
61240 #define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT (16U)
61241 /*! EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request
61242  *  0b0..Stop request off
61243  *  0b1..Stop request on
61244  */
61245 #define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK)
61246 
61247 #define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK (0x20000U)
61248 #define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT (17U)
61249 /*! ENET_IPG_DOZE - ENET doze mode
61250  *  0b0..Not in doze mode
61251  *  0b1..In doze mode
61252  */
61253 #define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK)
61254 
61255 #define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK (0x40000U)
61256 #define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT (18U)
61257 /*! ENET_STOP_REQ - ENET stop request
61258  *  0b0..Stop request off
61259  *  0b1..Stop request on
61260  */
61261 #define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK)
61262 
61263 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK (0x80000U)
61264 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT (19U)
61265 /*! ENET1G_IPG_DOZE - ENET1G doze mode
61266  *  0b0..Not in doze mode
61267  *  0b1..In doze mode
61268  */
61269 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK)
61270 
61271 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK (0x100000U)
61272 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT (20U)
61273 /*! ENET1G_STOP_REQ - ENET1G stop request
61274  *  0b0..Stop request off
61275  *  0b1..Stop request on
61276  */
61277 #define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK)
61278 
61279 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK (0x200000U)
61280 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT (21U)
61281 /*! FLEXIO1_IPG_DOZE - FLEXIO2 doze mode
61282  *  0b0..Not in doze mode
61283  *  0b1..In doze mode
61284  */
61285 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK)
61286 
61287 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK (0x400000U)
61288 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT (22U)
61289 /*! FLEXIO2_IPG_DOZE - FLEXIO2 doze mode
61290  *  0b0..Not in doze mode
61291  *  0b1..In doze mode
61292  */
61293 #define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK)
61294 
61295 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK (0x800000U)
61296 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT (23U)
61297 /*! FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode
61298  *  0b0..Not in doze mode
61299  *  0b1..In doze mode
61300  */
61301 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK)
61302 
61303 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK (0x1000000U)
61304 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT (24U)
61305 /*! FLEXSPI1_STOP_REQ - FLEXSPI1 stop request
61306  *  0b0..Stop request off
61307  *  0b1..Stop request on
61308  */
61309 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK)
61310 
61311 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK (0x2000000U)
61312 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT (25U)
61313 /*! FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode
61314  *  0b0..Not in doze mode
61315  *  0b1..In doze mode
61316  */
61317 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK)
61318 
61319 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK (0x4000000U)
61320 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT (26U)
61321 /*! FLEXSPI2_STOP_REQ - FLEXSPI2 stop request
61322  *  0b0..Stop request off
61323  *  0b1..Stop request on
61324  */
61325 #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK)
61326 
61327 #define IOMUXC_LPSR_GPR_GPR35_DWP_MASK           (0x30000000U)
61328 #define IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT          (28U)
61329 /*! DWP - Domain write protection
61330  *  0b00..Both cores are allowed
61331  *  0b01..CM7 is forbidden
61332  *  0b10..CM4 is forbidden
61333  *  0b11..Both cores are forbidden
61334  */
61335 #define IOMUXC_LPSR_GPR_GPR35_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_MASK)
61336 
61337 #define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK      (0xC0000000U)
61338 #define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT     (30U)
61339 /*! DWP_LOCK - Domain write protection lock
61340  *  0b00..Neither of DWP bits is locked
61341  *  0b01..The lower DWP bit is locked
61342  *  0b10..The higher DWP bit is locked
61343  *  0b11..Both DWP bits are locked
61344  */
61345 #define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK)
61346 /*! @} */
61347 
61348 /*! @name GPR36 - GPR36 General Purpose Register */
61349 /*! @{ */
61350 
61351 #define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK (0x1U)
61352 #define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT (0U)
61353 /*! GPT1_IPG_DOZE - GPT1 doze mode
61354  *  0b0..Not in doze mode
61355  *  0b1..In doze mode
61356  */
61357 #define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK)
61358 
61359 #define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK (0x2U)
61360 #define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT (1U)
61361 /*! GPT2_IPG_DOZE - GPT2 doze mode
61362  *  0b0..Not in doze mode
61363  *  0b1..In doze mode
61364  */
61365 #define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK)
61366 
61367 #define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK (0x4U)
61368 #define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT (2U)
61369 /*! GPT3_IPG_DOZE - GPT3 doze mode
61370  *  0b0..Not in doze mode
61371  *  0b1..In doze mode
61372  */
61373 #define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK)
61374 
61375 #define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK (0x8U)
61376 #define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT (3U)
61377 /*! GPT4_IPG_DOZE - GPT4 doze mode
61378  *  0b0..Not in doze mode
61379  *  0b1..In doze mode
61380  */
61381 #define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK)
61382 
61383 #define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK (0x10U)
61384 #define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT (4U)
61385 /*! GPT5_IPG_DOZE - GPT5 doze mode
61386  *  0b0..Not in doze mode
61387  *  0b1..In doze mode
61388  */
61389 #define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK)
61390 
61391 #define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK (0x20U)
61392 #define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT (5U)
61393 /*! GPT6_IPG_DOZE - GPT6 doze mode
61394  *  0b0..Not in doze mode
61395  *  0b1..In doze mode
61396  */
61397 #define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK)
61398 
61399 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK (0x40U)
61400 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT (6U)
61401 /*! LPI2C1_IPG_DOZE - LPI2C1 doze mode
61402  *  0b0..Not in doze mode
61403  *  0b1..In doze mode
61404  */
61405 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK)
61406 
61407 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK (0x80U)
61408 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT (7U)
61409 /*! LPI2C1_STOP_REQ - LPI2C1 stop request
61410  *  0b0..Stop request off
61411  *  0b1..Stop request on
61412  */
61413 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK)
61414 
61415 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK (0x100U)
61416 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT (8U)
61417 /*! LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection. This bitfield cannot change when LPI2C1_STOP_REQ is asserted.
61418  *  0b0..This module is functional in Stop Mode
61419  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61420  */
61421 #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK)
61422 
61423 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK (0x200U)
61424 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT (9U)
61425 /*! LPI2C2_IPG_DOZE - LPI2C2 doze mode
61426  *  0b0..Not in doze mode
61427  *  0b1..In doze mode
61428  */
61429 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK)
61430 
61431 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK (0x400U)
61432 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT (10U)
61433 /*! LPI2C2_STOP_REQ - LPI2C2 stop request
61434  *  0b0..Stop request off
61435  *  0b1..Stop request on
61436  */
61437 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK)
61438 
61439 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK (0x800U)
61440 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT (11U)
61441 /*! LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection. This bitfield cannot change when LPI2C2_STOP_REQ is asserted.
61442  *  0b0..This module is functional in Stop Mode
61443  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61444  */
61445 #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK)
61446 
61447 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK (0x1000U)
61448 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT (12U)
61449 /*! LPI2C3_IPG_DOZE - LPI2C3 doze mode
61450  *  0b0..Not in doze mode
61451  *  0b1..In doze mode
61452  */
61453 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK)
61454 
61455 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK (0x2000U)
61456 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT (13U)
61457 /*! LPI2C3_STOP_REQ - LPI2C3 stop request
61458  *  0b0..Stop request off
61459  *  0b1..Stop request on
61460  */
61461 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK)
61462 
61463 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK (0x4000U)
61464 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT (14U)
61465 /*! LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection. This bitfield cannot change when LPI2C3_STOP_REQ is asserted.
61466  *  0b0..This module is functional in Stop Mode
61467  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61468  */
61469 #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK)
61470 
61471 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK (0x8000U)
61472 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT (15U)
61473 /*! LPI2C4_IPG_DOZE - LPI2C4 doze mode
61474  *  0b0..Not in doze mode
61475  *  0b1..In doze mode
61476  */
61477 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK)
61478 
61479 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK (0x10000U)
61480 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT (16U)
61481 /*! LPI2C4_STOP_REQ - LPI2C4 stop request
61482  *  0b0..Stop request off
61483  *  0b1..Stop request on
61484  */
61485 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK)
61486 
61487 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK (0x20000U)
61488 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT (17U)
61489 /*! LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection. This bitfield cannot change when LPI2C4_STOP_REQ is asserted.
61490  *  0b0..This module is functional in Stop Mode
61491  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61492  */
61493 #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK)
61494 
61495 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK (0x40000U)
61496 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT (18U)
61497 /*! LPI2C5_IPG_DOZE - LPI2C5 doze mode
61498  *  0b0..Not in doze mode
61499  *  0b1..In doze mode
61500  */
61501 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK)
61502 
61503 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK (0x80000U)
61504 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT (19U)
61505 /*! LPI2C5_STOP_REQ - LPI2C5 stop request
61506  *  0b0..Stop request off
61507  *  0b1..Stop request on
61508  */
61509 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK)
61510 
61511 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK (0x100000U)
61512 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT (20U)
61513 /*! LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection. This bitfield cannot change when LPI2C5_STOP_REQ is asserted.
61514  *  0b0..This module is functional in Stop Mode
61515  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61516  */
61517 #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK)
61518 
61519 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK (0x200000U)
61520 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT (21U)
61521 /*! LPI2C6_IPG_DOZE - LPI2C6 doze mode
61522  *  0b0..Not in doze mode
61523  *  0b1..In doze mode
61524  */
61525 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK)
61526 
61527 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK (0x400000U)
61528 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT (22U)
61529 /*! LPI2C6_STOP_REQ - LPI2C6 stop request
61530  *  0b0..Stop request off
61531  *  0b1..Stop request on
61532  */
61533 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK)
61534 
61535 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK (0x800000U)
61536 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT (23U)
61537 /*! LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection. This bitfield cannot change when LPI2C6_STOP_REQ is asserted.
61538  *  0b0..This module is functional in Stop Mode
61539  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61540  */
61541 #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK)
61542 
61543 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK (0x1000000U)
61544 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT (24U)
61545 /*! LPSPI1_IPG_DOZE - LPSPI1 doze mode
61546  *  0b0..Not in doze mode
61547  *  0b1..In doze mode
61548  */
61549 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK)
61550 
61551 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK (0x2000000U)
61552 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT (25U)
61553 /*! LPSPI1_STOP_REQ - LPSPI1 stop request
61554  *  0b0..Stop request off
61555  *  0b1..Stop request on
61556  */
61557 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK)
61558 
61559 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U)
61560 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT (26U)
61561 /*! LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection. This bitfield cannot change when LPSPI1_STOP_REQ is asserted.
61562  *  0b0..This module is functional in Stop Mode
61563  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61564  */
61565 #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK)
61566 
61567 #define IOMUXC_LPSR_GPR_GPR36_DWP_MASK           (0x30000000U)
61568 #define IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT          (28U)
61569 /*! DWP - Domain write protection
61570  *  0b00..Both cores are allowed
61571  *  0b01..CM7 is forbidden
61572  *  0b10..CM4 is forbidden
61573  *  0b11..Both cores are forbidden
61574  */
61575 #define IOMUXC_LPSR_GPR_GPR36_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_MASK)
61576 
61577 #define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK      (0xC0000000U)
61578 #define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT     (30U)
61579 /*! DWP_LOCK - Domain write protection lock
61580  *  0b00..Neither of DWP bits is locked
61581  *  0b01..The lower DWP bit is locked
61582  *  0b10..The higher DWP bit is locked
61583  *  0b11..Both DWP bits are locked
61584  */
61585 #define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK)
61586 /*! @} */
61587 
61588 /*! @name GPR37 - GPR37 General Purpose Register */
61589 /*! @{ */
61590 
61591 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK (0x1U)
61592 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT (0U)
61593 /*! LPSPI2_IPG_DOZE - LPSPI2 doze mode
61594  *  0b0..Not in doze mode
61595  *  0b1..In doze mode
61596  */
61597 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK)
61598 
61599 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK (0x2U)
61600 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT (1U)
61601 /*! LPSPI2_STOP_REQ - LPSPI2 stop request
61602  *  0b0..Stop request off
61603  *  0b1..Stop request on
61604  */
61605 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK)
61606 
61607 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK (0x4U)
61608 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT (2U)
61609 /*! LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection. This bitfield cannot change when LPSPI2_STOP_REQ is asserted.
61610  *  0b0..This module is functional in Stop Mode
61611  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61612  */
61613 #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK)
61614 
61615 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK (0x8U)
61616 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT (3U)
61617 /*! LPSPI3_IPG_DOZE - LPSPI3 doze mode
61618  *  0b0..Not in doze mode
61619  *  0b1..In doze mode
61620  */
61621 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK)
61622 
61623 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK (0x10U)
61624 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT (4U)
61625 /*! LPSPI3_STOP_REQ - LPSPI3 stop request
61626  *  0b0..Stop request off
61627  *  0b1..Stop request on
61628  */
61629 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK)
61630 
61631 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK (0x20U)
61632 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT (5U)
61633 /*! LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection. This bitfield cannot change when LPSPI3_STOP_REQ is asserted.
61634  *  0b0..This module is functional in Stop Mode
61635  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61636  */
61637 #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK)
61638 
61639 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK (0x40U)
61640 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT (6U)
61641 /*! LPSPI4_IPG_DOZE - LPSPI4 doze mode
61642  *  0b0..Not in doze mode
61643  *  0b1..In doze mode
61644  */
61645 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK)
61646 
61647 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK (0x80U)
61648 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT (7U)
61649 /*! LPSPI4_STOP_REQ - LPSPI4 stop request
61650  *  0b0..Stop request off
61651  *  0b1..Stop request on
61652  */
61653 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK)
61654 
61655 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK (0x100U)
61656 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT (8U)
61657 /*! LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection. This bitfield cannot change when LPSPI4_STOP_REQ is asserted.
61658  *  0b0..This module is functional in Stop Mode
61659  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61660  */
61661 #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK)
61662 
61663 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK (0x200U)
61664 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT (9U)
61665 /*! LPSPI5_IPG_DOZE - LPSPI5 doze mode
61666  *  0b0..Not in doze mode
61667  *  0b1..In doze mode
61668  */
61669 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK)
61670 
61671 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK (0x400U)
61672 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT (10U)
61673 /*! LPSPI5_STOP_REQ - LPSPI5 stop request
61674  *  0b0..Stop request off
61675  *  0b1..Stop request on
61676  */
61677 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK)
61678 
61679 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK (0x800U)
61680 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT (11U)
61681 /*! LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection. This bitfield cannot change when LPSPI5_STOP_REQ is asserted.
61682  *  0b0..This module is functional in Stop Mode
61683  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61684  */
61685 #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK)
61686 
61687 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK (0x1000U)
61688 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT (12U)
61689 /*! LPSPI6_IPG_DOZE - LPSPI6 doze mode
61690  *  0b0..Not in doze mode
61691  *  0b1..In doze mode
61692  */
61693 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK)
61694 
61695 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK (0x2000U)
61696 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT (13U)
61697 /*! LPSPI6_STOP_REQ - LPSPI6 stop request
61698  *  0b0..Stop request off
61699  *  0b1..Stop request on
61700  */
61701 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK)
61702 
61703 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK (0x4000U)
61704 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT (14U)
61705 /*! LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection. This bitfield cannot change when LPSPI6_STOP_REQ is asserted.
61706  *  0b0..This module is functional in Stop Mode
61707  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61708  */
61709 #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK)
61710 
61711 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK (0x8000U)
61712 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT (15U)
61713 /*! LPUART1_IPG_DOZE - LPUART1 doze mode
61714  *  0b0..Not in doze mode
61715  *  0b1..In doze mode
61716  */
61717 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK)
61718 
61719 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK (0x10000U)
61720 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT (16U)
61721 /*! LPUART1_STOP_REQ - LPUART1 stop request
61722  *  0b0..Stop request off
61723  *  0b1..Stop request on
61724  */
61725 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK)
61726 
61727 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK (0x20000U)
61728 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT (17U)
61729 /*! LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection. This bitfield cannot change when LPUART1_STOP_REQ is asserted.
61730  *  0b0..This module is functional in Stop Mode
61731  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61732  */
61733 #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK)
61734 
61735 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK (0x40000U)
61736 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT (18U)
61737 /*! LPUART2_IPG_DOZE - LPUART2 doze mode
61738  *  0b0..Not in doze mode
61739  *  0b1..In doze mode
61740  */
61741 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK)
61742 
61743 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK (0x80000U)
61744 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT (19U)
61745 /*! LPUART2_STOP_REQ - LPUART2 stop request
61746  *  0b0..Stop request off
61747  *  0b1..Stop request on
61748  */
61749 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK)
61750 
61751 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK (0x100000U)
61752 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT (20U)
61753 /*! LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection. This bitfield cannot change when LPUART2_STOP_REQ is asserted.
61754  *  0b0..This module is functional in Stop Mode
61755  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61756  */
61757 #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK)
61758 
61759 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK (0x200000U)
61760 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT (21U)
61761 /*! LPUART3_IPG_DOZE - LPUART3 doze mode
61762  *  0b0..Not in doze mode
61763  *  0b1..In doze mode
61764  */
61765 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK)
61766 
61767 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK (0x400000U)
61768 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT (22U)
61769 /*! LPUART3_STOP_REQ - LPUART3 stop request
61770  *  0b0..Stop request off
61771  *  0b1..Stop request on
61772  */
61773 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK)
61774 
61775 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK (0x800000U)
61776 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT (23U)
61777 /*! LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection. This bitfield cannot change when LPUART3_STOP_REQ is asserted.
61778  *  0b0..This module is functional in Stop Mode
61779  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61780  */
61781 #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK)
61782 
61783 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK (0x1000000U)
61784 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT (24U)
61785 /*! LPUART4_IPG_DOZE - LPUART4 doze mode
61786  *  0b0..Not in doze mode
61787  *  0b1..In doze mode
61788  */
61789 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK)
61790 
61791 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK (0x2000000U)
61792 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT (25U)
61793 /*! LPUART4_STOP_REQ - LPUART4 stop request
61794  *  0b0..Stop request off
61795  *  0b1..Stop request on
61796  */
61797 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK)
61798 
61799 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK (0x4000000U)
61800 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT (26U)
61801 /*! LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection. This bitfield cannot change when LPUART4_STOP_REQ is asserted.
61802  *  0b0..This module is functional in Stop Mode
61803  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61804  */
61805 #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK)
61806 
61807 #define IOMUXC_LPSR_GPR_GPR37_DWP_MASK           (0x30000000U)
61808 #define IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT          (28U)
61809 /*! DWP - Domain write protection
61810  *  0b00..Both cores are allowed
61811  *  0b01..CM7 is forbidden
61812  *  0b10..CM4 is forbidden
61813  *  0b11..Both cores are forbidden
61814  */
61815 #define IOMUXC_LPSR_GPR_GPR37_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_MASK)
61816 
61817 #define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK      (0xC0000000U)
61818 #define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT     (30U)
61819 /*! DWP_LOCK - Domain write protection lock
61820  *  0b00..Neither of DWP bits is locked
61821  *  0b01..The lower DWP bit is locked
61822  *  0b10..The higher DWP bit is locked
61823  *  0b11..Both DWP bits are locked
61824  */
61825 #define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK)
61826 /*! @} */
61827 
61828 /*! @name GPR38 - GPR38 General Purpose Register */
61829 /*! @{ */
61830 
61831 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK (0x1U)
61832 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT (0U)
61833 /*! LPUART5_IPG_DOZE - LPUART5 doze mode
61834  *  0b0..Not in doze mode
61835  *  0b1..In doze mode
61836  */
61837 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK)
61838 
61839 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK (0x2U)
61840 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT (1U)
61841 /*! LPUART5_STOP_REQ - LPUART5 stop request
61842  *  0b0..Stop request off
61843  *  0b1..Stop request on
61844  */
61845 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK)
61846 
61847 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK (0x4U)
61848 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT (2U)
61849 /*! LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection. This bitfield cannot change when LPUART5_STOP_REQ is asserted.
61850  *  0b0..This module is functional in Stop Mode
61851  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61852  */
61853 #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK)
61854 
61855 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK (0x8U)
61856 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT (3U)
61857 /*! LPUART6_IPG_DOZE - LPUART6 doze mode
61858  *  0b0..Not in doze mode
61859  *  0b1..In doze mode
61860  */
61861 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK)
61862 
61863 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK (0x10U)
61864 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT (4U)
61865 /*! LPUART6_STOP_REQ - LPUART6 stop request
61866  *  0b0..Stop request off
61867  *  0b1..Stop request on
61868  */
61869 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK)
61870 
61871 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK (0x20U)
61872 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT (5U)
61873 /*! LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection. This bitfield cannot change when LPUART6_STOP_REQ is asserted.
61874  *  0b0..This module is functional in Stop Mode
61875  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61876  */
61877 #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK)
61878 
61879 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK (0x40U)
61880 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT (6U)
61881 /*! LPUART7_IPG_DOZE - LPUART7 doze mode
61882  *  0b0..Not in doze mode
61883  *  0b1..In doze mode
61884  */
61885 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK)
61886 
61887 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK (0x80U)
61888 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT (7U)
61889 /*! LPUART7_STOP_REQ - LPUART7 stop request
61890  *  0b0..Stop request off
61891  *  0b1..Stop request on
61892  */
61893 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK)
61894 
61895 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK (0x100U)
61896 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT (8U)
61897 /*! LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection. This bitfield cannot change when LPUART7_STOP_REQ is asserted.
61898  *  0b0..This module is functional in Stop Mode
61899  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61900  */
61901 #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK)
61902 
61903 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK (0x200U)
61904 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT (9U)
61905 /*! LPUART8_IPG_DOZE - LPUART8 doze mode
61906  *  0b0..Not in doze mode
61907  *  0b1..In doze mode
61908  */
61909 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK)
61910 
61911 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK (0x400U)
61912 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT (10U)
61913 /*! LPUART8_STOP_REQ - LPUART8 stop request
61914  *  0b0..Stop request off
61915  *  0b1..Stop request on
61916  */
61917 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK)
61918 
61919 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK (0x800U)
61920 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT (11U)
61921 /*! LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection. This bitfield cannot change when LPUART8_STOP_REQ is asserted.
61922  *  0b0..This module is functional in Stop Mode
61923  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61924  */
61925 #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK)
61926 
61927 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK (0x1000U)
61928 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT (12U)
61929 /*! LPUART9_IPG_DOZE - LPUART9 doze mode
61930  *  0b0..Not in doze mode
61931  *  0b1..In doze mode
61932  */
61933 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK)
61934 
61935 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK (0x2000U)
61936 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT (13U)
61937 /*! LPUART9_STOP_REQ - LPUART9 stop request
61938  *  0b0..Stop request off
61939  *  0b1..Stop request on
61940  */
61941 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK)
61942 
61943 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK (0x4000U)
61944 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT (14U)
61945 /*! LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection. This bitfield cannot change when LPUART9_STOP_REQ is asserted.
61946  *  0b0..This module is functional in Stop Mode
61947  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61948  */
61949 #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK)
61950 
61951 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK (0x8000U)
61952 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT (15U)
61953 /*! LPUART10_IPG_DOZE - LPUART10 doze mode
61954  *  0b0..Not in doze mode
61955  *  0b1..In doze mode
61956  */
61957 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK)
61958 
61959 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK (0x10000U)
61960 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT (16U)
61961 /*! LPUART10_STOP_REQ - LPUART10 stop request
61962  *  0b0..Stop request off
61963  *  0b1..Stop request on
61964  */
61965 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK)
61966 
61967 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK (0x20000U)
61968 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT (17U)
61969 /*! LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection. This bitfield cannot change when LPUART10_STOP_REQ is asserted.
61970  *  0b0..This module is functional in Stop Mode
61971  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61972  */
61973 #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK)
61974 
61975 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK (0x40000U)
61976 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT (18U)
61977 /*! LPUART11_IPG_DOZE - LPUART11 doze mode
61978  *  0b0..Not in doze mode
61979  *  0b1..In doze mode
61980  */
61981 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK)
61982 
61983 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK (0x80000U)
61984 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT (19U)
61985 /*! LPUART11_STOP_REQ - LPUART11 stop request
61986  *  0b0..Stop request off
61987  *  0b1..Stop request on
61988  */
61989 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK)
61990 
61991 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK (0x100000U)
61992 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT (20U)
61993 /*! LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection. This bitfield cannot change when LPUART11_STOP_REQ is asserted.
61994  *  0b0..This module is functional in Stop Mode
61995  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
61996  */
61997 #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK)
61998 
61999 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK (0x200000U)
62000 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT (21U)
62001 /*! LPUART12_IPG_DOZE - LPUART12 doze mode
62002  *  0b0..Not in doze mode
62003  *  0b1..In doze mode
62004  */
62005 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK)
62006 
62007 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK (0x400000U)
62008 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT (22U)
62009 /*! LPUART12_STOP_REQ - LPUART12 stop request
62010  *  0b0..Stop request off
62011  *  0b1..Stop request on
62012  */
62013 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK)
62014 
62015 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK (0x800000U)
62016 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT (23U)
62017 /*! LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection. This bitfield cannot change when LPUART12_STOP_REQ is asserted.
62018  *  0b0..This module is functional in Stop Mode
62019  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
62020  */
62021 #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK)
62022 
62023 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK  (0x1000000U)
62024 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT (24U)
62025 /*! MIC_IPG_DOZE - MIC doze mode
62026  *  0b0..Not in doze mode
62027  *  0b1..In doze mode
62028  */
62029 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK)
62030 
62031 #define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK  (0x2000000U)
62032 #define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT (25U)
62033 /*! MIC_STOP_REQ - MIC stop request
62034  *  0b0..Stop request off
62035  *  0b1..Stop request on
62036  */
62037 #define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK)
62038 
62039 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK (0x4000000U)
62040 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT (26U)
62041 /*! MIC_IPG_STOP_MODE - MIC stop mode selection. This bitfield cannot change when MIC_STOP_REQ is asserted.
62042  *  0b0..This module is functional in Stop Mode
62043  *  0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
62044  */
62045 #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK)
62046 
62047 #define IOMUXC_LPSR_GPR_GPR38_DWP_MASK           (0x30000000U)
62048 #define IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT          (28U)
62049 /*! DWP - Domain write protection
62050  *  0b00..Both cores are allowed
62051  *  0b01..CM7 is forbidden
62052  *  0b10..CM4 is forbidden
62053  *  0b11..Both cores are forbidden
62054  */
62055 #define IOMUXC_LPSR_GPR_GPR38_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_MASK)
62056 
62057 #define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK      (0xC0000000U)
62058 #define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT     (30U)
62059 /*! DWP_LOCK - Domain write protection lock
62060  *  0b00..Neither of DWP bits is locked
62061  *  0b01..The lower DWP bit is locked
62062  *  0b10..The higher DWP bit is locked
62063  *  0b11..Both DWP bits are locked
62064  */
62065 #define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK)
62066 /*! @} */
62067 
62068 /*! @name GPR39 - GPR39 General Purpose Register */
62069 /*! @{ */
62070 
62071 #define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK (0x2U)
62072 #define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT (1U)
62073 /*! PIT1_STOP_REQ - PIT1 stop request
62074  *  0b0..Stop request off
62075  *  0b1..Stop request on
62076  */
62077 #define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK)
62078 
62079 #define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK (0x4U)
62080 #define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT (2U)
62081 /*! PIT2_STOP_REQ - PIT2 stop request
62082  *  0b0..Stop request off
62083  *  0b1..Stop request on
62084  */
62085 #define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK)
62086 
62087 #define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK (0x8U)
62088 #define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT (3U)
62089 /*! SEMC_STOP_REQ - SEMC stop request
62090  *  0b0..Stop request off
62091  *  0b1..Stop request on
62092  */
62093 #define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK)
62094 
62095 #define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK (0x10U)
62096 #define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT (4U)
62097 /*! SIM1_IPG_DOZE - SIM1 doze mode
62098  *  0b0..Not in doze mode
62099  *  0b1..In doze mode
62100  */
62101 #define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK)
62102 
62103 #define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK (0x20U)
62104 #define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT (5U)
62105 /*! SIM2_IPG_DOZE - SIM2 doze mode
62106  *  0b0..Not in doze mode
62107  *  0b1..In doze mode
62108  */
62109 #define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK)
62110 
62111 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK (0x40U)
62112 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT (6U)
62113 /*! SNVS_HP_IPG_DOZE - SNVS_HP doze mode
62114  *  0b0..Not in doze mode
62115  *  0b1..In doze mode
62116  */
62117 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK)
62118 
62119 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK (0x80U)
62120 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT (7U)
62121 /*! SNVS_HP_STOP_REQ - SNVS_HP stop request
62122  *  0b0..Stop request off
62123  *  0b1..Stop request on
62124  */
62125 #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK)
62126 
62127 #define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK (0x100U)
62128 #define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT (8U)
62129 /*! WDOG1_IPG_DOZE - WDOG1 doze mode
62130  *  0b0..Not in doze mode
62131  *  0b1..In doze mode
62132  */
62133 #define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK)
62134 
62135 #define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK (0x200U)
62136 #define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT (9U)
62137 /*! WDOG2_IPG_DOZE - WDOG2 doze mode
62138  *  0b0..Not in doze mode
62139  *  0b1..In doze mode
62140  */
62141 #define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK)
62142 
62143 #define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK (0x400U)
62144 #define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT (10U)
62145 /*! SAI1_STOP_REQ - SAI1 stop request
62146  *  0b0..Stop request off
62147  *  0b1..Stop request on
62148  */
62149 #define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK)
62150 
62151 #define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK (0x800U)
62152 #define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT (11U)
62153 /*! SAI2_STOP_REQ - SAI2 stop request
62154  *  0b0..Stop request off
62155  *  0b1..Stop request on
62156  */
62157 #define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK)
62158 
62159 #define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK (0x1000U)
62160 #define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT (12U)
62161 /*! SAI3_STOP_REQ - SAI3 stop request
62162  *  0b0..Stop request off
62163  *  0b1..Stop request on
62164  */
62165 #define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK)
62166 
62167 #define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK (0x2000U)
62168 #define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT (13U)
62169 /*! SAI4_STOP_REQ - SAI4 stop request
62170  *  0b0..Stop request off
62171  *  0b1..Stop request on
62172  */
62173 #define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK)
62174 
62175 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U)
62176 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT (14U)
62177 /*! FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request
62178  *  0b0..Stop request off
62179  *  0b1..Stop request on
62180  */
62181 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK)
62182 
62183 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK (0x8000U)
62184 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT (15U)
62185 /*! FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request
62186  *  0b0..Stop request off
62187  *  0b1..Stop request on
62188  */
62189 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK)
62190 
62191 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U)
62192 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT (16U)
62193 /*! FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request
62194  *  0b0..Stop request off
62195  *  0b1..Stop request on
62196  */
62197 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK)
62198 
62199 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK (0x20000U)
62200 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT (17U)
62201 /*! FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request
62202  *  0b0..Stop request off
62203  *  0b1..Stop request on
62204  */
62205 #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK)
62206 
62207 #define IOMUXC_LPSR_GPR_GPR39_DWP_MASK           (0x30000000U)
62208 #define IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT          (28U)
62209 /*! DWP - Domain write protection
62210  *  0b00..Both cores are allowed
62211  *  0b01..CM7 is forbidden
62212  *  0b10..CM4 is forbidden
62213  *  0b11..Both cores are forbidden
62214  */
62215 #define IOMUXC_LPSR_GPR_GPR39_DWP(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_MASK)
62216 
62217 #define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK      (0xC0000000U)
62218 #define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT     (30U)
62219 /*! DWP_LOCK - Domain write protection lock
62220  *  0b00..Neither of DWP bits is locked
62221  *  0b01..The lower DWP bit is locked
62222  *  0b10..The higher DWP bit is locked
62223  *  0b11..Both DWP bits are locked
62224  */
62225 #define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK(x)        (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK)
62226 /*! @} */
62227 
62228 /*! @name GPR40 - GPR40 General Purpose Register */
62229 /*! @{ */
62230 
62231 #define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK (0x1U)
62232 #define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT (0U)
62233 /*! ADC1_STOP_ACK - ADC1 stop acknowledge */
62234 #define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK)
62235 
62236 #define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK (0x2U)
62237 #define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT (1U)
62238 /*! ADC2_STOP_ACK - ADC2 stop acknowledge */
62239 #define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK)
62240 
62241 #define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK (0x4U)
62242 #define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT (2U)
62243 /*! CAAM_STOP_ACK - CAAM stop acknowledge */
62244 #define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK)
62245 
62246 #define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK (0x8U)
62247 #define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT (3U)
62248 /*! CAN1_STOP_ACK - CAN1 stop acknowledge */
62249 #define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK)
62250 
62251 #define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK (0x10U)
62252 #define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT (4U)
62253 /*! CAN2_STOP_ACK - CAN2 stop acknowledge */
62254 #define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK)
62255 
62256 #define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK (0x20U)
62257 #define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT (5U)
62258 /*! CAN3_STOP_ACK - CAN3 stop acknowledge */
62259 #define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK)
62260 
62261 #define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK (0x40U)
62262 #define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT (6U)
62263 /*! EDMA_STOP_ACK - EDMA stop acknowledge */
62264 #define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK)
62265 
62266 #define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK (0x80U)
62267 #define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT (7U)
62268 /*! EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge */
62269 #define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK)
62270 
62271 #define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK (0x100U)
62272 #define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT (8U)
62273 /*! ENET_STOP_ACK - ENET stop acknowledge */
62274 #define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK)
62275 
62276 #define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK (0x200U)
62277 #define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT (9U)
62278 /*! ENET1G_STOP_ACK - ENET1G stop acknowledge */
62279 #define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK)
62280 
62281 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK (0x400U)
62282 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT (10U)
62283 /*! FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge */
62284 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK)
62285 
62286 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK (0x800U)
62287 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT (11U)
62288 /*! FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge */
62289 #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK)
62290 
62291 #define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK (0x1000U)
62292 #define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT (12U)
62293 /*! LPI2C1_STOP_ACK - LPI2C1 stop acknowledge */
62294 #define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK)
62295 
62296 #define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK (0x2000U)
62297 #define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT (13U)
62298 /*! LPI2C2_STOP_ACK - LPI2C2 stop acknowledge */
62299 #define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK)
62300 
62301 #define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK (0x4000U)
62302 #define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT (14U)
62303 /*! LPI2C3_STOP_ACK - LPI2C3 stop acknowledge */
62304 #define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK)
62305 
62306 #define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK (0x8000U)
62307 #define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT (15U)
62308 /*! LPI2C4_STOP_ACK - LPI2C4 stop acknowledge */
62309 #define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK)
62310 
62311 #define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK (0x10000U)
62312 #define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT (16U)
62313 /*! LPI2C5_STOP_ACK - LPI2C5 stop acknowledge */
62314 #define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK)
62315 
62316 #define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK (0x20000U)
62317 #define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT (17U)
62318 /*! LPI2C6_STOP_ACK - LPI2C6 stop acknowledge */
62319 #define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK)
62320 
62321 #define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK (0x40000U)
62322 #define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT (18U)
62323 /*! LPSPI1_STOP_ACK - LPSPI1 stop acknowledge */
62324 #define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK)
62325 
62326 #define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK (0x80000U)
62327 #define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT (19U)
62328 /*! LPSPI2_STOP_ACK - LPSPI2 stop acknowledge */
62329 #define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK)
62330 
62331 #define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK (0x100000U)
62332 #define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT (20U)
62333 /*! LPSPI3_STOP_ACK - LPSPI3 stop acknowledge */
62334 #define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK)
62335 
62336 #define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK (0x200000U)
62337 #define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT (21U)
62338 /*! LPSPI4_STOP_ACK - LPSPI4 stop acknowledge */
62339 #define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK)
62340 
62341 #define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK (0x400000U)
62342 #define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT (22U)
62343 /*! LPSPI5_STOP_ACK - LPSPI5 stop acknowledge */
62344 #define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK)
62345 
62346 #define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK (0x800000U)
62347 #define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT (23U)
62348 /*! LPSPI6_STOP_ACK - LPSPI6 stop acknowledge */
62349 #define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK)
62350 
62351 #define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK (0x1000000U)
62352 #define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT (24U)
62353 /*! LPUART1_STOP_ACK - LPUART1 stop acknowledge */
62354 #define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK)
62355 
62356 #define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK (0x2000000U)
62357 #define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT (25U)
62358 /*! LPUART2_STOP_ACK - LPUART2 stop acknowledge */
62359 #define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK)
62360 
62361 #define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK (0x4000000U)
62362 #define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT (26U)
62363 /*! LPUART3_STOP_ACK - LPUART3 stop acknowledge */
62364 #define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK)
62365 
62366 #define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK (0x8000000U)
62367 #define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT (27U)
62368 /*! LPUART4_STOP_ACK - LPUART4 stop acknowledge */
62369 #define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK)
62370 
62371 #define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK (0x10000000U)
62372 #define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT (28U)
62373 /*! LPUART5_STOP_ACK - LPUART5 stop acknowledge */
62374 #define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK)
62375 
62376 #define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK (0x20000000U)
62377 #define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT (29U)
62378 /*! LPUART6_STOP_ACK - LPUART6 stop acknowledge */
62379 #define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK)
62380 
62381 #define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK (0x40000000U)
62382 #define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT (30U)
62383 /*! LPUART7_STOP_ACK - LPUART7 stop acknowledge */
62384 #define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK)
62385 
62386 #define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK (0x80000000U)
62387 #define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT (31U)
62388 /*! LPUART8_STOP_ACK - LPUART8 stop acknowledge */
62389 #define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK)
62390 /*! @} */
62391 
62392 /*! @name GPR41 - GPR41 General Purpose Register */
62393 /*! @{ */
62394 
62395 #define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK (0x1U)
62396 #define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT (0U)
62397 /*! LPUART9_STOP_ACK - LPUART9 stop acknowledge */
62398 #define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK)
62399 
62400 #define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK (0x2U)
62401 #define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT (1U)
62402 /*! LPUART10_STOP_ACK - LPUART10 stop acknowledge */
62403 #define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK)
62404 
62405 #define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK (0x4U)
62406 #define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT (2U)
62407 /*! LPUART11_STOP_ACK - LPUART11 stop acknowledge */
62408 #define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK)
62409 
62410 #define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK (0x8U)
62411 #define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT (3U)
62412 /*! LPUART12_STOP_ACK - LPUART12 stop acknowledge */
62413 #define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK)
62414 
62415 #define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK  (0x10U)
62416 #define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT (4U)
62417 /*! MIC_STOP_ACK - MIC stop acknowledge */
62418 #define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK(x)    (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK)
62419 
62420 #define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK (0x20U)
62421 #define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT (5U)
62422 /*! PIT1_STOP_ACK - PIT1 stop acknowledge */
62423 #define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK)
62424 
62425 #define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK (0x40U)
62426 #define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT (6U)
62427 /*! PIT2_STOP_ACK - PIT2 stop acknowledge */
62428 #define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK)
62429 
62430 #define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK (0x80U)
62431 #define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT (7U)
62432 /*! SEMC_STOP_ACK - SEMC stop acknowledge */
62433 #define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK)
62434 
62435 #define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK (0x100U)
62436 #define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT (8U)
62437 /*! SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge */
62438 #define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK)
62439 
62440 #define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK (0x200U)
62441 #define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT (9U)
62442 /*! SAI1_STOP_ACK - SAI1 stop acknowledge */
62443 #define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK)
62444 
62445 #define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK (0x400U)
62446 #define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT (10U)
62447 /*! SAI2_STOP_ACK - SAI2 stop acknowledge */
62448 #define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK)
62449 
62450 #define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK (0x800U)
62451 #define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT (11U)
62452 /*! SAI3_STOP_ACK - SAI3 stop acknowledge */
62453 #define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK)
62454 
62455 #define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK (0x1000U)
62456 #define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT (12U)
62457 /*! SAI4_STOP_ACK - SAI4 stop acknowledge */
62458 #define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK)
62459 
62460 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U)
62461 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT (13U)
62462 /*! FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain */
62463 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK)
62464 
62465 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK (0x4000U)
62466 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT (14U)
62467 /*! FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain */
62468 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK)
62469 
62470 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U)
62471 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT (15U)
62472 /*! FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain */
62473 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK)
62474 
62475 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK (0x10000U)
62476 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT (16U)
62477 /*! FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain */
62478 #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK)
62479 
62480 #define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK (0x1000000U)
62481 #define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT (24U)
62482 /*! ROM_READ_LOCKED - ROM read lock status bit */
62483 #define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK)
62484 /*! @} */
62485 
62486 
62487 /*!
62488  * @}
62489  */ /* end of group IOMUXC_LPSR_GPR_Register_Masks */
62490 
62491 
62492 /* IOMUXC_LPSR_GPR - Peripheral instance base addresses */
62493 /** Peripheral IOMUXC_LPSR_GPR base address */
62494 #define IOMUXC_LPSR_GPR_BASE                     (0x40C0C000u)
62495 /** Peripheral IOMUXC_LPSR_GPR base pointer */
62496 #define IOMUXC_LPSR_GPR                          ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE)
62497 /** Array initializer of IOMUXC_LPSR_GPR peripheral base addresses */
62498 #define IOMUXC_LPSR_GPR_BASE_ADDRS               { IOMUXC_LPSR_GPR_BASE }
62499 /** Array initializer of IOMUXC_LPSR_GPR peripheral base pointers */
62500 #define IOMUXC_LPSR_GPR_BASE_PTRS                { IOMUXC_LPSR_GPR }
62501 
62502 /*!
62503  * @}
62504  */ /* end of group IOMUXC_LPSR_GPR_Peripheral_Access_Layer */
62505 
62506 
62507 /* ----------------------------------------------------------------------------
62508    -- IOMUXC_SNVS Peripheral Access Layer
62509    ---------------------------------------------------------------------------- */
62510 
62511 /*!
62512  * @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer
62513  * @{
62514  */
62515 
62516 /** IOMUXC_SNVS - Register Layout Typedef */
62517 typedef struct {
62518   __IO uint32_t SW_MUX_CTL_PAD_WAKEUP_DIG;         /**< SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register, offset: 0x0 */
62519   __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG;    /**< SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register, offset: 0x4 */
62520   __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG;  /**< SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register, offset: 0x8 */
62521   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register, offset: 0xC */
62522   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register, offset: 0x10 */
62523   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register, offset: 0x14 */
62524   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register, offset: 0x18 */
62525   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register, offset: 0x1C */
62526   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register, offset: 0x20 */
62527   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register, offset: 0x24 */
62528   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register, offset: 0x28 */
62529   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register, offset: 0x2C */
62530   __IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG;   /**< SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register, offset: 0x30 */
62531   __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE_DIG;      /**< SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register, offset: 0x34 */
62532   __IO uint32_t SW_PAD_CTL_PAD_POR_B_DIG;          /**< SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register, offset: 0x38 */
62533   __IO uint32_t SW_PAD_CTL_PAD_ONOFF_DIG;          /**< SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register, offset: 0x3C */
62534   __IO uint32_t SW_PAD_CTL_PAD_WAKEUP_DIG;         /**< SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register, offset: 0x40 */
62535   __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG;    /**< SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register, offset: 0x44 */
62536   __IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG;  /**< SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register, offset: 0x48 */
62537   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register, offset: 0x4C */
62538   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register, offset: 0x50 */
62539   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register, offset: 0x54 */
62540   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register, offset: 0x58 */
62541   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register, offset: 0x5C */
62542   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register, offset: 0x60 */
62543   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register, offset: 0x64 */
62544   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register, offset: 0x68 */
62545   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register, offset: 0x6C */
62546   __IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG;   /**< SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register, offset: 0x70 */
62547 } IOMUXC_SNVS_Type;
62548 
62549 /* ----------------------------------------------------------------------------
62550    -- IOMUXC_SNVS Register Masks
62551    ---------------------------------------------------------------------------- */
62552 
62553 /*!
62554  * @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks
62555  * @{
62556  */
62557 
62558 /*! @name SW_MUX_CTL_PAD_WAKEUP_DIG - SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register */
62559 /*! @{ */
62560 
62561 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK (0x7U)
62562 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT (0U)
62563 /*! MUX_MODE - MUX Mode Select Field.
62564  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO00 of instance: GPIO13
62565  *  0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: NMI_GLUE
62566  */
62567 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK)
62568 
62569 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK (0x10U)
62570 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT (4U)
62571 /*! SION - Software Input On Field.
62572  *  0b1..Force input path of pad WAKEUP_DIG
62573  *  0b0..Input Path is determined by functionality
62574  */
62575 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK)
62576 /*! @} */
62577 
62578 /*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG - SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register */
62579 /*! @{ */
62580 
62581 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK (0x7U)
62582 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT (0U)
62583 /*! MUX_MODE - MUX Mode Select Field.
62584  *  0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: SNVS_LP
62585  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO01 of instance: GPIO13
62586  */
62587 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK)
62588 
62589 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK (0x10U)
62590 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT (4U)
62591 /*! SION - Software Input On Field.
62592  *  0b1..Force input path of pad PMIC_ON_REQ_DIG
62593  *  0b0..Input Path is determined by functionality
62594  */
62595 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK)
62596 /*! @} */
62597 
62598 /*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG - SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register */
62599 /*! @{ */
62600 
62601 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK (0x7U)
62602 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT (0U)
62603 /*! MUX_MODE - MUX Mode Select Field.
62604  *  0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: CCM
62605  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO02 of instance: GPIO13
62606  */
62607 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK)
62608 
62609 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK (0x10U)
62610 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT (4U)
62611 /*! SION - Software Input On Field.
62612  *  0b1..Force input path of pad PMIC_STBY_REQ_DIG
62613  *  0b0..Input Path is determined by functionality
62614  */
62615 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK)
62616 /*! @} */
62617 
62618 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register */
62619 /*! @{ */
62620 
62621 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK (0x7U)
62622 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT (0U)
62623 /*! MUX_MODE - MUX Mode Select Field.
62624  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER0 of instance: SNVS_LP
62625  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO03 of instance: GPIO13
62626  */
62627 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK)
62628 
62629 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK (0x10U)
62630 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT (4U)
62631 /*! SION - Software Input On Field.
62632  *  0b1..Force input path of pad GPIO_SNVS_00_DIG
62633  *  0b0..Input Path is determined by functionality
62634  */
62635 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK)
62636 /*! @} */
62637 
62638 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register */
62639 /*! @{ */
62640 
62641 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK (0x7U)
62642 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT (0U)
62643 /*! MUX_MODE - MUX Mode Select Field.
62644  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER1 of instance: SNVS_LP
62645  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO04 of instance: GPIO13
62646  */
62647 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK)
62648 
62649 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK (0x10U)
62650 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT (4U)
62651 /*! SION - Software Input On Field.
62652  *  0b1..Force input path of pad GPIO_SNVS_01_DIG
62653  *  0b0..Input Path is determined by functionality
62654  */
62655 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK)
62656 /*! @} */
62657 
62658 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register */
62659 /*! @{ */
62660 
62661 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK (0x7U)
62662 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT (0U)
62663 /*! MUX_MODE - MUX Mode Select Field.
62664  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER2 of instance: SNVS_LP
62665  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO05 of instance: GPIO13
62666  */
62667 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK)
62668 
62669 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK (0x10U)
62670 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT (4U)
62671 /*! SION - Software Input On Field.
62672  *  0b1..Force input path of pad GPIO_SNVS_02_DIG
62673  *  0b0..Input Path is determined by functionality
62674  */
62675 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK)
62676 /*! @} */
62677 
62678 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register */
62679 /*! @{ */
62680 
62681 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK (0x7U)
62682 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT (0U)
62683 /*! MUX_MODE - MUX Mode Select Field.
62684  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER3 of instance: SNVS_LP
62685  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO06 of instance: GPIO13
62686  */
62687 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK)
62688 
62689 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK (0x10U)
62690 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT (4U)
62691 /*! SION - Software Input On Field.
62692  *  0b1..Force input path of pad GPIO_SNVS_03_DIG
62693  *  0b0..Input Path is determined by functionality
62694  */
62695 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK)
62696 /*! @} */
62697 
62698 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register */
62699 /*! @{ */
62700 
62701 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK (0x7U)
62702 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT (0U)
62703 /*! MUX_MODE - MUX Mode Select Field.
62704  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER4 of instance: SNVS_LP
62705  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO07 of instance: GPIO13
62706  */
62707 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK)
62708 
62709 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK (0x10U)
62710 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT (4U)
62711 /*! SION - Software Input On Field.
62712  *  0b1..Force input path of pad GPIO_SNVS_04_DIG
62713  *  0b0..Input Path is determined by functionality
62714  */
62715 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK)
62716 /*! @} */
62717 
62718 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register */
62719 /*! @{ */
62720 
62721 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK (0x7U)
62722 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT (0U)
62723 /*! MUX_MODE - MUX Mode Select Field.
62724  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER5 of instance: SNVS_LP
62725  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO08 of instance: GPIO13
62726  */
62727 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK)
62728 
62729 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK (0x10U)
62730 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT (4U)
62731 /*! SION - Software Input On Field.
62732  *  0b1..Force input path of pad GPIO_SNVS_05_DIG
62733  *  0b0..Input Path is determined by functionality
62734  */
62735 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK)
62736 /*! @} */
62737 
62738 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register */
62739 /*! @{ */
62740 
62741 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK (0x7U)
62742 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT (0U)
62743 /*! MUX_MODE - MUX Mode Select Field.
62744  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER6 of instance: SNVS_LP
62745  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO09 of instance: GPIO13
62746  */
62747 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK)
62748 
62749 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK (0x10U)
62750 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT (4U)
62751 /*! SION - Software Input On Field.
62752  *  0b1..Force input path of pad GPIO_SNVS_06_DIG
62753  *  0b0..Input Path is determined by functionality
62754  */
62755 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK)
62756 /*! @} */
62757 
62758 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register */
62759 /*! @{ */
62760 
62761 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK (0x7U)
62762 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT (0U)
62763 /*! MUX_MODE - MUX Mode Select Field.
62764  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER7 of instance: SNVS_LP
62765  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO10 of instance: GPIO13
62766  */
62767 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK)
62768 
62769 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK (0x10U)
62770 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT (4U)
62771 /*! SION - Software Input On Field.
62772  *  0b1..Force input path of pad GPIO_SNVS_07_DIG
62773  *  0b0..Input Path is determined by functionality
62774  */
62775 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK)
62776 /*! @} */
62777 
62778 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register */
62779 /*! @{ */
62780 
62781 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK (0x7U)
62782 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT (0U)
62783 /*! MUX_MODE - MUX Mode Select Field.
62784  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER8 of instance: SNVS_LP
62785  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO11 of instance: GPIO13
62786  */
62787 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK)
62788 
62789 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK (0x10U)
62790 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT (4U)
62791 /*! SION - Software Input On Field.
62792  *  0b1..Force input path of pad GPIO_SNVS_08_DIG
62793  *  0b0..Input Path is determined by functionality
62794  */
62795 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK)
62796 /*! @} */
62797 
62798 /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register */
62799 /*! @{ */
62800 
62801 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK (0x7U)
62802 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT (0U)
62803 /*! MUX_MODE - MUX Mode Select Field.
62804  *  0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER9 of instance: SNVS_LP
62805  *  0b101..Select mux mode: ALT5 mux port: GPIO13_IO12 of instance: GPIO13
62806  */
62807 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK)
62808 
62809 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK (0x10U)
62810 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT (4U)
62811 /*! SION - Software Input On Field.
62812  *  0b1..Force input path of pad GPIO_SNVS_09_DIG
62813  *  0b0..Input Path is determined by functionality
62814  */
62815 #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK)
62816 /*! @} */
62817 
62818 /*! @name SW_PAD_CTL_PAD_TEST_MODE_DIG - SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register */
62819 /*! @{ */
62820 
62821 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK (0x4U)
62822 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT (2U)
62823 /*! PUE - Pull / Keep Select Field
62824  *  0b0..Pull Disable
62825  *  0b1..Pull Enable
62826  */
62827 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK)
62828 
62829 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK (0x8U)
62830 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT (3U)
62831 /*! PUS - Pull Up / Down Config. Field
62832  *  0b0..Weak pull down
62833  *  0b1..Weak pull up
62834  */
62835 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK)
62836 
62837 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK (0x30000000U)
62838 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT (28U)
62839 /*! DWP - Domain write protection
62840  *  0b00..Both cores are allowed
62841  *  0b01..CM7 is forbidden
62842  *  0b10..CM4 is forbidden
62843  *  0b11..Both cores are forbidden
62844  */
62845 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK)
62846 
62847 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK (0xC0000000U)
62848 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT (30U)
62849 /*! DWP_LOCK - Domain write protection lock
62850  *  0b00..Neither of DWP bits is locked
62851  *  0b01..The lower DWP bit is locked
62852  *  0b10..The higher DWP bit is locked
62853  *  0b11..Both DWP bits are locked
62854  */
62855 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK)
62856 /*! @} */
62857 
62858 /*! @name SW_PAD_CTL_PAD_POR_B_DIG - SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register */
62859 /*! @{ */
62860 
62861 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK (0x4U)
62862 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT (2U)
62863 /*! PUE - Pull / Keep Select Field
62864  *  0b0..Pull Disable
62865  *  0b1..Pull Enable
62866  */
62867 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK)
62868 
62869 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK (0x8U)
62870 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT (3U)
62871 /*! PUS - Pull Up / Down Config. Field
62872  *  0b0..Weak pull down
62873  *  0b1..Weak pull up
62874  */
62875 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK)
62876 
62877 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK (0x30000000U)
62878 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT (28U)
62879 /*! DWP - Domain write protection
62880  *  0b00..Both cores are allowed
62881  *  0b01..CM7 is forbidden
62882  *  0b10..CM4 is forbidden
62883  *  0b11..Both cores are forbidden
62884  */
62885 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK)
62886 
62887 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK (0xC0000000U)
62888 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT (30U)
62889 /*! DWP_LOCK - Domain write protection lock
62890  *  0b00..Neither of DWP bits is locked
62891  *  0b01..The lower DWP bit is locked
62892  *  0b10..The higher DWP bit is locked
62893  *  0b11..Both DWP bits are locked
62894  */
62895 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK)
62896 /*! @} */
62897 
62898 /*! @name SW_PAD_CTL_PAD_ONOFF_DIG - SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register */
62899 /*! @{ */
62900 
62901 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK (0x4U)
62902 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT (2U)
62903 /*! PUE - Pull / Keep Select Field
62904  *  0b0..Pull Disable
62905  *  0b1..Pull Enable
62906  */
62907 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK)
62908 
62909 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK (0x8U)
62910 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT (3U)
62911 /*! PUS - Pull Up / Down Config. Field
62912  *  0b0..Weak pull down
62913  *  0b1..Weak pull up
62914  */
62915 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK)
62916 
62917 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK (0x30000000U)
62918 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT (28U)
62919 /*! DWP - Domain write protection
62920  *  0b00..Both cores are allowed
62921  *  0b01..CM7 is forbidden
62922  *  0b10..CM4 is forbidden
62923  *  0b11..Both cores are forbidden
62924  */
62925 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK)
62926 
62927 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK (0xC0000000U)
62928 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT (30U)
62929 /*! DWP_LOCK - Domain write protection lock
62930  *  0b00..Neither of DWP bits is locked
62931  *  0b01..The lower DWP bit is locked
62932  *  0b10..The higher DWP bit is locked
62933  *  0b11..Both DWP bits are locked
62934  */
62935 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK)
62936 /*! @} */
62937 
62938 /*! @name SW_PAD_CTL_PAD_WAKEUP_DIG - SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register */
62939 /*! @{ */
62940 
62941 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK (0x4U)
62942 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT (2U)
62943 /*! PUE - Pull / Keep Select Field
62944  *  0b0..Pull Disable
62945  *  0b1..Pull Enable
62946  */
62947 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK)
62948 
62949 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK (0x8U)
62950 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT (3U)
62951 /*! PUS - Pull Up / Down Config. Field
62952  *  0b0..Weak pull down
62953  *  0b1..Weak pull up
62954  */
62955 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK)
62956 
62957 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK (0x40U)
62958 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT (6U)
62959 /*! ODE_SNVS - Open Drain SNVS Field
62960  *  0b0..Disabled
62961  *  0b1..Enabled
62962  */
62963 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK)
62964 
62965 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK (0x30000000U)
62966 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT (28U)
62967 /*! DWP - Domain write protection
62968  *  0b00..Both cores are allowed
62969  *  0b01..CM7 is forbidden
62970  *  0b10..CM4 is forbidden
62971  *  0b11..Both cores are forbidden
62972  */
62973 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK)
62974 
62975 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK (0xC0000000U)
62976 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT (30U)
62977 /*! DWP_LOCK - Domain write protection lock
62978  *  0b00..Neither of DWP bits is locked
62979  *  0b01..The lower DWP bit is locked
62980  *  0b10..The higher DWP bit is locked
62981  *  0b11..Both DWP bits are locked
62982  */
62983 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK)
62984 /*! @} */
62985 
62986 /*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG - SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register */
62987 /*! @{ */
62988 
62989 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK (0x4U)
62990 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT (2U)
62991 /*! PUE - Pull / Keep Select Field
62992  *  0b0..Pull Disable
62993  *  0b1..Pull Enable
62994  */
62995 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK)
62996 
62997 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK (0x8U)
62998 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT (3U)
62999 /*! PUS - Pull Up / Down Config. Field
63000  *  0b0..Weak pull down
63001  *  0b1..Weak pull up
63002  */
63003 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK)
63004 
63005 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK (0x40U)
63006 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT (6U)
63007 /*! ODE_SNVS - Open Drain SNVS Field
63008  *  0b0..Disabled
63009  *  0b1..Enabled
63010  */
63011 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK)
63012 
63013 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK (0x30000000U)
63014 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT (28U)
63015 /*! DWP - Domain write protection
63016  *  0b00..Both cores are allowed
63017  *  0b01..CM7 is forbidden
63018  *  0b10..CM4 is forbidden
63019  *  0b11..Both cores are forbidden
63020  */
63021 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK)
63022 
63023 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK (0xC0000000U)
63024 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT (30U)
63025 /*! DWP_LOCK - Domain write protection lock
63026  *  0b00..Neither of DWP bits is locked
63027  *  0b01..The lower DWP bit is locked
63028  *  0b10..The higher DWP bit is locked
63029  *  0b11..Both DWP bits are locked
63030  */
63031 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK)
63032 /*! @} */
63033 
63034 /*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG - SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register */
63035 /*! @{ */
63036 
63037 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK (0x4U)
63038 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT (2U)
63039 /*! PUE - Pull / Keep Select Field
63040  *  0b0..Pull Disable
63041  *  0b1..Pull Enable
63042  */
63043 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK)
63044 
63045 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK (0x8U)
63046 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT (3U)
63047 /*! PUS - Pull Up / Down Config. Field
63048  *  0b0..Weak pull down
63049  *  0b1..Weak pull up
63050  */
63051 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK)
63052 
63053 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK (0x40U)
63054 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT (6U)
63055 /*! ODE_SNVS - Open Drain SNVS Field
63056  *  0b0..Disabled
63057  *  0b1..Enabled
63058  */
63059 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK)
63060 
63061 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK (0x30000000U)
63062 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT (28U)
63063 /*! DWP - Domain write protection
63064  *  0b00..Both cores are allowed
63065  *  0b01..CM7 is forbidden
63066  *  0b10..CM4 is forbidden
63067  *  0b11..Both cores are forbidden
63068  */
63069 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK)
63070 
63071 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK (0xC0000000U)
63072 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT (30U)
63073 /*! DWP_LOCK - Domain write protection lock
63074  *  0b00..Neither of DWP bits is locked
63075  *  0b01..The lower DWP bit is locked
63076  *  0b10..The higher DWP bit is locked
63077  *  0b11..Both DWP bits are locked
63078  */
63079 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK)
63080 /*! @} */
63081 
63082 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register */
63083 /*! @{ */
63084 
63085 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK (0x4U)
63086 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT (2U)
63087 /*! PUE - Pull / Keep Select Field
63088  *  0b0..Pull Disable
63089  *  0b1..Pull Enable
63090  */
63091 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK)
63092 
63093 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK (0x8U)
63094 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT (3U)
63095 /*! PUS - Pull Up / Down Config. Field
63096  *  0b0..Weak pull down
63097  *  0b1..Weak pull up
63098  */
63099 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK)
63100 
63101 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK (0x40U)
63102 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT (6U)
63103 /*! ODE_SNVS - Open Drain SNVS Field
63104  *  0b0..Disabled
63105  *  0b1..Enabled
63106  */
63107 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK)
63108 
63109 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK (0x30000000U)
63110 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT (28U)
63111 /*! DWP - Domain write protection
63112  *  0b00..Both cores are allowed
63113  *  0b01..CM7 is forbidden
63114  *  0b10..CM4 is forbidden
63115  *  0b11..Both cores are forbidden
63116  */
63117 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK)
63118 
63119 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK (0xC0000000U)
63120 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT (30U)
63121 /*! DWP_LOCK - Domain write protection lock
63122  *  0b00..Neither of DWP bits is locked
63123  *  0b01..The lower DWP bit is locked
63124  *  0b10..The higher DWP bit is locked
63125  *  0b11..Both DWP bits are locked
63126  */
63127 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK)
63128 /*! @} */
63129 
63130 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register */
63131 /*! @{ */
63132 
63133 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK (0x4U)
63134 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT (2U)
63135 /*! PUE - Pull / Keep Select Field
63136  *  0b0..Pull Disable
63137  *  0b1..Pull Enable
63138  */
63139 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK)
63140 
63141 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK (0x8U)
63142 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT (3U)
63143 /*! PUS - Pull Up / Down Config. Field
63144  *  0b0..Weak pull down
63145  *  0b1..Weak pull up
63146  */
63147 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK)
63148 
63149 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK (0x40U)
63150 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT (6U)
63151 /*! ODE_SNVS - Open Drain SNVS Field
63152  *  0b0..Disabled
63153  *  0b1..Enabled
63154  */
63155 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK)
63156 
63157 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK (0x30000000U)
63158 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT (28U)
63159 /*! DWP - Domain write protection
63160  *  0b00..Both cores are allowed
63161  *  0b01..CM7 is forbidden
63162  *  0b10..CM4 is forbidden
63163  *  0b11..Both cores are forbidden
63164  */
63165 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK)
63166 
63167 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK (0xC0000000U)
63168 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT (30U)
63169 /*! DWP_LOCK - Domain write protection lock
63170  *  0b00..Neither of DWP bits is locked
63171  *  0b01..The lower DWP bit is locked
63172  *  0b10..The higher DWP bit is locked
63173  *  0b11..Both DWP bits are locked
63174  */
63175 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK)
63176 /*! @} */
63177 
63178 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register */
63179 /*! @{ */
63180 
63181 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK (0x4U)
63182 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT (2U)
63183 /*! PUE - Pull / Keep Select Field
63184  *  0b0..Pull Disable
63185  *  0b1..Pull Enable
63186  */
63187 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK)
63188 
63189 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK (0x8U)
63190 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT (3U)
63191 /*! PUS - Pull Up / Down Config. Field
63192  *  0b0..Weak pull down
63193  *  0b1..Weak pull up
63194  */
63195 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK)
63196 
63197 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK (0x40U)
63198 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT (6U)
63199 /*! ODE_SNVS - Open Drain SNVS Field
63200  *  0b0..Disabled
63201  *  0b1..Enabled
63202  */
63203 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK)
63204 
63205 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK (0x30000000U)
63206 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT (28U)
63207 /*! DWP - Domain write protection
63208  *  0b00..Both cores are allowed
63209  *  0b01..CM7 is forbidden
63210  *  0b10..CM4 is forbidden
63211  *  0b11..Both cores are forbidden
63212  */
63213 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK)
63214 
63215 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK (0xC0000000U)
63216 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT (30U)
63217 /*! DWP_LOCK - Domain write protection lock
63218  *  0b00..Neither of DWP bits is locked
63219  *  0b01..The lower DWP bit is locked
63220  *  0b10..The higher DWP bit is locked
63221  *  0b11..Both DWP bits are locked
63222  */
63223 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK)
63224 /*! @} */
63225 
63226 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register */
63227 /*! @{ */
63228 
63229 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK (0x4U)
63230 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT (2U)
63231 /*! PUE - Pull / Keep Select Field
63232  *  0b0..Pull Disable
63233  *  0b1..Pull Enable
63234  */
63235 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK)
63236 
63237 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK (0x8U)
63238 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT (3U)
63239 /*! PUS - Pull Up / Down Config. Field
63240  *  0b0..Weak pull down
63241  *  0b1..Weak pull up
63242  */
63243 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK)
63244 
63245 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK (0x40U)
63246 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT (6U)
63247 /*! ODE_SNVS - Open Drain SNVS Field
63248  *  0b0..Disabled
63249  *  0b1..Enabled
63250  */
63251 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK)
63252 
63253 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK (0x30000000U)
63254 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT (28U)
63255 /*! DWP - Domain write protection
63256  *  0b00..Both cores are allowed
63257  *  0b01..CM7 is forbidden
63258  *  0b10..CM4 is forbidden
63259  *  0b11..Both cores are forbidden
63260  */
63261 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK)
63262 
63263 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK (0xC0000000U)
63264 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT (30U)
63265 /*! DWP_LOCK - Domain write protection lock
63266  *  0b00..Neither of DWP bits is locked
63267  *  0b01..The lower DWP bit is locked
63268  *  0b10..The higher DWP bit is locked
63269  *  0b11..Both DWP bits are locked
63270  */
63271 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK)
63272 /*! @} */
63273 
63274 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register */
63275 /*! @{ */
63276 
63277 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK (0x4U)
63278 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT (2U)
63279 /*! PUE - Pull / Keep Select Field
63280  *  0b0..Pull Disable
63281  *  0b1..Pull Enable
63282  */
63283 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK)
63284 
63285 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK (0x8U)
63286 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT (3U)
63287 /*! PUS - Pull Up / Down Config. Field
63288  *  0b0..Weak pull down
63289  *  0b1..Weak pull up
63290  */
63291 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK)
63292 
63293 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK (0x40U)
63294 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT (6U)
63295 /*! ODE_SNVS - Open Drain SNVS Field
63296  *  0b0..Disabled
63297  *  0b1..Enabled
63298  */
63299 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK)
63300 
63301 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK (0x30000000U)
63302 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT (28U)
63303 /*! DWP - Domain write protection
63304  *  0b00..Both cores are allowed
63305  *  0b01..CM7 is forbidden
63306  *  0b10..CM4 is forbidden
63307  *  0b11..Both cores are forbidden
63308  */
63309 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK)
63310 
63311 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK (0xC0000000U)
63312 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT (30U)
63313 /*! DWP_LOCK - Domain write protection lock
63314  *  0b00..Neither of DWP bits is locked
63315  *  0b01..The lower DWP bit is locked
63316  *  0b10..The higher DWP bit is locked
63317  *  0b11..Both DWP bits are locked
63318  */
63319 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK)
63320 /*! @} */
63321 
63322 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register */
63323 /*! @{ */
63324 
63325 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK (0x4U)
63326 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT (2U)
63327 /*! PUE - Pull / Keep Select Field
63328  *  0b0..Pull Disable
63329  *  0b1..Pull Enable
63330  */
63331 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK)
63332 
63333 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK (0x8U)
63334 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT (3U)
63335 /*! PUS - Pull Up / Down Config. Field
63336  *  0b0..Weak pull down
63337  *  0b1..Weak pull up
63338  */
63339 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK)
63340 
63341 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK (0x40U)
63342 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT (6U)
63343 /*! ODE_SNVS - Open Drain SNVS Field
63344  *  0b0..Disabled
63345  *  0b1..Enabled
63346  */
63347 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK)
63348 
63349 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK (0x30000000U)
63350 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT (28U)
63351 /*! DWP - Domain write protection
63352  *  0b00..Both cores are allowed
63353  *  0b01..CM7 is forbidden
63354  *  0b10..CM4 is forbidden
63355  *  0b11..Both cores are forbidden
63356  */
63357 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK)
63358 
63359 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK (0xC0000000U)
63360 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT (30U)
63361 /*! DWP_LOCK - Domain write protection lock
63362  *  0b00..Neither of DWP bits is locked
63363  *  0b01..The lower DWP bit is locked
63364  *  0b10..The higher DWP bit is locked
63365  *  0b11..Both DWP bits are locked
63366  */
63367 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK)
63368 /*! @} */
63369 
63370 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register */
63371 /*! @{ */
63372 
63373 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK (0x4U)
63374 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT (2U)
63375 /*! PUE - Pull / Keep Select Field
63376  *  0b0..Pull Disable
63377  *  0b1..Pull Enable
63378  */
63379 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK)
63380 
63381 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK (0x8U)
63382 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT (3U)
63383 /*! PUS - Pull Up / Down Config. Field
63384  *  0b0..Weak pull down
63385  *  0b1..Weak pull up
63386  */
63387 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK)
63388 
63389 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK (0x40U)
63390 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT (6U)
63391 /*! ODE_SNVS - Open Drain SNVS Field
63392  *  0b0..Disabled
63393  *  0b1..Enabled
63394  */
63395 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK)
63396 
63397 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK (0x30000000U)
63398 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT (28U)
63399 /*! DWP - Domain write protection
63400  *  0b00..Both cores are allowed
63401  *  0b01..CM7 is forbidden
63402  *  0b10..CM4 is forbidden
63403  *  0b11..Both cores are forbidden
63404  */
63405 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK)
63406 
63407 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK (0xC0000000U)
63408 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT (30U)
63409 /*! DWP_LOCK - Domain write protection lock
63410  *  0b00..Neither of DWP bits is locked
63411  *  0b01..The lower DWP bit is locked
63412  *  0b10..The higher DWP bit is locked
63413  *  0b11..Both DWP bits are locked
63414  */
63415 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK)
63416 /*! @} */
63417 
63418 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register */
63419 /*! @{ */
63420 
63421 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK (0x4U)
63422 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT (2U)
63423 /*! PUE - Pull / Keep Select Field
63424  *  0b0..Pull Disable
63425  *  0b1..Pull Enable
63426  */
63427 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK)
63428 
63429 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK (0x8U)
63430 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT (3U)
63431 /*! PUS - Pull Up / Down Config. Field
63432  *  0b0..Weak pull down
63433  *  0b1..Weak pull up
63434  */
63435 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK)
63436 
63437 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK (0x40U)
63438 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT (6U)
63439 /*! ODE_SNVS - Open Drain SNVS Field
63440  *  0b0..Disabled
63441  *  0b1..Enabled
63442  */
63443 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK)
63444 
63445 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK (0x30000000U)
63446 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT (28U)
63447 /*! DWP - Domain write protection
63448  *  0b00..Both cores are allowed
63449  *  0b01..CM7 is forbidden
63450  *  0b10..CM4 is forbidden
63451  *  0b11..Both cores are forbidden
63452  */
63453 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK)
63454 
63455 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK (0xC0000000U)
63456 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT (30U)
63457 /*! DWP_LOCK - Domain write protection lock
63458  *  0b00..Neither of DWP bits is locked
63459  *  0b01..The lower DWP bit is locked
63460  *  0b10..The higher DWP bit is locked
63461  *  0b11..Both DWP bits are locked
63462  */
63463 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK)
63464 /*! @} */
63465 
63466 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register */
63467 /*! @{ */
63468 
63469 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK (0x4U)
63470 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT (2U)
63471 /*! PUE - Pull / Keep Select Field
63472  *  0b0..Pull Disable
63473  *  0b1..Pull Enable
63474  */
63475 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK)
63476 
63477 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK (0x8U)
63478 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT (3U)
63479 /*! PUS - Pull Up / Down Config. Field
63480  *  0b0..Weak pull down
63481  *  0b1..Weak pull up
63482  */
63483 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK)
63484 
63485 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK (0x40U)
63486 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT (6U)
63487 /*! ODE_SNVS - Open Drain SNVS Field
63488  *  0b0..Disabled
63489  *  0b1..Enabled
63490  */
63491 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK)
63492 
63493 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK (0x30000000U)
63494 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT (28U)
63495 /*! DWP - Domain write protection
63496  *  0b00..Both cores are allowed
63497  *  0b01..CM7 is forbidden
63498  *  0b10..CM4 is forbidden
63499  *  0b11..Both cores are forbidden
63500  */
63501 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK)
63502 
63503 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK (0xC0000000U)
63504 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT (30U)
63505 /*! DWP_LOCK - Domain write protection lock
63506  *  0b00..Neither of DWP bits is locked
63507  *  0b01..The lower DWP bit is locked
63508  *  0b10..The higher DWP bit is locked
63509  *  0b11..Both DWP bits are locked
63510  */
63511 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK)
63512 /*! @} */
63513 
63514 /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register */
63515 /*! @{ */
63516 
63517 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK (0x4U)
63518 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT (2U)
63519 /*! PUE - Pull / Keep Select Field
63520  *  0b0..Pull Disable
63521  *  0b1..Pull Enable
63522  */
63523 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK)
63524 
63525 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK (0x8U)
63526 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT (3U)
63527 /*! PUS - Pull Up / Down Config. Field
63528  *  0b0..Weak pull down
63529  *  0b1..Weak pull up
63530  */
63531 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK)
63532 
63533 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK (0x40U)
63534 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT (6U)
63535 /*! ODE_SNVS - Open Drain SNVS Field
63536  *  0b0..Disabled
63537  *  0b1..Enabled
63538  */
63539 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK)
63540 
63541 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK (0x30000000U)
63542 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT (28U)
63543 /*! DWP - Domain write protection
63544  *  0b00..Both cores are allowed
63545  *  0b01..CM7 is forbidden
63546  *  0b10..CM4 is forbidden
63547  *  0b11..Both cores are forbidden
63548  */
63549 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK)
63550 
63551 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK (0xC0000000U)
63552 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT (30U)
63553 /*! DWP_LOCK - Domain write protection lock
63554  *  0b00..Neither of DWP bits is locked
63555  *  0b01..The lower DWP bit is locked
63556  *  0b10..The higher DWP bit is locked
63557  *  0b11..Both DWP bits are locked
63558  */
63559 #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK)
63560 /*! @} */
63561 
63562 
63563 /*!
63564  * @}
63565  */ /* end of group IOMUXC_SNVS_Register_Masks */
63566 
63567 
63568 /* IOMUXC_SNVS - Peripheral instance base addresses */
63569 /** Peripheral IOMUXC_SNVS base address */
63570 #define IOMUXC_SNVS_BASE                         (0x40C94000u)
63571 /** Peripheral IOMUXC_SNVS base pointer */
63572 #define IOMUXC_SNVS                              ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)
63573 /** Array initializer of IOMUXC_SNVS peripheral base addresses */
63574 #define IOMUXC_SNVS_BASE_ADDRS                   { IOMUXC_SNVS_BASE }
63575 /** Array initializer of IOMUXC_SNVS peripheral base pointers */
63576 #define IOMUXC_SNVS_BASE_PTRS                    { IOMUXC_SNVS }
63577 
63578 /*!
63579  * @}
63580  */ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */
63581 
63582 
63583 /* ----------------------------------------------------------------------------
63584    -- IOMUXC_SNVS_GPR Peripheral Access Layer
63585    ---------------------------------------------------------------------------- */
63586 
63587 /*!
63588  * @addtogroup IOMUXC_SNVS_GPR_Peripheral_Access_Layer IOMUXC_SNVS_GPR Peripheral Access Layer
63589  * @{
63590  */
63591 
63592 /** IOMUXC_SNVS_GPR - Register Layout Typedef */
63593 typedef struct {
63594   __IO uint32_t GPR[32];                           /**< GPR0 General Purpose Register, array offset: 0x0, array step: 0x4 */
63595   __IO uint32_t GPR32;                             /**< GPR32 General Purpose Register, offset: 0x80 */
63596   __IO uint32_t GPR33;                             /**< GPR33 General Purpose Register, offset: 0x84 */
63597   __IO uint32_t GPR34;                             /**< GPR34 General Purpose Register, offset: 0x88 */
63598   __IO uint32_t GPR35;                             /**< GPR35 General Purpose Register, offset: 0x8C */
63599   __IO uint32_t GPR36;                             /**< GPR36 General Purpose Register, offset: 0x90 */
63600   __IO uint32_t GPR37;                             /**< GPR37 General Purpose Register, offset: 0x94 */
63601 } IOMUXC_SNVS_GPR_Type;
63602 
63603 /* ----------------------------------------------------------------------------
63604    -- IOMUXC_SNVS_GPR Register Masks
63605    ---------------------------------------------------------------------------- */
63606 
63607 /*!
63608  * @addtogroup IOMUXC_SNVS_GPR_Register_Masks IOMUXC_SNVS_GPR Register Masks
63609  * @{
63610  */
63611 
63612 /*! @name GPR - GPR0 General Purpose Register */
63613 /*! @{ */
63614 
63615 #define IOMUXC_SNVS_GPR_GPR_GPR_MASK             (0xFFFFFFFFU)
63616 #define IOMUXC_SNVS_GPR_GPR_GPR_SHIFT            (0U)
63617 /*! GPR - General purpose bits */
63618 #define IOMUXC_SNVS_GPR_GPR_GPR(x)               (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR_GPR_MASK)
63619 /*! @} */
63620 
63621 /* The count of IOMUXC_SNVS_GPR_GPR */
63622 #define IOMUXC_SNVS_GPR_GPR_COUNT                (32U)
63623 
63624 /*! @name GPR32 - GPR32 General Purpose Register */
63625 /*! @{ */
63626 
63627 #define IOMUXC_SNVS_GPR_GPR32_GPR_MASK           (0xFFFEU)
63628 #define IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT          (1U)
63629 /*! GPR - General purpose bits */
63630 #define IOMUXC_SNVS_GPR_GPR32_GPR(x)             (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_GPR_MASK)
63631 
63632 #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK          (0xFFFF0000U)
63633 #define IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT         (16U)
63634 /*! LOCK - Lock the write to bit 15:0 */
63635 #define IOMUXC_SNVS_GPR_GPR32_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
63636 /*! @} */
63637 
63638 /*! @name GPR33 - GPR33 General Purpose Register */
63639 /*! @{ */
63640 
63641 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
63642 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
63643 /*! DCDC_STATUS_CAPT_CLR - DCDC captured status clear
63644  *  0b0..No change
63645  *  0b1..Clear the 3 bits of DCDC captured status: DCDC_OVER_VOL, DCDC_OVER_CUR, and DCDC_IN_LOW_VOL
63646  */
63647 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK)
63648 
63649 #define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK (0x4U)
63650 #define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT (2U)
63651 /*! SNVS_BYPASS_EN - SNVS LDO_SNVS_ANA bypass enable
63652  *  0b1..Enable bypass
63653  *  0b0..Disable bypass
63654  */
63655 #define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK)
63656 
63657 #define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK (0x10000U)
63658 #define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT (16U)
63659 /*! DCDC_IN_LOW_VOL - DCDC_IN low voltage detect
63660  *  0b1..Voltage on DCDC_IN is lower than 2.6V
63661  *  0b0..Voltage on DCDC_IN is higher than 2.6V
63662  */
63663 #define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK)
63664 
63665 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK (0x20000U)
63666 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT (17U)
63667 /*! DCDC_OVER_CUR - DCDC output over current alert
63668  *  0b1..Overcurrent on DCDC output
63669  *  0b0..No Overcurrent on DCDC output
63670  */
63671 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK)
63672 
63673 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK (0x40000U)
63674 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT (18U)
63675 /*! DCDC_OVER_VOL - DCDC output over voltage alert
63676  *  0b1..Overvoltage on DCDC VDDLP0 or VDDLP8 output
63677  *  0b0..No Overvoltage on DCDC VDDLP0 or VDDLP8 output
63678  */
63679 #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL(x)   (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK)
63680 
63681 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK (0x80000U)
63682 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT (19U)
63683 /*! DCDC_STS_DC_OK - DCDC status OK
63684  *  0b0..DCDC is settling
63685  *  0b1..DCDC already settled
63686  */
63687 #define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK(x)  (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK)
63688 
63689 #define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK (0x100000U)
63690 #define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT (20U)
63691 /*! SNVS_XTAL_CLK_OK - 32K OSC ok flag
63692  *  0b1..32K oscillator is stable into normal operation
63693  *  0b0..32K oscillator is NOT stable into normal operation
63694  */
63695 #define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK)
63696 /*! @} */
63697 
63698 /*! @name GPR34 - GPR34 General Purpose Register */
63699 /*! @{ */
63700 
63701 #define IOMUXC_SNVS_GPR_GPR34_LOCK_MASK          (0x1U)
63702 #define IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT         (0U)
63703 /*! LOCK - Lock the write to bit 31:1
63704  *  0b0..Write access is not blocked
63705  *  0b1..Write access is blocked
63706  */
63707 #define IOMUXC_SNVS_GPR_GPR34_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_LOCK_MASK)
63708 
63709 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK (0x2U)
63710 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT (1U)
63711 /*! SNVS_CORE_VOLT_DET_TRIM_SEL - SNVS core voltage detect trim select
63712  *  0b0..The trimming codes are selected from eFuse
63713  *  0b1..The trimming codes of core voltage detectors used to change the voltage falling trip point are selected from SNVS_CORE_VOLT_DET_TRIM
63714  */
63715 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK)
63716 
63717 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK (0xCU)
63718 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT (2U)
63719 /*! SNVS_CORE_VOLT_DET_TRIM - SNVS core voltage detect trim */
63720 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK)
63721 
63722 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK (0x80U)
63723 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT (7U)
63724 /*! SNVS_CLK_DET_TRIM_SEL - SNVS clock detect trim select
63725  *  0b0..The trimming codes are selected from eFuse
63726  *  0b1..The trimming codes of clock detector used to change the boundary frequencies are selected from SNVS_CLK_DET_TRIM
63727  */
63728 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK)
63729 
63730 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK (0xFF00U)
63731 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT (8U)
63732 /*! SNVS_CLK_DET_TRIM - SNVS clock detect trim bits */
63733 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK)
63734 
63735 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK (0x30000U)
63736 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT (16U)
63737 /*! SNVS_CLK_DET_OFFSET_HIGH - SNVS clock detect offset of high boundary frequency
63738  *  0b00..No change (Default)
63739  *  0b01..Add +5 to the Trim
63740  *  0b10..Add +10 to the trim
63741  *  0b11..Add -5 to the Trim
63742  */
63743 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK)
63744 
63745 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK (0xC0000U)
63746 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT (18U)
63747 /*! SNVS_CLK_DET_OFFSET_LOW - SNVS clock detect offset of low boundary frequency
63748  *  0b00..No change (Default)
63749  *  0b01..Add +5 to the Trim
63750  *  0b10..Add +10 to the trim
63751  *  0b11..Add -5 to the Trim
63752  */
63753 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK)
63754 
63755 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK (0x800000U)
63756 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT (23U)
63757 /*! SNVS_CAP_TRIM_SEL - SNVS OSC load capacitor trim select
63758  *  0b0..The trimming codes are selected from eFuse
63759  *  0b1..The trimming codes are used from SNVS_OSC_CAP_TRIM (osc32k's load capacitor)
63760  */
63761 #define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK)
63762 
63763 #define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK (0xF000000U)
63764 #define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT (24U)
63765 /*! SNVS_OSC_CAP_TRIM - SNVS OSC load capacitor trim */
63766 #define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK)
63767 /*! @} */
63768 
63769 /*! @name GPR35 - GPR35 General Purpose Register */
63770 /*! @{ */
63771 
63772 #define IOMUXC_SNVS_GPR_GPR35_LOCK_MASK          (0x1U)
63773 #define IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT         (0U)
63774 /*! LOCK - Lock the write to bit 31:1
63775  *  0b0..Write access is not blocked
63776  *  0b1..Write access is blocked
63777  */
63778 #define IOMUXC_SNVS_GPR_GPR35_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_LOCK_MASK)
63779 
63780 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK (0x8U)
63781 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT (3U)
63782 /*! SNVS_VOLT_DET_TRIM_SEL - SNVS voltage detect trim select
63783  *  0b0..The trimming codes are selected from eFuse
63784  *  0b1..The trimming codes of voltage detectors to change the voltage boundaries in battery voltage detecting are selected from SNVS_VOLT_DET_TRIM
63785  */
63786 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK)
63787 
63788 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK (0xFF0U)
63789 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT (4U)
63790 /*! SNVS_VOLT_DET_TRIM - SNVS voltage detect trim */
63791 #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK)
63792 
63793 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK (0x8000U)
63794 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT (15U)
63795 /*! SNVS_TEMP_DET_TRIM_SEL - SNVS temperature detect trim select
63796  *  0b0..The trimming codes are selected from eFuse
63797  *  0b1..The trimming codes to define the temperature boundaries of temperature detector are selected from SNVS_TEMP_DET_TRIM
63798  */
63799 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK)
63800 
63801 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK (0xFFF0000U)
63802 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT (16U)
63803 /*! SNVS_TEMP_DET_TRIM - SNVS temperature detect trim */
63804 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK)
63805 
63806 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK (0x30000000U)
63807 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT (28U)
63808 /*! SNVS_TEMP_DET_OFFSET_HIGH - SNVS temperature detect offset of high temperature boundary
63809  *  0b00..No change (Default)
63810  *  0b01..Add +5 to the Trim
63811  *  0b10..Add +10 to the trim
63812  *  0b11..Add -5 to the Trim
63813  */
63814 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK)
63815 
63816 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK (0xC0000000U)
63817 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT (30U)
63818 /*! SNVS_TEMP_DET_OFFSET_LOW - SNVS temperature detect offset of low temperature boundary
63819  *  0b00..No change (Default)
63820  *  0b01..Add +5 to the Trim
63821  *  0b10..Add +10 to the trim
63822  *  0b11..Add -5 to the Trim
63823  */
63824 #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK)
63825 /*! @} */
63826 
63827 /*! @name GPR36 - GPR36 General Purpose Register */
63828 /*! @{ */
63829 
63830 #define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK (0x800000U)
63831 #define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT (23U)
63832 /*! SNVSDIG_SNVS1P8_ISO_EN - SNVS RAM isolation enable bit
63833  *  0b1..Enable the isolation to avoid extra leakage power before SNVS SRAM peripheral power or LDO_SNVS_DIG is switched off
63834  *  0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG and SNVS SRAM peripheral power is back)
63835  */
63836 #define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK)
63837 
63838 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK (0x4000000U)
63839 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT (26U)
63840 /*! SNVS_SRAM_SLEEP - SNVS SRAM power-down enable bit
63841  *  0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG is enabled)
63842  *  0b1..SNVS SRAM can go in Shutdown/ Periphery Off Array On/ Periphery On Array Off mode. In addition, this bit
63843  *       ensures power-up without stuck-at /high DC current states and hence must be held to 1 during wake-up, so
63844  *       this bit is default high.
63845  */
63846 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK)
63847 
63848 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK (0x8000000U)
63849 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT (27U)
63850 /*! SNVS_SRAM_STDBY - SNVS SRAM standby enable bit
63851  *  0b1..SNVS SRAM enters low leakage state and large drivers are switched OFF
63852  *  0b0..SNVS SRAM does not enter low leakage state
63853  */
63854 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK)
63855 
63856 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK (0x10000000U)
63857 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT (28U)
63858 /*! SNVS_SRAM_PSWLARGEMP_FORCE - SNVS SRAM large switch control bit for peripheral
63859  *  0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained)
63860  *  0b0..Switch on SNVS SRAM power for peripheral
63861  */
63862 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK)
63863 
63864 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK (0x20000000U)
63865 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT (29U)
63866 /*! SNVS_SRAM_PSWLARGE - SNVS SRAM large switch control bit
63867  *  0b1..Switch off SNVS SRAM power for peripheral and array
63868  *  0b0..Switch on SNVS SRAM power for peripheral and array
63869  */
63870 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK)
63871 
63872 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK (0x40000000U)
63873 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT (30U)
63874 /*! SNVS_SRAM_PSWSMALLMP_FORCE - SNVS SRAM small switch control bit for peripheral
63875  *  0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained)
63876  *  0b0..Switch on SNVS SRAM power for peripheral
63877  */
63878 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK)
63879 
63880 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK (0x80000000U)
63881 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT (31U)
63882 /*! SNVS_SRAM_PSWSMALL - SNVS SRAM small switch control bit
63883  *  0b1..Switch off SNVS SRAM power for peripheral and array
63884  *  0b0..Switch on SNVS SRAM power for peripheral and array
63885  */
63886 #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK)
63887 /*! @} */
63888 
63889 /*! @name GPR37 - GPR37 General Purpose Register */
63890 /*! @{ */
63891 
63892 #define IOMUXC_SNVS_GPR_GPR37_LOCK_MASK          (0x1U)
63893 #define IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT         (0U)
63894 /*! LOCK - Lock the write to bit 31:1
63895  *  0b0..Write access is not blocked
63896  *  0b1..Write access is blocked
63897  */
63898 #define IOMUXC_SNVS_GPR_GPR37_LOCK(x)            (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_LOCK_MASK)
63899 
63900 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK (0x7FEU)
63901 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT (1U)
63902 /*! SNVS_TAMPER_PUE - SNVS tamper detect pin pull enable bit */
63903 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK)
63904 
63905 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK (0x1FF800U)
63906 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT (11U)
63907 /*! SNVS_TAMPER_PUS - SNVS tamper detect pin pull selection bit */
63908 #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK)
63909 /*! @} */
63910 
63911 
63912 /*!
63913  * @}
63914  */ /* end of group IOMUXC_SNVS_GPR_Register_Masks */
63915 
63916 
63917 /* IOMUXC_SNVS_GPR - Peripheral instance base addresses */
63918 /** Peripheral IOMUXC_SNVS_GPR base address */
63919 #define IOMUXC_SNVS_GPR_BASE                     (0x40C98000u)
63920 /** Peripheral IOMUXC_SNVS_GPR base pointer */
63921 #define IOMUXC_SNVS_GPR                          ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)
63922 /** Array initializer of IOMUXC_SNVS_GPR peripheral base addresses */
63923 #define IOMUXC_SNVS_GPR_BASE_ADDRS               { IOMUXC_SNVS_GPR_BASE }
63924 /** Array initializer of IOMUXC_SNVS_GPR peripheral base pointers */
63925 #define IOMUXC_SNVS_GPR_BASE_PTRS                { IOMUXC_SNVS_GPR }
63926 
63927 /*!
63928  * @}
63929  */ /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */
63930 
63931 
63932 /* ----------------------------------------------------------------------------
63933    -- IPS_DOMAIN Peripheral Access Layer
63934    ---------------------------------------------------------------------------- */
63935 
63936 /*!
63937  * @addtogroup IPS_DOMAIN_Peripheral_Access_Layer IPS_DOMAIN Peripheral Access Layer
63938  * @{
63939  */
63940 
63941 /** IPS_DOMAIN - Register Layout Typedef */
63942 typedef struct {
63943   struct {                                         /* offset: 0x0, array step: 0x10 */
63944     __IO uint32_t SLOT_CTRL;                         /**< Slot Control Register, array offset: 0x0, array step: 0x10 */
63945          uint8_t RESERVED_0[12];
63946   } SLOT_CTRL[38];
63947 } IPS_DOMAIN_Type;
63948 
63949 /* ----------------------------------------------------------------------------
63950    -- IPS_DOMAIN Register Masks
63951    ---------------------------------------------------------------------------- */
63952 
63953 /*!
63954  * @addtogroup IPS_DOMAIN_Register_Masks IPS_DOMAIN Register Masks
63955  * @{
63956  */
63957 
63958 /*! @name SLOT_CTRL - Slot Control Register */
63959 /*! @{ */
63960 
63961 #define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK (0xFU)
63962 #define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT (0U)
63963 /*! LOCKED_DOMAIN_ID - Domain ID of the slot to be locked */
63964 #define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK)
63965 
63966 #define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK    (0x8000U)
63967 #define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT   (15U)
63968 /*! DOMAIN_LOCK - Lock domain ID of this slot
63969  *  0b0..Do not lock the domain ID
63970  *  0b1..Lock the domain ID
63971  */
63972 #define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK(x)      (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK)
63973 
63974 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK (0x10000U)
63975 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT (16U)
63976 /*! ALLOW_NONSECURE - Allow non-secure write access to this domain control register or domain register
63977  *  0b0..Do not allow non-secure write access
63978  *  0b1..Allow non-secure write access
63979  */
63980 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE(x)  (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK)
63981 
63982 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK     (0x20000U)
63983 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT    (17U)
63984 /*! ALLOW_USER - Allow user write access to this domain control register or domain register
63985  *  0b0..Do not allow user write access
63986  *  0b1..Allow user write access
63987  */
63988 #define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER(x)       (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK)
63989 
63990 #define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK   (0x80000000U)
63991 #define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT  (31U)
63992 /*! LOCK_CONTROL - Lock control of this slot
63993  *  0b0..Do not lock the control register of this slot
63994  *  0b1..Lock the control register of this slot
63995  */
63996 #define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL(x)     (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK)
63997 /*! @} */
63998 
63999 /* The count of IPS_DOMAIN_SLOT_CTRL */
64000 #define IPS_DOMAIN_SLOT_CTRL_COUNT               (38U)
64001 
64002 
64003 /*!
64004  * @}
64005  */ /* end of group IPS_DOMAIN_Register_Masks */
64006 
64007 
64008 /* IPS_DOMAIN - Peripheral instance base addresses */
64009 /** Peripheral IPS_DOMAIN base address */
64010 #define IPS_DOMAIN_BASE                          (0x40C87C00u)
64011 /** Peripheral IPS_DOMAIN base pointer */
64012 #define IPS_DOMAIN                               ((IPS_DOMAIN_Type *)IPS_DOMAIN_BASE)
64013 /** Array initializer of IPS_DOMAIN peripheral base addresses */
64014 #define IPS_DOMAIN_BASE_ADDRS                    { IPS_DOMAIN_BASE }
64015 /** Array initializer of IPS_DOMAIN peripheral base pointers */
64016 #define IPS_DOMAIN_BASE_PTRS                     { IPS_DOMAIN }
64017 
64018 /*!
64019  * @}
64020  */ /* end of group IPS_DOMAIN_Peripheral_Access_Layer */
64021 
64022 
64023 /* ----------------------------------------------------------------------------
64024    -- KEY_MANAGER Peripheral Access Layer
64025    ---------------------------------------------------------------------------- */
64026 
64027 /*!
64028  * @addtogroup KEY_MANAGER_Peripheral_Access_Layer KEY_MANAGER Peripheral Access Layer
64029  * @{
64030  */
64031 
64032 /** KEY_MANAGER - Register Layout Typedef */
64033 typedef struct {
64034   __IO uint32_t MASTER_KEY_CTRL;                   /**< CSR Master Key Control Register, offset: 0x0 */
64035        uint8_t RESERVED_0[12];
64036   __IO uint32_t OTFAD1_KEY_CTRL;                   /**< CSR OTFAD-1 Key Control, offset: 0x10 */
64037        uint8_t RESERVED_1[4];
64038   __IO uint32_t OTFAD2_KEY_CTRL;                   /**< CSR OTFAD-2 Key Control, offset: 0x18 */
64039        uint8_t RESERVED_2[4];
64040   __IO uint32_t IEE_KEY_CTRL;                      /**< CSR IEE Key Control, offset: 0x20 */
64041        uint8_t RESERVED_3[12];
64042   __IO uint32_t PUF_KEY_CTRL;                      /**< CSR PUF Key Control, offset: 0x30 */
64043        uint8_t RESERVED_4[972];
64044   __IO uint32_t SLOT0_CTRL;                        /**< Slot 0 Control, offset: 0x400 */
64045   __IO uint32_t SLOT1_CTRL;                        /**< Slot1 Control, offset: 0x404 */
64046   __IO uint32_t SLOT2_CTRL;                        /**< Slot2 Control, offset: 0x408 */
64047   __IO uint32_t SLOT3_CTRL;                        /**< Slot3 Control, offset: 0x40C */
64048   __IO uint32_t SLOT4_CTRL;                        /**< Slot 4 Control, offset: 0x410 */
64049 } KEY_MANAGER_Type;
64050 
64051 /* ----------------------------------------------------------------------------
64052    -- KEY_MANAGER Register Masks
64053    ---------------------------------------------------------------------------- */
64054 
64055 /*!
64056  * @addtogroup KEY_MANAGER_Register_Masks KEY_MANAGER Register Masks
64057  * @{
64058  */
64059 
64060 /*! @name MASTER_KEY_CTRL - CSR Master Key Control Register */
64061 /*! @{ */
64062 
64063 #define KEY_MANAGER_MASTER_KEY_CTRL_SELECT_MASK  (0x1U)
64064 #define KEY_MANAGER_MASTER_KEY_CTRL_SELECT_SHIFT (0U)
64065 /*! SELECT - Key select for SNVS OTPMK. Default value comes from FUSE_MASTER_KEY_SEL.
64066  *  0b0..select key from UDF
64067  *  0b1..If LOCK = 1, select key from PUF, otherwise select key from fuse (bypass the fuse OTPMK to SNVS)
64068  */
64069 #define KEY_MANAGER_MASTER_KEY_CTRL_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_MASTER_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_MASTER_KEY_CTRL_SELECT_MASK)
64070 
64071 #define KEY_MANAGER_MASTER_KEY_CTRL_LOCK_MASK    (0x10000U)
64072 #define KEY_MANAGER_MASTER_KEY_CTRL_LOCK_SHIFT   (16U)
64073 /*! LOCK - lock this register, prevent from writing. Default value comes from FUSE_MASTER_KEY_SEL_LOCK.
64074  *  0b0..not locked
64075  *  0b1..locked
64076  */
64077 #define KEY_MANAGER_MASTER_KEY_CTRL_LOCK(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_MASTER_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_MASTER_KEY_CTRL_LOCK_MASK)
64078 /*! @} */
64079 
64080 /*! @name OTFAD1_KEY_CTRL - CSR OTFAD-1 Key Control */
64081 /*! @{ */
64082 
64083 #define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_MASK  (0x1U)
64084 #define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_SHIFT (0U)
64085 /*! SELECT - key select for OTFAD-1. Default value comes from FUSE_OTFAD1_KEY_SEL.
64086  *  0b0..Select key from OCOTP USER_KEY5
64087  *  0b1..If PUF_KEY_CTRL[LOCK] is 1, select key from PUF, otherwise select key from OCOTP USER_KEY5
64088  */
64089 #define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_MASK)
64090 
64091 #define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_MASK    (0x10000U)
64092 #define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_SHIFT   (16U)
64093 /*! LOCK - lock this register, prevent from writing. Default value comes from FUSE_OTFAD1_KEY_SEL_LOCK.
64094  *  0b0..not locked
64095  *  0b1..locked
64096  */
64097 #define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_MASK)
64098 /*! @} */
64099 
64100 /*! @name OTFAD2_KEY_CTRL - CSR OTFAD-2 Key Control */
64101 /*! @{ */
64102 
64103 #define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_MASK  (0x1U)
64104 #define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_SHIFT (0U)
64105 /*! SELECT - key select for OTFAD-2. Default value comes from FUSE_OTFAD1_KEY_SEL.
64106  *  0b0..select key from OCOTP USER_KEY5
64107  *  0b1..If PUF_KEY_CTRL[LOCK] is 1, select key from PUF, otherwise select key from OCOTP USER_KEY5
64108  */
64109 #define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT(x)    (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_MASK)
64110 
64111 #define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_MASK    (0x10000U)
64112 #define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_SHIFT   (16U)
64113 /*! LOCK - lock this register, prevent from writing. Default value comes from FUSE_OTFAD2_KEY_SEL_LOCK.
64114  *  0b0..not locked
64115  *  0b1..locked
64116  */
64117 #define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_MASK)
64118 /*! @} */
64119 
64120 /*! @name IEE_KEY_CTRL - CSR IEE Key Control */
64121 /*! @{ */
64122 
64123 #define KEY_MANAGER_IEE_KEY_CTRL_RELOAD_MASK     (0x1U)
64124 #define KEY_MANAGER_IEE_KEY_CTRL_RELOAD_SHIFT    (0U)
64125 /*! RELOAD - Restart load key signal for IEE
64126  *  0b0..Do nothing
64127  *  0b1..Restart IEE key load flow
64128  */
64129 #define KEY_MANAGER_IEE_KEY_CTRL_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_IEE_KEY_CTRL_RELOAD_SHIFT)) & KEY_MANAGER_IEE_KEY_CTRL_RELOAD_MASK)
64130 /*! @} */
64131 
64132 /*! @name PUF_KEY_CTRL - CSR PUF Key Control */
64133 /*! @{ */
64134 
64135 #define KEY_MANAGER_PUF_KEY_CTRL_LOCK_MASK       (0x1U)
64136 #define KEY_MANAGER_PUF_KEY_CTRL_LOCK_SHIFT      (0U)
64137 /*! LOCK - Lock signal for key select
64138  *  0b0..Do not lock the key select
64139  *  0b1..Lock the key select to select key from PUF, otherwise bypass key from OCOPT and do not lock. Once it has
64140  *       been set to 1, it cannot be reset manually. It will be set to 0 when the IEE key reload operation is done.
64141  */
64142 #define KEY_MANAGER_PUF_KEY_CTRL_LOCK(x)         (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_PUF_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_PUF_KEY_CTRL_LOCK_MASK)
64143 /*! @} */
64144 
64145 /*! @name SLOT0_CTRL - Slot 0 Control */
64146 /*! @{ */
64147 
64148 #define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_MASK   (0xFU)
64149 #define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_SHIFT  (0U)
64150 /*! WHITE_LIST - Whitelist */
64151 #define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_MASK)
64152 
64153 #define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_MASK    (0x8000U)
64154 #define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_SHIFT   (15U)
64155 /*! LOCK_LIST - Lock whitelist
64156  *  0b0..Whitelist is not locked
64157  *  0b1..Whitelist is locked
64158  */
64159 #define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_MASK)
64160 
64161 #define KEY_MANAGER_SLOT0_CTRL_TZ_NS_MASK        (0x10000U)
64162 #define KEY_MANAGER_SLOT0_CTRL_TZ_NS_SHIFT       (16U)
64163 /*! TZ_NS - Allow non-secure write access to this register and the slot it controls
64164  *  0b0..Do not allow non-secure write access
64165  *  0b1..Allow non-secure write access
64166  */
64167 #define KEY_MANAGER_SLOT0_CTRL_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_TZ_NS_MASK)
64168 
64169 #define KEY_MANAGER_SLOT0_CTRL_TZ_USER_MASK      (0x20000U)
64170 #define KEY_MANAGER_SLOT0_CTRL_TZ_USER_SHIFT     (17U)
64171 /*! TZ_USER - Allow user write access to this register and the slot it controls
64172  *  0b0..Do not allow user write access
64173  *  0b1..Allow user write access
64174  */
64175 #define KEY_MANAGER_SLOT0_CTRL_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_TZ_USER_MASK)
64176 
64177 #define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_MASK (0x80000000U)
64178 #define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_SHIFT (31U)
64179 /*! LOCK_CONTROL - Lock control of this slot
64180  *  0b0..Do not lock the control register of this slot
64181  *  0b1..Lock the control register of this slot
64182  */
64183 #define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_MASK)
64184 /*! @} */
64185 
64186 /*! @name SLOT1_CTRL - Slot1 Control */
64187 /*! @{ */
64188 
64189 #define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_MASK   (0xFU)
64190 #define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_SHIFT  (0U)
64191 /*! WHITE_LIST - Whitelist */
64192 #define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_MASK)
64193 
64194 #define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_MASK    (0x8000U)
64195 #define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_SHIFT   (15U)
64196 /*! LOCK_LIST - Lock whitelist
64197  *  0b0..Whitelist is not locked
64198  *  0b1..Whitelist is locked
64199  */
64200 #define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_MASK)
64201 
64202 #define KEY_MANAGER_SLOT1_CTRL_TZ_NS_MASK        (0x10000U)
64203 #define KEY_MANAGER_SLOT1_CTRL_TZ_NS_SHIFT       (16U)
64204 /*! TZ_NS - Allow non-secure write access to this register and the slot it controls
64205  *  0b0..Do not allow non-secure write access
64206  *  0b1..Allow non-secure write access
64207  */
64208 #define KEY_MANAGER_SLOT1_CTRL_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_TZ_NS_MASK)
64209 
64210 #define KEY_MANAGER_SLOT1_CTRL_TZ_USER_MASK      (0x20000U)
64211 #define KEY_MANAGER_SLOT1_CTRL_TZ_USER_SHIFT     (17U)
64212 /*! TZ_USER - Allow user write access to this register and the slot it controls
64213  *  0b0..Do not allow user write access
64214  *  0b1..Allow user write access
64215  */
64216 #define KEY_MANAGER_SLOT1_CTRL_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_TZ_USER_MASK)
64217 
64218 #define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_MASK (0x80000000U)
64219 #define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_SHIFT (31U)
64220 /*! LOCK_CONTROL - Lock control of this slot
64221  *  0b0..Do not lock the control register of this slot
64222  *  0b1..Lock the control register of this slot
64223  */
64224 #define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_MASK)
64225 /*! @} */
64226 
64227 /*! @name SLOT2_CTRL - Slot2 Control */
64228 /*! @{ */
64229 
64230 #define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_MASK   (0xFU)
64231 #define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_SHIFT  (0U)
64232 /*! WHITE_LIST - Whitelist */
64233 #define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_MASK)
64234 
64235 #define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_MASK    (0x8000U)
64236 #define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_SHIFT   (15U)
64237 /*! LOCK_LIST - Lock whitelist
64238  *  0b0..Whitelist is not locked
64239  *  0b1..Whitelist is locked
64240  */
64241 #define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_MASK)
64242 
64243 #define KEY_MANAGER_SLOT2_CTRL_TZ_NS_MASK        (0x10000U)
64244 #define KEY_MANAGER_SLOT2_CTRL_TZ_NS_SHIFT       (16U)
64245 /*! TZ_NS - Allow non-secure write access to this register and the slot it controls
64246  *  0b0..Do not allow non-secure write access
64247  *  0b1..Allow non-secure write access
64248  */
64249 #define KEY_MANAGER_SLOT2_CTRL_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_TZ_NS_MASK)
64250 
64251 #define KEY_MANAGER_SLOT2_CTRL_TZ_USER_MASK      (0x20000U)
64252 #define KEY_MANAGER_SLOT2_CTRL_TZ_USER_SHIFT     (17U)
64253 /*! TZ_USER - Allow user write access to this register and the slot it controls
64254  *  0b0..Do not allow user write access
64255  *  0b1..Allow user write access
64256  */
64257 #define KEY_MANAGER_SLOT2_CTRL_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_TZ_USER_MASK)
64258 
64259 #define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_MASK (0x80000000U)
64260 #define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_SHIFT (31U)
64261 /*! LOCK_CONTROL - Lock control of this slot
64262  *  0b0..Do not lock the control register of this slot
64263  *  0b1..Lock the control register of this slot
64264  */
64265 #define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_MASK)
64266 /*! @} */
64267 
64268 /*! @name SLOT3_CTRL - Slot3 Control */
64269 /*! @{ */
64270 
64271 #define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_MASK   (0xFU)
64272 #define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_SHIFT  (0U)
64273 /*! WHITE_LIST - Whitelist */
64274 #define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_MASK)
64275 
64276 #define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_MASK    (0x8000U)
64277 #define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_SHIFT   (15U)
64278 /*! LOCK_LIST - Lock whitelist
64279  *  0b0..Whitelist is not locked
64280  *  0b1..Whitelist is locked
64281  */
64282 #define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_MASK)
64283 
64284 #define KEY_MANAGER_SLOT3_CTRL_TZ_NS_MASK        (0x10000U)
64285 #define KEY_MANAGER_SLOT3_CTRL_TZ_NS_SHIFT       (16U)
64286 /*! TZ_NS - Allow non-secure write access to this register and the slot it controls
64287  *  0b0..Do not allow non-secure write access
64288  *  0b1..Allow non-secure write access
64289  */
64290 #define KEY_MANAGER_SLOT3_CTRL_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_TZ_NS_MASK)
64291 
64292 #define KEY_MANAGER_SLOT3_CTRL_TZ_USER_MASK      (0x20000U)
64293 #define KEY_MANAGER_SLOT3_CTRL_TZ_USER_SHIFT     (17U)
64294 /*! TZ_USER - Allow user write access to this register and the slot it controls
64295  *  0b0..Do not allow user write access
64296  *  0b1..Allow user write access
64297  */
64298 #define KEY_MANAGER_SLOT3_CTRL_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_TZ_USER_MASK)
64299 
64300 #define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_MASK (0x80000000U)
64301 #define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_SHIFT (31U)
64302 /*! LOCK_CONTROL - Lock control of this slot
64303  *  0b0..Do not lock the control register of this slot
64304  *  0b1..Lock the control register of this slot
64305  */
64306 #define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_MASK)
64307 /*! @} */
64308 
64309 /*! @name SLOT4_CTRL - Slot 4 Control */
64310 /*! @{ */
64311 
64312 #define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_MASK   (0xFU)
64313 #define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_SHIFT  (0U)
64314 /*! WHITE_LIST - Whitelist */
64315 #define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST(x)     (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_MASK)
64316 
64317 #define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_MASK    (0x8000U)
64318 #define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_SHIFT   (15U)
64319 /*! LOCK_LIST - Lock whitelist
64320  *  0b0..Whitelist is not locked
64321  *  0b1..Whitelist is locked
64322  */
64323 #define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST(x)      (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_MASK)
64324 
64325 #define KEY_MANAGER_SLOT4_CTRL_TZ_NS_MASK        (0x10000U)
64326 #define KEY_MANAGER_SLOT4_CTRL_TZ_NS_SHIFT       (16U)
64327 /*! TZ_NS - Allow non-secure write access to this register and the slot it controls
64328  *  0b0..Do not allow non-secure write access
64329  *  0b1..Allow non-secure write access
64330  */
64331 #define KEY_MANAGER_SLOT4_CTRL_TZ_NS(x)          (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_TZ_NS_MASK)
64332 
64333 #define KEY_MANAGER_SLOT4_CTRL_TZ_USER_MASK      (0x20000U)
64334 #define KEY_MANAGER_SLOT4_CTRL_TZ_USER_SHIFT     (17U)
64335 /*! TZ_USER - Allow user write access to this register and the slot it controls
64336  *  0b0..Do not allow user write access
64337  *  0b1..Allow user write access
64338  */
64339 #define KEY_MANAGER_SLOT4_CTRL_TZ_USER(x)        (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_TZ_USER_MASK)
64340 
64341 #define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_MASK (0x80000000U)
64342 #define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_SHIFT (31U)
64343 /*! LOCK_CONTROL - Lock control of this slot
64344  *  0b0..Do not lock the control register of this slot
64345  *  0b1..Lock the control register of this slot
64346  */
64347 #define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL(x)   (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_MASK)
64348 /*! @} */
64349 
64350 
64351 /*!
64352  * @}
64353  */ /* end of group KEY_MANAGER_Register_Masks */
64354 
64355 
64356 /* KEY_MANAGER - Peripheral instance base addresses */
64357 /** Peripheral KEY_MANAGER base address */
64358 #define KEY_MANAGER_BASE                         (0x40C80000u)
64359 /** Peripheral KEY_MANAGER base pointer */
64360 #define KEY_MANAGER                              ((KEY_MANAGER_Type *)KEY_MANAGER_BASE)
64361 /** Array initializer of KEY_MANAGER peripheral base addresses */
64362 #define KEY_MANAGER_BASE_ADDRS                   { KEY_MANAGER_BASE }
64363 /** Array initializer of KEY_MANAGER peripheral base pointers */
64364 #define KEY_MANAGER_BASE_PTRS                    { KEY_MANAGER }
64365 
64366 /*!
64367  * @}
64368  */ /* end of group KEY_MANAGER_Peripheral_Access_Layer */
64369 
64370 
64371 /* ----------------------------------------------------------------------------
64372    -- KPP Peripheral Access Layer
64373    ---------------------------------------------------------------------------- */
64374 
64375 /*!
64376  * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer
64377  * @{
64378  */
64379 
64380 /** KPP - Register Layout Typedef */
64381 typedef struct {
64382   __IO uint16_t KPCR;                              /**< Keypad Control Register, offset: 0x0 */
64383   __IO uint16_t KPSR;                              /**< Keypad Status Register, offset: 0x2 */
64384   __IO uint16_t KDDR;                              /**< Keypad Data Direction Register, offset: 0x4 */
64385   __IO uint16_t KPDR;                              /**< Keypad Data Register, offset: 0x6 */
64386 } KPP_Type;
64387 
64388 /* ----------------------------------------------------------------------------
64389    -- KPP Register Masks
64390    ---------------------------------------------------------------------------- */
64391 
64392 /*!
64393  * @addtogroup KPP_Register_Masks KPP Register Masks
64394  * @{
64395  */
64396 
64397 /*! @name KPCR - Keypad Control Register */
64398 /*! @{ */
64399 
64400 #define KPP_KPCR_KRE_MASK                        (0xFFU)
64401 #define KPP_KPCR_KRE_SHIFT                       (0U)
64402 /*! KRE - KRE
64403  *  0b00000000..Row is not included in the keypad key press detect.
64404  *  0b00000001..Row is included in the keypad key press detect.
64405  */
64406 #define KPP_KPCR_KRE(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
64407 
64408 #define KPP_KPCR_KCO_MASK                        (0xFF00U)
64409 #define KPP_KPCR_KCO_SHIFT                       (8U)
64410 /*! KCO - KCO
64411  *  0b00000000..Column strobe output is totem pole drive.
64412  *  0b00000001..Column strobe output is open drain.
64413  */
64414 #define KPP_KPCR_KCO(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
64415 /*! @} */
64416 
64417 /*! @name KPSR - Keypad Status Register */
64418 /*! @{ */
64419 
64420 #define KPP_KPSR_KPKD_MASK                       (0x1U)
64421 #define KPP_KPSR_KPKD_SHIFT                      (0U)
64422 /*! KPKD - KPKD
64423  *  0b0..No key presses detected
64424  *  0b1..A key has been depressed
64425  */
64426 #define KPP_KPSR_KPKD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
64427 
64428 #define KPP_KPSR_KPKR_MASK                       (0x2U)
64429 #define KPP_KPSR_KPKR_SHIFT                      (1U)
64430 /*! KPKR - KPKR
64431  *  0b0..No key release detected
64432  *  0b1..All keys have been released
64433  */
64434 #define KPP_KPSR_KPKR(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
64435 
64436 #define KPP_KPSR_KDSC_MASK                       (0x4U)
64437 #define KPP_KPSR_KDSC_SHIFT                      (2U)
64438 /*! KDSC - KDSC
64439  *  0b0..No effect
64440  *  0b1..Set bits that clear the keypad depress synchronizer chain
64441  */
64442 #define KPP_KPSR_KDSC(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
64443 
64444 #define KPP_KPSR_KRSS_MASK                       (0x8U)
64445 #define KPP_KPSR_KRSS_SHIFT                      (3U)
64446 /*! KRSS - KRSS
64447  *  0b0..No effect
64448  *  0b1..Set bits which sets keypad release synchronizer chain
64449  */
64450 #define KPP_KPSR_KRSS(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
64451 
64452 #define KPP_KPSR_KDIE_MASK                       (0x100U)
64453 #define KPP_KPSR_KDIE_SHIFT                      (8U)
64454 /*! KDIE - KDIE
64455  *  0b0..No interrupt request is generated when KPKD is set.
64456  *  0b1..An interrupt request is generated when KPKD is set.
64457  */
64458 #define KPP_KPSR_KDIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
64459 
64460 #define KPP_KPSR_KRIE_MASK                       (0x200U)
64461 #define KPP_KPSR_KRIE_SHIFT                      (9U)
64462 /*! KRIE - KRIE
64463  *  0b0..No interrupt request is generated when KPKR is set.
64464  *  0b1..An interrupt request is generated when KPKR is set.
64465  */
64466 #define KPP_KPSR_KRIE(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
64467 /*! @} */
64468 
64469 /*! @name KDDR - Keypad Data Direction Register */
64470 /*! @{ */
64471 
64472 #define KPP_KDDR_KRDD_MASK                       (0xFFU)
64473 #define KPP_KDDR_KRDD_SHIFT                      (0U)
64474 /*! KRDD - KRDD
64475  *  0b00000000..ROWn pin configured as an input.
64476  *  0b00000001..ROWn pin configured as an output.
64477  */
64478 #define KPP_KDDR_KRDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
64479 
64480 #define KPP_KDDR_KCDD_MASK                       (0xFF00U)
64481 #define KPP_KDDR_KCDD_SHIFT                      (8U)
64482 /*! KCDD - KCDD
64483  *  0b00000000..COLn pin is configured as an input.
64484  *  0b00000001..COLn pin is configured as an output.
64485  */
64486 #define KPP_KDDR_KCDD(x)                         (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
64487 /*! @} */
64488 
64489 /*! @name KPDR - Keypad Data Register */
64490 /*! @{ */
64491 
64492 #define KPP_KPDR_KRD_MASK                        (0xFFU)
64493 #define KPP_KPDR_KRD_SHIFT                       (0U)
64494 /*! KRD - KRD */
64495 #define KPP_KPDR_KRD(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
64496 
64497 #define KPP_KPDR_KCD_MASK                        (0xFF00U)
64498 #define KPP_KPDR_KCD_SHIFT                       (8U)
64499 /*! KCD - KCD */
64500 #define KPP_KPDR_KCD(x)                          (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)
64501 /*! @} */
64502 
64503 
64504 /*!
64505  * @}
64506  */ /* end of group KPP_Register_Masks */
64507 
64508 
64509 /* KPP - Peripheral instance base addresses */
64510 /** Peripheral KPP base address */
64511 #define KPP_BASE                                 (0x400E0000u)
64512 /** Peripheral KPP base pointer */
64513 #define KPP                                      ((KPP_Type *)KPP_BASE)
64514 /** Array initializer of KPP peripheral base addresses */
64515 #define KPP_BASE_ADDRS                           { KPP_BASE }
64516 /** Array initializer of KPP peripheral base pointers */
64517 #define KPP_BASE_PTRS                            { KPP }
64518 /** Interrupt vectors for the KPP peripheral type */
64519 #define KPP_IRQS                                 { KPP_IRQn }
64520 
64521 /*!
64522  * @}
64523  */ /* end of group KPP_Peripheral_Access_Layer */
64524 
64525 
64526 /* ----------------------------------------------------------------------------
64527    -- LCDIF Peripheral Access Layer
64528    ---------------------------------------------------------------------------- */
64529 
64530 /*!
64531  * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
64532  * @{
64533  */
64534 
64535 /** LCDIF - Register Layout Typedef */
64536 typedef struct {
64537   __IO uint32_t CTRL;                              /**< LCDIF General Control Register, offset: 0x0 */
64538   __IO uint32_t CTRL_SET;                          /**< LCDIF General Control Register, offset: 0x4 */
64539   __IO uint32_t CTRL_CLR;                          /**< LCDIF General Control Register, offset: 0x8 */
64540   __IO uint32_t CTRL_TOG;                          /**< LCDIF General Control Register, offset: 0xC */
64541   __IO uint32_t CTRL1;                             /**< LCDIF General Control1 Register, offset: 0x10 */
64542   __IO uint32_t CTRL1_SET;                         /**< LCDIF General Control1 Register, offset: 0x14 */
64543   __IO uint32_t CTRL1_CLR;                         /**< LCDIF General Control1 Register, offset: 0x18 */
64544   __IO uint32_t CTRL1_TOG;                         /**< LCDIF General Control1 Register, offset: 0x1C */
64545   __IO uint32_t CTRL2;                             /**< LCDIF General Control2 Register, offset: 0x20 */
64546   __IO uint32_t CTRL2_SET;                         /**< LCDIF General Control2 Register, offset: 0x24 */
64547   __IO uint32_t CTRL2_CLR;                         /**< LCDIF General Control2 Register, offset: 0x28 */
64548   __IO uint32_t CTRL2_TOG;                         /**< LCDIF General Control2 Register, offset: 0x2C */
64549   __IO uint32_t TRANSFER_COUNT;                    /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */
64550        uint8_t RESERVED_0[12];
64551   __IO uint32_t CUR_BUF;                           /**< LCD Interface Current Buffer Address Register, offset: 0x40 */
64552        uint8_t RESERVED_1[12];
64553   __IO uint32_t NEXT_BUF;                          /**< LCD Interface Next Buffer Address Register, offset: 0x50 */
64554        uint8_t RESERVED_2[28];
64555   __IO uint32_t VDCTRL0;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */
64556   __IO uint32_t VDCTRL0_SET;                       /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */
64557   __IO uint32_t VDCTRL0_CLR;                       /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */
64558   __IO uint32_t VDCTRL0_TOG;                       /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */
64559   __IO uint32_t VDCTRL1;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */
64560        uint8_t RESERVED_3[12];
64561   __IO uint32_t VDCTRL2;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */
64562        uint8_t RESERVED_4[12];
64563   __IO uint32_t VDCTRL3;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */
64564        uint8_t RESERVED_5[12];
64565   __IO uint32_t VDCTRL4;                           /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */
64566        uint8_t RESERVED_6[220];
64567   __IO uint32_t BM_ERROR_STAT;                     /**< Bus Master Error Status Register, offset: 0x190 */
64568        uint8_t RESERVED_7[12];
64569   __IO uint32_t CRC_STAT;                          /**< CRC Status Register, offset: 0x1A0 */
64570        uint8_t RESERVED_8[12];
64571   __I  uint32_t STAT;                              /**< LCD Interface Status Register, offset: 0x1B0 */
64572        uint8_t RESERVED_9[76];
64573   __IO uint32_t THRES;                             /**< LCDIF Threshold Register, offset: 0x200 */
64574        uint8_t RESERVED_10[380];
64575   __IO uint32_t PIGEONCTRL0;                       /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */
64576   __IO uint32_t PIGEONCTRL0_SET;                   /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */
64577   __IO uint32_t PIGEONCTRL0_CLR;                   /**< LCDIF Pigeon Mode Control0 Register, offset: 0x388 */
64578   __IO uint32_t PIGEONCTRL0_TOG;                   /**< LCDIF Pigeon Mode Control0 Register, offset: 0x38C */
64579   __IO uint32_t PIGEONCTRL1;                       /**< LCDIF Pigeon Mode Control1 Register, offset: 0x390 */
64580   __IO uint32_t PIGEONCTRL1_SET;                   /**< LCDIF Pigeon Mode Control1 Register, offset: 0x394 */
64581   __IO uint32_t PIGEONCTRL1_CLR;                   /**< LCDIF Pigeon Mode Control1 Register, offset: 0x398 */
64582   __IO uint32_t PIGEONCTRL1_TOG;                   /**< LCDIF Pigeon Mode Control1 Register, offset: 0x39C */
64583   __IO uint32_t PIGEONCTRL2;                       /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A0 */
64584   __IO uint32_t PIGEONCTRL2_SET;                   /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A4 */
64585   __IO uint32_t PIGEONCTRL2_CLR;                   /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A8 */
64586   __IO uint32_t PIGEONCTRL2_TOG;                   /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3AC */
64587        uint8_t RESERVED_11[1104];
64588   struct {                                         /* offset: 0x800, array step: 0x40 */
64589     __IO uint32_t PIGEON_0;                          /**< Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40 */
64590          uint8_t RESERVED_0[12];
64591     __IO uint32_t PIGEON_1;                          /**< Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40 */
64592          uint8_t RESERVED_1[12];
64593     __IO uint32_t PIGEON_2;                          /**< Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40 */
64594          uint8_t RESERVED_2[28];
64595   } PIGEON[12];
64596   __IO uint32_t LUT_CTRL;                          /**< Look Up Table Control Register, offset: 0xB00 */
64597        uint8_t RESERVED_12[12];
64598   __IO uint32_t LUT0_ADDR;                         /**< Lookup Table 0 Index Register, offset: 0xB10 */
64599        uint8_t RESERVED_13[12];
64600   __IO uint32_t LUT0_DATA;                         /**< Lookup Table 0 Data Register, offset: 0xB20 */
64601        uint8_t RESERVED_14[12];
64602   __IO uint32_t LUT1_ADDR;                         /**< Lookup Table 1 Index Register, offset: 0xB30 */
64603        uint8_t RESERVED_15[12];
64604   __IO uint32_t LUT1_DATA;                         /**< Lookup Table 1 Data Register, offset: 0xB40 */
64605 } LCDIF_Type;
64606 
64607 /* ----------------------------------------------------------------------------
64608    -- LCDIF Register Masks
64609    ---------------------------------------------------------------------------- */
64610 
64611 /*!
64612  * @addtogroup LCDIF_Register_Masks LCDIF Register Masks
64613  * @{
64614  */
64615 
64616 /*! @name CTRL - LCDIF General Control Register */
64617 /*! @{ */
64618 
64619 #define LCDIF_CTRL_RUN_MASK                      (0x1U)
64620 #define LCDIF_CTRL_RUN_SHIFT                     (0U)
64621 #define LCDIF_CTRL_RUN(x)                        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
64622 
64623 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK       (0x2U)
64624 #define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT      (1U)
64625 /*! DATA_FORMAT_24_BIT
64626  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
64627  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
64628  *       each byte do not contain any useful data, and should be dropped.
64629  */
64630 #define LCDIF_CTRL_DATA_FORMAT_24_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
64631 
64632 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK       (0x4U)
64633 #define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT      (2U)
64634 /*! DATA_FORMAT_18_BIT
64635  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
64636  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
64637  */
64638 #define LCDIF_CTRL_DATA_FORMAT_18_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
64639 
64640 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK       (0x8U)
64641 #define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT      (3U)
64642 #define LCDIF_CTRL_DATA_FORMAT_16_BIT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)
64643 
64644 #define LCDIF_CTRL_RSRVD0_MASK                   (0x10U)
64645 #define LCDIF_CTRL_RSRVD0_SHIFT                  (4U)
64646 #define LCDIF_CTRL_RSRVD0(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)
64647 
64648 #define LCDIF_CTRL_MASTER_MASK                   (0x20U)
64649 #define LCDIF_CTRL_MASTER_SHIFT                  (5U)
64650 #define LCDIF_CTRL_MASTER(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)
64651 
64652 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK     (0x40U)
64653 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT    (6U)
64654 #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)
64655 
64656 #define LCDIF_CTRL_WORD_LENGTH_MASK              (0x300U)
64657 #define LCDIF_CTRL_WORD_LENGTH_SHIFT             (8U)
64658 /*! WORD_LENGTH
64659  *  0b00..Input data is 16 bits per pixel.
64660  *  0b01..Input data is 8 bits wide.
64661  *  0b10..Input data is 18 bits per pixel.
64662  *  0b11..Input data is 24 bits per pixel.
64663  */
64664 #define LCDIF_CTRL_WORD_LENGTH(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
64665 
64666 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK        (0xC00U)
64667 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT       (10U)
64668 /*! LCD_DATABUS_WIDTH
64669  *  0b00..16-bit data bus mode.
64670  *  0b01..8-bit data bus mode.
64671  *  0b10..18-bit data bus mode.
64672  *  0b11..24-bit data bus mode.
64673  */
64674 #define LCDIF_CTRL_LCD_DATABUS_WIDTH(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
64675 
64676 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK         (0x3000U)
64677 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT        (12U)
64678 /*! CSC_DATA_SWIZZLE
64679  *  0b00..No byte swapping.(Little endian)
64680  *  0b00..Little Endian byte ordering (same as NO_SWAP).
64681  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
64682  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
64683  *  0b10..Swap half-words.
64684  *  0b11..Swap bytes within each half-word.
64685  */
64686 #define LCDIF_CTRL_CSC_DATA_SWIZZLE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
64687 
64688 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK       (0xC000U)
64689 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT      (14U)
64690 /*! INPUT_DATA_SWIZZLE
64691  *  0b00..No byte swapping.(Little endian)
64692  *  0b00..Little Endian byte ordering (same as NO_SWAP).
64693  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
64694  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
64695  *  0b10..Swap half-words.
64696  *  0b11..Swap bytes within each half-word.
64697  */
64698 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
64699 
64700 #define LCDIF_CTRL_DOTCLK_MODE_MASK              (0x20000U)
64701 #define LCDIF_CTRL_DOTCLK_MODE_SHIFT             (17U)
64702 #define LCDIF_CTRL_DOTCLK_MODE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)
64703 
64704 #define LCDIF_CTRL_BYPASS_COUNT_MASK             (0x80000U)
64705 #define LCDIF_CTRL_BYPASS_COUNT_SHIFT            (19U)
64706 #define LCDIF_CTRL_BYPASS_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)
64707 
64708 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK           (0x3E00000U)
64709 #define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT          (21U)
64710 #define LCDIF_CTRL_SHIFT_NUM_BITS(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
64711 
64712 #define LCDIF_CTRL_DATA_SHIFT_DIR_MASK           (0x4000000U)
64713 #define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT          (26U)
64714 /*! DATA_SHIFT_DIR
64715  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
64716  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
64717  */
64718 #define LCDIF_CTRL_DATA_SHIFT_DIR(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
64719 
64720 #define LCDIF_CTRL_CLKGATE_MASK                  (0x40000000U)
64721 #define LCDIF_CTRL_CLKGATE_SHIFT                 (30U)
64722 #define LCDIF_CTRL_CLKGATE(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)
64723 
64724 #define LCDIF_CTRL_SFTRST_MASK                   (0x80000000U)
64725 #define LCDIF_CTRL_SFTRST_SHIFT                  (31U)
64726 #define LCDIF_CTRL_SFTRST(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)
64727 /*! @} */
64728 
64729 /*! @name CTRL_SET - LCDIF General Control Register */
64730 /*! @{ */
64731 
64732 #define LCDIF_CTRL_SET_RUN_MASK                  (0x1U)
64733 #define LCDIF_CTRL_SET_RUN_SHIFT                 (0U)
64734 #define LCDIF_CTRL_SET_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
64735 
64736 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK   (0x2U)
64737 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT  (1U)
64738 /*! DATA_FORMAT_24_BIT
64739  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
64740  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
64741  *       each byte do not contain any useful data, and should be dropped.
64742  */
64743 #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
64744 
64745 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK   (0x4U)
64746 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT  (2U)
64747 /*! DATA_FORMAT_18_BIT
64748  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
64749  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
64750  */
64751 #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
64752 
64753 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK   (0x8U)
64754 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT  (3U)
64755 #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)
64756 
64757 #define LCDIF_CTRL_SET_RSRVD0_MASK               (0x10U)
64758 #define LCDIF_CTRL_SET_RSRVD0_SHIFT              (4U)
64759 #define LCDIF_CTRL_SET_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)
64760 
64761 #define LCDIF_CTRL_SET_MASTER_MASK               (0x20U)
64762 #define LCDIF_CTRL_SET_MASTER_SHIFT              (5U)
64763 #define LCDIF_CTRL_SET_MASTER(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)
64764 
64765 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
64766 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
64767 #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)
64768 
64769 #define LCDIF_CTRL_SET_WORD_LENGTH_MASK          (0x300U)
64770 #define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT         (8U)
64771 /*! WORD_LENGTH
64772  *  0b00..Input data is 16 bits per pixel.
64773  *  0b01..Input data is 8 bits wide.
64774  *  0b10..Input data is 18 bits per pixel.
64775  *  0b11..Input data is 24 bits per pixel.
64776  */
64777 #define LCDIF_CTRL_SET_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
64778 
64779 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK    (0xC00U)
64780 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT   (10U)
64781 /*! LCD_DATABUS_WIDTH
64782  *  0b00..16-bit data bus mode.
64783  *  0b01..8-bit data bus mode.
64784  *  0b10..18-bit data bus mode.
64785  *  0b11..24-bit data bus mode.
64786  */
64787 #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
64788 
64789 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK     (0x3000U)
64790 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT    (12U)
64791 /*! CSC_DATA_SWIZZLE
64792  *  0b00..No byte swapping.(Little endian)
64793  *  0b00..Little Endian byte ordering (same as NO_SWAP).
64794  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
64795  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
64796  *  0b10..Swap half-words.
64797  *  0b11..Swap bytes within each half-word.
64798  */
64799 #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
64800 
64801 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
64802 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT  (14U)
64803 /*! INPUT_DATA_SWIZZLE
64804  *  0b00..No byte swapping.(Little endian)
64805  *  0b00..Little Endian byte ordering (same as NO_SWAP).
64806  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
64807  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
64808  *  0b10..Swap half-words.
64809  *  0b11..Swap bytes within each half-word.
64810  */
64811 #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
64812 
64813 #define LCDIF_CTRL_SET_DOTCLK_MODE_MASK          (0x20000U)
64814 #define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT         (17U)
64815 #define LCDIF_CTRL_SET_DOTCLK_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)
64816 
64817 #define LCDIF_CTRL_SET_BYPASS_COUNT_MASK         (0x80000U)
64818 #define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT        (19U)
64819 #define LCDIF_CTRL_SET_BYPASS_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)
64820 
64821 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK       (0x3E00000U)
64822 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT      (21U)
64823 #define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
64824 
64825 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK       (0x4000000U)
64826 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT      (26U)
64827 /*! DATA_SHIFT_DIR
64828  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
64829  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
64830  */
64831 #define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
64832 
64833 #define LCDIF_CTRL_SET_CLKGATE_MASK              (0x40000000U)
64834 #define LCDIF_CTRL_SET_CLKGATE_SHIFT             (30U)
64835 #define LCDIF_CTRL_SET_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)
64836 
64837 #define LCDIF_CTRL_SET_SFTRST_MASK               (0x80000000U)
64838 #define LCDIF_CTRL_SET_SFTRST_SHIFT              (31U)
64839 #define LCDIF_CTRL_SET_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)
64840 /*! @} */
64841 
64842 /*! @name CTRL_CLR - LCDIF General Control Register */
64843 /*! @{ */
64844 
64845 #define LCDIF_CTRL_CLR_RUN_MASK                  (0x1U)
64846 #define LCDIF_CTRL_CLR_RUN_SHIFT                 (0U)
64847 #define LCDIF_CTRL_CLR_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
64848 
64849 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK   (0x2U)
64850 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT  (1U)
64851 /*! DATA_FORMAT_24_BIT
64852  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
64853  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
64854  *       each byte do not contain any useful data, and should be dropped.
64855  */
64856 #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
64857 
64858 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK   (0x4U)
64859 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT  (2U)
64860 /*! DATA_FORMAT_18_BIT
64861  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
64862  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
64863  */
64864 #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
64865 
64866 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK   (0x8U)
64867 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT  (3U)
64868 #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)
64869 
64870 #define LCDIF_CTRL_CLR_RSRVD0_MASK               (0x10U)
64871 #define LCDIF_CTRL_CLR_RSRVD0_SHIFT              (4U)
64872 #define LCDIF_CTRL_CLR_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)
64873 
64874 #define LCDIF_CTRL_CLR_MASTER_MASK               (0x20U)
64875 #define LCDIF_CTRL_CLR_MASTER_SHIFT              (5U)
64876 #define LCDIF_CTRL_CLR_MASTER(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)
64877 
64878 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
64879 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
64880 #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)
64881 
64882 #define LCDIF_CTRL_CLR_WORD_LENGTH_MASK          (0x300U)
64883 #define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT         (8U)
64884 /*! WORD_LENGTH
64885  *  0b00..Input data is 16 bits per pixel.
64886  *  0b01..Input data is 8 bits wide.
64887  *  0b10..Input data is 18 bits per pixel.
64888  *  0b11..Input data is 24 bits per pixel.
64889  */
64890 #define LCDIF_CTRL_CLR_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
64891 
64892 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK    (0xC00U)
64893 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT   (10U)
64894 /*! LCD_DATABUS_WIDTH
64895  *  0b00..16-bit data bus mode.
64896  *  0b01..8-bit data bus mode.
64897  *  0b10..18-bit data bus mode.
64898  *  0b11..24-bit data bus mode.
64899  */
64900 #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
64901 
64902 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK     (0x3000U)
64903 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT    (12U)
64904 /*! CSC_DATA_SWIZZLE
64905  *  0b00..No byte swapping.(Little endian)
64906  *  0b00..Little Endian byte ordering (same as NO_SWAP).
64907  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
64908  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
64909  *  0b10..Swap half-words.
64910  *  0b11..Swap bytes within each half-word.
64911  */
64912 #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
64913 
64914 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
64915 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT  (14U)
64916 /*! INPUT_DATA_SWIZZLE
64917  *  0b00..No byte swapping.(Little endian)
64918  *  0b00..Little Endian byte ordering (same as NO_SWAP).
64919  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
64920  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
64921  *  0b10..Swap half-words.
64922  *  0b11..Swap bytes within each half-word.
64923  */
64924 #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
64925 
64926 #define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK          (0x20000U)
64927 #define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT         (17U)
64928 #define LCDIF_CTRL_CLR_DOTCLK_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)
64929 
64930 #define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK         (0x80000U)
64931 #define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT        (19U)
64932 #define LCDIF_CTRL_CLR_BYPASS_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)
64933 
64934 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK       (0x3E00000U)
64935 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT      (21U)
64936 #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
64937 
64938 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK       (0x4000000U)
64939 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT      (26U)
64940 /*! DATA_SHIFT_DIR
64941  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
64942  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
64943  */
64944 #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
64945 
64946 #define LCDIF_CTRL_CLR_CLKGATE_MASK              (0x40000000U)
64947 #define LCDIF_CTRL_CLR_CLKGATE_SHIFT             (30U)
64948 #define LCDIF_CTRL_CLR_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)
64949 
64950 #define LCDIF_CTRL_CLR_SFTRST_MASK               (0x80000000U)
64951 #define LCDIF_CTRL_CLR_SFTRST_SHIFT              (31U)
64952 #define LCDIF_CTRL_CLR_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)
64953 /*! @} */
64954 
64955 /*! @name CTRL_TOG - LCDIF General Control Register */
64956 /*! @{ */
64957 
64958 #define LCDIF_CTRL_TOG_RUN_MASK                  (0x1U)
64959 #define LCDIF_CTRL_TOG_RUN_SHIFT                 (0U)
64960 #define LCDIF_CTRL_TOG_RUN(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
64961 
64962 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK   (0x2U)
64963 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT  (1U)
64964 /*! DATA_FORMAT_24_BIT
64965  *  0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
64966  *  0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
64967  *       each byte do not contain any useful data, and should be dropped.
64968  */
64969 #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
64970 
64971 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK   (0x4U)
64972 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT  (2U)
64973 /*! DATA_FORMAT_18_BIT
64974  *  0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
64975  *  0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
64976  */
64977 #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
64978 
64979 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK   (0x8U)
64980 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT  (3U)
64981 #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)
64982 
64983 #define LCDIF_CTRL_TOG_RSRVD0_MASK               (0x10U)
64984 #define LCDIF_CTRL_TOG_RSRVD0_SHIFT              (4U)
64985 #define LCDIF_CTRL_TOG_RSRVD0(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)
64986 
64987 #define LCDIF_CTRL_TOG_MASTER_MASK               (0x20U)
64988 #define LCDIF_CTRL_TOG_MASTER_SHIFT              (5U)
64989 #define LCDIF_CTRL_TOG_MASTER(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)
64990 
64991 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
64992 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
64993 #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)
64994 
64995 #define LCDIF_CTRL_TOG_WORD_LENGTH_MASK          (0x300U)
64996 #define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT         (8U)
64997 /*! WORD_LENGTH
64998  *  0b00..Input data is 16 bits per pixel.
64999  *  0b01..Input data is 8 bits wide.
65000  *  0b10..Input data is 18 bits per pixel.
65001  *  0b11..Input data is 24 bits per pixel.
65002  */
65003 #define LCDIF_CTRL_TOG_WORD_LENGTH(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
65004 
65005 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK    (0xC00U)
65006 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT   (10U)
65007 /*! LCD_DATABUS_WIDTH
65008  *  0b00..16-bit data bus mode.
65009  *  0b01..8-bit data bus mode.
65010  *  0b10..18-bit data bus mode.
65011  *  0b11..24-bit data bus mode.
65012  */
65013 #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
65014 
65015 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK     (0x3000U)
65016 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT    (12U)
65017 /*! CSC_DATA_SWIZZLE
65018  *  0b00..No byte swapping.(Little endian)
65019  *  0b00..Little Endian byte ordering (same as NO_SWAP).
65020  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
65021  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
65022  *  0b10..Swap half-words.
65023  *  0b11..Swap bytes within each half-word.
65024  */
65025 #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
65026 
65027 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK   (0xC000U)
65028 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT  (14U)
65029 /*! INPUT_DATA_SWIZZLE
65030  *  0b00..No byte swapping.(Little endian)
65031  *  0b00..Little Endian byte ordering (same as NO_SWAP).
65032  *  0b01..Big Endian swap (swap bytes 0,3 and 1,2).
65033  *  0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
65034  *  0b10..Swap half-words.
65035  *  0b11..Swap bytes within each half-word.
65036  */
65037 #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
65038 
65039 #define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK          (0x20000U)
65040 #define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT         (17U)
65041 #define LCDIF_CTRL_TOG_DOTCLK_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)
65042 
65043 #define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK         (0x80000U)
65044 #define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT        (19U)
65045 #define LCDIF_CTRL_TOG_BYPASS_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)
65046 
65047 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK       (0x3E00000U)
65048 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT      (21U)
65049 #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
65050 
65051 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK       (0x4000000U)
65052 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT      (26U)
65053 /*! DATA_SHIFT_DIR
65054  *  0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
65055  *  0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
65056  */
65057 #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
65058 
65059 #define LCDIF_CTRL_TOG_CLKGATE_MASK              (0x40000000U)
65060 #define LCDIF_CTRL_TOG_CLKGATE_SHIFT             (30U)
65061 #define LCDIF_CTRL_TOG_CLKGATE(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)
65062 
65063 #define LCDIF_CTRL_TOG_SFTRST_MASK               (0x80000000U)
65064 #define LCDIF_CTRL_TOG_SFTRST_SHIFT              (31U)
65065 #define LCDIF_CTRL_TOG_SFTRST(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)
65066 /*! @} */
65067 
65068 /*! @name CTRL1 - LCDIF General Control1 Register */
65069 /*! @{ */
65070 
65071 #define LCDIF_CTRL1_RSRVD0_MASK                  (0xF8U)
65072 #define LCDIF_CTRL1_RSRVD0_SHIFT                 (3U)
65073 #define LCDIF_CTRL1_RSRVD0(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
65074 
65075 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK          (0x100U)
65076 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT         (8U)
65077 /*! VSYNC_EDGE_IRQ
65078  *  0b0..No Interrupt Request Pending.
65079  *  0b1..Interrupt Request Pending.
65080  */
65081 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
65082 
65083 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK      (0x200U)
65084 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT     (9U)
65085 /*! CUR_FRAME_DONE_IRQ
65086  *  0b0..No Interrupt Request Pending.
65087  *  0b1..Interrupt Request Pending.
65088  */
65089 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
65090 
65091 #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK           (0x400U)
65092 #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT          (10U)
65093 /*! UNDERFLOW_IRQ
65094  *  0b0..No Interrupt Request Pending.
65095  *  0b1..Interrupt Request Pending.
65096  */
65097 #define LCDIF_CTRL1_UNDERFLOW_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
65098 
65099 #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK            (0x800U)
65100 #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT           (11U)
65101 /*! OVERFLOW_IRQ
65102  *  0b0..No Interrupt Request Pending.
65103  *  0b1..Interrupt Request Pending.
65104  */
65105 #define LCDIF_CTRL1_OVERFLOW_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
65106 
65107 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK       (0x1000U)
65108 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT      (12U)
65109 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
65110 
65111 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK   (0x2000U)
65112 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT  (13U)
65113 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)
65114 
65115 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK        (0x4000U)
65116 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT       (14U)
65117 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)
65118 
65119 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK         (0x8000U)
65120 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT        (15U)
65121 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)
65122 
65123 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK     (0xF0000U)
65124 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT    (16U)
65125 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
65126 
65127 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
65128 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
65129 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)
65130 
65131 #define LCDIF_CTRL1_FIFO_CLEAR_MASK              (0x200000U)
65132 #define LCDIF_CTRL1_FIFO_CLEAR_SHIFT             (21U)
65133 #define LCDIF_CTRL1_FIFO_CLEAR(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)
65134 
65135 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
65136 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
65137 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)
65138 
65139 #define LCDIF_CTRL1_INTERLACE_FIELDS_MASK        (0x800000U)
65140 #define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT       (23U)
65141 #define LCDIF_CTRL1_INTERLACE_FIELDS(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)
65142 
65143 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK    (0x1000000U)
65144 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT   (24U)
65145 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
65146 
65147 #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK            (0x2000000U)
65148 #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT           (25U)
65149 /*! BM_ERROR_IRQ
65150  *  0b0..No Interrupt Request Pending.
65151  *  0b1..Interrupt Request Pending.
65152  */
65153 #define LCDIF_CTRL1_BM_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
65154 
65155 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK         (0x4000000U)
65156 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT        (26U)
65157 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)
65158 
65159 #define LCDIF_CTRL1_CS_OUT_SELECT_MASK           (0x40000000U)
65160 #define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT          (30U)
65161 #define LCDIF_CTRL1_CS_OUT_SELECT(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)
65162 
65163 #define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK       (0x80000000U)
65164 #define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT      (31U)
65165 #define LCDIF_CTRL1_IMAGE_DATA_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)
65166 /*! @} */
65167 
65168 /*! @name CTRL1_SET - LCDIF General Control1 Register */
65169 /*! @{ */
65170 
65171 #define LCDIF_CTRL1_SET_RSRVD0_MASK              (0xF8U)
65172 #define LCDIF_CTRL1_SET_RSRVD0_SHIFT             (3U)
65173 #define LCDIF_CTRL1_SET_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
65174 
65175 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK      (0x100U)
65176 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT     (8U)
65177 /*! VSYNC_EDGE_IRQ
65178  *  0b0..No Interrupt Request Pending.
65179  *  0b1..Interrupt Request Pending.
65180  */
65181 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
65182 
65183 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
65184 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
65185 /*! CUR_FRAME_DONE_IRQ
65186  *  0b0..No Interrupt Request Pending.
65187  *  0b1..Interrupt Request Pending.
65188  */
65189 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
65190 
65191 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK       (0x400U)
65192 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT      (10U)
65193 /*! UNDERFLOW_IRQ
65194  *  0b0..No Interrupt Request Pending.
65195  *  0b1..Interrupt Request Pending.
65196  */
65197 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
65198 
65199 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK        (0x800U)
65200 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT       (11U)
65201 /*! OVERFLOW_IRQ
65202  *  0b0..No Interrupt Request Pending.
65203  *  0b1..Interrupt Request Pending.
65204  */
65205 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
65206 
65207 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
65208 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
65209 #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)
65210 
65211 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
65212 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
65213 #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)
65214 
65215 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK    (0x4000U)
65216 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT   (14U)
65217 #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)
65218 
65219 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK     (0x8000U)
65220 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT    (15U)
65221 #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)
65222 
65223 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)
65224 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)
65225 #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
65226 
65227 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
65228 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
65229 #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)
65230 
65231 #define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK          (0x200000U)
65232 #define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT         (21U)
65233 #define LCDIF_CTRL1_SET_FIFO_CLEAR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)
65234 
65235 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
65236 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
65237 #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)
65238 
65239 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK    (0x800000U)
65240 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT   (23U)
65241 #define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)
65242 
65243 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
65244 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)
65245 #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
65246 
65247 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK        (0x2000000U)
65248 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT       (25U)
65249 /*! BM_ERROR_IRQ
65250  *  0b0..No Interrupt Request Pending.
65251  *  0b1..Interrupt Request Pending.
65252  */
65253 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
65254 
65255 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
65256 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT    (26U)
65257 #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)
65258 
65259 #define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK       (0x40000000U)
65260 #define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT      (30U)
65261 #define LCDIF_CTRL1_SET_CS_OUT_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)
65262 
65263 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK   (0x80000000U)
65264 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT  (31U)
65265 #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)
65266 /*! @} */
65267 
65268 /*! @name CTRL1_CLR - LCDIF General Control1 Register */
65269 /*! @{ */
65270 
65271 #define LCDIF_CTRL1_CLR_RSRVD0_MASK              (0xF8U)
65272 #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT             (3U)
65273 #define LCDIF_CTRL1_CLR_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
65274 
65275 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK      (0x100U)
65276 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT     (8U)
65277 /*! VSYNC_EDGE_IRQ
65278  *  0b0..No Interrupt Request Pending.
65279  *  0b1..Interrupt Request Pending.
65280  */
65281 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
65282 
65283 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
65284 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
65285 /*! CUR_FRAME_DONE_IRQ
65286  *  0b0..No Interrupt Request Pending.
65287  *  0b1..Interrupt Request Pending.
65288  */
65289 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
65290 
65291 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK       (0x400U)
65292 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT      (10U)
65293 /*! UNDERFLOW_IRQ
65294  *  0b0..No Interrupt Request Pending.
65295  *  0b1..Interrupt Request Pending.
65296  */
65297 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
65298 
65299 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK        (0x800U)
65300 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT       (11U)
65301 /*! OVERFLOW_IRQ
65302  *  0b0..No Interrupt Request Pending.
65303  *  0b1..Interrupt Request Pending.
65304  */
65305 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
65306 
65307 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
65308 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
65309 #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)
65310 
65311 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
65312 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
65313 #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)
65314 
65315 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK    (0x4000U)
65316 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT   (14U)
65317 #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)
65318 
65319 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK     (0x8000U)
65320 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT    (15U)
65321 #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)
65322 
65323 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)
65324 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)
65325 #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
65326 
65327 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
65328 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
65329 #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)
65330 
65331 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK          (0x200000U)
65332 #define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT         (21U)
65333 #define LCDIF_CTRL1_CLR_FIFO_CLEAR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)
65334 
65335 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
65336 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
65337 #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)
65338 
65339 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK    (0x800000U)
65340 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT   (23U)
65341 #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)
65342 
65343 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
65344 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)
65345 #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
65346 
65347 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK        (0x2000000U)
65348 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT       (25U)
65349 /*! BM_ERROR_IRQ
65350  *  0b0..No Interrupt Request Pending.
65351  *  0b1..Interrupt Request Pending.
65352  */
65353 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
65354 
65355 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
65356 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT    (26U)
65357 #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)
65358 
65359 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK       (0x40000000U)
65360 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT      (30U)
65361 #define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)
65362 
65363 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK   (0x80000000U)
65364 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT  (31U)
65365 #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)
65366 /*! @} */
65367 
65368 /*! @name CTRL1_TOG - LCDIF General Control1 Register */
65369 /*! @{ */
65370 
65371 #define LCDIF_CTRL1_TOG_RSRVD0_MASK              (0xF8U)
65372 #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT             (3U)
65373 #define LCDIF_CTRL1_TOG_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
65374 
65375 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK      (0x100U)
65376 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT     (8U)
65377 /*! VSYNC_EDGE_IRQ
65378  *  0b0..No Interrupt Request Pending.
65379  *  0b1..Interrupt Request Pending.
65380  */
65381 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
65382 
65383 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK  (0x200U)
65384 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
65385 /*! CUR_FRAME_DONE_IRQ
65386  *  0b0..No Interrupt Request Pending.
65387  *  0b1..Interrupt Request Pending.
65388  */
65389 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
65390 
65391 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK       (0x400U)
65392 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT      (10U)
65393 /*! UNDERFLOW_IRQ
65394  *  0b0..No Interrupt Request Pending.
65395  *  0b1..Interrupt Request Pending.
65396  */
65397 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
65398 
65399 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK        (0x800U)
65400 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT       (11U)
65401 /*! OVERFLOW_IRQ
65402  *  0b0..No Interrupt Request Pending.
65403  *  0b1..Interrupt Request Pending.
65404  */
65405 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
65406 
65407 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK   (0x1000U)
65408 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT  (12U)
65409 #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)
65410 
65411 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
65412 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
65413 #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)
65414 
65415 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK    (0x4000U)
65416 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT   (14U)
65417 #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)
65418 
65419 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK     (0x8000U)
65420 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT    (15U)
65421 #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)
65422 
65423 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)
65424 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)
65425 #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
65426 
65427 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
65428 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
65429 #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)
65430 
65431 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK          (0x200000U)
65432 #define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT         (21U)
65433 #define LCDIF_CTRL1_TOG_FIFO_CLEAR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)
65434 
65435 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
65436 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
65437 #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)
65438 
65439 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK    (0x800000U)
65440 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT   (23U)
65441 #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)
65442 
65443 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
65444 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)
65445 #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
65446 
65447 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK        (0x2000000U)
65448 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT       (25U)
65449 /*! BM_ERROR_IRQ
65450  *  0b0..No Interrupt Request Pending.
65451  *  0b1..Interrupt Request Pending.
65452  */
65453 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
65454 
65455 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK     (0x4000000U)
65456 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT    (26U)
65457 #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)
65458 
65459 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK       (0x40000000U)
65460 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT      (30U)
65461 #define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)
65462 
65463 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK   (0x80000000U)
65464 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT  (31U)
65465 #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)
65466 /*! @} */
65467 
65468 /*! @name CTRL2 - LCDIF General Control2 Register */
65469 /*! @{ */
65470 
65471 #define LCDIF_CTRL2_RSRVD0_MASK                  (0xFFFU)
65472 #define LCDIF_CTRL2_RSRVD0_SHIFT                 (0U)
65473 #define LCDIF_CTRL2_RSRVD0(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
65474 
65475 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK       (0x7000U)
65476 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT      (12U)
65477 /*! EVEN_LINE_PATTERN
65478  *  0b000..RGB
65479  *  0b001..RBG
65480  *  0b010..GBR
65481  *  0b011..GRB
65482  *  0b100..BRG
65483  *  0b101..BGR
65484  */
65485 #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
65486 
65487 #define LCDIF_CTRL2_RSRVD3_MASK                  (0x8000U)
65488 #define LCDIF_CTRL2_RSRVD3_SHIFT                 (15U)
65489 #define LCDIF_CTRL2_RSRVD3(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
65490 
65491 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK        (0x70000U)
65492 #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT       (16U)
65493 /*! ODD_LINE_PATTERN
65494  *  0b000..RGB
65495  *  0b001..RBG
65496  *  0b010..GBR
65497  *  0b011..GRB
65498  *  0b100..BRG
65499  *  0b101..BGR
65500  */
65501 #define LCDIF_CTRL2_ODD_LINE_PATTERN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
65502 
65503 #define LCDIF_CTRL2_RSRVD4_MASK                  (0x80000U)
65504 #define LCDIF_CTRL2_RSRVD4_SHIFT                 (19U)
65505 #define LCDIF_CTRL2_RSRVD4(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)
65506 
65507 #define LCDIF_CTRL2_BURST_LEN_8_MASK             (0x100000U)
65508 #define LCDIF_CTRL2_BURST_LEN_8_SHIFT            (20U)
65509 #define LCDIF_CTRL2_BURST_LEN_8(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
65510 
65511 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK        (0xE00000U)
65512 #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT       (21U)
65513 /*! OUTSTANDING_REQS
65514  *  0b000..REQ_1
65515  *  0b001..REQ_2
65516  *  0b010..REQ_4
65517  *  0b011..REQ_8
65518  *  0b100..REQ_16
65519  */
65520 #define LCDIF_CTRL2_OUTSTANDING_REQS(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
65521 
65522 #define LCDIF_CTRL2_RSRVD5_MASK                  (0xFF000000U)
65523 #define LCDIF_CTRL2_RSRVD5_SHIFT                 (24U)
65524 #define LCDIF_CTRL2_RSRVD5(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)
65525 /*! @} */
65526 
65527 /*! @name CTRL2_SET - LCDIF General Control2 Register */
65528 /*! @{ */
65529 
65530 #define LCDIF_CTRL2_SET_RSRVD0_MASK              (0xFFFU)
65531 #define LCDIF_CTRL2_SET_RSRVD0_SHIFT             (0U)
65532 #define LCDIF_CTRL2_SET_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
65533 
65534 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK   (0x7000U)
65535 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT  (12U)
65536 /*! EVEN_LINE_PATTERN
65537  *  0b000..RGB
65538  *  0b001..RBG
65539  *  0b010..GBR
65540  *  0b011..GRB
65541  *  0b100..BRG
65542  *  0b101..BGR
65543  */
65544 #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
65545 
65546 #define LCDIF_CTRL2_SET_RSRVD3_MASK              (0x8000U)
65547 #define LCDIF_CTRL2_SET_RSRVD3_SHIFT             (15U)
65548 #define LCDIF_CTRL2_SET_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
65549 
65550 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK    (0x70000U)
65551 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT   (16U)
65552 /*! ODD_LINE_PATTERN
65553  *  0b000..RGB
65554  *  0b001..RBG
65555  *  0b010..GBR
65556  *  0b011..GRB
65557  *  0b100..BRG
65558  *  0b101..BGR
65559  */
65560 #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
65561 
65562 #define LCDIF_CTRL2_SET_RSRVD4_MASK              (0x80000U)
65563 #define LCDIF_CTRL2_SET_RSRVD4_SHIFT             (19U)
65564 #define LCDIF_CTRL2_SET_RSRVD4(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)
65565 
65566 #define LCDIF_CTRL2_SET_BURST_LEN_8_MASK         (0x100000U)
65567 #define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT        (20U)
65568 #define LCDIF_CTRL2_SET_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
65569 
65570 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK    (0xE00000U)
65571 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT   (21U)
65572 /*! OUTSTANDING_REQS
65573  *  0b000..REQ_1
65574  *  0b001..REQ_2
65575  *  0b010..REQ_4
65576  *  0b011..REQ_8
65577  *  0b100..REQ_16
65578  */
65579 #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
65580 
65581 #define LCDIF_CTRL2_SET_RSRVD5_MASK              (0xFF000000U)
65582 #define LCDIF_CTRL2_SET_RSRVD5_SHIFT             (24U)
65583 #define LCDIF_CTRL2_SET_RSRVD5(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)
65584 /*! @} */
65585 
65586 /*! @name CTRL2_CLR - LCDIF General Control2 Register */
65587 /*! @{ */
65588 
65589 #define LCDIF_CTRL2_CLR_RSRVD0_MASK              (0xFFFU)
65590 #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT             (0U)
65591 #define LCDIF_CTRL2_CLR_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
65592 
65593 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK   (0x7000U)
65594 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT  (12U)
65595 /*! EVEN_LINE_PATTERN
65596  *  0b000..RGB
65597  *  0b001..RBG
65598  *  0b010..GBR
65599  *  0b011..GRB
65600  *  0b100..BRG
65601  *  0b101..BGR
65602  */
65603 #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
65604 
65605 #define LCDIF_CTRL2_CLR_RSRVD3_MASK              (0x8000U)
65606 #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT             (15U)
65607 #define LCDIF_CTRL2_CLR_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
65608 
65609 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK    (0x70000U)
65610 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT   (16U)
65611 /*! ODD_LINE_PATTERN
65612  *  0b000..RGB
65613  *  0b001..RBG
65614  *  0b010..GBR
65615  *  0b011..GRB
65616  *  0b100..BRG
65617  *  0b101..BGR
65618  */
65619 #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
65620 
65621 #define LCDIF_CTRL2_CLR_RSRVD4_MASK              (0x80000U)
65622 #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT             (19U)
65623 #define LCDIF_CTRL2_CLR_RSRVD4(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)
65624 
65625 #define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK         (0x100000U)
65626 #define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT        (20U)
65627 #define LCDIF_CTRL2_CLR_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
65628 
65629 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK    (0xE00000U)
65630 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT   (21U)
65631 /*! OUTSTANDING_REQS
65632  *  0b000..REQ_1
65633  *  0b001..REQ_2
65634  *  0b010..REQ_4
65635  *  0b011..REQ_8
65636  *  0b100..REQ_16
65637  */
65638 #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
65639 
65640 #define LCDIF_CTRL2_CLR_RSRVD5_MASK              (0xFF000000U)
65641 #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT             (24U)
65642 #define LCDIF_CTRL2_CLR_RSRVD5(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)
65643 /*! @} */
65644 
65645 /*! @name CTRL2_TOG - LCDIF General Control2 Register */
65646 /*! @{ */
65647 
65648 #define LCDIF_CTRL2_TOG_RSRVD0_MASK              (0xFFFU)
65649 #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT             (0U)
65650 #define LCDIF_CTRL2_TOG_RSRVD0(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
65651 
65652 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK   (0x7000U)
65653 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT  (12U)
65654 /*! EVEN_LINE_PATTERN
65655  *  0b000..RGB
65656  *  0b001..RBG
65657  *  0b010..GBR
65658  *  0b011..GRB
65659  *  0b100..BRG
65660  *  0b101..BGR
65661  */
65662 #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
65663 
65664 #define LCDIF_CTRL2_TOG_RSRVD3_MASK              (0x8000U)
65665 #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT             (15U)
65666 #define LCDIF_CTRL2_TOG_RSRVD3(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
65667 
65668 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK    (0x70000U)
65669 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT   (16U)
65670 /*! ODD_LINE_PATTERN
65671  *  0b000..RGB
65672  *  0b001..RBG
65673  *  0b010..GBR
65674  *  0b011..GRB
65675  *  0b100..BRG
65676  *  0b101..BGR
65677  */
65678 #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
65679 
65680 #define LCDIF_CTRL2_TOG_RSRVD4_MASK              (0x80000U)
65681 #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT             (19U)
65682 #define LCDIF_CTRL2_TOG_RSRVD4(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)
65683 
65684 #define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK         (0x100000U)
65685 #define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT        (20U)
65686 #define LCDIF_CTRL2_TOG_BURST_LEN_8(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
65687 
65688 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK    (0xE00000U)
65689 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT   (21U)
65690 /*! OUTSTANDING_REQS
65691  *  0b000..REQ_1
65692  *  0b001..REQ_2
65693  *  0b010..REQ_4
65694  *  0b011..REQ_8
65695  *  0b100..REQ_16
65696  */
65697 #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
65698 
65699 #define LCDIF_CTRL2_TOG_RSRVD5_MASK              (0xFF000000U)
65700 #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT             (24U)
65701 #define LCDIF_CTRL2_TOG_RSRVD5(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
65702 /*! @} */
65703 
65704 /*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */
65705 /*! @{ */
65706 
65707 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK        (0xFFFFU)
65708 #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT       (0U)
65709 #define LCDIF_TRANSFER_COUNT_H_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
65710 
65711 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK        (0xFFFF0000U)
65712 #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT       (16U)
65713 #define LCDIF_TRANSFER_COUNT_V_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
65714 /*! @} */
65715 
65716 /*! @name CUR_BUF - LCD Interface Current Buffer Address Register */
65717 /*! @{ */
65718 
65719 #define LCDIF_CUR_BUF_ADDR_MASK                  (0xFFFFFFFFU)
65720 #define LCDIF_CUR_BUF_ADDR_SHIFT                 (0U)
65721 #define LCDIF_CUR_BUF_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)
65722 /*! @} */
65723 
65724 /*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */
65725 /*! @{ */
65726 
65727 #define LCDIF_NEXT_BUF_ADDR_MASK                 (0xFFFFFFFFU)
65728 #define LCDIF_NEXT_BUF_ADDR_SHIFT                (0U)
65729 #define LCDIF_NEXT_BUF_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)
65730 /*! @} */
65731 
65732 /*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
65733 /*! @{ */
65734 
65735 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK     (0x3FFFFU)
65736 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT    (0U)
65737 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
65738 
65739 #define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK        (0x40000U)
65740 #define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT       (18U)
65741 #define LCDIF_VDCTRL0_HALF_LINE_MODE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)
65742 
65743 #define LCDIF_VDCTRL0_HALF_LINE_MASK             (0x80000U)
65744 #define LCDIF_VDCTRL0_HALF_LINE_SHIFT            (19U)
65745 #define LCDIF_VDCTRL0_HALF_LINE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)
65746 
65747 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
65748 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
65749 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)
65750 
65751 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK     (0x200000U)
65752 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT    (21U)
65753 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)
65754 
65755 #define LCDIF_VDCTRL0_RSRVD1_MASK                (0xC00000U)
65756 #define LCDIF_VDCTRL0_RSRVD1_SHIFT               (22U)
65757 #define LCDIF_VDCTRL0_RSRVD1(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)
65758 
65759 #define LCDIF_VDCTRL0_ENABLE_POL_MASK            (0x1000000U)
65760 #define LCDIF_VDCTRL0_ENABLE_POL_SHIFT           (24U)
65761 #define LCDIF_VDCTRL0_ENABLE_POL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)
65762 
65763 #define LCDIF_VDCTRL0_DOTCLK_POL_MASK            (0x2000000U)
65764 #define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT           (25U)
65765 #define LCDIF_VDCTRL0_DOTCLK_POL(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)
65766 
65767 #define LCDIF_VDCTRL0_HSYNC_POL_MASK             (0x4000000U)
65768 #define LCDIF_VDCTRL0_HSYNC_POL_SHIFT            (26U)
65769 #define LCDIF_VDCTRL0_HSYNC_POL(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)
65770 
65771 #define LCDIF_VDCTRL0_VSYNC_POL_MASK             (0x8000000U)
65772 #define LCDIF_VDCTRL0_VSYNC_POL_SHIFT            (27U)
65773 #define LCDIF_VDCTRL0_VSYNC_POL(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)
65774 
65775 #define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK        (0x10000000U)
65776 #define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT       (28U)
65777 #define LCDIF_VDCTRL0_ENABLE_PRESENT(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)
65778 
65779 #define LCDIF_VDCTRL0_VSYNC_OEB_MASK             (0x20000000U)
65780 #define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT            (29U)
65781 /*! VSYNC_OEB
65782  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
65783  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
65784  */
65785 #define LCDIF_VDCTRL0_VSYNC_OEB(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK)
65786 
65787 #define LCDIF_VDCTRL0_RSRVD2_MASK                (0xC0000000U)
65788 #define LCDIF_VDCTRL0_RSRVD2_SHIFT               (30U)
65789 #define LCDIF_VDCTRL0_RSRVD2(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)
65790 /*! @} */
65791 
65792 /*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
65793 /*! @{ */
65794 
65795 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
65796 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)
65797 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
65798 
65799 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK    (0x40000U)
65800 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT   (18U)
65801 #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)
65802 
65803 #define LCDIF_VDCTRL0_SET_HALF_LINE_MASK         (0x80000U)
65804 #define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT        (19U)
65805 #define LCDIF_VDCTRL0_SET_HALF_LINE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)
65806 
65807 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
65808 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
65809 #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)
65810 
65811 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)
65812 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)
65813 #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)
65814 
65815 #define LCDIF_VDCTRL0_SET_RSRVD1_MASK            (0xC00000U)
65816 #define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT           (22U)
65817 #define LCDIF_VDCTRL0_SET_RSRVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)
65818 
65819 #define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK        (0x1000000U)
65820 #define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT       (24U)
65821 #define LCDIF_VDCTRL0_SET_ENABLE_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)
65822 
65823 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK        (0x2000000U)
65824 #define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT       (25U)
65825 #define LCDIF_VDCTRL0_SET_DOTCLK_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)
65826 
65827 #define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK         (0x4000000U)
65828 #define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT        (26U)
65829 #define LCDIF_VDCTRL0_SET_HSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)
65830 
65831 #define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK         (0x8000000U)
65832 #define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT        (27U)
65833 #define LCDIF_VDCTRL0_SET_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)
65834 
65835 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK    (0x10000000U)
65836 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT   (28U)
65837 #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)
65838 
65839 #define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK         (0x20000000U)
65840 #define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT        (29U)
65841 /*! VSYNC_OEB
65842  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
65843  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
65844  */
65845 #define LCDIF_VDCTRL0_SET_VSYNC_OEB(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK)
65846 
65847 #define LCDIF_VDCTRL0_SET_RSRVD2_MASK            (0xC0000000U)
65848 #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT           (30U)
65849 #define LCDIF_VDCTRL0_SET_RSRVD2(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)
65850 /*! @} */
65851 
65852 /*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
65853 /*! @{ */
65854 
65855 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
65856 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)
65857 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
65858 
65859 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK    (0x40000U)
65860 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT   (18U)
65861 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)
65862 
65863 #define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK         (0x80000U)
65864 #define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT        (19U)
65865 #define LCDIF_VDCTRL0_CLR_HALF_LINE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)
65866 
65867 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
65868 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
65869 #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)
65870 
65871 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)
65872 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)
65873 #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)
65874 
65875 #define LCDIF_VDCTRL0_CLR_RSRVD1_MASK            (0xC00000U)
65876 #define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT           (22U)
65877 #define LCDIF_VDCTRL0_CLR_RSRVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
65878 
65879 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK        (0x1000000U)
65880 #define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT       (24U)
65881 #define LCDIF_VDCTRL0_CLR_ENABLE_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)
65882 
65883 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK        (0x2000000U)
65884 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT       (25U)
65885 #define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)
65886 
65887 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK         (0x4000000U)
65888 #define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT        (26U)
65889 #define LCDIF_VDCTRL0_CLR_HSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)
65890 
65891 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK         (0x8000000U)
65892 #define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT        (27U)
65893 #define LCDIF_VDCTRL0_CLR_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)
65894 
65895 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK    (0x10000000U)
65896 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT   (28U)
65897 #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)
65898 
65899 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK         (0x20000000U)
65900 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT        (29U)
65901 /*! VSYNC_OEB
65902  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
65903  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
65904  */
65905 #define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK)
65906 
65907 #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK            (0xC0000000U)
65908 #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT           (30U)
65909 #define LCDIF_VDCTRL0_CLR_RSRVD2(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
65910 /*! @} */
65911 
65912 /*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
65913 /*! @{ */
65914 
65915 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
65916 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)
65917 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
65918 
65919 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK    (0x40000U)
65920 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT   (18U)
65921 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)
65922 
65923 #define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK         (0x80000U)
65924 #define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT        (19U)
65925 #define LCDIF_VDCTRL0_TOG_HALF_LINE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)
65926 
65927 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
65928 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
65929 #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)
65930 
65931 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)
65932 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)
65933 #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)
65934 
65935 #define LCDIF_VDCTRL0_TOG_RSRVD1_MASK            (0xC00000U)
65936 #define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT           (22U)
65937 #define LCDIF_VDCTRL0_TOG_RSRVD1(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
65938 
65939 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK        (0x1000000U)
65940 #define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT       (24U)
65941 #define LCDIF_VDCTRL0_TOG_ENABLE_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)
65942 
65943 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK        (0x2000000U)
65944 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT       (25U)
65945 #define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)
65946 
65947 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK         (0x4000000U)
65948 #define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT        (26U)
65949 #define LCDIF_VDCTRL0_TOG_HSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)
65950 
65951 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK         (0x8000000U)
65952 #define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT        (27U)
65953 #define LCDIF_VDCTRL0_TOG_VSYNC_POL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)
65954 
65955 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK    (0x10000000U)
65956 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT   (28U)
65957 #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)
65958 
65959 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK         (0x20000000U)
65960 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT        (29U)
65961 /*! VSYNC_OEB
65962  *  0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
65963  *  0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
65964  */
65965 #define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK)
65966 
65967 #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK            (0xC0000000U)
65968 #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT           (30U)
65969 #define LCDIF_VDCTRL0_TOG_RSRVD2(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
65970 /*! @} */
65971 
65972 /*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */
65973 /*! @{ */
65974 
65975 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK          (0xFFFFFFFFU)
65976 #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT         (0U)
65977 #define LCDIF_VDCTRL1_VSYNC_PERIOD(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
65978 /*! @} */
65979 
65980 /*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */
65981 /*! @{ */
65982 
65983 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK          (0x3FFFFU)
65984 #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT         (0U)
65985 #define LCDIF_VDCTRL2_HSYNC_PERIOD(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
65986 
65987 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK     (0xFFFC0000U)
65988 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT    (18U)
65989 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
65990 /*! @} */
65991 
65992 /*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */
65993 /*! @{ */
65994 
65995 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK     (0xFFFFU)
65996 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT    (0U)
65997 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
65998 
65999 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK   (0xFFF0000U)
66000 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT  (16U)
66001 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
66002 
66003 #define LCDIF_VDCTRL3_VSYNC_ONLY_MASK            (0x10000000U)
66004 #define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT           (28U)
66005 #define LCDIF_VDCTRL3_VSYNC_ONLY(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)
66006 
66007 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK      (0x20000000U)
66008 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT     (29U)
66009 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x)        (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)
66010 
66011 #define LCDIF_VDCTRL3_RSRVD0_MASK                (0xC0000000U)
66012 #define LCDIF_VDCTRL3_RSRVD0_SHIFT               (30U)
66013 #define LCDIF_VDCTRL3_RSRVD0(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
66014 /*! @} */
66015 
66016 /*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */
66017 /*! @{ */
66018 
66019 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)
66020 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)
66021 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
66022 
66023 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK       (0x40000U)
66024 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT      (18U)
66025 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x)         (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)
66026 
66027 #define LCDIF_VDCTRL4_RSRVD0_MASK                (0x1FF80000U)
66028 #define LCDIF_VDCTRL4_RSRVD0_SHIFT               (19U)
66029 #define LCDIF_VDCTRL4_RSRVD0(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)
66030 
66031 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK        (0xE0000000U)
66032 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT       (29U)
66033 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x)          (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
66034 /*! @} */
66035 
66036 /*! @name BM_ERROR_STAT - Bus Master Error Status Register */
66037 /*! @{ */
66038 
66039 #define LCDIF_BM_ERROR_STAT_ADDR_MASK            (0xFFFFFFFFU)
66040 #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT           (0U)
66041 #define LCDIF_BM_ERROR_STAT_ADDR(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)
66042 /*! @} */
66043 
66044 /*! @name CRC_STAT - CRC Status Register */
66045 /*! @{ */
66046 
66047 #define LCDIF_CRC_STAT_CRC_VALUE_MASK            (0xFFFFFFFFU)
66048 #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT           (0U)
66049 #define LCDIF_CRC_STAT_CRC_VALUE(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)
66050 /*! @} */
66051 
66052 /*! @name STAT - LCD Interface Status Register */
66053 /*! @{ */
66054 
66055 #define LCDIF_STAT_LFIFO_COUNT_MASK              (0x1FFU)
66056 #define LCDIF_STAT_LFIFO_COUNT_SHIFT             (0U)
66057 #define LCDIF_STAT_LFIFO_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)
66058 
66059 #define LCDIF_STAT_RSRVD0_MASK                   (0x1FFFE00U)
66060 #define LCDIF_STAT_RSRVD0_SHIFT                  (9U)
66061 #define LCDIF_STAT_RSRVD0(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)
66062 
66063 #define LCDIF_STAT_TXFIFO_EMPTY_MASK             (0x4000000U)
66064 #define LCDIF_STAT_TXFIFO_EMPTY_SHIFT            (26U)
66065 #define LCDIF_STAT_TXFIFO_EMPTY(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)
66066 
66067 #define LCDIF_STAT_TXFIFO_FULL_MASK              (0x8000000U)
66068 #define LCDIF_STAT_TXFIFO_FULL_SHIFT             (27U)
66069 #define LCDIF_STAT_TXFIFO_FULL(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)
66070 
66071 #define LCDIF_STAT_LFIFO_EMPTY_MASK              (0x10000000U)
66072 #define LCDIF_STAT_LFIFO_EMPTY_SHIFT             (28U)
66073 #define LCDIF_STAT_LFIFO_EMPTY(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)
66074 
66075 #define LCDIF_STAT_LFIFO_FULL_MASK               (0x20000000U)
66076 #define LCDIF_STAT_LFIFO_FULL_SHIFT              (29U)
66077 #define LCDIF_STAT_LFIFO_FULL(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)
66078 
66079 #define LCDIF_STAT_DMA_REQ_MASK                  (0x40000000U)
66080 #define LCDIF_STAT_DMA_REQ_SHIFT                 (30U)
66081 #define LCDIF_STAT_DMA_REQ(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK)
66082 
66083 #define LCDIF_STAT_PRESENT_MASK                  (0x80000000U)
66084 #define LCDIF_STAT_PRESENT_SHIFT                 (31U)
66085 #define LCDIF_STAT_PRESENT(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)
66086 /*! @} */
66087 
66088 /*! @name THRES - LCDIF Threshold Register */
66089 /*! @{ */
66090 
66091 #define LCDIF_THRES_RSRVD_MASK                   (0x1FFU)
66092 #define LCDIF_THRES_RSRVD_SHIFT                  (0U)
66093 #define LCDIF_THRES_RSRVD(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD_SHIFT)) & LCDIF_THRES_RSRVD_MASK)
66094 
66095 #define LCDIF_THRES_RSRVD1_MASK                  (0xFE00U)
66096 #define LCDIF_THRES_RSRVD1_SHIFT                 (9U)
66097 #define LCDIF_THRES_RSRVD1(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK)
66098 
66099 #define LCDIF_THRES_FASTCLOCK_MASK               (0x1FF0000U)
66100 #define LCDIF_THRES_FASTCLOCK_SHIFT              (16U)
66101 #define LCDIF_THRES_FASTCLOCK(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK)
66102 
66103 #define LCDIF_THRES_RSRVD2_MASK                  (0xFE000000U)
66104 #define LCDIF_THRES_RSRVD2_SHIFT                 (25U)
66105 #define LCDIF_THRES_RSRVD2(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK)
66106 /*! @} */
66107 
66108 /*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */
66109 /*! @{ */
66110 
66111 #define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK         (0xFFFU)
66112 #define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT        (0U)
66113 #define LCDIF_PIGEONCTRL0_FD_PERIOD(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)
66114 
66115 #define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK         (0xFFF0000U)
66116 #define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT        (16U)
66117 #define LCDIF_PIGEONCTRL0_LD_PERIOD(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)
66118 /*! @} */
66119 
66120 /*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */
66121 /*! @{ */
66122 
66123 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK     (0xFFFU)
66124 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT    (0U)
66125 #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)
66126 
66127 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK     (0xFFF0000U)
66128 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT    (16U)
66129 #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)
66130 /*! @} */
66131 
66132 /*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */
66133 /*! @{ */
66134 
66135 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK     (0xFFFU)
66136 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT    (0U)
66137 #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)
66138 
66139 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK     (0xFFF0000U)
66140 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT    (16U)
66141 #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)
66142 /*! @} */
66143 
66144 /*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */
66145 /*! @{ */
66146 
66147 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK     (0xFFFU)
66148 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT    (0U)
66149 #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)
66150 
66151 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK     (0xFFF0000U)
66152 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT    (16U)
66153 #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x)       (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)
66154 /*! @} */
66155 
66156 /*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */
66157 /*! @{ */
66158 
66159 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK  (0xFFFU)
66160 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)
66161 #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)
66162 
66163 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK  (0xFFF0000U)
66164 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)
66165 #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x)    (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)
66166 /*! @} */
66167 
66168 /*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */
66169 /*! @{ */
66170 
66171 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)
66172 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)
66173 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)
66174 
66175 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
66176 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)
66177 #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)
66178 /*! @} */
66179 
66180 /*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */
66181 /*! @{ */
66182 
66183 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)
66184 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)
66185 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)
66186 
66187 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
66188 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)
66189 #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)
66190 /*! @} */
66191 
66192 /*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */
66193 /*! @{ */
66194 
66195 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)
66196 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)
66197 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)
66198 
66199 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
66200 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)
66201 #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)
66202 /*! @} */
66203 
66204 /*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */
66205 /*! @{ */
66206 
66207 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK    (0x1U)
66208 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT   (0U)
66209 #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)
66210 
66211 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK   (0x2U)
66212 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT  (1U)
66213 #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)
66214 /*! @} */
66215 
66216 /*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */
66217 /*! @{ */
66218 
66219 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)
66220 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)
66221 #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)
66222 
66223 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)
66224 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)
66225 #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)
66226 /*! @} */
66227 
66228 /*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */
66229 /*! @{ */
66230 
66231 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)
66232 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)
66233 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)
66234 
66235 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)
66236 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)
66237 #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)
66238 /*! @} */
66239 
66240 /*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */
66241 /*! @{ */
66242 
66243 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)
66244 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)
66245 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x)  (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)
66246 
66247 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)
66248 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)
66249 #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)
66250 /*! @} */
66251 
66252 /*! @name PIGEON_0 - Panel Interface Signal Generator Register */
66253 /*! @{ */
66254 
66255 #define LCDIF_PIGEON_0_EN_MASK                   (0x1U)
66256 #define LCDIF_PIGEON_0_EN_SHIFT                  (0U)
66257 #define LCDIF_PIGEON_0_EN(x)                     (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)
66258 
66259 #define LCDIF_PIGEON_0_POL_MASK                  (0x2U)
66260 #define LCDIF_PIGEON_0_POL_SHIFT                 (1U)
66261 /*! POL
66262  *  0b0..Normal Signal (Active high)
66263  *  0b1..Inverted signal (Active low)
66264  */
66265 #define LCDIF_PIGEON_0_POL(x)                    (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)
66266 
66267 #define LCDIF_PIGEON_0_INC_SEL_MASK              (0xCU)
66268 #define LCDIF_PIGEON_0_INC_SEL_SHIFT             (2U)
66269 /*! INC_SEL
66270  *  0b00..pclk
66271  *  0b01..Line start pulse
66272  *  0b10..Frame start pulse
66273  *  0b11..Use another signal as tick event
66274  */
66275 #define LCDIF_PIGEON_0_INC_SEL(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)
66276 
66277 #define LCDIF_PIGEON_0_OFFSET_MASK               (0xF0U)
66278 #define LCDIF_PIGEON_0_OFFSET_SHIFT              (4U)
66279 #define LCDIF_PIGEON_0_OFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)
66280 
66281 #define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK         (0xF00U)
66282 #define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT        (8U)
66283 /*! MASK_CNT_SEL
66284  *  0b0000..pclk counter within one hscan state
66285  *  0b0001..pclk cycle within one hscan state
66286  *  0b0010..line counter within one vscan state
66287  *  0b0011..line cycle within one vscan state
66288  *  0b0100..frame counter
66289  *  0b0101..frame cycle
66290  *  0b0110..horizontal counter (pclk counter within one line )
66291  *  0b0111..vertical counter (line counter within one frame)
66292  */
66293 #define LCDIF_PIGEON_0_MASK_CNT_SEL(x)           (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)
66294 
66295 #define LCDIF_PIGEON_0_MASK_CNT_MASK             (0xFFF000U)
66296 #define LCDIF_PIGEON_0_MASK_CNT_SHIFT            (12U)
66297 #define LCDIF_PIGEON_0_MASK_CNT(x)               (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)
66298 
66299 #define LCDIF_PIGEON_0_STATE_MASK_MASK           (0xFF000000U)
66300 #define LCDIF_PIGEON_0_STATE_MASK_SHIFT          (24U)
66301 /*! STATE_MASK
66302  *  0b00000001..FRAME SYNC
66303  *  0b00000010..FRAME BEGIN
66304  *  0b00000100..FRAME DATA
66305  *  0b00001000..FRAME END
66306  *  0b00010000..LINE SYNC
66307  *  0b00100000..LINE BEGIN
66308  *  0b01000000..LINE DATA
66309  *  0b10000000..LINE END
66310  */
66311 #define LCDIF_PIGEON_0_STATE_MASK(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)
66312 /*! @} */
66313 
66314 /* The count of LCDIF_PIGEON_0 */
66315 #define LCDIF_PIGEON_0_COUNT                     (12U)
66316 
66317 /*! @name PIGEON_1 - Panel Interface Signal Generator Register */
66318 /*! @{ */
66319 
66320 #define LCDIF_PIGEON_1_SET_CNT_MASK              (0xFFFFU)
66321 #define LCDIF_PIGEON_1_SET_CNT_SHIFT             (0U)
66322 /*! SET_CNT
66323  *  0b0000000000000000..Start as active
66324  */
66325 #define LCDIF_PIGEON_1_SET_CNT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)
66326 
66327 #define LCDIF_PIGEON_1_CLR_CNT_MASK              (0xFFFF0000U)
66328 #define LCDIF_PIGEON_1_CLR_CNT_SHIFT             (16U)
66329 /*! CLR_CNT
66330  *  0b0000000000000000..Keep active until mask off
66331  */
66332 #define LCDIF_PIGEON_1_CLR_CNT(x)                (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)
66333 /*! @} */
66334 
66335 /* The count of LCDIF_PIGEON_1 */
66336 #define LCDIF_PIGEON_1_COUNT                     (12U)
66337 
66338 /*! @name PIGEON_2 - Panel Interface Signal Generator Register */
66339 /*! @{ */
66340 
66341 #define LCDIF_PIGEON_2_SIG_LOGIC_MASK            (0xFU)
66342 #define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT           (0U)
66343 /*! SIG_LOGIC
66344  *  0b0000..No logic operation
66345  *  0b0001..sigout = sig_another AND this_sig
66346  *  0b0010..sigout = sig_another OR this_sig
66347  *  0b0011..mask = sig_another AND other_masks
66348  */
66349 #define LCDIF_PIGEON_2_SIG_LOGIC(x)              (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)
66350 
66351 #define LCDIF_PIGEON_2_SIG_ANOTHER_MASK          (0x1F0U)
66352 #define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT         (4U)
66353 /*! SIG_ANOTHER
66354  *  0b00000..Keep active until mask off
66355  */
66356 #define LCDIF_PIGEON_2_SIG_ANOTHER(x)            (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)
66357 
66358 #define LCDIF_PIGEON_2_RSVD_MASK                 (0xFFFFFE00U)
66359 #define LCDIF_PIGEON_2_RSVD_SHIFT                (9U)
66360 #define LCDIF_PIGEON_2_RSVD(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)
66361 /*! @} */
66362 
66363 /* The count of LCDIF_PIGEON_2 */
66364 #define LCDIF_PIGEON_2_COUNT                     (12U)
66365 
66366 /*! @name LUT_CTRL - Look Up Table Control Register */
66367 /*! @{ */
66368 
66369 #define LCDIF_LUT_CTRL_LUT_BYPASS_MASK           (0x1U)
66370 #define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT          (0U)
66371 #define LCDIF_LUT_CTRL_LUT_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)
66372 /*! @} */
66373 
66374 /*! @name LUT0_ADDR - Lookup Table 0 Index Register */
66375 /*! @{ */
66376 
66377 #define LCDIF_LUT0_ADDR_ADDR_MASK                (0xFFU)
66378 #define LCDIF_LUT0_ADDR_ADDR_SHIFT               (0U)
66379 #define LCDIF_LUT0_ADDR_ADDR(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)
66380 /*! @} */
66381 
66382 /*! @name LUT0_DATA - Lookup Table 0 Data Register */
66383 /*! @{ */
66384 
66385 #define LCDIF_LUT0_DATA_DATA_MASK                (0xFFFFFFFFU)
66386 #define LCDIF_LUT0_DATA_DATA_SHIFT               (0U)
66387 #define LCDIF_LUT0_DATA_DATA(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)
66388 /*! @} */
66389 
66390 /*! @name LUT1_ADDR - Lookup Table 1 Index Register */
66391 /*! @{ */
66392 
66393 #define LCDIF_LUT1_ADDR_ADDR_MASK                (0xFFU)
66394 #define LCDIF_LUT1_ADDR_ADDR_SHIFT               (0U)
66395 #define LCDIF_LUT1_ADDR_ADDR(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)
66396 /*! @} */
66397 
66398 /*! @name LUT1_DATA - Lookup Table 1 Data Register */
66399 /*! @{ */
66400 
66401 #define LCDIF_LUT1_DATA_DATA_MASK                (0xFFFFFFFFU)
66402 #define LCDIF_LUT1_DATA_DATA_SHIFT               (0U)
66403 #define LCDIF_LUT1_DATA_DATA(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)
66404 /*! @} */
66405 
66406 
66407 /*!
66408  * @}
66409  */ /* end of group LCDIF_Register_Masks */
66410 
66411 
66412 /* LCDIF - Peripheral instance base addresses */
66413 /** Peripheral LCDIF base address */
66414 #define LCDIF_BASE                               (0x40804000u)
66415 /** Peripheral LCDIF base pointer */
66416 #define LCDIF                                    ((LCDIF_Type *)LCDIF_BASE)
66417 /** Array initializer of LCDIF peripheral base addresses */
66418 #define LCDIF_BASE_ADDRS                         { LCDIF_BASE }
66419 /** Array initializer of LCDIF peripheral base pointers */
66420 #define LCDIF_BASE_PTRS                          { LCDIF }
66421 /** Interrupt vectors for the LCDIF peripheral type */
66422 #define LCDIF_IRQ0_IRQS                          { eLCDIF_IRQn }
66423 
66424 /*!
66425  * @}
66426  */ /* end of group LCDIF_Peripheral_Access_Layer */
66427 
66428 
66429 /* ----------------------------------------------------------------------------
66430    -- LCDIFV2 Peripheral Access Layer
66431    ---------------------------------------------------------------------------- */
66432 
66433 /*!
66434  * @addtogroup LCDIFV2_Peripheral_Access_Layer LCDIFV2 Peripheral Access Layer
66435  * @{
66436  */
66437 
66438 /** LCDIFV2 - Register Layout Typedef */
66439 typedef struct {
66440   __IO uint32_t CTRL;                              /**< LCDIFv2 display control Register, offset: 0x0 */
66441   __IO uint32_t CTRL_SET;                          /**< LCDIFv2 display control Register, offset: 0x4 */
66442   __IO uint32_t CTRL_CLR;                          /**< LCDIFv2 display control Register, offset: 0x8 */
66443   __IO uint32_t CTRL_TOG;                          /**< LCDIFv2 display control Register, offset: 0xC */
66444   __IO uint32_t DISP_PARA;                         /**< Display Parameter Register, offset: 0x10 */
66445   __IO uint32_t DISP_SIZE;                         /**< Display Size Register, offset: 0x14 */
66446   __IO uint32_t HSYN_PARA;                         /**< Horizontal Sync Parameter Register, offset: 0x18 */
66447   __IO uint32_t VSYN_PARA;                         /**< Vertical Sync Parameter Register, offset: 0x1C */
66448   struct {                                         /* offset: 0x20, array step: 0x10 */
66449     __IO uint32_t INT_STATUS;                        /**< Interrupt Status Register for domain 0..Interrupt Status Register for domain 1, array offset: 0x20, array step: 0x10 */
66450     __IO uint32_t INT_ENABLE;                        /**< Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1, array offset: 0x24, array step: 0x10 */
66451          uint8_t RESERVED_0[8];
66452   } INT[2];
66453        uint32_t PDI_PARA;                          /**< Reserved, offset: 0x40 */
66454        uint8_t RESERVED_0[444];
66455   struct {                                         /* offset: 0x200, array step: 0x40 */
66456     __IO uint32_t CTRLDESCL1;                        /**< Control Descriptor Layer 1 Register, array offset: 0x200, array step: 0x40 */
66457     __IO uint32_t CTRLDESCL2;                        /**< Control Descriptor Layer 2 Register, array offset: 0x204, array step: 0x40 */
66458     __IO uint32_t CTRLDESCL3;                        /**< Control Descriptor Layer 3 Register, array offset: 0x208, array step: 0x40 */
66459     __IO uint32_t CTRLDESCL4;                        /**< Control Descriptor Layer 4 Register, array offset: 0x20C, array step: 0x40 */
66460     __IO uint32_t CTRLDESCL5;                        /**< Control Descriptor Layer 5 Register, array offset: 0x210, array step: 0x40 */
66461     __IO uint32_t CTRLDESCL6;                        /**< Control Descriptor Layer 6 Register, array offset: 0x214, array step: 0x40 */
66462     __IO uint32_t CSC_COEF0;                         /**< Color Space Conversion Coefficient Register 0, array offset: 0x218, array step: 0x40, valid indices: [0-1] */
66463     __IO uint32_t CSC_COEF1;                         /**< Color Space Conversion Coefficient Register 1, array offset: 0x21C, array step: 0x40, valid indices: [0-1] */
66464     __IO uint32_t CSC_COEF2;                         /**< Color Space Conversion Coefficient Register 2, array offset: 0x220, array step: 0x40, valid indices: [0-1] */
66465          uint8_t RESERVED_0[28];
66466   } LAYER[8];
66467   __IO uint32_t CLUT_LOAD;                         /**< LCDIFv2 CLUT load Register, offset: 0x400 */
66468 } LCDIFV2_Type;
66469 
66470 /* ----------------------------------------------------------------------------
66471    -- LCDIFV2 Register Masks
66472    ---------------------------------------------------------------------------- */
66473 
66474 /*!
66475  * @addtogroup LCDIFV2_Register_Masks LCDIFV2 Register Masks
66476  * @{
66477  */
66478 
66479 /*! @name CTRL - LCDIFv2 display control Register */
66480 /*! @{ */
66481 
66482 #define LCDIFV2_CTRL_INV_HS_MASK                 (0x1U)
66483 #define LCDIFV2_CTRL_INV_HS_SHIFT                (0U)
66484 /*! INV_HS - Invert Horizontal synchronization signal
66485  *  0b0..HSYNC signal not inverted (active HIGH)
66486  *  0b1..Invert HSYNC signal (active LOW)
66487  */
66488 #define LCDIFV2_CTRL_INV_HS(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_HS_SHIFT)) & LCDIFV2_CTRL_INV_HS_MASK)
66489 
66490 #define LCDIFV2_CTRL_INV_VS_MASK                 (0x2U)
66491 #define LCDIFV2_CTRL_INV_VS_SHIFT                (1U)
66492 /*! INV_VS - Invert Vertical synchronization signal
66493  *  0b0..VSYNC signal not inverted (active HIGH)
66494  *  0b1..Invert VSYNC signal (active LOW)
66495  */
66496 #define LCDIFV2_CTRL_INV_VS(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_VS_SHIFT)) & LCDIFV2_CTRL_INV_VS_MASK)
66497 
66498 #define LCDIFV2_CTRL_INV_DE_MASK                 (0x4U)
66499 #define LCDIFV2_CTRL_INV_DE_SHIFT                (2U)
66500 /*! INV_DE - Invert Data Enable polarity
66501  *  0b0..Data enable is active high
66502  *  0b1..Data enable is active low
66503  */
66504 #define LCDIFV2_CTRL_INV_DE(x)                   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_DE_SHIFT)) & LCDIFV2_CTRL_INV_DE_MASK)
66505 
66506 #define LCDIFV2_CTRL_INV_PXCK_MASK               (0x8U)
66507 #define LCDIFV2_CTRL_INV_PXCK_SHIFT              (3U)
66508 /*! INV_PXCK - Polarity change of Pixel Clock
66509  *  0b0..Display samples data on the falling edge
66510  *  0b1..Display samples data on the rising edge
66511  */
66512 #define LCDIFV2_CTRL_INV_PXCK(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_INV_PXCK_MASK)
66513 
66514 #define LCDIFV2_CTRL_NEG_MASK                    (0x10U)
66515 #define LCDIFV2_CTRL_NEG_SHIFT                   (4U)
66516 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated
66517  *  0b0..Output is to remain same
66518  *  0b1..Output to be negated
66519  */
66520 #define LCDIFV2_CTRL_NEG(x)                      (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_NEG_SHIFT)) & LCDIFV2_CTRL_NEG_MASK)
66521 
66522 #define LCDIFV2_CTRL_SW_RESET_MASK               (0x80000000U)
66523 #define LCDIFV2_CTRL_SW_RESET_SHIFT              (31U)
66524 /*! SW_RESET - Software Reset
66525  *  0b0..No action
66526  *  0b1..All LCDIFv2 internal registers are forced into their reset state. User registers are not affected
66527  */
66528 #define LCDIFV2_CTRL_SW_RESET(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SW_RESET_MASK)
66529 /*! @} */
66530 
66531 /*! @name CTRL_SET - LCDIFv2 display control Register */
66532 /*! @{ */
66533 
66534 #define LCDIFV2_CTRL_SET_INV_HS_MASK             (0x1U)
66535 #define LCDIFV2_CTRL_SET_INV_HS_SHIFT            (0U)
66536 /*! INV_HS - Invert Horizontal synchronization signal */
66537 #define LCDIFV2_CTRL_SET_INV_HS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_HS_SHIFT)) & LCDIFV2_CTRL_SET_INV_HS_MASK)
66538 
66539 #define LCDIFV2_CTRL_SET_INV_VS_MASK             (0x2U)
66540 #define LCDIFV2_CTRL_SET_INV_VS_SHIFT            (1U)
66541 /*! INV_VS - Invert Vertical synchronization signal */
66542 #define LCDIFV2_CTRL_SET_INV_VS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_VS_SHIFT)) & LCDIFV2_CTRL_SET_INV_VS_MASK)
66543 
66544 #define LCDIFV2_CTRL_SET_INV_DE_MASK             (0x4U)
66545 #define LCDIFV2_CTRL_SET_INV_DE_SHIFT            (2U)
66546 /*! INV_DE - Invert Data Enable polarity */
66547 #define LCDIFV2_CTRL_SET_INV_DE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_DE_SHIFT)) & LCDIFV2_CTRL_SET_INV_DE_MASK)
66548 
66549 #define LCDIFV2_CTRL_SET_INV_PXCK_MASK           (0x8U)
66550 #define LCDIFV2_CTRL_SET_INV_PXCK_SHIFT          (3U)
66551 /*! INV_PXCK - Polarity change of Pixel Clock */
66552 #define LCDIFV2_CTRL_SET_INV_PXCK(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_SET_INV_PXCK_MASK)
66553 
66554 #define LCDIFV2_CTRL_SET_NEG_MASK                (0x10U)
66555 #define LCDIFV2_CTRL_SET_NEG_SHIFT               (4U)
66556 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated */
66557 #define LCDIFV2_CTRL_SET_NEG(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_NEG_SHIFT)) & LCDIFV2_CTRL_SET_NEG_MASK)
66558 
66559 #define LCDIFV2_CTRL_SET_SW_RESET_MASK           (0x80000000U)
66560 #define LCDIFV2_CTRL_SET_SW_RESET_SHIFT          (31U)
66561 /*! SW_RESET - Software Reset */
66562 #define LCDIFV2_CTRL_SET_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SET_SW_RESET_MASK)
66563 /*! @} */
66564 
66565 /*! @name CTRL_CLR - LCDIFv2 display control Register */
66566 /*! @{ */
66567 
66568 #define LCDIFV2_CTRL_CLR_INV_HS_MASK             (0x1U)
66569 #define LCDIFV2_CTRL_CLR_INV_HS_SHIFT            (0U)
66570 /*! INV_HS - Invert Horizontal synchronization signal */
66571 #define LCDIFV2_CTRL_CLR_INV_HS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_HS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_HS_MASK)
66572 
66573 #define LCDIFV2_CTRL_CLR_INV_VS_MASK             (0x2U)
66574 #define LCDIFV2_CTRL_CLR_INV_VS_SHIFT            (1U)
66575 /*! INV_VS - Invert Vertical synchronization signal */
66576 #define LCDIFV2_CTRL_CLR_INV_VS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_VS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_VS_MASK)
66577 
66578 #define LCDIFV2_CTRL_CLR_INV_DE_MASK             (0x4U)
66579 #define LCDIFV2_CTRL_CLR_INV_DE_SHIFT            (2U)
66580 /*! INV_DE - Invert Data Enable polarity */
66581 #define LCDIFV2_CTRL_CLR_INV_DE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_DE_SHIFT)) & LCDIFV2_CTRL_CLR_INV_DE_MASK)
66582 
66583 #define LCDIFV2_CTRL_CLR_INV_PXCK_MASK           (0x8U)
66584 #define LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT          (3U)
66585 /*! INV_PXCK - Polarity change of Pixel Clock */
66586 #define LCDIFV2_CTRL_CLR_INV_PXCK(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_CLR_INV_PXCK_MASK)
66587 
66588 #define LCDIFV2_CTRL_CLR_NEG_MASK                (0x10U)
66589 #define LCDIFV2_CTRL_CLR_NEG_SHIFT               (4U)
66590 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated */
66591 #define LCDIFV2_CTRL_CLR_NEG(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_NEG_SHIFT)) & LCDIFV2_CTRL_CLR_NEG_MASK)
66592 
66593 #define LCDIFV2_CTRL_CLR_SW_RESET_MASK           (0x80000000U)
66594 #define LCDIFV2_CTRL_CLR_SW_RESET_SHIFT          (31U)
66595 /*! SW_RESET - Software Reset */
66596 #define LCDIFV2_CTRL_CLR_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_SW_RESET_SHIFT)) & LCDIFV2_CTRL_CLR_SW_RESET_MASK)
66597 /*! @} */
66598 
66599 /*! @name CTRL_TOG - LCDIFv2 display control Register */
66600 /*! @{ */
66601 
66602 #define LCDIFV2_CTRL_TOG_INV_HS_MASK             (0x1U)
66603 #define LCDIFV2_CTRL_TOG_INV_HS_SHIFT            (0U)
66604 /*! INV_HS - Invert Horizontal synchronization signal */
66605 #define LCDIFV2_CTRL_TOG_INV_HS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_HS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_HS_MASK)
66606 
66607 #define LCDIFV2_CTRL_TOG_INV_VS_MASK             (0x2U)
66608 #define LCDIFV2_CTRL_TOG_INV_VS_SHIFT            (1U)
66609 /*! INV_VS - Invert Vertical synchronization signal */
66610 #define LCDIFV2_CTRL_TOG_INV_VS(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_VS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_VS_MASK)
66611 
66612 #define LCDIFV2_CTRL_TOG_INV_DE_MASK             (0x4U)
66613 #define LCDIFV2_CTRL_TOG_INV_DE_SHIFT            (2U)
66614 /*! INV_DE - Invert Data Enable polarity */
66615 #define LCDIFV2_CTRL_TOG_INV_DE(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_DE_SHIFT)) & LCDIFV2_CTRL_TOG_INV_DE_MASK)
66616 
66617 #define LCDIFV2_CTRL_TOG_INV_PXCK_MASK           (0x8U)
66618 #define LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT          (3U)
66619 /*! INV_PXCK - Polarity change of Pixel Clock */
66620 #define LCDIFV2_CTRL_TOG_INV_PXCK(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_TOG_INV_PXCK_MASK)
66621 
66622 #define LCDIFV2_CTRL_TOG_NEG_MASK                (0x10U)
66623 #define LCDIFV2_CTRL_TOG_NEG_SHIFT               (4U)
66624 /*! NEG - Indicates if value at the output (pixel data output) needs to be negated */
66625 #define LCDIFV2_CTRL_TOG_NEG(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_NEG_SHIFT)) & LCDIFV2_CTRL_TOG_NEG_MASK)
66626 
66627 #define LCDIFV2_CTRL_TOG_SW_RESET_MASK           (0x80000000U)
66628 #define LCDIFV2_CTRL_TOG_SW_RESET_SHIFT          (31U)
66629 /*! SW_RESET - Software Reset */
66630 #define LCDIFV2_CTRL_TOG_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_SW_RESET_SHIFT)) & LCDIFV2_CTRL_TOG_SW_RESET_MASK)
66631 /*! @} */
66632 
66633 /*! @name DISP_PARA - Display Parameter Register */
66634 /*! @{ */
66635 
66636 #define LCDIFV2_DISP_PARA_BGND_B_MASK            (0xFFU)
66637 #define LCDIFV2_DISP_PARA_BGND_B_SHIFT           (0U)
66638 /*! BGND_B - Blue component of the default color displayed in the sectors where no layer is active */
66639 #define LCDIFV2_DISP_PARA_BGND_B(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_B_SHIFT)) & LCDIFV2_DISP_PARA_BGND_B_MASK)
66640 
66641 #define LCDIFV2_DISP_PARA_BGND_G_MASK            (0xFF00U)
66642 #define LCDIFV2_DISP_PARA_BGND_G_SHIFT           (8U)
66643 /*! BGND_G - Green component of the default color displayed in the sectors where no layer is active */
66644 #define LCDIFV2_DISP_PARA_BGND_G(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_G_SHIFT)) & LCDIFV2_DISP_PARA_BGND_G_MASK)
66645 
66646 #define LCDIFV2_DISP_PARA_BGND_R_MASK            (0xFF0000U)
66647 #define LCDIFV2_DISP_PARA_BGND_R_SHIFT           (16U)
66648 /*! BGND_R - Red component of the default color displayed in the sectors where no layer is active */
66649 #define LCDIFV2_DISP_PARA_BGND_R(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_R_SHIFT)) & LCDIFV2_DISP_PARA_BGND_R_MASK)
66650 
66651 #define LCDIFV2_DISP_PARA_DISP_MODE_MASK         (0x3000000U)
66652 #define LCDIFV2_DISP_PARA_DISP_MODE_SHIFT        (24U)
66653 /*! DISP_MODE - LCDIFv2 operating mode
66654  *  0b00..Normal mode. Panel content controlled by layer configuration
66655  *  0b01..Test Mode1(BGND Color Display)
66656  *  0b10..Test Mode2(Column Color Bar)
66657  *  0b11..Test Mode3(Row Color Bar)
66658  */
66659 #define LCDIFV2_DISP_PARA_DISP_MODE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_MODE_SHIFT)) & LCDIFV2_DISP_PARA_DISP_MODE_MASK)
66660 
66661 #define LCDIFV2_DISP_PARA_LINE_PATTERN_MASK      (0x1C000000U)
66662 #define LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT     (26U)
66663 /*! LINE_PATTERN - LCDIFv2 line output order
66664  *  0b000..RGB
66665  *  0b001..RBG
66666  *  0b010..GBR
66667  *  0b011..GRB
66668  *  0b100..BRG
66669  *  0b101..BGR
66670  */
66671 #define LCDIFV2_DISP_PARA_LINE_PATTERN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT)) & LCDIFV2_DISP_PARA_LINE_PATTERN_MASK)
66672 
66673 #define LCDIFV2_DISP_PARA_DISP_ON_MASK           (0x80000000U)
66674 #define LCDIFV2_DISP_PARA_DISP_ON_SHIFT          (31U)
66675 /*! DISP_ON - Display panel On/Off mode
66676  *  0b0..Display Off
66677  *  0b1..Display On
66678  */
66679 #define LCDIFV2_DISP_PARA_DISP_ON(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_ON_SHIFT)) & LCDIFV2_DISP_PARA_DISP_ON_MASK)
66680 /*! @} */
66681 
66682 /*! @name DISP_SIZE - Display Size Register */
66683 /*! @{ */
66684 
66685 #define LCDIFV2_DISP_SIZE_DELTA_X_MASK           (0xFFFU)
66686 #define LCDIFV2_DISP_SIZE_DELTA_X_SHIFT          (0U)
66687 /*! DELTA_X - Sets the display size horizontal resolution in pixels */
66688 #define LCDIFV2_DISP_SIZE_DELTA_X(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_X_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_X_MASK)
66689 
66690 #define LCDIFV2_DISP_SIZE_DELTA_Y_MASK           (0xFFF0000U)
66691 #define LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT          (16U)
66692 /*! DELTA_Y - Sets the display size vertical resolution in pixels */
66693 #define LCDIFV2_DISP_SIZE_DELTA_Y(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_Y_MASK)
66694 /*! @} */
66695 
66696 /*! @name HSYN_PARA - Horizontal Sync Parameter Register */
66697 /*! @{ */
66698 
66699 #define LCDIFV2_HSYN_PARA_FP_H_MASK              (0x1FFU)
66700 #define LCDIFV2_HSYN_PARA_FP_H_SHIFT             (0U)
66701 /*! FP_H - HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1 */
66702 #define LCDIFV2_HSYN_PARA_FP_H(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_FP_H_SHIFT)) & LCDIFV2_HSYN_PARA_FP_H_MASK)
66703 
66704 #define LCDIFV2_HSYN_PARA_PW_H_MASK              (0xFF800U)
66705 #define LCDIFV2_HSYN_PARA_PW_H_SHIFT             (11U)
66706 /*! PW_H - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1 */
66707 #define LCDIFV2_HSYN_PARA_PW_H(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_PW_H_SHIFT)) & LCDIFV2_HSYN_PARA_PW_H_MASK)
66708 
66709 #define LCDIFV2_HSYN_PARA_BP_H_MASK              (0x7FC00000U)
66710 #define LCDIFV2_HSYN_PARA_BP_H_SHIFT             (22U)
66711 /*! BP_H - HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1 */
66712 #define LCDIFV2_HSYN_PARA_BP_H(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_BP_H_SHIFT)) & LCDIFV2_HSYN_PARA_BP_H_MASK)
66713 /*! @} */
66714 
66715 /*! @name VSYN_PARA - Vertical Sync Parameter Register */
66716 /*! @{ */
66717 
66718 #define LCDIFV2_VSYN_PARA_FP_V_MASK              (0x1FFU)
66719 #define LCDIFV2_VSYN_PARA_FP_V_SHIFT             (0U)
66720 /*! FP_V - VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1 */
66721 #define LCDIFV2_VSYN_PARA_FP_V(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_FP_V_SHIFT)) & LCDIFV2_VSYN_PARA_FP_V_MASK)
66722 
66723 #define LCDIFV2_VSYN_PARA_PW_V_MASK              (0xFF800U)
66724 #define LCDIFV2_VSYN_PARA_PW_V_SHIFT             (11U)
66725 /*! PW_V - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1 */
66726 #define LCDIFV2_VSYN_PARA_PW_V(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_PW_V_SHIFT)) & LCDIFV2_VSYN_PARA_PW_V_MASK)
66727 
66728 #define LCDIFV2_VSYN_PARA_BP_V_MASK              (0x7FC00000U)
66729 #define LCDIFV2_VSYN_PARA_BP_V_SHIFT             (22U)
66730 /*! BP_V - VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1 */
66731 #define LCDIFV2_VSYN_PARA_BP_V(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_BP_V_SHIFT)) & LCDIFV2_VSYN_PARA_BP_V_MASK)
66732 /*! @} */
66733 
66734 /*! @name INT_STATUS - Interrupt Status Register for domain 0..Interrupt Status Register for domain 1 */
66735 /*! @{ */
66736 
66737 #define LCDIFV2_INT_STATUS_VSYNC_MASK            (0x1U)
66738 #define LCDIFV2_INT_STATUS_VSYNC_SHIFT           (0U)
66739 /*! VSYNC - Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame)
66740  *  0b0..VSYNC has not started
66741  *  0b1..VSYNC has started
66742  */
66743 #define LCDIFV2_INT_STATUS_VSYNC(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VSYNC_SHIFT)) & LCDIFV2_INT_STATUS_VSYNC_MASK)
66744 
66745 #define LCDIFV2_INT_STATUS_UNDERRUN_MASK         (0x2U)
66746 #define LCDIFV2_INT_STATUS_UNDERRUN_SHIFT        (1U)
66747 /*! UNDERRUN - Interrupt flag to indicate the output buffer underrun condition
66748  *  0b0..Output buffer not underrun
66749  *  0b1..Output buffer underrun
66750  */
66751 #define LCDIFV2_INT_STATUS_UNDERRUN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_UNDERRUN_SHIFT)) & LCDIFV2_INT_STATUS_UNDERRUN_MASK)
66752 
66753 #define LCDIFV2_INT_STATUS_VS_BLANK_MASK         (0x4U)
66754 #define LCDIFV2_INT_STATUS_VS_BLANK_SHIFT        (2U)
66755 /*! VS_BLANK - Interrupt flag to indicate vertical blanking period
66756  *  0b0..Vertical blanking period has not started
66757  *  0b1..Vertical blanking period has started
66758  */
66759 #define LCDIFV2_INT_STATUS_VS_BLANK(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VS_BLANK_SHIFT)) & LCDIFV2_INT_STATUS_VS_BLANK_MASK)
66760 
66761 #define LCDIFV2_INT_STATUS_DMA_ERR_MASK          (0xFF00U)
66762 #define LCDIFV2_INT_STATUS_DMA_ERR_SHIFT         (8U)
66763 /*! DMA_ERR - Interrupt flag to indicate that which PLANE has Read Error on the AXI interface */
66764 #define LCDIFV2_INT_STATUS_DMA_ERR(x)            (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_ERR_SHIFT)) & LCDIFV2_INT_STATUS_DMA_ERR_MASK)
66765 
66766 #define LCDIFV2_INT_STATUS_DMA_DONE_MASK         (0xFF0000U)
66767 #define LCDIFV2_INT_STATUS_DMA_DONE_SHIFT        (16U)
66768 /*! DMA_DONE - Interrupt flag to indicate that which PLANE has fetched the last pixel from memory */
66769 #define LCDIFV2_INT_STATUS_DMA_DONE(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_DONE_SHIFT)) & LCDIFV2_INT_STATUS_DMA_DONE_MASK)
66770 
66771 #define LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK       (0xFF000000U)
66772 #define LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT      (24U)
66773 /*! FIFO_EMPTY - Interrupt flag to indicate that which FIFO in the pixel blending underflowed */
66774 #define LCDIFV2_INT_STATUS_FIFO_EMPTY(x)         (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT)) & LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK)
66775 /*! @} */
66776 
66777 /* The count of LCDIFV2_INT_STATUS */
66778 #define LCDIFV2_INT_STATUS_COUNT                 (2U)
66779 
66780 /*! @name INT_ENABLE - Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1 */
66781 /*! @{ */
66782 
66783 #define LCDIFV2_INT_ENABLE_VSYNC_EN_MASK         (0x1U)
66784 #define LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT        (0U)
66785 /*! VSYNC_EN - Enable Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame)
66786  *  0b0..VSYNC interrupt disable
66787  *  0b1..VSYNC interrupt enable
66788  */
66789 #define LCDIFV2_INT_ENABLE_VSYNC_EN(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VSYNC_EN_MASK)
66790 
66791 #define LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK      (0x2U)
66792 #define LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT     (1U)
66793 /*! UNDERRUN_EN - Enable Interrupt flag to indicate the output buffer underrun condition
66794  *  0b0..Output buffer underrun disable
66795  *  0b1..Output buffer underrun enable
66796  */
66797 #define LCDIFV2_INT_ENABLE_UNDERRUN_EN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT)) & LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK)
66798 
66799 #define LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK      (0x4U)
66800 #define LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT     (2U)
66801 /*! VS_BLANK_EN - Enable Interrupt flag to indicate vertical blanking period
66802  *  0b0..Vertical blanking start interrupt disable
66803  *  0b1..Vertical blanking start interrupt enable
66804  */
66805 #define LCDIFV2_INT_ENABLE_VS_BLANK_EN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK)
66806 
66807 #define LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK       (0xFF00U)
66808 #define LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT      (8U)
66809 /*! DMA_ERR_EN - Enable Interrupt flag to indicate that which PLANE has Read Error on the AXI interface */
66810 #define LCDIFV2_INT_ENABLE_DMA_ERR_EN(x)         (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK)
66811 
66812 #define LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK      (0xFF0000U)
66813 #define LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT     (16U)
66814 /*! DMA_DONE_EN - Enable Interrupt flag to indicate that which PLANE has fetched the last pixel from memory */
66815 #define LCDIFV2_INT_ENABLE_DMA_DONE_EN(x)        (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK)
66816 
66817 #define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK    (0xFF000000U)
66818 #define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT   (24U)
66819 /*! FIFO_EMPTY_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed */
66820 #define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT)) & LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK)
66821 /*! @} */
66822 
66823 /* The count of LCDIFV2_INT_ENABLE */
66824 #define LCDIFV2_INT_ENABLE_COUNT                 (2U)
66825 
66826 /*! @name CTRLDESCL1 - Control Descriptor Layer 1 Register */
66827 /*! @{ */
66828 
66829 #define LCDIFV2_CTRLDESCL1_WIDTH_MASK            (0xFFFU)
66830 #define LCDIFV2_CTRLDESCL1_WIDTH_SHIFT           (0U)
66831 /*! WIDTH - Width of the layer in pixels */
66832 #define LCDIFV2_CTRLDESCL1_WIDTH(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_WIDTH_SHIFT)) & LCDIFV2_CTRLDESCL1_WIDTH_MASK)
66833 
66834 #define LCDIFV2_CTRLDESCL1_HEIGHT_MASK           (0xFFF0000U)
66835 #define LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT          (16U)
66836 /*! HEIGHT - Height of the layer in pixels */
66837 #define LCDIFV2_CTRLDESCL1_HEIGHT(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT)) & LCDIFV2_CTRLDESCL1_HEIGHT_MASK)
66838 /*! @} */
66839 
66840 /* The count of LCDIFV2_CTRLDESCL1 */
66841 #define LCDIFV2_CTRLDESCL1_COUNT                 (8U)
66842 
66843 /*! @name CTRLDESCL2 - Control Descriptor Layer 2 Register */
66844 /*! @{ */
66845 
66846 #define LCDIFV2_CTRLDESCL2_POSX_MASK             (0xFFFU)
66847 #define LCDIFV2_CTRLDESCL2_POSX_SHIFT            (0U)
66848 /*! POSX - POS X */
66849 #define LCDIFV2_CTRLDESCL2_POSX(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSX_SHIFT)) & LCDIFV2_CTRLDESCL2_POSX_MASK)
66850 
66851 #define LCDIFV2_CTRLDESCL2_POSY_MASK             (0xFFF0000U)
66852 #define LCDIFV2_CTRLDESCL2_POSY_SHIFT            (16U)
66853 /*! POSY - The vertical position of top row of the layer, where 0 is the top row of the panel, only
66854  *    positive values are below the top row of the panel
66855  */
66856 #define LCDIFV2_CTRLDESCL2_POSY(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSY_SHIFT)) & LCDIFV2_CTRLDESCL2_POSY_MASK)
66857 /*! @} */
66858 
66859 /* The count of LCDIFV2_CTRLDESCL2 */
66860 #define LCDIFV2_CTRLDESCL2_COUNT                 (8U)
66861 
66862 /*! @name CTRLDESCL3 - Control Descriptor Layer 3 Register */
66863 /*! @{ */
66864 
66865 #define LCDIFV2_CTRLDESCL3_PITCH_MASK            (0xFFFFU)
66866 #define LCDIFV2_CTRLDESCL3_PITCH_SHIFT           (0U)
66867 /*! PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity
66868  *    is supported, but SW should align to 64B boundry
66869  */
66870 #define LCDIFV2_CTRLDESCL3_PITCH(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL3_PITCH_SHIFT)) & LCDIFV2_CTRLDESCL3_PITCH_MASK)
66871 /*! @} */
66872 
66873 /* The count of LCDIFV2_CTRLDESCL3 */
66874 #define LCDIFV2_CTRLDESCL3_COUNT                 (8U)
66875 
66876 /*! @name CTRLDESCL4 - Control Descriptor Layer 4 Register */
66877 /*! @{ */
66878 
66879 #define LCDIFV2_CTRLDESCL4_ADDR_MASK             (0xFFFFFFFFU)
66880 #define LCDIFV2_CTRLDESCL4_ADDR_SHIFT            (0U)
66881 /*! ADDR - Address of layer data in the memory. The address programmed should be 64-bit aligned */
66882 #define LCDIFV2_CTRLDESCL4_ADDR(x)               (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL4_ADDR_SHIFT)) & LCDIFV2_CTRLDESCL4_ADDR_MASK)
66883 /*! @} */
66884 
66885 /* The count of LCDIFV2_CTRLDESCL4 */
66886 #define LCDIFV2_CTRLDESCL4_COUNT                 (8U)
66887 
66888 /*! @name CTRLDESCL5 - Control Descriptor Layer 5 Register */
66889 /*! @{ */
66890 
66891 #define LCDIFV2_CTRLDESCL5_AB_MODE_MASK          (0x3U)
66892 #define LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT         (0U)
66893 /*! AB_MODE - Alpha Blending Mode
66894  *  0b00..No alpha Blending (The SAFETY_EN bit need set to 1)
66895  *  0b01..Blend with global ALPHA
66896  *  0b10..Blend with embedded ALPHA
66897  *  0b11..Blend with Porter Duff enable
66898  */
66899 #define LCDIFV2_CTRLDESCL5_AB_MODE(x)            (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_AB_MODE_MASK)
66900 
66901 #define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK   (0x30U)
66902 #define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT  (4U)
66903 /*! PD_FACTOR_MODE - Porter Duff factor mode
66904  *  0b00..Using 1
66905  *  0b01..Using 0
66906  *  0b10..Using straight alpha
66907  *  0b11..Using inverse alpha
66908  */
66909 #define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE(x)     (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK)
66910 
66911 #define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK (0xC0U)
66912 #define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT (6U)
66913 /*! PD_GLOBAL_ALPHA_MODE - Porter Duff global alpha mode
66914  *  0b00..Using global alpha
66915  *  0b01..Using local alpha
66916  *  0b10..Using scaled alpha
66917  *  0b11..Using scaled alpha
66918  */
66919 #define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK)
66920 
66921 #define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK    (0x100U)
66922 #define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT   (8U)
66923 /*! PD_ALPHA_MODE - Porter Duff alpha mode
66924  *  0b0..Straight mode for Porter Duff alpha
66925  *  0b1..Inversed mode for Porter Duff alpha
66926  */
66927 #define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK)
66928 
66929 #define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK    (0x200U)
66930 #define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT   (9U)
66931 /*! PD_COLOR_MODE - Porter Duff alpha mode
66932  *  0b0..Straight mode for Porter Duff color
66933  *  0b1..Inversed mode for Porter Duff color
66934  */
66935 #define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE(x)      (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK)
66936 
66937 #define LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK       (0xC000U)
66938 #define LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT      (14U)
66939 /*! YUV_FORMAT - The YUV422 input format selection
66940  *  0b00..The YVYU422 8bit sequence is U1,Y1,V1,Y2
66941  *  0b01..The YVYU422 8bit sequence is V1,Y1,U1,Y2
66942  *  0b10..The YVYU422 8bit sequence is Y1,U1,Y2,V1
66943  *  0b11..The YVYU422 8bit sequence is Y1,V1,Y2,U1
66944  */
66945 #define LCDIFV2_CTRLDESCL5_YUV_FORMAT(x)         (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT)) & LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK)
66946 
66947 #define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK     (0xFF0000U)
66948 #define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT    (16U)
66949 /*! GLOBAL_ALPHA - Global Alpha */
66950 #define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA(x)       (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT)) & LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK)
66951 
66952 #define LCDIFV2_CTRLDESCL5_BPP_MASK              (0xF000000U)
66953 #define LCDIFV2_CTRLDESCL5_BPP_SHIFT             (24U)
66954 /*! BPP - Layer encoding format (bit per pixel)
66955  *  0b0000..1 bpp
66956  *  0b0001..2 bpp
66957  *  0b0010..4 bpp
66958  *  0b0011..8 bpp
66959  *  0b0100..16 bpp (RGB565)
66960  *  0b0101..16 bpp (ARGB1555)
66961  *  0b0110..16 bpp (ARGB4444)
66962  *  0b0111..YCbCr422 (Only layer 0/1 can support this format)
66963  *  0b1000..24 bpp (RGB888)
66964  *  0b1001..32 bpp (ARGB8888)
66965  *  0b1010..32 bpp (ABGR8888)
66966  */
66967 #define LCDIFV2_CTRLDESCL5_BPP(x)                (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_BPP_SHIFT)) & LCDIFV2_CTRLDESCL5_BPP_MASK)
66968 
66969 #define LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK        (0x10000000U)
66970 #define LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT       (28U)
66971 /*! SAFETY_EN - Safety Mode Enable Bit
66972  *  0b0..Safety Mode is disabled
66973  *  0b1..Safety Mode is enabled for this layer
66974  */
66975 #define LCDIFV2_CTRLDESCL5_SAFETY_EN(x)          (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK)
66976 
66977 #define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK   (0x40000000U)
66978 #define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT  (30U)
66979 /*! SHADOW_LOAD_EN - Shadow Load Enable */
66980 #define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN(x)     (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK)
66981 
66982 #define LCDIFV2_CTRLDESCL5_EN_MASK               (0x80000000U)
66983 #define LCDIFV2_CTRLDESCL5_EN_SHIFT              (31U)
66984 /*! EN - Enable the layer for DMA
66985  *  0b0..OFF
66986  *  0b1..ON
66987  */
66988 #define LCDIFV2_CTRLDESCL5_EN(x)                 (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_EN_MASK)
66989 /*! @} */
66990 
66991 /* The count of LCDIFV2_CTRLDESCL5 */
66992 #define LCDIFV2_CTRLDESCL5_COUNT                 (8U)
66993 
66994 /*! @name CTRLDESCL6 - Control Descriptor Layer 6 Register */
66995 /*! @{ */
66996 
66997 #define LCDIFV2_CTRLDESCL6_BCLR_B_MASK           (0xFFU)
66998 #define LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT          (0U)
66999 /*! BCLR_B - Background B component value */
67000 #define LCDIFV2_CTRLDESCL6_BCLR_B(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_B_MASK)
67001 
67002 #define LCDIFV2_CTRLDESCL6_BCLR_G_MASK           (0xFF00U)
67003 #define LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT          (8U)
67004 /*! BCLR_G - Background G component value */
67005 #define LCDIFV2_CTRLDESCL6_BCLR_G(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_G_MASK)
67006 
67007 #define LCDIFV2_CTRLDESCL6_BCLR_R_MASK           (0xFF0000U)
67008 #define LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT          (16U)
67009 /*! BCLR_R - Background R component value */
67010 #define LCDIFV2_CTRLDESCL6_BCLR_R(x)             (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_R_MASK)
67011 /*! @} */
67012 
67013 /* The count of LCDIFV2_CTRLDESCL6 */
67014 #define LCDIFV2_CTRLDESCL6_COUNT                 (8U)
67015 
67016 /*! @name CSC_COEF0 - Color Space Conversion Coefficient Register 0 */
67017 /*! @{ */
67018 
67019 #define LCDIFV2_CSC_COEF0_Y_OFFSET_MASK          (0x1FFU)
67020 #define LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT         (0U)
67021 /*! Y_OFFSET - Y OFFSET */
67022 #define LCDIFV2_CSC_COEF0_Y_OFFSET(x)            (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_Y_OFFSET_MASK)
67023 
67024 #define LCDIFV2_CSC_COEF0_UV_OFFSET_MASK         (0x3FE00U)
67025 #define LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT        (9U)
67026 /*! UV_OFFSET - UV OFFSET */
67027 #define LCDIFV2_CSC_COEF0_UV_OFFSET(x)           (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_UV_OFFSET_MASK)
67028 
67029 #define LCDIFV2_CSC_COEF0_C0_MASK                (0x1FFC0000U)
67030 #define LCDIFV2_CSC_COEF0_C0_SHIFT               (18U)
67031 /*! C0 - Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) */
67032 #define LCDIFV2_CSC_COEF0_C0(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_C0_SHIFT)) & LCDIFV2_CSC_COEF0_C0_MASK)
67033 
67034 #define LCDIFV2_CSC_COEF0_ENABLE_MASK            (0x40000000U)
67035 #define LCDIFV2_CSC_COEF0_ENABLE_SHIFT           (30U)
67036 /*! ENABLE - Enable the CSC unit in the LCDIFv2 plane data path
67037  *  0b0..The CSC is bypassed and the input pixels are RGB data already
67038  *  0b1..The CSC is enabled and the pixels will be converted to RGB data
67039  */
67040 #define LCDIFV2_CSC_COEF0_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_ENABLE_SHIFT)) & LCDIFV2_CSC_COEF0_ENABLE_MASK)
67041 
67042 #define LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK        (0x80000000U)
67043 #define LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT       (31U)
67044 /*! YCBCR_MODE - This bit changes the behavior when performing U/V converting
67045  *  0b0..Converting YUV to RGB data
67046  *  0b1..Converting YCbCr to RGB data
67047  */
67048 #define LCDIFV2_CSC_COEF0_YCBCR_MODE(x)          (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT)) & LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK)
67049 /*! @} */
67050 
67051 /* The count of LCDIFV2_CSC_COEF0 */
67052 #define LCDIFV2_CSC_COEF0_COUNT                  (8U)
67053 
67054 /*! @name CSC_COEF1 - Color Space Conversion Coefficient Register 1 */
67055 /*! @{ */
67056 
67057 #define LCDIFV2_CSC_COEF1_C4_MASK                (0x7FFU)
67058 #define LCDIFV2_CSC_COEF1_C4_SHIFT               (0U)
67059 /*! C4 - Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017) */
67060 #define LCDIFV2_CSC_COEF1_C4(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C4_SHIFT)) & LCDIFV2_CSC_COEF1_C4_MASK)
67061 
67062 #define LCDIFV2_CSC_COEF1_C1_MASK                (0x7FF0000U)
67063 #define LCDIFV2_CSC_COEF1_C1_SHIFT               (16U)
67064 /*! C1 - Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596) */
67065 #define LCDIFV2_CSC_COEF1_C1(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C1_SHIFT)) & LCDIFV2_CSC_COEF1_C1_MASK)
67066 /*! @} */
67067 
67068 /* The count of LCDIFV2_CSC_COEF1 */
67069 #define LCDIFV2_CSC_COEF1_COUNT                  (8U)
67070 
67071 /*! @name CSC_COEF2 - Color Space Conversion Coefficient Register 2 */
67072 /*! @{ */
67073 
67074 #define LCDIFV2_CSC_COEF2_C3_MASK                (0x7FFU)
67075 #define LCDIFV2_CSC_COEF2_C3_SHIFT               (0U)
67076 /*! C3 - Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392) */
67077 #define LCDIFV2_CSC_COEF2_C3(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C3_SHIFT)) & LCDIFV2_CSC_COEF2_C3_MASK)
67078 
67079 #define LCDIFV2_CSC_COEF2_C2_MASK                (0x7FF0000U)
67080 #define LCDIFV2_CSC_COEF2_C2_SHIFT               (16U)
67081 /*! C2 - Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813) */
67082 #define LCDIFV2_CSC_COEF2_C2(x)                  (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C2_SHIFT)) & LCDIFV2_CSC_COEF2_C2_MASK)
67083 /*! @} */
67084 
67085 /* The count of LCDIFV2_CSC_COEF2 */
67086 #define LCDIFV2_CSC_COEF2_COUNT                  (8U)
67087 
67088 /*! @name CLUT_LOAD - LCDIFv2 CLUT load Register */
67089 /*! @{ */
67090 
67091 #define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK    (0x1U)
67092 #define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT   (0U)
67093 /*! CLUT_UPDATE_EN - CLUT Update Enable */
67094 #define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN(x)      (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT)) & LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK)
67095 
67096 #define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK      (0x70U)
67097 #define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT     (4U)
67098 /*! SEL_CLUT_NUM - Selected CLUT Number */
67099 #define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM(x)        (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT)) & LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK)
67100 /*! @} */
67101 
67102 
67103 /*!
67104  * @}
67105  */ /* end of group LCDIFV2_Register_Masks */
67106 
67107 
67108 /* LCDIFV2 - Peripheral instance base addresses */
67109 /** Peripheral LCDIFV2 base address */
67110 #define LCDIFV2_BASE                             (0x40808000u)
67111 /** Peripheral LCDIFV2 base pointer */
67112 #define LCDIFV2                                  ((LCDIFV2_Type *)LCDIFV2_BASE)
67113 /** Array initializer of LCDIFV2 peripheral base addresses */
67114 #define LCDIFV2_BASE_ADDRS                       { LCDIFV2_BASE }
67115 /** Array initializer of LCDIFV2 peripheral base pointers */
67116 #define LCDIFV2_BASE_PTRS                        { LCDIFV2 }
67117 
67118 /*!
67119  * @}
67120  */ /* end of group LCDIFV2_Peripheral_Access_Layer */
67121 
67122 
67123 /* ----------------------------------------------------------------------------
67124    -- LPI2C Peripheral Access Layer
67125    ---------------------------------------------------------------------------- */
67126 
67127 /*!
67128  * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
67129  * @{
67130  */
67131 
67132 /** LPI2C - Register Layout Typedef */
67133 typedef struct {
67134   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
67135   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
67136        uint8_t RESERVED_0[8];
67137   __IO uint32_t MCR;                               /**< Master Control, offset: 0x10 */
67138   __IO uint32_t MSR;                               /**< Master Status, offset: 0x14 */
67139   __IO uint32_t MIER;                              /**< Master Interrupt Enable, offset: 0x18 */
67140   __IO uint32_t MDER;                              /**< Master DMA Enable, offset: 0x1C */
67141   __IO uint32_t MCFGR0;                            /**< Master Configuration 0, offset: 0x20 */
67142   __IO uint32_t MCFGR1;                            /**< Master Configuration 1, offset: 0x24 */
67143   __IO uint32_t MCFGR2;                            /**< Master Configuration 2, offset: 0x28 */
67144   __IO uint32_t MCFGR3;                            /**< Master Configuration 3, offset: 0x2C */
67145        uint8_t RESERVED_1[16];
67146   __IO uint32_t MDMR;                              /**< Master Data Match, offset: 0x40 */
67147        uint8_t RESERVED_2[4];
67148   __IO uint32_t MCCR0;                             /**< Master Clock Configuration 0, offset: 0x48 */
67149        uint8_t RESERVED_3[4];
67150   __IO uint32_t MCCR1;                             /**< Master Clock Configuration 1, offset: 0x50 */
67151        uint8_t RESERVED_4[4];
67152   __IO uint32_t MFCR;                              /**< Master FIFO Control, offset: 0x58 */
67153   __I  uint32_t MFSR;                              /**< Master FIFO Status, offset: 0x5C */
67154   __O  uint32_t MTDR;                              /**< Master Transmit Data, offset: 0x60 */
67155        uint8_t RESERVED_5[12];
67156   __I  uint32_t MRDR;                              /**< Master Receive Data, offset: 0x70 */
67157        uint8_t RESERVED_6[156];
67158   __IO uint32_t SCR;                               /**< Slave Control, offset: 0x110 */
67159   __IO uint32_t SSR;                               /**< Slave Status, offset: 0x114 */
67160   __IO uint32_t SIER;                              /**< Slave Interrupt Enable, offset: 0x118 */
67161   __IO uint32_t SDER;                              /**< Slave DMA Enable, offset: 0x11C */
67162        uint8_t RESERVED_7[4];
67163   __IO uint32_t SCFGR1;                            /**< Slave Configuration 1, offset: 0x124 */
67164   __IO uint32_t SCFGR2;                            /**< Slave Configuration 2, offset: 0x128 */
67165        uint8_t RESERVED_8[20];
67166   __IO uint32_t SAMR;                              /**< Slave Address Match, offset: 0x140 */
67167        uint8_t RESERVED_9[12];
67168   __I  uint32_t SASR;                              /**< Slave Address Status, offset: 0x150 */
67169   __IO uint32_t STAR;                              /**< Slave Transmit ACK, offset: 0x154 */
67170        uint8_t RESERVED_10[8];
67171   __O  uint32_t STDR;                              /**< Slave Transmit Data, offset: 0x160 */
67172        uint8_t RESERVED_11[12];
67173   __I  uint32_t SRDR;                              /**< Slave Receive Data, offset: 0x170 */
67174 } LPI2C_Type;
67175 
67176 /* ----------------------------------------------------------------------------
67177    -- LPI2C Register Masks
67178    ---------------------------------------------------------------------------- */
67179 
67180 /*!
67181  * @addtogroup LPI2C_Register_Masks LPI2C Register Masks
67182  * @{
67183  */
67184 
67185 /*! @name VERID - Version ID */
67186 /*! @{ */
67187 
67188 #define LPI2C_VERID_FEATURE_MASK                 (0xFFFFU)
67189 #define LPI2C_VERID_FEATURE_SHIFT                (0U)
67190 /*! FEATURE - Feature Specification Number
67191  *  0b0000000000000010..Master only, with standard feature set
67192  *  0b0000000000000011..Master and slave, with standard feature set
67193  */
67194 #define LPI2C_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
67195 
67196 #define LPI2C_VERID_MINOR_MASK                   (0xFF0000U)
67197 #define LPI2C_VERID_MINOR_SHIFT                  (16U)
67198 /*! MINOR - Minor Version Number */
67199 #define LPI2C_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
67200 
67201 #define LPI2C_VERID_MAJOR_MASK                   (0xFF000000U)
67202 #define LPI2C_VERID_MAJOR_SHIFT                  (24U)
67203 /*! MAJOR - Major Version Number */
67204 #define LPI2C_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
67205 /*! @} */
67206 
67207 /*! @name PARAM - Parameter */
67208 /*! @{ */
67209 
67210 #define LPI2C_PARAM_MTXFIFO_MASK                 (0xFU)
67211 #define LPI2C_PARAM_MTXFIFO_SHIFT                (0U)
67212 /*! MTXFIFO - Master Transmit FIFO Size */
67213 #define LPI2C_PARAM_MTXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
67214 
67215 #define LPI2C_PARAM_MRXFIFO_MASK                 (0xF00U)
67216 #define LPI2C_PARAM_MRXFIFO_SHIFT                (8U)
67217 /*! MRXFIFO - Master Receive FIFO Size */
67218 #define LPI2C_PARAM_MRXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
67219 /*! @} */
67220 
67221 /*! @name MCR - Master Control */
67222 /*! @{ */
67223 
67224 #define LPI2C_MCR_MEN_MASK                       (0x1U)
67225 #define LPI2C_MCR_MEN_SHIFT                      (0U)
67226 /*! MEN - Master Enable
67227  *  0b0..Master logic is disabled
67228  *  0b1..Master logic is enabled
67229  */
67230 #define LPI2C_MCR_MEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
67231 
67232 #define LPI2C_MCR_RST_MASK                       (0x2U)
67233 #define LPI2C_MCR_RST_SHIFT                      (1U)
67234 /*! RST - Software Reset
67235  *  0b0..Master logic is not reset
67236  *  0b1..Master logic is reset
67237  */
67238 #define LPI2C_MCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
67239 
67240 #define LPI2C_MCR_DOZEN_MASK                     (0x4U)
67241 #define LPI2C_MCR_DOZEN_SHIFT                    (2U)
67242 /*! DOZEN - Doze mode enable
67243  *  0b0..Master is enabled in Doze mode
67244  *  0b1..Master is disabled in Doze mode
67245  */
67246 #define LPI2C_MCR_DOZEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
67247 
67248 #define LPI2C_MCR_DBGEN_MASK                     (0x8U)
67249 #define LPI2C_MCR_DBGEN_SHIFT                    (3U)
67250 /*! DBGEN - Debug Enable
67251  *  0b0..Master is disabled in debug mode
67252  *  0b1..Master is enabled in debug mode
67253  */
67254 #define LPI2C_MCR_DBGEN(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
67255 
67256 #define LPI2C_MCR_RTF_MASK                       (0x100U)
67257 #define LPI2C_MCR_RTF_SHIFT                      (8U)
67258 /*! RTF - Reset Transmit FIFO
67259  *  0b0..No effect
67260  *  0b1..Transmit FIFO is reset
67261  */
67262 #define LPI2C_MCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
67263 
67264 #define LPI2C_MCR_RRF_MASK                       (0x200U)
67265 #define LPI2C_MCR_RRF_SHIFT                      (9U)
67266 /*! RRF - Reset Receive FIFO
67267  *  0b0..No effect
67268  *  0b1..Receive FIFO is reset
67269  */
67270 #define LPI2C_MCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
67271 /*! @} */
67272 
67273 /*! @name MSR - Master Status */
67274 /*! @{ */
67275 
67276 #define LPI2C_MSR_TDF_MASK                       (0x1U)
67277 #define LPI2C_MSR_TDF_SHIFT                      (0U)
67278 /*! TDF - Transmit Data Flag
67279  *  0b0..Transmit data is not requested
67280  *  0b1..Transmit data is requested
67281  */
67282 #define LPI2C_MSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
67283 
67284 #define LPI2C_MSR_RDF_MASK                       (0x2U)
67285 #define LPI2C_MSR_RDF_SHIFT                      (1U)
67286 /*! RDF - Receive Data Flag
67287  *  0b0..Receive Data is not ready
67288  *  0b1..Receive data is ready
67289  */
67290 #define LPI2C_MSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
67291 
67292 #define LPI2C_MSR_EPF_MASK                       (0x100U)
67293 #define LPI2C_MSR_EPF_SHIFT                      (8U)
67294 /*! EPF - End Packet Flag
67295  *  0b0..Master has not generated a STOP or Repeated START condition
67296  *  0b1..Master has generated a STOP or Repeated START condition
67297  */
67298 #define LPI2C_MSR_EPF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
67299 
67300 #define LPI2C_MSR_SDF_MASK                       (0x200U)
67301 #define LPI2C_MSR_SDF_SHIFT                      (9U)
67302 /*! SDF - STOP Detect Flag
67303  *  0b0..Master has not generated a STOP condition
67304  *  0b1..Master has generated a STOP condition
67305  */
67306 #define LPI2C_MSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
67307 
67308 #define LPI2C_MSR_NDF_MASK                       (0x400U)
67309 #define LPI2C_MSR_NDF_SHIFT                      (10U)
67310 /*! NDF - NACK Detect Flag
67311  *  0b0..Unexpected NACK was not detected
67312  *  0b1..Unexpected NACK was detected
67313  */
67314 #define LPI2C_MSR_NDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
67315 
67316 #define LPI2C_MSR_ALF_MASK                       (0x800U)
67317 #define LPI2C_MSR_ALF_SHIFT                      (11U)
67318 /*! ALF - Arbitration Lost Flag
67319  *  0b0..Master has not lost arbitration
67320  *  0b1..Master has lost arbitration
67321  */
67322 #define LPI2C_MSR_ALF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
67323 
67324 #define LPI2C_MSR_FEF_MASK                       (0x1000U)
67325 #define LPI2C_MSR_FEF_SHIFT                      (12U)
67326 /*! FEF - FIFO Error Flag
67327  *  0b0..No error
67328  *  0b1..Master sending or receiving data without a START condition
67329  */
67330 #define LPI2C_MSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
67331 
67332 #define LPI2C_MSR_PLTF_MASK                      (0x2000U)
67333 #define LPI2C_MSR_PLTF_SHIFT                     (13U)
67334 /*! PLTF - Pin Low Timeout Flag
67335  *  0b0..Pin low timeout has not occurred or is disabled
67336  *  0b1..Pin low timeout has occurred
67337  */
67338 #define LPI2C_MSR_PLTF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
67339 
67340 #define LPI2C_MSR_DMF_MASK                       (0x4000U)
67341 #define LPI2C_MSR_DMF_SHIFT                      (14U)
67342 /*! DMF - Data Match Flag
67343  *  0b0..Have not received matching data
67344  *  0b1..Have received matching data
67345  */
67346 #define LPI2C_MSR_DMF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
67347 
67348 #define LPI2C_MSR_MBF_MASK                       (0x1000000U)
67349 #define LPI2C_MSR_MBF_SHIFT                      (24U)
67350 /*! MBF - Master Busy Flag
67351  *  0b0..I2C Master is idle
67352  *  0b1..I2C Master is busy
67353  */
67354 #define LPI2C_MSR_MBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
67355 
67356 #define LPI2C_MSR_BBF_MASK                       (0x2000000U)
67357 #define LPI2C_MSR_BBF_SHIFT                      (25U)
67358 /*! BBF - Bus Busy Flag
67359  *  0b0..I2C Bus is idle
67360  *  0b1..I2C Bus is busy
67361  */
67362 #define LPI2C_MSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
67363 /*! @} */
67364 
67365 /*! @name MIER - Master Interrupt Enable */
67366 /*! @{ */
67367 
67368 #define LPI2C_MIER_TDIE_MASK                     (0x1U)
67369 #define LPI2C_MIER_TDIE_SHIFT                    (0U)
67370 /*! TDIE - Transmit Data Interrupt Enable
67371  *  0b0..Disabled
67372  *  0b1..Enabled
67373  */
67374 #define LPI2C_MIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
67375 
67376 #define LPI2C_MIER_RDIE_MASK                     (0x2U)
67377 #define LPI2C_MIER_RDIE_SHIFT                    (1U)
67378 /*! RDIE - Receive Data Interrupt Enable
67379  *  0b0..Disabled
67380  *  0b1..Enabled
67381  */
67382 #define LPI2C_MIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
67383 
67384 #define LPI2C_MIER_EPIE_MASK                     (0x100U)
67385 #define LPI2C_MIER_EPIE_SHIFT                    (8U)
67386 /*! EPIE - End Packet Interrupt Enable
67387  *  0b0..Disabled
67388  *  0b1..Enabled
67389  */
67390 #define LPI2C_MIER_EPIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
67391 
67392 #define LPI2C_MIER_SDIE_MASK                     (0x200U)
67393 #define LPI2C_MIER_SDIE_SHIFT                    (9U)
67394 /*! SDIE - STOP Detect Interrupt Enable
67395  *  0b0..Disabled
67396  *  0b1..Enabled
67397  */
67398 #define LPI2C_MIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
67399 
67400 #define LPI2C_MIER_NDIE_MASK                     (0x400U)
67401 #define LPI2C_MIER_NDIE_SHIFT                    (10U)
67402 /*! NDIE - NACK Detect Interrupt Enable
67403  *  0b0..Disabled
67404  *  0b1..Enabled
67405  */
67406 #define LPI2C_MIER_NDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
67407 
67408 #define LPI2C_MIER_ALIE_MASK                     (0x800U)
67409 #define LPI2C_MIER_ALIE_SHIFT                    (11U)
67410 /*! ALIE - Arbitration Lost Interrupt Enable
67411  *  0b0..Disabled
67412  *  0b1..Enabled
67413  */
67414 #define LPI2C_MIER_ALIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
67415 
67416 #define LPI2C_MIER_FEIE_MASK                     (0x1000U)
67417 #define LPI2C_MIER_FEIE_SHIFT                    (12U)
67418 /*! FEIE - FIFO Error Interrupt Enable
67419  *  0b0..Enabled
67420  *  0b1..Disabled
67421  */
67422 #define LPI2C_MIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
67423 
67424 #define LPI2C_MIER_PLTIE_MASK                    (0x2000U)
67425 #define LPI2C_MIER_PLTIE_SHIFT                   (13U)
67426 /*! PLTIE - Pin Low Timeout Interrupt Enable
67427  *  0b0..Disabled
67428  *  0b1..Enabled
67429  */
67430 #define LPI2C_MIER_PLTIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
67431 
67432 #define LPI2C_MIER_DMIE_MASK                     (0x4000U)
67433 #define LPI2C_MIER_DMIE_SHIFT                    (14U)
67434 /*! DMIE - Data Match Interrupt Enable
67435  *  0b0..Disabled
67436  *  0b1..Enabled
67437  */
67438 #define LPI2C_MIER_DMIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
67439 /*! @} */
67440 
67441 /*! @name MDER - Master DMA Enable */
67442 /*! @{ */
67443 
67444 #define LPI2C_MDER_TDDE_MASK                     (0x1U)
67445 #define LPI2C_MDER_TDDE_SHIFT                    (0U)
67446 /*! TDDE - Transmit Data DMA Enable
67447  *  0b0..DMA request is disabled
67448  *  0b1..DMA request is enabled
67449  */
67450 #define LPI2C_MDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
67451 
67452 #define LPI2C_MDER_RDDE_MASK                     (0x2U)
67453 #define LPI2C_MDER_RDDE_SHIFT                    (1U)
67454 /*! RDDE - Receive Data DMA Enable
67455  *  0b0..DMA request is disabled
67456  *  0b1..DMA request is enabled
67457  */
67458 #define LPI2C_MDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
67459 /*! @} */
67460 
67461 /*! @name MCFGR0 - Master Configuration 0 */
67462 /*! @{ */
67463 
67464 #define LPI2C_MCFGR0_HREN_MASK                   (0x1U)
67465 #define LPI2C_MCFGR0_HREN_SHIFT                  (0U)
67466 /*! HREN - Host Request Enable
67467  *  0b0..Host request input is disabled
67468  *  0b1..Host request input is enabled
67469  */
67470 #define LPI2C_MCFGR0_HREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
67471 
67472 #define LPI2C_MCFGR0_HRPOL_MASK                  (0x2U)
67473 #define LPI2C_MCFGR0_HRPOL_SHIFT                 (1U)
67474 /*! HRPOL - Host Request Polarity
67475  *  0b0..Active low
67476  *  0b1..Active high
67477  */
67478 #define LPI2C_MCFGR0_HRPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
67479 
67480 #define LPI2C_MCFGR0_HRSEL_MASK                  (0x4U)
67481 #define LPI2C_MCFGR0_HRSEL_SHIFT                 (2U)
67482 /*! HRSEL - Host Request Select
67483  *  0b0..Host request input is pin HREQ
67484  *  0b1..Host request input is input trigger
67485  */
67486 #define LPI2C_MCFGR0_HRSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
67487 
67488 #define LPI2C_MCFGR0_CIRFIFO_MASK                (0x100U)
67489 #define LPI2C_MCFGR0_CIRFIFO_SHIFT               (8U)
67490 /*! CIRFIFO - Circular FIFO Enable
67491  *  0b0..Circular FIFO is disabled
67492  *  0b1..Circular FIFO is enabled
67493  */
67494 #define LPI2C_MCFGR0_CIRFIFO(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
67495 
67496 #define LPI2C_MCFGR0_RDMO_MASK                   (0x200U)
67497 #define LPI2C_MCFGR0_RDMO_SHIFT                  (9U)
67498 /*! RDMO - Receive Data Match Only
67499  *  0b0..Received data is stored in the receive FIFO
67500  *  0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set
67501  */
67502 #define LPI2C_MCFGR0_RDMO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
67503 /*! @} */
67504 
67505 /*! @name MCFGR1 - Master Configuration 1 */
67506 /*! @{ */
67507 
67508 #define LPI2C_MCFGR1_PRESCALE_MASK               (0x7U)
67509 #define LPI2C_MCFGR1_PRESCALE_SHIFT              (0U)
67510 /*! PRESCALE - Prescaler
67511  *  0b000..Divide by 1
67512  *  0b001..Divide by 2
67513  *  0b010..Divide by 4
67514  *  0b011..Divide by 8
67515  *  0b100..Divide by 16
67516  *  0b101..Divide by 32
67517  *  0b110..Divide by 64
67518  *  0b111..Divide by 128
67519  */
67520 #define LPI2C_MCFGR1_PRESCALE(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
67521 
67522 #define LPI2C_MCFGR1_AUTOSTOP_MASK               (0x100U)
67523 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT              (8U)
67524 /*! AUTOSTOP - Automatic STOP Generation
67525  *  0b0..No effect
67526  *  0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy
67527  */
67528 #define LPI2C_MCFGR1_AUTOSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
67529 
67530 #define LPI2C_MCFGR1_IGNACK_MASK                 (0x200U)
67531 #define LPI2C_MCFGR1_IGNACK_SHIFT                (9U)
67532 /*! IGNACK - IGNACK
67533  *  0b0..LPI2C Master receives ACK and NACK normally
67534  *  0b1..LPI2C Master treats a received NACK as if it (NACK) was an ACK
67535  */
67536 #define LPI2C_MCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
67537 
67538 #define LPI2C_MCFGR1_TIMECFG_MASK                (0x400U)
67539 #define LPI2C_MCFGR1_TIMECFG_SHIFT               (10U)
67540 /*! TIMECFG - Timeout Configuration
67541  *  0b0..MSR[PLTF] sets if SCL is low for longer than the configured timeout
67542  *  0b1..MSR[PLTF] sets if either SCL or SDA is low for longer than the configured timeout
67543  */
67544 #define LPI2C_MCFGR1_TIMECFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
67545 
67546 #define LPI2C_MCFGR1_MATCFG_MASK                 (0x70000U)
67547 #define LPI2C_MCFGR1_MATCFG_SHIFT                (16U)
67548 /*! MATCFG - Match Configuration
67549  *  0b000..Match is disabled
67550  *  0b001..Reserved
67551  *  0b010..Match is enabled (1st data word equals MDMR[MATCH0] OR MDMR[MATCH1])
67552  *  0b011..Match is enabled (any data word equals MDMR[MATCH0] OR MDMR[MATCH1])
67553  *  0b100..Match is enabled (1st data word equals MDMR[MATCH0] AND 2nd data word equals MDMR[MATCH1)
67554  *  0b101..Match is enabled (any data word equals MDMR[MATCH0] AND next data word equals MDMR[MATCH1)
67555  *  0b110..Match is enabled (1st data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1])
67556  *  0b111..Match is enabled (any data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1])
67557  */
67558 #define LPI2C_MCFGR1_MATCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
67559 
67560 #define LPI2C_MCFGR1_PINCFG_MASK                 (0x7000000U)
67561 #define LPI2C_MCFGR1_PINCFG_SHIFT                (24U)
67562 /*! PINCFG - Pin Configuration
67563  *  0b000..2-pin open drain mode
67564  *  0b001..2-pin output only mode (ultra-fast mode)
67565  *  0b010..2-pin push-pull mode
67566  *  0b011..4-pin push-pull mode
67567  *  0b100..2-pin open drain mode with separate LPI2C slave
67568  *  0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave
67569  *  0b110..2-pin push-pull mode with separate LPI2C slave
67570  *  0b111..4-pin push-pull mode (inverted outputs)
67571  */
67572 #define LPI2C_MCFGR1_PINCFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
67573 /*! @} */
67574 
67575 /*! @name MCFGR2 - Master Configuration 2 */
67576 /*! @{ */
67577 
67578 #define LPI2C_MCFGR2_BUSIDLE_MASK                (0xFFFU)
67579 #define LPI2C_MCFGR2_BUSIDLE_SHIFT               (0U)
67580 /*! BUSIDLE - Bus Idle Timeout */
67581 #define LPI2C_MCFGR2_BUSIDLE(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
67582 
67583 #define LPI2C_MCFGR2_FILTSCL_MASK                (0xF0000U)
67584 #define LPI2C_MCFGR2_FILTSCL_SHIFT               (16U)
67585 /*! FILTSCL - Glitch Filter SCL */
67586 #define LPI2C_MCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
67587 
67588 #define LPI2C_MCFGR2_FILTSDA_MASK                (0xF000000U)
67589 #define LPI2C_MCFGR2_FILTSDA_SHIFT               (24U)
67590 /*! FILTSDA - Glitch Filter SDA */
67591 #define LPI2C_MCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
67592 /*! @} */
67593 
67594 /*! @name MCFGR3 - Master Configuration 3 */
67595 /*! @{ */
67596 
67597 #define LPI2C_MCFGR3_PINLOW_MASK                 (0xFFF00U)
67598 #define LPI2C_MCFGR3_PINLOW_SHIFT                (8U)
67599 /*! PINLOW - Pin Low Timeout */
67600 #define LPI2C_MCFGR3_PINLOW(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
67601 /*! @} */
67602 
67603 /*! @name MDMR - Master Data Match */
67604 /*! @{ */
67605 
67606 #define LPI2C_MDMR_MATCH0_MASK                   (0xFFU)
67607 #define LPI2C_MDMR_MATCH0_SHIFT                  (0U)
67608 /*! MATCH0 - Match 0 Value */
67609 #define LPI2C_MDMR_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
67610 
67611 #define LPI2C_MDMR_MATCH1_MASK                   (0xFF0000U)
67612 #define LPI2C_MDMR_MATCH1_SHIFT                  (16U)
67613 /*! MATCH1 - Match 1 Value */
67614 #define LPI2C_MDMR_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
67615 /*! @} */
67616 
67617 /*! @name MCCR0 - Master Clock Configuration 0 */
67618 /*! @{ */
67619 
67620 #define LPI2C_MCCR0_CLKLO_MASK                   (0x3FU)
67621 #define LPI2C_MCCR0_CLKLO_SHIFT                  (0U)
67622 /*! CLKLO - Clock Low Period */
67623 #define LPI2C_MCCR0_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
67624 
67625 #define LPI2C_MCCR0_CLKHI_MASK                   (0x3F00U)
67626 #define LPI2C_MCCR0_CLKHI_SHIFT                  (8U)
67627 /*! CLKHI - Clock High Period */
67628 #define LPI2C_MCCR0_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
67629 
67630 #define LPI2C_MCCR0_SETHOLD_MASK                 (0x3F0000U)
67631 #define LPI2C_MCCR0_SETHOLD_SHIFT                (16U)
67632 /*! SETHOLD - Setup Hold Delay */
67633 #define LPI2C_MCCR0_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
67634 
67635 #define LPI2C_MCCR0_DATAVD_MASK                  (0x3F000000U)
67636 #define LPI2C_MCCR0_DATAVD_SHIFT                 (24U)
67637 /*! DATAVD - Data Valid Delay */
67638 #define LPI2C_MCCR0_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
67639 /*! @} */
67640 
67641 /*! @name MCCR1 - Master Clock Configuration 1 */
67642 /*! @{ */
67643 
67644 #define LPI2C_MCCR1_CLKLO_MASK                   (0x3FU)
67645 #define LPI2C_MCCR1_CLKLO_SHIFT                  (0U)
67646 /*! CLKLO - Clock Low Period */
67647 #define LPI2C_MCCR1_CLKLO(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
67648 
67649 #define LPI2C_MCCR1_CLKHI_MASK                   (0x3F00U)
67650 #define LPI2C_MCCR1_CLKHI_SHIFT                  (8U)
67651 /*! CLKHI - Clock High Period */
67652 #define LPI2C_MCCR1_CLKHI(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
67653 
67654 #define LPI2C_MCCR1_SETHOLD_MASK                 (0x3F0000U)
67655 #define LPI2C_MCCR1_SETHOLD_SHIFT                (16U)
67656 /*! SETHOLD - Setup Hold Delay */
67657 #define LPI2C_MCCR1_SETHOLD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
67658 
67659 #define LPI2C_MCCR1_DATAVD_MASK                  (0x3F000000U)
67660 #define LPI2C_MCCR1_DATAVD_SHIFT                 (24U)
67661 /*! DATAVD - Data Valid Delay */
67662 #define LPI2C_MCCR1_DATAVD(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
67663 /*! @} */
67664 
67665 /*! @name MFCR - Master FIFO Control */
67666 /*! @{ */
67667 
67668 #define LPI2C_MFCR_TXWATER_MASK                  (0x3U)
67669 #define LPI2C_MFCR_TXWATER_SHIFT                 (0U)
67670 /*! TXWATER - Transmit FIFO Watermark */
67671 #define LPI2C_MFCR_TXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
67672 
67673 #define LPI2C_MFCR_RXWATER_MASK                  (0x30000U)
67674 #define LPI2C_MFCR_RXWATER_SHIFT                 (16U)
67675 /*! RXWATER - Receive FIFO Watermark */
67676 #define LPI2C_MFCR_RXWATER(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
67677 /*! @} */
67678 
67679 /*! @name MFSR - Master FIFO Status */
67680 /*! @{ */
67681 
67682 #define LPI2C_MFSR_TXCOUNT_MASK                  (0x7U)
67683 #define LPI2C_MFSR_TXCOUNT_SHIFT                 (0U)
67684 /*! TXCOUNT - Transmit FIFO Count */
67685 #define LPI2C_MFSR_TXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
67686 
67687 #define LPI2C_MFSR_RXCOUNT_MASK                  (0x70000U)
67688 #define LPI2C_MFSR_RXCOUNT_SHIFT                 (16U)
67689 /*! RXCOUNT - Receive FIFO Count */
67690 #define LPI2C_MFSR_RXCOUNT(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
67691 /*! @} */
67692 
67693 /*! @name MTDR - Master Transmit Data */
67694 /*! @{ */
67695 
67696 #define LPI2C_MTDR_DATA_MASK                     (0xFFU)
67697 #define LPI2C_MTDR_DATA_SHIFT                    (0U)
67698 /*! DATA - Transmit Data */
67699 #define LPI2C_MTDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
67700 
67701 #define LPI2C_MTDR_CMD_MASK                      (0x700U)
67702 #define LPI2C_MTDR_CMD_SHIFT                     (8U)
67703 /*! CMD - Command Data
67704  *  0b000..Transmit DATA[7:0]
67705  *  0b001..Receive (DATA[7:0] + 1) bytes
67706  *  0b010..Generate STOP condition
67707  *  0b011..Receive and discard (DATA[7:0] + 1) bytes
67708  *  0b100..Generate (repeated) START and transmit address in DATA[7:0]
67709  *  0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
67710  *  0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
67711  *  0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
67712  */
67713 #define LPI2C_MTDR_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
67714 /*! @} */
67715 
67716 /*! @name MRDR - Master Receive Data */
67717 /*! @{ */
67718 
67719 #define LPI2C_MRDR_DATA_MASK                     (0xFFU)
67720 #define LPI2C_MRDR_DATA_SHIFT                    (0U)
67721 /*! DATA - Receive Data */
67722 #define LPI2C_MRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
67723 
67724 #define LPI2C_MRDR_RXEMPTY_MASK                  (0x4000U)
67725 #define LPI2C_MRDR_RXEMPTY_SHIFT                 (14U)
67726 /*! RXEMPTY - RX Empty
67727  *  0b0..Receive FIFO is not empty
67728  *  0b1..Receive FIFO is empty
67729  */
67730 #define LPI2C_MRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
67731 /*! @} */
67732 
67733 /*! @name SCR - Slave Control */
67734 /*! @{ */
67735 
67736 #define LPI2C_SCR_SEN_MASK                       (0x1U)
67737 #define LPI2C_SCR_SEN_SHIFT                      (0U)
67738 /*! SEN - Slave Enable
67739  *  0b0..I2C Slave mode is disabled
67740  *  0b1..I2C Slave mode is enabled
67741  */
67742 #define LPI2C_SCR_SEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
67743 
67744 #define LPI2C_SCR_RST_MASK                       (0x2U)
67745 #define LPI2C_SCR_RST_SHIFT                      (1U)
67746 /*! RST - Software Reset
67747  *  0b0..Slave mode logic is not reset
67748  *  0b1..Slave mode logic is reset
67749  */
67750 #define LPI2C_SCR_RST(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
67751 
67752 #define LPI2C_SCR_FILTEN_MASK                    (0x10U)
67753 #define LPI2C_SCR_FILTEN_SHIFT                   (4U)
67754 /*! FILTEN - Filter Enable
67755  *  0b0..Disable digital filter and output delay counter for slave mode
67756  *  0b1..Enable digital filter and output delay counter for slave mode
67757  */
67758 #define LPI2C_SCR_FILTEN(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
67759 
67760 #define LPI2C_SCR_FILTDZ_MASK                    (0x20U)
67761 #define LPI2C_SCR_FILTDZ_SHIFT                   (5U)
67762 /*! FILTDZ - Filter Doze Enable
67763  *  0b0..Filter remains enabled in Doze mode
67764  *  0b1..Filter is disabled in Doze mode
67765  */
67766 #define LPI2C_SCR_FILTDZ(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
67767 
67768 #define LPI2C_SCR_RTF_MASK                       (0x100U)
67769 #define LPI2C_SCR_RTF_SHIFT                      (8U)
67770 /*! RTF - Reset Transmit FIFO
67771  *  0b0..No effect
67772  *  0b1..Transmit Data Register is now empty
67773  */
67774 #define LPI2C_SCR_RTF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
67775 
67776 #define LPI2C_SCR_RRF_MASK                       (0x200U)
67777 #define LPI2C_SCR_RRF_SHIFT                      (9U)
67778 /*! RRF - Reset Receive FIFO
67779  *  0b0..No effect
67780  *  0b1..Receive Data Register is now empty
67781  */
67782 #define LPI2C_SCR_RRF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
67783 /*! @} */
67784 
67785 /*! @name SSR - Slave Status */
67786 /*! @{ */
67787 
67788 #define LPI2C_SSR_TDF_MASK                       (0x1U)
67789 #define LPI2C_SSR_TDF_SHIFT                      (0U)
67790 /*! TDF - Transmit Data Flag
67791  *  0b0..Transmit data not requested
67792  *  0b1..Transmit data is requested
67793  */
67794 #define LPI2C_SSR_TDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
67795 
67796 #define LPI2C_SSR_RDF_MASK                       (0x2U)
67797 #define LPI2C_SSR_RDF_SHIFT                      (1U)
67798 /*! RDF - Receive Data Flag
67799  *  0b0..Receive data is not ready
67800  *  0b1..Receive data is ready
67801  */
67802 #define LPI2C_SSR_RDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
67803 
67804 #define LPI2C_SSR_AVF_MASK                       (0x4U)
67805 #define LPI2C_SSR_AVF_SHIFT                      (2U)
67806 /*! AVF - Address Valid Flag
67807  *  0b0..Address Status Register is not valid
67808  *  0b1..Address Status Register is valid
67809  */
67810 #define LPI2C_SSR_AVF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
67811 
67812 #define LPI2C_SSR_TAF_MASK                       (0x8U)
67813 #define LPI2C_SSR_TAF_SHIFT                      (3U)
67814 /*! TAF - Transmit ACK Flag
67815  *  0b0..Transmit ACK/NACK is not required
67816  *  0b1..Transmit ACK/NACK is required
67817  */
67818 #define LPI2C_SSR_TAF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
67819 
67820 #define LPI2C_SSR_RSF_MASK                       (0x100U)
67821 #define LPI2C_SSR_RSF_SHIFT                      (8U)
67822 /*! RSF - Repeated Start Flag
67823  *  0b0..Slave has not detected a Repeated START condition
67824  *  0b1..Slave has detected a Repeated START condition
67825  */
67826 #define LPI2C_SSR_RSF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
67827 
67828 #define LPI2C_SSR_SDF_MASK                       (0x200U)
67829 #define LPI2C_SSR_SDF_SHIFT                      (9U)
67830 /*! SDF - STOP Detect Flag
67831  *  0b0..Slave has not detected a STOP condition
67832  *  0b1..Slave has detected a STOP condition
67833  */
67834 #define LPI2C_SSR_SDF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
67835 
67836 #define LPI2C_SSR_BEF_MASK                       (0x400U)
67837 #define LPI2C_SSR_BEF_SHIFT                      (10U)
67838 /*! BEF - Bit Error Flag
67839  *  0b0..Slave has not detected a bit error
67840  *  0b1..Slave has detected a bit error
67841  */
67842 #define LPI2C_SSR_BEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
67843 
67844 #define LPI2C_SSR_FEF_MASK                       (0x800U)
67845 #define LPI2C_SSR_FEF_SHIFT                      (11U)
67846 /*! FEF - FIFO Error Flag
67847  *  0b0..FIFO underflow or overflow was not detected
67848  *  0b1..FIFO underflow or overflow was detected
67849  */
67850 #define LPI2C_SSR_FEF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
67851 
67852 #define LPI2C_SSR_AM0F_MASK                      (0x1000U)
67853 #define LPI2C_SSR_AM0F_SHIFT                     (12U)
67854 /*! AM0F - Address Match 0 Flag
67855  *  0b0..Have not received an ADDR0 matching address
67856  *  0b1..Have received an ADDR0 matching address
67857  */
67858 #define LPI2C_SSR_AM0F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
67859 
67860 #define LPI2C_SSR_AM1F_MASK                      (0x2000U)
67861 #define LPI2C_SSR_AM1F_SHIFT                     (13U)
67862 /*! AM1F - Address Match 1 Flag
67863  *  0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address
67864  *  0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address
67865  */
67866 #define LPI2C_SSR_AM1F(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
67867 
67868 #define LPI2C_SSR_GCF_MASK                       (0x4000U)
67869 #define LPI2C_SSR_GCF_SHIFT                      (14U)
67870 /*! GCF - General Call Flag
67871  *  0b0..Slave has not detected the General Call Address or the General Call Address is disabled
67872  *  0b1..Slave has detected the General Call Address
67873  */
67874 #define LPI2C_SSR_GCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
67875 
67876 #define LPI2C_SSR_SARF_MASK                      (0x8000U)
67877 #define LPI2C_SSR_SARF_SHIFT                     (15U)
67878 /*! SARF - SMBus Alert Response Flag
67879  *  0b0..SMBus Alert Response is disabled or not detected
67880  *  0b1..SMBus Alert Response is enabled and detected
67881  */
67882 #define LPI2C_SSR_SARF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
67883 
67884 #define LPI2C_SSR_SBF_MASK                       (0x1000000U)
67885 #define LPI2C_SSR_SBF_SHIFT                      (24U)
67886 /*! SBF - Slave Busy Flag
67887  *  0b0..I2C Slave is idle
67888  *  0b1..I2C Slave is busy
67889  */
67890 #define LPI2C_SSR_SBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
67891 
67892 #define LPI2C_SSR_BBF_MASK                       (0x2000000U)
67893 #define LPI2C_SSR_BBF_SHIFT                      (25U)
67894 /*! BBF - Bus Busy Flag
67895  *  0b0..I2C Bus is idle
67896  *  0b1..I2C Bus is busy
67897  */
67898 #define LPI2C_SSR_BBF(x)                         (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
67899 /*! @} */
67900 
67901 /*! @name SIER - Slave Interrupt Enable */
67902 /*! @{ */
67903 
67904 #define LPI2C_SIER_TDIE_MASK                     (0x1U)
67905 #define LPI2C_SIER_TDIE_SHIFT                    (0U)
67906 /*! TDIE - Transmit Data Interrupt Enable
67907  *  0b0..Disabled
67908  *  0b1..Enabled
67909  */
67910 #define LPI2C_SIER_TDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
67911 
67912 #define LPI2C_SIER_RDIE_MASK                     (0x2U)
67913 #define LPI2C_SIER_RDIE_SHIFT                    (1U)
67914 /*! RDIE - Receive Data Interrupt Enable
67915  *  0b0..Disabled
67916  *  0b1..Enabled
67917  */
67918 #define LPI2C_SIER_RDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
67919 
67920 #define LPI2C_SIER_AVIE_MASK                     (0x4U)
67921 #define LPI2C_SIER_AVIE_SHIFT                    (2U)
67922 /*! AVIE - Address Valid Interrupt Enable
67923  *  0b0..Disabled
67924  *  0b1..Enabled
67925  */
67926 #define LPI2C_SIER_AVIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
67927 
67928 #define LPI2C_SIER_TAIE_MASK                     (0x8U)
67929 #define LPI2C_SIER_TAIE_SHIFT                    (3U)
67930 /*! TAIE - Transmit ACK Interrupt Enable
67931  *  0b0..Disabled
67932  *  0b1..Enabled
67933  */
67934 #define LPI2C_SIER_TAIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
67935 
67936 #define LPI2C_SIER_RSIE_MASK                     (0x100U)
67937 #define LPI2C_SIER_RSIE_SHIFT                    (8U)
67938 /*! RSIE - Repeated Start Interrupt Enable
67939  *  0b0..Disabled
67940  *  0b1..Enabled
67941  */
67942 #define LPI2C_SIER_RSIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
67943 
67944 #define LPI2C_SIER_SDIE_MASK                     (0x200U)
67945 #define LPI2C_SIER_SDIE_SHIFT                    (9U)
67946 /*! SDIE - STOP Detect Interrupt Enable
67947  *  0b0..Disabled
67948  *  0b1..Enabled
67949  */
67950 #define LPI2C_SIER_SDIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
67951 
67952 #define LPI2C_SIER_BEIE_MASK                     (0x400U)
67953 #define LPI2C_SIER_BEIE_SHIFT                    (10U)
67954 /*! BEIE - Bit Error Interrupt Enable
67955  *  0b0..Disabled
67956  *  0b1..Enabled
67957  */
67958 #define LPI2C_SIER_BEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
67959 
67960 #define LPI2C_SIER_FEIE_MASK                     (0x800U)
67961 #define LPI2C_SIER_FEIE_SHIFT                    (11U)
67962 /*! FEIE - FIFO Error Interrupt Enable
67963  *  0b0..Disabled
67964  *  0b1..Enabled
67965  */
67966 #define LPI2C_SIER_FEIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
67967 
67968 #define LPI2C_SIER_AM0IE_MASK                    (0x1000U)
67969 #define LPI2C_SIER_AM0IE_SHIFT                   (12U)
67970 /*! AM0IE - Address Match 0 Interrupt Enable
67971  *  0b0..Disabled
67972  *  0b1..Enabled
67973  */
67974 #define LPI2C_SIER_AM0IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
67975 
67976 #define LPI2C_SIER_AM1IE_MASK                    (0x2000U)
67977 #define LPI2C_SIER_AM1IE_SHIFT                   (13U)
67978 /*! AM1IE - Address Match 1 Interrupt Enable
67979  *  0b0..Disabled
67980  *  0b1..Enabled
67981  */
67982 #define LPI2C_SIER_AM1IE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)
67983 
67984 #define LPI2C_SIER_GCIE_MASK                     (0x4000U)
67985 #define LPI2C_SIER_GCIE_SHIFT                    (14U)
67986 /*! GCIE - General Call Interrupt Enable
67987  *  0b0..Disabled
67988  *  0b1..Enabled
67989  */
67990 #define LPI2C_SIER_GCIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
67991 
67992 #define LPI2C_SIER_SARIE_MASK                    (0x8000U)
67993 #define LPI2C_SIER_SARIE_SHIFT                   (15U)
67994 /*! SARIE - SMBus Alert Response Interrupt Enable
67995  *  0b0..Disabled
67996  *  0b1..Enabled
67997  */
67998 #define LPI2C_SIER_SARIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
67999 /*! @} */
68000 
68001 /*! @name SDER - Slave DMA Enable */
68002 /*! @{ */
68003 
68004 #define LPI2C_SDER_TDDE_MASK                     (0x1U)
68005 #define LPI2C_SDER_TDDE_SHIFT                    (0U)
68006 /*! TDDE - Transmit Data DMA Enable
68007  *  0b0..DMA request is disabled
68008  *  0b1..DMA request is enabled
68009  */
68010 #define LPI2C_SDER_TDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
68011 
68012 #define LPI2C_SDER_RDDE_MASK                     (0x2U)
68013 #define LPI2C_SDER_RDDE_SHIFT                    (1U)
68014 /*! RDDE - Receive Data DMA Enable
68015  *  0b0..DMA request is disabled
68016  *  0b1..DMA request is enabled
68017  */
68018 #define LPI2C_SDER_RDDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
68019 
68020 #define LPI2C_SDER_AVDE_MASK                     (0x4U)
68021 #define LPI2C_SDER_AVDE_SHIFT                    (2U)
68022 /*! AVDE - Address Valid DMA Enable
68023  *  0b0..DMA request is disabled
68024  *  0b1..DMA request is enabled
68025  */
68026 #define LPI2C_SDER_AVDE(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
68027 /*! @} */
68028 
68029 /*! @name SCFGR1 - Slave Configuration 1 */
68030 /*! @{ */
68031 
68032 #define LPI2C_SCFGR1_ADRSTALL_MASK               (0x1U)
68033 #define LPI2C_SCFGR1_ADRSTALL_SHIFT              (0U)
68034 /*! ADRSTALL - Address SCL Stall
68035  *  0b0..Clock stretching is disabled
68036  *  0b1..Clock stretching is enabled
68037  */
68038 #define LPI2C_SCFGR1_ADRSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
68039 
68040 #define LPI2C_SCFGR1_RXSTALL_MASK                (0x2U)
68041 #define LPI2C_SCFGR1_RXSTALL_SHIFT               (1U)
68042 /*! RXSTALL - RX SCL Stall
68043  *  0b0..Clock stretching is disabled
68044  *  0b1..Clock stretching is enabled
68045  */
68046 #define LPI2C_SCFGR1_RXSTALL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
68047 
68048 #define LPI2C_SCFGR1_TXDSTALL_MASK               (0x4U)
68049 #define LPI2C_SCFGR1_TXDSTALL_SHIFT              (2U)
68050 /*! TXDSTALL - TX Data SCL Stall
68051  *  0b0..Clock stretching is disabled
68052  *  0b1..Clock stretching is enabled
68053  */
68054 #define LPI2C_SCFGR1_TXDSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
68055 
68056 #define LPI2C_SCFGR1_ACKSTALL_MASK               (0x8U)
68057 #define LPI2C_SCFGR1_ACKSTALL_SHIFT              (3U)
68058 /*! ACKSTALL - ACK SCL Stall
68059  *  0b0..Clock stretching is disabled
68060  *  0b1..Clock stretching is enabled
68061  */
68062 #define LPI2C_SCFGR1_ACKSTALL(x)                 (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
68063 
68064 #define LPI2C_SCFGR1_GCEN_MASK                   (0x100U)
68065 #define LPI2C_SCFGR1_GCEN_SHIFT                  (8U)
68066 /*! GCEN - General Call Enable
68067  *  0b0..General Call address is disabled
68068  *  0b1..General Call address is enabled
68069  */
68070 #define LPI2C_SCFGR1_GCEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
68071 
68072 #define LPI2C_SCFGR1_SAEN_MASK                   (0x200U)
68073 #define LPI2C_SCFGR1_SAEN_SHIFT                  (9U)
68074 /*! SAEN - SMBus Alert Enable
68075  *  0b0..Disables match on SMBus Alert
68076  *  0b1..Enables match on SMBus Alert
68077  */
68078 #define LPI2C_SCFGR1_SAEN(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
68079 
68080 #define LPI2C_SCFGR1_TXCFG_MASK                  (0x400U)
68081 #define LPI2C_SCFGR1_TXCFG_SHIFT                 (10U)
68082 /*! TXCFG - Transmit Flag Configuration
68083  *  0b0..Transmit Data Flag only asserts during a slave-transmit transfer when the Transmit Data register is empty
68084  *  0b1..Transmit Data Flag asserts whenever the Transmit Data register is empty
68085  */
68086 #define LPI2C_SCFGR1_TXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
68087 
68088 #define LPI2C_SCFGR1_RXCFG_MASK                  (0x800U)
68089 #define LPI2C_SCFGR1_RXCFG_SHIFT                 (11U)
68090 /*! RXCFG - Receive Data Configuration
68091  *  0b0..Reading the Receive Data register returns received data and clears the Receive Data flag (MSR[RDF]).
68092  *  0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, returns the Address
68093  *       Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag
68094  *       is clear, returns received data and clears the Receive Data flag (MSR[RDF]).
68095  */
68096 #define LPI2C_SCFGR1_RXCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
68097 
68098 #define LPI2C_SCFGR1_IGNACK_MASK                 (0x1000U)
68099 #define LPI2C_SCFGR1_IGNACK_SHIFT                (12U)
68100 /*! IGNACK - Ignore NACK
68101  *  0b0..Slave ends transfer when NACK is detected
68102  *  0b1..Slave does not end transfer when NACK detected
68103  */
68104 #define LPI2C_SCFGR1_IGNACK(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
68105 
68106 #define LPI2C_SCFGR1_HSMEN_MASK                  (0x2000U)
68107 #define LPI2C_SCFGR1_HSMEN_SHIFT                 (13U)
68108 /*! HSMEN - High Speed Mode Enable
68109  *  0b0..Disables detection of HS-mode master code
68110  *  0b1..Enables detection of HS-mode master code
68111  */
68112 #define LPI2C_SCFGR1_HSMEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
68113 
68114 #define LPI2C_SCFGR1_ADDRCFG_MASK                (0x70000U)
68115 #define LPI2C_SCFGR1_ADDRCFG_SHIFT               (16U)
68116 /*! ADDRCFG - Address Configuration
68117  *  0b000..Address match 0 (7-bit)
68118  *  0b001..Address match 0 (10-bit)
68119  *  0b010..Address match 0 (7-bit) or Address match 1 (7-bit)
68120  *  0b011..Address match 0 (10-bit) or Address match 1 (10-bit)
68121  *  0b100..Address match 0 (7-bit) or Address match 1 (10-bit)
68122  *  0b101..Address match 0 (10-bit) or Address match 1 (7-bit)
68123  *  0b110..From Address match 0 (7-bit) to Address match 1 (7-bit)
68124  *  0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)
68125  */
68126 #define LPI2C_SCFGR1_ADDRCFG(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
68127 /*! @} */
68128 
68129 /*! @name SCFGR2 - Slave Configuration 2 */
68130 /*! @{ */
68131 
68132 #define LPI2C_SCFGR2_CLKHOLD_MASK                (0xFU)
68133 #define LPI2C_SCFGR2_CLKHOLD_SHIFT               (0U)
68134 /*! CLKHOLD - Clock Hold Time */
68135 #define LPI2C_SCFGR2_CLKHOLD(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
68136 
68137 #define LPI2C_SCFGR2_DATAVD_MASK                 (0x3F00U)
68138 #define LPI2C_SCFGR2_DATAVD_SHIFT                (8U)
68139 /*! DATAVD - Data Valid Delay */
68140 #define LPI2C_SCFGR2_DATAVD(x)                   (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
68141 
68142 #define LPI2C_SCFGR2_FILTSCL_MASK                (0xF0000U)
68143 #define LPI2C_SCFGR2_FILTSCL_SHIFT               (16U)
68144 /*! FILTSCL - Glitch Filter SCL */
68145 #define LPI2C_SCFGR2_FILTSCL(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
68146 
68147 #define LPI2C_SCFGR2_FILTSDA_MASK                (0xF000000U)
68148 #define LPI2C_SCFGR2_FILTSDA_SHIFT               (24U)
68149 /*! FILTSDA - Glitch Filter SDA */
68150 #define LPI2C_SCFGR2_FILTSDA(x)                  (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
68151 /*! @} */
68152 
68153 /*! @name SAMR - Slave Address Match */
68154 /*! @{ */
68155 
68156 #define LPI2C_SAMR_ADDR0_MASK                    (0x7FEU)
68157 #define LPI2C_SAMR_ADDR0_SHIFT                   (1U)
68158 /*! ADDR0 - Address 0 Value */
68159 #define LPI2C_SAMR_ADDR0(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
68160 
68161 #define LPI2C_SAMR_ADDR1_MASK                    (0x7FE0000U)
68162 #define LPI2C_SAMR_ADDR1_SHIFT                   (17U)
68163 /*! ADDR1 - Address 1 Value */
68164 #define LPI2C_SAMR_ADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
68165 /*! @} */
68166 
68167 /*! @name SASR - Slave Address Status */
68168 /*! @{ */
68169 
68170 #define LPI2C_SASR_RADDR_MASK                    (0x7FFU)
68171 #define LPI2C_SASR_RADDR_SHIFT                   (0U)
68172 /*! RADDR - Received Address */
68173 #define LPI2C_SASR_RADDR(x)                      (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
68174 
68175 #define LPI2C_SASR_ANV_MASK                      (0x4000U)
68176 #define LPI2C_SASR_ANV_SHIFT                     (14U)
68177 /*! ANV - Address Not Valid
68178  *  0b0..Received Address (RADDR) is valid
68179  *  0b1..Received Address (RADDR) is not valid
68180  */
68181 #define LPI2C_SASR_ANV(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
68182 /*! @} */
68183 
68184 /*! @name STAR - Slave Transmit ACK */
68185 /*! @{ */
68186 
68187 #define LPI2C_STAR_TXNACK_MASK                   (0x1U)
68188 #define LPI2C_STAR_TXNACK_SHIFT                  (0U)
68189 /*! TXNACK - Transmit NACK
68190  *  0b0..Write a Transmit ACK for each received word
68191  *  0b1..Write a Transmit NACK for each received word
68192  */
68193 #define LPI2C_STAR_TXNACK(x)                     (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
68194 /*! @} */
68195 
68196 /*! @name STDR - Slave Transmit Data */
68197 /*! @{ */
68198 
68199 #define LPI2C_STDR_DATA_MASK                     (0xFFU)
68200 #define LPI2C_STDR_DATA_SHIFT                    (0U)
68201 /*! DATA - Transmit Data */
68202 #define LPI2C_STDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
68203 /*! @} */
68204 
68205 /*! @name SRDR - Slave Receive Data */
68206 /*! @{ */
68207 
68208 #define LPI2C_SRDR_DATA_MASK                     (0xFFU)
68209 #define LPI2C_SRDR_DATA_SHIFT                    (0U)
68210 /*! DATA - Receive Data */
68211 #define LPI2C_SRDR_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
68212 
68213 #define LPI2C_SRDR_RXEMPTY_MASK                  (0x4000U)
68214 #define LPI2C_SRDR_RXEMPTY_SHIFT                 (14U)
68215 /*! RXEMPTY - RX Empty
68216  *  0b0..The Receive Data Register is not empty
68217  *  0b1..The Receive Data Register is empty
68218  */
68219 #define LPI2C_SRDR_RXEMPTY(x)                    (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
68220 
68221 #define LPI2C_SRDR_SOF_MASK                      (0x8000U)
68222 #define LPI2C_SRDR_SOF_SHIFT                     (15U)
68223 /*! SOF - Start Of Frame
68224  *  0b0..Indicates this is not the first data word since a (repeated) START or STOP condition
68225  *  0b1..Indicates this is the first data word since a (repeated) START or STOP condition
68226  */
68227 #define LPI2C_SRDR_SOF(x)                        (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
68228 /*! @} */
68229 
68230 
68231 /*!
68232  * @}
68233  */ /* end of group LPI2C_Register_Masks */
68234 
68235 
68236 /* LPI2C - Peripheral instance base addresses */
68237 /** Peripheral LPI2C1 base address */
68238 #define LPI2C1_BASE                              (0x40104000u)
68239 /** Peripheral LPI2C1 base pointer */
68240 #define LPI2C1                                   ((LPI2C_Type *)LPI2C1_BASE)
68241 /** Peripheral LPI2C2 base address */
68242 #define LPI2C2_BASE                              (0x40108000u)
68243 /** Peripheral LPI2C2 base pointer */
68244 #define LPI2C2                                   ((LPI2C_Type *)LPI2C2_BASE)
68245 /** Peripheral LPI2C3 base address */
68246 #define LPI2C3_BASE                              (0x4010C000u)
68247 /** Peripheral LPI2C3 base pointer */
68248 #define LPI2C3                                   ((LPI2C_Type *)LPI2C3_BASE)
68249 /** Peripheral LPI2C4 base address */
68250 #define LPI2C4_BASE                              (0x40110000u)
68251 /** Peripheral LPI2C4 base pointer */
68252 #define LPI2C4                                   ((LPI2C_Type *)LPI2C4_BASE)
68253 /** Peripheral LPI2C5 base address */
68254 #define LPI2C5_BASE                              (0x40C34000u)
68255 /** Peripheral LPI2C5 base pointer */
68256 #define LPI2C5                                   ((LPI2C_Type *)LPI2C5_BASE)
68257 /** Peripheral LPI2C6 base address */
68258 #define LPI2C6_BASE                              (0x40C38000u)
68259 /** Peripheral LPI2C6 base pointer */
68260 #define LPI2C6                                   ((LPI2C_Type *)LPI2C6_BASE)
68261 /** Array initializer of LPI2C peripheral base addresses */
68262 #define LPI2C_BASE_ADDRS                         { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE }
68263 /** Array initializer of LPI2C peripheral base pointers */
68264 #define LPI2C_BASE_PTRS                          { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6 }
68265 /** Interrupt vectors for the LPI2C peripheral type */
68266 #define LPI2C_IRQS                               { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn, LPI2C5_IRQn, LPI2C6_IRQn }
68267 
68268 /*!
68269  * @}
68270  */ /* end of group LPI2C_Peripheral_Access_Layer */
68271 
68272 
68273 /* ----------------------------------------------------------------------------
68274    -- LPSPI Peripheral Access Layer
68275    ---------------------------------------------------------------------------- */
68276 
68277 /*!
68278  * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
68279  * @{
68280  */
68281 
68282 /** LPSPI - Register Layout Typedef */
68283 typedef struct {
68284   __I  uint32_t VERID;                             /**< Version ID, offset: 0x0 */
68285   __I  uint32_t PARAM;                             /**< Parameter, offset: 0x4 */
68286        uint8_t RESERVED_0[8];
68287   __IO uint32_t CR;                                /**< Control, offset: 0x10 */
68288   __IO uint32_t SR;                                /**< Status, offset: 0x14 */
68289   __IO uint32_t IER;                               /**< Interrupt Enable, offset: 0x18 */
68290   __IO uint32_t DER;                               /**< DMA Enable, offset: 0x1C */
68291   __IO uint32_t CFGR0;                             /**< Configuration 0, offset: 0x20 */
68292   __IO uint32_t CFGR1;                             /**< Configuration 1, offset: 0x24 */
68293        uint8_t RESERVED_1[8];
68294   __IO uint32_t DMR0;                              /**< Data Match 0, offset: 0x30 */
68295   __IO uint32_t DMR1;                              /**< Data Match 1, offset: 0x34 */
68296        uint8_t RESERVED_2[8];
68297   __IO uint32_t CCR;                               /**< Clock Configuration, offset: 0x40 */
68298        uint8_t RESERVED_3[20];
68299   __IO uint32_t FCR;                               /**< FIFO Control, offset: 0x58 */
68300   __I  uint32_t FSR;                               /**< FIFO Status, offset: 0x5C */
68301   __IO uint32_t TCR;                               /**< Transmit Command, offset: 0x60 */
68302   __O  uint32_t TDR;                               /**< Transmit Data, offset: 0x64 */
68303        uint8_t RESERVED_4[8];
68304   __I  uint32_t RSR;                               /**< Receive Status, offset: 0x70 */
68305   __I  uint32_t RDR;                               /**< Receive Data, offset: 0x74 */
68306 } LPSPI_Type;
68307 
68308 /* ----------------------------------------------------------------------------
68309    -- LPSPI Register Masks
68310    ---------------------------------------------------------------------------- */
68311 
68312 /*!
68313  * @addtogroup LPSPI_Register_Masks LPSPI Register Masks
68314  * @{
68315  */
68316 
68317 /*! @name VERID - Version ID */
68318 /*! @{ */
68319 
68320 #define LPSPI_VERID_FEATURE_MASK                 (0xFFFFU)
68321 #define LPSPI_VERID_FEATURE_SHIFT                (0U)
68322 /*! FEATURE - Module Identification Number
68323  *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
68324  *  *..
68325  */
68326 #define LPSPI_VERID_FEATURE(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
68327 
68328 #define LPSPI_VERID_MINOR_MASK                   (0xFF0000U)
68329 #define LPSPI_VERID_MINOR_SHIFT                  (16U)
68330 /*! MINOR - Minor Version Number */
68331 #define LPSPI_VERID_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
68332 
68333 #define LPSPI_VERID_MAJOR_MASK                   (0xFF000000U)
68334 #define LPSPI_VERID_MAJOR_SHIFT                  (24U)
68335 /*! MAJOR - Major Version Number */
68336 #define LPSPI_VERID_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
68337 /*! @} */
68338 
68339 /*! @name PARAM - Parameter */
68340 /*! @{ */
68341 
68342 #define LPSPI_PARAM_TXFIFO_MASK                  (0xFFU)
68343 #define LPSPI_PARAM_TXFIFO_SHIFT                 (0U)
68344 /*! TXFIFO - Transmit FIFO Size */
68345 #define LPSPI_PARAM_TXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
68346 
68347 #define LPSPI_PARAM_RXFIFO_MASK                  (0xFF00U)
68348 #define LPSPI_PARAM_RXFIFO_SHIFT                 (8U)
68349 /*! RXFIFO - Receive FIFO Size */
68350 #define LPSPI_PARAM_RXFIFO(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
68351 
68352 #define LPSPI_PARAM_PCSNUM_MASK                  (0xFF0000U)
68353 #define LPSPI_PARAM_PCSNUM_SHIFT                 (16U)
68354 /*! PCSNUM - PCS Number */
68355 #define LPSPI_PARAM_PCSNUM(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
68356 /*! @} */
68357 
68358 /*! @name CR - Control */
68359 /*! @{ */
68360 
68361 #define LPSPI_CR_MEN_MASK                        (0x1U)
68362 #define LPSPI_CR_MEN_SHIFT                       (0U)
68363 /*! MEN - Module Enable
68364  *  0b0..Disable
68365  *  0b1..Enable
68366  */
68367 #define LPSPI_CR_MEN(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
68368 
68369 #define LPSPI_CR_RST_MASK                        (0x2U)
68370 #define LPSPI_CR_RST_SHIFT                       (1U)
68371 /*! RST - Software Reset
68372  *  0b0..Not reset
68373  *  0b1..Reset
68374  */
68375 #define LPSPI_CR_RST(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
68376 
68377 #define LPSPI_CR_DOZEN_MASK                      (0x4U)
68378 #define LPSPI_CR_DOZEN_SHIFT                     (2U)
68379 /*! DOZEN - Doze Mode Enable
68380  *  0b0..Enable
68381  *  0b1..Disable
68382  */
68383 #define LPSPI_CR_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
68384 
68385 #define LPSPI_CR_DBGEN_MASK                      (0x8U)
68386 #define LPSPI_CR_DBGEN_SHIFT                     (3U)
68387 /*! DBGEN - Debug Enable
68388  *  0b0..Disable
68389  *  0b1..Enable
68390  */
68391 #define LPSPI_CR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
68392 
68393 #define LPSPI_CR_RTF_MASK                        (0x100U)
68394 #define LPSPI_CR_RTF_SHIFT                       (8U)
68395 /*! RTF - Reset Transmit FIFO
68396  *  0b0..No effect
68397  *  0b1..Reset
68398  */
68399 #define LPSPI_CR_RTF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
68400 
68401 #define LPSPI_CR_RRF_MASK                        (0x200U)
68402 #define LPSPI_CR_RRF_SHIFT                       (9U)
68403 /*! RRF - Reset Receive FIFO
68404  *  0b0..No effect
68405  *  0b1..Reset
68406  */
68407 #define LPSPI_CR_RRF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
68408 /*! @} */
68409 
68410 /*! @name SR - Status */
68411 /*! @{ */
68412 
68413 #define LPSPI_SR_TDF_MASK                        (0x1U)
68414 #define LPSPI_SR_TDF_SHIFT                       (0U)
68415 /*! TDF - Transmit Data Flag
68416  *  0b0..Transmit data not requested
68417  *  0b1..Transmit data is requested
68418  */
68419 #define LPSPI_SR_TDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
68420 
68421 #define LPSPI_SR_RDF_MASK                        (0x2U)
68422 #define LPSPI_SR_RDF_SHIFT                       (1U)
68423 /*! RDF - Receive Data Flag
68424  *  0b0..Receive data not ready
68425  *  0b1..Receive data is ready
68426  */
68427 #define LPSPI_SR_RDF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
68428 
68429 #define LPSPI_SR_WCF_MASK                        (0x100U)
68430 #define LPSPI_SR_WCF_SHIFT                       (8U)
68431 /*! WCF - Word Complete Flag
68432  *  0b0..Not complete
68433  *  0b1..Complete
68434  */
68435 #define LPSPI_SR_WCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
68436 
68437 #define LPSPI_SR_FCF_MASK                        (0x200U)
68438 #define LPSPI_SR_FCF_SHIFT                       (9U)
68439 /*! FCF - Frame Complete Flag
68440  *  0b0..Not complete
68441  *  0b1..Complete
68442  */
68443 #define LPSPI_SR_FCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
68444 
68445 #define LPSPI_SR_TCF_MASK                        (0x400U)
68446 #define LPSPI_SR_TCF_SHIFT                       (10U)
68447 /*! TCF - Transfer Complete Flag
68448  *  0b0..Not complete
68449  *  0b1..Complete
68450  */
68451 #define LPSPI_SR_TCF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
68452 
68453 #define LPSPI_SR_TEF_MASK                        (0x800U)
68454 #define LPSPI_SR_TEF_SHIFT                       (11U)
68455 /*! TEF - Transmit Error Flag
68456  *  0b0..No underrun
68457  *  0b1..Underrun
68458  */
68459 #define LPSPI_SR_TEF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
68460 
68461 #define LPSPI_SR_REF_MASK                        (0x1000U)
68462 #define LPSPI_SR_REF_SHIFT                       (12U)
68463 /*! REF - Receive Error Flag
68464  *  0b0..No overflow
68465  *  0b1..Overflow
68466  */
68467 #define LPSPI_SR_REF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
68468 
68469 #define LPSPI_SR_DMF_MASK                        (0x2000U)
68470 #define LPSPI_SR_DMF_SHIFT                       (13U)
68471 /*! DMF - Data Match Flag
68472  *  0b0..No match
68473  *  0b1..Match
68474  */
68475 #define LPSPI_SR_DMF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
68476 
68477 #define LPSPI_SR_MBF_MASK                        (0x1000000U)
68478 #define LPSPI_SR_MBF_SHIFT                       (24U)
68479 /*! MBF - Module Busy Flag
68480  *  0b0..LPSPI is idle
68481  *  0b1..LPSPI is busy
68482  */
68483 #define LPSPI_SR_MBF(x)                          (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
68484 /*! @} */
68485 
68486 /*! @name IER - Interrupt Enable */
68487 /*! @{ */
68488 
68489 #define LPSPI_IER_TDIE_MASK                      (0x1U)
68490 #define LPSPI_IER_TDIE_SHIFT                     (0U)
68491 /*! TDIE - Transmit Data Interrupt Enable
68492  *  0b0..Disable
68493  *  0b1..Enable
68494  */
68495 #define LPSPI_IER_TDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
68496 
68497 #define LPSPI_IER_RDIE_MASK                      (0x2U)
68498 #define LPSPI_IER_RDIE_SHIFT                     (1U)
68499 /*! RDIE - Receive Data Interrupt Enable
68500  *  0b0..Disable
68501  *  0b1..Enable
68502  */
68503 #define LPSPI_IER_RDIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
68504 
68505 #define LPSPI_IER_WCIE_MASK                      (0x100U)
68506 #define LPSPI_IER_WCIE_SHIFT                     (8U)
68507 /*! WCIE - Word Complete Interrupt Enable
68508  *  0b0..Disable
68509  *  0b1..Enable
68510  */
68511 #define LPSPI_IER_WCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
68512 
68513 #define LPSPI_IER_FCIE_MASK                      (0x200U)
68514 #define LPSPI_IER_FCIE_SHIFT                     (9U)
68515 /*! FCIE - Frame Complete Interrupt Enable
68516  *  0b0..Disable
68517  *  0b1..Enable
68518  */
68519 #define LPSPI_IER_FCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
68520 
68521 #define LPSPI_IER_TCIE_MASK                      (0x400U)
68522 #define LPSPI_IER_TCIE_SHIFT                     (10U)
68523 /*! TCIE - Transfer Complete Interrupt Enable
68524  *  0b0..Disable
68525  *  0b1..Enable
68526  */
68527 #define LPSPI_IER_TCIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
68528 
68529 #define LPSPI_IER_TEIE_MASK                      (0x800U)
68530 #define LPSPI_IER_TEIE_SHIFT                     (11U)
68531 /*! TEIE - Transmit Error Interrupt Enable
68532  *  0b0..Disable
68533  *  0b1..Enable
68534  */
68535 #define LPSPI_IER_TEIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
68536 
68537 #define LPSPI_IER_REIE_MASK                      (0x1000U)
68538 #define LPSPI_IER_REIE_SHIFT                     (12U)
68539 /*! REIE - Receive Error Interrupt Enable
68540  *  0b0..Disable
68541  *  0b1..Enable
68542  */
68543 #define LPSPI_IER_REIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
68544 
68545 #define LPSPI_IER_DMIE_MASK                      (0x2000U)
68546 #define LPSPI_IER_DMIE_SHIFT                     (13U)
68547 /*! DMIE - Data Match Interrupt Enable
68548  *  0b0..Disable
68549  *  0b1..Enable
68550  */
68551 #define LPSPI_IER_DMIE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
68552 /*! @} */
68553 
68554 /*! @name DER - DMA Enable */
68555 /*! @{ */
68556 
68557 #define LPSPI_DER_TDDE_MASK                      (0x1U)
68558 #define LPSPI_DER_TDDE_SHIFT                     (0U)
68559 /*! TDDE - Transmit Data DMA Enable
68560  *  0b0..Disable
68561  *  0b1..Enable
68562  */
68563 #define LPSPI_DER_TDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
68564 
68565 #define LPSPI_DER_RDDE_MASK                      (0x2U)
68566 #define LPSPI_DER_RDDE_SHIFT                     (1U)
68567 /*! RDDE - Receive Data DMA Enable
68568  *  0b0..Disable
68569  *  0b1..Enable
68570  */
68571 #define LPSPI_DER_RDDE(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
68572 /*! @} */
68573 
68574 /*! @name CFGR0 - Configuration 0 */
68575 /*! @{ */
68576 
68577 #define LPSPI_CFGR0_CIRFIFO_MASK                 (0x100U)
68578 #define LPSPI_CFGR0_CIRFIFO_SHIFT                (8U)
68579 /*! CIRFIFO - Circular FIFO Enable
68580  *  0b0..Disable
68581  *  0b1..Enable
68582  */
68583 #define LPSPI_CFGR0_CIRFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
68584 
68585 #define LPSPI_CFGR0_RDMO_MASK                    (0x200U)
68586 #define LPSPI_CFGR0_RDMO_SHIFT                   (9U)
68587 /*! RDMO - Receive Data Match Only
68588  *  0b0..Disable
68589  *  0b1..Enable
68590  */
68591 #define LPSPI_CFGR0_RDMO(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
68592 /*! @} */
68593 
68594 /*! @name CFGR1 - Configuration 1 */
68595 /*! @{ */
68596 
68597 #define LPSPI_CFGR1_MASTER_MASK                  (0x1U)
68598 #define LPSPI_CFGR1_MASTER_SHIFT                 (0U)
68599 /*! MASTER - Master Mode
68600  *  0b0..Slave mode
68601  *  0b1..Master mode
68602  */
68603 #define LPSPI_CFGR1_MASTER(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
68604 
68605 #define LPSPI_CFGR1_SAMPLE_MASK                  (0x2U)
68606 #define LPSPI_CFGR1_SAMPLE_SHIFT                 (1U)
68607 /*! SAMPLE - Sample Point
68608  *  0b0..SCK edge
68609  *  0b1..Delayed SCK edge
68610  */
68611 #define LPSPI_CFGR1_SAMPLE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
68612 
68613 #define LPSPI_CFGR1_AUTOPCS_MASK                 (0x4U)
68614 #define LPSPI_CFGR1_AUTOPCS_SHIFT                (2U)
68615 /*! AUTOPCS - Automatic PCS
68616  *  0b0..Disable
68617  *  0b1..Enable
68618  */
68619 #define LPSPI_CFGR1_AUTOPCS(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
68620 
68621 #define LPSPI_CFGR1_NOSTALL_MASK                 (0x8U)
68622 #define LPSPI_CFGR1_NOSTALL_SHIFT                (3U)
68623 /*! NOSTALL - No Stall
68624  *  0b0..Disable
68625  *  0b1..Enable
68626  */
68627 #define LPSPI_CFGR1_NOSTALL(x)                   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
68628 
68629 #define LPSPI_CFGR1_PCSPOL_MASK                  (0xF00U)
68630 #define LPSPI_CFGR1_PCSPOL_SHIFT                 (8U)
68631 /*! PCSPOL - Peripheral Chip Select Polarity */
68632 #define LPSPI_CFGR1_PCSPOL(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
68633 
68634 #define LPSPI_CFGR1_MATCFG_MASK                  (0x70000U)
68635 #define LPSPI_CFGR1_MATCFG_SHIFT                 (16U)
68636 /*! MATCFG - Match Configuration
68637  *  0b000..Match is disabled
68638  *  0b001..
68639  *  0b010..Match first data word with compare word
68640  *  0b011..Match any data word with compare word
68641  *  0b100..Sequential match, first data word
68642  *  0b101..Sequential match, any data word
68643  *  0b110..Match first data word (masked) with compare word (masked)
68644  *  0b111..Match any data word (masked) with compare word (masked)
68645  */
68646 #define LPSPI_CFGR1_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
68647 
68648 #define LPSPI_CFGR1_PINCFG_MASK                  (0x3000000U)
68649 #define LPSPI_CFGR1_PINCFG_SHIFT                 (24U)
68650 /*! PINCFG - Pin Configuration
68651  *  0b00..SIN is used for input data; SOUT is used for output data.
68652  *  0b01..SIN is used for both input and output data. Only half-duplex serial transfers are supported.
68653  *  0b10..SOUT is used for both input and output data. Only half-duplex serial transfers are supported.
68654  *  0b11..SOUT is used for input data; SIN is used for output data.
68655  */
68656 #define LPSPI_CFGR1_PINCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
68657 
68658 #define LPSPI_CFGR1_OUTCFG_MASK                  (0x4000000U)
68659 #define LPSPI_CFGR1_OUTCFG_SHIFT                 (26U)
68660 /*! OUTCFG - Output Configuration
68661  *  0b0..Output data retains last value.
68662  *  0b1..Output data is 3-stated.
68663  */
68664 #define LPSPI_CFGR1_OUTCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
68665 
68666 #define LPSPI_CFGR1_PCSCFG_MASK                  (0x8000000U)
68667 #define LPSPI_CFGR1_PCSCFG_SHIFT                 (27U)
68668 /*! PCSCFG - Peripheral Chip Select Configuration
68669  *  0b0..PCS[3:2] are configured for chip select function
68670  *  0b1..PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
68671  */
68672 #define LPSPI_CFGR1_PCSCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
68673 /*! @} */
68674 
68675 /*! @name DMR0 - Data Match 0 */
68676 /*! @{ */
68677 
68678 #define LPSPI_DMR0_MATCH0_MASK                   (0xFFFFFFFFU)
68679 #define LPSPI_DMR0_MATCH0_SHIFT                  (0U)
68680 /*! MATCH0 - Match 0 Value */
68681 #define LPSPI_DMR0_MATCH0(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
68682 /*! @} */
68683 
68684 /*! @name DMR1 - Data Match 1 */
68685 /*! @{ */
68686 
68687 #define LPSPI_DMR1_MATCH1_MASK                   (0xFFFFFFFFU)
68688 #define LPSPI_DMR1_MATCH1_SHIFT                  (0U)
68689 /*! MATCH1 - Match 1 Value */
68690 #define LPSPI_DMR1_MATCH1(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
68691 /*! @} */
68692 
68693 /*! @name CCR - Clock Configuration */
68694 /*! @{ */
68695 
68696 #define LPSPI_CCR_SCKDIV_MASK                    (0xFFU)
68697 #define LPSPI_CCR_SCKDIV_SHIFT                   (0U)
68698 /*! SCKDIV - SCK Divider */
68699 #define LPSPI_CCR_SCKDIV(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
68700 
68701 #define LPSPI_CCR_DBT_MASK                       (0xFF00U)
68702 #define LPSPI_CCR_DBT_SHIFT                      (8U)
68703 /*! DBT - Delay Between Transfers */
68704 #define LPSPI_CCR_DBT(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
68705 
68706 #define LPSPI_CCR_PCSSCK_MASK                    (0xFF0000U)
68707 #define LPSPI_CCR_PCSSCK_SHIFT                   (16U)
68708 /*! PCSSCK - PCS-to-SCK Delay */
68709 #define LPSPI_CCR_PCSSCK(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
68710 
68711 #define LPSPI_CCR_SCKPCS_MASK                    (0xFF000000U)
68712 #define LPSPI_CCR_SCKPCS_SHIFT                   (24U)
68713 /*! SCKPCS - SCK-to-PCS Delay */
68714 #define LPSPI_CCR_SCKPCS(x)                      (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
68715 /*! @} */
68716 
68717 /*! @name FCR - FIFO Control */
68718 /*! @{ */
68719 
68720 #define LPSPI_FCR_TXWATER_MASK                   (0xFU)
68721 #define LPSPI_FCR_TXWATER_SHIFT                  (0U)
68722 /*! TXWATER - Transmit FIFO Watermark */
68723 #define LPSPI_FCR_TXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
68724 
68725 #define LPSPI_FCR_RXWATER_MASK                   (0xF0000U)
68726 #define LPSPI_FCR_RXWATER_SHIFT                  (16U)
68727 /*! RXWATER - Receive FIFO Watermark */
68728 #define LPSPI_FCR_RXWATER(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
68729 /*! @} */
68730 
68731 /*! @name FSR - FIFO Status */
68732 /*! @{ */
68733 
68734 #define LPSPI_FSR_TXCOUNT_MASK                   (0x1FU)
68735 #define LPSPI_FSR_TXCOUNT_SHIFT                  (0U)
68736 /*! TXCOUNT - Transmit FIFO Count */
68737 #define LPSPI_FSR_TXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
68738 
68739 #define LPSPI_FSR_RXCOUNT_MASK                   (0x1F0000U)
68740 #define LPSPI_FSR_RXCOUNT_SHIFT                  (16U)
68741 /*! RXCOUNT - Receive FIFO Count */
68742 #define LPSPI_FSR_RXCOUNT(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
68743 /*! @} */
68744 
68745 /*! @name TCR - Transmit Command */
68746 /*! @{ */
68747 
68748 #define LPSPI_TCR_FRAMESZ_MASK                   (0xFFFU)
68749 #define LPSPI_TCR_FRAMESZ_SHIFT                  (0U)
68750 /*! FRAMESZ - Frame Size */
68751 #define LPSPI_TCR_FRAMESZ(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
68752 
68753 #define LPSPI_TCR_WIDTH_MASK                     (0x30000U)
68754 #define LPSPI_TCR_WIDTH_SHIFT                    (16U)
68755 /*! WIDTH - Transfer Width
68756  *  0b00..1-bit transfer
68757  *  0b01..2-bit transfer
68758  *  0b10..4-bit transfer
68759  *  0b11..Reserved
68760  */
68761 #define LPSPI_TCR_WIDTH(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
68762 
68763 #define LPSPI_TCR_TXMSK_MASK                     (0x40000U)
68764 #define LPSPI_TCR_TXMSK_SHIFT                    (18U)
68765 /*! TXMSK - Transmit Data Mask
68766  *  0b0..Normal transfer
68767  *  0b1..Mask transmit data
68768  */
68769 #define LPSPI_TCR_TXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
68770 
68771 #define LPSPI_TCR_RXMSK_MASK                     (0x80000U)
68772 #define LPSPI_TCR_RXMSK_SHIFT                    (19U)
68773 /*! RXMSK - Receive Data Mask
68774  *  0b0..Normal transfer
68775  *  0b1..Receive data is masked
68776  */
68777 #define LPSPI_TCR_RXMSK(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
68778 
68779 #define LPSPI_TCR_CONTC_MASK                     (0x100000U)
68780 #define LPSPI_TCR_CONTC_SHIFT                    (20U)
68781 /*! CONTC - Continuing Command
68782  *  0b0..Command word for start of new transfer
68783  *  0b1..Command word for continuing transfer
68784  */
68785 #define LPSPI_TCR_CONTC(x)                       (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
68786 
68787 #define LPSPI_TCR_CONT_MASK                      (0x200000U)
68788 #define LPSPI_TCR_CONT_SHIFT                     (21U)
68789 /*! CONT - Continuous Transfer
68790  *  0b0..Continuous transfer is disabled
68791  *  0b1..Continuous transfer is enabled
68792  */
68793 #define LPSPI_TCR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
68794 
68795 #define LPSPI_TCR_BYSW_MASK                      (0x400000U)
68796 #define LPSPI_TCR_BYSW_SHIFT                     (22U)
68797 /*! BYSW - Byte Swap
68798  *  0b0..Disabled
68799  *  0b1..Enabled
68800  */
68801 #define LPSPI_TCR_BYSW(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
68802 
68803 #define LPSPI_TCR_LSBF_MASK                      (0x800000U)
68804 #define LPSPI_TCR_LSBF_SHIFT                     (23U)
68805 /*! LSBF - LSB First
68806  *  0b0..Data is transferred MSB first
68807  *  0b1..Data is transferred LSB first
68808  */
68809 #define LPSPI_TCR_LSBF(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
68810 
68811 #define LPSPI_TCR_PCS_MASK                       (0x3000000U)
68812 #define LPSPI_TCR_PCS_SHIFT                      (24U)
68813 /*! PCS - Peripheral Chip Select
68814  *  0b00..Transfer using PCS[0]
68815  *  0b01..Transfer using PCS[1]
68816  *  0b10..Transfer using PCS[2]
68817  *  0b11..Transfer using PCS[3]
68818  */
68819 #define LPSPI_TCR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
68820 
68821 #define LPSPI_TCR_PRESCALE_MASK                  (0x38000000U)
68822 #define LPSPI_TCR_PRESCALE_SHIFT                 (27U)
68823 /*! PRESCALE - Prescaler Value
68824  *  0b000..Divide by 1
68825  *  0b001..Divide by 2
68826  *  0b010..Divide by 4
68827  *  0b011..Divide by 8
68828  *  0b100..Divide by 16
68829  *  0b101..Divide by 32
68830  *  0b110..Divide by 64
68831  *  0b111..Divide by 128
68832  */
68833 #define LPSPI_TCR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
68834 
68835 #define LPSPI_TCR_CPHA_MASK                      (0x40000000U)
68836 #define LPSPI_TCR_CPHA_SHIFT                     (30U)
68837 /*! CPHA - Clock Phase
68838  *  0b0..Captured
68839  *  0b1..Changed
68840  */
68841 #define LPSPI_TCR_CPHA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
68842 
68843 #define LPSPI_TCR_CPOL_MASK                      (0x80000000U)
68844 #define LPSPI_TCR_CPOL_SHIFT                     (31U)
68845 /*! CPOL - Clock Polarity
68846  *  0b0..Inactive low
68847  *  0b1..Inactive high
68848  */
68849 #define LPSPI_TCR_CPOL(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
68850 /*! @} */
68851 
68852 /*! @name TDR - Transmit Data */
68853 /*! @{ */
68854 
68855 #define LPSPI_TDR_DATA_MASK                      (0xFFFFFFFFU)
68856 #define LPSPI_TDR_DATA_SHIFT                     (0U)
68857 /*! DATA - Transmit Data */
68858 #define LPSPI_TDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
68859 /*! @} */
68860 
68861 /*! @name RSR - Receive Status */
68862 /*! @{ */
68863 
68864 #define LPSPI_RSR_SOF_MASK                       (0x1U)
68865 #define LPSPI_RSR_SOF_SHIFT                      (0U)
68866 /*! SOF - Start Of Frame
68867  *  0b0..Subsequent data word
68868  *  0b1..First data word
68869  */
68870 #define LPSPI_RSR_SOF(x)                         (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
68871 
68872 #define LPSPI_RSR_RXEMPTY_MASK                   (0x2U)
68873 #define LPSPI_RSR_RXEMPTY_SHIFT                  (1U)
68874 /*! RXEMPTY - RX FIFO Empty
68875  *  0b0..Not empty
68876  *  0b1..Empty
68877  */
68878 #define LPSPI_RSR_RXEMPTY(x)                     (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
68879 /*! @} */
68880 
68881 /*! @name RDR - Receive Data */
68882 /*! @{ */
68883 
68884 #define LPSPI_RDR_DATA_MASK                      (0xFFFFFFFFU)
68885 #define LPSPI_RDR_DATA_SHIFT                     (0U)
68886 /*! DATA - Receive Data */
68887 #define LPSPI_RDR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
68888 /*! @} */
68889 
68890 
68891 /*!
68892  * @}
68893  */ /* end of group LPSPI_Register_Masks */
68894 
68895 
68896 /* LPSPI - Peripheral instance base addresses */
68897 /** Peripheral LPSPI1 base address */
68898 #define LPSPI1_BASE                              (0x40114000u)
68899 /** Peripheral LPSPI1 base pointer */
68900 #define LPSPI1                                   ((LPSPI_Type *)LPSPI1_BASE)
68901 /** Peripheral LPSPI2 base address */
68902 #define LPSPI2_BASE                              (0x40118000u)
68903 /** Peripheral LPSPI2 base pointer */
68904 #define LPSPI2                                   ((LPSPI_Type *)LPSPI2_BASE)
68905 /** Peripheral LPSPI3 base address */
68906 #define LPSPI3_BASE                              (0x4011C000u)
68907 /** Peripheral LPSPI3 base pointer */
68908 #define LPSPI3                                   ((LPSPI_Type *)LPSPI3_BASE)
68909 /** Peripheral LPSPI4 base address */
68910 #define LPSPI4_BASE                              (0x40120000u)
68911 /** Peripheral LPSPI4 base pointer */
68912 #define LPSPI4                                   ((LPSPI_Type *)LPSPI4_BASE)
68913 /** Peripheral LPSPI5 base address */
68914 #define LPSPI5_BASE                              (0x40C2C000u)
68915 /** Peripheral LPSPI5 base pointer */
68916 #define LPSPI5                                   ((LPSPI_Type *)LPSPI5_BASE)
68917 /** Peripheral LPSPI6 base address */
68918 #define LPSPI6_BASE                              (0x40C30000u)
68919 /** Peripheral LPSPI6 base pointer */
68920 #define LPSPI6                                   ((LPSPI_Type *)LPSPI6_BASE)
68921 /** Array initializer of LPSPI peripheral base addresses */
68922 #define LPSPI_BASE_ADDRS                         { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE }
68923 /** Array initializer of LPSPI peripheral base pointers */
68924 #define LPSPI_BASE_PTRS                          { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6 }
68925 /** Interrupt vectors for the LPSPI peripheral type */
68926 #define LPSPI_IRQS                               { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn, LPSPI5_IRQn, LPSPI6_IRQn }
68927 
68928 /*!
68929  * @}
68930  */ /* end of group LPSPI_Peripheral_Access_Layer */
68931 
68932 
68933 /* ----------------------------------------------------------------------------
68934    -- LPUART Peripheral Access Layer
68935    ---------------------------------------------------------------------------- */
68936 
68937 /*!
68938  * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
68939  * @{
68940  */
68941 
68942 /** LPUART - Register Layout Typedef */
68943 typedef struct {
68944   __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
68945   __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
68946   __IO uint32_t GLOBAL;                            /**< LPUART Global Register, offset: 0x8 */
68947   __IO uint32_t PINCFG;                            /**< LPUART Pin Configuration Register, offset: 0xC */
68948   __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x10 */
68949   __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x14 */
68950   __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x18 */
68951   __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0x1C */
68952   __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x20 */
68953   __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x24 */
68954   __IO uint32_t FIFO;                              /**< LPUART FIFO Register, offset: 0x28 */
68955   __IO uint32_t WATER;                             /**< LPUART Watermark Register, offset: 0x2C */
68956 } LPUART_Type;
68957 
68958 /* ----------------------------------------------------------------------------
68959    -- LPUART Register Masks
68960    ---------------------------------------------------------------------------- */
68961 
68962 /*!
68963  * @addtogroup LPUART_Register_Masks LPUART Register Masks
68964  * @{
68965  */
68966 
68967 /*! @name VERID - Version ID Register */
68968 /*! @{ */
68969 
68970 #define LPUART_VERID_FEATURE_MASK                (0xFFFFU)
68971 #define LPUART_VERID_FEATURE_SHIFT               (0U)
68972 /*! FEATURE - Feature Identification Number
68973  *  0b0000000000000001..Standard feature set.
68974  *  0b0000000000000011..Standard feature set with MODEM/IrDA support.
68975  */
68976 #define LPUART_VERID_FEATURE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
68977 
68978 #define LPUART_VERID_MINOR_MASK                  (0xFF0000U)
68979 #define LPUART_VERID_MINOR_SHIFT                 (16U)
68980 /*! MINOR - Minor Version Number */
68981 #define LPUART_VERID_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
68982 
68983 #define LPUART_VERID_MAJOR_MASK                  (0xFF000000U)
68984 #define LPUART_VERID_MAJOR_SHIFT                 (24U)
68985 /*! MAJOR - Major Version Number */
68986 #define LPUART_VERID_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
68987 /*! @} */
68988 
68989 /*! @name PARAM - Parameter Register */
68990 /*! @{ */
68991 
68992 #define LPUART_PARAM_TXFIFO_MASK                 (0xFFU)
68993 #define LPUART_PARAM_TXFIFO_SHIFT                (0U)
68994 /*! TXFIFO - Transmit FIFO Size */
68995 #define LPUART_PARAM_TXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
68996 
68997 #define LPUART_PARAM_RXFIFO_MASK                 (0xFF00U)
68998 #define LPUART_PARAM_RXFIFO_SHIFT                (8U)
68999 /*! RXFIFO - Receive FIFO Size */
69000 #define LPUART_PARAM_RXFIFO(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
69001 /*! @} */
69002 
69003 /*! @name GLOBAL - LPUART Global Register */
69004 /*! @{ */
69005 
69006 #define LPUART_GLOBAL_RST_MASK                   (0x2U)
69007 #define LPUART_GLOBAL_RST_SHIFT                  (1U)
69008 /*! RST - Software Reset
69009  *  0b0..Module is not reset.
69010  *  0b1..Module is reset.
69011  */
69012 #define LPUART_GLOBAL_RST(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
69013 /*! @} */
69014 
69015 /*! @name PINCFG - LPUART Pin Configuration Register */
69016 /*! @{ */
69017 
69018 #define LPUART_PINCFG_TRGSEL_MASK                (0x3U)
69019 #define LPUART_PINCFG_TRGSEL_SHIFT               (0U)
69020 /*! TRGSEL - Trigger Select
69021  *  0b00..Input trigger is disabled.
69022  *  0b01..Input trigger is used instead of RXD pin input.
69023  *  0b10..Input trigger is used instead of CTS_B pin input.
69024  *  0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is
69025  *        internally ANDed with the input trigger.
69026  */
69027 #define LPUART_PINCFG_TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
69028 /*! @} */
69029 
69030 /*! @name BAUD - LPUART Baud Rate Register */
69031 /*! @{ */
69032 
69033 #define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
69034 #define LPUART_BAUD_SBR_SHIFT                    (0U)
69035 /*! SBR - Baud Rate Modulo Divisor. */
69036 #define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
69037 
69038 #define LPUART_BAUD_SBNS_MASK                    (0x2000U)
69039 #define LPUART_BAUD_SBNS_SHIFT                   (13U)
69040 /*! SBNS - Stop Bit Number Select
69041  *  0b0..One stop bit.
69042  *  0b1..Two stop bits.
69043  */
69044 #define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
69045 
69046 #define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
69047 #define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
69048 /*! RXEDGIE - RX Input Active Edge Interrupt Enable
69049  *  0b0..Hardware interrupts from STAT[RXEDGIF] are disabled.
69050  *  0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.
69051  */
69052 #define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
69053 
69054 #define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
69055 #define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
69056 /*! LBKDIE - LIN Break Detect Interrupt Enable
69057  *  0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling).
69058  *  0b1..Hardware interrupt is requested when STAT[LBKDIF] flag is 1.
69059  */
69060 #define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
69061 
69062 #define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
69063 #define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
69064 /*! RESYNCDIS - Resynchronization Disable
69065  *  0b0..Resynchronization during received data word is supported.
69066  *  0b1..Resynchronization during received data word is disabled.
69067  */
69068 #define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
69069 
69070 #define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
69071 #define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
69072 /*! BOTHEDGE - Both Edge Sampling
69073  *  0b0..Receiver samples input data using the rising edge of the baud rate clock.
69074  *  0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
69075  */
69076 #define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
69077 
69078 #define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
69079 #define LPUART_BAUD_MATCFG_SHIFT                 (18U)
69080 /*! MATCFG - Match Configuration
69081  *  0b00..Address Match Wakeup
69082  *  0b01..Idle Match Wakeup
69083  *  0b10..Match On and Match Off
69084  *  0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
69085  */
69086 #define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
69087 
69088 #define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
69089 #define LPUART_BAUD_RDMAE_SHIFT                  (21U)
69090 /*! RDMAE - Receiver Full DMA Enable
69091  *  0b0..DMA request disabled.
69092  *  0b1..DMA request enabled.
69093  */
69094 #define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
69095 
69096 #define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
69097 #define LPUART_BAUD_TDMAE_SHIFT                  (23U)
69098 /*! TDMAE - Transmitter DMA Enable
69099  *  0b0..DMA request disabled.
69100  *  0b1..DMA request enabled.
69101  */
69102 #define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
69103 
69104 #define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
69105 #define LPUART_BAUD_OSR_SHIFT                    (24U)
69106 /*! OSR - Oversampling Ratio
69107  *  0b00000..Writing 0 to this field results in an oversampling ratio of 16
69108  *  0b00001..Reserved
69109  *  0b00010..Reserved
69110  *  0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set.
69111  *  0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set.
69112  *  0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set.
69113  *  0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set.
69114  *  0b00111..Oversampling ratio of 8.
69115  *  0b01000..Oversampling ratio of 9.
69116  *  0b01001..Oversampling ratio of 10.
69117  *  0b01010..Oversampling ratio of 11.
69118  *  0b01011..Oversampling ratio of 12.
69119  *  0b01100..Oversampling ratio of 13.
69120  *  0b01101..Oversampling ratio of 14.
69121  *  0b01110..Oversampling ratio of 15.
69122  *  0b01111..Oversampling ratio of 16.
69123  *  0b10000..Oversampling ratio of 17.
69124  *  0b10001..Oversampling ratio of 18.
69125  *  0b10010..Oversampling ratio of 19.
69126  *  0b10011..Oversampling ratio of 20.
69127  *  0b10100..Oversampling ratio of 21.
69128  *  0b10101..Oversampling ratio of 22.
69129  *  0b10110..Oversampling ratio of 23.
69130  *  0b10111..Oversampling ratio of 24.
69131  *  0b11000..Oversampling ratio of 25.
69132  *  0b11001..Oversampling ratio of 26.
69133  *  0b11010..Oversampling ratio of 27.
69134  *  0b11011..Oversampling ratio of 28.
69135  *  0b11100..Oversampling ratio of 29.
69136  *  0b11101..Oversampling ratio of 30.
69137  *  0b11110..Oversampling ratio of 31.
69138  *  0b11111..Oversampling ratio of 32.
69139  */
69140 #define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
69141 
69142 #define LPUART_BAUD_M10_MASK                     (0x20000000U)
69143 #define LPUART_BAUD_M10_SHIFT                    (29U)
69144 /*! M10 - 10-bit Mode select
69145  *  0b0..Receiver and transmitter use 7-bit to 9-bit data characters.
69146  *  0b1..Receiver and transmitter use 10-bit data characters.
69147  */
69148 #define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
69149 
69150 #define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
69151 #define LPUART_BAUD_MAEN2_SHIFT                  (30U)
69152 /*! MAEN2 - Match Address Mode Enable 2
69153  *  0b0..Normal operation.
69154  *  0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
69155  */
69156 #define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
69157 
69158 #define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
69159 #define LPUART_BAUD_MAEN1_SHIFT                  (31U)
69160 /*! MAEN1 - Match Address Mode Enable 1
69161  *  0b0..Normal operation.
69162  *  0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
69163  */
69164 #define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
69165 /*! @} */
69166 
69167 /*! @name STAT - LPUART Status Register */
69168 /*! @{ */
69169 
69170 #define LPUART_STAT_MA2F_MASK                    (0x4000U)
69171 #define LPUART_STAT_MA2F_SHIFT                   (14U)
69172 /*! MA2F - Match 2 Flag
69173  *  0b0..Received data is not equal to MA2
69174  *  0b1..Received data is equal to MA2
69175  */
69176 #define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
69177 
69178 #define LPUART_STAT_MA1F_MASK                    (0x8000U)
69179 #define LPUART_STAT_MA1F_SHIFT                   (15U)
69180 /*! MA1F - Match 1 Flag
69181  *  0b0..Received data is not equal to MA1
69182  *  0b1..Received data is equal to MA1
69183  */
69184 #define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
69185 
69186 #define LPUART_STAT_PF_MASK                      (0x10000U)
69187 #define LPUART_STAT_PF_SHIFT                     (16U)
69188 /*! PF - Parity Error Flag
69189  *  0b0..No parity error.
69190  *  0b1..Parity error.
69191  */
69192 #define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
69193 
69194 #define LPUART_STAT_FE_MASK                      (0x20000U)
69195 #define LPUART_STAT_FE_SHIFT                     (17U)
69196 /*! FE - Framing Error Flag
69197  *  0b0..No framing error detected. This does not guarantee the framing is correct.
69198  *  0b1..Framing error.
69199  */
69200 #define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
69201 
69202 #define LPUART_STAT_NF_MASK                      (0x40000U)
69203 #define LPUART_STAT_NF_SHIFT                     (18U)
69204 /*! NF - Noise Flag
69205  *  0b0..No noise detected.
69206  *  0b1..Noise detected in the received character in the DATA register.
69207  */
69208 #define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
69209 
69210 #define LPUART_STAT_OR_MASK                      (0x80000U)
69211 #define LPUART_STAT_OR_SHIFT                     (19U)
69212 /*! OR - Receiver Overrun Flag
69213  *  0b0..No overrun.
69214  *  0b1..Receive overrun (new LPUART data lost).
69215  */
69216 #define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
69217 
69218 #define LPUART_STAT_IDLE_MASK                    (0x100000U)
69219 #define LPUART_STAT_IDLE_SHIFT                   (20U)
69220 /*! IDLE - Idle Line Flag
69221  *  0b0..No idle line detected.
69222  *  0b1..Idle line is detected.
69223  */
69224 #define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
69225 
69226 #define LPUART_STAT_RDRF_MASK                    (0x200000U)
69227 #define LPUART_STAT_RDRF_SHIFT                   (21U)
69228 /*! RDRF - Receive Data Register Full Flag
69229  *  0b0..Receive FIFO level is less than watermark.
69230  *  0b1..Receive FIFO level is equal or greater than watermark.
69231  */
69232 #define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
69233 
69234 #define LPUART_STAT_TC_MASK                      (0x400000U)
69235 #define LPUART_STAT_TC_SHIFT                     (22U)
69236 /*! TC - Transmission Complete Flag
69237  *  0b0..Transmitter active (sending data, a preamble, or a break).
69238  *  0b1..Transmitter idle (transmission activity complete).
69239  */
69240 #define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
69241 
69242 #define LPUART_STAT_TDRE_MASK                    (0x800000U)
69243 #define LPUART_STAT_TDRE_SHIFT                   (23U)
69244 /*! TDRE - Transmit Data Register Empty Flag
69245  *  0b0..Transmit FIFO level is greater than watermark.
69246  *  0b1..Transmit FIFO level is equal or less than watermark.
69247  */
69248 #define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
69249 
69250 #define LPUART_STAT_RAF_MASK                     (0x1000000U)
69251 #define LPUART_STAT_RAF_SHIFT                    (24U)
69252 /*! RAF - Receiver Active Flag
69253  *  0b0..LPUART receiver idle waiting for a start bit.
69254  *  0b1..LPUART receiver active (RXD input not idle).
69255  */
69256 #define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
69257 
69258 #define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
69259 #define LPUART_STAT_LBKDE_SHIFT                  (25U)
69260 /*! LBKDE - LIN Break Detection Enable
69261  *  0b0..LIN break detect is disabled, normal break character can be detected.
69262  *  0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
69263  */
69264 #define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
69265 
69266 #define LPUART_STAT_BRK13_MASK                   (0x4000000U)
69267 #define LPUART_STAT_BRK13_SHIFT                  (26U)
69268 /*! BRK13 - Break Character Generation Length
69269  *  0b0..Break character is transmitted with length of 9 to 13 bit times.
69270  *  0b1..Break character is transmitted with length of 12 to 15 bit times.
69271  */
69272 #define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
69273 
69274 #define LPUART_STAT_RWUID_MASK                   (0x8000000U)
69275 #define LPUART_STAT_RWUID_SHIFT                  (27U)
69276 /*! RWUID - Receive Wake Up Idle Detect
69277  *  0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
69278  *       character. During address match wakeup, the IDLE bit does not set when an address does not match.
69279  *  0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During
69280  *       address match wakeup, the IDLE bit does set when an address does not match.
69281  */
69282 #define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
69283 
69284 #define LPUART_STAT_RXINV_MASK                   (0x10000000U)
69285 #define LPUART_STAT_RXINV_SHIFT                  (28U)
69286 /*! RXINV - Receive Data Inversion
69287  *  0b0..Receive data not inverted.
69288  *  0b1..Receive data inverted.
69289  */
69290 #define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
69291 
69292 #define LPUART_STAT_MSBF_MASK                    (0x20000000U)
69293 #define LPUART_STAT_MSBF_SHIFT                   (29U)
69294 /*! MSBF - MSB First
69295  *  0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received
69296  *       after the start bit is identified as bit0.
69297  *  0b1..MSB (identified as bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit
69298  *       depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. .
69299  */
69300 #define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
69301 
69302 #define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
69303 #define LPUART_STAT_RXEDGIF_SHIFT                (30U)
69304 /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
69305  *  0b0..No active edge on the receive pin has occurred.
69306  *  0b1..An active edge on the receive pin has occurred.
69307  */
69308 #define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
69309 
69310 #define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
69311 #define LPUART_STAT_LBKDIF_SHIFT                 (31U)
69312 /*! LBKDIF - LIN Break Detect Interrupt Flag
69313  *  0b0..No LIN break character has been detected.
69314  *  0b1..LIN break character has been detected.
69315  */
69316 #define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
69317 /*! @} */
69318 
69319 /*! @name CTRL - LPUART Control Register */
69320 /*! @{ */
69321 
69322 #define LPUART_CTRL_PT_MASK                      (0x1U)
69323 #define LPUART_CTRL_PT_SHIFT                     (0U)
69324 /*! PT - Parity Type
69325  *  0b0..Even parity.
69326  *  0b1..Odd parity.
69327  */
69328 #define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
69329 
69330 #define LPUART_CTRL_PE_MASK                      (0x2U)
69331 #define LPUART_CTRL_PE_SHIFT                     (1U)
69332 /*! PE - Parity Enable
69333  *  0b0..No hardware parity generation or checking.
69334  *  0b1..Parity enabled.
69335  */
69336 #define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
69337 
69338 #define LPUART_CTRL_ILT_MASK                     (0x4U)
69339 #define LPUART_CTRL_ILT_SHIFT                    (2U)
69340 /*! ILT - Idle Line Type Select
69341  *  0b0..Idle character bit count starts after start bit.
69342  *  0b1..Idle character bit count starts after stop bit.
69343  */
69344 #define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
69345 
69346 #define LPUART_CTRL_WAKE_MASK                    (0x8U)
69347 #define LPUART_CTRL_WAKE_SHIFT                   (3U)
69348 /*! WAKE - Receiver Wakeup Method Select
69349  *  0b0..Configures RWU for idle-line wakeup.
69350  *  0b1..Configures RWU with address-mark wakeup.
69351  */
69352 #define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
69353 
69354 #define LPUART_CTRL_M_MASK                       (0x10U)
69355 #define LPUART_CTRL_M_SHIFT                      (4U)
69356 /*! M - 9-Bit or 8-Bit Mode Select
69357  *  0b0..Receiver and transmitter use 8-bit data characters.
69358  *  0b1..Receiver and transmitter use 9-bit data characters.
69359  */
69360 #define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
69361 
69362 #define LPUART_CTRL_RSRC_MASK                    (0x20U)
69363 #define LPUART_CTRL_RSRC_SHIFT                   (5U)
69364 /*! RSRC - Receiver Source Select
69365  *  0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.
69366  *  0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.
69367  */
69368 #define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
69369 
69370 #define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
69371 #define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
69372 /*! DOZEEN - Doze Enable
69373  *  0b0..LPUART is enabled in Doze mode.
69374  *  0b1..LPUART is disabled in Doze mode .
69375  */
69376 #define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
69377 
69378 #define LPUART_CTRL_LOOPS_MASK                   (0x80U)
69379 #define LPUART_CTRL_LOOPS_SHIFT                  (7U)
69380 /*! LOOPS - Loop Mode Select
69381  *  0b0..Normal operation - RXD and TXD use separate pins.
69382  *  0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
69383  */
69384 #define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
69385 
69386 #define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
69387 #define LPUART_CTRL_IDLECFG_SHIFT                (8U)
69388 /*! IDLECFG - Idle Configuration
69389  *  0b000..1 idle character
69390  *  0b001..2 idle characters
69391  *  0b010..4 idle characters
69392  *  0b011..8 idle characters
69393  *  0b100..16 idle characters
69394  *  0b101..32 idle characters
69395  *  0b110..64 idle characters
69396  *  0b111..128 idle characters
69397  */
69398 #define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
69399 
69400 #define LPUART_CTRL_M7_MASK                      (0x800U)
69401 #define LPUART_CTRL_M7_SHIFT                     (11U)
69402 /*! M7 - 7-Bit Mode Select
69403  *  0b0..Receiver and transmitter use 8-bit to 10-bit data characters.
69404  *  0b1..Receiver and transmitter use 7-bit data characters.
69405  */
69406 #define LPUART_CTRL_M7(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
69407 
69408 #define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
69409 #define LPUART_CTRL_MA2IE_SHIFT                  (14U)
69410 /*! MA2IE - Match 2 Interrupt Enable
69411  *  0b0..MA2F interrupt disabled
69412  *  0b1..MA2F interrupt enabled
69413  */
69414 #define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
69415 
69416 #define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
69417 #define LPUART_CTRL_MA1IE_SHIFT                  (15U)
69418 /*! MA1IE - Match 1 Interrupt Enable
69419  *  0b0..MA1F interrupt disabled
69420  *  0b1..MA1F interrupt enabled
69421  */
69422 #define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
69423 
69424 #define LPUART_CTRL_SBK_MASK                     (0x10000U)
69425 #define LPUART_CTRL_SBK_SHIFT                    (16U)
69426 /*! SBK - Send Break
69427  *  0b0..Normal transmitter operation.
69428  *  0b1..Queue break character(s) to be sent.
69429  */
69430 #define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
69431 
69432 #define LPUART_CTRL_RWU_MASK                     (0x20000U)
69433 #define LPUART_CTRL_RWU_SHIFT                    (17U)
69434 /*! RWU - Receiver Wakeup Control
69435  *  0b0..Normal receiver operation.
69436  *  0b1..LPUART receiver in standby waiting for wakeup condition.
69437  */
69438 #define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
69439 
69440 #define LPUART_CTRL_RE_MASK                      (0x40000U)
69441 #define LPUART_CTRL_RE_SHIFT                     (18U)
69442 /*! RE - Receiver Enable
69443  *  0b0..Receiver disabled.
69444  *  0b1..Receiver enabled.
69445  */
69446 #define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
69447 
69448 #define LPUART_CTRL_TE_MASK                      (0x80000U)
69449 #define LPUART_CTRL_TE_SHIFT                     (19U)
69450 /*! TE - Transmitter Enable
69451  *  0b0..Transmitter disabled.
69452  *  0b1..Transmitter enabled.
69453  */
69454 #define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
69455 
69456 #define LPUART_CTRL_ILIE_MASK                    (0x100000U)
69457 #define LPUART_CTRL_ILIE_SHIFT                   (20U)
69458 /*! ILIE - Idle Line Interrupt Enable
69459  *  0b0..Hardware interrupts from IDLE disabled; use polling.
69460  *  0b1..Hardware interrupt is requested when IDLE flag is 1.
69461  */
69462 #define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
69463 
69464 #define LPUART_CTRL_RIE_MASK                     (0x200000U)
69465 #define LPUART_CTRL_RIE_SHIFT                    (21U)
69466 /*! RIE - Receiver Interrupt Enable
69467  *  0b0..Hardware interrupts from RDRF disabled.
69468  *  0b1..Hardware interrupt is requested when RDRF flag is 1.
69469  */
69470 #define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
69471 
69472 #define LPUART_CTRL_TCIE_MASK                    (0x400000U)
69473 #define LPUART_CTRL_TCIE_SHIFT                   (22U)
69474 /*! TCIE - Transmission Complete Interrupt Enable for
69475  *  0b0..Hardware interrupts from TC disabled.
69476  *  0b1..Hardware interrupt is requested when TC flag is 1.
69477  */
69478 #define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
69479 
69480 #define LPUART_CTRL_TIE_MASK                     (0x800000U)
69481 #define LPUART_CTRL_TIE_SHIFT                    (23U)
69482 /*! TIE - Transmit Interrupt Enable
69483  *  0b0..Hardware interrupts from TDRE disabled.
69484  *  0b1..Hardware interrupt is requested when TDRE flag is 1.
69485  */
69486 #define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
69487 
69488 #define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
69489 #define LPUART_CTRL_PEIE_SHIFT                   (24U)
69490 /*! PEIE - Parity Error Interrupt Enable
69491  *  0b0..PF interrupts disabled; use polling).
69492  *  0b1..Hardware interrupt is requested when PF is set.
69493  */
69494 #define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
69495 
69496 #define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
69497 #define LPUART_CTRL_FEIE_SHIFT                   (25U)
69498 /*! FEIE - Framing Error Interrupt Enable
69499  *  0b0..FE interrupts disabled; use polling.
69500  *  0b1..Hardware interrupt is requested when FE is set.
69501  */
69502 #define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
69503 
69504 #define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
69505 #define LPUART_CTRL_NEIE_SHIFT                   (26U)
69506 /*! NEIE - Noise Error Interrupt Enable
69507  *  0b0..NF interrupts disabled; use polling.
69508  *  0b1..Hardware interrupt is requested when NF is set.
69509  */
69510 #define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
69511 
69512 #define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
69513 #define LPUART_CTRL_ORIE_SHIFT                   (27U)
69514 /*! ORIE - Overrun Interrupt Enable
69515  *  0b0..OR interrupts disabled; use polling.
69516  *  0b1..Hardware interrupt is requested when OR is set.
69517  */
69518 #define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
69519 
69520 #define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
69521 #define LPUART_CTRL_TXINV_SHIFT                  (28U)
69522 /*! TXINV - Transmit Data Inversion
69523  *  0b0..Transmit data not inverted.
69524  *  0b1..Transmit data inverted.
69525  */
69526 #define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
69527 
69528 #define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
69529 #define LPUART_CTRL_TXDIR_SHIFT                  (29U)
69530 /*! TXDIR - TXD Pin Direction in Single-Wire Mode
69531  *  0b0..TXD pin is an input in single-wire mode.
69532  *  0b1..TXD pin is an output in single-wire mode.
69533  */
69534 #define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
69535 
69536 #define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
69537 #define LPUART_CTRL_R9T8_SHIFT                   (30U)
69538 /*! R9T8 - Receive Bit 9 / Transmit Bit 8 */
69539 #define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
69540 
69541 #define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
69542 #define LPUART_CTRL_R8T9_SHIFT                   (31U)
69543 /*! R8T9 - Receive Bit 8 / Transmit Bit 9 */
69544 #define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
69545 /*! @} */
69546 
69547 /*! @name DATA - LPUART Data Register */
69548 /*! @{ */
69549 
69550 #define LPUART_DATA_R0T0_MASK                    (0x1U)
69551 #define LPUART_DATA_R0T0_SHIFT                   (0U)
69552 /*! R0T0 - R0T0 */
69553 #define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
69554 
69555 #define LPUART_DATA_R1T1_MASK                    (0x2U)
69556 #define LPUART_DATA_R1T1_SHIFT                   (1U)
69557 /*! R1T1 - R1T1 */
69558 #define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
69559 
69560 #define LPUART_DATA_R2T2_MASK                    (0x4U)
69561 #define LPUART_DATA_R2T2_SHIFT                   (2U)
69562 /*! R2T2 - R2T2 */
69563 #define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
69564 
69565 #define LPUART_DATA_R3T3_MASK                    (0x8U)
69566 #define LPUART_DATA_R3T3_SHIFT                   (3U)
69567 /*! R3T3 - R3T3 */
69568 #define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
69569 
69570 #define LPUART_DATA_R4T4_MASK                    (0x10U)
69571 #define LPUART_DATA_R4T4_SHIFT                   (4U)
69572 /*! R4T4 - R4T4 */
69573 #define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
69574 
69575 #define LPUART_DATA_R5T5_MASK                    (0x20U)
69576 #define LPUART_DATA_R5T5_SHIFT                   (5U)
69577 /*! R5T5 - R5T5 */
69578 #define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
69579 
69580 #define LPUART_DATA_R6T6_MASK                    (0x40U)
69581 #define LPUART_DATA_R6T6_SHIFT                   (6U)
69582 /*! R6T6 - R6T6 */
69583 #define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
69584 
69585 #define LPUART_DATA_R7T7_MASK                    (0x80U)
69586 #define LPUART_DATA_R7T7_SHIFT                   (7U)
69587 /*! R7T7 - R7T7 */
69588 #define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
69589 
69590 #define LPUART_DATA_R8T8_MASK                    (0x100U)
69591 #define LPUART_DATA_R8T8_SHIFT                   (8U)
69592 /*! R8T8 - R8T8 */
69593 #define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
69594 
69595 #define LPUART_DATA_R9T9_MASK                    (0x200U)
69596 #define LPUART_DATA_R9T9_SHIFT                   (9U)
69597 /*! R9T9 - R9T9 */
69598 #define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
69599 
69600 #define LPUART_DATA_IDLINE_MASK                  (0x800U)
69601 #define LPUART_DATA_IDLINE_SHIFT                 (11U)
69602 /*! IDLINE - Idle Line
69603  *  0b0..Receiver was not idle before receiving this character.
69604  *  0b1..Receiver was idle before receiving this character.
69605  */
69606 #define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
69607 
69608 #define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
69609 #define LPUART_DATA_RXEMPT_SHIFT                 (12U)
69610 /*! RXEMPT - Receive Buffer Empty
69611  *  0b0..Receive buffer contains valid data.
69612  *  0b1..Receive buffer is empty, data returned on read is not valid.
69613  */
69614 #define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
69615 
69616 #define LPUART_DATA_FRETSC_MASK                  (0x2000U)
69617 #define LPUART_DATA_FRETSC_SHIFT                 (13U)
69618 /*! FRETSC - Frame Error / Transmit Special Character
69619  *  0b0..The dataword is received without a frame error on read, or transmit a normal character on write.
69620  *  0b1..The dataword is received with a frame error, or transmit an idle or break character on transmit.
69621  */
69622 #define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
69623 
69624 #define LPUART_DATA_PARITYE_MASK                 (0x4000U)
69625 #define LPUART_DATA_PARITYE_SHIFT                (14U)
69626 /*! PARITYE - Parity Error
69627  *  0b0..The dataword is received without a parity error.
69628  *  0b1..The dataword is received with a parity error.
69629  */
69630 #define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
69631 
69632 #define LPUART_DATA_NOISY_MASK                   (0x8000U)
69633 #define LPUART_DATA_NOISY_SHIFT                  (15U)
69634 /*! NOISY - Noisy Data Received
69635  *  0b0..The dataword is received without noise.
69636  *  0b1..The data is received with noise.
69637  */
69638 #define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
69639 /*! @} */
69640 
69641 /*! @name MATCH - LPUART Match Address Register */
69642 /*! @{ */
69643 
69644 #define LPUART_MATCH_MA1_MASK                    (0x3FFU)
69645 #define LPUART_MATCH_MA1_SHIFT                   (0U)
69646 /*! MA1 - Match Address 1 */
69647 #define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
69648 
69649 #define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
69650 #define LPUART_MATCH_MA2_SHIFT                   (16U)
69651 /*! MA2 - Match Address 2 */
69652 #define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
69653 /*! @} */
69654 
69655 /*! @name MODIR - LPUART Modem IrDA Register */
69656 /*! @{ */
69657 
69658 #define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
69659 #define LPUART_MODIR_TXCTSE_SHIFT                (0U)
69660 /*! TXCTSE - Transmitter clear-to-send enable
69661  *  0b0..CTS has no effect on the transmitter.
69662  *  0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a
69663  *       character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the
69664  *       mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent
69665  *       do not affect its transmission.
69666  */
69667 #define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
69668 
69669 #define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
69670 #define LPUART_MODIR_TXRTSE_SHIFT                (1U)
69671 /*! TXRTSE - Transmitter request-to-send enable
69672  *  0b0..The transmitter has no effect on RTS.
69673  *  0b1..When a character is placed into an empty transmit shift register, RTS asserts one bit time before the
69674  *       start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter FIFO and shift
69675  *       register are completely sent, including the last stop bit.
69676  */
69677 #define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
69678 
69679 #define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
69680 #define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
69681 /*! TXRTSPOL - Transmitter request-to-send polarity
69682  *  0b0..Transmitter RTS is active low.
69683  *  0b1..Transmitter RTS is active high.
69684  */
69685 #define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
69686 
69687 #define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
69688 #define LPUART_MODIR_RXRTSE_SHIFT                (3U)
69689 /*! RXRTSE - Receiver request-to-send enable
69690  *  0b0..The receiver has no effect on RTS.
69691  *  0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause
69692  *       the receiver data register to become full. RTS is asserted if the receiver data register is not full and
69693  *       has not detected a start bit that would cause the receiver data register to become full.
69694  */
69695 #define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
69696 
69697 #define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
69698 #define LPUART_MODIR_TXCTSC_SHIFT                (4U)
69699 /*! TXCTSC - Transmit CTS Configuration
69700  *  0b0..CTS input is sampled at the start of each character.
69701  *  0b1..CTS input is sampled when the transmitter is idle.
69702  */
69703 #define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
69704 
69705 #define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
69706 #define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
69707 /*! TXCTSSRC - Transmit CTS Source
69708  *  0b0..CTS input is the CTS_B pin.
69709  *  0b1..CTS input is an internal connection to the receiver address match result.
69710  */
69711 #define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
69712 
69713 #define LPUART_MODIR_RTSWATER_MASK               (0x300U)
69714 #define LPUART_MODIR_RTSWATER_SHIFT              (8U)
69715 /*! RTSWATER - Receive RTS Configuration */
69716 #define LPUART_MODIR_RTSWATER(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
69717 
69718 #define LPUART_MODIR_TNP_MASK                    (0x30000U)
69719 #define LPUART_MODIR_TNP_SHIFT                   (16U)
69720 /*! TNP - Transmitter narrow pulse
69721  *  0b00..1/OSR.
69722  *  0b01..2/OSR.
69723  *  0b10..3/OSR.
69724  *  0b11..4/OSR.
69725  */
69726 #define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
69727 
69728 #define LPUART_MODIR_IREN_MASK                   (0x40000U)
69729 #define LPUART_MODIR_IREN_SHIFT                  (18U)
69730 /*! IREN - Infrared enable
69731  *  0b0..IR disabled.
69732  *  0b1..IR enabled.
69733  */
69734 #define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
69735 /*! @} */
69736 
69737 /*! @name FIFO - LPUART FIFO Register */
69738 /*! @{ */
69739 
69740 #define LPUART_FIFO_RXFIFOSIZE_MASK              (0x7U)
69741 #define LPUART_FIFO_RXFIFOSIZE_SHIFT             (0U)
69742 /*! RXFIFOSIZE - Receive FIFO Buffer Depth
69743  *  0b000..Receive FIFO/Buffer depth = 1 dataword.
69744  *  0b001..Receive FIFO/Buffer depth = 4 datawords.
69745  *  0b010..Receive FIFO/Buffer depth = 8 datawords.
69746  *  0b011..Receive FIFO/Buffer depth = 16 datawords.
69747  *  0b100..Receive FIFO/Buffer depth = 32 datawords.
69748  *  0b101..Receive FIFO/Buffer depth = 64 datawords.
69749  *  0b110..Receive FIFO/Buffer depth = 128 datawords.
69750  *  0b111..Receive FIFO/Buffer depth = 256 datawords.
69751  */
69752 #define LPUART_FIFO_RXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
69753 
69754 #define LPUART_FIFO_RXFE_MASK                    (0x8U)
69755 #define LPUART_FIFO_RXFE_SHIFT                   (3U)
69756 /*! RXFE - Receive FIFO Enable
69757  *  0b0..Receive FIFO is not enabled. Buffer depth is 1.
69758  *  0b1..Receive FIFO is enabled. Buffer depth is indicted by RXFIFOSIZE.
69759  */
69760 #define LPUART_FIFO_RXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
69761 
69762 #define LPUART_FIFO_TXFIFOSIZE_MASK              (0x70U)
69763 #define LPUART_FIFO_TXFIFOSIZE_SHIFT             (4U)
69764 /*! TXFIFOSIZE - Transmit FIFO Buffer Depth
69765  *  0b000..Transmit FIFO/Buffer depth = 1 dataword.
69766  *  0b001..Transmit FIFO/Buffer depth = 4 datawords.
69767  *  0b010..Transmit FIFO/Buffer depth = 8 datawords.
69768  *  0b011..Transmit FIFO/Buffer depth = 16 datawords.
69769  *  0b100..Transmit FIFO/Buffer depth = 32 datawords.
69770  *  0b101..Transmit FIFO/Buffer depth = 64 datawords.
69771  *  0b110..Transmit FIFO/Buffer depth = 128 datawords.
69772  *  0b111..Transmit FIFO/Buffer depth = 256 datawords
69773  */
69774 #define LPUART_FIFO_TXFIFOSIZE(x)                (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
69775 
69776 #define LPUART_FIFO_TXFE_MASK                    (0x80U)
69777 #define LPUART_FIFO_TXFE_SHIFT                   (7U)
69778 /*! TXFE - Transmit FIFO Enable
69779  *  0b0..Transmit FIFO is not enabled. Buffer depth is 1.
69780  *  0b1..Transmit FIFO is enabled. Buffer depth is indicated by TXFIFOSIZE.
69781  */
69782 #define LPUART_FIFO_TXFE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
69783 
69784 #define LPUART_FIFO_RXUFE_MASK                   (0x100U)
69785 #define LPUART_FIFO_RXUFE_SHIFT                  (8U)
69786 /*! RXUFE - Receive FIFO Underflow Interrupt Enable
69787  *  0b0..RXUF flag does not generate an interrupt to the host.
69788  *  0b1..RXUF flag generates an interrupt to the host.
69789  */
69790 #define LPUART_FIFO_RXUFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
69791 
69792 #define LPUART_FIFO_TXOFE_MASK                   (0x200U)
69793 #define LPUART_FIFO_TXOFE_SHIFT                  (9U)
69794 /*! TXOFE - Transmit FIFO Overflow Interrupt Enable
69795  *  0b0..TXOF flag does not generate an interrupt to the host.
69796  *  0b1..TXOF flag generates an interrupt to the host.
69797  */
69798 #define LPUART_FIFO_TXOFE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
69799 
69800 #define LPUART_FIFO_RXIDEN_MASK                  (0x1C00U)
69801 #define LPUART_FIFO_RXIDEN_SHIFT                 (10U)
69802 /*! RXIDEN - Receiver Idle Empty Enable
69803  *  0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle.
69804  *  0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
69805  *  0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
69806  *  0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
69807  *  0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
69808  *  0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
69809  *  0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
69810  *  0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
69811  */
69812 #define LPUART_FIFO_RXIDEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
69813 
69814 #define LPUART_FIFO_RXFLUSH_MASK                 (0x4000U)
69815 #define LPUART_FIFO_RXFLUSH_SHIFT                (14U)
69816 /*! RXFLUSH - Receive FIFO Flush
69817  *  0b0..No flush operation occurs.
69818  *  0b1..All data in the receive FIFO/buffer is cleared out.
69819  */
69820 #define LPUART_FIFO_RXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
69821 
69822 #define LPUART_FIFO_TXFLUSH_MASK                 (0x8000U)
69823 #define LPUART_FIFO_TXFLUSH_SHIFT                (15U)
69824 /*! TXFLUSH - Transmit FIFO Flush
69825  *  0b0..No flush operation occurs.
69826  *  0b1..All data in the transmit FIFO is cleared out.
69827  */
69828 #define LPUART_FIFO_TXFLUSH(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
69829 
69830 #define LPUART_FIFO_RXUF_MASK                    (0x10000U)
69831 #define LPUART_FIFO_RXUF_SHIFT                   (16U)
69832 /*! RXUF - Receiver FIFO Underflow Flag
69833  *  0b0..No receive FIFO underflow has occurred since the last time the flag was cleared.
69834  *  0b1..At least one receive FIFO underflow has occurred since the last time the flag was cleared.
69835  */
69836 #define LPUART_FIFO_RXUF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
69837 
69838 #define LPUART_FIFO_TXOF_MASK                    (0x20000U)
69839 #define LPUART_FIFO_TXOF_SHIFT                   (17U)
69840 /*! TXOF - Transmitter FIFO Overflow Flag
69841  *  0b0..No transmit FIFO overflow has occurred since the last time the flag was cleared.
69842  *  0b1..At least one transmit FIFO overflow has occurred since the last time the flag was cleared.
69843  */
69844 #define LPUART_FIFO_TXOF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
69845 
69846 #define LPUART_FIFO_RXEMPT_MASK                  (0x400000U)
69847 #define LPUART_FIFO_RXEMPT_SHIFT                 (22U)
69848 /*! RXEMPT - Receive FIFO/Buffer Empty
69849  *  0b0..Receive buffer is not empty.
69850  *  0b1..Receive buffer is empty.
69851  */
69852 #define LPUART_FIFO_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
69853 
69854 #define LPUART_FIFO_TXEMPT_MASK                  (0x800000U)
69855 #define LPUART_FIFO_TXEMPT_SHIFT                 (23U)
69856 /*! TXEMPT - Transmit FIFO/Buffer Empty
69857  *  0b0..Transmit buffer is not empty.
69858  *  0b1..Transmit buffer is empty.
69859  */
69860 #define LPUART_FIFO_TXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
69861 /*! @} */
69862 
69863 /*! @name WATER - LPUART Watermark Register */
69864 /*! @{ */
69865 
69866 #define LPUART_WATER_TXWATER_MASK                (0x3U)
69867 #define LPUART_WATER_TXWATER_SHIFT               (0U)
69868 /*! TXWATER - Transmit Watermark */
69869 #define LPUART_WATER_TXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
69870 
69871 #define LPUART_WATER_TXCOUNT_MASK                (0x700U)
69872 #define LPUART_WATER_TXCOUNT_SHIFT               (8U)
69873 /*! TXCOUNT - Transmit Counter */
69874 #define LPUART_WATER_TXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
69875 
69876 #define LPUART_WATER_RXWATER_MASK                (0x30000U)
69877 #define LPUART_WATER_RXWATER_SHIFT               (16U)
69878 /*! RXWATER - Receive Watermark */
69879 #define LPUART_WATER_RXWATER(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
69880 
69881 #define LPUART_WATER_RXCOUNT_MASK                (0x7000000U)
69882 #define LPUART_WATER_RXCOUNT_SHIFT               (24U)
69883 /*! RXCOUNT - Receive Counter */
69884 #define LPUART_WATER_RXCOUNT(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
69885 /*! @} */
69886 
69887 
69888 /*!
69889  * @}
69890  */ /* end of group LPUART_Register_Masks */
69891 
69892 
69893 /* LPUART - Peripheral instance base addresses */
69894 /** Peripheral LPUART1 base address */
69895 #define LPUART1_BASE                             (0x4007C000u)
69896 /** Peripheral LPUART1 base pointer */
69897 #define LPUART1                                  ((LPUART_Type *)LPUART1_BASE)
69898 /** Peripheral LPUART2 base address */
69899 #define LPUART2_BASE                             (0x40080000u)
69900 /** Peripheral LPUART2 base pointer */
69901 #define LPUART2                                  ((LPUART_Type *)LPUART2_BASE)
69902 /** Peripheral LPUART3 base address */
69903 #define LPUART3_BASE                             (0x40084000u)
69904 /** Peripheral LPUART3 base pointer */
69905 #define LPUART3                                  ((LPUART_Type *)LPUART3_BASE)
69906 /** Peripheral LPUART4 base address */
69907 #define LPUART4_BASE                             (0x40088000u)
69908 /** Peripheral LPUART4 base pointer */
69909 #define LPUART4                                  ((LPUART_Type *)LPUART4_BASE)
69910 /** Peripheral LPUART5 base address */
69911 #define LPUART5_BASE                             (0x4008C000u)
69912 /** Peripheral LPUART5 base pointer */
69913 #define LPUART5                                  ((LPUART_Type *)LPUART5_BASE)
69914 /** Peripheral LPUART6 base address */
69915 #define LPUART6_BASE                             (0x40090000u)
69916 /** Peripheral LPUART6 base pointer */
69917 #define LPUART6                                  ((LPUART_Type *)LPUART6_BASE)
69918 /** Peripheral LPUART7 base address */
69919 #define LPUART7_BASE                             (0x40094000u)
69920 /** Peripheral LPUART7 base pointer */
69921 #define LPUART7                                  ((LPUART_Type *)LPUART7_BASE)
69922 /** Peripheral LPUART8 base address */
69923 #define LPUART8_BASE                             (0x40098000u)
69924 /** Peripheral LPUART8 base pointer */
69925 #define LPUART8                                  ((LPUART_Type *)LPUART8_BASE)
69926 /** Peripheral LPUART9 base address */
69927 #define LPUART9_BASE                             (0x4009C000u)
69928 /** Peripheral LPUART9 base pointer */
69929 #define LPUART9                                  ((LPUART_Type *)LPUART9_BASE)
69930 /** Peripheral LPUART10 base address */
69931 #define LPUART10_BASE                            (0x400A0000u)
69932 /** Peripheral LPUART10 base pointer */
69933 #define LPUART10                                 ((LPUART_Type *)LPUART10_BASE)
69934 /** Peripheral LPUART11 base address */
69935 #define LPUART11_BASE                            (0x40C24000u)
69936 /** Peripheral LPUART11 base pointer */
69937 #define LPUART11                                 ((LPUART_Type *)LPUART11_BASE)
69938 /** Peripheral LPUART12 base address */
69939 #define LPUART12_BASE                            (0x40C28000u)
69940 /** Peripheral LPUART12 base pointer */
69941 #define LPUART12                                 ((LPUART_Type *)LPUART12_BASE)
69942 /** Array initializer of LPUART peripheral base addresses */
69943 #define LPUART_BASE_ADDRS                        { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE, LPUART10_BASE, LPUART11_BASE, LPUART12_BASE }
69944 /** Array initializer of LPUART peripheral base pointers */
69945 #define LPUART_BASE_PTRS                         { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LPUART10, LPUART11, LPUART12 }
69946 /** Interrupt vectors for the LPUART peripheral type */
69947 #define LPUART_RX_TX_IRQS                        { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn, LPUART9_IRQn, LPUART10_IRQn, LPUART11_IRQn, LPUART12_IRQn }
69948 
69949 /*!
69950  * @}
69951  */ /* end of group LPUART_Peripheral_Access_Layer */
69952 
69953 
69954 /* ----------------------------------------------------------------------------
69955    -- MCM Peripheral Access Layer
69956    ---------------------------------------------------------------------------- */
69957 
69958 /*!
69959  * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
69960  * @{
69961  */
69962 
69963 /** MCM - Register Layout Typedef */
69964 typedef struct {
69965        uint8_t RESERVED_0[16];
69966   __IO uint32_t ISCR;                              /**< Interrupt Status and Control Register, offset: 0x10 */
69967 } MCM_Type;
69968 
69969 /* ----------------------------------------------------------------------------
69970    -- MCM Register Masks
69971    ---------------------------------------------------------------------------- */
69972 
69973 /*!
69974  * @addtogroup MCM_Register_Masks MCM Register Masks
69975  * @{
69976  */
69977 
69978 /*! @name ISCR - Interrupt Status and Control Register */
69979 /*! @{ */
69980 
69981 #define MCM_ISCR_WABS_MASK                       (0x20U)
69982 #define MCM_ISCR_WABS_SHIFT                      (5U)
69983 /*! WABS - Write Abort on Slave
69984  *  0b0..No abort
69985  *  0b1..Abort
69986  */
69987 #define MCM_ISCR_WABS(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABS_SHIFT)) & MCM_ISCR_WABS_MASK)
69988 
69989 #define MCM_ISCR_WABSO_MASK                      (0x40U)
69990 #define MCM_ISCR_WABSO_SHIFT                     (6U)
69991 /*! WABSO - Write Abort on Slave Overrun
69992  *  0b0..No write abort overrun
69993  *  0b1..Write abort overrun occurred
69994  */
69995 #define MCM_ISCR_WABSO(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABSO_SHIFT)) & MCM_ISCR_WABSO_MASK)
69996 
69997 #define MCM_ISCR_FIOC_MASK                       (0x100U)
69998 #define MCM_ISCR_FIOC_SHIFT                      (8U)
69999 /*! FIOC - FPU Invalid Operation interrupt Status
70000  *  0b0..No interrupt
70001  *  0b1..Interrupt occured
70002  */
70003 #define MCM_ISCR_FIOC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
70004 
70005 #define MCM_ISCR_FDZC_MASK                       (0x200U)
70006 #define MCM_ISCR_FDZC_SHIFT                      (9U)
70007 /*! FDZC - FPU Divide-by-Zero Interrupt Status
70008  *  0b0..No interrupt
70009  *  0b1..Interrupt occured
70010  */
70011 #define MCM_ISCR_FDZC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
70012 
70013 #define MCM_ISCR_FOFC_MASK                       (0x400U)
70014 #define MCM_ISCR_FOFC_SHIFT                      (10U)
70015 /*! FOFC - FPU Overflow interrupt status
70016  *  0b0..No interrupt
70017  *  0b1..Interrupt occured
70018  */
70019 #define MCM_ISCR_FOFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
70020 
70021 #define MCM_ISCR_FUFC_MASK                       (0x800U)
70022 #define MCM_ISCR_FUFC_SHIFT                      (11U)
70023 /*! FUFC - FPU Underflow Interrupt Status
70024  *  0b0..No interrupt
70025  *  0b1..Interrupt occured
70026  */
70027 #define MCM_ISCR_FUFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
70028 
70029 #define MCM_ISCR_FIXC_MASK                       (0x1000U)
70030 #define MCM_ISCR_FIXC_SHIFT                      (12U)
70031 /*! FIXC - FPU Inexact Interrupt Status
70032  *  0b0..No interrupt
70033  *  0b1..Interrupt occured
70034  */
70035 #define MCM_ISCR_FIXC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
70036 
70037 #define MCM_ISCR_FIDC_MASK                       (0x8000U)
70038 #define MCM_ISCR_FIDC_SHIFT                      (15U)
70039 /*! FIDC - FPU Input Denormal Interrupt Status
70040  *  0b0..No interrupt
70041  *  0b1..Interrupt occured
70042  */
70043 #define MCM_ISCR_FIDC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
70044 
70045 #define MCM_ISCR_WABE_MASK                       (0x200000U)
70046 #define MCM_ISCR_WABE_SHIFT                      (21U)
70047 /*! WABE - TCM Write Abort Interrupt enable
70048  *  0b0..Disable interrupt
70049  *  0b1..Enable interrupt
70050  */
70051 #define MCM_ISCR_WABE(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABE_SHIFT)) & MCM_ISCR_WABE_MASK)
70052 
70053 #define MCM_ISCR_FIOCE_MASK                      (0x1000000U)
70054 #define MCM_ISCR_FIOCE_SHIFT                     (24U)
70055 /*! FIOCE - FPU Invalid Operation Interrupt Enable
70056  *  0b0..Disable interrupt
70057  *  0b1..Enable interrupt
70058  */
70059 #define MCM_ISCR_FIOCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
70060 
70061 #define MCM_ISCR_FDZCE_MASK                      (0x2000000U)
70062 #define MCM_ISCR_FDZCE_SHIFT                     (25U)
70063 /*! FDZCE - FPU Divide-by-Zero Interrupt Enable
70064  *  0b0..Disable interrupt
70065  *  0b1..Enable interrupt
70066  */
70067 #define MCM_ISCR_FDZCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
70068 
70069 #define MCM_ISCR_FOFCE_MASK                      (0x4000000U)
70070 #define MCM_ISCR_FOFCE_SHIFT                     (26U)
70071 /*! FOFCE - FPU Overflow Interrupt Enable
70072  *  0b0..Disable interrupt
70073  *  0b1..Enable interrupt
70074  */
70075 #define MCM_ISCR_FOFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
70076 
70077 #define MCM_ISCR_FUFCE_MASK                      (0x8000000U)
70078 #define MCM_ISCR_FUFCE_SHIFT                     (27U)
70079 /*! FUFCE - FPU Underflow Interrupt Enable
70080  *  0b0..Disable interrupt
70081  *  0b1..Enable interrupt
70082  */
70083 #define MCM_ISCR_FUFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
70084 
70085 #define MCM_ISCR_FIXCE_MASK                      (0x10000000U)
70086 #define MCM_ISCR_FIXCE_SHIFT                     (28U)
70087 /*! FIXCE - FPU Inexact Interrupt Enable
70088  *  0b0..Disable interrupt
70089  *  0b1..Enable interrupt
70090  */
70091 #define MCM_ISCR_FIXCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
70092 
70093 #define MCM_ISCR_FIDCE_MASK                      (0x80000000U)
70094 #define MCM_ISCR_FIDCE_SHIFT                     (31U)
70095 /*! FIDCE - FPU Input Denormal Interrupt Enable
70096  *  0b0..Disable interrupt
70097  *  0b1..Enable interrupt
70098  */
70099 #define MCM_ISCR_FIDCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
70100 /*! @} */
70101 
70102 
70103 /*!
70104  * @}
70105  */ /* end of group MCM_Register_Masks */
70106 
70107 
70108 /* MCM - Peripheral instance base addresses */
70109 /** Peripheral CM7_MCM base address */
70110 #define CM7_MCM_BASE                             (0xE0080000u)
70111 /** Peripheral CM7_MCM base pointer */
70112 #define CM7_MCM                                  ((MCM_Type *)CM7_MCM_BASE)
70113 /** Array initializer of MCM peripheral base addresses */
70114 #define MCM_BASE_ADDRS                           { CM7_MCM_BASE }
70115 /** Array initializer of MCM peripheral base pointers */
70116 #define MCM_BASE_PTRS                            { CM7_MCM }
70117 
70118 /*!
70119  * @}
70120  */ /* end of group MCM_Peripheral_Access_Layer */
70121 
70122 
70123 /* ----------------------------------------------------------------------------
70124    -- MECC Peripheral Access Layer
70125    ---------------------------------------------------------------------------- */
70126 
70127 /*!
70128  * @addtogroup MECC_Peripheral_Access_Layer MECC Peripheral Access Layer
70129  * @{
70130  */
70131 
70132 /** MECC - Register Layout Typedef */
70133 typedef struct {
70134   __IO uint32_t ERR_STATUS;                        /**< Error Interrupt Status Register, offset: 0x0 */
70135   __IO uint32_t ERR_STAT_EN;                       /**< Error Interrupt Status Enable Register, offset: 0x4 */
70136   __IO uint32_t ERR_SIG_EN;                        /**< Error Interrupt Enable Register, offset: 0x8 */
70137   __IO uint32_t ERR_DATA_INJ_LOW0;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data, offset: 0xC */
70138   __IO uint32_t ERR_DATA_INJ_HIGH0;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data, offset: 0x10 */
70139   __IO uint32_t ERR_ECC_INJ0;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data, offset: 0x14 */
70140   __IO uint32_t ERR_DATA_INJ_LOW1;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data, offset: 0x18 */
70141   __IO uint32_t ERR_DATA_INJ_HIGH1;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data, offset: 0x1C */
70142   __IO uint32_t ERR_ECC_INJ1;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data, offset: 0x20 */
70143   __IO uint32_t ERR_DATA_INJ_LOW2;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data, offset: 0x24 */
70144   __IO uint32_t ERR_DATA_INJ_HIGH2;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data, offset: 0x28 */
70145   __IO uint32_t ERR_ECC_INJ2;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data, offset: 0x2C */
70146   __IO uint32_t ERR_DATA_INJ_LOW3;                 /**< Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data, offset: 0x30 */
70147   __IO uint32_t ERR_DATA_INJ_HIGH3;                /**< Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data, offset: 0x34 */
70148   __IO uint32_t ERR_ECC_INJ3;                      /**< Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data, offset: 0x38 */
70149   __I  uint32_t SINGLE_ERR_ADDR_ECC0;              /**< Single Error Address And ECC code On OCRAM Bank0, offset: 0x3C */
70150   __I  uint32_t SINGLE_ERR_DATA_LOW0;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x40 */
70151   __I  uint32_t SINGLE_ERR_DATA_HIGH0;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x44 */
70152   __I  uint32_t SINGLE_ERR_POS_LOW0;               /**< LOW Single Error Bit Position On OCRAM Bank0, offset: 0x48 */
70153   __I  uint32_t SINGLE_ERR_POS_HIGH0;              /**< HIGH Single Error Bit Position On OCRAM Bank0, offset: 0x4C */
70154   __I  uint32_t SINGLE_ERR_ADDR_ECC1;              /**< Single Error Address And ECC code On OCRAM Bank1, offset: 0x50 */
70155   __I  uint32_t SINGLE_ERR_DATA_LOW1;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x54 */
70156   __I  uint32_t SINGLE_ERR_DATA_HIGH1;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x58 */
70157   __I  uint32_t SINGLE_ERR_POS_LOW1;               /**< LOW Single Error Bit Position On OCRAM Bank1, offset: 0x5C */
70158   __I  uint32_t SINGLE_ERR_POS_HIGH1;              /**< HIGH Single Error Bit Position On OCRAM Bank1, offset: 0x60 */
70159   __I  uint32_t SINGLE_ERR_ADDR_ECC2;              /**< Single Error Address And ECC code On OCRAM Bank2, offset: 0x64 */
70160   __I  uint32_t SINGLE_ERR_DATA_LOW2;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x68 */
70161   __I  uint32_t SINGLE_ERR_DATA_HIGH2;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x6C */
70162   __I  uint32_t SINGLE_ERR_POS_LOW2;               /**< LOW Single Error Bit Position On OCRAM Bank2, offset: 0x70 */
70163   __I  uint32_t SINGLE_ERR_POS_HIGH2;              /**< HIGH Single Error Bit Position On OCRAM Bank2, offset: 0x74 */
70164   __I  uint32_t SINGLE_ERR_ADDR_ECC3;              /**< Single Error Address And ECC code On OCRAM Bank3, offset: 0x78 */
70165   __I  uint32_t SINGLE_ERR_DATA_LOW3;              /**< LOW 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x7C */
70166   __I  uint32_t SINGLE_ERR_DATA_HIGH3;             /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x80 */
70167   __I  uint32_t SINGLE_ERR_POS_LOW3;               /**< LOW Single Error Bit Position On OCRAM Bank3, offset: 0x84 */
70168   __I  uint32_t SINGLE_ERR_POS_HIGH3;              /**< HIGH Single Error Bit Position On OCRAM Bank3, offset: 0x88 */
70169   __I  uint32_t MULTI_ERR_ADDR_ECC0;               /**< Multiple Error Address And ECC code On OCRAM Bank0, offset: 0x8C */
70170   __I  uint32_t MULTI_ERR_DATA_LOW0;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x90 */
70171   __I  uint32_t MULTI_ERR_DATA_HIGH0;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x94 */
70172   __I  uint32_t MULTI_ERR_ADDR_ECC1;               /**< Multiple Error Address And ECC code On OCRAM Bank1, offset: 0x98 */
70173   __I  uint32_t MULTI_ERR_DATA_LOW1;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0x9C */
70174   __I  uint32_t MULTI_ERR_DATA_HIGH1;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0xA0 */
70175   __I  uint32_t MULTI_ERR_ADDR_ECC2;               /**< Multiple Error Address And ECC code On OCRAM Bank2, offset: 0xA4 */
70176   __I  uint32_t MULTI_ERR_DATA_LOW2;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xA8 */
70177   __I  uint32_t MULTI_ERR_DATA_HIGH2;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xAC */
70178   __I  uint32_t MULTI_ERR_ADDR_ECC3;               /**< Multiple Error Address And ECC code On OCRAM Bank3, offset: 0xB0 */
70179   __I  uint32_t MULTI_ERR_DATA_LOW3;               /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB4 */
70180   __I  uint32_t MULTI_ERR_DATA_HIGH3;              /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB8 */
70181        uint8_t RESERVED_0[68];
70182   __IO uint32_t PIPE_ECC_EN;                       /**< OCRAM Pipeline And ECC Enable, offset: 0x100 */
70183   __I  uint32_t PENDING_STAT;                      /**< Pending Status, offset: 0x104 */
70184 } MECC_Type;
70185 
70186 /* ----------------------------------------------------------------------------
70187    -- MECC Register Masks
70188    ---------------------------------------------------------------------------- */
70189 
70190 /*!
70191  * @addtogroup MECC_Register_Masks MECC Register Masks
70192  * @{
70193  */
70194 
70195 /*! @name ERR_STATUS - Error Interrupt Status Register */
70196 /*! @{ */
70197 
70198 #define MECC_ERR_STATUS_SINGLE_ERR0_MASK         (0x1U)
70199 #define MECC_ERR_STATUS_SINGLE_ERR0_SHIFT        (0U)
70200 /*! SINGLE_ERR0 - Single Bit Error On OCRAM Bank0
70201  *  0b0..Single bit error does not happen on OCRAM bank0.
70202  *  0b1..Single bit error happens on OCRAM bank0.
70203  */
70204 #define MECC_ERR_STATUS_SINGLE_ERR0(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR0_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR0_MASK)
70205 
70206 #define MECC_ERR_STATUS_SINGLE_ERR1_MASK         (0x2U)
70207 #define MECC_ERR_STATUS_SINGLE_ERR1_SHIFT        (1U)
70208 /*! SINGLE_ERR1 - Single Bit Error On OCRAM Bank1
70209  *  0b0..Single bit error does not happen on OCRAM bank1.
70210  *  0b1..Single bit error happens on OCRAM bank1.
70211  */
70212 #define MECC_ERR_STATUS_SINGLE_ERR1(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR1_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR1_MASK)
70213 
70214 #define MECC_ERR_STATUS_SINGLE_ERR2_MASK         (0x4U)
70215 #define MECC_ERR_STATUS_SINGLE_ERR2_SHIFT        (2U)
70216 /*! SINGLE_ERR2 - Single Bit Error On OCRAM Bank2
70217  *  0b0..Single bit error does not happen on OCRAM bank2.
70218  *  0b1..Single bit error happens on OCRAM bank2.
70219  */
70220 #define MECC_ERR_STATUS_SINGLE_ERR2(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR2_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR2_MASK)
70221 
70222 #define MECC_ERR_STATUS_SINGLE_ERR3_MASK         (0x8U)
70223 #define MECC_ERR_STATUS_SINGLE_ERR3_SHIFT        (3U)
70224 /*! SINGLE_ERR3 - Single Bit Error On OCRAM Bank3
70225  *  0b0..Single bit error does not happen on OCRAM bank3.
70226  *  0b1..Single bit error happens on OCRAM bank3.
70227  */
70228 #define MECC_ERR_STATUS_SINGLE_ERR3(x)           (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR3_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR3_MASK)
70229 
70230 #define MECC_ERR_STATUS_MULTI_ERR0_MASK          (0x10U)
70231 #define MECC_ERR_STATUS_MULTI_ERR0_SHIFT         (4U)
70232 /*! MULTI_ERR0 - Multiple Bits Error On OCRAM Bank0
70233  *  0b0..Multiple bits error does not happen on OCRAM bank0.
70234  *  0b1..Multiple bits error happens on OCRAM bank0.
70235  */
70236 #define MECC_ERR_STATUS_MULTI_ERR0(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR0_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR0_MASK)
70237 
70238 #define MECC_ERR_STATUS_MULTI_ERR1_MASK          (0x20U)
70239 #define MECC_ERR_STATUS_MULTI_ERR1_SHIFT         (5U)
70240 /*! MULTI_ERR1 - Multiple Bits Error On OCRAM Bank1
70241  *  0b0..Multiple bits error does not happen on OCRAM bank1.
70242  *  0b1..Multiple bits error happens on OCRAM bank1.
70243  */
70244 #define MECC_ERR_STATUS_MULTI_ERR1(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR1_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR1_MASK)
70245 
70246 #define MECC_ERR_STATUS_MULTI_ERR2_MASK          (0x40U)
70247 #define MECC_ERR_STATUS_MULTI_ERR2_SHIFT         (6U)
70248 /*! MULTI_ERR2 - Multiple Bits Error On OCRAM Bank2
70249  *  0b0..Multiple bits error does not happen on OCRAM bank2.
70250  *  0b1..Multiple bits error happens on OCRAM bank2.
70251  */
70252 #define MECC_ERR_STATUS_MULTI_ERR2(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR2_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR2_MASK)
70253 
70254 #define MECC_ERR_STATUS_MULTI_ERR3_MASK          (0x80U)
70255 #define MECC_ERR_STATUS_MULTI_ERR3_SHIFT         (7U)
70256 /*! MULTI_ERR3 - Multiple Bits Error On OCRAM Bank3
70257  *  0b0..Multiple bits error does not happen on OCRAM bank3.
70258  *  0b1..Multiple bits error happens on OCRAM bank3.
70259  */
70260 #define MECC_ERR_STATUS_MULTI_ERR3(x)            (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR3_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR3_MASK)
70261 
70262 #define MECC_ERR_STATUS_STRB_ERR0_MASK           (0x100U)
70263 #define MECC_ERR_STATUS_STRB_ERR0_SHIFT          (8U)
70264 /*! STRB_ERR0 - AXI Strobe Error On OCRAM Bank0
70265  *  0b0..AXI strobe error does not happen on OCRAM bank0.
70266  *  0b1..AXI strobe error happens on OCRAM bank0.
70267  */
70268 #define MECC_ERR_STATUS_STRB_ERR0(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR0_SHIFT)) & MECC_ERR_STATUS_STRB_ERR0_MASK)
70269 
70270 #define MECC_ERR_STATUS_STRB_ERR1_MASK           (0x200U)
70271 #define MECC_ERR_STATUS_STRB_ERR1_SHIFT          (9U)
70272 /*! STRB_ERR1 - AXI Strobe Error On OCRAM Bank1
70273  *  0b0..AXI strobe error does not happen on OCRAM bank1.
70274  *  0b1..AXI strobe error happens on OCRAM bank1.
70275  */
70276 #define MECC_ERR_STATUS_STRB_ERR1(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR1_SHIFT)) & MECC_ERR_STATUS_STRB_ERR1_MASK)
70277 
70278 #define MECC_ERR_STATUS_STRB_ERR2_MASK           (0x400U)
70279 #define MECC_ERR_STATUS_STRB_ERR2_SHIFT          (10U)
70280 /*! STRB_ERR2 - AXI Strobe Error On OCRAM Bank2
70281  *  0b0..AXI strobe error does not happen on OCRAM bank2.
70282  *  0b1..AXI strobe error happens on OCRAM bank2.
70283  */
70284 #define MECC_ERR_STATUS_STRB_ERR2(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR2_SHIFT)) & MECC_ERR_STATUS_STRB_ERR2_MASK)
70285 
70286 #define MECC_ERR_STATUS_STRB_ERR3_MASK           (0x800U)
70287 #define MECC_ERR_STATUS_STRB_ERR3_SHIFT          (11U)
70288 /*! STRB_ERR3 - AXI Strobe Error On OCRAM Bank3
70289  *  0b0..AXI strobe error does not happen on OCRAM bank3.
70290  *  0b1..AXI strobe error happens on OCRAM bank3.
70291  */
70292 #define MECC_ERR_STATUS_STRB_ERR3(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR3_SHIFT)) & MECC_ERR_STATUS_STRB_ERR3_MASK)
70293 
70294 #define MECC_ERR_STATUS_ADDR_ERR0_MASK           (0x1000U)
70295 #define MECC_ERR_STATUS_ADDR_ERR0_SHIFT          (12U)
70296 /*! ADDR_ERR0 - OCRAM Access Error On Bank0
70297  *  0b0..OCRAM access error does not happen on OCRAM bank0.
70298  *  0b1..OCRAM access error happens on OCRAM bank0.
70299  */
70300 #define MECC_ERR_STATUS_ADDR_ERR0(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR0_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR0_MASK)
70301 
70302 #define MECC_ERR_STATUS_ADDR_ERR1_MASK           (0x2000U)
70303 #define MECC_ERR_STATUS_ADDR_ERR1_SHIFT          (13U)
70304 /*! ADDR_ERR1 - OCRAM Access Error On Bank1
70305  *  0b0..OCRAM access error does not happen on OCRAM bank1.
70306  *  0b1..OCRAM access error happens on OCRAM bank1.
70307  */
70308 #define MECC_ERR_STATUS_ADDR_ERR1(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR1_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR1_MASK)
70309 
70310 #define MECC_ERR_STATUS_ADDR_ERR2_MASK           (0x4000U)
70311 #define MECC_ERR_STATUS_ADDR_ERR2_SHIFT          (14U)
70312 /*! ADDR_ERR2 - OCRAM Access Error On Bank2
70313  *  0b0..OCRAM access error does not happen on OCRAM bank2.
70314  *  0b1..OCRAM access error happens on OCRAM bank2.
70315  */
70316 #define MECC_ERR_STATUS_ADDR_ERR2(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR2_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR2_MASK)
70317 
70318 #define MECC_ERR_STATUS_ADDR_ERR3_MASK           (0x8000U)
70319 #define MECC_ERR_STATUS_ADDR_ERR3_SHIFT          (15U)
70320 /*! ADDR_ERR3 - OCRAM Access Error On Bank3
70321  *  0b0..OCRAM access error does not happen on OCRAM bank3.
70322  *  0b1..OCRAM access error happens on OCRAM bank3.
70323  */
70324 #define MECC_ERR_STATUS_ADDR_ERR3(x)             (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR3_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR3_MASK)
70325 /*! @} */
70326 
70327 /*! @name ERR_STAT_EN - Error Interrupt Status Enable Register */
70328 /*! @{ */
70329 
70330 #define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK (0x1U)
70331 #define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT (0U)
70332 /*! SINGLE_ERR0_STAT_EN - Single Bit Error Status Enable On OCRAM Bank0
70333  *  0b0..Disabled
70334  *  0b1..Enabled
70335  */
70336 #define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK)
70337 
70338 #define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK (0x2U)
70339 #define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT (1U)
70340 /*! SINGLE_ERR1_STAT_EN - Single Bit Error Status Enable On OCRAM Bank1
70341  *  0b0..Disabled
70342  *  0b1..Enabled
70343  */
70344 #define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK)
70345 
70346 #define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK (0x4U)
70347 #define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT (2U)
70348 /*! SINGLE_ERR2_STAT_EN - Single Bit Error Status Enable On OCRAM Bank2
70349  *  0b0..Disabled
70350  *  0b1..Enabled
70351  */
70352 #define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK)
70353 
70354 #define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK (0x8U)
70355 #define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT (3U)
70356 /*! SINGLE_ERR3_STAT_EN - Single Bit Error Status Enable On OCRAM Bank3
70357  *  0b0..Disabled
70358  *  0b1..Enabled
70359  */
70360 #define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK)
70361 
70362 #define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK (0x10U)
70363 #define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT (4U)
70364 /*! MULTI_ERR0_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank0
70365  *  0b0..Disabled
70366  *  0b1..Enabled
70367  */
70368 #define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK)
70369 
70370 #define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK (0x20U)
70371 #define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT (5U)
70372 /*! MULTI_ERR1_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank1
70373  *  0b0..Disabled
70374  *  0b1..Enabled
70375  */
70376 #define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK)
70377 
70378 #define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK (0x40U)
70379 #define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT (6U)
70380 /*! MULTI_ERR2_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank2
70381  *  0b0..Disabled
70382  *  0b1..Enabled
70383  */
70384 #define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK)
70385 
70386 #define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK (0x80U)
70387 #define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT (7U)
70388 /*! MULTI_ERR3_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank3
70389  *  0b0..Disabled
70390  *  0b1..Enabled
70391  */
70392 #define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK)
70393 
70394 #define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK  (0x100U)
70395 #define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT (8U)
70396 /*! STRB_ERR0_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank0
70397  *  0b0..Disabled
70398  *  0b1..Enabled
70399  */
70400 #define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK)
70401 
70402 #define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK  (0x200U)
70403 #define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT (9U)
70404 /*! STRB_ERR1_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank1
70405  *  0b0..Disabled
70406  *  0b1..Enabled
70407  */
70408 #define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK)
70409 
70410 #define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK  (0x400U)
70411 #define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT (10U)
70412 /*! STRB_ERR2_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank2
70413  *  0b0..Disabled
70414  *  0b1..Enabled
70415  */
70416 #define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK)
70417 
70418 #define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK  (0x800U)
70419 #define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT (11U)
70420 /*! STRB_ERR3_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank3
70421  *  0b0..Disabled
70422  *  0b1..Enabled
70423  */
70424 #define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK)
70425 
70426 #define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK  (0x1000U)
70427 #define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT (12U)
70428 /*! ADDR_ERR0_STAT_EN - OCRAM Access Error Status Enable On Bank0
70429  *  0b0..Disabled
70430  *  0b1..Enabled
70431  */
70432 #define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK)
70433 
70434 #define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK  (0x2000U)
70435 #define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT (13U)
70436 /*! ADDR_ERR1_STAT_EN - OCRAM Access Error Status Enable On Bank1
70437  *  0b0..Disabled
70438  *  0b1..Enabled
70439  */
70440 #define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK)
70441 
70442 #define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK  (0x4000U)
70443 #define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT (14U)
70444 /*! ADDR_ERR2_STAT_EN - OCRAM Access Error Status Enable On Bank2
70445  *  0b0..Disabled
70446  *  0b1..Enabled
70447  */
70448 #define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK)
70449 
70450 #define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK  (0x8000U)
70451 #define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT (15U)
70452 /*! ADDR_ERR3_STAT_EN - OCRAM Access Error Status Enable On Bank3
70453  *  0b0..Disabled
70454  *  0b1..Enabled
70455  */
70456 #define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK)
70457 /*! @} */
70458 
70459 /*! @name ERR_SIG_EN - Error Interrupt Enable Register */
70460 /*! @{ */
70461 
70462 #define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK  (0x1U)
70463 #define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT (0U)
70464 /*! SINGLE_ERR0_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank0
70465  *  0b0..Disabled
70466  *  0b1..Enabled
70467  */
70468 #define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK)
70469 
70470 #define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK  (0x2U)
70471 #define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT (1U)
70472 /*! SINGLE_ERR1_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank1
70473  *  0b0..Disabled
70474  *  0b1..Enabled
70475  */
70476 #define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK)
70477 
70478 #define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK  (0x4U)
70479 #define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT (2U)
70480 /*! SINGLE_ERR2_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank2
70481  *  0b0..Disabled
70482  *  0b1..Enabled
70483  */
70484 #define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK)
70485 
70486 #define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK  (0x8U)
70487 #define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT (3U)
70488 /*! SINGLE_ERR3_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank3
70489  *  0b0..Disabled
70490  *  0b1..Enabled
70491  */
70492 #define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK)
70493 
70494 #define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK   (0x10U)
70495 #define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT  (4U)
70496 /*! MULTI_ERR0_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank0
70497  *  0b0..Disabled
70498  *  0b1..Enabled
70499  */
70500 #define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK)
70501 
70502 #define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK   (0x20U)
70503 #define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT  (5U)
70504 /*! MULTI_ERR1_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank1
70505  *  0b0..Disabled
70506  *  0b1..Enabled
70507  */
70508 #define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK)
70509 
70510 #define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK   (0x40U)
70511 #define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT  (6U)
70512 /*! MULTI_ERR2_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank2
70513  *  0b0..Disabled
70514  *  0b1..Enabled
70515  */
70516 #define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK)
70517 
70518 #define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK   (0x80U)
70519 #define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT  (7U)
70520 /*! MULTI_ERR3_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank3
70521  *  0b0..Disabled
70522  *  0b1..Enabled
70523  */
70524 #define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK)
70525 
70526 #define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK    (0x100U)
70527 #define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT   (8U)
70528 /*! STRB_ERR0_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank0
70529  *  0b0..Disabled
70530  *  0b1..Enabled
70531  */
70532 #define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK)
70533 
70534 #define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK    (0x200U)
70535 #define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT   (9U)
70536 /*! STRB_ERR1_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank1
70537  *  0b0..Disabled
70538  *  0b1..Enabled
70539  */
70540 #define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK)
70541 
70542 #define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK    (0x400U)
70543 #define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT   (10U)
70544 /*! STRB_ERR2_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank2
70545  *  0b0..Disabled
70546  *  0b1..Enabled
70547  */
70548 #define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK)
70549 
70550 #define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK    (0x800U)
70551 #define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT   (11U)
70552 /*! STRB_ERR3_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank3
70553  *  0b0..Disabled
70554  *  0b1..Enabled
70555  */
70556 #define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK)
70557 
70558 #define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK    (0x1000U)
70559 #define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT   (12U)
70560 /*! ADDR_ERR0_SIG_EN - OCRAM Access Error Interrupt Enable On Bank0
70561  *  0b0..Disabled
70562  *  0b1..Enabled
70563  */
70564 #define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK)
70565 
70566 #define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK    (0x2000U)
70567 #define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT   (13U)
70568 /*! ADDR_ERR1_SIG_EN - OCRAM Access Error Interrupt Enable On Bank1
70569  *  0b0..Disabled
70570  *  0b1..Enabled
70571  */
70572 #define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK)
70573 
70574 #define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK    (0x4000U)
70575 #define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT   (14U)
70576 /*! ADDR_ERR2_SIG_EN - OCRAM Access Error Interrupt Enable On Bank2
70577  *  0b0..Disabled
70578  *  0b1..Enabled
70579  */
70580 #define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK)
70581 
70582 #define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK    (0x8000U)
70583 #define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT   (15U)
70584 /*! ADDR_ERR3_SIG_EN - OCRAM Access Error Interrupt Enable On Bank3
70585  *  0b0..Disabled
70586  *  0b1..Enabled
70587  */
70588 #define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK)
70589 /*! @} */
70590 
70591 /*! @name ERR_DATA_INJ_LOW0 - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data */
70592 /*! @{ */
70593 
70594 #define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
70595 #define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT (0U)
70596 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data */
70597 #define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK)
70598 /*! @} */
70599 
70600 /*! @name ERR_DATA_INJ_HIGH0 - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data */
70601 /*! @{ */
70602 
70603 #define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
70604 #define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT (0U)
70605 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data */
70606 #define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK)
70607 /*! @} */
70608 
70609 /*! @name ERR_ECC_INJ0 - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data */
70610 /*! @{ */
70611 
70612 #define MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK       (0xFFU)
70613 #define MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT      (0U)
70614 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data */
70615 #define MECC_ERR_ECC_INJ0_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK)
70616 /*! @} */
70617 
70618 /*! @name ERR_DATA_INJ_LOW1 - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data */
70619 /*! @{ */
70620 
70621 #define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
70622 #define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT (0U)
70623 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data */
70624 #define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK)
70625 /*! @} */
70626 
70627 /*! @name ERR_DATA_INJ_HIGH1 - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data */
70628 /*! @{ */
70629 
70630 #define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
70631 #define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT (0U)
70632 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data */
70633 #define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK)
70634 /*! @} */
70635 
70636 /*! @name ERR_ECC_INJ1 - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data */
70637 /*! @{ */
70638 
70639 #define MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK       (0xFFU)
70640 #define MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT      (0U)
70641 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data */
70642 #define MECC_ERR_ECC_INJ1_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK)
70643 /*! @} */
70644 
70645 /*! @name ERR_DATA_INJ_LOW2 - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data */
70646 /*! @{ */
70647 
70648 #define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
70649 #define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT (0U)
70650 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data */
70651 #define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK)
70652 /*! @} */
70653 
70654 /*! @name ERR_DATA_INJ_HIGH2 - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data */
70655 /*! @{ */
70656 
70657 #define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
70658 #define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT (0U)
70659 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data */
70660 #define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK)
70661 /*! @} */
70662 
70663 /*! @name ERR_ECC_INJ2 - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data */
70664 /*! @{ */
70665 
70666 #define MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK       (0xFFU)
70667 #define MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT      (0U)
70668 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data */
70669 #define MECC_ERR_ECC_INJ2_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK)
70670 /*! @} */
70671 
70672 /*! @name ERR_DATA_INJ_LOW3 - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data */
70673 /*! @{ */
70674 
70675 #define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
70676 #define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT (0U)
70677 /*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data */
70678 #define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ(x)   (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK)
70679 /*! @} */
70680 
70681 /*! @name ERR_DATA_INJ_HIGH3 - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data */
70682 /*! @{ */
70683 
70684 #define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
70685 #define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT (0U)
70686 /*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data */
70687 #define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ(x)  (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK)
70688 /*! @} */
70689 
70690 /*! @name ERR_ECC_INJ3 - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data */
70691 /*! @{ */
70692 
70693 #define MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK       (0xFFU)
70694 #define MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT      (0U)
70695 /*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data */
70696 #define MECC_ERR_ECC_INJ3_ERR_ECC_INJ(x)         (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK)
70697 /*! @} */
70698 
70699 /*! @name SINGLE_ERR_ADDR_ECC0 - Single Error Address And ECC code On OCRAM Bank0 */
70700 /*! @{ */
70701 
70702 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK (0xFFU)
70703 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT (0U)
70704 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank0 */
70705 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK)
70706 
70707 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
70708 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT (8U)
70709 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank0 */
70710 #define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK)
70711 /*! @} */
70712 
70713 /*! @name SINGLE_ERR_DATA_LOW0 - LOW 32 Bits Single Error Read Data On OCRAM Bank0 */
70714 /*! @{ */
70715 
70716 #define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
70717 #define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT (0U)
70718 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank0 */
70719 #define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK)
70720 /*! @} */
70721 
70722 /*! @name SINGLE_ERR_DATA_HIGH0 - HIGH 32 Bits Single Error Read Data On OCRAM Bank0 */
70723 /*! @{ */
70724 
70725 #define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
70726 #define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT (0U)
70727 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank0 */
70728 #define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK)
70729 /*! @} */
70730 
70731 /*! @name SINGLE_ERR_POS_LOW0 - LOW Single Error Bit Position On OCRAM Bank0 */
70732 /*! @{ */
70733 
70734 #define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
70735 #define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT (0U)
70736 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank0 */
70737 #define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK)
70738 /*! @} */
70739 
70740 /*! @name SINGLE_ERR_POS_HIGH0 - HIGH Single Error Bit Position On OCRAM Bank0 */
70741 /*! @{ */
70742 
70743 #define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
70744 #define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT (0U)
70745 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank0 */
70746 #define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK)
70747 /*! @} */
70748 
70749 /*! @name SINGLE_ERR_ADDR_ECC1 - Single Error Address And ECC code On OCRAM Bank1 */
70750 /*! @{ */
70751 
70752 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK (0xFFU)
70753 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT (0U)
70754 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank1 */
70755 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK)
70756 
70757 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
70758 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT (8U)
70759 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank1 */
70760 #define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK)
70761 /*! @} */
70762 
70763 /*! @name SINGLE_ERR_DATA_LOW1 - LOW 32 Bits Single Error Read Data On OCRAM Bank1 */
70764 /*! @{ */
70765 
70766 #define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
70767 #define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT (0U)
70768 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank1 */
70769 #define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK)
70770 /*! @} */
70771 
70772 /*! @name SINGLE_ERR_DATA_HIGH1 - HIGH 32 Bits Single Error Read Data On OCRAM Bank1 */
70773 /*! @{ */
70774 
70775 #define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
70776 #define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT (0U)
70777 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank1 */
70778 #define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK)
70779 /*! @} */
70780 
70781 /*! @name SINGLE_ERR_POS_LOW1 - LOW Single Error Bit Position On OCRAM Bank1 */
70782 /*! @{ */
70783 
70784 #define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
70785 #define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT (0U)
70786 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank1 */
70787 #define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK)
70788 /*! @} */
70789 
70790 /*! @name SINGLE_ERR_POS_HIGH1 - HIGH Single Error Bit Position On OCRAM Bank1 */
70791 /*! @{ */
70792 
70793 #define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
70794 #define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT (0U)
70795 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank1 */
70796 #define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK)
70797 /*! @} */
70798 
70799 /*! @name SINGLE_ERR_ADDR_ECC2 - Single Error Address And ECC code On OCRAM Bank2 */
70800 /*! @{ */
70801 
70802 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK (0xFFU)
70803 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT (0U)
70804 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank2 */
70805 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK)
70806 
70807 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
70808 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT (8U)
70809 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank2 */
70810 #define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK)
70811 /*! @} */
70812 
70813 /*! @name SINGLE_ERR_DATA_LOW2 - LOW 32 Bits Single Error Read Data On OCRAM Bank2 */
70814 /*! @{ */
70815 
70816 #define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
70817 #define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT (0U)
70818 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank2 */
70819 #define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK)
70820 /*! @} */
70821 
70822 /*! @name SINGLE_ERR_DATA_HIGH2 - HIGH 32 Bits Single Error Read Data On OCRAM Bank2 */
70823 /*! @{ */
70824 
70825 #define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
70826 #define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT (0U)
70827 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank2 */
70828 #define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK)
70829 /*! @} */
70830 
70831 /*! @name SINGLE_ERR_POS_LOW2 - LOW Single Error Bit Position On OCRAM Bank2 */
70832 /*! @{ */
70833 
70834 #define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
70835 #define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT (0U)
70836 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank2 */
70837 #define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK)
70838 /*! @} */
70839 
70840 /*! @name SINGLE_ERR_POS_HIGH2 - HIGH Single Error Bit Position On OCRAM Bank2 */
70841 /*! @{ */
70842 
70843 #define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
70844 #define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT (0U)
70845 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank2 */
70846 #define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK)
70847 /*! @} */
70848 
70849 /*! @name SINGLE_ERR_ADDR_ECC3 - Single Error Address And ECC code On OCRAM Bank3 */
70850 /*! @{ */
70851 
70852 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK (0xFFU)
70853 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT (0U)
70854 /*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank3 */
70855 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK)
70856 
70857 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
70858 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT (8U)
70859 /*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank3 */
70860 #define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK)
70861 /*! @} */
70862 
70863 /*! @name SINGLE_ERR_DATA_LOW3 - LOW 32 Bits Single Error Read Data On OCRAM Bank3 */
70864 /*! @{ */
70865 
70866 #define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
70867 #define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT (0U)
70868 /*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank3 */
70869 #define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK)
70870 /*! @} */
70871 
70872 /*! @name SINGLE_ERR_DATA_HIGH3 - HIGH 32 Bits Single Error Read Data On OCRAM Bank3 */
70873 /*! @{ */
70874 
70875 #define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
70876 #define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT (0U)
70877 /*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank3 */
70878 #define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK)
70879 /*! @} */
70880 
70881 /*! @name SINGLE_ERR_POS_LOW3 - LOW Single Error Bit Position On OCRAM Bank3 */
70882 /*! @{ */
70883 
70884 #define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
70885 #define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT (0U)
70886 /*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank3 */
70887 #define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK)
70888 /*! @} */
70889 
70890 /*! @name SINGLE_ERR_POS_HIGH3 - HIGH Single Error Bit Position On OCRAM Bank3 */
70891 /*! @{ */
70892 
70893 #define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
70894 #define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT (0U)
70895 /*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank3 */
70896 #define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK)
70897 /*! @} */
70898 
70899 /*! @name MULTI_ERR_ADDR_ECC0 - Multiple Error Address And ECC code On OCRAM Bank0 */
70900 /*! @{ */
70901 
70902 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK (0xFFU)
70903 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT (0U)
70904 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank0 */
70905 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK)
70906 
70907 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
70908 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT (8U)
70909 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank0 */
70910 #define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK)
70911 /*! @} */
70912 
70913 /*! @name MULTI_ERR_DATA_LOW0 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0 */
70914 /*! @{ */
70915 
70916 #define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
70917 #define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT (0U)
70918 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0 */
70919 #define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK)
70920 /*! @} */
70921 
70922 /*! @name MULTI_ERR_DATA_HIGH0 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0 */
70923 /*! @{ */
70924 
70925 #define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
70926 #define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT (0U)
70927 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0 */
70928 #define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK)
70929 /*! @} */
70930 
70931 /*! @name MULTI_ERR_ADDR_ECC1 - Multiple Error Address And ECC code On OCRAM Bank1 */
70932 /*! @{ */
70933 
70934 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK (0xFFU)
70935 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT (0U)
70936 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank1 */
70937 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK)
70938 
70939 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
70940 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT (8U)
70941 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank1 */
70942 #define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK)
70943 /*! @} */
70944 
70945 /*! @name MULTI_ERR_DATA_LOW1 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1 */
70946 /*! @{ */
70947 
70948 #define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
70949 #define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT (0U)
70950 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1 */
70951 #define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK)
70952 /*! @} */
70953 
70954 /*! @name MULTI_ERR_DATA_HIGH1 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1 */
70955 /*! @{ */
70956 
70957 #define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
70958 #define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT (0U)
70959 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1 */
70960 #define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK)
70961 /*! @} */
70962 
70963 /*! @name MULTI_ERR_ADDR_ECC2 - Multiple Error Address And ECC code On OCRAM Bank2 */
70964 /*! @{ */
70965 
70966 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK (0xFFU)
70967 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT (0U)
70968 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank2 */
70969 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK)
70970 
70971 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
70972 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT (8U)
70973 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank2 */
70974 #define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK)
70975 /*! @} */
70976 
70977 /*! @name MULTI_ERR_DATA_LOW2 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2 */
70978 /*! @{ */
70979 
70980 #define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
70981 #define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT (0U)
70982 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2 */
70983 #define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK)
70984 /*! @} */
70985 
70986 /*! @name MULTI_ERR_DATA_HIGH2 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2 */
70987 /*! @{ */
70988 
70989 #define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
70990 #define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT (0U)
70991 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2 */
70992 #define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK)
70993 /*! @} */
70994 
70995 /*! @name MULTI_ERR_ADDR_ECC3 - Multiple Error Address And ECC code On OCRAM Bank3 */
70996 /*! @{ */
70997 
70998 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK (0xFFU)
70999 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT (0U)
71000 /*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank3 */
71001 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK)
71002 
71003 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
71004 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT (8U)
71005 /*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank3 */
71006 #define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK)
71007 /*! @} */
71008 
71009 /*! @name MULTI_ERR_DATA_LOW3 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3 */
71010 /*! @{ */
71011 
71012 #define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
71013 #define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT (0U)
71014 /*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3 */
71015 #define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK)
71016 /*! @} */
71017 
71018 /*! @name MULTI_ERR_DATA_HIGH3 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3 */
71019 /*! @{ */
71020 
71021 #define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
71022 #define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT (0U)
71023 /*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3 */
71024 #define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK)
71025 /*! @} */
71026 
71027 /*! @name PIPE_ECC_EN - OCRAM Pipeline And ECC Enable */
71028 /*! @{ */
71029 
71030 #define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK  (0x1U)
71031 #define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT (0U)
71032 /*! READ_DATA_WAIT_EN - Read Data Wait Enable
71033  *  0b0..Disable.
71034  *  0b1..Enable.
71035  */
71036 #define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK)
71037 
71038 #define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK  (0x2U)
71039 #define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT (1U)
71040 /*! READ_ADDR_PIPE_EN - Read Address Pipeline Enable
71041  *  0b0..Disable.
71042  *  0b1..Enable.
71043  */
71044 #define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(x)    (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK)
71045 
71046 #define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK (0x4U)
71047 #define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT (2U)
71048 /*! WRITE_DATA_PIPE_EN - Write Data Pipeline Enable
71049  *  0b0..Disable.
71050  *  0b1..Enable.
71051  */
71052 #define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK)
71053 
71054 #define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK (0x8U)
71055 #define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT (3U)
71056 /*! WRITE_ADDR_PIPE_EN - Write Address Pipeline Enable
71057  *  0b0..Disable.
71058  *  0b1..Enable.
71059  */
71060 #define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(x)   (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK)
71061 
71062 #define MECC_PIPE_ECC_EN_ECC_EN_MASK             (0x10U)
71063 #define MECC_PIPE_ECC_EN_ECC_EN_SHIFT            (4U)
71064 /*! ECC_EN - ECC Function Enable
71065  *  0b0..Disable.
71066  *  0b1..Enable.
71067  */
71068 #define MECC_PIPE_ECC_EN_ECC_EN(x)               (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_ECC_EN_SHIFT)) & MECC_PIPE_ECC_EN_ECC_EN_MASK)
71069 /*! @} */
71070 
71071 /*! @name PENDING_STAT - Pending Status */
71072 /*! @{ */
71073 
71074 #define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK (0x1U)
71075 #define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT (0U)
71076 /*! READ_DATA_WAIT_PENDING - Read Data Wait Pending
71077  *  0b0..No update pending status for READ_DATA_WAIT_EN.
71078  *  0b1..When READ_DATA_WAIT_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
71079  */
71080 #define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK)
71081 
71082 #define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK (0x2U)
71083 #define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT (1U)
71084 /*! READ_ADDR_PIPE_PENDING - Read Address Pipeline Pending
71085  *  0b0..No update pending status for READ_ADDR_PIPE_EN.
71086  *  0b1..When READ_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
71087  */
71088 #define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK)
71089 
71090 #define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK (0x4U)
71091 #define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT (2U)
71092 /*! WRITE_DATA_PIPE_PENDING - Write Data Pipeline Pending
71093  *  0b0..No update pending status for WRITE_DATA_PIPE_EN.
71094  *  0b1..When WRITE_DATA_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
71095  */
71096 #define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK)
71097 
71098 #define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK (0x8U)
71099 #define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT (3U)
71100 /*! WRITE_ADDR_PIPE_PENDING - Write Address Pipeline Pending
71101  *  0b0..No update pending status for WRITE_ADDR_PIPE_EN.
71102  *  0b1..When WRITE_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
71103  */
71104 #define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK)
71105 /*! @} */
71106 
71107 
71108 /*!
71109  * @}
71110  */ /* end of group MECC_Register_Masks */
71111 
71112 
71113 /* MECC - Peripheral instance base addresses */
71114 /** Peripheral MECC1 base address */
71115 #define MECC1_BASE                               (0x40014000u)
71116 /** Peripheral MECC1 base pointer */
71117 #define MECC1                                    ((MECC_Type *)MECC1_BASE)
71118 /** Peripheral MECC2 base address */
71119 #define MECC2_BASE                               (0x40018000u)
71120 /** Peripheral MECC2 base pointer */
71121 #define MECC2                                    ((MECC_Type *)MECC2_BASE)
71122 /** Array initializer of MECC peripheral base addresses */
71123 #define MECC_BASE_ADDRS                          { 0u, MECC1_BASE, MECC2_BASE }
71124 /** Array initializer of MECC peripheral base pointers */
71125 #define MECC_BASE_PTRS                           { (MECC_Type *)0u, MECC1, MECC2 }
71126 
71127 /*!
71128  * @}
71129  */ /* end of group MECC_Peripheral_Access_Layer */
71130 
71131 
71132 /* ----------------------------------------------------------------------------
71133    -- MIPI_CSI2RX Peripheral Access Layer
71134    ---------------------------------------------------------------------------- */
71135 
71136 /*!
71137  * @addtogroup MIPI_CSI2RX_Peripheral_Access_Layer MIPI_CSI2RX Peripheral Access Layer
71138  * @{
71139  */
71140 
71141 /** MIPI_CSI2RX - Register Layout Typedef */
71142 typedef struct {
71143        uint8_t RESERVED_0[256];
71144   __IO uint32_t CFG_NUM_LANES;                     /**< Lane Configuration Register, offset: 0x100 */
71145   __IO uint32_t CFG_DISABLE_DATA_LANES;            /**< Disable Data Lane Register, offset: 0x104 */
71146   __I  uint32_t BIT_ERR;                           /**< ECC and CRC Error Status Register, offset: 0x108 */
71147   __I  uint32_t IRQ_STATUS;                        /**< IRQ Status Register, offset: 0x10C */
71148   __IO uint32_t IRQ_MASK;                          /**< IRQ Mask Setting Register, offset: 0x110 */
71149   __I  uint32_t ULPS_STATUS;                       /**< Ultra Low Power State (ULPS) Status Register, offset: 0x114 */
71150   __I  uint32_t PPI_ERRSOT_HS;                     /**< ERRSotHS Status Register, offset: 0x118 */
71151   __I  uint32_t PPI_ERRSOTSYNC_HS;                 /**< ErrSotSync HS Status Register, offset: 0x11C */
71152   __I  uint32_t PPI_ERRESC;                        /**< ErrEsc Status Register, offset: 0x120 */
71153   __I  uint32_t PPI_ERRSYNCESC;                    /**< ErrSyncEsc Status Register, offset: 0x124 */
71154   __I  uint32_t PPI_ERRCONTROL;                    /**< ErrControl Status Register, offset: 0x128 */
71155   __IO uint32_t CFG_DISABLE_PAYLOAD_0;             /**< Disable Payload 0 Register, offset: 0x12C */
71156   __IO uint32_t CFG_DISABLE_PAYLOAD_1;             /**< Disable Payload 1 Register, offset: 0x130 */
71157 } MIPI_CSI2RX_Type;
71158 
71159 /* ----------------------------------------------------------------------------
71160    -- MIPI_CSI2RX Register Masks
71161    ---------------------------------------------------------------------------- */
71162 
71163 /*!
71164  * @addtogroup MIPI_CSI2RX_Register_Masks MIPI_CSI2RX Register Masks
71165  * @{
71166  */
71167 
71168 /*! @name CFG_NUM_LANES - Lane Configuration Register */
71169 /*! @{ */
71170 
71171 #define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK (0x3U)
71172 #define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT (0U)
71173 /*! CFG_NUM_LANES - This field is used to set the number of active lanes for receiving data.
71174  *  0b00..1 Lane
71175  *  0b01..2 Lane
71176  *  0b10-0b11..
71177  */
71178 #define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT)) & MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK)
71179 /*! @} */
71180 
71181 /*! @name CFG_DISABLE_DATA_LANES - Disable Data Lane Register */
71182 /*! @{ */
71183 
71184 #define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK (0xFU)
71185 #define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT (0U)
71186 /*! CFG_DISABLE_DATA_LANES - Used to disable data lanes. */
71187 #define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK)
71188 /*! @} */
71189 
71190 /*! @name BIT_ERR - ECC and CRC Error Status Register */
71191 /*! @{ */
71192 
71193 #define MIPI_CSI2RX_BIT_ERR_BIT_ERR_MASK         (0x3FFU)
71194 #define MIPI_CSI2RX_BIT_ERR_BIT_ERR_SHIFT        (0U)
71195 /*! BIT_ERR - This field shows the error status of ECC and CRC */
71196 #define MIPI_CSI2RX_BIT_ERR_BIT_ERR(x)           (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_BIT_ERR_BIT_ERR_SHIFT)) & MIPI_CSI2RX_BIT_ERR_BIT_ERR_MASK)
71197 /*! @} */
71198 
71199 /*! @name IRQ_STATUS - IRQ Status Register */
71200 /*! @{ */
71201 
71202 #define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK   (0x1FFU)
71203 #define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT  (0U)
71204 /*! IRQ_STATUS - This field shows the IRQ status */
71205 #define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT)) & MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK)
71206 /*! @} */
71207 
71208 /*! @name IRQ_MASK - IRQ Mask Setting Register */
71209 /*! @{ */
71210 
71211 #define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK       (0x1FFU)
71212 #define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT      (0U)
71213 /*! IRQ_MASK - This field shows the IRQ Mask setting */
71214 #define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT)) & MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK)
71215 /*! @} */
71216 
71217 /*! @name ULPS_STATUS - Ultra Low Power State (ULPS) Status Register */
71218 /*! @{ */
71219 
71220 #define MIPI_CSI2RX_ULPS_STATUS_STATUS_MASK      (0x3FFU)
71221 #define MIPI_CSI2RX_ULPS_STATUS_STATUS_SHIFT     (0U)
71222 /*! STATUS - This field shows the status of Rx D-PHY ULPS state */
71223 #define MIPI_CSI2RX_ULPS_STATUS_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_ULPS_STATUS_STATUS_SHIFT)) & MIPI_CSI2RX_ULPS_STATUS_STATUS_MASK)
71224 /*! @} */
71225 
71226 /*! @name PPI_ERRSOT_HS - ERRSotHS Status Register */
71227 /*! @{ */
71228 
71229 #define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK    (0xFU)
71230 #define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT   (0U)
71231 /*! STATUS - This field indicates PPI ErrSotHS captured status from D-PHY */
71232 #define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS(x)      (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK)
71233 /*! @} */
71234 
71235 /*! @name PPI_ERRSOTSYNC_HS - ErrSotSync HS Status Register */
71236 /*! @{ */
71237 
71238 #define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK (0xFU)
71239 #define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT (0U)
71240 /*! STATUS - This field indicates PPI ErrSotSync_HS captured status from D-PHY */
71241 #define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS(x)  (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK)
71242 /*! @} */
71243 
71244 /*! @name PPI_ERRESC - ErrEsc Status Register */
71245 /*! @{ */
71246 
71247 #define MIPI_CSI2RX_PPI_ERRESC_STATUS_MASK       (0xFU)
71248 #define MIPI_CSI2RX_PPI_ERRESC_STATUS_SHIFT      (0U)
71249 /*! STATUS - This field indicates PPI ErrEsc captured status from D-PHY */
71250 #define MIPI_CSI2RX_PPI_ERRESC_STATUS(x)         (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRESC_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRESC_STATUS_MASK)
71251 /*! @} */
71252 
71253 /*! @name PPI_ERRSYNCESC - ErrSyncEsc Status Register */
71254 /*! @{ */
71255 
71256 #define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK   (0xFU)
71257 #define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT  (0U)
71258 /*! STATUS - This field indicates PPI ErrSyncEsc captured status from D-PHY */
71259 #define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK)
71260 /*! @} */
71261 
71262 /*! @name PPI_ERRCONTROL - ErrControl Status Register */
71263 /*! @{ */
71264 
71265 #define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_MASK   (0xFU)
71266 #define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT  (0U)
71267 /*! STATUS - This field indicates PPI ErrControl captured status from D-PHY */
71268 #define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS(x)     (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_MASK)
71269 /*! @} */
71270 
71271 /*! @name CFG_DISABLE_PAYLOAD_0 - Disable Payload 0 Register */
71272 /*! @{ */
71273 
71274 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK (0x1U)
71275 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT (0U)
71276 /*! DIS_PAYLOAD_NULL - Null */
71277 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK)
71278 
71279 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK (0x2U)
71280 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT (1U)
71281 /*! DIS_PAYLOAD_BLANK - Blank */
71282 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK)
71283 
71284 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK (0x4U)
71285 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT (2U)
71286 /*! DIS_PAYLOAD_EMBEDDED - Embedded */
71287 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK)
71288 
71289 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK (0x400U)
71290 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT (10U)
71291 /*! DIS_PAYLOAD_YUV420 - Legacy YUV 420 8 bit */
71292 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK)
71293 
71294 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK (0x4000U)
71295 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT (14U)
71296 /*! DIS_PAYLOAD_YUV422_8BIT - YUV422 8 bit */
71297 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK)
71298 
71299 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK (0x10000U)
71300 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT (16U)
71301 /*! DIS_PAYLOAD_RGB444 - RGB444 */
71302 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK)
71303 
71304 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK (0x20000U)
71305 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT (17U)
71306 /*! DIS_PAYLOAD_RGB555 - RGB555 */
71307 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK)
71308 
71309 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK (0x40000U)
71310 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT (18U)
71311 /*! DIS_PAYLOAD_RGB565 - RGB565 */
71312 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK)
71313 
71314 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK (0x80000U)
71315 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT (19U)
71316 /*! DIS_PAYLOAD_RGB666 - RGB666 */
71317 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK)
71318 
71319 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK (0x100000U)
71320 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT (20U)
71321 /*! DIS_PAYLOAD_RGB888 - RGB888 */
71322 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK)
71323 /*! @} */
71324 
71325 /*! @name CFG_DISABLE_PAYLOAD_1 - Disable Payload 1 Register */
71326 /*! @{ */
71327 
71328 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK (0x1U)
71329 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT (0U)
71330 /*! DIS_PAYLOAD_UDEF_30 - User defined type 0x31 */
71331 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK)
71332 
71333 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK (0x2U)
71334 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT (1U)
71335 /*! DIS_PAYLOAD_UDEF_31 - User defined type 0x32 */
71336 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK)
71337 
71338 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK (0x4U)
71339 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT (2U)
71340 /*! DIS_PAYLOAD_UDEF_32 - User defined type 0x33 */
71341 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK)
71342 
71343 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK (0x8U)
71344 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT (3U)
71345 /*! DIS_PAYLOAD_UDEF_33 - User defined type 0x34 */
71346 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK)
71347 
71348 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK (0x10U)
71349 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT (4U)
71350 /*! DIS_PAYLOAD_UDEF_34 - User defined type 0x35 */
71351 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK)
71352 
71353 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK (0x20U)
71354 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT (5U)
71355 /*! DIS_PAYLOAD_UDEF_35 - User defined type 0x35 */
71356 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK)
71357 
71358 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK (0x40U)
71359 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT (6U)
71360 /*! DIS_PAYLOAD_UDEF_36 - User defined type 0x36 */
71361 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK)
71362 
71363 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK (0x80U)
71364 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT (7U)
71365 /*! DIS_PAYLOAD_UDEF_37 - User defined type 0x37 */
71366 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK)
71367 
71368 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK (0x10000U)
71369 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT (16U)
71370 /*! DIS_PAYLOAD_UNSUPPORTED - Unsupported Data Types */
71371 #define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK)
71372 /*! @} */
71373 
71374 
71375 /*!
71376  * @}
71377  */ /* end of group MIPI_CSI2RX_Register_Masks */
71378 
71379 
71380 /* MIPI_CSI2RX - Peripheral instance base addresses */
71381 /** Peripheral MIPI_CSI2RX base address */
71382 #define MIPI_CSI2RX_BASE                         (0x40810000u)
71383 /** Peripheral MIPI_CSI2RX base pointer */
71384 #define MIPI_CSI2RX                              ((MIPI_CSI2RX_Type *)MIPI_CSI2RX_BASE)
71385 /** Array initializer of MIPI_CSI2RX peripheral base addresses */
71386 #define MIPI_CSI2RX_BASE_ADDRS                   { MIPI_CSI2RX_BASE }
71387 /** Array initializer of MIPI_CSI2RX peripheral base pointers */
71388 #define MIPI_CSI2RX_BASE_PTRS                    { MIPI_CSI2RX }
71389 
71390 /*!
71391  * @}
71392  */ /* end of group MIPI_CSI2RX_Peripheral_Access_Layer */
71393 
71394 
71395 /* ----------------------------------------------------------------------------
71396    -- MU Peripheral Access Layer
71397    ---------------------------------------------------------------------------- */
71398 
71399 /*!
71400  * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
71401  * @{
71402  */
71403 
71404 /** MU - Register Layout Typedef */
71405 typedef struct {
71406   __IO uint32_t TR[4];                             /**< Processor A Transmit Register 0..Processor A Transmit Register 3, array offset: 0x0, array step: 0x4 */
71407   __I  uint32_t RR[4];                             /**< Processor A Receive Register 0..Processor A Receive Register 3, array offset: 0x10, array step: 0x4 */
71408   __IO uint32_t SR;                                /**< Processor A Status Register, offset: 0x20 */
71409   __IO uint32_t CR;                                /**< Processor A Control Register, offset: 0x24 */
71410 } MU_Type;
71411 
71412 /* ----------------------------------------------------------------------------
71413    -- MU Register Masks
71414    ---------------------------------------------------------------------------- */
71415 
71416 /*!
71417  * @addtogroup MU_Register_Masks MU Register Masks
71418  * @{
71419  */
71420 
71421 /*! @name TR - Processor A Transmit Register 0..Processor A Transmit Register 3 */
71422 /*! @{ */
71423 
71424 #define MU_TR_DATA_MASK                          (0xFFFFFFFFU)
71425 #define MU_TR_DATA_SHIFT                         (0U)
71426 /*! DATA - TR3 */
71427 #define MU_TR_DATA(x)                            (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK)
71428 /*! @} */
71429 
71430 /* The count of MU_TR */
71431 #define MU_TR_COUNT                              (4U)
71432 
71433 /*! @name RR - Processor A Receive Register 0..Processor A Receive Register 3 */
71434 /*! @{ */
71435 
71436 #define MU_RR_DATA_MASK                          (0xFFFFFFFFU)
71437 #define MU_RR_DATA_SHIFT                         (0U)
71438 /*! DATA - RR3 */
71439 #define MU_RR_DATA(x)                            (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK)
71440 /*! @} */
71441 
71442 /* The count of MU_RR */
71443 #define MU_RR_COUNT                              (4U)
71444 
71445 /*! @name SR - Processor A Status Register */
71446 /*! @{ */
71447 
71448 #define MU_SR_Fn_MASK                            (0x7U)
71449 #define MU_SR_Fn_SHIFT                           (0U)
71450 /*! Fn - Fn
71451  *  0b000..BAFn bit in MUB.CR register is written 0 (default).
71452  *  0b001..BAFn bit in MUB.CR register is written 1.
71453  */
71454 #define MU_SR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
71455 
71456 #define MU_SR_EP_MASK                            (0x10U)
71457 #define MU_SR_EP_SHIFT                           (4U)
71458 /*! EP - EP
71459  *  0b0..The Processor A-side event is not pending (default).
71460  *  0b1..The Processor A-side event is pending.
71461  */
71462 #define MU_SR_EP(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
71463 
71464 #define MU_SR_RS_MASK                            (0x80U)
71465 #define MU_SR_RS_SHIFT                           (7U)
71466 /*! RS - RS
71467  *  0b0..The Processor B-side of the MU is not in reset.
71468  *  0b1..The Processor B-side of the MU is in reset.
71469  */
71470 #define MU_SR_RS(x)                              (((uint32_t)(((uint32_t)(x)) << MU_SR_RS_SHIFT)) & MU_SR_RS_MASK)
71471 
71472 #define MU_SR_FUP_MASK                           (0x100U)
71473 #define MU_SR_FUP_SHIFT                          (8U)
71474 /*! FUP - FUP
71475  *  0b0..No flags updated, initiated by the Processor A, in progress (default)
71476  *  0b1..Processor A initiated flags update, processing
71477  */
71478 #define MU_SR_FUP(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
71479 
71480 #define MU_SR_TEn_MASK                           (0xF00000U)
71481 #define MU_SR_TEn_SHIFT                          (20U)
71482 /*! TEn - TEn
71483  *  0b0000..MUA.TRn register is not empty.
71484  *  0b0001..MUA.TRn register is empty (default).
71485  */
71486 #define MU_SR_TEn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
71487 
71488 #define MU_SR_RFn_MASK                           (0xF000000U)
71489 #define MU_SR_RFn_SHIFT                          (24U)
71490 /*! RFn - RFn
71491  *  0b0000..MUA.RRn register is not full (default).
71492  *  0b0001..MUA.RRn register has received data from MUB.TRn register and is ready to be read by the Processor A.
71493  */
71494 #define MU_SR_RFn(x)                             (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
71495 
71496 #define MU_SR_GIPn_MASK                          (0xF0000000U)
71497 #define MU_SR_GIPn_SHIFT                         (28U)
71498 /*! GIPn - GIPn
71499  *  0b0000..Processor A general purpose interrupt n is not pending. (default)
71500  *  0b0001..Processor A general purpose interrupt n is pending.
71501  */
71502 #define MU_SR_GIPn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)
71503 /*! @} */
71504 
71505 /*! @name CR - Processor A Control Register */
71506 /*! @{ */
71507 
71508 #define MU_CR_Fn_MASK                            (0x7U)
71509 #define MU_CR_Fn_SHIFT                           (0U)
71510 /*! Fn - Fn
71511  *  0b000..N/A. Self clearing bit (default).
71512  *  0b001..Asserts the Processor A MU reset.
71513  */
71514 #define MU_CR_Fn(x)                              (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK)
71515 
71516 #define MU_CR_MUR_MASK                           (0x20U)
71517 #define MU_CR_MUR_SHIFT                          (5U)
71518 /*! MUR - MUR
71519  *  0b0..N/A. Self clearing bit (default).
71520  *  0b1..Asserts the Processor A MU reset.
71521  */
71522 #define MU_CR_MUR(x)                             (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
71523 
71524 #define MU_CR_GIRn_MASK                          (0xF0000U)
71525 #define MU_CR_GIRn_SHIFT                         (16U)
71526 /*! GIRn - GIRn
71527  *  0b0000..Processor A General Interrupt n is not requested to the Processor B (default).
71528  *  0b0001..Processor A General Interrupt n is requested to the Processor B.
71529  */
71530 #define MU_CR_GIRn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
71531 
71532 #define MU_CR_TIEn_MASK                          (0xF00000U)
71533 #define MU_CR_TIEn_SHIFT                         (20U)
71534 /*! TIEn - TIEn
71535  *  0b0000..Disables Processor A Transmit Interrupt n. (default)
71536  *  0b0001..Enables Processor A Transmit Interrupt n.
71537  */
71538 #define MU_CR_TIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
71539 
71540 #define MU_CR_RIEn_MASK                          (0xF000000U)
71541 #define MU_CR_RIEn_SHIFT                         (24U)
71542 /*! RIEn - RIEn
71543  *  0b0000..Disables Processor A Receive Interrupt n. (default)
71544  *  0b0001..Enables Processor A Receive Interrupt n.
71545  */
71546 #define MU_CR_RIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
71547 
71548 #define MU_CR_GIEn_MASK                          (0xF0000000U)
71549 #define MU_CR_GIEn_SHIFT                         (28U)
71550 /*! GIEn - GIEn
71551  *  0b0000..Disables Processor A General Interrupt n. (default)
71552  *  0b0001..Enables Processor A General Interrupt n.
71553  */
71554 #define MU_CR_GIEn(x)                            (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)
71555 /*! @} */
71556 
71557 
71558 /*!
71559  * @}
71560  */ /* end of group MU_Register_Masks */
71561 
71562 
71563 /* MU - Peripheral instance base addresses */
71564 /** Peripheral MUA base address */
71565 #define MUA_BASE                                 (0x40C48000u)
71566 /** Peripheral MUA base pointer */
71567 #define MUA                                      ((MU_Type *)MUA_BASE)
71568 /** Array initializer of MU peripheral base addresses */
71569 #define MU_BASE_ADDRS                            { MUA_BASE }
71570 /** Array initializer of MU peripheral base pointers */
71571 #define MU_BASE_PTRS                             { MUA }
71572 /** Interrupt vectors for the MU peripheral type */
71573 #define MU_IRQS                                  { MUA_IRQn }
71574 
71575 /*!
71576  * @}
71577  */ /* end of group MU_Peripheral_Access_Layer */
71578 
71579 
71580 /* ----------------------------------------------------------------------------
71581    -- OCOTP Peripheral Access Layer
71582    ---------------------------------------------------------------------------- */
71583 
71584 /*!
71585  * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
71586  * @{
71587  */
71588 
71589 /** OCOTP - Register Layout Typedef */
71590 typedef struct {
71591   __IO uint32_t CTRL;                              /**< OTP Controller Control and Status Register, offset: 0x0 */
71592   __IO uint32_t CTRL_SET;                          /**< OTP Controller Control and Status Register, offset: 0x4 */
71593   __IO uint32_t CTRL_CLR;                          /**< OTP Controller Control and Status Register, offset: 0x8 */
71594   __IO uint32_t CTRL_TOG;                          /**< OTP Controller Control and Status Register, offset: 0xC */
71595   __IO uint32_t PDN;                               /**< OTP Controller PDN Register, offset: 0x10 */
71596        uint8_t RESERVED_0[12];
71597   __IO uint32_t DATA;                              /**< OTP Controller Write Data Register, offset: 0x20 */
71598        uint8_t RESERVED_1[12];
71599   __IO uint32_t READ_CTRL;                         /**< OTP Controller Read Control Register, offset: 0x30 */
71600        uint8_t RESERVED_2[92];
71601   __IO uint32_t OUT_STATUS;                        /**< 8K OTP Memory STATUS Register, offset: 0x90 */
71602   __IO uint32_t OUT_STATUS_SET;                    /**< 8K OTP Memory STATUS Register, offset: 0x94 */
71603   __IO uint32_t OUT_STATUS_CLR;                    /**< 8K OTP Memory STATUS Register, offset: 0x98 */
71604   __IO uint32_t OUT_STATUS_TOG;                    /**< 8K OTP Memory STATUS Register, offset: 0x9C */
71605        uint8_t RESERVED_3[16];
71606   __I  uint32_t VERSION;                           /**< OTP Controller Version Register, offset: 0xB0 */
71607        uint8_t RESERVED_4[76];
71608   struct {                                         /* offset: 0x100, array step: 0x10 */
71609     __IO uint32_t READ_FUSE_DATA;                    /**< OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register, array offset: 0x100, array step: 0x10 */
71610          uint8_t RESERVED_0[12];
71611   } READ_FUSE_DATAS[4];
71612   __IO uint32_t SW_LOCK;                           /**< SW_LOCK Register, offset: 0x140 */
71613        uint8_t RESERVED_5[12];
71614   __IO uint32_t BIT_LOCK;                          /**< BIT_LOCK Register, offset: 0x150 */
71615        uint8_t RESERVED_6[1196];
71616   __I  uint32_t LOCKED0;                           /**< OTP Controller Program Locked Status 0 Register, offset: 0x600 */
71617        uint8_t RESERVED_7[12];
71618   __I  uint32_t LOCKED1;                           /**< OTP Controller Program Locked Status 1 Register, offset: 0x610 */
71619        uint8_t RESERVED_8[492];
71620   struct {                                         /* offset: 0x800, array step: 0x10 */
71621     __I  uint32_t FUSE;                              /**< Value of fuse word 0..Value of fuse word 143, array offset: 0x800, array step: 0x10 */
71622          uint8_t RESERVED_0[12];
71623   } FUSEN[144];
71624 } OCOTP_Type;
71625 
71626 /* ----------------------------------------------------------------------------
71627    -- OCOTP Register Masks
71628    ---------------------------------------------------------------------------- */
71629 
71630 /*!
71631  * @addtogroup OCOTP_Register_Masks OCOTP Register Masks
71632  * @{
71633  */
71634 
71635 /*! @name CTRL - OTP Controller Control and Status Register */
71636 /*! @{ */
71637 
71638 #define OCOTP_CTRL_ADDR_MASK                     (0x3FFU)
71639 #define OCOTP_CTRL_ADDR_SHIFT                    (0U)
71640 /*! ADDR - OTP write and read access address register
71641  *  0b0000000000-0b0000001111..Address of one of the 16 supplementary fuse words in OTP memory.
71642  *  0b0000010000-0b0100001111..Address of one of the 256 user fuse words in OTP memory.
71643  */
71644 #define OCOTP_CTRL_ADDR(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)
71645 
71646 #define OCOTP_CTRL_BUSY_MASK                     (0x400U)
71647 #define OCOTP_CTRL_BUSY_SHIFT                    (10U)
71648 /*! BUSY - OTP controller status bit
71649  *  0b0..No write or read access to OTP started.
71650  *  0b1..Write or read access to OTP started.
71651  */
71652 #define OCOTP_CTRL_BUSY(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)
71653 
71654 #define OCOTP_CTRL_ERROR_MASK                    (0x800U)
71655 #define OCOTP_CTRL_ERROR_SHIFT                   (11U)
71656 /*! ERROR - Locked Region Access Error
71657  *  0b0..No error.
71658  *  0b1..Error - access to a locked region requested.
71659  */
71660 #define OCOTP_CTRL_ERROR(x)                      (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)
71661 
71662 #define OCOTP_CTRL_RELOAD_SHADOWS_MASK           (0x1000U)
71663 #define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT          (12U)
71664 /*! RELOAD_SHADOWS - Reload Shadow Registers
71665  *  0b0..Do not force shadow register re-load.
71666  *  0b1..Force shadow register re-load. This bit is cleared automatically after shadow registers are re-loaded.
71667  */
71668 #define OCOTP_CTRL_RELOAD_SHADOWS(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)
71669 
71670 #define OCOTP_CTRL_WORDLOCK_MASK                 (0x8000U)
71671 #define OCOTP_CTRL_WORDLOCK_SHIFT                (15U)
71672 /*! WORDLOCK - Lock fuse word
71673  *  0b0..No change to LOCK bit when programming a word using redundancy
71674  *  0b1..LOCK bit for fuse word will be set after successfully programming a word using redundancy
71675  */
71676 #define OCOTP_CTRL_WORDLOCK(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WORDLOCK_SHIFT)) & OCOTP_CTRL_WORDLOCK_MASK)
71677 
71678 #define OCOTP_CTRL_WR_UNLOCK_MASK                (0xFFFF0000U)
71679 #define OCOTP_CTRL_WR_UNLOCK_SHIFT               (16U)
71680 /*! WR_UNLOCK - Write unlock
71681  *  0b0000000000000000..OTP write access is locked.
71682  *  0b0011111001110111..OTP write access is unlocked.
71683  */
71684 #define OCOTP_CTRL_WR_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)
71685 /*! @} */
71686 
71687 /*! @name CTRL_SET - OTP Controller Control and Status Register */
71688 /*! @{ */
71689 
71690 #define OCOTP_CTRL_SET_ADDR_MASK                 (0x3FFU)
71691 #define OCOTP_CTRL_SET_ADDR_SHIFT                (0U)
71692 /*! ADDR - OTP write and read access address register */
71693 #define OCOTP_CTRL_SET_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)
71694 
71695 #define OCOTP_CTRL_SET_BUSY_MASK                 (0x400U)
71696 #define OCOTP_CTRL_SET_BUSY_SHIFT                (10U)
71697 /*! BUSY - OTP controller status bit */
71698 #define OCOTP_CTRL_SET_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)
71699 
71700 #define OCOTP_CTRL_SET_ERROR_MASK                (0x800U)
71701 #define OCOTP_CTRL_SET_ERROR_SHIFT               (11U)
71702 /*! ERROR - Locked Region Access Error */
71703 #define OCOTP_CTRL_SET_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)
71704 
71705 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK       (0x1000U)
71706 #define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT      (12U)
71707 /*! RELOAD_SHADOWS - Reload Shadow Registers */
71708 #define OCOTP_CTRL_SET_RELOAD_SHADOWS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
71709 
71710 #define OCOTP_CTRL_SET_WORDLOCK_MASK             (0x8000U)
71711 #define OCOTP_CTRL_SET_WORDLOCK_SHIFT            (15U)
71712 /*! WORDLOCK - Lock fuse word */
71713 #define OCOTP_CTRL_SET_WORDLOCK(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WORDLOCK_SHIFT)) & OCOTP_CTRL_SET_WORDLOCK_MASK)
71714 
71715 #define OCOTP_CTRL_SET_WR_UNLOCK_MASK            (0xFFFF0000U)
71716 #define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT           (16U)
71717 /*! WR_UNLOCK - Write unlock */
71718 #define OCOTP_CTRL_SET_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)
71719 /*! @} */
71720 
71721 /*! @name CTRL_CLR - OTP Controller Control and Status Register */
71722 /*! @{ */
71723 
71724 #define OCOTP_CTRL_CLR_ADDR_MASK                 (0x3FFU)
71725 #define OCOTP_CTRL_CLR_ADDR_SHIFT                (0U)
71726 /*! ADDR - OTP write and read access address register */
71727 #define OCOTP_CTRL_CLR_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)
71728 
71729 #define OCOTP_CTRL_CLR_BUSY_MASK                 (0x400U)
71730 #define OCOTP_CTRL_CLR_BUSY_SHIFT                (10U)
71731 /*! BUSY - OTP controller status bit */
71732 #define OCOTP_CTRL_CLR_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)
71733 
71734 #define OCOTP_CTRL_CLR_ERROR_MASK                (0x800U)
71735 #define OCOTP_CTRL_CLR_ERROR_SHIFT               (11U)
71736 /*! ERROR - Locked Region Access Error */
71737 #define OCOTP_CTRL_CLR_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)
71738 
71739 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK       (0x1000U)
71740 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT      (12U)
71741 /*! RELOAD_SHADOWS - Reload Shadow Registers */
71742 #define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
71743 
71744 #define OCOTP_CTRL_CLR_WORDLOCK_MASK             (0x8000U)
71745 #define OCOTP_CTRL_CLR_WORDLOCK_SHIFT            (15U)
71746 /*! WORDLOCK - Lock fuse word */
71747 #define OCOTP_CTRL_CLR_WORDLOCK(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WORDLOCK_SHIFT)) & OCOTP_CTRL_CLR_WORDLOCK_MASK)
71748 
71749 #define OCOTP_CTRL_CLR_WR_UNLOCK_MASK            (0xFFFF0000U)
71750 #define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT           (16U)
71751 /*! WR_UNLOCK - Write unlock */
71752 #define OCOTP_CTRL_CLR_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
71753 /*! @} */
71754 
71755 /*! @name CTRL_TOG - OTP Controller Control and Status Register */
71756 /*! @{ */
71757 
71758 #define OCOTP_CTRL_TOG_ADDR_MASK                 (0x3FFU)
71759 #define OCOTP_CTRL_TOG_ADDR_SHIFT                (0U)
71760 /*! ADDR - OTP write and read access address register */
71761 #define OCOTP_CTRL_TOG_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)
71762 
71763 #define OCOTP_CTRL_TOG_BUSY_MASK                 (0x400U)
71764 #define OCOTP_CTRL_TOG_BUSY_SHIFT                (10U)
71765 /*! BUSY - OTP controller status bit */
71766 #define OCOTP_CTRL_TOG_BUSY(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)
71767 
71768 #define OCOTP_CTRL_TOG_ERROR_MASK                (0x800U)
71769 #define OCOTP_CTRL_TOG_ERROR_SHIFT               (11U)
71770 /*! ERROR - Locked Region Access Error */
71771 #define OCOTP_CTRL_TOG_ERROR(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)
71772 
71773 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK       (0x1000U)
71774 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT      (12U)
71775 /*! RELOAD_SHADOWS - Reload Shadow Registers */
71776 #define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
71777 
71778 #define OCOTP_CTRL_TOG_WORDLOCK_MASK             (0x8000U)
71779 #define OCOTP_CTRL_TOG_WORDLOCK_SHIFT            (15U)
71780 /*! WORDLOCK - Lock fuse word */
71781 #define OCOTP_CTRL_TOG_WORDLOCK(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WORDLOCK_SHIFT)) & OCOTP_CTRL_TOG_WORDLOCK_MASK)
71782 
71783 #define OCOTP_CTRL_TOG_WR_UNLOCK_MASK            (0xFFFF0000U)
71784 #define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT           (16U)
71785 /*! WR_UNLOCK - Write unlock */
71786 #define OCOTP_CTRL_TOG_WR_UNLOCK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
71787 /*! @} */
71788 
71789 /*! @name PDN - OTP Controller PDN Register */
71790 /*! @{ */
71791 
71792 #define OCOTP_PDN_PDN_MASK                       (0x1U)
71793 #define OCOTP_PDN_PDN_SHIFT                      (0U)
71794 /*! PDN - PDN value
71795  *  0b0..OTP memory is not powered
71796  *  0b1..OTP memory is powered
71797  */
71798 #define OCOTP_PDN_PDN(x)                         (((uint32_t)(((uint32_t)(x)) << OCOTP_PDN_PDN_SHIFT)) & OCOTP_PDN_PDN_MASK)
71799 /*! @} */
71800 
71801 /*! @name DATA - OTP Controller Write Data Register */
71802 /*! @{ */
71803 
71804 #define OCOTP_DATA_DATA_MASK                     (0xFFFFFFFFU)
71805 #define OCOTP_DATA_DATA_SHIFT                    (0U)
71806 /*! DATA - Data */
71807 #define OCOTP_DATA_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)
71808 /*! @} */
71809 
71810 /*! @name READ_CTRL - OTP Controller Read Control Register */
71811 /*! @{ */
71812 
71813 #define OCOTP_READ_CTRL_READ_FUSE_MASK           (0x1U)
71814 #define OCOTP_READ_CTRL_READ_FUSE_SHIFT          (0U)
71815 /*! READ_FUSE - Read Fuse
71816  *  0b0..Do not initiate a read from OTP
71817  *  0b1..Initiate a read from OTP
71818  */
71819 #define OCOTP_READ_CTRL_READ_FUSE(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)
71820 
71821 #define OCOTP_READ_CTRL_READ_FUSE_CNTR_MASK      (0x6U)
71822 #define OCOTP_READ_CTRL_READ_FUSE_CNTR_SHIFT     (1U)
71823 /*! READ_FUSE_CNTR - Number of words to read.
71824  *  0b00..1 word
71825  *  0b01..2 words
71826  *  0b10..3 words
71827  *  0b11..4 words
71828  */
71829 #define OCOTP_READ_CTRL_READ_FUSE_CNTR(x)        (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_CNTR_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_CNTR_MASK)
71830 
71831 #define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_MASK (0x8U)
71832 #define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_SHIFT (3U)
71833 /*! READ_FUSE_DONE_INTR_ENA - Enable read-done interrupt
71834  *  0b0..Disable
71835  *  0b1..Enable
71836  */
71837 #define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_MASK)
71838 
71839 #define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_MASK (0x10U)
71840 #define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_SHIFT (4U)
71841 /*! READ_FUSE_ERROR_INTR_ENA - Enable read-error interrupt
71842  *  0b0..Disable
71843  *  0b1..Enable
71844  */
71845 #define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_MASK)
71846 /*! @} */
71847 
71848 /*! @name OUT_STATUS - 8K OTP Memory STATUS Register */
71849 /*! @{ */
71850 
71851 #define OCOTP_OUT_STATUS_SEC_MASK                (0x200U)
71852 #define OCOTP_OUT_STATUS_SEC_SHIFT               (9U)
71853 /*! SEC - Single Error Correct */
71854 #define OCOTP_OUT_STATUS_SEC(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SEC_SHIFT)) & OCOTP_OUT_STATUS_SEC_MASK)
71855 
71856 #define OCOTP_OUT_STATUS_DED_MASK                (0x400U)
71857 #define OCOTP_OUT_STATUS_DED_SHIFT               (10U)
71858 /*! DED - Double error detect */
71859 #define OCOTP_OUT_STATUS_DED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED_SHIFT)) & OCOTP_OUT_STATUS_DED_MASK)
71860 
71861 #define OCOTP_OUT_STATUS_LOCKED_MASK             (0x800U)
71862 #define OCOTP_OUT_STATUS_LOCKED_SHIFT            (11U)
71863 /*! LOCKED - Word Locked */
71864 #define OCOTP_OUT_STATUS_LOCKED(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_LOCKED_MASK)
71865 
71866 #define OCOTP_OUT_STATUS_PROGFAIL_MASK           (0x1000U)
71867 #define OCOTP_OUT_STATUS_PROGFAIL_SHIFT          (12U)
71868 /*! PROGFAIL - Programming failed */
71869 #define OCOTP_OUT_STATUS_PROGFAIL(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_PROGFAIL_MASK)
71870 
71871 #define OCOTP_OUT_STATUS_ACK_MASK                (0x2000U)
71872 #define OCOTP_OUT_STATUS_ACK_SHIFT               (13U)
71873 /*! ACK - Acknowledge */
71874 #define OCOTP_OUT_STATUS_ACK(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_ACK_SHIFT)) & OCOTP_OUT_STATUS_ACK_MASK)
71875 
71876 #define OCOTP_OUT_STATUS_PWOK_MASK               (0x4000U)
71877 #define OCOTP_OUT_STATUS_PWOK_SHIFT              (14U)
71878 /*! PWOK - Power OK */
71879 #define OCOTP_OUT_STATUS_PWOK(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_PWOK_SHIFT)) & OCOTP_OUT_STATUS_PWOK_MASK)
71880 
71881 #define OCOTP_OUT_STATUS_FLAGSTATE_MASK          (0x78000U)
71882 #define OCOTP_OUT_STATUS_FLAGSTATE_SHIFT         (15U)
71883 /*! FLAGSTATE - Flag state */
71884 #define OCOTP_OUT_STATUS_FLAGSTATE(x)            (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_FLAGSTATE_MASK)
71885 
71886 #define OCOTP_OUT_STATUS_SEC_RELOAD_MASK         (0x80000U)
71887 #define OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT        (19U)
71888 /*! SEC_RELOAD - Indicates single error correction occured on reload */
71889 #define OCOTP_OUT_STATUS_SEC_RELOAD(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SEC_RELOAD_MASK)
71890 
71891 #define OCOTP_OUT_STATUS_DED_RELOAD_MASK         (0x100000U)
71892 #define OCOTP_OUT_STATUS_DED_RELOAD_SHIFT        (20U)
71893 /*! DED_RELOAD - Indicates double error detection occured on reload */
71894 #define OCOTP_OUT_STATUS_DED_RELOAD(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_DED_RELOAD_MASK)
71895 
71896 #define OCOTP_OUT_STATUS_CALIBRATED_MASK         (0x200000U)
71897 #define OCOTP_OUT_STATUS_CALIBRATED_SHIFT        (21U)
71898 /*! CALIBRATED - Calibrated status */
71899 #define OCOTP_OUT_STATUS_CALIBRATED(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_CALIBRATED_MASK)
71900 
71901 #define OCOTP_OUT_STATUS_READ_DONE_INTR_MASK     (0x400000U)
71902 #define OCOTP_OUT_STATUS_READ_DONE_INTR_SHIFT    (22U)
71903 /*! READ_DONE_INTR - Read fuse done */
71904 #define OCOTP_OUT_STATUS_READ_DONE_INTR(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_READ_DONE_INTR_MASK)
71905 
71906 #define OCOTP_OUT_STATUS_READ_ERROR_INTR_MASK    (0x800000U)
71907 #define OCOTP_OUT_STATUS_READ_ERROR_INTR_SHIFT   (23U)
71908 /*! READ_ERROR_INTR - Fuse read error
71909  *  0b0..Read operation finished with out any error
71910  *  0b1..Read operation finished with an error
71911  */
71912 #define OCOTP_OUT_STATUS_READ_ERROR_INTR(x)      (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_READ_ERROR_INTR_MASK)
71913 
71914 #define OCOTP_OUT_STATUS_DED0_MASK               (0x1000000U)
71915 #define OCOTP_OUT_STATUS_DED0_SHIFT              (24U)
71916 /*! DED0 - Double error detect */
71917 #define OCOTP_OUT_STATUS_DED0(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED0_SHIFT)) & OCOTP_OUT_STATUS_DED0_MASK)
71918 
71919 #define OCOTP_OUT_STATUS_DED1_MASK               (0x2000000U)
71920 #define OCOTP_OUT_STATUS_DED1_SHIFT              (25U)
71921 /*! DED1 - Double error detect */
71922 #define OCOTP_OUT_STATUS_DED1(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED1_SHIFT)) & OCOTP_OUT_STATUS_DED1_MASK)
71923 
71924 #define OCOTP_OUT_STATUS_DED2_MASK               (0x4000000U)
71925 #define OCOTP_OUT_STATUS_DED2_SHIFT              (26U)
71926 /*! DED2 - Double error detect */
71927 #define OCOTP_OUT_STATUS_DED2(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED2_SHIFT)) & OCOTP_OUT_STATUS_DED2_MASK)
71928 
71929 #define OCOTP_OUT_STATUS_DED3_MASK               (0x8000000U)
71930 #define OCOTP_OUT_STATUS_DED3_SHIFT              (27U)
71931 /*! DED3 - Double error detect */
71932 #define OCOTP_OUT_STATUS_DED3(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED3_SHIFT)) & OCOTP_OUT_STATUS_DED3_MASK)
71933 /*! @} */
71934 
71935 /*! @name OUT_STATUS_SET - 8K OTP Memory STATUS Register */
71936 /*! @{ */
71937 
71938 #define OCOTP_OUT_STATUS_SET_SEC_MASK            (0x200U)
71939 #define OCOTP_OUT_STATUS_SET_SEC_SHIFT           (9U)
71940 /*! SEC - Single Error Correct */
71941 #define OCOTP_OUT_STATUS_SET_SEC(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_SEC_SHIFT)) & OCOTP_OUT_STATUS_SET_SEC_MASK)
71942 
71943 #define OCOTP_OUT_STATUS_SET_DED_MASK            (0x400U)
71944 #define OCOTP_OUT_STATUS_SET_DED_SHIFT           (10U)
71945 /*! DED - Double error detect */
71946 #define OCOTP_OUT_STATUS_SET_DED(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED_SHIFT)) & OCOTP_OUT_STATUS_SET_DED_MASK)
71947 
71948 #define OCOTP_OUT_STATUS_SET_LOCKED_MASK         (0x800U)
71949 #define OCOTP_OUT_STATUS_SET_LOCKED_SHIFT        (11U)
71950 /*! LOCKED - Word Locked */
71951 #define OCOTP_OUT_STATUS_SET_LOCKED(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_SET_LOCKED_MASK)
71952 
71953 #define OCOTP_OUT_STATUS_SET_PROGFAIL_MASK       (0x1000U)
71954 #define OCOTP_OUT_STATUS_SET_PROGFAIL_SHIFT      (12U)
71955 /*! PROGFAIL - Programming failed */
71956 #define OCOTP_OUT_STATUS_SET_PROGFAIL(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_SET_PROGFAIL_MASK)
71957 
71958 #define OCOTP_OUT_STATUS_SET_ACK_MASK            (0x2000U)
71959 #define OCOTP_OUT_STATUS_SET_ACK_SHIFT           (13U)
71960 /*! ACK - Acknowledge */
71961 #define OCOTP_OUT_STATUS_SET_ACK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_ACK_SHIFT)) & OCOTP_OUT_STATUS_SET_ACK_MASK)
71962 
71963 #define OCOTP_OUT_STATUS_SET_PWOK_MASK           (0x4000U)
71964 #define OCOTP_OUT_STATUS_SET_PWOK_SHIFT          (14U)
71965 /*! PWOK - Power OK */
71966 #define OCOTP_OUT_STATUS_SET_PWOK(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_PWOK_SHIFT)) & OCOTP_OUT_STATUS_SET_PWOK_MASK)
71967 
71968 #define OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK      (0x78000U)
71969 #define OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT     (15U)
71970 /*! FLAGSTATE - Flag state */
71971 #define OCOTP_OUT_STATUS_SET_FLAGSTATE(x)        (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK)
71972 
71973 #define OCOTP_OUT_STATUS_SET_SEC_RELOAD_MASK     (0x80000U)
71974 #define OCOTP_OUT_STATUS_SET_SEC_RELOAD_SHIFT    (19U)
71975 /*! SEC_RELOAD - Indicates single error correction occured on reload */
71976 #define OCOTP_OUT_STATUS_SET_SEC_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SET_SEC_RELOAD_MASK)
71977 
71978 #define OCOTP_OUT_STATUS_SET_DED_RELOAD_MASK     (0x100000U)
71979 #define OCOTP_OUT_STATUS_SET_DED_RELOAD_SHIFT    (20U)
71980 /*! DED_RELOAD - Indicates double error detection occured on reload */
71981 #define OCOTP_OUT_STATUS_SET_DED_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SET_DED_RELOAD_MASK)
71982 
71983 #define OCOTP_OUT_STATUS_SET_CALIBRATED_MASK     (0x200000U)
71984 #define OCOTP_OUT_STATUS_SET_CALIBRATED_SHIFT    (21U)
71985 /*! CALIBRATED - Calibrated status */
71986 #define OCOTP_OUT_STATUS_SET_CALIBRATED(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_SET_CALIBRATED_MASK)
71987 
71988 #define OCOTP_OUT_STATUS_SET_READ_DONE_INTR_MASK (0x400000U)
71989 #define OCOTP_OUT_STATUS_SET_READ_DONE_INTR_SHIFT (22U)
71990 /*! READ_DONE_INTR - Read fuse done */
71991 #define OCOTP_OUT_STATUS_SET_READ_DONE_INTR(x)   (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_SET_READ_DONE_INTR_MASK)
71992 
71993 #define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_MASK (0x800000U)
71994 #define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_SHIFT (23U)
71995 /*! READ_ERROR_INTR - Fuse read error */
71996 #define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR(x)  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_MASK)
71997 
71998 #define OCOTP_OUT_STATUS_SET_DED0_MASK           (0x1000000U)
71999 #define OCOTP_OUT_STATUS_SET_DED0_SHIFT          (24U)
72000 /*! DED0 - Double error detect */
72001 #define OCOTP_OUT_STATUS_SET_DED0(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED0_SHIFT)) & OCOTP_OUT_STATUS_SET_DED0_MASK)
72002 
72003 #define OCOTP_OUT_STATUS_SET_DED1_MASK           (0x2000000U)
72004 #define OCOTP_OUT_STATUS_SET_DED1_SHIFT          (25U)
72005 /*! DED1 - Double error detect */
72006 #define OCOTP_OUT_STATUS_SET_DED1(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED1_SHIFT)) & OCOTP_OUT_STATUS_SET_DED1_MASK)
72007 
72008 #define OCOTP_OUT_STATUS_SET_DED2_MASK           (0x4000000U)
72009 #define OCOTP_OUT_STATUS_SET_DED2_SHIFT          (26U)
72010 /*! DED2 - Double error detect */
72011 #define OCOTP_OUT_STATUS_SET_DED2(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED2_SHIFT)) & OCOTP_OUT_STATUS_SET_DED2_MASK)
72012 
72013 #define OCOTP_OUT_STATUS_SET_DED3_MASK           (0x8000000U)
72014 #define OCOTP_OUT_STATUS_SET_DED3_SHIFT          (27U)
72015 /*! DED3 - Double error detect */
72016 #define OCOTP_OUT_STATUS_SET_DED3(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED3_SHIFT)) & OCOTP_OUT_STATUS_SET_DED3_MASK)
72017 /*! @} */
72018 
72019 /*! @name OUT_STATUS_CLR - 8K OTP Memory STATUS Register */
72020 /*! @{ */
72021 
72022 #define OCOTP_OUT_STATUS_CLR_SEC_MASK            (0x200U)
72023 #define OCOTP_OUT_STATUS_CLR_SEC_SHIFT           (9U)
72024 /*! SEC - Single Error Correct */
72025 #define OCOTP_OUT_STATUS_CLR_SEC(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_SEC_SHIFT)) & OCOTP_OUT_STATUS_CLR_SEC_MASK)
72026 
72027 #define OCOTP_OUT_STATUS_CLR_DED_MASK            (0x400U)
72028 #define OCOTP_OUT_STATUS_CLR_DED_SHIFT           (10U)
72029 /*! DED - Double error detect */
72030 #define OCOTP_OUT_STATUS_CLR_DED(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED_MASK)
72031 
72032 #define OCOTP_OUT_STATUS_CLR_LOCKED_MASK         (0x800U)
72033 #define OCOTP_OUT_STATUS_CLR_LOCKED_SHIFT        (11U)
72034 /*! LOCKED - Word Locked */
72035 #define OCOTP_OUT_STATUS_CLR_LOCKED(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_CLR_LOCKED_MASK)
72036 
72037 #define OCOTP_OUT_STATUS_CLR_PROGFAIL_MASK       (0x1000U)
72038 #define OCOTP_OUT_STATUS_CLR_PROGFAIL_SHIFT      (12U)
72039 /*! PROGFAIL - Programming failed */
72040 #define OCOTP_OUT_STATUS_CLR_PROGFAIL(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_CLR_PROGFAIL_MASK)
72041 
72042 #define OCOTP_OUT_STATUS_CLR_ACK_MASK            (0x2000U)
72043 #define OCOTP_OUT_STATUS_CLR_ACK_SHIFT           (13U)
72044 /*! ACK - Acknowledge */
72045 #define OCOTP_OUT_STATUS_CLR_ACK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_ACK_SHIFT)) & OCOTP_OUT_STATUS_CLR_ACK_MASK)
72046 
72047 #define OCOTP_OUT_STATUS_CLR_PWOK_MASK           (0x4000U)
72048 #define OCOTP_OUT_STATUS_CLR_PWOK_SHIFT          (14U)
72049 /*! PWOK - Power OK */
72050 #define OCOTP_OUT_STATUS_CLR_PWOK(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_PWOK_SHIFT)) & OCOTP_OUT_STATUS_CLR_PWOK_MASK)
72051 
72052 #define OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK      (0x78000U)
72053 #define OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT     (15U)
72054 /*! FLAGSTATE - Flag state */
72055 #define OCOTP_OUT_STATUS_CLR_FLAGSTATE(x)        (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK)
72056 
72057 #define OCOTP_OUT_STATUS_CLR_SEC_RELOAD_MASK     (0x80000U)
72058 #define OCOTP_OUT_STATUS_CLR_SEC_RELOAD_SHIFT    (19U)
72059 /*! SEC_RELOAD - Indicates single error correction occured on reload */
72060 #define OCOTP_OUT_STATUS_CLR_SEC_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_CLR_SEC_RELOAD_MASK)
72061 
72062 #define OCOTP_OUT_STATUS_CLR_DED_RELOAD_MASK     (0x100000U)
72063 #define OCOTP_OUT_STATUS_CLR_DED_RELOAD_SHIFT    (20U)
72064 /*! DED_RELOAD - Indicates double error detection occured on reload */
72065 #define OCOTP_OUT_STATUS_CLR_DED_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED_RELOAD_MASK)
72066 
72067 #define OCOTP_OUT_STATUS_CLR_CALIBRATED_MASK     (0x200000U)
72068 #define OCOTP_OUT_STATUS_CLR_CALIBRATED_SHIFT    (21U)
72069 /*! CALIBRATED - Calibrated status */
72070 #define OCOTP_OUT_STATUS_CLR_CALIBRATED(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_CLR_CALIBRATED_MASK)
72071 
72072 #define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_MASK (0x400000U)
72073 #define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_SHIFT (22U)
72074 /*! READ_DONE_INTR - Read fuse done */
72075 #define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR(x)   (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_MASK)
72076 
72077 #define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_MASK (0x800000U)
72078 #define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_SHIFT (23U)
72079 /*! READ_ERROR_INTR - Fuse read error */
72080 #define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR(x)  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_MASK)
72081 
72082 #define OCOTP_OUT_STATUS_CLR_DED0_MASK           (0x1000000U)
72083 #define OCOTP_OUT_STATUS_CLR_DED0_SHIFT          (24U)
72084 /*! DED0 - Double error detect */
72085 #define OCOTP_OUT_STATUS_CLR_DED0(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED0_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED0_MASK)
72086 
72087 #define OCOTP_OUT_STATUS_CLR_DED1_MASK           (0x2000000U)
72088 #define OCOTP_OUT_STATUS_CLR_DED1_SHIFT          (25U)
72089 /*! DED1 - Double error detect */
72090 #define OCOTP_OUT_STATUS_CLR_DED1(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED1_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED1_MASK)
72091 
72092 #define OCOTP_OUT_STATUS_CLR_DED2_MASK           (0x4000000U)
72093 #define OCOTP_OUT_STATUS_CLR_DED2_SHIFT          (26U)
72094 /*! DED2 - Double error detect */
72095 #define OCOTP_OUT_STATUS_CLR_DED2(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED2_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED2_MASK)
72096 
72097 #define OCOTP_OUT_STATUS_CLR_DED3_MASK           (0x8000000U)
72098 #define OCOTP_OUT_STATUS_CLR_DED3_SHIFT          (27U)
72099 /*! DED3 - Double error detect */
72100 #define OCOTP_OUT_STATUS_CLR_DED3(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED3_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED3_MASK)
72101 /*! @} */
72102 
72103 /*! @name OUT_STATUS_TOG - 8K OTP Memory STATUS Register */
72104 /*! @{ */
72105 
72106 #define OCOTP_OUT_STATUS_TOG_SEC_MASK            (0x200U)
72107 #define OCOTP_OUT_STATUS_TOG_SEC_SHIFT           (9U)
72108 /*! SEC - Single Error Correct */
72109 #define OCOTP_OUT_STATUS_TOG_SEC(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_SEC_SHIFT)) & OCOTP_OUT_STATUS_TOG_SEC_MASK)
72110 
72111 #define OCOTP_OUT_STATUS_TOG_DED_MASK            (0x400U)
72112 #define OCOTP_OUT_STATUS_TOG_DED_SHIFT           (10U)
72113 /*! DED - Double error detect */
72114 #define OCOTP_OUT_STATUS_TOG_DED(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED_MASK)
72115 
72116 #define OCOTP_OUT_STATUS_TOG_LOCKED_MASK         (0x800U)
72117 #define OCOTP_OUT_STATUS_TOG_LOCKED_SHIFT        (11U)
72118 /*! LOCKED - Word Locked */
72119 #define OCOTP_OUT_STATUS_TOG_LOCKED(x)           (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_TOG_LOCKED_MASK)
72120 
72121 #define OCOTP_OUT_STATUS_TOG_PROGFAIL_MASK       (0x1000U)
72122 #define OCOTP_OUT_STATUS_TOG_PROGFAIL_SHIFT      (12U)
72123 /*! PROGFAIL - Programming failed */
72124 #define OCOTP_OUT_STATUS_TOG_PROGFAIL(x)         (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_TOG_PROGFAIL_MASK)
72125 
72126 #define OCOTP_OUT_STATUS_TOG_ACK_MASK            (0x2000U)
72127 #define OCOTP_OUT_STATUS_TOG_ACK_SHIFT           (13U)
72128 /*! ACK - Acknowledge */
72129 #define OCOTP_OUT_STATUS_TOG_ACK(x)              (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_ACK_SHIFT)) & OCOTP_OUT_STATUS_TOG_ACK_MASK)
72130 
72131 #define OCOTP_OUT_STATUS_TOG_PWOK_MASK           (0x4000U)
72132 #define OCOTP_OUT_STATUS_TOG_PWOK_SHIFT          (14U)
72133 /*! PWOK - Power OK */
72134 #define OCOTP_OUT_STATUS_TOG_PWOK(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_PWOK_SHIFT)) & OCOTP_OUT_STATUS_TOG_PWOK_MASK)
72135 
72136 #define OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK      (0x78000U)
72137 #define OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT     (15U)
72138 /*! FLAGSTATE - Flag state */
72139 #define OCOTP_OUT_STATUS_TOG_FLAGSTATE(x)        (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK)
72140 
72141 #define OCOTP_OUT_STATUS_TOG_SEC_RELOAD_MASK     (0x80000U)
72142 #define OCOTP_OUT_STATUS_TOG_SEC_RELOAD_SHIFT    (19U)
72143 /*! SEC_RELOAD - Indicates single error correction occured on reload */
72144 #define OCOTP_OUT_STATUS_TOG_SEC_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_TOG_SEC_RELOAD_MASK)
72145 
72146 #define OCOTP_OUT_STATUS_TOG_DED_RELOAD_MASK     (0x100000U)
72147 #define OCOTP_OUT_STATUS_TOG_DED_RELOAD_SHIFT    (20U)
72148 /*! DED_RELOAD - Indicates double error detection occured on reload */
72149 #define OCOTP_OUT_STATUS_TOG_DED_RELOAD(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED_RELOAD_MASK)
72150 
72151 #define OCOTP_OUT_STATUS_TOG_CALIBRATED_MASK     (0x200000U)
72152 #define OCOTP_OUT_STATUS_TOG_CALIBRATED_SHIFT    (21U)
72153 /*! CALIBRATED - Calibrated status */
72154 #define OCOTP_OUT_STATUS_TOG_CALIBRATED(x)       (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_TOG_CALIBRATED_MASK)
72155 
72156 #define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_MASK (0x400000U)
72157 #define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_SHIFT (22U)
72158 /*! READ_DONE_INTR - Read fuse done */
72159 #define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR(x)   (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_MASK)
72160 
72161 #define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_MASK (0x800000U)
72162 #define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_SHIFT (23U)
72163 /*! READ_ERROR_INTR - Fuse read error */
72164 #define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR(x)  (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_MASK)
72165 
72166 #define OCOTP_OUT_STATUS_TOG_DED0_MASK           (0x1000000U)
72167 #define OCOTP_OUT_STATUS_TOG_DED0_SHIFT          (24U)
72168 /*! DED0 - Double error detect */
72169 #define OCOTP_OUT_STATUS_TOG_DED0(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED0_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED0_MASK)
72170 
72171 #define OCOTP_OUT_STATUS_TOG_DED1_MASK           (0x2000000U)
72172 #define OCOTP_OUT_STATUS_TOG_DED1_SHIFT          (25U)
72173 /*! DED1 - Double error detect */
72174 #define OCOTP_OUT_STATUS_TOG_DED1(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED1_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED1_MASK)
72175 
72176 #define OCOTP_OUT_STATUS_TOG_DED2_MASK           (0x4000000U)
72177 #define OCOTP_OUT_STATUS_TOG_DED2_SHIFT          (26U)
72178 /*! DED2 - Double error detect */
72179 #define OCOTP_OUT_STATUS_TOG_DED2(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED2_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED2_MASK)
72180 
72181 #define OCOTP_OUT_STATUS_TOG_DED3_MASK           (0x8000000U)
72182 #define OCOTP_OUT_STATUS_TOG_DED3_SHIFT          (27U)
72183 /*! DED3 - Double error detect */
72184 #define OCOTP_OUT_STATUS_TOG_DED3(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED3_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED3_MASK)
72185 /*! @} */
72186 
72187 /*! @name VERSION - OTP Controller Version Register */
72188 /*! @{ */
72189 
72190 #define OCOTP_VERSION_STEP_MASK                  (0xFFFFU)
72191 #define OCOTP_VERSION_STEP_SHIFT                 (0U)
72192 /*! STEP - RTL Version Stepping */
72193 #define OCOTP_VERSION_STEP(x)                    (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)
72194 
72195 #define OCOTP_VERSION_MINOR_MASK                 (0xFF0000U)
72196 #define OCOTP_VERSION_MINOR_SHIFT                (16U)
72197 /*! MINOR - Minor RTL Version */
72198 #define OCOTP_VERSION_MINOR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)
72199 
72200 #define OCOTP_VERSION_MAJOR_MASK                 (0xFF000000U)
72201 #define OCOTP_VERSION_MAJOR_SHIFT                (24U)
72202 /*! MAJOR - Major RTL Version */
72203 #define OCOTP_VERSION_MAJOR(x)                   (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)
72204 /*! @} */
72205 
72206 /*! @name READ_FUSE_DATA - OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register */
72207 /*! @{ */
72208 
72209 #define OCOTP_READ_FUSE_DATA_DATA_MASK           (0xFFFFFFFFU)
72210 #define OCOTP_READ_FUSE_DATA_DATA_SHIFT          (0U)
72211 /*! DATA - Data */
72212 #define OCOTP_READ_FUSE_DATA_DATA(x)             (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)
72213 /*! @} */
72214 
72215 /* The count of OCOTP_READ_FUSE_DATA */
72216 #define OCOTP_READ_FUSE_DATA_COUNT               (4U)
72217 
72218 /*! @name SW_LOCK - SW_LOCK Register */
72219 /*! @{ */
72220 
72221 #define OCOTP_SW_LOCK_SW_LOCK_MASK               (0xFFFFFFFFU)
72222 #define OCOTP_SW_LOCK_SW_LOCK_SHIFT              (0U)
72223 #define OCOTP_SW_LOCK_SW_LOCK(x)                 (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_LOCK_SW_LOCK_SHIFT)) & OCOTP_SW_LOCK_SW_LOCK_MASK)
72224 /*! @} */
72225 
72226 /*! @name BIT_LOCK - BIT_LOCK Register */
72227 /*! @{ */
72228 
72229 #define OCOTP_BIT_LOCK_BIT_LOCK_MASK             (0xFFFFFFFFU)
72230 #define OCOTP_BIT_LOCK_BIT_LOCK_SHIFT            (0U)
72231 #define OCOTP_BIT_LOCK_BIT_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << OCOTP_BIT_LOCK_BIT_LOCK_SHIFT)) & OCOTP_BIT_LOCK_BIT_LOCK_MASK)
72232 /*! @} */
72233 
72234 /*! @name LOCKED0 - OTP Controller Program Locked Status 0 Register */
72235 /*! @{ */
72236 
72237 #define OCOTP_LOCKED0_LOCKED_MASK                (0xFFFFU)
72238 #define OCOTP_LOCKED0_LOCKED_SHIFT               (0U)
72239 #define OCOTP_LOCKED0_LOCKED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED0_LOCKED_SHIFT)) & OCOTP_LOCKED0_LOCKED_MASK)
72240 /*! @} */
72241 
72242 /*! @name LOCKED1 - OTP Controller Program Locked Status 1 Register */
72243 /*! @{ */
72244 
72245 #define OCOTP_LOCKED1_LOCKED_MASK                (0xFFFFFFFFU)
72246 #define OCOTP_LOCKED1_LOCKED_SHIFT               (0U)
72247 #define OCOTP_LOCKED1_LOCKED(x)                  (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED1_LOCKED_SHIFT)) & OCOTP_LOCKED1_LOCKED_MASK)
72248 /*! @} */
72249 
72250 /*! @name FUSE - Value of fuse word 0..Value of fuse word 143 */
72251 /*! @{ */
72252 
72253 #define OCOTP_FUSE_BITS_MASK                     (0xFFFFFFFFU)
72254 #define OCOTP_FUSE_BITS_SHIFT                    (0U)
72255 /*! BITS - Reflects value of the fuse word */
72256 #define OCOTP_FUSE_BITS(x)                       (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE_BITS_SHIFT)) & OCOTP_FUSE_BITS_MASK)
72257 /*! @} */
72258 
72259 /* The count of OCOTP_FUSE */
72260 #define OCOTP_FUSE_COUNT                         (144U)
72261 
72262 
72263 /*!
72264  * @}
72265  */ /* end of group OCOTP_Register_Masks */
72266 
72267 
72268 /* OCOTP - Peripheral instance base addresses */
72269 /** Peripheral OCOTP base address */
72270 #define OCOTP_BASE                               (0x40CAC000u)
72271 /** Peripheral OCOTP base pointer */
72272 #define OCOTP                                    ((OCOTP_Type *)OCOTP_BASE)
72273 /** Array initializer of OCOTP peripheral base addresses */
72274 #define OCOTP_BASE_ADDRS                         { OCOTP_BASE }
72275 /** Array initializer of OCOTP peripheral base pointers */
72276 #define OCOTP_BASE_PTRS                          { OCOTP }
72277 
72278 /*!
72279  * @}
72280  */ /* end of group OCOTP_Peripheral_Access_Layer */
72281 
72282 
72283 /* ----------------------------------------------------------------------------
72284    -- OSC_RC_400M Peripheral Access Layer
72285    ---------------------------------------------------------------------------- */
72286 
72287 /*!
72288  * @addtogroup OSC_RC_400M_Peripheral_Access_Layer OSC_RC_400M Peripheral Access Layer
72289  * @{
72290  */
72291 
72292 /** OSC_RC_400M - Register Layout Typedef */
72293 typedef struct {
72294   struct {                                         /* offset: 0x0 */
72295     __IO uint32_t RW;                                /**< Control Register 0, offset: 0x0 */
72296     __IO uint32_t SET;                               /**< Control Register 0, offset: 0x4 */
72297     __IO uint32_t CLR;                               /**< Control Register 0, offset: 0x8 */
72298     __IO uint32_t TOG;                               /**< Control Register 0, offset: 0xC */
72299   } CTRL0;
72300   struct {                                         /* offset: 0x10 */
72301     __IO uint32_t RW;                                /**< Control Register 1, offset: 0x10 */
72302     __IO uint32_t SET;                               /**< Control Register 1, offset: 0x14 */
72303     __IO uint32_t CLR;                               /**< Control Register 1, offset: 0x18 */
72304     __IO uint32_t TOG;                               /**< Control Register 1, offset: 0x1C */
72305   } CTRL1;
72306   struct {                                         /* offset: 0x20 */
72307     __IO uint32_t RW;                                /**< Control Register 2, offset: 0x20 */
72308     __IO uint32_t SET;                               /**< Control Register 2, offset: 0x24 */
72309     __IO uint32_t CLR;                               /**< Control Register 2, offset: 0x28 */
72310     __IO uint32_t TOG;                               /**< Control Register 2, offset: 0x2C */
72311   } CTRL2;
72312   struct {                                         /* offset: 0x30 */
72313     __IO uint32_t RW;                                /**< Control Register 3, offset: 0x30 */
72314     __IO uint32_t SET;                               /**< Control Register 3, offset: 0x34 */
72315     __IO uint32_t CLR;                               /**< Control Register 3, offset: 0x38 */
72316     __IO uint32_t TOG;                               /**< Control Register 3, offset: 0x3C */
72317   } CTRL3;
72318        uint8_t RESERVED_0[16];
72319   struct {                                         /* offset: 0x50 */
72320     __I  uint32_t RW;                                /**< Status Register 0, offset: 0x50 */
72321     __I  uint32_t SET;                               /**< Status Register 0, offset: 0x54 */
72322     __I  uint32_t CLR;                               /**< Status Register 0, offset: 0x58 */
72323     __I  uint32_t TOG;                               /**< Status Register 0, offset: 0x5C */
72324   } STAT0;
72325   struct {                                         /* offset: 0x60 */
72326     __I  uint32_t RW;                                /**< Status Register 1, offset: 0x60 */
72327     __I  uint32_t SET;                               /**< Status Register 1, offset: 0x64 */
72328     __I  uint32_t CLR;                               /**< Status Register 1, offset: 0x68 */
72329     __I  uint32_t TOG;                               /**< Status Register 1, offset: 0x6C */
72330   } STAT1;
72331   struct {                                         /* offset: 0x70 */
72332     __I  uint32_t RW;                                /**< Status Register 2, offset: 0x70 */
72333     __I  uint32_t SET;                               /**< Status Register 2, offset: 0x74 */
72334     __I  uint32_t CLR;                               /**< Status Register 2, offset: 0x78 */
72335     __I  uint32_t TOG;                               /**< Status Register 2, offset: 0x7C */
72336   } STAT2;
72337 } OSC_RC_400M_Type;
72338 
72339 /* ----------------------------------------------------------------------------
72340    -- OSC_RC_400M Register Masks
72341    ---------------------------------------------------------------------------- */
72342 
72343 /*!
72344  * @addtogroup OSC_RC_400M_Register_Masks OSC_RC_400M Register Masks
72345  * @{
72346  */
72347 
72348 /*! @name CTRL0 - Control Register 0 */
72349 /*! @{ */
72350 
72351 #define OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK       (0x3F000000U)
72352 #define OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT      (24U)
72353 /*! REF_CLK_DIV - Divide value for ref_clk to generate slow_clk (used inside this IP) */
72354 #define OSC_RC_400M_CTRL0_REF_CLK_DIV(x)         (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT)) & OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK)
72355 /*! @} */
72356 
72357 /*! @name CTRL1 - Control Register 1 */
72358 /*! @{ */
72359 
72360 #define OSC_RC_400M_CTRL1_HYST_MINUS_MASK        (0xFU)
72361 #define OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT       (0U)
72362 /*! HYST_MINUS - Negative hysteresis value for the tuned clock */
72363 #define OSC_RC_400M_CTRL1_HYST_MINUS(x)          (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_MINUS_MASK)
72364 
72365 #define OSC_RC_400M_CTRL1_HYST_PLUS_MASK         (0xF00U)
72366 #define OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT        (8U)
72367 /*! HYST_PLUS - Positive hysteresis value for the tuned clock */
72368 #define OSC_RC_400M_CTRL1_HYST_PLUS(x)           (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_PLUS_MASK)
72369 
72370 #define OSC_RC_400M_CTRL1_TARGET_COUNT_MASK      (0xFFFF0000U)
72371 #define OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT     (16U)
72372 /*! TARGET_COUNT - Target count for the fast clock */
72373 #define OSC_RC_400M_CTRL1_TARGET_COUNT(x)        (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT)) & OSC_RC_400M_CTRL1_TARGET_COUNT_MASK)
72374 /*! @} */
72375 
72376 /*! @name CTRL2 - Control Register 2 */
72377 /*! @{ */
72378 
72379 #define OSC_RC_400M_CTRL2_TUNE_BYP_MASK          (0x400U)
72380 #define OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT         (10U)
72381 /*! TUNE_BYP - Bypass the tuning logic
72382  *  0b0..Use the output of tuning logic to run the oscillator
72383  *  0b1..Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator
72384  */
72385 #define OSC_RC_400M_CTRL2_TUNE_BYP(x)            (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_BYP_MASK)
72386 
72387 #define OSC_RC_400M_CTRL2_TUNE_EN_MASK           (0x1000U)
72388 #define OSC_RC_400M_CTRL2_TUNE_EN_SHIFT          (12U)
72389 /*! TUNE_EN - Freeze/Unfreeze the tuning value
72390  *  0b0..Freezes the tuning at the current tuned value. Oscillator runs at the frozen tuning value
72391  *  0b1..Unfreezes and continues the tuning operation
72392  */
72393 #define OSC_RC_400M_CTRL2_TUNE_EN(x)             (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_EN_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_EN_MASK)
72394 
72395 #define OSC_RC_400M_CTRL2_TUNE_START_MASK        (0x4000U)
72396 #define OSC_RC_400M_CTRL2_TUNE_START_SHIFT       (14U)
72397 /*! TUNE_START - Start/Stop tuning
72398  *  0b0..Stop tuning and reset the tuning logic. Oscillator runs using programmed OSC_TUNE_VAL
72399  *  0b1..Start tuning
72400  */
72401 #define OSC_RC_400M_CTRL2_TUNE_START(x)          (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_START_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_START_MASK)
72402 
72403 #define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK      (0xFF000000U)
72404 #define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT     (24U)
72405 /*! OSC_TUNE_VAL - Program the oscillator frequency */
72406 #define OSC_RC_400M_CTRL2_OSC_TUNE_VAL(x)        (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK)
72407 /*! @} */
72408 
72409 /*! @name CTRL3 - Control Register 3 */
72410 /*! @{ */
72411 
72412 #define OSC_RC_400M_CTRL3_CLR_ERR_MASK           (0x1U)
72413 #define OSC_RC_400M_CTRL3_CLR_ERR_SHIFT          (0U)
72414 /*! CLR_ERR - Clear the error flag CLK1M_ERR
72415  *  0b0..No effect
72416  *  0b1..Clears the error flag CLK1M_ERR in status register STAT0
72417  */
72418 #define OSC_RC_400M_CTRL3_CLR_ERR(x)             (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_CLR_ERR_SHIFT)) & OSC_RC_400M_CTRL3_CLR_ERR_MASK)
72419 
72420 #define OSC_RC_400M_CTRL3_EN_1M_CLK_MASK         (0x100U)
72421 #define OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT        (8U)
72422 /*! EN_1M_CLK - Enable 1MHz output Clock
72423  *  0b0..Enable the output (clk_1m_out)
72424  *  0b1..Disable the output (clk_1m_out)
72425  */
72426 #define OSC_RC_400M_CTRL3_EN_1M_CLK(x)           (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_EN_1M_CLK_MASK)
72427 
72428 #define OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK        (0x400U)
72429 #define OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT       (10U)
72430 /*! MUX_1M_CLK - Select free/locked 1MHz output
72431  *  0b0..Select free-running 1MHz to be put out on clk_1m_out
72432  *  0b1..Select locked 1MHz to be put out on clk_1m_out
72433  */
72434 #define OSC_RC_400M_CTRL3_MUX_1M_CLK(x)          (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK)
72435 
72436 #define OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK      (0xFFFF0000U)
72437 #define OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT     (16U)
72438 /*! COUNT_1M_CLK - Count for the locked clk_1m_out */
72439 #define OSC_RC_400M_CTRL3_COUNT_1M_CLK(x)        (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK)
72440 /*! @} */
72441 
72442 /*! @name STAT0 - Status Register 0 */
72443 /*! @{ */
72444 
72445 #define OSC_RC_400M_STAT0_CLK1M_ERR_MASK         (0x1U)
72446 #define OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT        (0U)
72447 /*! CLK1M_ERR - Error flag for clk_1m_locked
72448  *  0b0..No effect
72449  *  0b1..The count value has been reached within one divided ref_clk period
72450  */
72451 #define OSC_RC_400M_STAT0_CLK1M_ERR(x)           (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT)) & OSC_RC_400M_STAT0_CLK1M_ERR_MASK)
72452 /*! @} */
72453 
72454 /*! @name STAT1 - Status Register 1 */
72455 /*! @{ */
72456 
72457 #define OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK    (0xFFFF0000U)
72458 #define OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT   (16U)
72459 /*! CURR_COUNT_VAL - Current count for the fast clock */
72460 #define OSC_RC_400M_STAT1_CURR_COUNT_VAL(x)      (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT)) & OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK)
72461 /*! @} */
72462 
72463 /*! @name STAT2 - Status Register 2 */
72464 /*! @{ */
72465 
72466 #define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U)
72467 #define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U)
72468 /*! CURR_OSC_TUNE_VAL - Current tuning value used by oscillator */
72469 #define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL(x)   (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK)
72470 /*! @} */
72471 
72472 
72473 /*!
72474  * @}
72475  */ /* end of group OSC_RC_400M_Register_Masks */
72476 
72477 
72478 /* OSC_RC_400M - Peripheral instance base addresses */
72479 /** Peripheral OSC_RC_400M base address */
72480 #define OSC_RC_400M_BASE                         (0u)
72481 /** Peripheral OSC_RC_400M base pointer */
72482 #define OSC_RC_400M                              ((OSC_RC_400M_Type *)OSC_RC_400M_BASE)
72483 /** Array initializer of OSC_RC_400M peripheral base addresses */
72484 #define OSC_RC_400M_BASE_ADDRS                   { OSC_RC_400M_BASE }
72485 /** Array initializer of OSC_RC_400M peripheral base pointers */
72486 #define OSC_RC_400M_BASE_PTRS                    { OSC_RC_400M }
72487 
72488 /*!
72489  * @}
72490  */ /* end of group OSC_RC_400M_Peripheral_Access_Layer */
72491 
72492 
72493 /* ----------------------------------------------------------------------------
72494    -- OTFAD Peripheral Access Layer
72495    ---------------------------------------------------------------------------- */
72496 
72497 /*!
72498  * @addtogroup OTFAD_Peripheral_Access_Layer OTFAD Peripheral Access Layer
72499  * @{
72500  */
72501 
72502 /** OTFAD - Register Layout Typedef */
72503 typedef struct {
72504        uint8_t RESERVED_0[3072];
72505   __IO uint32_t CR;                                /**< Control Register, offset: 0xC00 */
72506   __IO uint32_t SR;                                /**< Status Register, offset: 0xC04 */
72507        uint8_t RESERVED_1[248];
72508   struct {                                         /* offset: 0xD00, array step: 0x40 */
72509     __IO uint32_t KEY[4];                            /**< AES Key Word, array offset: 0xD00, array step: index*0x40, index2*0x4 */
72510     __IO uint32_t CTR[2];                            /**< AES Counter Word, array offset: 0xD10, array step: index*0x40, index2*0x4 */
72511     __IO uint32_t RGD_W0;                            /**< AES Region Descriptor Word0, array offset: 0xD18, array step: 0x40 */
72512     __IO uint32_t RGD_W1;                            /**< AES Region Descriptor Word1, array offset: 0xD1C, array step: 0x40 */
72513          uint8_t RESERVED_0[32];
72514   } CTX[4];
72515 } OTFAD_Type;
72516 
72517 /* ----------------------------------------------------------------------------
72518    -- OTFAD Register Masks
72519    ---------------------------------------------------------------------------- */
72520 
72521 /*!
72522  * @addtogroup OTFAD_Register_Masks OTFAD Register Masks
72523  * @{
72524  */
72525 
72526 /*! @name CR - Control Register */
72527 /*! @{ */
72528 
72529 #define OTFAD_CR_FERR_MASK                       (0x2U)
72530 #define OTFAD_CR_FERR_SHIFT                      (1U)
72531 /*! FERR - Force Error
72532  *  0b0..No effect on the SR[KBERE] indicator.
72533  *  0b1..SR[KBERR] is immediately set after a write with this data bit set.
72534  */
72535 #define OTFAD_CR_FERR(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FERR_SHIFT)) & OTFAD_CR_FERR_MASK)
72536 
72537 #define OTFAD_CR_FLDM_MASK                       (0x8U)
72538 #define OTFAD_CR_FLDM_SHIFT                      (3U)
72539 /*! FLDM - Force Logically Disabled Mode
72540  *  0b0..No effect on the operating mode.
72541  *  0b1..Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode.
72542  */
72543 #define OTFAD_CR_FLDM(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)
72544 
72545 #define OTFAD_CR_KBSE_MASK                       (0x10U)
72546 #define OTFAD_CR_KBSE_SHIFT                      (4U)
72547 /*! KBSE - Key Blob Scramble Enable
72548  *  0b0..Key blob KEK scrambling is disabled.
72549  *  0b1..Key blob KEK scrambling is enabled.
72550  */
72551 #define OTFAD_CR_KBSE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBSE_SHIFT)) & OTFAD_CR_KBSE_MASK)
72552 
72553 #define OTFAD_CR_KBPE_MASK                       (0x20U)
72554 #define OTFAD_CR_KBPE_SHIFT                      (5U)
72555 /*! KBPE - Key Blob Processing Enable
72556  *  0b0..Key blob processing is disabled.
72557  *  0b1..Key blob processing is enabled.
72558  */
72559 #define OTFAD_CR_KBPE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBPE_SHIFT)) & OTFAD_CR_KBPE_MASK)
72560 
72561 #define OTFAD_CR_RRAE_MASK                       (0x80U)
72562 #define OTFAD_CR_RRAE_SHIFT                      (7U)
72563 /*! RRAE - Restricted Register Access Enable
72564  *  0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
72565  *  0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
72566  */
72567 #define OTFAD_CR_RRAE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)
72568 
72569 #define OTFAD_CR_SKBP_MASK                       (0x40000000U)
72570 #define OTFAD_CR_SKBP_SHIFT                      (30U)
72571 /*! SKBP - Start key blob processing
72572  *  0b0..Key blob processing is not initiated.
72573  *  0b1..Properly-enabled key blob processing is initiated.
72574  */
72575 #define OTFAD_CR_SKBP(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_SKBP_SHIFT)) & OTFAD_CR_SKBP_MASK)
72576 
72577 #define OTFAD_CR_GE_MASK                         (0x80000000U)
72578 #define OTFAD_CR_GE_SHIFT                        (31U)
72579 /*! GE - Global OTFAD Enable
72580  *  0b0..OTFAD has decryption disabled. All data fetched by the FlexSPI bypasses OTFAD processing.
72581  *  0b1..OTFAD has decryption enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.
72582  */
72583 #define OTFAD_CR_GE(x)                           (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)
72584 /*! @} */
72585 
72586 /*! @name SR - Status Register */
72587 /*! @{ */
72588 
72589 #define OTFAD_SR_KBERR_MASK                      (0x1U)
72590 #define OTFAD_SR_KBERR_SHIFT                     (0U)
72591 /*! KBERR - Key Blob Error
72592  *  0b0..No key blob error detected.
72593  *  0b1..One or more key blob errors has been detected.
72594  */
72595 #define OTFAD_SR_KBERR(x)                        (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBERR_SHIFT)) & OTFAD_SR_KBERR_MASK)
72596 
72597 #define OTFAD_SR_MDPCP_MASK                      (0x2U)
72598 #define OTFAD_SR_MDPCP_SHIFT                     (1U)
72599 /*! MDPCP - MDPC Present */
72600 #define OTFAD_SR_MDPCP(x)                        (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK)
72601 
72602 #define OTFAD_SR_MODE_MASK                       (0xCU)
72603 #define OTFAD_SR_MODE_SHIFT                      (2U)
72604 /*! MODE - Operating Mode
72605  *  0b00..Operating in Normal mode (NRM)
72606  *  0b01..Unused (reserved)
72607  *  0b10..Unused (reserved)
72608  *  0b11..Operating in Logically Disabled Mode (LDM)
72609  */
72610 #define OTFAD_SR_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK)
72611 
72612 #define OTFAD_SR_NCTX_MASK                       (0xF0U)
72613 #define OTFAD_SR_NCTX_SHIFT                      (4U)
72614 /*! NCTX - Number of Contexts */
72615 #define OTFAD_SR_NCTX(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK)
72616 
72617 #define OTFAD_SR_CTXER0_MASK                     (0x100U)
72618 #define OTFAD_SR_CTXER0_SHIFT                    (8U)
72619 /*! CTXER0 - Context Error
72620  *  0b0..No key blob error was detected for context "n".
72621  *  0b1..A key blob integrity error might have been detected in context "n".
72622  */
72623 #define OTFAD_SR_CTXER0(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER0_SHIFT)) & OTFAD_SR_CTXER0_MASK)
72624 
72625 #define OTFAD_SR_CTXER1_MASK                     (0x200U)
72626 #define OTFAD_SR_CTXER1_SHIFT                    (9U)
72627 /*! CTXER1 - Context Error
72628  *  0b0..No key blob error was detected for context "n".
72629  *  0b1..A key blob integrity error might have been detected in context "n".
72630  */
72631 #define OTFAD_SR_CTXER1(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER1_SHIFT)) & OTFAD_SR_CTXER1_MASK)
72632 
72633 #define OTFAD_SR_CTXER2_MASK                     (0x400U)
72634 #define OTFAD_SR_CTXER2_SHIFT                    (10U)
72635 /*! CTXER2 - Context Error
72636  *  0b0..No key blob error was detected for context "n".
72637  *  0b1..A key blob integrity error might have been detected in context "n".
72638  */
72639 #define OTFAD_SR_CTXER2(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER2_SHIFT)) & OTFAD_SR_CTXER2_MASK)
72640 
72641 #define OTFAD_SR_CTXER3_MASK                     (0x800U)
72642 #define OTFAD_SR_CTXER3_SHIFT                    (11U)
72643 /*! CTXER3 - Context Error
72644  *  0b0..No key blob error was detected for context "n".
72645  *  0b1..A key blob integrity error might have been detected in context "n".
72646  */
72647 #define OTFAD_SR_CTXER3(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER3_SHIFT)) & OTFAD_SR_CTXER3_MASK)
72648 
72649 #define OTFAD_SR_CTXIE0_MASK                     (0x10000U)
72650 #define OTFAD_SR_CTXIE0_SHIFT                    (16U)
72651 /*! CTXIE0 - Context Integrity Error
72652  *  0b0..No key blob integrity error was detected for context "n".
72653  *  0b1..A key blob integrity error was detected in context "n".
72654  */
72655 #define OTFAD_SR_CTXIE0(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE0_SHIFT)) & OTFAD_SR_CTXIE0_MASK)
72656 
72657 #define OTFAD_SR_CTXIE1_MASK                     (0x20000U)
72658 #define OTFAD_SR_CTXIE1_SHIFT                    (17U)
72659 /*! CTXIE1 - Context Integrity Error
72660  *  0b0..No key blob integrity error was detected for context "n".
72661  *  0b1..A key blob integrity error was detected in context "n".
72662  */
72663 #define OTFAD_SR_CTXIE1(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE1_SHIFT)) & OTFAD_SR_CTXIE1_MASK)
72664 
72665 #define OTFAD_SR_CTXIE2_MASK                     (0x40000U)
72666 #define OTFAD_SR_CTXIE2_SHIFT                    (18U)
72667 /*! CTXIE2 - Context Integrity Error
72668  *  0b0..No key blob integrity error was detected for context "n".
72669  *  0b1..A key blob integrity error was detected in context "n".
72670  */
72671 #define OTFAD_SR_CTXIE2(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE2_SHIFT)) & OTFAD_SR_CTXIE2_MASK)
72672 
72673 #define OTFAD_SR_CTXIE3_MASK                     (0x80000U)
72674 #define OTFAD_SR_CTXIE3_SHIFT                    (19U)
72675 /*! CTXIE3 - Context Integrity Error
72676  *  0b0..No key blob integrity error was detected for context "n".
72677  *  0b1..A key blob integrity error was detected in context "n".
72678  */
72679 #define OTFAD_SR_CTXIE3(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE3_SHIFT)) & OTFAD_SR_CTXIE3_MASK)
72680 
72681 #define OTFAD_SR_HRL_MASK                        (0xF000000U)
72682 #define OTFAD_SR_HRL_SHIFT                       (24U)
72683 /*! HRL - Hardware Revision Level */
72684 #define OTFAD_SR_HRL(x)                          (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK)
72685 
72686 #define OTFAD_SR_RRAM_MASK                       (0x10000000U)
72687 #define OTFAD_SR_RRAM_SHIFT                      (28U)
72688 /*! RRAM - Restricted Register Access Mode
72689  *  0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
72690  *  0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
72691  */
72692 #define OTFAD_SR_RRAM(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
72693 
72694 #define OTFAD_SR_GEM_MASK                        (0x20000000U)
72695 #define OTFAD_SR_GEM_SHIFT                       (29U)
72696 /*! GEM - Global Enable Mode
72697  *  0b0..OTFAD is disabled. All data fetched by the FlexSPI bypasses OTFAD processing.
72698  *  0b1..OTFAD is enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.
72699  */
72700 #define OTFAD_SR_GEM(x)                          (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK)
72701 
72702 #define OTFAD_SR_KBPE_MASK                       (0x40000000U)
72703 #define OTFAD_SR_KBPE_SHIFT                      (30U)
72704 /*! KBPE - Key Blob Processing Enable
72705  *  0b0..Key blob processing is not enabled.
72706  *  0b1..Key blob processing is enabled.
72707  */
72708 #define OTFAD_SR_KBPE(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBPE_SHIFT)) & OTFAD_SR_KBPE_MASK)
72709 
72710 #define OTFAD_SR_KBD_MASK                        (0x80000000U)
72711 #define OTFAD_SR_KBD_SHIFT                       (31U)
72712 /*! KBD - Key Blob Processing Done
72713  *  0b0..Key blob processing was not enabled, or is not complete.
72714  *  0b1..Key blob processing was enabled and is complete.
72715  */
72716 #define OTFAD_SR_KBD(x)                          (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBD_SHIFT)) & OTFAD_SR_KBD_MASK)
72717 /*! @} */
72718 
72719 /*! @name KEY - AES Key Word */
72720 /*! @{ */
72721 
72722 #define OTFAD_KEY_KEY_MASK                       (0xFFFFFFFFU)
72723 #define OTFAD_KEY_KEY_SHIFT                      (0U)
72724 /*! KEY - AES Key */
72725 #define OTFAD_KEY_KEY(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_KEY_KEY_SHIFT)) & OTFAD_KEY_KEY_MASK)
72726 /*! @} */
72727 
72728 /* The count of OTFAD_KEY */
72729 #define OTFAD_KEY_COUNT                          (4U)
72730 
72731 /* The count of OTFAD_KEY */
72732 #define OTFAD_KEY_COUNT2                         (4U)
72733 
72734 /*! @name CTR - AES Counter Word */
72735 /*! @{ */
72736 
72737 #define OTFAD_CTR_CTR_MASK                       (0xFFFFFFFFU)
72738 #define OTFAD_CTR_CTR_SHIFT                      (0U)
72739 /*! CTR - AES Counter */
72740 #define OTFAD_CTR_CTR(x)                         (((uint32_t)(((uint32_t)(x)) << OTFAD_CTR_CTR_SHIFT)) & OTFAD_CTR_CTR_MASK)
72741 /*! @} */
72742 
72743 /* The count of OTFAD_CTR */
72744 #define OTFAD_CTR_COUNT                          (4U)
72745 
72746 /* The count of OTFAD_CTR */
72747 #define OTFAD_CTR_COUNT2                         (2U)
72748 
72749 /*! @name RGD_W0 - AES Region Descriptor Word0 */
72750 /*! @{ */
72751 
72752 #define OTFAD_RGD_W0_SRTADDR_MASK                (0xFFFFFC00U)
72753 #define OTFAD_RGD_W0_SRTADDR_SHIFT               (10U)
72754 /*! SRTADDR - Start Address */
72755 #define OTFAD_RGD_W0_SRTADDR(x)                  (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W0_SRTADDR_SHIFT)) & OTFAD_RGD_W0_SRTADDR_MASK)
72756 /*! @} */
72757 
72758 /* The count of OTFAD_RGD_W0 */
72759 #define OTFAD_RGD_W0_COUNT                       (4U)
72760 
72761 /*! @name RGD_W1 - AES Region Descriptor Word1 */
72762 /*! @{ */
72763 
72764 #define OTFAD_RGD_W1_VLD_MASK                    (0x1U)
72765 #define OTFAD_RGD_W1_VLD_SHIFT                   (0U)
72766 /*! VLD - Valid
72767  *  0b0..Context is invalid.
72768  *  0b1..Context is valid.
72769  */
72770 #define OTFAD_RGD_W1_VLD(x)                      (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_VLD_SHIFT)) & OTFAD_RGD_W1_VLD_MASK)
72771 
72772 #define OTFAD_RGD_W1_ADE_MASK                    (0x2U)
72773 #define OTFAD_RGD_W1_ADE_SHIFT                   (1U)
72774 /*! ADE - AES Decryption Enable.
72775  *  0b0..Bypass the fetched data.
72776  *  0b1..Perform the CTR-AES128 mode decryption on the fetched data.
72777  */
72778 #define OTFAD_RGD_W1_ADE(x)                      (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ADE_SHIFT)) & OTFAD_RGD_W1_ADE_MASK)
72779 
72780 #define OTFAD_RGD_W1_RO_MASK                     (0x4U)
72781 #define OTFAD_RGD_W1_RO_SHIFT                    (2U)
72782 /*! RO - Read-Only
72783  *  0b0..The context registers can be accessed normally (as defined by SR[RRAM]).
72784  *  0b1..The context registers are read-only and accesses may be further restricted based on SR[RRAM].
72785  */
72786 #define OTFAD_RGD_W1_RO(x)                       (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_RO_SHIFT)) & OTFAD_RGD_W1_RO_MASK)
72787 
72788 #define OTFAD_RGD_W1_ENDADDR_MASK                (0xFFFFFC00U)
72789 #define OTFAD_RGD_W1_ENDADDR_SHIFT               (10U)
72790 /*! ENDADDR - End Address */
72791 #define OTFAD_RGD_W1_ENDADDR(x)                  (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ENDADDR_SHIFT)) & OTFAD_RGD_W1_ENDADDR_MASK)
72792 /*! @} */
72793 
72794 /* The count of OTFAD_RGD_W1 */
72795 #define OTFAD_RGD_W1_COUNT                       (4U)
72796 
72797 
72798 /*!
72799  * @}
72800  */ /* end of group OTFAD_Register_Masks */
72801 
72802 
72803 /* OTFAD - Peripheral instance base addresses */
72804 /** Peripheral OTFAD1 base address */
72805 #define OTFAD1_BASE                              (0x400CC000u)
72806 /** Peripheral OTFAD1 base pointer */
72807 #define OTFAD1                                   ((OTFAD_Type *)OTFAD1_BASE)
72808 /** Peripheral OTFAD2 base address */
72809 #define OTFAD2_BASE                              (0x400D0000u)
72810 /** Peripheral OTFAD2 base pointer */
72811 #define OTFAD2                                   ((OTFAD_Type *)OTFAD2_BASE)
72812 /** Array initializer of OTFAD peripheral base addresses */
72813 #define OTFAD_BASE_ADDRS                         { 0u, OTFAD1_BASE, OTFAD2_BASE }
72814 /** Array initializer of OTFAD peripheral base pointers */
72815 #define OTFAD_BASE_PTRS                          { (OTFAD_Type *)0u, OTFAD1, OTFAD2 }
72816 
72817 /*!
72818  * @}
72819  */ /* end of group OTFAD_Peripheral_Access_Layer */
72820 
72821 
72822 /* ----------------------------------------------------------------------------
72823    -- PDM Peripheral Access Layer
72824    ---------------------------------------------------------------------------- */
72825 
72826 /*!
72827  * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer
72828  * @{
72829  */
72830 
72831 /** PDM - Register Layout Typedef */
72832 typedef struct {
72833   __IO uint32_t CTRL_1;                            /**< PDM Control register 1, offset: 0x0 */
72834   __IO uint32_t CTRL_2;                            /**< PDM Control register 2, offset: 0x4 */
72835   __IO uint32_t STAT;                              /**< PDM Status register, offset: 0x8 */
72836        uint8_t RESERVED_0[4];
72837   __IO uint32_t FIFO_CTRL;                         /**< PDM FIFO Control register, offset: 0x10 */
72838   __IO uint32_t FIFO_STAT;                         /**< PDM FIFO Status register, offset: 0x14 */
72839        uint8_t RESERVED_1[12];
72840   __I  uint32_t DATACH[8];                         /**< PDM Output Result Register, array offset: 0x24, array step: 0x4 */
72841        uint8_t RESERVED_2[32];
72842   __IO uint32_t DC_CTRL;                           /**< PDM DC Remover Control register, offset: 0x64 */
72843        uint8_t RESERVED_3[12];
72844   __IO uint32_t RANGE_CTRL;                        /**< PDM Range Control register, offset: 0x74 */
72845        uint8_t RESERVED_4[4];
72846   __IO uint32_t RANGE_STAT;                        /**< PDM Range Status register, offset: 0x7C */
72847        uint8_t RESERVED_5[16];
72848   __IO uint32_t VAD0_CTRL_1;                       /**< Voice Activity Detector 0 Control register, offset: 0x90 */
72849   __IO uint32_t VAD0_CTRL_2;                       /**< Voice Activity Detector 0 Control register, offset: 0x94 */
72850   __IO uint32_t VAD0_STAT;                         /**< Voice Activity Detector 0 Status register, offset: 0x98 */
72851   __IO uint32_t VAD0_SCONFIG;                      /**< Voice Activity Detector 0 Signal Configuration, offset: 0x9C */
72852   __IO uint32_t VAD0_NCONFIG;                      /**< Voice Activity Detector 0 Noise Configuration, offset: 0xA0 */
72853   __I  uint32_t VAD0_NDATA;                        /**< Voice Activity Detector 0 Noise Data, offset: 0xA4 */
72854   __IO uint32_t VAD0_ZCD;                          /**< Voice Activity Detector 0 Zero-Crossing Detector, offset: 0xA8 */
72855 } PDM_Type;
72856 
72857 /* ----------------------------------------------------------------------------
72858    -- PDM Register Masks
72859    ---------------------------------------------------------------------------- */
72860 
72861 /*!
72862  * @addtogroup PDM_Register_Masks PDM Register Masks
72863  * @{
72864  */
72865 
72866 /*! @name CTRL_1 - PDM Control register 1 */
72867 /*! @{ */
72868 
72869 #define PDM_CTRL_1_CH0EN_MASK                    (0x1U)
72870 #define PDM_CTRL_1_CH0EN_SHIFT                   (0U)
72871 /*! CH0EN - Channel 0 Enable */
72872 #define PDM_CTRL_1_CH0EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)
72873 
72874 #define PDM_CTRL_1_CH1EN_MASK                    (0x2U)
72875 #define PDM_CTRL_1_CH1EN_SHIFT                   (1U)
72876 /*! CH1EN - Channel 1 Enable */
72877 #define PDM_CTRL_1_CH1EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)
72878 
72879 #define PDM_CTRL_1_CH2EN_MASK                    (0x4U)
72880 #define PDM_CTRL_1_CH2EN_SHIFT                   (2U)
72881 /*! CH2EN - Channel 2 Enable */
72882 #define PDM_CTRL_1_CH2EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)
72883 
72884 #define PDM_CTRL_1_CH3EN_MASK                    (0x8U)
72885 #define PDM_CTRL_1_CH3EN_SHIFT                   (3U)
72886 /*! CH3EN - Channel 3 Enable */
72887 #define PDM_CTRL_1_CH3EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)
72888 
72889 #define PDM_CTRL_1_CH4EN_MASK                    (0x10U)
72890 #define PDM_CTRL_1_CH4EN_SHIFT                   (4U)
72891 /*! CH4EN - Channel 4 Enable */
72892 #define PDM_CTRL_1_CH4EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK)
72893 
72894 #define PDM_CTRL_1_CH5EN_MASK                    (0x20U)
72895 #define PDM_CTRL_1_CH5EN_SHIFT                   (5U)
72896 /*! CH5EN - Channel 5 Enable */
72897 #define PDM_CTRL_1_CH5EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK)
72898 
72899 #define PDM_CTRL_1_CH6EN_MASK                    (0x40U)
72900 #define PDM_CTRL_1_CH6EN_SHIFT                   (6U)
72901 /*! CH6EN - Channel 6 Enable */
72902 #define PDM_CTRL_1_CH6EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK)
72903 
72904 #define PDM_CTRL_1_CH7EN_MASK                    (0x80U)
72905 #define PDM_CTRL_1_CH7EN_SHIFT                   (7U)
72906 /*! CH7EN - Channel 7 Enable */
72907 #define PDM_CTRL_1_CH7EN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK)
72908 
72909 #define PDM_CTRL_1_ERREN_MASK                    (0x800000U)
72910 #define PDM_CTRL_1_ERREN_SHIFT                   (23U)
72911 /*! ERREN - Error Interruption Enable
72912  *  0b0..Error Interrupts disabled
72913  *  0b1..Error Interrupts enabled
72914  */
72915 #define PDM_CTRL_1_ERREN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)
72916 
72917 #define PDM_CTRL_1_DISEL_MASK                    (0x3000000U)
72918 #define PDM_CTRL_1_DISEL_SHIFT                   (24U)
72919 /*! DISEL - DMA Interrupt Selection
72920  *  0b00..DMA and interrupt requests disabled
72921  *  0b01..DMA requests enabled
72922  *  0b10..Interrupt requests enabled
72923  *  0b11..Reserved
72924  */
72925 #define PDM_CTRL_1_DISEL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)
72926 
72927 #define PDM_CTRL_1_DBGE_MASK                     (0x4000000U)
72928 #define PDM_CTRL_1_DBGE_SHIFT                    (26U)
72929 /*! DBGE - Module Enable in Debug
72930  *  0b0..Disabled after completing the current frame
72931  *  0b1..Enabled
72932  */
72933 #define PDM_CTRL_1_DBGE(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)
72934 
72935 #define PDM_CTRL_1_SRES_MASK                     (0x8000000U)
72936 #define PDM_CTRL_1_SRES_SHIFT                    (27U)
72937 /*! SRES - Software-reset bit
72938  *  0b0..No action
72939  *  0b1..Software reset
72940  */
72941 #define PDM_CTRL_1_SRES(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)
72942 
72943 #define PDM_CTRL_1_DBG_MASK                      (0x10000000U)
72944 #define PDM_CTRL_1_DBG_SHIFT                     (28U)
72945 /*! DBG - Debug Mode
72946  *  0b0..Normal Mode
72947  *  0b1..Debug Mode
72948  */
72949 #define PDM_CTRL_1_DBG(x)                        (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)
72950 
72951 #define PDM_CTRL_1_PDMIEN_MASK                   (0x20000000U)
72952 #define PDM_CTRL_1_PDMIEN_SHIFT                  (29U)
72953 /*! PDMIEN - PDM Enable
72954  *  0b0..PDM stopped
72955  *  0b1..PDM operation started
72956  */
72957 #define PDM_CTRL_1_PDMIEN(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)
72958 
72959 #define PDM_CTRL_1_DOZEN_MASK                    (0x40000000U)
72960 #define PDM_CTRL_1_DOZEN_SHIFT                   (30U)
72961 /*! DOZEN - DOZE enable */
72962 #define PDM_CTRL_1_DOZEN(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)
72963 
72964 #define PDM_CTRL_1_MDIS_MASK                     (0x80000000U)
72965 #define PDM_CTRL_1_MDIS_SHIFT                    (31U)
72966 /*! MDIS - Module Disable
72967  *  0b0..Normal Mode
72968  *  0b1..Disable/Low Leakage Mode
72969  */
72970 #define PDM_CTRL_1_MDIS(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)
72971 /*! @} */
72972 
72973 /*! @name CTRL_2 - PDM Control register 2 */
72974 /*! @{ */
72975 
72976 #define PDM_CTRL_2_CLKDIV_MASK                   (0xFFU)
72977 #define PDM_CTRL_2_CLKDIV_SHIFT                  (0U)
72978 /*! CLKDIV - Clock Divider */
72979 #define PDM_CTRL_2_CLKDIV(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)
72980 
72981 #define PDM_CTRL_2_CICOSR_MASK                   (0xF0000U)
72982 #define PDM_CTRL_2_CICOSR_SHIFT                  (16U)
72983 /*! CICOSR - CIC Decimation Rate */
72984 #define PDM_CTRL_2_CICOSR(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)
72985 
72986 #define PDM_CTRL_2_QSEL_MASK                     (0xE000000U)
72987 #define PDM_CTRL_2_QSEL_SHIFT                    (25U)
72988 /*! QSEL - Quality Mode
72989  *  0b001..High quality mode
72990  *  0b000..Medium quality mode
72991  *  0b111..Low quality mode
72992  *  0b110..Very low quality 0 mode
72993  *  0b101..Very low quality 1 mode
72994  *  0b100..Very low quality 2 mode
72995  */
72996 #define PDM_CTRL_2_QSEL(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)
72997 /*! @} */
72998 
72999 /*! @name STAT - PDM Status register */
73000 /*! @{ */
73001 
73002 #define PDM_STAT_CH0F_MASK                       (0x1U)
73003 #define PDM_STAT_CH0F_SHIFT                      (0U)
73004 /*! CH0F - Channel 0 Output Data Flag
73005  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
73006  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
73007  */
73008 #define PDM_STAT_CH0F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)
73009 
73010 #define PDM_STAT_CH1F_MASK                       (0x2U)
73011 #define PDM_STAT_CH1F_SHIFT                      (1U)
73012 /*! CH1F - Channel 1 Output Data Flag
73013  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
73014  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
73015  */
73016 #define PDM_STAT_CH1F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)
73017 
73018 #define PDM_STAT_CH2F_MASK                       (0x4U)
73019 #define PDM_STAT_CH2F_SHIFT                      (2U)
73020 /*! CH2F - Channel 2 Output Data Flag
73021  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
73022  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
73023  */
73024 #define PDM_STAT_CH2F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)
73025 
73026 #define PDM_STAT_CH3F_MASK                       (0x8U)
73027 #define PDM_STAT_CH3F_SHIFT                      (3U)
73028 /*! CH3F - Channel 3 Output Data Flag
73029  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
73030  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
73031  */
73032 #define PDM_STAT_CH3F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)
73033 
73034 #define PDM_STAT_CH4F_MASK                       (0x10U)
73035 #define PDM_STAT_CH4F_SHIFT                      (4U)
73036 /*! CH4F - Channel 4 Output Data Flag
73037  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
73038  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
73039  */
73040 #define PDM_STAT_CH4F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK)
73041 
73042 #define PDM_STAT_CH5F_MASK                       (0x20U)
73043 #define PDM_STAT_CH5F_SHIFT                      (5U)
73044 /*! CH5F - Channel 5 Output Data Flag
73045  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
73046  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
73047  */
73048 #define PDM_STAT_CH5F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK)
73049 
73050 #define PDM_STAT_CH6F_MASK                       (0x40U)
73051 #define PDM_STAT_CH6F_SHIFT                      (6U)
73052 /*! CH6F - Channel 6 Output Data Flag
73053  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
73054  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
73055  */
73056 #define PDM_STAT_CH6F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK)
73057 
73058 #define PDM_STAT_CH7F_MASK                       (0x80U)
73059 #define PDM_STAT_CH7F_SHIFT                      (7U)
73060 /*! CH7F - Channel 7 Output Data Flag
73061  *  0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
73062  *  0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
73063  */
73064 #define PDM_STAT_CH7F(x)                         (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK)
73065 
73066 #define PDM_STAT_LOWFREQF_MASK                   (0x20000000U)
73067 #define PDM_STAT_LOWFREQF_SHIFT                  (29U)
73068 /*! LOWFREQF - Low Frequency Flag
73069  *  0b0..CLKDIV value is OK
73070  *  0b1..CLKDIV value is too low
73071  */
73072 #define PDM_STAT_LOWFREQF(x)                     (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK)
73073 
73074 #define PDM_STAT_FIR_RDY_MASK                    (0x40000000U)
73075 #define PDM_STAT_FIR_RDY_SHIFT                   (30U)
73076 /*! FIR_RDY - Filter Data Ready
73077  *  0b0..Filter data is not reliable
73078  *  0b1..Filter data is reliable
73079  */
73080 #define PDM_STAT_FIR_RDY(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK)
73081 
73082 #define PDM_STAT_BSY_FIL_MASK                    (0x80000000U)
73083 #define PDM_STAT_BSY_FIL_SHIFT                   (31U)
73084 /*! BSY_FIL - Busy Flag
73085  *  0b1..PDM is running
73086  *  0b0..PDM is stopped
73087  */
73088 #define PDM_STAT_BSY_FIL(x)                      (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)
73089 /*! @} */
73090 
73091 /*! @name FIFO_CTRL - PDM FIFO Control register */
73092 /*! @{ */
73093 
73094 #define PDM_FIFO_CTRL_FIFOWMK_MASK               (0x7U)
73095 #define PDM_FIFO_CTRL_FIFOWMK_SHIFT              (0U)
73096 /*! FIFOWMK - FIFO Watermark Control */
73097 #define PDM_FIFO_CTRL_FIFOWMK(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
73098 /*! @} */
73099 
73100 /*! @name FIFO_STAT - PDM FIFO Status register */
73101 /*! @{ */
73102 
73103 #define PDM_FIFO_STAT_FIFOOVF0_MASK              (0x1U)
73104 #define PDM_FIFO_STAT_FIFOOVF0_SHIFT             (0U)
73105 /*! FIFOOVF0 - FIFO Overflow Exception flag for Channel 0
73106  *  0b0..No exception by FIFO overflow
73107  *  0b1..Exception by FIFO overflow
73108  */
73109 #define PDM_FIFO_STAT_FIFOOVF0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)
73110 
73111 #define PDM_FIFO_STAT_FIFOOVF1_MASK              (0x2U)
73112 #define PDM_FIFO_STAT_FIFOOVF1_SHIFT             (1U)
73113 /*! FIFOOVF1 - FIFO Overflow Exception flag for Channel 1
73114  *  0b0..No exception by FIFO overflow
73115  *  0b1..Exception by FIFO overflow
73116  */
73117 #define PDM_FIFO_STAT_FIFOOVF1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)
73118 
73119 #define PDM_FIFO_STAT_FIFOOVF2_MASK              (0x4U)
73120 #define PDM_FIFO_STAT_FIFOOVF2_SHIFT             (2U)
73121 /*! FIFOOVF2 - FIFO Overflow Exception flag for Channel 2
73122  *  0b0..No exception by FIFO overflow
73123  *  0b1..Exception by FIFO overflow
73124  */
73125 #define PDM_FIFO_STAT_FIFOOVF2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)
73126 
73127 #define PDM_FIFO_STAT_FIFOOVF3_MASK              (0x8U)
73128 #define PDM_FIFO_STAT_FIFOOVF3_SHIFT             (3U)
73129 /*! FIFOOVF3 - FIFO Overflow Exception flag for Channel 3
73130  *  0b0..No exception by FIFO overflow
73131  *  0b1..Exception by FIFO overflow
73132  */
73133 #define PDM_FIFO_STAT_FIFOOVF3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)
73134 
73135 #define PDM_FIFO_STAT_FIFOOVF4_MASK              (0x10U)
73136 #define PDM_FIFO_STAT_FIFOOVF4_SHIFT             (4U)
73137 /*! FIFOOVF4 - FIFO Overflow Exception flag for Channel 4
73138  *  0b0..No exception by FIFO overflow
73139  *  0b1..Exception by FIFO overflow
73140  */
73141 #define PDM_FIFO_STAT_FIFOOVF4(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK)
73142 
73143 #define PDM_FIFO_STAT_FIFOOVF5_MASK              (0x20U)
73144 #define PDM_FIFO_STAT_FIFOOVF5_SHIFT             (5U)
73145 /*! FIFOOVF5 - FIFO Overflow Exception flag for Channel 5
73146  *  0b0..No exception by FIFO overflow
73147  *  0b1..Exception by FIFO overflow
73148  */
73149 #define PDM_FIFO_STAT_FIFOOVF5(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
73150 
73151 #define PDM_FIFO_STAT_FIFOOVF6_MASK              (0x40U)
73152 #define PDM_FIFO_STAT_FIFOOVF6_SHIFT             (6U)
73153 /*! FIFOOVF6 - FIFO Overflow Exception flag for Channel 6
73154  *  0b0..No exception by FIFO overflow
73155  *  0b1..Exception by FIFO overflow
73156  */
73157 #define PDM_FIFO_STAT_FIFOOVF6(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
73158 
73159 #define PDM_FIFO_STAT_FIFOOVF7_MASK              (0x80U)
73160 #define PDM_FIFO_STAT_FIFOOVF7_SHIFT             (7U)
73161 /*! FIFOOVF7 - FIFO Overflow Exception flag for Channel 7
73162  *  0b0..No exception by FIFO overflow
73163  *  0b1..Exception by FIFO overflow
73164  */
73165 #define PDM_FIFO_STAT_FIFOOVF7(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK)
73166 
73167 #define PDM_FIFO_STAT_FIFOUND0_MASK              (0x100U)
73168 #define PDM_FIFO_STAT_FIFOUND0_SHIFT             (8U)
73169 /*! FIFOUND0 - FIFO Underflow Exception flag for Channel 0
73170  *  0b0..No exception by FIFO Underflow
73171  *  0b1..Exception by FIFO underflow
73172  */
73173 #define PDM_FIFO_STAT_FIFOUND0(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)
73174 
73175 #define PDM_FIFO_STAT_FIFOUND1_MASK              (0x200U)
73176 #define PDM_FIFO_STAT_FIFOUND1_SHIFT             (9U)
73177 /*! FIFOUND1 - FIFO Underflow Exception flag for Channel 1
73178  *  0b0..No exception by FIFO Underflow
73179  *  0b1..Exception by FIFO underflow
73180  */
73181 #define PDM_FIFO_STAT_FIFOUND1(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)
73182 
73183 #define PDM_FIFO_STAT_FIFOUND2_MASK              (0x400U)
73184 #define PDM_FIFO_STAT_FIFOUND2_SHIFT             (10U)
73185 /*! FIFOUND2 - FIFO Underflow Exception flag for Channel 2
73186  *  0b0..No exception by FIFO Underflow
73187  *  0b1..Exception by FIFO underflow
73188  */
73189 #define PDM_FIFO_STAT_FIFOUND2(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)
73190 
73191 #define PDM_FIFO_STAT_FIFOUND3_MASK              (0x800U)
73192 #define PDM_FIFO_STAT_FIFOUND3_SHIFT             (11U)
73193 /*! FIFOUND3 - FIFO Underflow Exception flag for Channel 3
73194  *  0b0..No exception by FIFO Underflow
73195  *  0b1..Exception by FIFO underflow
73196  */
73197 #define PDM_FIFO_STAT_FIFOUND3(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)
73198 
73199 #define PDM_FIFO_STAT_FIFOUND4_MASK              (0x1000U)
73200 #define PDM_FIFO_STAT_FIFOUND4_SHIFT             (12U)
73201 /*! FIFOUND4 - FIFO Underflow Exception flag for Channel 4
73202  *  0b0..No exception by FIFO Underflow
73203  *  0b1..Exception by FIFO underflow
73204  */
73205 #define PDM_FIFO_STAT_FIFOUND4(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK)
73206 
73207 #define PDM_FIFO_STAT_FIFOUND5_MASK              (0x2000U)
73208 #define PDM_FIFO_STAT_FIFOUND5_SHIFT             (13U)
73209 /*! FIFOUND5 - FIFO Underflow Exception flag for Channel 5
73210  *  0b0..No exception by FIFO Underflow
73211  *  0b1..Exception by FIFO underflow
73212  */
73213 #define PDM_FIFO_STAT_FIFOUND5(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK)
73214 
73215 #define PDM_FIFO_STAT_FIFOUND6_MASK              (0x4000U)
73216 #define PDM_FIFO_STAT_FIFOUND6_SHIFT             (14U)
73217 /*! FIFOUND6 - FIFO Underflow Exception flag for Channel 6
73218  *  0b0..No exception by FIFO Underflow
73219  *  0b1..Exception by FIFO underflow
73220  */
73221 #define PDM_FIFO_STAT_FIFOUND6(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK)
73222 
73223 #define PDM_FIFO_STAT_FIFOUND7_MASK              (0x8000U)
73224 #define PDM_FIFO_STAT_FIFOUND7_SHIFT             (15U)
73225 /*! FIFOUND7 - FIFO Underflow Exception flag for Channel 7
73226  *  0b0..No exception by FIFO Underflow
73227  *  0b1..Exception by FIFO underflow
73228  */
73229 #define PDM_FIFO_STAT_FIFOUND7(x)                (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK)
73230 /*! @} */
73231 
73232 /*! @name DATACH - PDM Output Result Register */
73233 /*! @{ */
73234 
73235 #define PDM_DATACH_DATA_MASK                     (0xFFFFFFFFU)
73236 #define PDM_DATACH_DATA_SHIFT                    (0U)
73237 /*! DATA - Channel n Data */
73238 #define PDM_DATACH_DATA(x)                       (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK)
73239 /*! @} */
73240 
73241 /* The count of PDM_DATACH */
73242 #define PDM_DATACH_COUNT                         (8U)
73243 
73244 /*! @name DC_CTRL - PDM DC Remover Control register */
73245 /*! @{ */
73246 
73247 #define PDM_DC_CTRL_DCCONFIG0_MASK               (0x3U)
73248 #define PDM_DC_CTRL_DCCONFIG0_SHIFT              (0U)
73249 /*! DCCONFIG0 - Channel 0 DC Remover Configuration
73250  *  0b11..DC Remover is bypassed
73251  *  0b00..DC Remover cut-off at 21Hz
73252  *  0b01..DC Remover cut-off at 83Hz
73253  *  0b10..DC Remover cut-off at 152Hz
73254  */
73255 #define PDM_DC_CTRL_DCCONFIG0(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)
73256 
73257 #define PDM_DC_CTRL_DCCONFIG1_MASK               (0xCU)
73258 #define PDM_DC_CTRL_DCCONFIG1_SHIFT              (2U)
73259 /*! DCCONFIG1 - Channel 1 DC Remover Configuration
73260  *  0b11..DC Remover is bypassed
73261  *  0b00..DC Remover cut-off at 21Hz
73262  *  0b01..DC Remover cut-off at 83Hz
73263  *  0b10..DC Remover cut-off at 152Hz
73264  */
73265 #define PDM_DC_CTRL_DCCONFIG1(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)
73266 
73267 #define PDM_DC_CTRL_DCCONFIG2_MASK               (0x30U)
73268 #define PDM_DC_CTRL_DCCONFIG2_SHIFT              (4U)
73269 /*! DCCONFIG2 - Channel 2 DC Remover Configuration
73270  *  0b11..DC Remover is bypassed
73271  *  0b00..DC Remover cut-off at 21Hz
73272  *  0b01..DC Remover cut-off at 83Hz
73273  *  0b10..DC Remover cut-off at 152Hz
73274  */
73275 #define PDM_DC_CTRL_DCCONFIG2(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)
73276 
73277 #define PDM_DC_CTRL_DCCONFIG3_MASK               (0xC0U)
73278 #define PDM_DC_CTRL_DCCONFIG3_SHIFT              (6U)
73279 /*! DCCONFIG3 - Channel 3 DC Remover Configuration
73280  *  0b11..DC Remover is bypassed
73281  *  0b00..DC Remover cut-off at 21Hz
73282  *  0b01..DC Remover cut-off at 83Hz
73283  *  0b10..DC Remover cut-off at 152Hz
73284  */
73285 #define PDM_DC_CTRL_DCCONFIG3(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)
73286 
73287 #define PDM_DC_CTRL_DCCONFIG4_MASK               (0x300U)
73288 #define PDM_DC_CTRL_DCCONFIG4_SHIFT              (8U)
73289 /*! DCCONFIG4 - Channel 4 DC Remover Configuration
73290  *  0b11..DC Remover is bypassed
73291  *  0b00..DC Remover cut-off at 21Hz
73292  *  0b01..DC Remover cut-off at 83Hz
73293  *  0b10..DC Remover cut-off at 152Hz
73294  */
73295 #define PDM_DC_CTRL_DCCONFIG4(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK)
73296 
73297 #define PDM_DC_CTRL_DCCONFIG5_MASK               (0xC00U)
73298 #define PDM_DC_CTRL_DCCONFIG5_SHIFT              (10U)
73299 /*! DCCONFIG5 - Channel 5 DC Remover Configuration
73300  *  0b11..DC Remover is bypassed
73301  *  0b00..DC Remover cut-off at 21Hz
73302  *  0b01..DC Remover cut-off at 83Hz
73303  *  0b10..DC Remover cut-off at 152Hz
73304  */
73305 #define PDM_DC_CTRL_DCCONFIG5(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK)
73306 
73307 #define PDM_DC_CTRL_DCCONFIG6_MASK               (0x3000U)
73308 #define PDM_DC_CTRL_DCCONFIG6_SHIFT              (12U)
73309 /*! DCCONFIG6 - Channel 6 DC Remover Configuration
73310  *  0b11..DC Remover is bypassed
73311  *  0b00..DC Remover cut-off at 21Hz
73312  *  0b01..DC Remover cut-off at 83Hz
73313  *  0b10..DC Remover cut-off at 152Hz
73314  */
73315 #define PDM_DC_CTRL_DCCONFIG6(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK)
73316 
73317 #define PDM_DC_CTRL_DCCONFIG7_MASK               (0xC000U)
73318 #define PDM_DC_CTRL_DCCONFIG7_SHIFT              (14U)
73319 /*! DCCONFIG7 - Channel 7 DC Remover Configuration
73320  *  0b11..DC Remover is bypassed
73321  *  0b00..DC Remover cut-off at 21Hz
73322  *  0b01..DC Remover cut-off at 83Hz
73323  *  0b10..DC Remover cut-off at 152Hz
73324  */
73325 #define PDM_DC_CTRL_DCCONFIG7(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK)
73326 /*! @} */
73327 
73328 /*! @name RANGE_CTRL - PDM Range Control register */
73329 /*! @{ */
73330 
73331 #define PDM_RANGE_CTRL_RANGEADJ0_MASK            (0xFU)
73332 #define PDM_RANGE_CTRL_RANGEADJ0_SHIFT           (0U)
73333 /*! RANGEADJ0 - Channel 0 Range Adjustment */
73334 #define PDM_RANGE_CTRL_RANGEADJ0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK)
73335 
73336 #define PDM_RANGE_CTRL_RANGEADJ1_MASK            (0xF0U)
73337 #define PDM_RANGE_CTRL_RANGEADJ1_SHIFT           (4U)
73338 /*! RANGEADJ1 - Channel 1 Range Adjustment */
73339 #define PDM_RANGE_CTRL_RANGEADJ1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK)
73340 
73341 #define PDM_RANGE_CTRL_RANGEADJ2_MASK            (0xF00U)
73342 #define PDM_RANGE_CTRL_RANGEADJ2_SHIFT           (8U)
73343 /*! RANGEADJ2 - Channel 2 Range Adjustment */
73344 #define PDM_RANGE_CTRL_RANGEADJ2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK)
73345 
73346 #define PDM_RANGE_CTRL_RANGEADJ3_MASK            (0xF000U)
73347 #define PDM_RANGE_CTRL_RANGEADJ3_SHIFT           (12U)
73348 /*! RANGEADJ3 - Channel 3 Range Adjustment */
73349 #define PDM_RANGE_CTRL_RANGEADJ3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK)
73350 
73351 #define PDM_RANGE_CTRL_RANGEADJ4_MASK            (0xF0000U)
73352 #define PDM_RANGE_CTRL_RANGEADJ4_SHIFT           (16U)
73353 /*! RANGEADJ4 - Channel 4 Range Adjustment */
73354 #define PDM_RANGE_CTRL_RANGEADJ4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK)
73355 
73356 #define PDM_RANGE_CTRL_RANGEADJ5_MASK            (0xF00000U)
73357 #define PDM_RANGE_CTRL_RANGEADJ5_SHIFT           (20U)
73358 /*! RANGEADJ5 - Channel 5 Range Adjustment */
73359 #define PDM_RANGE_CTRL_RANGEADJ5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK)
73360 
73361 #define PDM_RANGE_CTRL_RANGEADJ6_MASK            (0xF000000U)
73362 #define PDM_RANGE_CTRL_RANGEADJ6_SHIFT           (24U)
73363 /*! RANGEADJ6 - Channel 6 Range Adjustment */
73364 #define PDM_RANGE_CTRL_RANGEADJ6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK)
73365 
73366 #define PDM_RANGE_CTRL_RANGEADJ7_MASK            (0xF0000000U)
73367 #define PDM_RANGE_CTRL_RANGEADJ7_SHIFT           (28U)
73368 /*! RANGEADJ7 - Channel 7 Range Adjustment */
73369 #define PDM_RANGE_CTRL_RANGEADJ7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK)
73370 /*! @} */
73371 
73372 /*! @name RANGE_STAT - PDM Range Status register */
73373 /*! @{ */
73374 
73375 #define PDM_RANGE_STAT_RANGEOVF0_MASK            (0x1U)
73376 #define PDM_RANGE_STAT_RANGEOVF0_SHIFT           (0U)
73377 /*! RANGEOVF0 - Channel 0 Range Overflow Error Flag
73378  *  0b0..No exception by range overflow
73379  *  0b1..Exception by range overflow
73380  */
73381 #define PDM_RANGE_STAT_RANGEOVF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK)
73382 
73383 #define PDM_RANGE_STAT_RANGEOVF1_MASK            (0x2U)
73384 #define PDM_RANGE_STAT_RANGEOVF1_SHIFT           (1U)
73385 /*! RANGEOVF1 - Channel 1 Range Overflow Error Flag
73386  *  0b0..No exception by range overflow
73387  *  0b1..Exception by range overflow
73388  */
73389 #define PDM_RANGE_STAT_RANGEOVF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK)
73390 
73391 #define PDM_RANGE_STAT_RANGEOVF2_MASK            (0x4U)
73392 #define PDM_RANGE_STAT_RANGEOVF2_SHIFT           (2U)
73393 /*! RANGEOVF2 - Channel 2 Range Overflow Error Flag
73394  *  0b0..No exception by range overflow
73395  *  0b1..Exception by range overflow
73396  */
73397 #define PDM_RANGE_STAT_RANGEOVF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK)
73398 
73399 #define PDM_RANGE_STAT_RANGEOVF3_MASK            (0x8U)
73400 #define PDM_RANGE_STAT_RANGEOVF3_SHIFT           (3U)
73401 /*! RANGEOVF3 - Channel 3 Range Overflow Error Flag
73402  *  0b0..No exception by range overflow
73403  *  0b1..Exception by range overflow
73404  */
73405 #define PDM_RANGE_STAT_RANGEOVF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK)
73406 
73407 #define PDM_RANGE_STAT_RANGEOVF4_MASK            (0x10U)
73408 #define PDM_RANGE_STAT_RANGEOVF4_SHIFT           (4U)
73409 /*! RANGEOVF4 - Channel 4 Range Overflow Error Flag
73410  *  0b0..No exception by range overflow
73411  *  0b1..Exception by range overflow
73412  */
73413 #define PDM_RANGE_STAT_RANGEOVF4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK)
73414 
73415 #define PDM_RANGE_STAT_RANGEOVF5_MASK            (0x20U)
73416 #define PDM_RANGE_STAT_RANGEOVF5_SHIFT           (5U)
73417 /*! RANGEOVF5 - Channel 5 Range Overflow Error Flag
73418  *  0b0..No exception by range overflow
73419  *  0b1..Exception by range overflow
73420  */
73421 #define PDM_RANGE_STAT_RANGEOVF5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK)
73422 
73423 #define PDM_RANGE_STAT_RANGEOVF6_MASK            (0x40U)
73424 #define PDM_RANGE_STAT_RANGEOVF6_SHIFT           (6U)
73425 /*! RANGEOVF6 - Channel 6 Range Overflow Error Flag
73426  *  0b0..No exception by range overflow
73427  *  0b1..Exception by range overflow
73428  */
73429 #define PDM_RANGE_STAT_RANGEOVF6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK)
73430 
73431 #define PDM_RANGE_STAT_RANGEOVF7_MASK            (0x80U)
73432 #define PDM_RANGE_STAT_RANGEOVF7_SHIFT           (7U)
73433 /*! RANGEOVF7 - Channel 7 Range Overflow Error Flag
73434  *  0b0..No exception by range overflow
73435  *  0b1..Exception by range overflow
73436  */
73437 #define PDM_RANGE_STAT_RANGEOVF7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK)
73438 
73439 #define PDM_RANGE_STAT_RANGEUNF0_MASK            (0x10000U)
73440 #define PDM_RANGE_STAT_RANGEUNF0_SHIFT           (16U)
73441 /*! RANGEUNF0 - Channel 0 Range Underflow Error Flag
73442  *  0b0..No exception by range underflow
73443  *  0b1..Exception by range underflow
73444  */
73445 #define PDM_RANGE_STAT_RANGEUNF0(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK)
73446 
73447 #define PDM_RANGE_STAT_RANGEUNF1_MASK            (0x20000U)
73448 #define PDM_RANGE_STAT_RANGEUNF1_SHIFT           (17U)
73449 /*! RANGEUNF1 - Channel 1 Range Underflow Error Flag
73450  *  0b0..No exception by range underflow
73451  *  0b1..Exception by range underflow
73452  */
73453 #define PDM_RANGE_STAT_RANGEUNF1(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK)
73454 
73455 #define PDM_RANGE_STAT_RANGEUNF2_MASK            (0x40000U)
73456 #define PDM_RANGE_STAT_RANGEUNF2_SHIFT           (18U)
73457 /*! RANGEUNF2 - Channel 2 Range Underflow Error Flag
73458  *  0b0..No exception by range underflow
73459  *  0b1..Exception by range underflow
73460  */
73461 #define PDM_RANGE_STAT_RANGEUNF2(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK)
73462 
73463 #define PDM_RANGE_STAT_RANGEUNF3_MASK            (0x80000U)
73464 #define PDM_RANGE_STAT_RANGEUNF3_SHIFT           (19U)
73465 /*! RANGEUNF3 - Channel 3 Range Underflow Error Flag
73466  *  0b0..No exception by range underflow
73467  *  0b1..Exception by range underflow
73468  */
73469 #define PDM_RANGE_STAT_RANGEUNF3(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK)
73470 
73471 #define PDM_RANGE_STAT_RANGEUNF4_MASK            (0x100000U)
73472 #define PDM_RANGE_STAT_RANGEUNF4_SHIFT           (20U)
73473 /*! RANGEUNF4 - Channel 4 Range Underflow Error Flag
73474  *  0b0..No exception by range underflow
73475  *  0b1..Exception by range underflow
73476  */
73477 #define PDM_RANGE_STAT_RANGEUNF4(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK)
73478 
73479 #define PDM_RANGE_STAT_RANGEUNF5_MASK            (0x200000U)
73480 #define PDM_RANGE_STAT_RANGEUNF5_SHIFT           (21U)
73481 /*! RANGEUNF5 - Channel 5 Range Underflow Error Flag
73482  *  0b0..No exception by range underflow
73483  *  0b1..Exception by range underflow
73484  */
73485 #define PDM_RANGE_STAT_RANGEUNF5(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK)
73486 
73487 #define PDM_RANGE_STAT_RANGEUNF6_MASK            (0x400000U)
73488 #define PDM_RANGE_STAT_RANGEUNF6_SHIFT           (22U)
73489 /*! RANGEUNF6 - Channel 6 Range Underflow Error Flag
73490  *  0b0..No exception by range underflow
73491  *  0b1..Exception by range underflow
73492  */
73493 #define PDM_RANGE_STAT_RANGEUNF6(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK)
73494 
73495 #define PDM_RANGE_STAT_RANGEUNF7_MASK            (0x800000U)
73496 #define PDM_RANGE_STAT_RANGEUNF7_SHIFT           (23U)
73497 /*! RANGEUNF7 - Channel 7 Range Underflow Error Flag
73498  *  0b0..No exception by range underflow
73499  *  0b1..Exception by range underflow
73500  */
73501 #define PDM_RANGE_STAT_RANGEUNF7(x)              (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK)
73502 /*! @} */
73503 
73504 /*! @name VAD0_CTRL_1 - Voice Activity Detector 0 Control register */
73505 /*! @{ */
73506 
73507 #define PDM_VAD0_CTRL_1_VADEN_MASK               (0x1U)
73508 #define PDM_VAD0_CTRL_1_VADEN_SHIFT              (0U)
73509 /*! VADEN - Voice Activity Detector Enable
73510  *  0b0..The HWVAD is disabled
73511  *  0b1..The HWVAD is enabled
73512  */
73513 #define PDM_VAD0_CTRL_1_VADEN(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK)
73514 
73515 #define PDM_VAD0_CTRL_1_VADRST_MASK              (0x2U)
73516 #define PDM_VAD0_CTRL_1_VADRST_SHIFT             (1U)
73517 /*! VADRST - Voice Activity Detector Reset */
73518 #define PDM_VAD0_CTRL_1_VADRST(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK)
73519 
73520 #define PDM_VAD0_CTRL_1_VADIE_MASK               (0x4U)
73521 #define PDM_VAD0_CTRL_1_VADIE_SHIFT              (2U)
73522 /*! VADIE - Voice Activity Detector Interruption Enable
73523  *  0b0..HWVAD Interrupts disabled
73524  *  0b1..HWVAD Interrupts enabled
73525  */
73526 #define PDM_VAD0_CTRL_1_VADIE(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK)
73527 
73528 #define PDM_VAD0_CTRL_1_VADERIE_MASK             (0x8U)
73529 #define PDM_VAD0_CTRL_1_VADERIE_SHIFT            (3U)
73530 /*! VADERIE - Voice Activity Detector Error Interruption Enable
73531  *  0b0..HWVAD Error Interrupts disabled
73532  *  0b1..HWVAD Error Interrupts enabled
73533  */
73534 #define PDM_VAD0_CTRL_1_VADERIE(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK)
73535 
73536 #define PDM_VAD0_CTRL_1_VADST10_MASK             (0x10U)
73537 #define PDM_VAD0_CTRL_1_VADST10_SHIFT            (4U)
73538 /*! VADST10 - Voice Activity Detector Internal Filters Initialization
73539  *  0b0..Normal operation.
73540  *  0b1..Filters are initialized.
73541  */
73542 #define PDM_VAD0_CTRL_1_VADST10(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK)
73543 
73544 #define PDM_VAD0_CTRL_1_VADINITT_MASK            (0x1F00U)
73545 #define PDM_VAD0_CTRL_1_VADINITT_SHIFT           (8U)
73546 /*! VADINITT - Voice Activity Detector Initialization Time */
73547 #define PDM_VAD0_CTRL_1_VADINITT(x)              (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK)
73548 
73549 #define PDM_VAD0_CTRL_1_VADCICOSR_MASK           (0xF0000U)
73550 #define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT          (16U)
73551 /*! VADCICOSR - Voice Activity Detector CIC Oversampling Rate */
73552 #define PDM_VAD0_CTRL_1_VADCICOSR(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK)
73553 
73554 #define PDM_VAD0_CTRL_1_VADCHSEL_MASK            (0x7000000U)
73555 #define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT           (24U)
73556 /*! VADCHSEL - Voice Activity Detector Channel Selector */
73557 #define PDM_VAD0_CTRL_1_VADCHSEL(x)              (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK)
73558 /*! @} */
73559 
73560 /*! @name VAD0_CTRL_2 - Voice Activity Detector 0 Control register */
73561 /*! @{ */
73562 
73563 #define PDM_VAD0_CTRL_2_VADHPF_MASK              (0x3U)
73564 #define PDM_VAD0_CTRL_2_VADHPF_SHIFT             (0U)
73565 /*! VADHPF - Voice Activity Detector High-Pass Filter
73566  *  0b00..Filter bypassed.
73567  *  0b01..Cut-off frequency at 1750Hz.
73568  *  0b10..Cut-off frequency at 215Hz.
73569  *  0b11..Cut-off frequency at 102Hz.
73570  */
73571 #define PDM_VAD0_CTRL_2_VADHPF(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK)
73572 
73573 #define PDM_VAD0_CTRL_2_VADINPGAIN_MASK          (0xF00U)
73574 #define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT         (8U)
73575 /*! VADINPGAIN - Voice Activity Detector Input Gain */
73576 #define PDM_VAD0_CTRL_2_VADINPGAIN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK)
73577 
73578 #define PDM_VAD0_CTRL_2_VADFRAMET_MASK           (0x3F0000U)
73579 #define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT          (16U)
73580 /*! VADFRAMET - Voice Activity Detector Frame Time */
73581 #define PDM_VAD0_CTRL_2_VADFRAMET(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK)
73582 
73583 #define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK          (0x10000000U)
73584 #define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT         (28U)
73585 /*! VADFOUTDIS - Voice Activity Detector Force Output Disable
73586  *  0b0..Output is enabled.
73587  *  0b1..Output is disabled.
73588  */
73589 #define PDM_VAD0_CTRL_2_VADFOUTDIS(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK)
73590 
73591 #define PDM_VAD0_CTRL_2_VADPREFEN_MASK           (0x40000000U)
73592 #define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT          (30U)
73593 /*! VADPREFEN - Voice Activity Detector Pre Filter Enable
73594  *  0b0..Pre-filter is bypassed.
73595  *  0b1..Pre-filter is enabled.
73596  */
73597 #define PDM_VAD0_CTRL_2_VADPREFEN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK)
73598 
73599 #define PDM_VAD0_CTRL_2_VADFRENDIS_MASK          (0x80000000U)
73600 #define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT         (31U)
73601 /*! VADFRENDIS - Voice Activity Detector Frame Energy Disable
73602  *  0b1..Frame energy calculus disabled.
73603  *  0b0..Frame energy calculus enabled.
73604  */
73605 #define PDM_VAD0_CTRL_2_VADFRENDIS(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK)
73606 /*! @} */
73607 
73608 /*! @name VAD0_STAT - Voice Activity Detector 0 Status register */
73609 /*! @{ */
73610 
73611 #define PDM_VAD0_STAT_VADIF_MASK                 (0x1U)
73612 #define PDM_VAD0_STAT_VADIF_SHIFT                (0U)
73613 /*! VADIF - Voice Activity Detector Interrupt Flag
73614  *  0b0..Voice activity not detected
73615  *  0b1..Voice activity detected
73616  */
73617 #define PDM_VAD0_STAT_VADIF(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK)
73618 
73619 #define PDM_VAD0_STAT_VADEF_MASK                 (0x8000U)
73620 #define PDM_VAD0_STAT_VADEF_SHIFT                (15U)
73621 /*! VADEF - Voice Activity Detector Event Flag
73622  *  0b0..Voice activity not detected
73623  *  0b1..Voice activity detected
73624  */
73625 #define PDM_VAD0_STAT_VADEF(x)                   (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADEF_SHIFT)) & PDM_VAD0_STAT_VADEF_MASK)
73626 
73627 #define PDM_VAD0_STAT_VADINSATF_MASK             (0x10000U)
73628 #define PDM_VAD0_STAT_VADINSATF_SHIFT            (16U)
73629 /*! VADINSATF - Voice Activity Detector Input Saturation Flag
73630  *  0b0..No exception
73631  *  0b1..Exception
73632  */
73633 #define PDM_VAD0_STAT_VADINSATF(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK)
73634 
73635 #define PDM_VAD0_STAT_VADINITF_MASK              (0x80000000U)
73636 #define PDM_VAD0_STAT_VADINITF_SHIFT             (31U)
73637 /*! VADINITF - Voice Activity Detector Initialization Flag
73638  *  0b0..HWVAD is not being initialized.
73639  *  0b1..HWVAD is being initialized.
73640  */
73641 #define PDM_VAD0_STAT_VADINITF(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK)
73642 /*! @} */
73643 
73644 /*! @name VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration */
73645 /*! @{ */
73646 
73647 #define PDM_VAD0_SCONFIG_VADSGAIN_MASK           (0xFU)
73648 #define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT          (0U)
73649 /*! VADSGAIN - Voice Activity Detector Signal Gain */
73650 #define PDM_VAD0_SCONFIG_VADSGAIN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK)
73651 
73652 #define PDM_VAD0_SCONFIG_VADSMAXEN_MASK          (0x40000000U)
73653 #define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT         (30U)
73654 /*! VADSMAXEN - Voice Activity Detector Signal Maximum Enable
73655  *  0b0..Maximum block is bypassed.
73656  *  0b1..Maximum block is enabled.
73657  */
73658 #define PDM_VAD0_SCONFIG_VADSMAXEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK)
73659 
73660 #define PDM_VAD0_SCONFIG_VADSFILEN_MASK          (0x80000000U)
73661 #define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT         (31U)
73662 /*! VADSFILEN - Voice Activity Detector Signal Filter Enable
73663  *  0b0..Signal filter is disabled.
73664  *  0b1..Signal filter is enabled.
73665  */
73666 #define PDM_VAD0_SCONFIG_VADSFILEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
73667 /*! @} */
73668 
73669 /*! @name VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration */
73670 /*! @{ */
73671 
73672 #define PDM_VAD0_NCONFIG_VADNGAIN_MASK           (0xFU)
73673 #define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT          (0U)
73674 /*! VADNGAIN - Voice Activity Detector Noise Gain */
73675 #define PDM_VAD0_NCONFIG_VADNGAIN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK)
73676 
73677 #define PDM_VAD0_NCONFIG_VADNFILADJ_MASK         (0x1F00U)
73678 #define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT        (8U)
73679 /*! VADNFILADJ - Voice Activity Detector Noise Filter Adjustment */
73680 #define PDM_VAD0_NCONFIG_VADNFILADJ(x)           (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK)
73681 
73682 #define PDM_VAD0_NCONFIG_VADNOREN_MASK           (0x10000000U)
73683 #define PDM_VAD0_NCONFIG_VADNOREN_SHIFT          (28U)
73684 /*! VADNOREN - Voice Activity Detector Noise OR Enable
73685  *  0b0..Noise input is not decimated.
73686  *  0b1..Noise input is decimated.
73687  */
73688 #define PDM_VAD0_NCONFIG_VADNOREN(x)             (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK)
73689 
73690 #define PDM_VAD0_NCONFIG_VADNDECEN_MASK          (0x20000000U)
73691 #define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT         (29U)
73692 /*! VADNDECEN - Voice Activity Detector Noise Decimation Enable
73693  *  0b0..Noise input is not decimated.
73694  *  0b1..Noise input is decimated.
73695  */
73696 #define PDM_VAD0_NCONFIG_VADNDECEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK)
73697 
73698 #define PDM_VAD0_NCONFIG_VADNMINEN_MASK          (0x40000000U)
73699 #define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT         (30U)
73700 /*! VADNMINEN - Voice Activity Detector Noise Minimum Enable
73701  *  0b0..Minimum block is bypassed.
73702  *  0b1..Minimum block is enabled.
73703  */
73704 #define PDM_VAD0_NCONFIG_VADNMINEN(x)            (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK)
73705 
73706 #define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK        (0x80000000U)
73707 #define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT       (31U)
73708 /*! VADNFILAUTO - Voice Activity Detector Noise Filter Auto
73709  *  0b0..Noise filter is always enabled.
73710  *  0b1..Noise filter is enabled/disabled based on voice activity information.
73711  */
73712 #define PDM_VAD0_NCONFIG_VADNFILAUTO(x)          (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK)
73713 /*! @} */
73714 
73715 /*! @name VAD0_NDATA - Voice Activity Detector 0 Noise Data */
73716 /*! @{ */
73717 
73718 #define PDM_VAD0_NDATA_VADNDATA_MASK             (0xFFFFU)
73719 #define PDM_VAD0_NDATA_VADNDATA_SHIFT            (0U)
73720 /*! VADNDATA - Voice Activity Detector Noise Data */
73721 #define PDM_VAD0_NDATA_VADNDATA(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK)
73722 /*! @} */
73723 
73724 /*! @name VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector */
73725 /*! @{ */
73726 
73727 #define PDM_VAD0_ZCD_VADZCDEN_MASK               (0x1U)
73728 #define PDM_VAD0_ZCD_VADZCDEN_SHIFT              (0U)
73729 /*! VADZCDEN - Zero-Crossing Detector Enable
73730  *  0b0..The ZCD is disabled
73731  *  0b1..The ZCD is enabled
73732  */
73733 #define PDM_VAD0_ZCD_VADZCDEN(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK)
73734 
73735 #define PDM_VAD0_ZCD_VADZCDAUTO_MASK             (0x4U)
73736 #define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT            (2U)
73737 /*! VADZCDAUTO - Zero-Crossing Detector Automatic Threshold
73738  *  0b0..The ZCD threshold is not estimated automatically
73739  *  0b1..The ZCD threshold is estimated automatically
73740  */
73741 #define PDM_VAD0_ZCD_VADZCDAUTO(x)               (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK)
73742 
73743 #define PDM_VAD0_ZCD_VADZCDAND_MASK              (0x10U)
73744 #define PDM_VAD0_ZCD_VADZCDAND_SHIFT             (4U)
73745 /*! VADZCDAND - Zero-Crossing Detector AND Behavior
73746  *  0b0..The ZCD result is OR'ed with the energy-based detection.
73747  *  0b1..The ZCD result is AND'ed with the energy-based detection.
73748  */
73749 #define PDM_VAD0_ZCD_VADZCDAND(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
73750 
73751 #define PDM_VAD0_ZCD_VADZCDADJ_MASK              (0xF00U)
73752 #define PDM_VAD0_ZCD_VADZCDADJ_SHIFT             (8U)
73753 /*! VADZCDADJ - Zero-Crossing Detector Adjustment */
73754 #define PDM_VAD0_ZCD_VADZCDADJ(x)                (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK)
73755 
73756 #define PDM_VAD0_ZCD_VADZCDTH_MASK               (0x3FF0000U)
73757 #define PDM_VAD0_ZCD_VADZCDTH_SHIFT              (16U)
73758 /*! VADZCDTH - Zero-Crossing Detector Threshold */
73759 #define PDM_VAD0_ZCD_VADZCDTH(x)                 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK)
73760 /*! @} */
73761 
73762 
73763 /*!
73764  * @}
73765  */ /* end of group PDM_Register_Masks */
73766 
73767 
73768 /* PDM - Peripheral instance base addresses */
73769 /** Peripheral PDM base address */
73770 #define PDM_BASE                                 (0x40C20000u)
73771 /** Peripheral PDM base pointer */
73772 #define PDM                                      ((PDM_Type *)PDM_BASE)
73773 /** Array initializer of PDM peripheral base addresses */
73774 #define PDM_BASE_ADDRS                           { PDM_BASE }
73775 /** Array initializer of PDM peripheral base pointers */
73776 #define PDM_BASE_PTRS                            { PDM }
73777 
73778 /*!
73779  * @}
73780  */ /* end of group PDM_Peripheral_Access_Layer */
73781 
73782 
73783 /* ----------------------------------------------------------------------------
73784    -- PGMC_BPC Peripheral Access Layer
73785    ---------------------------------------------------------------------------- */
73786 
73787 /*!
73788  * @addtogroup PGMC_BPC_Peripheral_Access_Layer PGMC_BPC Peripheral Access Layer
73789  * @{
73790  */
73791 
73792 /** PGMC_BPC - Register Layout Typedef */
73793 typedef struct {
73794        uint8_t RESERVED_0[4];
73795   __IO uint32_t BPC_AUTHEN_CTRL;                   /**< BPC Authentication Control, offset: 0x4 */
73796        uint8_t RESERVED_1[8];
73797   __IO uint32_t BPC_MODE;                          /**< BPC Mode, offset: 0x10 */
73798   __IO uint32_t BPC_POWER_CTRL;                    /**< BPC power control, offset: 0x14 */
73799        uint8_t RESERVED_2[20];
73800   __IO uint32_t BPC_FLAG;                          /**< BPC flag, offset: 0x2C */
73801        uint8_t RESERVED_3[16];
73802   __IO uint32_t BPC_SSAR_SAVE_CTRL;                /**< BPC SSAR save control, offset: 0x40 */
73803   __IO uint32_t BPC_SSAR_RESTORE_CTRL;             /**< BPC SSAR restore control, offset: 0x44 */
73804 } PGMC_BPC_Type;
73805 
73806 /* ----------------------------------------------------------------------------
73807    -- PGMC_BPC Register Masks
73808    ---------------------------------------------------------------------------- */
73809 
73810 /*!
73811  * @addtogroup PGMC_BPC_Register_Masks PGMC_BPC Register Masks
73812  * @{
73813  */
73814 
73815 /*! @name BPC_AUTHEN_CTRL - BPC Authentication Control */
73816 /*! @{ */
73817 
73818 #define PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK       (0x1U)
73819 #define PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT      (0U)
73820 /*! USER - Allow user mode access
73821  *  0b0..Allow only privilege mode to access basic power control registers
73822  *  0b1..Allow both privilege and user mode to access basic power control registers
73823  */
73824 #define PGMC_BPC_BPC_AUTHEN_CTRL_USER(x)         (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK)
73825 
73826 #define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK  (0x2U)
73827 #define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
73828 /*! NONSECURE - Allow non-secure mode access
73829  *  0b0..Allow only secure mode to access basic power control registers
73830  *  0b1..Allow both secure and non-secure mode to access basic power control registers
73831  */
73832 #define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK)
73833 
73834 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
73835 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
73836 /*! LOCK_SETTING - Lock NONSECURE and USER */
73837 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK)
73838 
73839 #define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
73840 #define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
73841 /*! WHITE_LIST - Domain ID white list */
73842 #define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK)
73843 
73844 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK  (0x1000U)
73845 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
73846 /*! LOCK_LIST - White list lock */
73847 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK)
73848 
73849 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
73850 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT  (20U)
73851 /*! LOCK_CFG - Configuration lock */
73852 #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK)
73853 /*! @} */
73854 
73855 /*! @name BPC_MODE - BPC Mode */
73856 /*! @{ */
73857 
73858 #define PGMC_BPC_BPC_MODE_CTRL_MODE_MASK         (0x3U)
73859 #define PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT        (0U)
73860 /*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
73861  *  0b00..Not affected by any low power mode
73862  *  0b01..Controlled by CPU power mode of the domain
73863  *  0b10..Controlled by Setpoint
73864  *  0b11..Reserved
73865  */
73866 #define PGMC_BPC_BPC_MODE_CTRL_MODE(x)           (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT)) & PGMC_BPC_BPC_MODE_CTRL_MODE_MASK)
73867 
73868 #define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK     (0x30U)
73869 #define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT    (4U)
73870 /*! DOMAIN_ASSIGN - Domain assignment of the BPC
73871  *  0b00..Domain 0
73872  *  0b01..Domain 1
73873  *  0b10..Domain 2
73874  *  0b11..Domain 3
73875  */
73876 #define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN(x)       (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK)
73877 /*! @} */
73878 
73879 /*! @name BPC_POWER_CTRL - BPC power control */
73880 /*! @{ */
73881 
73882 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U)
73883 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U)
73884 /*! PWR_OFF_AT_WAIT - 0x1: Power off when domain enters WAIT mode */
73885 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK)
73886 
73887 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U)
73888 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U)
73889 /*! PWR_OFF_AT_STOP - 0x1: Power off when domain enters STOP mode */
73890 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK)
73891 
73892 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U)
73893 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U)
73894 /*! PWR_OFF_AT_SUSPEND - 0x1: Power off when domain enters SUSPEND mode */
73895 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK)
73896 
73897 #define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U)
73898 #define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U)
73899 /*! ISO_ON_SOFT - Software isolation on trigger */
73900 #define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK)
73901 
73902 #define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U)
73903 #define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U)
73904 /*! PSW_OFF_SOFT - Software power off trigger */
73905 #define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT(x)  (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK)
73906 
73907 #define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U)
73908 #define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U)
73909 /*! PSW_ON_SOFT - Software power on trigger */
73910 #define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK)
73911 
73912 #define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U)
73913 #define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U)
73914 /*! ISO_OFF_SOFT - Software isolation off trigger */
73915 #define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT(x)  (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK)
73916 
73917 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK (0xFFFF0000U)
73918 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT (16U)
73919 /*! PWR_OFF_AT_SP - Power off when system enters Setpoint number */
73920 #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK)
73921 /*! @} */
73922 
73923 /*! @name BPC_FLAG - BPC flag */
73924 /*! @{ */
73925 
73926 #define PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK          (0x1U)
73927 #define PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT         (0U)
73928 /*! PDN_FLAG - set to 1 after power switch off, cleared by writing 1 */
73929 #define PGMC_BPC_BPC_FLAG_PDN_FLAG(x)            (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT)) & PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK)
73930 /*! @} */
73931 
73932 /*! @name BPC_SSAR_SAVE_CTRL - BPC SSAR save control */
73933 /*! @{ */
73934 
73935 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK (0x1U)
73936 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT (0U)
73937 /*! SAVE_AT_RUN - Save data at RUN mode, software writting 0x1 to trigger SSARC to execute save process */
73938 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK)
73939 
73940 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK (0x2U)
73941 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT (1U)
73942 /*! SAVE_AT_WAIT - Save data when domain enters WAIT mode */
73943 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK)
73944 
73945 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK (0x4U)
73946 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT (2U)
73947 /*! SAVE_AT_STOP - Save data when domain enters STOP mode */
73948 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK)
73949 
73950 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK (0x8U)
73951 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT (3U)
73952 /*! SAVE_AT_SUSPEND - Save data when domain enters SUSPEND mode */
73953 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK)
73954 
73955 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK (0xFFFF0000U)
73956 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT (16U)
73957 /*! SAVE_AT_SP - Save data when system enters a Setpoint. */
73958 #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK)
73959 /*! @} */
73960 
73961 /*! @name BPC_SSAR_RESTORE_CTRL - BPC SSAR restore control */
73962 /*! @{ */
73963 
73964 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK (0x1U)
73965 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT (0U)
73966 /*! RESTORE_AT_RUN - Restore data at RUN mode */
73967 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK)
73968 
73969 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK (0xFFFF0000U)
73970 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT (16U)
73971 /*! RESTORE_AT_SP - Restore data when system enters a Setpoint. */
73972 #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK)
73973 /*! @} */
73974 
73975 
73976 /*!
73977  * @}
73978  */ /* end of group PGMC_BPC_Register_Masks */
73979 
73980 
73981 /* PGMC_BPC - Peripheral instance base addresses */
73982 /** Peripheral PGMC_BPC0 base address */
73983 #define PGMC_BPC0_BASE                           (0x40C88000u)
73984 /** Peripheral PGMC_BPC0 base pointer */
73985 #define PGMC_BPC0                                ((PGMC_BPC_Type *)PGMC_BPC0_BASE)
73986 /** Peripheral PGMC_BPC1 base address */
73987 #define PGMC_BPC1_BASE                           (0x40C88200u)
73988 /** Peripheral PGMC_BPC1 base pointer */
73989 #define PGMC_BPC1                                ((PGMC_BPC_Type *)PGMC_BPC1_BASE)
73990 /** Peripheral PGMC_BPC2 base address */
73991 #define PGMC_BPC2_BASE                           (0x40C88400u)
73992 /** Peripheral PGMC_BPC2 base pointer */
73993 #define PGMC_BPC2                                ((PGMC_BPC_Type *)PGMC_BPC2_BASE)
73994 /** Peripheral PGMC_BPC3 base address */
73995 #define PGMC_BPC3_BASE                           (0x40C88600u)
73996 /** Peripheral PGMC_BPC3 base pointer */
73997 #define PGMC_BPC3                                ((PGMC_BPC_Type *)PGMC_BPC3_BASE)
73998 /** Peripheral PGMC_BPC4 base address */
73999 #define PGMC_BPC4_BASE                           (0x40C88800u)
74000 /** Peripheral PGMC_BPC4 base pointer */
74001 #define PGMC_BPC4                                ((PGMC_BPC_Type *)PGMC_BPC4_BASE)
74002 /** Peripheral PGMC_BPC5 base address */
74003 #define PGMC_BPC5_BASE                           (0x40C88A00u)
74004 /** Peripheral PGMC_BPC5 base pointer */
74005 #define PGMC_BPC5                                ((PGMC_BPC_Type *)PGMC_BPC5_BASE)
74006 /** Peripheral PGMC_BPC6 base address */
74007 #define PGMC_BPC6_BASE                           (0x40C88C00u)
74008 /** Peripheral PGMC_BPC6 base pointer */
74009 #define PGMC_BPC6                                ((PGMC_BPC_Type *)PGMC_BPC6_BASE)
74010 /** Peripheral PGMC_BPC7 base address */
74011 #define PGMC_BPC7_BASE                           (0x40C88E00u)
74012 /** Peripheral PGMC_BPC7 base pointer */
74013 #define PGMC_BPC7                                ((PGMC_BPC_Type *)PGMC_BPC7_BASE)
74014 /** Array initializer of PGMC_BPC peripheral base addresses */
74015 #define PGMC_BPC_BASE_ADDRS                      { PGMC_BPC0_BASE, PGMC_BPC1_BASE, PGMC_BPC2_BASE, PGMC_BPC3_BASE, PGMC_BPC4_BASE, PGMC_BPC5_BASE, PGMC_BPC6_BASE, PGMC_BPC7_BASE }
74016 /** Array initializer of PGMC_BPC peripheral base pointers */
74017 #define PGMC_BPC_BASE_PTRS                       { PGMC_BPC0, PGMC_BPC1, PGMC_BPC2, PGMC_BPC3, PGMC_BPC4, PGMC_BPC5, PGMC_BPC6, PGMC_BPC7 }
74018 
74019 /*!
74020  * @}
74021  */ /* end of group PGMC_BPC_Peripheral_Access_Layer */
74022 
74023 
74024 /* ----------------------------------------------------------------------------
74025    -- PGMC_CPC Peripheral Access Layer
74026    ---------------------------------------------------------------------------- */
74027 
74028 /*!
74029  * @addtogroup PGMC_CPC_Peripheral_Access_Layer PGMC_CPC Peripheral Access Layer
74030  * @{
74031  */
74032 
74033 /** PGMC_CPC - Register Layout Typedef */
74034 typedef struct {
74035        uint8_t RESERVED_0[4];
74036   __IO uint32_t CPC_AUTHEN_CTRL;                   /**< CPC Authentication Control, offset: 0x4 */
74037        uint8_t RESERVED_1[8];
74038   __IO uint32_t CPC_CORE_MODE;                     /**< CPC Core Mode, offset: 0x10 */
74039   __IO uint32_t CPC_CORE_POWER_CTRL;               /**< CPC core power control, offset: 0x14 */
74040        uint8_t RESERVED_2[20];
74041   __IO uint32_t CPC_FLAG;                          /**< CPC flag, offset: 0x2C */
74042        uint8_t RESERVED_3[16];
74043   __IO uint32_t CPC_CACHE_MODE;                    /**< CPC Cache Mode, offset: 0x40 */
74044   __IO uint32_t CPC_CACHE_CM_CTRL;                 /**< CPC cache CPU mode control, offset: 0x44 */
74045   __IO uint32_t CPC_CACHE_SP_CTRL_0;               /**< CPC cache Setpoint control 0, offset: 0x48 */
74046   __IO uint32_t CPC_CACHE_SP_CTRL_1;               /**< CPC cache Setpoint control 1, offset: 0x4C */
74047        uint8_t RESERVED_4[112];
74048   __IO uint32_t CPC_LMEM_MODE;                     /**< CPC local memory Mode, offset: 0xC0 */
74049   __IO uint32_t CPC_LMEM_CM_CTRL;                  /**< CPC local memory CPU mode control, offset: 0xC4 */
74050   __IO uint32_t CPC_LMEM_SP_CTRL_0;                /**< CPC local memory Setpoint control 0, offset: 0xC8 */
74051   __IO uint32_t CPC_LMEM_SP_CTRL_1;                /**< CPC local memory Setpoint control 1, offset: 0xCC */
74052 } PGMC_CPC_Type;
74053 
74054 /* ----------------------------------------------------------------------------
74055    -- PGMC_CPC Register Masks
74056    ---------------------------------------------------------------------------- */
74057 
74058 /*!
74059  * @addtogroup PGMC_CPC_Register_Masks PGMC_CPC Register Masks
74060  * @{
74061  */
74062 
74063 /*! @name CPC_AUTHEN_CTRL - CPC Authentication Control */
74064 /*! @{ */
74065 
74066 #define PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK       (0x1U)
74067 #define PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT      (0U)
74068 /*! USER - Allow user mode access */
74069 #define PGMC_CPC_CPC_AUTHEN_CTRL_USER(x)         (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK)
74070 
74071 #define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK  (0x2U)
74072 #define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
74073 /*! NONSECURE - Allow non-secure mode access */
74074 #define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK)
74075 
74076 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
74077 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
74078 /*! LOCK_SETTING - Lock NONSECURE and USER */
74079 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK)
74080 
74081 #define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
74082 #define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
74083 /*! WHITE_LIST - Domain ID white list */
74084 #define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK)
74085 
74086 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK  (0x1000U)
74087 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
74088 /*! LOCK_LIST - White list lock */
74089 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK)
74090 
74091 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
74092 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT  (20U)
74093 /*! LOCK_CFG - Configuration lock */
74094 #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK)
74095 /*! @} */
74096 
74097 /*! @name CPC_CORE_MODE - CPC Core Mode */
74098 /*! @{ */
74099 
74100 #define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK    (0x3U)
74101 #define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT   (0U)
74102 /*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
74103  *  0b00..Not affected by any low power mode
74104  *  0b01..Controlled by CPU power mode of the domain
74105  *  0b10..Reserved
74106  *  0b11..Reserved
74107  */
74108 #define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE(x)      (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK)
74109 /*! @} */
74110 
74111 /*! @name CPC_CORE_POWER_CTRL - CPC core power control */
74112 /*! @{ */
74113 
74114 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U)
74115 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U)
74116 /*! PWR_OFF_AT_WAIT - Power off when domain enters WAIT mode */
74117 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK)
74118 
74119 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U)
74120 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U)
74121 /*! PWR_OFF_AT_STOP - Power off when domain enters STOP mode */
74122 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK)
74123 
74124 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U)
74125 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U)
74126 /*! PWR_OFF_AT_SUSPEND - Power off when domain enters SUSPEND mode */
74127 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK)
74128 
74129 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U)
74130 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U)
74131 /*! ISO_ON_SOFT - Software isolation on trigger */
74132 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK)
74133 
74134 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U)
74135 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U)
74136 /*! PSW_OFF_SOFT - Software power off trigger */
74137 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK)
74138 
74139 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U)
74140 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U)
74141 /*! PSW_ON_SOFT - Software power on trigger */
74142 #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK)
74143 
74144 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U)
74145 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U)
74146 /*! ISO_OFF_SOFT - Software isolation off trigger */
74147 #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK)
74148 /*! @} */
74149 
74150 /*! @name CPC_FLAG - CPC flag */
74151 /*! @{ */
74152 
74153 #define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK     (0x1U)
74154 #define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT    (0U)
74155 /*! CORE_PDN_FLAG - set to 1 after core power switch off, cleared by writing 1 */
74156 #define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG(x)       (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT)) & PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK)
74157 /*! @} */
74158 
74159 /*! @name CPC_CACHE_MODE - CPC Cache Mode */
74160 /*! @{ */
74161 
74162 #define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK   (0x3U)
74163 #define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT  (0U)
74164 /*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
74165  *  0b00..Not affected by any low power mode
74166  *  0b01..Controlled by CPU power mode of the domain
74167  *  0b10..Controlled by Setpoint
74168  *  0b11..Reserved
74169  */
74170 #define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK)
74171 /*! @} */
74172 
74173 /*! @name CPC_CACHE_CM_CTRL - CPC cache CPU mode control */
74174 /*! @{ */
74175 
74176 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK (0xFU)
74177 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT (0U)
74178 /*! MLPL_AT_RUN - Memory Low Power Level (MLPL) at RUN mode */
74179 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK)
74180 
74181 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U)
74182 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U)
74183 /*! MLPL_AT_WAIT - Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74184 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK)
74185 
74186 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U)
74187 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT (8U)
74188 /*! MLPL_AT_STOP - Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74189 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK)
74190 
74191 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U)
74192 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U)
74193 /*! MLPL_AT_SUSPEND - Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74194 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK)
74195 
74196 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK (0x10000U)
74197 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT (16U)
74198 /*! MLPL_SOFT - Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete */
74199 #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT(x)  (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK)
74200 /*! @} */
74201 
74202 /*! @name CPC_CACHE_SP_CTRL_0 - CPC cache Setpoint control 0 */
74203 /*! @{ */
74204 
74205 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU)
74206 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U)
74207 /*! MLPL_AT_SP0 - Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74208 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK)
74209 
74210 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U)
74211 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U)
74212 /*! MLPL_AT_SP1 - Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74213 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK)
74214 
74215 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U)
74216 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U)
74217 /*! MLPL_AT_SP2 - Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74218 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK)
74219 
74220 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U)
74221 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U)
74222 /*! MLPL_AT_SP3 - Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74223 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK)
74224 
74225 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U)
74226 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U)
74227 /*! MLPL_AT_SP4 - Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74228 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK)
74229 
74230 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U)
74231 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U)
74232 /*! MLPL_AT_SP5 - Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74233 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK)
74234 
74235 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U)
74236 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U)
74237 /*! MLPL_AT_SP6 - Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74238 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK)
74239 
74240 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U)
74241 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U)
74242 /*! MLPL_AT_SP7 - Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74243 #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK)
74244 /*! @} */
74245 
74246 /*! @name CPC_CACHE_SP_CTRL_1 - CPC cache Setpoint control 1 */
74247 /*! @{ */
74248 
74249 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU)
74250 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U)
74251 /*! MLPL_AT_SP8 - Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74252 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK)
74253 
74254 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U)
74255 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U)
74256 /*! MLPL_AT_SP9 - Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74257 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK)
74258 
74259 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U)
74260 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U)
74261 /*! MLPL_AT_SP10 - Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74262 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK)
74263 
74264 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U)
74265 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U)
74266 /*! MLPL_AT_SP11 - Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74267 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK)
74268 
74269 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U)
74270 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U)
74271 /*! MLPL_AT_SP12 - Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74272 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK)
74273 
74274 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U)
74275 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U)
74276 /*! MLPL_AT_SP13 - Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74277 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK)
74278 
74279 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U)
74280 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U)
74281 /*! MLPL_AT_SP14 - Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74282 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK)
74283 
74284 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U)
74285 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U)
74286 /*! MLPL_AT_SP15 - Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74287 #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK)
74288 /*! @} */
74289 
74290 /*! @name CPC_LMEM_MODE - CPC local memory Mode */
74291 /*! @{ */
74292 
74293 #define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK    (0x3U)
74294 #define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT   (0U)
74295 /*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
74296  *  0b00..Not affected by any low power mode
74297  *  0b01..Controlled by CPU power mode of the domain
74298  *  0b10..Controlled by Setpoint
74299  *  0b11..Reserved
74300  */
74301 #define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(x)      (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK)
74302 /*! @} */
74303 
74304 /*! @name CPC_LMEM_CM_CTRL - CPC local memory CPU mode control */
74305 /*! @{ */
74306 
74307 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK (0xFU)
74308 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT (0U)
74309 /*! MLPL_AT_RUN - Memory Low Power Level (MLPL) at RUN mode */
74310 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK)
74311 
74312 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U)
74313 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U)
74314 /*! MLPL_AT_WAIT - Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74315 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK)
74316 
74317 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U)
74318 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT (8U)
74319 /*! MLPL_AT_STOP - Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74320 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK)
74321 
74322 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U)
74323 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U)
74324 /*! MLPL_AT_SUSPEND - Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74325 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK)
74326 
74327 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK (0x10000U)
74328 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT (16U)
74329 /*! MLPL_SOFT - Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete */
74330 #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK)
74331 /*! @} */
74332 
74333 /*! @name CPC_LMEM_SP_CTRL_0 - CPC local memory Setpoint control 0 */
74334 /*! @{ */
74335 
74336 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU)
74337 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U)
74338 /*! MLPL_AT_SP0 - Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74339 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK)
74340 
74341 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U)
74342 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U)
74343 /*! MLPL_AT_SP1 - Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74344 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK)
74345 
74346 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U)
74347 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U)
74348 /*! MLPL_AT_SP2 - Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74349 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK)
74350 
74351 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U)
74352 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U)
74353 /*! MLPL_AT_SP3 - Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74354 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK)
74355 
74356 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U)
74357 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U)
74358 /*! MLPL_AT_SP4 - Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74359 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK)
74360 
74361 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U)
74362 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U)
74363 /*! MLPL_AT_SP5 - Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74364 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK)
74365 
74366 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U)
74367 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U)
74368 /*! MLPL_AT_SP6 - Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74369 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK)
74370 
74371 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U)
74372 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U)
74373 /*! MLPL_AT_SP7 - Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74374 #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK)
74375 /*! @} */
74376 
74377 /*! @name CPC_LMEM_SP_CTRL_1 - CPC local memory Setpoint control 1 */
74378 /*! @{ */
74379 
74380 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU)
74381 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U)
74382 /*! MLPL_AT_SP8 - Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74383 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK)
74384 
74385 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U)
74386 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U)
74387 /*! MLPL_AT_SP9 - Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74388 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK)
74389 
74390 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U)
74391 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U)
74392 /*! MLPL_AT_SP10 - Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74393 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK)
74394 
74395 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U)
74396 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U)
74397 /*! MLPL_AT_SP11 - Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74398 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK)
74399 
74400 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U)
74401 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U)
74402 /*! MLPL_AT_SP12 - Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74403 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK)
74404 
74405 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U)
74406 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U)
74407 /*! MLPL_AT_SP13 - Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74408 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK)
74409 
74410 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U)
74411 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U)
74412 /*! MLPL_AT_SP14 - Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74413 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK)
74414 
74415 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U)
74416 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U)
74417 /*! MLPL_AT_SP15 - Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74418 #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK)
74419 /*! @} */
74420 
74421 
74422 /*!
74423  * @}
74424  */ /* end of group PGMC_CPC_Register_Masks */
74425 
74426 
74427 /* PGMC_CPC - Peripheral instance base addresses */
74428 /** Peripheral PGMC_CPC0 base address */
74429 #define PGMC_CPC0_BASE                           (0x40C89000u)
74430 /** Peripheral PGMC_CPC0 base pointer */
74431 #define PGMC_CPC0                                ((PGMC_CPC_Type *)PGMC_CPC0_BASE)
74432 /** Peripheral PGMC_CPC1 base address */
74433 #define PGMC_CPC1_BASE                           (0x40C89400u)
74434 /** Peripheral PGMC_CPC1 base pointer */
74435 #define PGMC_CPC1                                ((PGMC_CPC_Type *)PGMC_CPC1_BASE)
74436 /** Array initializer of PGMC_CPC peripheral base addresses */
74437 #define PGMC_CPC_BASE_ADDRS                      { PGMC_CPC0_BASE, PGMC_CPC1_BASE }
74438 /** Array initializer of PGMC_CPC peripheral base pointers */
74439 #define PGMC_CPC_BASE_PTRS                       { PGMC_CPC0, PGMC_CPC1 }
74440 
74441 /*!
74442  * @}
74443  */ /* end of group PGMC_CPC_Peripheral_Access_Layer */
74444 
74445 
74446 /* ----------------------------------------------------------------------------
74447    -- PGMC_MIF Peripheral Access Layer
74448    ---------------------------------------------------------------------------- */
74449 
74450 /*!
74451  * @addtogroup PGMC_MIF_Peripheral_Access_Layer PGMC_MIF Peripheral Access Layer
74452  * @{
74453  */
74454 
74455 /** PGMC_MIF - Register Layout Typedef */
74456 typedef struct {
74457        uint8_t RESERVED_0[4];
74458   __IO uint32_t MIF_AUTHEN_CTRL;                   /**< MIF Authentication Control, offset: 0x4 */
74459        uint8_t RESERVED_1[8];
74460   __IO uint32_t MIF_MLPL_SLEEP;                    /**< MIF MLPL control of SLEEP, offset: 0x10 */
74461        uint8_t RESERVED_2[12];
74462   __IO uint32_t MIF_MLPL_IG;                       /**< MIF MLPL control of IG, offset: 0x20 */
74463        uint8_t RESERVED_3[12];
74464   __IO uint32_t MIF_MLPL_LS;                       /**< MIF MLPL control of LS, offset: 0x30 */
74465        uint8_t RESERVED_4[12];
74466   __IO uint32_t MIF_MLPL_HS;                       /**< MIF MLPL control of HS, offset: 0x40 */
74467        uint8_t RESERVED_5[12];
74468   __IO uint32_t MIF_MLPL_STDBY;                    /**< MIF MLPL control of STDBY, offset: 0x50 */
74469        uint8_t RESERVED_6[12];
74470   __IO uint32_t MIF_MLPL_ARR_PDN;                  /**< MIF MLPL control of array power down, offset: 0x60 */
74471        uint8_t RESERVED_7[12];
74472   __IO uint32_t MIF_MLPL_PER_PDN;                  /**< MIF MLPL control of peripheral power down, offset: 0x70 */
74473        uint8_t RESERVED_8[12];
74474   __IO uint32_t MIF_MLPL_INITN;                    /**< MIF MLPL control of INITN, offset: 0x80 */
74475        uint8_t RESERVED_9[44];
74476   __IO uint32_t MIF_MLPL_ISO;                      /**< MIF MLPL control of isolation enable, offset: 0xB0 */
74477 } PGMC_MIF_Type;
74478 
74479 /* ----------------------------------------------------------------------------
74480    -- PGMC_MIF Register Masks
74481    ---------------------------------------------------------------------------- */
74482 
74483 /*!
74484  * @addtogroup PGMC_MIF_Register_Masks PGMC_MIF Register Masks
74485  * @{
74486  */
74487 
74488 /*! @name MIF_AUTHEN_CTRL - MIF Authentication Control */
74489 /*! @{ */
74490 
74491 #define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
74492 #define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_SHIFT  (20U)
74493 /*! LOCK_CFG - Configuration lock */
74494 #define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK)
74495 /*! @} */
74496 
74497 /*! @name MIF_MLPL_SLEEP - MIF MLPL control of SLEEP */
74498 /*! @{ */
74499 
74500 #define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_MASK   (0xFFFFU)
74501 #define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT  (0U)
74502 /*! MLPL_CTRL - Signal behavior at each MLPL */
74503 #define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_MASK)
74504 /*! @} */
74505 
74506 /*! @name MIF_MLPL_IG - MIF MLPL control of IG */
74507 /*! @{ */
74508 
74509 #define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_MASK      (0xFFFFU)
74510 #define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_SHIFT     (0U)
74511 /*! MLPL_CTRL - Signal behavior at each MLPL */
74512 #define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_MASK)
74513 /*! @} */
74514 
74515 /*! @name MIF_MLPL_LS - MIF MLPL control of LS */
74516 /*! @{ */
74517 
74518 #define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_MASK      (0xFFFFU)
74519 #define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_SHIFT     (0U)
74520 /*! MLPL_CTRL - Signal behavior at each MLPL */
74521 #define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_MASK)
74522 /*! @} */
74523 
74524 /*! @name MIF_MLPL_HS - MIF MLPL control of HS */
74525 /*! @{ */
74526 
74527 #define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_MASK      (0xFFFFU)
74528 #define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_SHIFT     (0U)
74529 /*! MLPL_CTRL - Signal behavior at each MLPL */
74530 #define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_MASK)
74531 /*! @} */
74532 
74533 /*! @name MIF_MLPL_STDBY - MIF MLPL control of STDBY */
74534 /*! @{ */
74535 
74536 #define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_MASK   (0xFFFFU)
74537 #define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT  (0U)
74538 /*! MLPL_CTRL - Signal behavior at each MLPL */
74539 #define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_MASK)
74540 /*! @} */
74541 
74542 /*! @name MIF_MLPL_ARR_PDN - MIF MLPL control of array power down */
74543 /*! @{ */
74544 
74545 #define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK (0xFFFFU)
74546 #define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT (0U)
74547 /*! MLPL_CTRL - Signal behavior at each MLPL */
74548 #define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK)
74549 /*! @} */
74550 
74551 /*! @name MIF_MLPL_PER_PDN - MIF MLPL control of peripheral power down */
74552 /*! @{ */
74553 
74554 #define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_MASK (0xFFFFU)
74555 #define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_SHIFT (0U)
74556 /*! MLPL_CTRL - Signal behavior at each MLPL */
74557 #define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_MASK)
74558 /*! @} */
74559 
74560 /*! @name MIF_MLPL_INITN - MIF MLPL control of INITN */
74561 /*! @{ */
74562 
74563 #define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_MASK   (0xFFFFU)
74564 #define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_SHIFT  (0U)
74565 /*! MLPL_CTRL - Signal behavior at each MLPL */
74566 #define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_MASK)
74567 
74568 #define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_MASK (0x80000000U)
74569 #define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_SHIFT (31U)
74570 /*! BYPASS_VDD_OK - Bypass vdd_ok. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74571 #define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_SHIFT)) & PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_MASK)
74572 /*! @} */
74573 
74574 /*! @name MIF_MLPL_ISO - MIF MLPL control of isolation enable */
74575 /*! @{ */
74576 
74577 #define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_MASK     (0xFFFFU)
74578 #define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_SHIFT    (0U)
74579 /*! MLPL_CTRL - Signal behavior at each MLPL */
74580 #define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL(x)       (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_MASK)
74581 /*! @} */
74582 
74583 
74584 /*!
74585  * @}
74586  */ /* end of group PGMC_MIF_Register_Masks */
74587 
74588 
74589 /* PGMC_MIF - Peripheral instance base addresses */
74590 /** Peripheral PGMC_CPC0_MIF0 base address */
74591 #define PGMC_CPC0_MIF0_BASE                      (0x40C89100u)
74592 /** Peripheral PGMC_CPC0_MIF0 base pointer */
74593 #define PGMC_CPC0_MIF0                           ((PGMC_MIF_Type *)PGMC_CPC0_MIF0_BASE)
74594 /** Peripheral PGMC_CPC0_MIF1 base address */
74595 #define PGMC_CPC0_MIF1_BASE                      (0x40C89200u)
74596 /** Peripheral PGMC_CPC0_MIF1 base pointer */
74597 #define PGMC_CPC0_MIF1                           ((PGMC_MIF_Type *)PGMC_CPC0_MIF1_BASE)
74598 /** Peripheral PGMC_CPC1_MIF0 base address */
74599 #define PGMC_CPC1_MIF0_BASE                      (0x40C89500u)
74600 /** Peripheral PGMC_CPC1_MIF0 base pointer */
74601 #define PGMC_CPC1_MIF0                           ((PGMC_MIF_Type *)PGMC_CPC1_MIF0_BASE)
74602 /** Peripheral PGMC_CPC1_MIF1 base address */
74603 #define PGMC_CPC1_MIF1_BASE                      (0x40C89600u)
74604 /** Peripheral PGMC_CPC1_MIF1 base pointer */
74605 #define PGMC_CPC1_MIF1                           ((PGMC_MIF_Type *)PGMC_CPC1_MIF1_BASE)
74606 /** Array initializer of PGMC_MIF peripheral base addresses */
74607 #define PGMC_MIF_BASE_ADDRS                      { PGMC_CPC0_MIF0_BASE, PGMC_CPC0_MIF1_BASE, PGMC_CPC1_MIF0_BASE, PGMC_CPC1_MIF1_BASE }
74608 /** Array initializer of PGMC_MIF peripheral base pointers */
74609 #define PGMC_MIF_BASE_PTRS                       { PGMC_CPC0_MIF0, PGMC_CPC0_MIF1, PGMC_CPC1_MIF0, PGMC_CPC1_MIF1 }
74610 
74611 /*!
74612  * @}
74613  */ /* end of group PGMC_MIF_Peripheral_Access_Layer */
74614 
74615 
74616 /* ----------------------------------------------------------------------------
74617    -- PGMC_PPC Peripheral Access Layer
74618    ---------------------------------------------------------------------------- */
74619 
74620 /*!
74621  * @addtogroup PGMC_PPC_Peripheral_Access_Layer PGMC_PPC Peripheral Access Layer
74622  * @{
74623  */
74624 
74625 /** PGMC_PPC - Register Layout Typedef */
74626 typedef struct {
74627        uint8_t RESERVED_0[4];
74628   __IO uint32_t PPC_AUTHEN_CTRL;                   /**< PPC Authentication Control, offset: 0x4 */
74629        uint8_t RESERVED_1[8];
74630   __IO uint32_t PPC_MODE;                          /**< PPC Mode, offset: 0x10 */
74631   __IO uint32_t PPC_STBY_CM_CTRL;                  /**< PPC standby CPU mode control, offset: 0x14 */
74632   __IO uint32_t PPC_STBY_SP_CTRL;                  /**< PPC standby Setpoint control, offset: 0x18 */
74633 } PGMC_PPC_Type;
74634 
74635 /* ----------------------------------------------------------------------------
74636    -- PGMC_PPC Register Masks
74637    ---------------------------------------------------------------------------- */
74638 
74639 /*!
74640  * @addtogroup PGMC_PPC_Register_Masks PGMC_PPC Register Masks
74641  * @{
74642  */
74643 
74644 /*! @name PPC_AUTHEN_CTRL - PPC Authentication Control */
74645 /*! @{ */
74646 
74647 #define PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK       (0x1U)
74648 #define PGMC_PPC_PPC_AUTHEN_CTRL_USER_SHIFT      (0U)
74649 /*! USER - Allow user mode access */
74650 #define PGMC_PPC_PPC_AUTHEN_CTRL_USER(x)         (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK)
74651 
74652 #define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK  (0x2U)
74653 #define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
74654 /*! NONSECURE - Allow non-secure mode access */
74655 #define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK)
74656 
74657 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
74658 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
74659 /*! LOCK_SETTING - Lock NONSECURE and USER */
74660 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK)
74661 
74662 #define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
74663 #define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
74664 /*! WHITE_LIST - Domain ID white list */
74665 #define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST(x)   (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK)
74666 
74667 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK  (0x1000U)
74668 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
74669 /*! LOCK_LIST - White list lock */
74670 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST(x)    (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK)
74671 
74672 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK   (0x100000U)
74673 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_SHIFT  (20U)
74674 /*! LOCK_CFG - Configuration lock */
74675 #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG(x)     (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK)
74676 /*! @} */
74677 
74678 /*! @name PPC_MODE - PPC Mode */
74679 /*! @{ */
74680 
74681 #define PGMC_PPC_PPC_MODE_CTRL_MODE_MASK         (0x3U)
74682 #define PGMC_PPC_PPC_MODE_CTRL_MODE_SHIFT        (0U)
74683 /*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
74684  *  0b00..Not affected by any low power mode
74685  *  0b01..Controlled by CPU power mode of the domain
74686  *  0b10..Controlled by Setpoint and system standby
74687  *  0b11..Reserved
74688  */
74689 #define PGMC_PPC_PPC_MODE_CTRL_MODE(x)           (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_MODE_CTRL_MODE_SHIFT)) & PGMC_PPC_PPC_MODE_CTRL_MODE_MASK)
74690 
74691 #define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_MASK     (0x30U)
74692 #define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_SHIFT    (4U)
74693 /*! DOMAIN_ASSIGN - Domain assignment of the BPC
74694  *  0b00..Domain 0
74695  *  0b01..Domain 1
74696  *  0b10..Domain 2
74697  *  0b11..Domain 3
74698  */
74699 #define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN(x)       (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_MASK)
74700 /*! @} */
74701 
74702 /*! @name PPC_STBY_CM_CTRL - PPC standby CPU mode control */
74703 /*! @{ */
74704 
74705 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK (0x2U)
74706 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_SHIFT (1U)
74707 /*! STBY_ON_AT_WAIT - PMIC Standby on when domain enters WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74708 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK)
74709 
74710 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK (0x4U)
74711 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_SHIFT (2U)
74712 /*! STBY_ON_AT_STOP - PMIC Standby on when domain enters STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74713 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK)
74714 
74715 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK (0x8U)
74716 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_SHIFT (3U)
74717 /*! STBY_ON_AT_SUSPEND - PMIC Standby on when domain enters SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74718 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK)
74719 
74720 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK (0x100U)
74721 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_SHIFT (8U)
74722 /*! STBY_ON_SOFT - Software PMIC standby on trigger */
74723 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK)
74724 
74725 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK (0x200U)
74726 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_SHIFT (9U)
74727 /*! STBY_OFF_SOFT - Software PMIC standby off trigger */
74728 #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK)
74729 /*! @} */
74730 
74731 /*! @name PPC_STBY_SP_CTRL - PPC standby Setpoint control */
74732 /*! @{ */
74733 
74734 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_MASK (0xFFFFU)
74735 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_SHIFT (0U)
74736 /*! STBY_ON_AT_SP_ACTIVE - PMIC standby on when system enters Setpoint number. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */
74737 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_SHIFT)) & PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_MASK)
74738 
74739 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_MASK (0xFFFF0000U)
74740 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT (16U)
74741 /*! STBY_ON_AT_SP_SLEEP - PMIC standby on when system enters Setpoint number and system is in
74742  *    standby mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
74743  */
74744 #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT)) & PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_MASK)
74745 /*! @} */
74746 
74747 
74748 /*!
74749  * @}
74750  */ /* end of group PGMC_PPC_Register_Masks */
74751 
74752 
74753 /* PGMC_PPC - Peripheral instance base addresses */
74754 /** Peripheral PGMC_PPC0 base address */
74755 #define PGMC_PPC0_BASE                           (0x40C8B000u)
74756 /** Peripheral PGMC_PPC0 base pointer */
74757 #define PGMC_PPC0                                ((PGMC_PPC_Type *)PGMC_PPC0_BASE)
74758 /** Array initializer of PGMC_PPC peripheral base addresses */
74759 #define PGMC_PPC_BASE_ADDRS                      { PGMC_PPC0_BASE }
74760 /** Array initializer of PGMC_PPC peripheral base pointers */
74761 #define PGMC_PPC_BASE_PTRS                       { PGMC_PPC0 }
74762 
74763 /*!
74764  * @}
74765  */ /* end of group PGMC_PPC_Peripheral_Access_Layer */
74766 
74767 
74768 /* ----------------------------------------------------------------------------
74769    -- PHY_LDO Peripheral Access Layer
74770    ---------------------------------------------------------------------------- */
74771 
74772 /*!
74773  * @addtogroup PHY_LDO_Peripheral_Access_Layer PHY_LDO Peripheral Access Layer
74774  * @{
74775  */
74776 
74777 /** PHY_LDO - Register Layout Typedef */
74778 typedef struct {
74779   struct {                                         /* offset: 0x0 */
74780     __IO uint32_t RW;                                /**< Analog Control Register CTRL0, offset: 0x0 */
74781     __IO uint32_t SET;                               /**< Analog Control Register CTRL0, offset: 0x4 */
74782     __IO uint32_t CLR;                               /**< Analog Control Register CTRL0, offset: 0x8 */
74783     __IO uint32_t TOG;                               /**< Analog Control Register CTRL0, offset: 0xC */
74784   } CTRL0;
74785        uint8_t RESERVED_0[64];
74786   struct {                                         /* offset: 0x50 */
74787     __I  uint32_t RW;                                /**< Analog Status Register STAT0, offset: 0x50 */
74788     __I  uint32_t SET;                               /**< Analog Status Register STAT0, offset: 0x54 */
74789     __I  uint32_t CLR;                               /**< Analog Status Register STAT0, offset: 0x58 */
74790     __I  uint32_t TOG;                               /**< Analog Status Register STAT0, offset: 0x5C */
74791   } STAT0;
74792 } PHY_LDO_Type;
74793 
74794 /* ----------------------------------------------------------------------------
74795    -- PHY_LDO Register Masks
74796    ---------------------------------------------------------------------------- */
74797 
74798 /*!
74799  * @addtogroup PHY_LDO_Register_Masks PHY_LDO Register Masks
74800  * @{
74801  */
74802 
74803 /*! @name CTRL0 - Analog Control Register CTRL0 */
74804 /*! @{ */
74805 
74806 #define PHY_LDO_CTRL0_LINREG_EN_MASK             (0x1U)
74807 #define PHY_LDO_CTRL0_LINREG_EN_SHIFT            (0U)
74808 /*! LINREG_EN - LinrReg master enable */
74809 #define PHY_LDO_CTRL0_LINREG_EN(x)               (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_EN_MASK)
74810 
74811 #define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK  (0x2U)
74812 #define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT (1U)
74813 /*! LINREG_PWRUPLOAD_DIS - LinReg power-up load disable
74814  *  0b0..Internal pull-down enabled
74815  *  0b1..Internal pull-down disabled
74816  */
74817 #define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS(x)    (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT)) & PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK)
74818 
74819 #define PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK      (0x4U)
74820 #define PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT     (2U)
74821 /*! LINREG_ILIMIT_EN - LinReg current-limit enable */
74822 #define PHY_LDO_CTRL0_LINREG_ILIMIT_EN(x)        (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK)
74823 
74824 #define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK     (0x1F0U)
74825 #define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT    (4U)
74826 /*! LINREG_OUTPUT_TRG - LinReg output voltage target setting
74827  *  0b00000..Set output voltage to x.xV
74828  *  0b10000..Sets output voltage to 1.0V
74829  *  0b11111..Set output voltage to x.xV
74830  */
74831 #define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG(x)       (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT)) & PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK)
74832 
74833 #define PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK      (0x8000U)
74834 #define PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT     (15U)
74835 /*! LINREG_PHY_ISO_B - Isolation control for attached PHY load */
74836 #define PHY_LDO_CTRL0_LINREG_PHY_ISO_B(x)        (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT)) & PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK)
74837 /*! @} */
74838 
74839 /*! @name STAT0 - Analog Status Register STAT0 */
74840 /*! @{ */
74841 
74842 #define PHY_LDO_STAT0_LINREG_STAT_MASK           (0xFU)
74843 #define PHY_LDO_STAT0_LINREG_STAT_SHIFT          (0U)
74844 /*! LINREG_STAT - LinReg Status Bits */
74845 #define PHY_LDO_STAT0_LINREG_STAT(x)             (((uint32_t)(((uint32_t)(x)) << PHY_LDO_STAT0_LINREG_STAT_SHIFT)) & PHY_LDO_STAT0_LINREG_STAT_MASK)
74846 /*! @} */
74847 
74848 
74849 /*!
74850  * @}
74851  */ /* end of group PHY_LDO_Register_Masks */
74852 
74853 
74854 /* PHY_LDO - Peripheral instance base addresses */
74855 /** Peripheral PHY_LDO base address */
74856 #define PHY_LDO_BASE                             (0u)
74857 /** Peripheral PHY_LDO base pointer */
74858 #define PHY_LDO                                  ((PHY_LDO_Type *)PHY_LDO_BASE)
74859 /** Array initializer of PHY_LDO peripheral base addresses */
74860 #define PHY_LDO_BASE_ADDRS                       { PHY_LDO_BASE }
74861 /** Array initializer of PHY_LDO peripheral base pointers */
74862 #define PHY_LDO_BASE_PTRS                        { PHY_LDO }
74863 
74864 /*!
74865  * @}
74866  */ /* end of group PHY_LDO_Peripheral_Access_Layer */
74867 
74868 
74869 /* ----------------------------------------------------------------------------
74870    -- PIT Peripheral Access Layer
74871    ---------------------------------------------------------------------------- */
74872 
74873 /*!
74874  * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
74875  * @{
74876  */
74877 
74878 /** PIT - Register Layout Typedef */
74879 typedef struct {
74880   __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
74881        uint8_t RESERVED_0[220];
74882   __I  uint32_t LTMR64H;                           /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
74883   __I  uint32_t LTMR64L;                           /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
74884        uint8_t RESERVED_1[24];
74885   struct {                                         /* offset: 0x100, array step: 0x10 */
74886     __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
74887     __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
74888     __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
74889     __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
74890   } CHANNEL[4];
74891 } PIT_Type;
74892 
74893 /* ----------------------------------------------------------------------------
74894    -- PIT Register Masks
74895    ---------------------------------------------------------------------------- */
74896 
74897 /*!
74898  * @addtogroup PIT_Register_Masks PIT Register Masks
74899  * @{
74900  */
74901 
74902 /*! @name MCR - PIT Module Control Register */
74903 /*! @{ */
74904 
74905 #define PIT_MCR_FRZ_MASK                         (0x1U)
74906 #define PIT_MCR_FRZ_SHIFT                        (0U)
74907 /*! FRZ - Freeze
74908  *  0b0..Timers continue to run in Debug mode.
74909  *  0b1..Timers are stopped in Debug mode.
74910  */
74911 #define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
74912 
74913 #define PIT_MCR_MDIS_MASK                        (0x2U)
74914 #define PIT_MCR_MDIS_SHIFT                       (1U)
74915 /*! MDIS - Module Disable for PIT
74916  *  0b0..Clock for standard PIT timers is enabled.
74917  *  0b1..Clock for standard PIT timers is disabled.
74918  */
74919 #define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
74920 /*! @} */
74921 
74922 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */
74923 /*! @{ */
74924 
74925 #define PIT_LTMR64H_LTH_MASK                     (0xFFFFFFFFU)
74926 #define PIT_LTMR64H_LTH_SHIFT                    (0U)
74927 /*! LTH - Life Timer value */
74928 #define PIT_LTMR64H_LTH(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
74929 /*! @} */
74930 
74931 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */
74932 /*! @{ */
74933 
74934 #define PIT_LTMR64L_LTL_MASK                     (0xFFFFFFFFU)
74935 #define PIT_LTMR64L_LTL_SHIFT                    (0U)
74936 /*! LTL - Life Timer value */
74937 #define PIT_LTMR64L_LTL(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
74938 /*! @} */
74939 
74940 /*! @name LDVAL - Timer Load Value Register */
74941 /*! @{ */
74942 
74943 #define PIT_LDVAL_TSV_MASK                       (0xFFFFFFFFU)
74944 #define PIT_LDVAL_TSV_SHIFT                      (0U)
74945 /*! TSV - Timer Start Value */
74946 #define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
74947 /*! @} */
74948 
74949 /* The count of PIT_LDVAL */
74950 #define PIT_LDVAL_COUNT                          (4U)
74951 
74952 /*! @name CVAL - Current Timer Value Register */
74953 /*! @{ */
74954 
74955 #define PIT_CVAL_TVL_MASK                        (0xFFFFFFFFU)
74956 #define PIT_CVAL_TVL_SHIFT                       (0U)
74957 /*! TVL - Current Timer Value */
74958 #define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
74959 /*! @} */
74960 
74961 /* The count of PIT_CVAL */
74962 #define PIT_CVAL_COUNT                           (4U)
74963 
74964 /*! @name TCTRL - Timer Control Register */
74965 /*! @{ */
74966 
74967 #define PIT_TCTRL_TEN_MASK                       (0x1U)
74968 #define PIT_TCTRL_TEN_SHIFT                      (0U)
74969 /*! TEN - Timer Enable
74970  *  0b0..Timer n is disabled.
74971  *  0b1..Timer n is enabled.
74972  */
74973 #define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
74974 
74975 #define PIT_TCTRL_TIE_MASK                       (0x2U)
74976 #define PIT_TCTRL_TIE_SHIFT                      (1U)
74977 /*! TIE - Timer Interrupt Enable
74978  *  0b0..Interrupt requests from Timer n are disabled.
74979  *  0b1..Interrupt is requested whenever TIF is set.
74980  */
74981 #define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
74982 
74983 #define PIT_TCTRL_CHN_MASK                       (0x4U)
74984 #define PIT_TCTRL_CHN_SHIFT                      (2U)
74985 /*! CHN - Chain Mode
74986  *  0b0..Timer is not chained.
74987  *  0b1..Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1.
74988  */
74989 #define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
74990 /*! @} */
74991 
74992 /* The count of PIT_TCTRL */
74993 #define PIT_TCTRL_COUNT                          (4U)
74994 
74995 /*! @name TFLG - Timer Flag Register */
74996 /*! @{ */
74997 
74998 #define PIT_TFLG_TIF_MASK                        (0x1U)
74999 #define PIT_TFLG_TIF_SHIFT                       (0U)
75000 /*! TIF - Timer Interrupt Flag
75001  *  0b0..Timeout has not yet occurred.
75002  *  0b1..Timeout has occurred.
75003  */
75004 #define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
75005 /*! @} */
75006 
75007 /* The count of PIT_TFLG */
75008 #define PIT_TFLG_COUNT                           (4U)
75009 
75010 
75011 /*!
75012  * @}
75013  */ /* end of group PIT_Register_Masks */
75014 
75015 
75016 /* PIT - Peripheral instance base addresses */
75017 /** Peripheral PIT1 base address */
75018 #define PIT1_BASE                                (0x400D8000u)
75019 /** Peripheral PIT1 base pointer */
75020 #define PIT1                                     ((PIT_Type *)PIT1_BASE)
75021 /** Peripheral PIT2 base address */
75022 #define PIT2_BASE                                (0x40CB0000u)
75023 /** Peripheral PIT2 base pointer */
75024 #define PIT2                                     ((PIT_Type *)PIT2_BASE)
75025 /** Array initializer of PIT peripheral base addresses */
75026 #define PIT_BASE_ADDRS                           { 0u, PIT1_BASE, PIT2_BASE }
75027 /** Array initializer of PIT peripheral base pointers */
75028 #define PIT_BASE_PTRS                            { (PIT_Type *)0u, PIT1, PIT2 }
75029 /** Interrupt vectors for the PIT peripheral type */
75030 #define PIT_IRQS                                 { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PIT1_IRQn, PIT1_IRQn, PIT1_IRQn, PIT1_IRQn }, { PIT2_IRQn, PIT2_IRQn, PIT2_IRQn, PIT2_IRQn } }
75031 
75032 /*!
75033  * @}
75034  */ /* end of group PIT_Peripheral_Access_Layer */
75035 
75036 
75037 /* ----------------------------------------------------------------------------
75038    -- PUF Peripheral Access Layer
75039    ---------------------------------------------------------------------------- */
75040 
75041 /*!
75042  * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer
75043  * @{
75044  */
75045 
75046 /** PUF - Register Layout Typedef */
75047 typedef struct {
75048   __IO uint32_t CTRL;                              /**< PUF Control Register, offset: 0x0 */
75049   __IO uint32_t KEYINDEX;                          /**< PUF Key Index Register, offset: 0x4 */
75050   __IO uint32_t KEYSIZE;                           /**< PUF Key Size Register, offset: 0x8 */
75051        uint8_t RESERVED_0[20];
75052   __I  uint32_t STAT;                              /**< PUF Status Register, offset: 0x20 */
75053        uint8_t RESERVED_1[4];
75054   __I  uint32_t ALLOW;                             /**< PUF Allow Register, offset: 0x28 */
75055        uint8_t RESERVED_2[20];
75056   __O  uint32_t KEYINPUT;                          /**< PUF Key Input Register, offset: 0x40 */
75057   __O  uint32_t CODEINPUT;                         /**< PUF Code Input Register, offset: 0x44 */
75058   __I  uint32_t CODEOUTPUT;                        /**< PUF Code Output Register, offset: 0x48 */
75059        uint8_t RESERVED_3[20];
75060   __I  uint32_t KEYOUTINDEX;                       /**< PUF Key Output Index Register, offset: 0x60 */
75061   __I  uint32_t KEYOUTPUT;                         /**< PUF Key Output Register, offset: 0x64 */
75062        uint8_t RESERVED_4[116];
75063   __IO uint32_t IFSTAT;                            /**< PUF Interface Status Register, offset: 0xDC */
75064        uint8_t RESERVED_5[28];
75065   __I  uint32_t VERSION;                           /**< PUF Version Register, offset: 0xFC */
75066   __IO uint32_t INTEN;                             /**< PUF Interrupt Enable, offset: 0x100 */
75067   __IO uint32_t INTSTAT;                           /**< PUF Interrupt Status, offset: 0x104 */
75068   __IO uint32_t PWRCTRL;                           /**< PUF Power Control Of RAM, offset: 0x108 */
75069   __IO uint32_t CFG;                               /**< PUF Configuration Register, offset: 0x10C */
75070        uint8_t RESERVED_6[240];
75071   __IO uint32_t KEYLOCK;                           /**< PUF Key Manager Lock, offset: 0x200 */
75072   __IO uint32_t KEYENABLE;                         /**< PUF Key Manager Enable, offset: 0x204 */
75073   __O  uint32_t KEYRESET;                          /**< PUF Key Manager Reset, offset: 0x208 */
75074   __O  uint32_t IDXBLK;                            /**< PUF Index Block Key Output, offset: 0x20C */
75075   __O  uint32_t IDXBLK_DP;                         /**< PUF Index Block Key Output, offset: 0x210 */
75076   __O  uint32_t KEYMASK[2];                        /**< PUF Key Block 0 Mask Enable..PUF Key Block 1 Mask Enable, array offset: 0x214, array step: 0x4 */
75077        uint8_t RESERVED_7[56];
75078   __I  uint32_t IDXBLK_STATUS;                     /**< PUF Index Block Setting Status Register, offset: 0x254 */
75079   __I  uint32_t IDXBLK_SHIFT;                      /**< PUF Key Manager Shift Status, offset: 0x258 */
75080 } PUF_Type;
75081 
75082 /* ----------------------------------------------------------------------------
75083    -- PUF Register Masks
75084    ---------------------------------------------------------------------------- */
75085 
75086 /*!
75087  * @addtogroup PUF_Register_Masks PUF Register Masks
75088  * @{
75089  */
75090 
75091 /*! @name CTRL - PUF Control Register */
75092 /*! @{ */
75093 
75094 #define PUF_CTRL_ZEROIZE_MASK                    (0x1U)
75095 #define PUF_CTRL_ZEROIZE_SHIFT                   (0U)
75096 /*! ZEROIZE - Begin Zeroize operation for PUF and go to Error state
75097  *  0b0..No Zeroize operation in progress
75098  *  0b1..Zeroize operation in progress
75099  */
75100 #define PUF_CTRL_ZEROIZE(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK)
75101 
75102 #define PUF_CTRL_ENROLL_MASK                     (0x2U)
75103 #define PUF_CTRL_ENROLL_SHIFT                    (1U)
75104 /*! ENROLL - Begin Enroll operation
75105  *  0b0..No Enroll operation in progress
75106  *  0b1..Enroll operation in progress
75107  */
75108 #define PUF_CTRL_ENROLL(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK)
75109 
75110 #define PUF_CTRL_START_MASK                      (0x4U)
75111 #define PUF_CTRL_START_SHIFT                     (2U)
75112 /*! START - Begin Start operation
75113  *  0b0..No Start operation in progress
75114  *  0b1..Start operation in progress
75115  */
75116 #define PUF_CTRL_START(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK)
75117 
75118 #define PUF_CTRL_GENERATEKEY_MASK                (0x8U)
75119 #define PUF_CTRL_GENERATEKEY_SHIFT               (3U)
75120 /*! GENERATEKEY - Begin Set Intrinsic Key operation
75121  *  0b0..No Set Intrinsic Key operation in progress
75122  *  0b1..Set Intrinsic Key operation in progress
75123  */
75124 #define PUF_CTRL_GENERATEKEY(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK)
75125 
75126 #define PUF_CTRL_SETKEY_MASK                     (0x10U)
75127 #define PUF_CTRL_SETKEY_SHIFT                    (4U)
75128 /*! SETKEY - Begin Set User Key operation
75129  *  0b0..No Set Key operation in progress
75130  *  0b1..Set Key operation in progress
75131  */
75132 #define PUF_CTRL_SETKEY(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK)
75133 
75134 #define PUF_CTRL_GETKEY_MASK                     (0x40U)
75135 #define PUF_CTRL_GETKEY_SHIFT                    (6U)
75136 /*! GETKEY - Begin Get Key operation
75137  *  0b0..No Get Key operation in progress
75138  *  0b1..Get Key operation in progress
75139  */
75140 #define PUF_CTRL_GETKEY(x)                       (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK)
75141 /*! @} */
75142 
75143 /*! @name KEYINDEX - PUF Key Index Register */
75144 /*! @{ */
75145 
75146 #define PUF_KEYINDEX_KEYIDX_MASK                 (0xFU)
75147 #define PUF_KEYINDEX_KEYIDX_SHIFT                (0U)
75148 /*! KEYIDX - PUF Key Index
75149  *  0b0000..USE INDEX0
75150  *  0b0001..USE INDEX1
75151  *  0b0010..USE INDEX2
75152  *  0b0011..USE INDEX3
75153  *  0b0100..USE INDEX4
75154  *  0b0101..USE INDEX5
75155  *  0b0110..USE INDEX6
75156  *  0b0111..USE INDEX7
75157  *  0b1000..USE INDEX8
75158  *  0b1001..USE INDEX9
75159  *  0b1010..USE INDEX10
75160  *  0b1011..USE INDEX11
75161  *  0b1100..USE INDEX12
75162  *  0b1101..USE INDEX13
75163  *  0b1110..USE INDEX14
75164  *  0b1111..USE INDEX15
75165  */
75166 #define PUF_KEYINDEX_KEYIDX(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK)
75167 /*! @} */
75168 
75169 /*! @name KEYSIZE - PUF Key Size Register */
75170 /*! @{ */
75171 
75172 #define PUF_KEYSIZE_KEYSIZE_MASK                 (0x3FU)
75173 #define PUF_KEYSIZE_KEYSIZE_SHIFT                (0U)
75174 /*! KEYSIZE - PUF Key Size
75175  *  0b000001..Key Size is 8 Bytes and KC Size is 52 Bytes
75176  *  0b000010..Key Size is 16 Bytes and KC Size is 52 Bytes
75177  *  0b000011..Key Size is 24 Bytes and KC Size is 52 Bytes
75178  *  0b000100..Key Size is 32 Bytes and KC Size is 52 Bytes
75179  *  0b000101..Key Size is 40 Bytes and KC Size is 84 Bytes
75180  *  0b000110..Key Size is 48 Bytes and KC Size is 84 Bytes
75181  *  0b000111..Key Size is 56 Bytes and KC Size is 84 Bytes
75182  *  0b001000..Key Size is 64 Bytes and KC Size is 84 Bytes
75183  *  0b001001..Key Size is 72 Bytes and KC Size is 116 Bytes
75184  *  0b001010..Key Size is 80 Bytes and KC Size is 116 Bytes
75185  *  0b001011..Key Size is 88 Bytes and KC Size is 116 Bytes
75186  *  0b001100..Key Size is 96 Bytes and KC Size is 116 Bytes
75187  *  0b001101..Key Size is 104 Bytes and KC Size is 148 Bytes
75188  *  0b001110..Key Size is 112 Bytes and KC Size is 148 Bytes
75189  *  0b001111..Key Size is 120 Bytes and KC Size is 148 Bytes
75190  *  0b010000..Key Size is 128 Bytes and KC Size is 148 Bytes
75191  *  0b010001..Key Size is 136 Bytes and KC Size is 180 Bytes
75192  *  0b010010..Key Size is 144 Bytes and KC Size is 180 Bytes
75193  *  0b010011..Key Size is 152 Bytes and KC Size is 180 Bytes
75194  *  0b010100..Key Size is 160 Bytes and KC Size is 180 Bytes
75195  *  0b010101..Key Size is 168 Bytes and KC Size is 212 Bytes
75196  *  0b010110..Key Size is 176 Bytes and KC Size is 212 Bytes
75197  *  0b010111..Key Size is 184 Bytes and KC Size is 212 Bytes
75198  *  0b011000..Key Size is 192 Bytes and KC Size is 212 Bytes
75199  *  0b011001..Key Size is 200 Bytes and KC Size is 244 Bytes
75200  *  0b011010..Key Size is 208 Bytes and KC Size is 244 Bytes
75201  *  0b011011..Key Size is 216 Bytes and KC Size is 244 Bytes
75202  *  0b011100..Key Size is 224 Bytes and KC Size is 244 Bytes
75203  *  0b011101..Key Size is 232 Bytes and KC Size is 276 Bytes
75204  *  0b011110..Key Size is 240 Bytes and KC Size is 276 Bytes
75205  *  0b011111..Key Size is 248 Bytes and KC Size is 276 Bytes
75206  *  0b100000..Key Size is 256 Bytes and KC Size is 276 Bytes
75207  *  0b100001..Key Size is 264 Bytes and KC Size is 308 Bytes
75208  *  0b100010..Key Size is 272 Bytes and KC Size is 308 Bytes
75209  *  0b100011..Key Size is 280 Bytes and KC Size is 308 Bytes
75210  *  0b100100..Key Size is 288 Bytes and KC Size is 308 Bytes
75211  *  0b100101..Key Size is 296 Bytes and KC Size is 340 Bytes
75212  *  0b100110..Key Size is 304 Bytes and KC Size is 340 Bytes
75213  *  0b100111..Key Size is 312 Bytes and KC Size is 340 Bytes
75214  *  0b101000..Key Size is 320 Bytes and KC Size is 340 Bytes
75215  *  0b101001..Key Size is 328 Bytes and KC Size is 372 Bytes
75216  *  0b101010..Key Size is 336 Bytes and KC Size is 372 Bytes
75217  *  0b101011..Key Size is 344 Bytes and KC Size is 372 Bytes
75218  *  0b101100..Key Size is 352 Bytes and KC Size is 372 Bytes
75219  *  0b101101..Key Size is 360 Bytes and KC Size is 404 Bytes
75220  *  0b101110..Key Size is 368 Bytes and KC Size is 404 Bytes
75221  *  0b101111..Key Size is 376 Bytes and KC Size is 404 Bytes
75222  *  0b110000..Key Size is 384 Bytes and KC Size is 404 Bytes
75223  *  0b110001..Key Size is 392 Bytes and KC Size is 436 Bytes
75224  *  0b110010..Key Size is 400 Bytes and KC Size is 436 Bytes
75225  *  0b110011..Key Size is 408 Bytes and KC Size is 436 Bytes
75226  *  0b110100..Key Size is 416 Bytes and KC Size is 436 Bytes
75227  *  0b110101..Key Size is 424 Bytes and KC Size is 468 Bytes
75228  *  0b110110..Key Size is 432 Bytes and KC Size is 468 Bytes
75229  *  0b110111..Key Size is 440 Bytes and KC Size is 468 Bytes
75230  *  0b111000..Key Size is 448 Bytes and KC Size is 468 Bytes
75231  *  0b111001..Key Size is 456 Bytes and KC Size is 500 Bytes
75232  *  0b111010..Key Size is 464 Bytes and KC Size is 500 Bytes
75233  *  0b111011..Key Size is 472 Bytes and KC Size is 500 Bytes
75234  *  0b111100..Key Size is 480 Bytes and KC Size is 500 Bytes
75235  *  0b111101..Key Size is 488 Bytes and KC Size is 532 Bytes
75236  *  0b111110..Key Size is 496 Bytes and KC Size is 532 Bytes
75237  *  0b111111..Key Size is 504 Bytes and KC Size is 532 Bytes
75238  *  0b000000..Key Size is 512 Bytes and KC Size is 532 Bytes
75239  */
75240 #define PUF_KEYSIZE_KEYSIZE(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK)
75241 /*! @} */
75242 
75243 /*! @name STAT - PUF Status Register */
75244 /*! @{ */
75245 
75246 #define PUF_STAT_BUSY_MASK                       (0x1U)
75247 #define PUF_STAT_BUSY_SHIFT                      (0U)
75248 /*! BUSY - puf_busy
75249  *  0b0..IDLE
75250  *  0b1..BUSY
75251  */
75252 #define PUF_STAT_BUSY(x)                         (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK)
75253 
75254 #define PUF_STAT_SUCCESS_MASK                    (0x2U)
75255 #define PUF_STAT_SUCCESS_SHIFT                   (1U)
75256 /*! SUCCESS - puf_ok
75257  *  0b0..Last operation was unsuccessful
75258  *  0b1..Last operation was successful
75259  */
75260 #define PUF_STAT_SUCCESS(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK)
75261 
75262 #define PUF_STAT_ERROR_MASK                      (0x4U)
75263 #define PUF_STAT_ERROR_SHIFT                     (2U)
75264 /*! ERROR - puf_error
75265  *  0b0..PUF is not in the Error state
75266  *  0b1..PUF is in the Error state
75267  */
75268 #define PUF_STAT_ERROR(x)                        (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK)
75269 
75270 #define PUF_STAT_KEYINREQ_MASK                   (0x10U)
75271 #define PUF_STAT_KEYINREQ_SHIFT                  (4U)
75272 /*! KEYINREQ - KI_ir
75273  *  0b0..No request for next part of key
75274  *  0b1..Request for next part of key in KEYINPUT register
75275  */
75276 #define PUF_STAT_KEYINREQ(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK)
75277 
75278 #define PUF_STAT_KEYOUTAVAIL_MASK                (0x20U)
75279 #define PUF_STAT_KEYOUTAVAIL_SHIFT               (5U)
75280 /*! KEYOUTAVAIL - KO_or
75281  *  0b0..Next part of key is not available
75282  *  0b1..Next part of key is available in KEYOUTPUT register
75283  */
75284 #define PUF_STAT_KEYOUTAVAIL(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK)
75285 
75286 #define PUF_STAT_CODEINREQ_MASK                  (0x40U)
75287 #define PUF_STAT_CODEINREQ_SHIFT                 (6U)
75288 /*! CODEINREQ - CI_ir
75289  *  0b0..No request for next part of Activation Code/Key Code
75290  *  0b1..request for next part of Activation Code/Key Code in CODEINPUT register
75291  */
75292 #define PUF_STAT_CODEINREQ(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK)
75293 
75294 #define PUF_STAT_CODEOUTAVAIL_MASK               (0x80U)
75295 #define PUF_STAT_CODEOUTAVAIL_SHIFT              (7U)
75296 /*! CODEOUTAVAIL - CO_or
75297  *  0b0..Next part of Activation Code/Key Code is not available
75298  *  0b1..Next part of Activation Code/Key Code is available in CODEOUTPUT register
75299  */
75300 #define PUF_STAT_CODEOUTAVAIL(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK)
75301 /*! @} */
75302 
75303 /*! @name ALLOW - PUF Allow Register */
75304 /*! @{ */
75305 
75306 #define PUF_ALLOW_ALLOWENROLL_MASK               (0x1U)
75307 #define PUF_ALLOW_ALLOWENROLL_SHIFT              (0U)
75308 /*! ALLOWENROLL - Allow Enroll operation
75309  *  0b0..Specified operation is not currently allowed
75310  *  0b1..Specified operation is allowed
75311  */
75312 #define PUF_ALLOW_ALLOWENROLL(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK)
75313 
75314 #define PUF_ALLOW_ALLOWSTART_MASK                (0x2U)
75315 #define PUF_ALLOW_ALLOWSTART_SHIFT               (1U)
75316 /*! ALLOWSTART - Allow Start operation
75317  *  0b0..Specified operation is not currently allowed
75318  *  0b1..Specified operation is allowed
75319  */
75320 #define PUF_ALLOW_ALLOWSTART(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK)
75321 
75322 #define PUF_ALLOW_ALLOWSETKEY_MASK               (0x4U)
75323 #define PUF_ALLOW_ALLOWSETKEY_SHIFT              (2U)
75324 /*! ALLOWSETKEY - Allow Set Key operations
75325  *  0b0..Specified operation is not currently allowed
75326  *  0b1..Specified operation is allowed
75327  */
75328 #define PUF_ALLOW_ALLOWSETKEY(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK)
75329 
75330 #define PUF_ALLOW_ALLOWGETKEY_MASK               (0x8U)
75331 #define PUF_ALLOW_ALLOWGETKEY_SHIFT              (3U)
75332 /*! ALLOWGETKEY - Allow Get Key operation
75333  *  0b0..Specified operation is not currently allowed
75334  *  0b1..Specified operation is allowed
75335  */
75336 #define PUF_ALLOW_ALLOWGETKEY(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK)
75337 /*! @} */
75338 
75339 /*! @name KEYINPUT - PUF Key Input Register */
75340 /*! @{ */
75341 
75342 #define PUF_KEYINPUT_KEYIN_MASK                  (0xFFFFFFFFU)
75343 #define PUF_KEYINPUT_KEYIN_SHIFT                 (0U)
75344 /*! KEYIN - Key input data */
75345 #define PUF_KEYINPUT_KEYIN(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK)
75346 /*! @} */
75347 
75348 /*! @name CODEINPUT - PUF Code Input Register */
75349 /*! @{ */
75350 
75351 #define PUF_CODEINPUT_CODEIN_MASK                (0xFFFFFFFFU)
75352 #define PUF_CODEINPUT_CODEIN_SHIFT               (0U)
75353 /*! CODEIN - AC/KC input data */
75354 #define PUF_CODEINPUT_CODEIN(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK)
75355 /*! @} */
75356 
75357 /*! @name CODEOUTPUT - PUF Code Output Register */
75358 /*! @{ */
75359 
75360 #define PUF_CODEOUTPUT_CODEOUT_MASK              (0xFFFFFFFFU)
75361 #define PUF_CODEOUTPUT_CODEOUT_SHIFT             (0U)
75362 /*! CODEOUT - AC/KC output data */
75363 #define PUF_CODEOUTPUT_CODEOUT(x)                (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK)
75364 /*! @} */
75365 
75366 /*! @name KEYOUTINDEX - PUF Key Output Index Register */
75367 /*! @{ */
75368 
75369 #define PUF_KEYOUTINDEX_KEYOUTIDX_MASK           (0xFFFFFFFFU)
75370 #define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT          (0U)
75371 /*! KEYOUTIDX - Output Key index */
75372 #define PUF_KEYOUTINDEX_KEYOUTIDX(x)             (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK)
75373 /*! @} */
75374 
75375 /*! @name KEYOUTPUT - PUF Key Output Register */
75376 /*! @{ */
75377 
75378 #define PUF_KEYOUTPUT_KEYOUT_MASK                (0xFFFFFFFFU)
75379 #define PUF_KEYOUTPUT_KEYOUT_SHIFT               (0U)
75380 /*! KEYOUT - Key output data from a Get Key operation */
75381 #define PUF_KEYOUTPUT_KEYOUT(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK)
75382 /*! @} */
75383 
75384 /*! @name IFSTAT - PUF Interface Status Register */
75385 /*! @{ */
75386 
75387 #define PUF_IFSTAT_ERROR_MASK                    (0x1U)
75388 #define PUF_IFSTAT_ERROR_SHIFT                   (0U)
75389 /*! ERROR - APB error has occurred
75390  *  0b0..NOERROR
75391  *  0b1..ERROR
75392  */
75393 #define PUF_IFSTAT_ERROR(x)                      (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK)
75394 /*! @} */
75395 
75396 /*! @name VERSION - PUF Version Register */
75397 /*! @{ */
75398 
75399 #define PUF_VERSION_VERSION_MASK                 (0xFFFFFFFFU)
75400 #define PUF_VERSION_VERSION_SHIFT                (0U)
75401 /*! VERSION - Version of PUF */
75402 #define PUF_VERSION_VERSION(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK)
75403 /*! @} */
75404 
75405 /*! @name INTEN - PUF Interrupt Enable */
75406 /*! @{ */
75407 
75408 #define PUF_INTEN_READYEN_MASK                   (0x1U)
75409 #define PUF_INTEN_READYEN_SHIFT                  (0U)
75410 /*! READYEN - PUF Ready Interrupt Enable
75411  *  0b0..PUF ready interrupt disabled
75412  *  0b1..PUF ready interrupt enabled
75413  */
75414 #define PUF_INTEN_READYEN(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK)
75415 
75416 #define PUF_INTEN_SUCCESSEN_MASK                 (0x2U)
75417 #define PUF_INTEN_SUCCESSEN_SHIFT                (1U)
75418 /*! SUCCESSEN - PUF_OK Interrupt Enable
75419  *  0b0..PUF successful interrupt disabled
75420  *  0b1..PUF successful interrupt enabled
75421  */
75422 #define PUF_INTEN_SUCCESSEN(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESSEN_SHIFT)) & PUF_INTEN_SUCCESSEN_MASK)
75423 
75424 #define PUF_INTEN_ERROREN_MASK                   (0x4U)
75425 #define PUF_INTEN_ERROREN_SHIFT                  (2U)
75426 /*! ERROREN - PUF Error Interrupt Enable
75427  *  0b0..PUF error interrupt disabled
75428  *  0b1..PUF error interrupt enabled
75429  */
75430 #define PUF_INTEN_ERROREN(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK)
75431 
75432 #define PUF_INTEN_KEYINREQEN_MASK                (0x10U)
75433 #define PUF_INTEN_KEYINREQEN_SHIFT               (4U)
75434 /*! KEYINREQEN - PUF Key Input Register Interrupt Enable
75435  *  0b0..Key interrupt request disabled
75436  *  0b1..Key interrupt request enabled
75437  */
75438 #define PUF_INTEN_KEYINREQEN(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK)
75439 
75440 #define PUF_INTEN_KEYOUTAVAILEN_MASK             (0x20U)
75441 #define PUF_INTEN_KEYOUTAVAILEN_SHIFT            (5U)
75442 /*! KEYOUTAVAILEN - PUF Key Output Register Interrupt Enable
75443  *  0b0..Key available interrupt disabled
75444  *  0b1..Key available interrupt enabled
75445  */
75446 #define PUF_INTEN_KEYOUTAVAILEN(x)               (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK)
75447 
75448 #define PUF_INTEN_CODEINREQEN_MASK               (0x40U)
75449 #define PUF_INTEN_CODEINREQEN_SHIFT              (6U)
75450 /*! CODEINREQEN - PUF Code Input Register Interrupt Enable
75451  *  0b0..AC/KC interrupt request disabled
75452  *  0b1..AC/KC interrupt request enabled
75453  */
75454 #define PUF_INTEN_CODEINREQEN(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK)
75455 
75456 #define PUF_INTEN_CODEOUTAVAILEN_MASK            (0x80U)
75457 #define PUF_INTEN_CODEOUTAVAILEN_SHIFT           (7U)
75458 /*! CODEOUTAVAILEN - PUF Code Output Register Interrupt Enable
75459  *  0b0..AC/KC available interrupt disabled
75460  *  0b1..AC/KC available interrupt enabled
75461  */
75462 #define PUF_INTEN_CODEOUTAVAILEN(x)              (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK)
75463 /*! @} */
75464 
75465 /*! @name INTSTAT - PUF Interrupt Status */
75466 /*! @{ */
75467 
75468 #define PUF_INTSTAT_READY_MASK                   (0x1U)
75469 #define PUF_INTSTAT_READY_SHIFT                  (0U)
75470 /*! READY - PUF_FINISH Interrupt Status
75471  *  0b0..Indicates that last operation not finished
75472  *  0b1..Indicates that last operation is finished
75473  */
75474 #define PUF_INTSTAT_READY(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK)
75475 
75476 #define PUF_INTSTAT_SUCCESS_MASK                 (0x2U)
75477 #define PUF_INTSTAT_SUCCESS_SHIFT                (1U)
75478 /*! SUCCESS - PUF_OK Interrupt Status
75479  *  0b0..Indicates that last operation was not successful
75480  *  0b1..Indicates that last operation was successful
75481  */
75482 #define PUF_INTSTAT_SUCCESS(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK)
75483 
75484 #define PUF_INTSTAT_ERROR_MASK                   (0x4U)
75485 #define PUF_INTSTAT_ERROR_SHIFT                  (2U)
75486 /*! ERROR - PUF_ERROR Interrupt Status
75487  *  0b0..PUF is not in the Error state and operations can be performed
75488  *  0b1..PUF is in the Error state and no operations can be performed
75489  */
75490 #define PUF_INTSTAT_ERROR(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK)
75491 
75492 #define PUF_INTSTAT_KEYINREQ_MASK                (0x10U)
75493 #define PUF_INTSTAT_KEYINREQ_SHIFT               (4U)
75494 /*! KEYINREQ - PUF Key Input Register Interrupt Status
75495  *  0b0..No request for next part of key
75496  *  0b1..Request for next part of key
75497  */
75498 #define PUF_INTSTAT_KEYINREQ(x)                  (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK)
75499 
75500 #define PUF_INTSTAT_KEYOUTAVAIL_MASK             (0x20U)
75501 #define PUF_INTSTAT_KEYOUTAVAIL_SHIFT            (5U)
75502 /*! KEYOUTAVAIL - PUF Key Output Register Interrupt Status
75503  *  0b0..Next part of key is not available
75504  *  0b1..Next part of key is available
75505  */
75506 #define PUF_INTSTAT_KEYOUTAVAIL(x)               (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK)
75507 
75508 #define PUF_INTSTAT_CODEINREQ_MASK               (0x40U)
75509 #define PUF_INTSTAT_CODEINREQ_SHIFT              (6U)
75510 /*! CODEINREQ - PUF Code Input Register Interrupt Status
75511  *  0b0..No request for next part of AC/KC
75512  *  0b1..Request for next part of AC/KC
75513  */
75514 #define PUF_INTSTAT_CODEINREQ(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK)
75515 
75516 #define PUF_INTSTAT_CODEOUTAVAIL_MASK            (0x80U)
75517 #define PUF_INTSTAT_CODEOUTAVAIL_SHIFT           (7U)
75518 /*! CODEOUTAVAIL - PUF Code Output Register Interrupt Status
75519  *  0b0..Next part of AC/KC is not available
75520  *  0b1..Next part of AC/KC is available
75521  */
75522 #define PUF_INTSTAT_CODEOUTAVAIL(x)              (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK)
75523 /*! @} */
75524 
75525 /*! @name PWRCTRL - PUF Power Control Of RAM */
75526 /*! @{ */
75527 
75528 #define PUF_PWRCTRL_RAM_ON_MASK                  (0x1U)
75529 #define PUF_PWRCTRL_RAM_ON_SHIFT                 (0U)
75530 /*! RAM_ON - PUF RAM on
75531  *  0b0..PUF RAM is in sleep mode (PUF operation disabled)
75532  *  0b1..PUF RAM is awake (normal PUF operation enabled)
75533  */
75534 #define PUF_PWRCTRL_RAM_ON(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_ON_SHIFT)) & PUF_PWRCTRL_RAM_ON_MASK)
75535 
75536 #define PUF_PWRCTRL_CK_DIS_MASK                  (0x4U)
75537 #define PUF_PWRCTRL_CK_DIS_SHIFT                 (2U)
75538 /*! CK_DIS - Clock disable
75539  *  0b0..PUF RAM is clocked (normal PUF operation enabled)
75540  *  0b1..PUF RAM clock is gated/disabled (PUF operation disabled)
75541  */
75542 #define PUF_PWRCTRL_CK_DIS(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_CK_DIS_SHIFT)) & PUF_PWRCTRL_CK_DIS_MASK)
75543 
75544 #define PUF_PWRCTRL_RAM_INITN_MASK               (0x8U)
75545 #define PUF_PWRCTRL_RAM_INITN_SHIFT              (3U)
75546 /*! RAM_INITN - RAM initialization
75547  *  0b0..Reset the PUF RAM (PUF operation disabled)
75548  *  0b1..Do not reset the PUF RAM (normal PUF operation enabled)
75549  */
75550 #define PUF_PWRCTRL_RAM_INITN(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_INITN_SHIFT)) & PUF_PWRCTRL_RAM_INITN_MASK)
75551 
75552 #define PUF_PWRCTRL_RAM_PSW_MASK                 (0xF0U)
75553 #define PUF_PWRCTRL_RAM_PSW_SHIFT                (4U)
75554 /*! RAM_PSW - PUF RAM power switches */
75555 #define PUF_PWRCTRL_RAM_PSW(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_PSW_SHIFT)) & PUF_PWRCTRL_RAM_PSW_MASK)
75556 /*! @} */
75557 
75558 /*! @name CFG - PUF Configuration Register */
75559 /*! @{ */
75560 
75561 #define PUF_CFG_PUF_BLOCK_SET_KEY_MASK           (0x1U)
75562 #define PUF_CFG_PUF_BLOCK_SET_KEY_SHIFT          (0U)
75563 /*! PUF_BLOCK_SET_KEY - PUF Block Set Key Disable
75564  *  0b0..Enable the Set Key state
75565  *  0b1..Disable the Set Key state
75566  */
75567 #define PUF_CFG_PUF_BLOCK_SET_KEY(x)             (((uint32_t)(((uint32_t)(x)) << PUF_CFG_PUF_BLOCK_SET_KEY_SHIFT)) & PUF_CFG_PUF_BLOCK_SET_KEY_MASK)
75568 
75569 #define PUF_CFG_PUF_BLOCK_ENROLL_MASK            (0x2U)
75570 #define PUF_CFG_PUF_BLOCK_ENROLL_SHIFT           (1U)
75571 /*! PUF_BLOCK_ENROLL - PUF Block Enroll Disable
75572  *  0b0..Enable the Enrollment state
75573  *  0b1..Disable the Enrollment state
75574  */
75575 #define PUF_CFG_PUF_BLOCK_ENROLL(x)              (((uint32_t)(((uint32_t)(x)) << PUF_CFG_PUF_BLOCK_ENROLL_SHIFT)) & PUF_CFG_PUF_BLOCK_ENROLL_MASK)
75576 /*! @} */
75577 
75578 /*! @name KEYLOCK - PUF Key Manager Lock */
75579 /*! @{ */
75580 
75581 #define PUF_KEYLOCK_LOCK0_MASK                   (0x3U)
75582 #define PUF_KEYLOCK_LOCK0_SHIFT                  (0U)
75583 /*! LOCK0 - Lock Block 0
75584  *  0b11..SNVS Key block locked
75585  *  0b10..SNVS Key block unlocked
75586  *  0b01..SNVS Key block locked
75587  *  0b00..SNVS Key block locked
75588  */
75589 #define PUF_KEYLOCK_LOCK0(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_LOCK0_SHIFT)) & PUF_KEYLOCK_LOCK0_MASK)
75590 
75591 #define PUF_KEYLOCK_LOCK1_MASK                   (0xCU)
75592 #define PUF_KEYLOCK_LOCK1_SHIFT                  (2U)
75593 /*! LOCK1 - Lock Block 1
75594  *  0b11..OTFAD Key block locked
75595  *  0b10..OTFAD Key block unlocked
75596  *  0b01..OTFAD Key block locked
75597  *  0b00..OTFAD Key block locked
75598  */
75599 #define PUF_KEYLOCK_LOCK1(x)                     (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_LOCK1_SHIFT)) & PUF_KEYLOCK_LOCK1_MASK)
75600 /*! @} */
75601 
75602 /*! @name KEYENABLE - PUF Key Manager Enable */
75603 /*! @{ */
75604 
75605 #define PUF_KEYENABLE_ENABLE0_MASK               (0x3U)
75606 #define PUF_KEYENABLE_ENABLE0_SHIFT              (0U)
75607 /*! ENABLE0 - Enable Block 0
75608  *  0b11..Key block 0 disabled
75609  *  0b10..Key block 0 enabled
75610  *  0b01..Key block 0 disabled
75611  *  0b00..Key block 0 disabled
75612  */
75613 #define PUF_KEYENABLE_ENABLE0(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_ENABLE0_SHIFT)) & PUF_KEYENABLE_ENABLE0_MASK)
75614 
75615 #define PUF_KEYENABLE_ENABLE1_MASK               (0xCU)
75616 #define PUF_KEYENABLE_ENABLE1_SHIFT              (2U)
75617 /*! ENABLE1 - Enable Block 1
75618  *  0b11..Key block 1 disabled
75619  *  0b10..Key block 1 enabled
75620  *  0b01..Key block 1 disabled
75621  *  0b00..Key block 1 disabled
75622  */
75623 #define PUF_KEYENABLE_ENABLE1(x)                 (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_ENABLE1_SHIFT)) & PUF_KEYENABLE_ENABLE1_MASK)
75624 /*! @} */
75625 
75626 /*! @name KEYRESET - PUF Key Manager Reset */
75627 /*! @{ */
75628 
75629 #define PUF_KEYRESET_RESET0_MASK                 (0x3U)
75630 #define PUF_KEYRESET_RESET0_SHIFT                (0U)
75631 /*! RESET0 - Reset Block 0
75632  *  0b11..Do not reset key block 0
75633  *  0b10..Reset key block 0
75634  *  0b01..Do not reset key block 0
75635  *  0b00..Do not reset key block 0
75636  */
75637 #define PUF_KEYRESET_RESET0(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_RESET0_SHIFT)) & PUF_KEYRESET_RESET0_MASK)
75638 
75639 #define PUF_KEYRESET_RESET1_MASK                 (0xCU)
75640 #define PUF_KEYRESET_RESET1_SHIFT                (2U)
75641 /*! RESET1 - Reset Block 1
75642  *  0b11..Do not reset key block 1
75643  *  0b10..Reset key block 1
75644  *  0b01..Do not reset key block 1
75645  *  0b00..Do not reset key block 1
75646  */
75647 #define PUF_KEYRESET_RESET1(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_RESET1_SHIFT)) & PUF_KEYRESET_RESET1_MASK)
75648 /*! @} */
75649 
75650 /*! @name IDXBLK - PUF Index Block Key Output */
75651 /*! @{ */
75652 
75653 #define PUF_IDXBLK_IDXBLK0_MASK                  (0x3U)
75654 #define PUF_IDXBLK_IDXBLK0_SHIFT                 (0U)
75655 /*! IDXBLK0 - idxblk0 */
75656 #define PUF_IDXBLK_IDXBLK0(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK0_SHIFT)) & PUF_IDXBLK_IDXBLK0_MASK)
75657 
75658 #define PUF_IDXBLK_IDXBLK1_MASK                  (0xCU)
75659 #define PUF_IDXBLK_IDXBLK1_SHIFT                 (2U)
75660 /*! IDXBLK1 - idxblk1 */
75661 #define PUF_IDXBLK_IDXBLK1(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK1_SHIFT)) & PUF_IDXBLK_IDXBLK1_MASK)
75662 
75663 #define PUF_IDXBLK_IDXBLK2_MASK                  (0x30U)
75664 #define PUF_IDXBLK_IDXBLK2_SHIFT                 (4U)
75665 /*! IDXBLK2 - idxblk2 */
75666 #define PUF_IDXBLK_IDXBLK2(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK2_SHIFT)) & PUF_IDXBLK_IDXBLK2_MASK)
75667 
75668 #define PUF_IDXBLK_IDXBLK3_MASK                  (0xC0U)
75669 #define PUF_IDXBLK_IDXBLK3_SHIFT                 (6U)
75670 /*! IDXBLK3 - idxblk3 */
75671 #define PUF_IDXBLK_IDXBLK3(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK3_SHIFT)) & PUF_IDXBLK_IDXBLK3_MASK)
75672 
75673 #define PUF_IDXBLK_IDXBLK4_MASK                  (0x300U)
75674 #define PUF_IDXBLK_IDXBLK4_SHIFT                 (8U)
75675 /*! IDXBLK4 - idxblk4 */
75676 #define PUF_IDXBLK_IDXBLK4(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK4_SHIFT)) & PUF_IDXBLK_IDXBLK4_MASK)
75677 
75678 #define PUF_IDXBLK_IDXBLK5_MASK                  (0xC00U)
75679 #define PUF_IDXBLK_IDXBLK5_SHIFT                 (10U)
75680 /*! IDXBLK5 - idxblk5 */
75681 #define PUF_IDXBLK_IDXBLK5(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK5_SHIFT)) & PUF_IDXBLK_IDXBLK5_MASK)
75682 
75683 #define PUF_IDXBLK_IDXBLK6_MASK                  (0x3000U)
75684 #define PUF_IDXBLK_IDXBLK6_SHIFT                 (12U)
75685 /*! IDXBLK6 - idxblk6 */
75686 #define PUF_IDXBLK_IDXBLK6(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK6_SHIFT)) & PUF_IDXBLK_IDXBLK6_MASK)
75687 
75688 #define PUF_IDXBLK_IDXBLK7_MASK                  (0xC000U)
75689 #define PUF_IDXBLK_IDXBLK7_SHIFT                 (14U)
75690 /*! IDXBLK7 - idxblk7 */
75691 #define PUF_IDXBLK_IDXBLK7(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK7_SHIFT)) & PUF_IDXBLK_IDXBLK7_MASK)
75692 
75693 #define PUF_IDXBLK_IDXBLK8_MASK                  (0x30000U)
75694 #define PUF_IDXBLK_IDXBLK8_SHIFT                 (16U)
75695 /*! IDXBLK8 - idxblk8 */
75696 #define PUF_IDXBLK_IDXBLK8(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK8_SHIFT)) & PUF_IDXBLK_IDXBLK8_MASK)
75697 
75698 #define PUF_IDXBLK_IDXBLK9_MASK                  (0xC0000U)
75699 #define PUF_IDXBLK_IDXBLK9_SHIFT                 (18U)
75700 /*! IDXBLK9 - idxblk9 */
75701 #define PUF_IDXBLK_IDXBLK9(x)                    (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK9_SHIFT)) & PUF_IDXBLK_IDXBLK9_MASK)
75702 
75703 #define PUF_IDXBLK_IDXBLK10_MASK                 (0x300000U)
75704 #define PUF_IDXBLK_IDXBLK10_SHIFT                (20U)
75705 /*! IDXBLK10 - idxblk10 */
75706 #define PUF_IDXBLK_IDXBLK10(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK10_SHIFT)) & PUF_IDXBLK_IDXBLK10_MASK)
75707 
75708 #define PUF_IDXBLK_IDXBLK11_MASK                 (0xC00000U)
75709 #define PUF_IDXBLK_IDXBLK11_SHIFT                (22U)
75710 /*! IDXBLK11 - idxblk11 */
75711 #define PUF_IDXBLK_IDXBLK11(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK11_SHIFT)) & PUF_IDXBLK_IDXBLK11_MASK)
75712 
75713 #define PUF_IDXBLK_IDXBLK12_MASK                 (0x3000000U)
75714 #define PUF_IDXBLK_IDXBLK12_SHIFT                (24U)
75715 /*! IDXBLK12 - idxblk12 */
75716 #define PUF_IDXBLK_IDXBLK12(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK12_SHIFT)) & PUF_IDXBLK_IDXBLK12_MASK)
75717 
75718 #define PUF_IDXBLK_IDXBLK13_MASK                 (0xC000000U)
75719 #define PUF_IDXBLK_IDXBLK13_SHIFT                (26U)
75720 /*! IDXBLK13 - idxblk13 */
75721 #define PUF_IDXBLK_IDXBLK13(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK13_SHIFT)) & PUF_IDXBLK_IDXBLK13_MASK)
75722 
75723 #define PUF_IDXBLK_IDXBLK14_MASK                 (0x30000000U)
75724 #define PUF_IDXBLK_IDXBLK14_SHIFT                (28U)
75725 /*! IDXBLK14 - idxblk14 */
75726 #define PUF_IDXBLK_IDXBLK14(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK14_SHIFT)) & PUF_IDXBLK_IDXBLK14_MASK)
75727 
75728 #define PUF_IDXBLK_IDXBLK15_MASK                 (0xC0000000U)
75729 #define PUF_IDXBLK_IDXBLK15_SHIFT                (30U)
75730 /*! IDXBLK15 - idxblk15 */
75731 #define PUF_IDXBLK_IDXBLK15(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK15_SHIFT)) & PUF_IDXBLK_IDXBLK15_MASK)
75732 /*! @} */
75733 
75734 /*! @name IDXBLK_DP - PUF Index Block Key Output */
75735 /*! @{ */
75736 
75737 #define PUF_IDXBLK_DP_IDXBLK_DP0_MASK            (0x3U)
75738 #define PUF_IDXBLK_DP_IDXBLK_DP0_SHIFT           (0U)
75739 /*! IDXBLK_DP0 - idxblk_dp0 */
75740 #define PUF_IDXBLK_DP_IDXBLK_DP0(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP0_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP0_MASK)
75741 
75742 #define PUF_IDXBLK_DP_IDXBLK_DP1_MASK            (0xCU)
75743 #define PUF_IDXBLK_DP_IDXBLK_DP1_SHIFT           (2U)
75744 /*! IDXBLK_DP1 - idxblk_dp1 */
75745 #define PUF_IDXBLK_DP_IDXBLK_DP1(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP1_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP1_MASK)
75746 
75747 #define PUF_IDXBLK_DP_IDXBLK_DP2_MASK            (0x30U)
75748 #define PUF_IDXBLK_DP_IDXBLK_DP2_SHIFT           (4U)
75749 /*! IDXBLK_DP2 - idxblk_dp2 */
75750 #define PUF_IDXBLK_DP_IDXBLK_DP2(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP2_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP2_MASK)
75751 
75752 #define PUF_IDXBLK_DP_IDXBLK_DP3_MASK            (0xC0U)
75753 #define PUF_IDXBLK_DP_IDXBLK_DP3_SHIFT           (6U)
75754 /*! IDXBLK_DP3 - idxblk_dp3 */
75755 #define PUF_IDXBLK_DP_IDXBLK_DP3(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP3_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP3_MASK)
75756 
75757 #define PUF_IDXBLK_DP_IDXBLK_DP4_MASK            (0x300U)
75758 #define PUF_IDXBLK_DP_IDXBLK_DP4_SHIFT           (8U)
75759 /*! IDXBLK_DP4 - idxblk_dp4 */
75760 #define PUF_IDXBLK_DP_IDXBLK_DP4(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP4_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP4_MASK)
75761 
75762 #define PUF_IDXBLK_DP_IDXBLK_DP5_MASK            (0xC00U)
75763 #define PUF_IDXBLK_DP_IDXBLK_DP5_SHIFT           (10U)
75764 /*! IDXBLK_DP5 - idxblk_dp5 */
75765 #define PUF_IDXBLK_DP_IDXBLK_DP5(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP5_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP5_MASK)
75766 
75767 #define PUF_IDXBLK_DP_IDXBLK_DP6_MASK            (0x3000U)
75768 #define PUF_IDXBLK_DP_IDXBLK_DP6_SHIFT           (12U)
75769 /*! IDXBLK_DP6 - idxblk_dp6 */
75770 #define PUF_IDXBLK_DP_IDXBLK_DP6(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP6_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP6_MASK)
75771 
75772 #define PUF_IDXBLK_DP_IDXBLK_DP7_MASK            (0xC000U)
75773 #define PUF_IDXBLK_DP_IDXBLK_DP7_SHIFT           (14U)
75774 /*! IDXBLK_DP7 - idxblk_dp7 */
75775 #define PUF_IDXBLK_DP_IDXBLK_DP7(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP7_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP7_MASK)
75776 
75777 #define PUF_IDXBLK_DP_IDXBLK_DP8_MASK            (0x30000U)
75778 #define PUF_IDXBLK_DP_IDXBLK_DP8_SHIFT           (16U)
75779 /*! IDXBLK_DP8 - idxblk_dp8 */
75780 #define PUF_IDXBLK_DP_IDXBLK_DP8(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP8_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP8_MASK)
75781 
75782 #define PUF_IDXBLK_DP_IDXBLK_DP9_MASK            (0xC0000U)
75783 #define PUF_IDXBLK_DP_IDXBLK_DP9_SHIFT           (18U)
75784 /*! IDXBLK_DP9 - idxblk_dp9 */
75785 #define PUF_IDXBLK_DP_IDXBLK_DP9(x)              (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP9_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP9_MASK)
75786 
75787 #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK           (0x300000U)
75788 #define PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT          (20U)
75789 /*! IDXBLK_DP10 - idxblk_dp10 */
75790 #define PUF_IDXBLK_DP_IDXBLK_DP10(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
75791 
75792 #define PUF_IDXBLK_DP_IDXBLK_DP11_MASK           (0xC00000U)
75793 #define PUF_IDXBLK_DP_IDXBLK_DP11_SHIFT          (22U)
75794 /*! IDXBLK_DP11 - idxblk_dp11 */
75795 #define PUF_IDXBLK_DP_IDXBLK_DP11(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP11_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP11_MASK)
75796 
75797 #define PUF_IDXBLK_DP_IDXBLK_DP12_MASK           (0x3000000U)
75798 #define PUF_IDXBLK_DP_IDXBLK_DP12_SHIFT          (24U)
75799 /*! IDXBLK_DP12 - idxblk_dp12 */
75800 #define PUF_IDXBLK_DP_IDXBLK_DP12(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP12_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP12_MASK)
75801 
75802 #define PUF_IDXBLK_DP_IDXBLK_DP13_MASK           (0xC000000U)
75803 #define PUF_IDXBLK_DP_IDXBLK_DP13_SHIFT          (26U)
75804 /*! IDXBLK_DP13 - idxblk_dp13 */
75805 #define PUF_IDXBLK_DP_IDXBLK_DP13(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP13_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP13_MASK)
75806 
75807 #define PUF_IDXBLK_DP_IDXBLK_DP14_MASK           (0x30000000U)
75808 #define PUF_IDXBLK_DP_IDXBLK_DP14_SHIFT          (28U)
75809 /*! IDXBLK_DP14 - idxblk_dp14 */
75810 #define PUF_IDXBLK_DP_IDXBLK_DP14(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP14_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP14_MASK)
75811 
75812 #define PUF_IDXBLK_DP_IDXBLK_DP15_MASK           (0xC0000000U)
75813 #define PUF_IDXBLK_DP_IDXBLK_DP15_SHIFT          (30U)
75814 /*! IDXBLK_DP15 - idxblk_dp15 */
75815 #define PUF_IDXBLK_DP_IDXBLK_DP15(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP15_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP15_MASK)
75816 /*! @} */
75817 
75818 /*! @name KEYMASK - PUF Key Block 0 Mask Enable..PUF Key Block 1 Mask Enable */
75819 /*! @{ */
75820 
75821 #define PUF_KEYMASK_KEYMASK_MASK                 (0xFFFFFFFFU)
75822 #define PUF_KEYMASK_KEYMASK_SHIFT                (0U)
75823 /*! KEYMASK - KEYMASK1 */
75824 #define PUF_KEYMASK_KEYMASK(x)                   (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK)
75825 /*! @} */
75826 
75827 /* The count of PUF_KEYMASK */
75828 #define PUF_KEYMASK_COUNT                        (2U)
75829 
75830 /*! @name IDXBLK_STATUS - PUF Index Block Setting Status Register */
75831 /*! @{ */
75832 
75833 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS0_MASK    (0x3U)
75834 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS0_SHIFT   (0U)
75835 /*! IDXBLK_STATUS0 - idxblk_status0 */
75836 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS0(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS0_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS0_MASK)
75837 
75838 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK    (0xCU)
75839 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT   (2U)
75840 /*! IDXBLK_STATUS1 - idxblk_status1 */
75841 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
75842 
75843 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS2_MASK    (0x30U)
75844 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS2_SHIFT   (4U)
75845 /*! IDXBLK_STATUS2 - idxblk_status2 */
75846 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS2(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS2_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS2_MASK)
75847 
75848 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS3_MASK    (0xC0U)
75849 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS3_SHIFT   (6U)
75850 /*! IDXBLK_STATUS3 - idxblk_status3 */
75851 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS3(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS3_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS3_MASK)
75852 
75853 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS4_MASK    (0x300U)
75854 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS4_SHIFT   (8U)
75855 /*! IDXBLK_STATUS4 - idxblk_status4 */
75856 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS4(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS4_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS4_MASK)
75857 
75858 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS5_MASK    (0xC00U)
75859 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS5_SHIFT   (10U)
75860 /*! IDXBLK_STATUS5 - idxblk_status5 */
75861 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS5(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS5_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS5_MASK)
75862 
75863 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS6_MASK    (0x3000U)
75864 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS6_SHIFT   (12U)
75865 /*! IDXBLK_STATUS6 - idxblk_status6 */
75866 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS6(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS6_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS6_MASK)
75867 
75868 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS7_MASK    (0xC000U)
75869 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS7_SHIFT   (14U)
75870 /*! IDXBLK_STATUS7 - idxblk_status7 */
75871 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS7(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS7_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS7_MASK)
75872 
75873 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS8_MASK    (0x30000U)
75874 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS8_SHIFT   (16U)
75875 /*! IDXBLK_STATUS8 - idxblk_status8 */
75876 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS8(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS8_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS8_MASK)
75877 
75878 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS9_MASK    (0xC0000U)
75879 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS9_SHIFT   (18U)
75880 /*! IDXBLK_STATUS9 - idxblk_status9 */
75881 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS9(x)      (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS9_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS9_MASK)
75882 
75883 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS10_MASK   (0x300000U)
75884 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS10_SHIFT  (20U)
75885 /*! IDXBLK_STATUS10 - idxblk_status10 */
75886 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS10(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS10_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS10_MASK)
75887 
75888 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS11_MASK   (0xC00000U)
75889 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS11_SHIFT  (22U)
75890 /*! IDXBLK_STATUS11 - idxblk_status11 */
75891 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS11(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS11_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS11_MASK)
75892 
75893 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS12_MASK   (0x3000000U)
75894 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS12_SHIFT  (24U)
75895 /*! IDXBLK_STATUS12 - idxblk_status12 */
75896 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS12(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS12_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS12_MASK)
75897 
75898 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS13_MASK   (0xC000000U)
75899 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS13_SHIFT  (26U)
75900 /*! IDXBLK_STATUS13 - idxblk_status13 */
75901 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS13(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS13_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS13_MASK)
75902 
75903 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS14_MASK   (0x30000000U)
75904 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS14_SHIFT  (28U)
75905 /*! IDXBLK_STATUS14 - idxblk_status14 */
75906 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS14(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS14_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS14_MASK)
75907 
75908 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS15_MASK   (0xC0000000U)
75909 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS15_SHIFT  (30U)
75910 /*! IDXBLK_STATUS15 - idxblk_status15 */
75911 #define PUF_IDXBLK_STATUS_IDXBLK_STATUS15(x)     (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS15_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS15_MASK)
75912 /*! @} */
75913 
75914 /*! @name IDXBLK_SHIFT - PUF Key Manager Shift Status */
75915 /*! @{ */
75916 
75917 #define PUF_IDXBLK_SHIFT_IND_KEY0_MASK           (0xFU)
75918 #define PUF_IDXBLK_SHIFT_IND_KEY0_SHIFT          (0U)
75919 /*! IND_KEY0 - Index of key space in block 0 */
75920 #define PUF_IDXBLK_SHIFT_IND_KEY0(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_SHIFT_IND_KEY0_SHIFT)) & PUF_IDXBLK_SHIFT_IND_KEY0_MASK)
75921 
75922 #define PUF_IDXBLK_SHIFT_IND_KEY1_MASK           (0xF0U)
75923 #define PUF_IDXBLK_SHIFT_IND_KEY1_SHIFT          (4U)
75924 /*! IND_KEY1 - Index of key space in block 1 */
75925 #define PUF_IDXBLK_SHIFT_IND_KEY1(x)             (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_SHIFT_IND_KEY1_SHIFT)) & PUF_IDXBLK_SHIFT_IND_KEY1_MASK)
75926 /*! @} */
75927 
75928 
75929 /*!
75930  * @}
75931  */ /* end of group PUF_Register_Masks */
75932 
75933 
75934 /* PUF - Peripheral instance base addresses */
75935 /** Peripheral KEY_MANAGER__PUF base address */
75936 #define KEY_MANAGER__PUF_BASE                    (0x40C82000u)
75937 /** Peripheral KEY_MANAGER__PUF base pointer */
75938 #define KEY_MANAGER__PUF                         ((PUF_Type *)KEY_MANAGER__PUF_BASE)
75939 /** Array initializer of PUF peripheral base addresses */
75940 #define PUF_BASE_ADDRS                           { KEY_MANAGER__PUF_BASE }
75941 /** Array initializer of PUF peripheral base pointers */
75942 #define PUF_BASE_PTRS                            { KEY_MANAGER__PUF }
75943 
75944 /*!
75945  * @}
75946  */ /* end of group PUF_Peripheral_Access_Layer */
75947 
75948 
75949 /* ----------------------------------------------------------------------------
75950    -- PWM Peripheral Access Layer
75951    ---------------------------------------------------------------------------- */
75952 
75953 /*!
75954  * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
75955  * @{
75956  */
75957 
75958 /** PWM - Register Layout Typedef */
75959 typedef struct {
75960   struct {                                         /* offset: 0x0, array step: 0x60 */
75961     __I  uint16_t CNT;                               /**< Counter Register, array offset: 0x0, array step: 0x60 */
75962     __IO uint16_t INIT;                              /**< Initial Count Register, array offset: 0x2, array step: 0x60 */
75963     __IO uint16_t CTRL2;                             /**< Control 2 Register, array offset: 0x4, array step: 0x60 */
75964     __IO uint16_t CTRL;                              /**< Control Register, array offset: 0x6, array step: 0x60 */
75965          uint8_t RESERVED_0[2];
75966     __IO uint16_t VAL0;                              /**< Value Register 0, array offset: 0xA, array step: 0x60 */
75967     __IO uint16_t FRACVAL1;                          /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */
75968     __IO uint16_t VAL1;                              /**< Value Register 1, array offset: 0xE, array step: 0x60 */
75969     __IO uint16_t FRACVAL2;                          /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */
75970     __IO uint16_t VAL2;                              /**< Value Register 2, array offset: 0x12, array step: 0x60 */
75971     __IO uint16_t FRACVAL3;                          /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */
75972     __IO uint16_t VAL3;                              /**< Value Register 3, array offset: 0x16, array step: 0x60 */
75973     __IO uint16_t FRACVAL4;                          /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */
75974     __IO uint16_t VAL4;                              /**< Value Register 4, array offset: 0x1A, array step: 0x60 */
75975     __IO uint16_t FRACVAL5;                          /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */
75976     __IO uint16_t VAL5;                              /**< Value Register 5, array offset: 0x1E, array step: 0x60 */
75977     __IO uint16_t FRCTRL;                            /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */
75978     __IO uint16_t OCTRL;                             /**< Output Control Register, array offset: 0x22, array step: 0x60 */
75979     __IO uint16_t STS;                               /**< Status Register, array offset: 0x24, array step: 0x60 */
75980     __IO uint16_t INTEN;                             /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */
75981     __IO uint16_t DMAEN;                             /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */
75982     __IO uint16_t TCTRL;                             /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */
75983     __IO uint16_t DISMAP[1];                         /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */
75984          uint8_t RESERVED_1[2];
75985     __IO uint16_t DTCNT0;                            /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */
75986     __IO uint16_t DTCNT1;                            /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */
75987     __IO uint16_t CAPTCTRLA;                         /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */
75988     __IO uint16_t CAPTCOMPA;                         /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */
75989     __IO uint16_t CAPTCTRLB;                         /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */
75990     __IO uint16_t CAPTCOMPB;                         /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */
75991     __IO uint16_t CAPTCTRLX;                         /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */
75992     __IO uint16_t CAPTCOMPX;                         /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */
75993     __I  uint16_t CVAL0;                             /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */
75994     __I  uint16_t CVAL0CYC;                          /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */
75995     __I  uint16_t CVAL1;                             /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */
75996     __I  uint16_t CVAL1CYC;                          /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */
75997     __I  uint16_t CVAL2;                             /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */
75998     __I  uint16_t CVAL2CYC;                          /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */
75999     __I  uint16_t CVAL3;                             /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */
76000     __I  uint16_t CVAL3CYC;                          /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */
76001     __I  uint16_t CVAL4;                             /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */
76002     __I  uint16_t CVAL4CYC;                          /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */
76003     __I  uint16_t CVAL5;                             /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */
76004     __I  uint16_t CVAL5CYC;                          /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */
76005          uint8_t RESERVED_2[8];
76006   } SM[4];
76007   __IO uint16_t OUTEN;                             /**< Output Enable Register, offset: 0x180 */
76008   __IO uint16_t MASK;                              /**< Mask Register, offset: 0x182 */
76009   __IO uint16_t SWCOUT;                            /**< Software Controlled Output Register, offset: 0x184 */
76010   __IO uint16_t DTSRCSEL;                          /**< PWM Source Select Register, offset: 0x186 */
76011   __IO uint16_t MCTRL;                             /**< Master Control Register, offset: 0x188 */
76012        uint8_t RESERVED_0[2];
76013   __IO uint16_t FCTRL;                             /**< Fault Control Register, offset: 0x18C */
76014   __IO uint16_t FSTS;                              /**< Fault Status Register, offset: 0x18E */
76015   __IO uint16_t FFILT;                             /**< Fault Filter Register, offset: 0x190 */
76016   __IO uint16_t FTST;                              /**< Fault Test Register, offset: 0x192 */
76017   __IO uint16_t FCTRL2;                            /**< Fault Control 2 Register, offset: 0x194 */
76018 } PWM_Type;
76019 
76020 /* ----------------------------------------------------------------------------
76021    -- PWM Register Masks
76022    ---------------------------------------------------------------------------- */
76023 
76024 /*!
76025  * @addtogroup PWM_Register_Masks PWM Register Masks
76026  * @{
76027  */
76028 
76029 /*! @name CNT - Counter Register */
76030 /*! @{ */
76031 
76032 #define PWM_CNT_CNT_MASK                         (0xFFFFU)
76033 #define PWM_CNT_CNT_SHIFT                        (0U)
76034 /*! CNT - Counter Register Bits */
76035 #define PWM_CNT_CNT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
76036 /*! @} */
76037 
76038 /* The count of PWM_CNT */
76039 #define PWM_CNT_COUNT                            (4U)
76040 
76041 /*! @name INIT - Initial Count Register */
76042 /*! @{ */
76043 
76044 #define PWM_INIT_INIT_MASK                       (0xFFFFU)
76045 #define PWM_INIT_INIT_SHIFT                      (0U)
76046 /*! INIT - Initial Count Register Bits */
76047 #define PWM_INIT_INIT(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
76048 /*! @} */
76049 
76050 /* The count of PWM_INIT */
76051 #define PWM_INIT_COUNT                           (4U)
76052 
76053 /*! @name CTRL2 - Control 2 Register */
76054 /*! @{ */
76055 
76056 #define PWM_CTRL2_CLK_SEL_MASK                   (0x3U)
76057 #define PWM_CTRL2_CLK_SEL_SHIFT                  (0U)
76058 /*! CLK_SEL - Clock Source Select
76059  *  0b00..The IPBus clock is used as the clock for the local prescaler and counter.
76060  *  0b01..EXT_CLK is used as the clock for the local prescaler and counter.
76061  *  0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This
76062  *        setting should not be used in submodule 0 as it forces the clock to logic 0.
76063  *  0b11..Reserved
76064  */
76065 #define PWM_CTRL2_CLK_SEL(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
76066 
76067 #define PWM_CTRL2_RELOAD_SEL_MASK                (0x4U)
76068 #define PWM_CTRL2_RELOAD_SEL_SHIFT               (2U)
76069 /*! RELOAD_SEL - Reload Source Select
76070  *  0b0..The local RELOAD signal is used to reload registers.
76071  *  0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used
76072  *       in submodule 0 as it forces the RELOAD signal to logic 0.
76073  */
76074 #define PWM_CTRL2_RELOAD_SEL(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
76075 
76076 #define PWM_CTRL2_FORCE_SEL_MASK                 (0x38U)
76077 #define PWM_CTRL2_FORCE_SEL_SHIFT                (3U)
76078 /*! FORCE_SEL - Force Select
76079  *  0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
76080  *  0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in
76081  *         submodule 0 as it holds the FORCE OUTPUT signal to logic 0.
76082  *  0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
76083  *  0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should
76084  *         not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0.
76085  *  0b100..The local sync signal from this submodule is used to force updates.
76086  *  0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in
76087  *         submodule0 as it holds the FORCE OUTPUT signal to logic 0.
76088  *  0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates.
76089  *  0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
76090  */
76091 #define PWM_CTRL2_FORCE_SEL(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
76092 
76093 #define PWM_CTRL2_FORCE_MASK                     (0x40U)
76094 #define PWM_CTRL2_FORCE_SHIFT                    (6U)
76095 /*! FORCE - Force Initialization */
76096 #define PWM_CTRL2_FORCE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
76097 
76098 #define PWM_CTRL2_FRCEN_MASK                     (0x80U)
76099 #define PWM_CTRL2_FRCEN_SHIFT                    (7U)
76100 /*! FRCEN - Force Enable
76101  *  0b0..Initialization from a FORCE_OUT is disabled.
76102  *  0b1..Initialization from a FORCE_OUT is enabled.
76103  */
76104 #define PWM_CTRL2_FRCEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
76105 
76106 #define PWM_CTRL2_INIT_SEL_MASK                  (0x300U)
76107 #define PWM_CTRL2_INIT_SEL_SHIFT                 (8U)
76108 /*! INIT_SEL - Initialization Control Select
76109  *  0b00..Local sync (PWM_X) causes initialization.
76110  *  0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as
76111  *        it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload
76112  *        occurs.
76113  *  0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0.
76114  *  0b11..EXT_SYNC causes initialization.
76115  */
76116 #define PWM_CTRL2_INIT_SEL(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
76117 
76118 #define PWM_CTRL2_PWMX_INIT_MASK                 (0x400U)
76119 #define PWM_CTRL2_PWMX_INIT_SHIFT                (10U)
76120 /*! PWMX_INIT - PWM_X Initial Value */
76121 #define PWM_CTRL2_PWMX_INIT(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
76122 
76123 #define PWM_CTRL2_PWM45_INIT_MASK                (0x800U)
76124 #define PWM_CTRL2_PWM45_INIT_SHIFT               (11U)
76125 /*! PWM45_INIT - PWM45 Initial Value */
76126 #define PWM_CTRL2_PWM45_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
76127 
76128 #define PWM_CTRL2_PWM23_INIT_MASK                (0x1000U)
76129 #define PWM_CTRL2_PWM23_INIT_SHIFT               (12U)
76130 /*! PWM23_INIT - PWM23 Initial Value */
76131 #define PWM_CTRL2_PWM23_INIT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
76132 
76133 #define PWM_CTRL2_INDEP_MASK                     (0x2000U)
76134 #define PWM_CTRL2_INDEP_SHIFT                    (13U)
76135 /*! INDEP - Independent or Complementary Pair Operation
76136  *  0b0..PWM_A and PWM_B form a complementary PWM pair.
76137  *  0b1..PWM_A and PWM_B outputs are independent PWMs.
76138  */
76139 #define PWM_CTRL2_INDEP(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
76140 
76141 #define PWM_CTRL2_WAITEN_MASK                    (0x4000U)
76142 #define PWM_CTRL2_WAITEN_SHIFT                   (14U)
76143 /*! WAITEN - Wait Enable */
76144 #define PWM_CTRL2_WAITEN(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
76145 
76146 #define PWM_CTRL2_DBGEN_MASK                     (0x8000U)
76147 #define PWM_CTRL2_DBGEN_SHIFT                    (15U)
76148 /*! DBGEN - Debug Enable */
76149 #define PWM_CTRL2_DBGEN(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
76150 /*! @} */
76151 
76152 /* The count of PWM_CTRL2 */
76153 #define PWM_CTRL2_COUNT                          (4U)
76154 
76155 /*! @name CTRL - Control Register */
76156 /*! @{ */
76157 
76158 #define PWM_CTRL_DBLEN_MASK                      (0x1U)
76159 #define PWM_CTRL_DBLEN_SHIFT                     (0U)
76160 /*! DBLEN - Double Switching Enable
76161  *  0b0..Double switching disabled.
76162  *  0b1..Double switching enabled.
76163  */
76164 #define PWM_CTRL_DBLEN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
76165 
76166 #define PWM_CTRL_DBLX_MASK                       (0x2U)
76167 #define PWM_CTRL_DBLX_SHIFT                      (1U)
76168 /*! DBLX - PWM_X Double Switching Enable
76169  *  0b0..PWM_X double pulse disabled.
76170  *  0b1..PWM_X double pulse enabled.
76171  */
76172 #define PWM_CTRL_DBLX(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
76173 
76174 #define PWM_CTRL_LDMOD_MASK                      (0x4U)
76175 #define PWM_CTRL_LDMOD_SHIFT                     (2U)
76176 /*! LDMOD - Load Mode Select
76177  *  0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
76178  *  0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set.
76179  *       In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF].
76180  */
76181 #define PWM_CTRL_LDMOD(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
76182 
76183 #define PWM_CTRL_SPLIT_MASK                      (0x8U)
76184 #define PWM_CTRL_SPLIT_SHIFT                     (3U)
76185 /*! SPLIT - Split the DBLPWM signal to PWM_A and PWM_B
76186  *  0b0..DBLPWM is not split. PWM_A and PWM_B each have double pulses.
76187  *  0b1..DBLPWM is split to PWM_A and PWM_B.
76188  */
76189 #define PWM_CTRL_SPLIT(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
76190 
76191 #define PWM_CTRL_PRSC_MASK                       (0x70U)
76192 #define PWM_CTRL_PRSC_SHIFT                      (4U)
76193 /*! PRSC - Prescaler
76194  *  0b000..Prescaler 1
76195  *  0b001..Prescaler 2
76196  *  0b010..Prescaler 4
76197  *  0b011..Prescaler 8
76198  *  0b100..Prescaler 16
76199  *  0b101..Prescaler 32
76200  *  0b110..Prescaler 64
76201  *  0b111..Prescaler 128
76202  */
76203 #define PWM_CTRL_PRSC(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
76204 
76205 #define PWM_CTRL_COMPMODE_MASK                   (0x80U)
76206 #define PWM_CTRL_COMPMODE_SHIFT                  (7U)
76207 /*! COMPMODE - Compare Mode
76208  *  0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges
76209  *       are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A
76210  *       output that is high at the end of a period maintains this state until a match with VAL3 clears the output
76211  *       in the following period.
76212  *  0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This
76213  *       means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register
76214  *       values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the
76215  *       next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
76216  */
76217 #define PWM_CTRL_COMPMODE(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
76218 
76219 #define PWM_CTRL_DT_MASK                         (0x300U)
76220 #define PWM_CTRL_DT_SHIFT                        (8U)
76221 /*! DT - Deadtime */
76222 #define PWM_CTRL_DT(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
76223 
76224 #define PWM_CTRL_FULL_MASK                       (0x400U)
76225 #define PWM_CTRL_FULL_SHIFT                      (10U)
76226 /*! FULL - Full Cycle Reload
76227  *  0b0..Full-cycle reloads disabled.
76228  *  0b1..Full-cycle reloads enabled.
76229  */
76230 #define PWM_CTRL_FULL(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
76231 
76232 #define PWM_CTRL_HALF_MASK                       (0x800U)
76233 #define PWM_CTRL_HALF_SHIFT                      (11U)
76234 /*! HALF - Half Cycle Reload
76235  *  0b0..Half-cycle reloads disabled.
76236  *  0b1..Half-cycle reloads enabled.
76237  */
76238 #define PWM_CTRL_HALF(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
76239 
76240 #define PWM_CTRL_LDFQ_MASK                       (0xF000U)
76241 #define PWM_CTRL_LDFQ_SHIFT                      (12U)
76242 /*! LDFQ - Load Frequency
76243  *  0b0000..Every PWM opportunity
76244  *  0b0001..Every 2 PWM opportunities
76245  *  0b0010..Every 3 PWM opportunities
76246  *  0b0011..Every 4 PWM opportunities
76247  *  0b0100..Every 5 PWM opportunities
76248  *  0b0101..Every 6 PWM opportunities
76249  *  0b0110..Every 7 PWM opportunities
76250  *  0b0111..Every 8 PWM opportunities
76251  *  0b1000..Every 9 PWM opportunities
76252  *  0b1001..Every 10 PWM opportunities
76253  *  0b1010..Every 11 PWM opportunities
76254  *  0b1011..Every 12 PWM opportunities
76255  *  0b1100..Every 13 PWM opportunities
76256  *  0b1101..Every 14 PWM opportunities
76257  *  0b1110..Every 15 PWM opportunities
76258  *  0b1111..Every 16 PWM opportunities
76259  */
76260 #define PWM_CTRL_LDFQ(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
76261 /*! @} */
76262 
76263 /* The count of PWM_CTRL */
76264 #define PWM_CTRL_COUNT                           (4U)
76265 
76266 /*! @name VAL0 - Value Register 0 */
76267 /*! @{ */
76268 
76269 #define PWM_VAL0_VAL0_MASK                       (0xFFFFU)
76270 #define PWM_VAL0_VAL0_SHIFT                      (0U)
76271 /*! VAL0 - Value 0 */
76272 #define PWM_VAL0_VAL0(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
76273 /*! @} */
76274 
76275 /* The count of PWM_VAL0 */
76276 #define PWM_VAL0_COUNT                           (4U)
76277 
76278 /*! @name FRACVAL1 - Fractional Value Register 1 */
76279 /*! @{ */
76280 
76281 #define PWM_FRACVAL1_FRACVAL1_MASK               (0xF800U)
76282 #define PWM_FRACVAL1_FRACVAL1_SHIFT              (11U)
76283 /*! FRACVAL1 - Fractional Value 1 */
76284 #define PWM_FRACVAL1_FRACVAL1(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
76285 /*! @} */
76286 
76287 /* The count of PWM_FRACVAL1 */
76288 #define PWM_FRACVAL1_COUNT                       (4U)
76289 
76290 /*! @name VAL1 - Value Register 1 */
76291 /*! @{ */
76292 
76293 #define PWM_VAL1_VAL1_MASK                       (0xFFFFU)
76294 #define PWM_VAL1_VAL1_SHIFT                      (0U)
76295 /*! VAL1 - Value 1 */
76296 #define PWM_VAL1_VAL1(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
76297 /*! @} */
76298 
76299 /* The count of PWM_VAL1 */
76300 #define PWM_VAL1_COUNT                           (4U)
76301 
76302 /*! @name FRACVAL2 - Fractional Value Register 2 */
76303 /*! @{ */
76304 
76305 #define PWM_FRACVAL2_FRACVAL2_MASK               (0xF800U)
76306 #define PWM_FRACVAL2_FRACVAL2_SHIFT              (11U)
76307 /*! FRACVAL2 - Fractional Value 2 */
76308 #define PWM_FRACVAL2_FRACVAL2(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
76309 /*! @} */
76310 
76311 /* The count of PWM_FRACVAL2 */
76312 #define PWM_FRACVAL2_COUNT                       (4U)
76313 
76314 /*! @name VAL2 - Value Register 2 */
76315 /*! @{ */
76316 
76317 #define PWM_VAL2_VAL2_MASK                       (0xFFFFU)
76318 #define PWM_VAL2_VAL2_SHIFT                      (0U)
76319 /*! VAL2 - Value 2 */
76320 #define PWM_VAL2_VAL2(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
76321 /*! @} */
76322 
76323 /* The count of PWM_VAL2 */
76324 #define PWM_VAL2_COUNT                           (4U)
76325 
76326 /*! @name FRACVAL3 - Fractional Value Register 3 */
76327 /*! @{ */
76328 
76329 #define PWM_FRACVAL3_FRACVAL3_MASK               (0xF800U)
76330 #define PWM_FRACVAL3_FRACVAL3_SHIFT              (11U)
76331 /*! FRACVAL3 - Fractional Value 3 */
76332 #define PWM_FRACVAL3_FRACVAL3(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
76333 /*! @} */
76334 
76335 /* The count of PWM_FRACVAL3 */
76336 #define PWM_FRACVAL3_COUNT                       (4U)
76337 
76338 /*! @name VAL3 - Value Register 3 */
76339 /*! @{ */
76340 
76341 #define PWM_VAL3_VAL3_MASK                       (0xFFFFU)
76342 #define PWM_VAL3_VAL3_SHIFT                      (0U)
76343 /*! VAL3 - Value 3 */
76344 #define PWM_VAL3_VAL3(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
76345 /*! @} */
76346 
76347 /* The count of PWM_VAL3 */
76348 #define PWM_VAL3_COUNT                           (4U)
76349 
76350 /*! @name FRACVAL4 - Fractional Value Register 4 */
76351 /*! @{ */
76352 
76353 #define PWM_FRACVAL4_FRACVAL4_MASK               (0xF800U)
76354 #define PWM_FRACVAL4_FRACVAL4_SHIFT              (11U)
76355 /*! FRACVAL4 - Fractional Value 4 */
76356 #define PWM_FRACVAL4_FRACVAL4(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
76357 /*! @} */
76358 
76359 /* The count of PWM_FRACVAL4 */
76360 #define PWM_FRACVAL4_COUNT                       (4U)
76361 
76362 /*! @name VAL4 - Value Register 4 */
76363 /*! @{ */
76364 
76365 #define PWM_VAL4_VAL4_MASK                       (0xFFFFU)
76366 #define PWM_VAL4_VAL4_SHIFT                      (0U)
76367 /*! VAL4 - Value 4 */
76368 #define PWM_VAL4_VAL4(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
76369 /*! @} */
76370 
76371 /* The count of PWM_VAL4 */
76372 #define PWM_VAL4_COUNT                           (4U)
76373 
76374 /*! @name FRACVAL5 - Fractional Value Register 5 */
76375 /*! @{ */
76376 
76377 #define PWM_FRACVAL5_FRACVAL5_MASK               (0xF800U)
76378 #define PWM_FRACVAL5_FRACVAL5_SHIFT              (11U)
76379 /*! FRACVAL5 - Fractional Value 5 */
76380 #define PWM_FRACVAL5_FRACVAL5(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
76381 /*! @} */
76382 
76383 /* The count of PWM_FRACVAL5 */
76384 #define PWM_FRACVAL5_COUNT                       (4U)
76385 
76386 /*! @name VAL5 - Value Register 5 */
76387 /*! @{ */
76388 
76389 #define PWM_VAL5_VAL5_MASK                       (0xFFFFU)
76390 #define PWM_VAL5_VAL5_SHIFT                      (0U)
76391 /*! VAL5 - Value 5 */
76392 #define PWM_VAL5_VAL5(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
76393 /*! @} */
76394 
76395 /* The count of PWM_VAL5 */
76396 #define PWM_VAL5_COUNT                           (4U)
76397 
76398 /*! @name FRCTRL - Fractional Control Register */
76399 /*! @{ */
76400 
76401 #define PWM_FRCTRL_FRAC1_EN_MASK                 (0x2U)
76402 #define PWM_FRCTRL_FRAC1_EN_SHIFT                (1U)
76403 /*! FRAC1_EN - Fractional Cycle PWM Period Enable
76404  *  0b0..Disable fractional cycle length for the PWM period.
76405  *  0b1..Enable fractional cycle length for the PWM period.
76406  */
76407 #define PWM_FRCTRL_FRAC1_EN(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
76408 
76409 #define PWM_FRCTRL_FRAC23_EN_MASK                (0x4U)
76410 #define PWM_FRCTRL_FRAC23_EN_SHIFT               (2U)
76411 /*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A
76412  *  0b0..Disable fractional cycle placement for PWM_A.
76413  *  0b1..Enable fractional cycle placement for PWM_A.
76414  */
76415 #define PWM_FRCTRL_FRAC23_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
76416 
76417 #define PWM_FRCTRL_FRAC45_EN_MASK                (0x10U)
76418 #define PWM_FRCTRL_FRAC45_EN_SHIFT               (4U)
76419 /*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B
76420  *  0b0..Disable fractional cycle placement for PWM_B.
76421  *  0b1..Enable fractional cycle placement for PWM_B.
76422  */
76423 #define PWM_FRCTRL_FRAC45_EN(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
76424 
76425 #define PWM_FRCTRL_TEST_MASK                     (0x8000U)
76426 #define PWM_FRCTRL_TEST_SHIFT                    (15U)
76427 /*! TEST - Test Status Bit */
76428 #define PWM_FRCTRL_TEST(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
76429 /*! @} */
76430 
76431 /* The count of PWM_FRCTRL */
76432 #define PWM_FRCTRL_COUNT                         (4U)
76433 
76434 /*! @name OCTRL - Output Control Register */
76435 /*! @{ */
76436 
76437 #define PWM_OCTRL_PWMXFS_MASK                    (0x3U)
76438 #define PWM_OCTRL_PWMXFS_SHIFT                   (0U)
76439 /*! PWMXFS - PWM_X Fault State
76440  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
76441  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
76442  *  0b10, 0b11..Output is put in a high-impedance state.
76443  */
76444 #define PWM_OCTRL_PWMXFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
76445 
76446 #define PWM_OCTRL_PWMBFS_MASK                    (0xCU)
76447 #define PWM_OCTRL_PWMBFS_SHIFT                   (2U)
76448 /*! PWMBFS - PWM_B Fault State
76449  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
76450  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
76451  *  0b10, 0b11..Output is put in a high-impedance state.
76452  */
76453 #define PWM_OCTRL_PWMBFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
76454 
76455 #define PWM_OCTRL_PWMAFS_MASK                    (0x30U)
76456 #define PWM_OCTRL_PWMAFS_SHIFT                   (4U)
76457 /*! PWMAFS - PWM_A Fault State
76458  *  0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
76459  *  0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
76460  *  0b10, 0b11..Output is put in a high-impedance state.
76461  */
76462 #define PWM_OCTRL_PWMAFS(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
76463 
76464 #define PWM_OCTRL_POLX_MASK                      (0x100U)
76465 #define PWM_OCTRL_POLX_SHIFT                     (8U)
76466 /*! POLX - PWM_X Output Polarity
76467  *  0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
76468  *  0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
76469  */
76470 #define PWM_OCTRL_POLX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
76471 
76472 #define PWM_OCTRL_POLB_MASK                      (0x200U)
76473 #define PWM_OCTRL_POLB_SHIFT                     (9U)
76474 /*! POLB - PWM_B Output Polarity
76475  *  0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
76476  *  0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
76477  */
76478 #define PWM_OCTRL_POLB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
76479 
76480 #define PWM_OCTRL_POLA_MASK                      (0x400U)
76481 #define PWM_OCTRL_POLA_SHIFT                     (10U)
76482 /*! POLA - PWM_A Output Polarity
76483  *  0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
76484  *  0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
76485  */
76486 #define PWM_OCTRL_POLA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
76487 
76488 #define PWM_OCTRL_PWMX_IN_MASK                   (0x2000U)
76489 #define PWM_OCTRL_PWMX_IN_SHIFT                  (13U)
76490 /*! PWMX_IN - PWM_X Input */
76491 #define PWM_OCTRL_PWMX_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
76492 
76493 #define PWM_OCTRL_PWMB_IN_MASK                   (0x4000U)
76494 #define PWM_OCTRL_PWMB_IN_SHIFT                  (14U)
76495 /*! PWMB_IN - PWM_B Input */
76496 #define PWM_OCTRL_PWMB_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
76497 
76498 #define PWM_OCTRL_PWMA_IN_MASK                   (0x8000U)
76499 #define PWM_OCTRL_PWMA_IN_SHIFT                  (15U)
76500 /*! PWMA_IN - PWM_A Input */
76501 #define PWM_OCTRL_PWMA_IN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
76502 /*! @} */
76503 
76504 /* The count of PWM_OCTRL */
76505 #define PWM_OCTRL_COUNT                          (4U)
76506 
76507 /*! @name STS - Status Register */
76508 /*! @{ */
76509 
76510 #define PWM_STS_CMPF_MASK                        (0x3FU)
76511 #define PWM_STS_CMPF_SHIFT                       (0U)
76512 /*! CMPF - Compare Flags
76513  *  0b000000..No compare event has occurred for a particular VALx value.
76514  *  0b000001..A compare event has occurred for a particular VALx value.
76515  */
76516 #define PWM_STS_CMPF(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
76517 
76518 #define PWM_STS_CFX0_MASK                        (0x40U)
76519 #define PWM_STS_CFX0_SHIFT                       (6U)
76520 /*! CFX0 - Capture Flag X0 */
76521 #define PWM_STS_CFX0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
76522 
76523 #define PWM_STS_CFX1_MASK                        (0x80U)
76524 #define PWM_STS_CFX1_SHIFT                       (7U)
76525 /*! CFX1 - Capture Flag X1 */
76526 #define PWM_STS_CFX1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
76527 
76528 #define PWM_STS_CFB0_MASK                        (0x100U)
76529 #define PWM_STS_CFB0_SHIFT                       (8U)
76530 /*! CFB0 - Capture Flag B0 */
76531 #define PWM_STS_CFB0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
76532 
76533 #define PWM_STS_CFB1_MASK                        (0x200U)
76534 #define PWM_STS_CFB1_SHIFT                       (9U)
76535 /*! CFB1 - Capture Flag B1 */
76536 #define PWM_STS_CFB1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
76537 
76538 #define PWM_STS_CFA0_MASK                        (0x400U)
76539 #define PWM_STS_CFA0_SHIFT                       (10U)
76540 /*! CFA0 - Capture Flag A0 */
76541 #define PWM_STS_CFA0(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
76542 
76543 #define PWM_STS_CFA1_MASK                        (0x800U)
76544 #define PWM_STS_CFA1_SHIFT                       (11U)
76545 /*! CFA1 - Capture Flag A1 */
76546 #define PWM_STS_CFA1(x)                          (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
76547 
76548 #define PWM_STS_RF_MASK                          (0x1000U)
76549 #define PWM_STS_RF_SHIFT                         (12U)
76550 /*! RF - Reload Flag
76551  *  0b0..No new reload cycle since last STS[RF] clearing
76552  *  0b1..New reload cycle since last STS[RF] clearing
76553  */
76554 #define PWM_STS_RF(x)                            (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
76555 
76556 #define PWM_STS_REF_MASK                         (0x2000U)
76557 #define PWM_STS_REF_SHIFT                        (13U)
76558 /*! REF - Reload Error Flag
76559  *  0b0..No reload error occurred.
76560  *  0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
76561  */
76562 #define PWM_STS_REF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
76563 
76564 #define PWM_STS_RUF_MASK                         (0x4000U)
76565 #define PWM_STS_RUF_SHIFT                        (14U)
76566 /*! RUF - Registers Updated Flag
76567  *  0b0..No register update has occurred since last reload.
76568  *  0b1..At least one of the double buffered registers has been updated since the last reload.
76569  */
76570 #define PWM_STS_RUF(x)                           (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
76571 /*! @} */
76572 
76573 /* The count of PWM_STS */
76574 #define PWM_STS_COUNT                            (4U)
76575 
76576 /*! @name INTEN - Interrupt Enable Register */
76577 /*! @{ */
76578 
76579 #define PWM_INTEN_CMPIE_MASK                     (0x3FU)
76580 #define PWM_INTEN_CMPIE_SHIFT                    (0U)
76581 /*! CMPIE - Compare Interrupt Enables
76582  *  0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request.
76583  *  0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
76584  */
76585 #define PWM_INTEN_CMPIE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
76586 
76587 #define PWM_INTEN_CX0IE_MASK                     (0x40U)
76588 #define PWM_INTEN_CX0IE_SHIFT                    (6U)
76589 /*! CX0IE - Capture X 0 Interrupt Enable
76590  *  0b0..Interrupt request disabled for STS[CFX0].
76591  *  0b1..Interrupt request enabled for STS[CFX0].
76592  */
76593 #define PWM_INTEN_CX0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
76594 
76595 #define PWM_INTEN_CX1IE_MASK                     (0x80U)
76596 #define PWM_INTEN_CX1IE_SHIFT                    (7U)
76597 /*! CX1IE - Capture X 1 Interrupt Enable
76598  *  0b0..Interrupt request disabled for STS[CFX1].
76599  *  0b1..Interrupt request enabled for STS[CFX1].
76600  */
76601 #define PWM_INTEN_CX1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
76602 
76603 #define PWM_INTEN_CB0IE_MASK                     (0x100U)
76604 #define PWM_INTEN_CB0IE_SHIFT                    (8U)
76605 /*! CB0IE - Capture B 0 Interrupt Enable
76606  *  0b0..Interrupt request disabled for STS[CFB0].
76607  *  0b1..Interrupt request enabled for STS[CFB0].
76608  */
76609 #define PWM_INTEN_CB0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
76610 
76611 #define PWM_INTEN_CB1IE_MASK                     (0x200U)
76612 #define PWM_INTEN_CB1IE_SHIFT                    (9U)
76613 /*! CB1IE - Capture B 1 Interrupt Enable
76614  *  0b0..Interrupt request disabled for STS[CFB1].
76615  *  0b1..Interrupt request enabled for STS[CFB1].
76616  */
76617 #define PWM_INTEN_CB1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
76618 
76619 #define PWM_INTEN_CA0IE_MASK                     (0x400U)
76620 #define PWM_INTEN_CA0IE_SHIFT                    (10U)
76621 /*! CA0IE - Capture A 0 Interrupt Enable
76622  *  0b0..Interrupt request disabled for STS[CFA0].
76623  *  0b1..Interrupt request enabled for STS[CFA0].
76624  */
76625 #define PWM_INTEN_CA0IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
76626 
76627 #define PWM_INTEN_CA1IE_MASK                     (0x800U)
76628 #define PWM_INTEN_CA1IE_SHIFT                    (11U)
76629 /*! CA1IE - Capture A 1 Interrupt Enable
76630  *  0b0..Interrupt request disabled for STS[CFA1]
76631  *  0b1..Interrupt request enabled for STS[CFA1]
76632  */
76633 #define PWM_INTEN_CA1IE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
76634 
76635 #define PWM_INTEN_RIE_MASK                       (0x1000U)
76636 #define PWM_INTEN_RIE_SHIFT                      (12U)
76637 /*! RIE - Reload Interrupt Enable
76638  *  0b0..STS[RF] CPU interrupt requests disabled
76639  *  0b1..STS[RF] CPU interrupt requests enabled
76640  */
76641 #define PWM_INTEN_RIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
76642 
76643 #define PWM_INTEN_REIE_MASK                      (0x2000U)
76644 #define PWM_INTEN_REIE_SHIFT                     (13U)
76645 /*! REIE - Reload Error Interrupt Enable
76646  *  0b0..STS[REF] CPU interrupt requests disabled
76647  *  0b1..STS[REF] CPU interrupt requests enabled
76648  */
76649 #define PWM_INTEN_REIE(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
76650 /*! @} */
76651 
76652 /* The count of PWM_INTEN */
76653 #define PWM_INTEN_COUNT                          (4U)
76654 
76655 /*! @name DMAEN - DMA Enable Register */
76656 /*! @{ */
76657 
76658 #define PWM_DMAEN_CX0DE_MASK                     (0x1U)
76659 #define PWM_DMAEN_CX0DE_SHIFT                    (0U)
76660 /*! CX0DE - Capture X0 FIFO DMA Enable */
76661 #define PWM_DMAEN_CX0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
76662 
76663 #define PWM_DMAEN_CX1DE_MASK                     (0x2U)
76664 #define PWM_DMAEN_CX1DE_SHIFT                    (1U)
76665 /*! CX1DE - Capture X1 FIFO DMA Enable */
76666 #define PWM_DMAEN_CX1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
76667 
76668 #define PWM_DMAEN_CB0DE_MASK                     (0x4U)
76669 #define PWM_DMAEN_CB0DE_SHIFT                    (2U)
76670 /*! CB0DE - Capture B0 FIFO DMA Enable */
76671 #define PWM_DMAEN_CB0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
76672 
76673 #define PWM_DMAEN_CB1DE_MASK                     (0x8U)
76674 #define PWM_DMAEN_CB1DE_SHIFT                    (3U)
76675 /*! CB1DE - Capture B1 FIFO DMA Enable */
76676 #define PWM_DMAEN_CB1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
76677 
76678 #define PWM_DMAEN_CA0DE_MASK                     (0x10U)
76679 #define PWM_DMAEN_CA0DE_SHIFT                    (4U)
76680 /*! CA0DE - Capture A0 FIFO DMA Enable */
76681 #define PWM_DMAEN_CA0DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
76682 
76683 #define PWM_DMAEN_CA1DE_MASK                     (0x20U)
76684 #define PWM_DMAEN_CA1DE_SHIFT                    (5U)
76685 /*! CA1DE - Capture A1 FIFO DMA Enable */
76686 #define PWM_DMAEN_CA1DE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
76687 
76688 #define PWM_DMAEN_CAPTDE_MASK                    (0xC0U)
76689 #define PWM_DMAEN_CAPTDE_SHIFT                   (6U)
76690 /*! CAPTDE - Capture DMA Enable Source Select
76691  *  0b00..Read DMA requests disabled.
76692  *  0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE],
76693  *        DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to be set to determine which
76694  *        watermark(s) the DMA request is sensitive.
76695  *  0b10..A local synchronization (VAL1 matches counter) sets the read DMA request.
76696  *  0b11..A local reload (STS[RF] being set) sets the read DMA request.
76697  */
76698 #define PWM_DMAEN_CAPTDE(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
76699 
76700 #define PWM_DMAEN_FAND_MASK                      (0x100U)
76701 #define PWM_DMAEN_FAND_SHIFT                     (8U)
76702 /*! FAND - FIFO Watermark AND Control
76703  *  0b0..Selected FIFO watermarks are OR'ed together.
76704  *  0b1..Selected FIFO watermarks are AND'ed together.
76705  */
76706 #define PWM_DMAEN_FAND(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
76707 
76708 #define PWM_DMAEN_VALDE_MASK                     (0x200U)
76709 #define PWM_DMAEN_VALDE_SHIFT                    (9U)
76710 /*! VALDE - Value Registers DMA Enable
76711  *  0b0..DMA write requests disabled
76712  *  0b1..Enabled
76713  */
76714 #define PWM_DMAEN_VALDE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
76715 /*! @} */
76716 
76717 /* The count of PWM_DMAEN */
76718 #define PWM_DMAEN_COUNT                          (4U)
76719 
76720 /*! @name TCTRL - Output Trigger Control Register */
76721 /*! @{ */
76722 
76723 #define PWM_TCTRL_OUT_TRIG_EN_MASK               (0x3FU)
76724 #define PWM_TCTRL_OUT_TRIG_EN_SHIFT              (0U)
76725 /*! OUT_TRIG_EN - Output Trigger Enables
76726  *  0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.
76727  *  0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value.
76728  *  0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value.
76729  *  0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value.
76730  *  0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value.
76731  *  0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value.
76732  */
76733 #define PWM_TCTRL_OUT_TRIG_EN(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
76734 
76735 #define PWM_TCTRL_TRGFRQ_MASK                    (0x1000U)
76736 #define PWM_TCTRL_TRGFRQ_SHIFT                   (12U)
76737 /*! TRGFRQ - Trigger Frequency
76738  *  0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
76739  *  0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM
76740  *       is not reloaded every period due to CTRL[LDFQ] being non-zero.
76741  */
76742 #define PWM_TCTRL_TRGFRQ(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
76743 
76744 #define PWM_TCTRL_PWBOT1_MASK                    (0x4000U)
76745 #define PWM_TCTRL_PWBOT1_SHIFT                   (14U)
76746 /*! PWBOT1 - Output Trigger 1 Source Select
76747  *  0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.
76748  *  0b1..Route the PWM_B output to the PWM_OUT_TRIG1 port.
76749  */
76750 #define PWM_TCTRL_PWBOT1(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
76751 
76752 #define PWM_TCTRL_PWAOT0_MASK                    (0x8000U)
76753 #define PWM_TCTRL_PWAOT0_SHIFT                   (15U)
76754 /*! PWAOT0 - Output Trigger 0 Source Select
76755  *  0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.
76756  *  0b1..Route the PWM_A output to the PWM_OUT_TRIG0 port.
76757  */
76758 #define PWM_TCTRL_PWAOT0(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
76759 /*! @} */
76760 
76761 /* The count of PWM_TCTRL */
76762 #define PWM_TCTRL_COUNT                          (4U)
76763 
76764 /*! @name DISMAP - Fault Disable Mapping Register 0 */
76765 /*! @{ */
76766 
76767 #define PWM_DISMAP_DIS0A_MASK                    (0xFU)
76768 #define PWM_DISMAP_DIS0A_SHIFT                   (0U)
76769 /*! DIS0A - PWM_A Fault Disable Mask 0 */
76770 #define PWM_DISMAP_DIS0A(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
76771 
76772 #define PWM_DISMAP_DIS0B_MASK                    (0xF0U)
76773 #define PWM_DISMAP_DIS0B_SHIFT                   (4U)
76774 /*! DIS0B - PWM_B Fault Disable Mask 0 */
76775 #define PWM_DISMAP_DIS0B(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
76776 
76777 #define PWM_DISMAP_DIS0X_MASK                    (0xF00U)
76778 #define PWM_DISMAP_DIS0X_SHIFT                   (8U)
76779 /*! DIS0X - PWM_X Fault Disable Mask 0 */
76780 #define PWM_DISMAP_DIS0X(x)                      (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
76781 /*! @} */
76782 
76783 /* The count of PWM_DISMAP */
76784 #define PWM_DISMAP_COUNT                         (4U)
76785 
76786 /* The count of PWM_DISMAP */
76787 #define PWM_DISMAP_COUNT2                        (1U)
76788 
76789 /*! @name DTCNT0 - Deadtime Count Register 0 */
76790 /*! @{ */
76791 
76792 #define PWM_DTCNT0_DTCNT0_MASK                   (0xFFFFU)
76793 #define PWM_DTCNT0_DTCNT0_SHIFT                  (0U)
76794 /*! DTCNT0 - DTCNT0 */
76795 #define PWM_DTCNT0_DTCNT0(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
76796 /*! @} */
76797 
76798 /* The count of PWM_DTCNT0 */
76799 #define PWM_DTCNT0_COUNT                         (4U)
76800 
76801 /*! @name DTCNT1 - Deadtime Count Register 1 */
76802 /*! @{ */
76803 
76804 #define PWM_DTCNT1_DTCNT1_MASK                   (0xFFFFU)
76805 #define PWM_DTCNT1_DTCNT1_SHIFT                  (0U)
76806 /*! DTCNT1 - DTCNT1 */
76807 #define PWM_DTCNT1_DTCNT1(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
76808 /*! @} */
76809 
76810 /* The count of PWM_DTCNT1 */
76811 #define PWM_DTCNT1_COUNT                         (4U)
76812 
76813 /*! @name CAPTCTRLA - Capture Control A Register */
76814 /*! @{ */
76815 
76816 #define PWM_CAPTCTRLA_ARMA_MASK                  (0x1U)
76817 #define PWM_CAPTCTRLA_ARMA_SHIFT                 (0U)
76818 /*! ARMA - Arm A
76819  *  0b0..Input capture operation is disabled.
76820  *  0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.
76821  */
76822 #define PWM_CAPTCTRLA_ARMA(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
76823 
76824 #define PWM_CAPTCTRLA_ONESHOTA_MASK              (0x2U)
76825 #define PWM_CAPTCTRLA_ONESHOTA_SHIFT             (1U)
76826 /*! ONESHOTA - One Shot Mode A
76827  *  0b0..Free Running
76828  *  0b1..One Shot
76829  */
76830 #define PWM_CAPTCTRLA_ONESHOTA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
76831 
76832 #define PWM_CAPTCTRLA_EDGA0_MASK                 (0xCU)
76833 #define PWM_CAPTCTRLA_EDGA0_SHIFT                (2U)
76834 /*! EDGA0 - Edge A 0
76835  *  0b00..Disabled
76836  *  0b01..Capture falling edges
76837  *  0b10..Capture rising edges
76838  *  0b11..Capture any edge
76839  */
76840 #define PWM_CAPTCTRLA_EDGA0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
76841 
76842 #define PWM_CAPTCTRLA_EDGA1_MASK                 (0x30U)
76843 #define PWM_CAPTCTRLA_EDGA1_SHIFT                (4U)
76844 /*! EDGA1 - Edge A 1
76845  *  0b00..Disabled
76846  *  0b01..Capture falling edges
76847  *  0b10..Capture rising edges
76848  *  0b11..Capture any edge
76849  */
76850 #define PWM_CAPTCTRLA_EDGA1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
76851 
76852 #define PWM_CAPTCTRLA_INP_SELA_MASK              (0x40U)
76853 #define PWM_CAPTCTRLA_INP_SELA_SHIFT             (6U)
76854 /*! INP_SELA - Input Select A
76855  *  0b0..Raw PWM_A input signal selected as source.
76856  *  0b1..Edge Counter
76857  */
76858 #define PWM_CAPTCTRLA_INP_SELA(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
76859 
76860 #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK            (0x80U)
76861 #define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT           (7U)
76862 /*! EDGCNTA_EN - Edge Counter A Enable
76863  *  0b0..Edge counter disabled and held in reset
76864  *  0b1..Edge counter enabled
76865  */
76866 #define PWM_CAPTCTRLA_EDGCNTA_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
76867 
76868 #define PWM_CAPTCTRLA_CFAWM_MASK                 (0x300U)
76869 #define PWM_CAPTCTRLA_CFAWM_SHIFT                (8U)
76870 /*! CFAWM - Capture A FIFOs Water Mark */
76871 #define PWM_CAPTCTRLA_CFAWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
76872 
76873 #define PWM_CAPTCTRLA_CA0CNT_MASK                (0x1C00U)
76874 #define PWM_CAPTCTRLA_CA0CNT_SHIFT               (10U)
76875 /*! CA0CNT - Capture A0 FIFO Word Count */
76876 #define PWM_CAPTCTRLA_CA0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
76877 
76878 #define PWM_CAPTCTRLA_CA1CNT_MASK                (0xE000U)
76879 #define PWM_CAPTCTRLA_CA1CNT_SHIFT               (13U)
76880 /*! CA1CNT - Capture A1 FIFO Word Count */
76881 #define PWM_CAPTCTRLA_CA1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
76882 /*! @} */
76883 
76884 /* The count of PWM_CAPTCTRLA */
76885 #define PWM_CAPTCTRLA_COUNT                      (4U)
76886 
76887 /*! @name CAPTCOMPA - Capture Compare A Register */
76888 /*! @{ */
76889 
76890 #define PWM_CAPTCOMPA_EDGCMPA_MASK               (0xFFU)
76891 #define PWM_CAPTCOMPA_EDGCMPA_SHIFT              (0U)
76892 /*! EDGCMPA - Edge Compare A */
76893 #define PWM_CAPTCOMPA_EDGCMPA(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
76894 
76895 #define PWM_CAPTCOMPA_EDGCNTA_MASK               (0xFF00U)
76896 #define PWM_CAPTCOMPA_EDGCNTA_SHIFT              (8U)
76897 /*! EDGCNTA - Edge Counter A */
76898 #define PWM_CAPTCOMPA_EDGCNTA(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
76899 /*! @} */
76900 
76901 /* The count of PWM_CAPTCOMPA */
76902 #define PWM_CAPTCOMPA_COUNT                      (4U)
76903 
76904 /*! @name CAPTCTRLB - Capture Control B Register */
76905 /*! @{ */
76906 
76907 #define PWM_CAPTCTRLB_ARMB_MASK                  (0x1U)
76908 #define PWM_CAPTCTRLB_ARMB_SHIFT                 (0U)
76909 /*! ARMB - Arm B
76910  *  0b0..Input capture operation is disabled.
76911  *  0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.
76912  */
76913 #define PWM_CAPTCTRLB_ARMB(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
76914 
76915 #define PWM_CAPTCTRLB_ONESHOTB_MASK              (0x2U)
76916 #define PWM_CAPTCTRLB_ONESHOTB_SHIFT             (1U)
76917 /*! ONESHOTB - One Shot Mode B
76918  *  0b0..Free Running
76919  *  0b1..One Shot
76920  */
76921 #define PWM_CAPTCTRLB_ONESHOTB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
76922 
76923 #define PWM_CAPTCTRLB_EDGB0_MASK                 (0xCU)
76924 #define PWM_CAPTCTRLB_EDGB0_SHIFT                (2U)
76925 /*! EDGB0 - Edge B 0
76926  *  0b00..Disabled
76927  *  0b01..Capture falling edges
76928  *  0b10..Capture rising edges
76929  *  0b11..Capture any edge
76930  */
76931 #define PWM_CAPTCTRLB_EDGB0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
76932 
76933 #define PWM_CAPTCTRLB_EDGB1_MASK                 (0x30U)
76934 #define PWM_CAPTCTRLB_EDGB1_SHIFT                (4U)
76935 /*! EDGB1 - Edge B 1
76936  *  0b00..Disabled
76937  *  0b01..Capture falling edges
76938  *  0b10..Capture rising edges
76939  *  0b11..Capture any edge
76940  */
76941 #define PWM_CAPTCTRLB_EDGB1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
76942 
76943 #define PWM_CAPTCTRLB_INP_SELB_MASK              (0x40U)
76944 #define PWM_CAPTCTRLB_INP_SELB_SHIFT             (6U)
76945 /*! INP_SELB - Input Select B
76946  *  0b0..Raw PWM_B input signal selected as source.
76947  *  0b1..Edge Counter
76948  */
76949 #define PWM_CAPTCTRLB_INP_SELB(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
76950 
76951 #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK            (0x80U)
76952 #define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT           (7U)
76953 /*! EDGCNTB_EN - Edge Counter B Enable
76954  *  0b0..Edge counter disabled and held in reset
76955  *  0b1..Edge counter enabled
76956  */
76957 #define PWM_CAPTCTRLB_EDGCNTB_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
76958 
76959 #define PWM_CAPTCTRLB_CFBWM_MASK                 (0x300U)
76960 #define PWM_CAPTCTRLB_CFBWM_SHIFT                (8U)
76961 /*! CFBWM - Capture B FIFOs Water Mark */
76962 #define PWM_CAPTCTRLB_CFBWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
76963 
76964 #define PWM_CAPTCTRLB_CB0CNT_MASK                (0x1C00U)
76965 #define PWM_CAPTCTRLB_CB0CNT_SHIFT               (10U)
76966 /*! CB0CNT - Capture B0 FIFO Word Count */
76967 #define PWM_CAPTCTRLB_CB0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
76968 
76969 #define PWM_CAPTCTRLB_CB1CNT_MASK                (0xE000U)
76970 #define PWM_CAPTCTRLB_CB1CNT_SHIFT               (13U)
76971 /*! CB1CNT - Capture B1 FIFO Word Count */
76972 #define PWM_CAPTCTRLB_CB1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
76973 /*! @} */
76974 
76975 /* The count of PWM_CAPTCTRLB */
76976 #define PWM_CAPTCTRLB_COUNT                      (4U)
76977 
76978 /*! @name CAPTCOMPB - Capture Compare B Register */
76979 /*! @{ */
76980 
76981 #define PWM_CAPTCOMPB_EDGCMPB_MASK               (0xFFU)
76982 #define PWM_CAPTCOMPB_EDGCMPB_SHIFT              (0U)
76983 /*! EDGCMPB - Edge Compare B */
76984 #define PWM_CAPTCOMPB_EDGCMPB(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
76985 
76986 #define PWM_CAPTCOMPB_EDGCNTB_MASK               (0xFF00U)
76987 #define PWM_CAPTCOMPB_EDGCNTB_SHIFT              (8U)
76988 /*! EDGCNTB - Edge Counter B */
76989 #define PWM_CAPTCOMPB_EDGCNTB(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
76990 /*! @} */
76991 
76992 /* The count of PWM_CAPTCOMPB */
76993 #define PWM_CAPTCOMPB_COUNT                      (4U)
76994 
76995 /*! @name CAPTCTRLX - Capture Control X Register */
76996 /*! @{ */
76997 
76998 #define PWM_CAPTCTRLX_ARMX_MASK                  (0x1U)
76999 #define PWM_CAPTCTRLX_ARMX_SHIFT                 (0U)
77000 /*! ARMX - Arm X
77001  *  0b0..Input capture operation is disabled.
77002  *  0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
77003  */
77004 #define PWM_CAPTCTRLX_ARMX(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
77005 
77006 #define PWM_CAPTCTRLX_ONESHOTX_MASK              (0x2U)
77007 #define PWM_CAPTCTRLX_ONESHOTX_SHIFT             (1U)
77008 /*! ONESHOTX - One Shot Mode Aux
77009  *  0b0..Free Running
77010  *  0b1..One Shot
77011  */
77012 #define PWM_CAPTCTRLX_ONESHOTX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
77013 
77014 #define PWM_CAPTCTRLX_EDGX0_MASK                 (0xCU)
77015 #define PWM_CAPTCTRLX_EDGX0_SHIFT                (2U)
77016 /*! EDGX0 - Edge X 0
77017  *  0b00..Disabled
77018  *  0b01..Capture falling edges
77019  *  0b10..Capture rising edges
77020  *  0b11..Capture any edge
77021  */
77022 #define PWM_CAPTCTRLX_EDGX0(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
77023 
77024 #define PWM_CAPTCTRLX_EDGX1_MASK                 (0x30U)
77025 #define PWM_CAPTCTRLX_EDGX1_SHIFT                (4U)
77026 /*! EDGX1 - Edge X 1
77027  *  0b00..Disabled
77028  *  0b01..Capture falling edges
77029  *  0b10..Capture rising edges
77030  *  0b11..Capture any edge
77031  */
77032 #define PWM_CAPTCTRLX_EDGX1(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
77033 
77034 #define PWM_CAPTCTRLX_INP_SELX_MASK              (0x40U)
77035 #define PWM_CAPTCTRLX_INP_SELX_SHIFT             (6U)
77036 /*! INP_SELX - Input Select X
77037  *  0b0..Raw PWM_X input signal selected as source.
77038  *  0b1..Edge Counter
77039  */
77040 #define PWM_CAPTCTRLX_INP_SELX(x)                (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
77041 
77042 #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK            (0x80U)
77043 #define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT           (7U)
77044 /*! EDGCNTX_EN - Edge Counter X Enable
77045  *  0b0..Edge counter disabled and held in reset
77046  *  0b1..Edge counter enabled
77047  */
77048 #define PWM_CAPTCTRLX_EDGCNTX_EN(x)              (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
77049 
77050 #define PWM_CAPTCTRLX_CFXWM_MASK                 (0x300U)
77051 #define PWM_CAPTCTRLX_CFXWM_SHIFT                (8U)
77052 /*! CFXWM - Capture X FIFOs Water Mark */
77053 #define PWM_CAPTCTRLX_CFXWM(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
77054 
77055 #define PWM_CAPTCTRLX_CX0CNT_MASK                (0x1C00U)
77056 #define PWM_CAPTCTRLX_CX0CNT_SHIFT               (10U)
77057 /*! CX0CNT - Capture X0 FIFO Word Count */
77058 #define PWM_CAPTCTRLX_CX0CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
77059 
77060 #define PWM_CAPTCTRLX_CX1CNT_MASK                (0xE000U)
77061 #define PWM_CAPTCTRLX_CX1CNT_SHIFT               (13U)
77062 /*! CX1CNT - Capture X1 FIFO Word Count */
77063 #define PWM_CAPTCTRLX_CX1CNT(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
77064 /*! @} */
77065 
77066 /* The count of PWM_CAPTCTRLX */
77067 #define PWM_CAPTCTRLX_COUNT                      (4U)
77068 
77069 /*! @name CAPTCOMPX - Capture Compare X Register */
77070 /*! @{ */
77071 
77072 #define PWM_CAPTCOMPX_EDGCMPX_MASK               (0xFFU)
77073 #define PWM_CAPTCOMPX_EDGCMPX_SHIFT              (0U)
77074 /*! EDGCMPX - Edge Compare X */
77075 #define PWM_CAPTCOMPX_EDGCMPX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
77076 
77077 #define PWM_CAPTCOMPX_EDGCNTX_MASK               (0xFF00U)
77078 #define PWM_CAPTCOMPX_EDGCNTX_SHIFT              (8U)
77079 /*! EDGCNTX - Edge Counter X */
77080 #define PWM_CAPTCOMPX_EDGCNTX(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
77081 /*! @} */
77082 
77083 /* The count of PWM_CAPTCOMPX */
77084 #define PWM_CAPTCOMPX_COUNT                      (4U)
77085 
77086 /*! @name CVAL0 - Capture Value 0 Register */
77087 /*! @{ */
77088 
77089 #define PWM_CVAL0_CAPTVAL0_MASK                  (0xFFFFU)
77090 #define PWM_CVAL0_CAPTVAL0_SHIFT                 (0U)
77091 /*! CAPTVAL0 - Capture Value 0 */
77092 #define PWM_CVAL0_CAPTVAL0(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
77093 /*! @} */
77094 
77095 /* The count of PWM_CVAL0 */
77096 #define PWM_CVAL0_COUNT                          (4U)
77097 
77098 /*! @name CVAL0CYC - Capture Value 0 Cycle Register */
77099 /*! @{ */
77100 
77101 #define PWM_CVAL0CYC_CVAL0CYC_MASK               (0xFU)
77102 #define PWM_CVAL0CYC_CVAL0CYC_SHIFT              (0U)
77103 /*! CVAL0CYC - Capture Value 0 Cycle */
77104 #define PWM_CVAL0CYC_CVAL0CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
77105 /*! @} */
77106 
77107 /* The count of PWM_CVAL0CYC */
77108 #define PWM_CVAL0CYC_COUNT                       (4U)
77109 
77110 /*! @name CVAL1 - Capture Value 1 Register */
77111 /*! @{ */
77112 
77113 #define PWM_CVAL1_CAPTVAL1_MASK                  (0xFFFFU)
77114 #define PWM_CVAL1_CAPTVAL1_SHIFT                 (0U)
77115 /*! CAPTVAL1 - Capture Value 1 */
77116 #define PWM_CVAL1_CAPTVAL1(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
77117 /*! @} */
77118 
77119 /* The count of PWM_CVAL1 */
77120 #define PWM_CVAL1_COUNT                          (4U)
77121 
77122 /*! @name CVAL1CYC - Capture Value 1 Cycle Register */
77123 /*! @{ */
77124 
77125 #define PWM_CVAL1CYC_CVAL1CYC_MASK               (0xFU)
77126 #define PWM_CVAL1CYC_CVAL1CYC_SHIFT              (0U)
77127 /*! CVAL1CYC - Capture Value 1 Cycle */
77128 #define PWM_CVAL1CYC_CVAL1CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
77129 /*! @} */
77130 
77131 /* The count of PWM_CVAL1CYC */
77132 #define PWM_CVAL1CYC_COUNT                       (4U)
77133 
77134 /*! @name CVAL2 - Capture Value 2 Register */
77135 /*! @{ */
77136 
77137 #define PWM_CVAL2_CAPTVAL2_MASK                  (0xFFFFU)
77138 #define PWM_CVAL2_CAPTVAL2_SHIFT                 (0U)
77139 /*! CAPTVAL2 - Capture Value 2 */
77140 #define PWM_CVAL2_CAPTVAL2(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
77141 /*! @} */
77142 
77143 /* The count of PWM_CVAL2 */
77144 #define PWM_CVAL2_COUNT                          (4U)
77145 
77146 /*! @name CVAL2CYC - Capture Value 2 Cycle Register */
77147 /*! @{ */
77148 
77149 #define PWM_CVAL2CYC_CVAL2CYC_MASK               (0xFU)
77150 #define PWM_CVAL2CYC_CVAL2CYC_SHIFT              (0U)
77151 /*! CVAL2CYC - Capture Value 2 Cycle */
77152 #define PWM_CVAL2CYC_CVAL2CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
77153 /*! @} */
77154 
77155 /* The count of PWM_CVAL2CYC */
77156 #define PWM_CVAL2CYC_COUNT                       (4U)
77157 
77158 /*! @name CVAL3 - Capture Value 3 Register */
77159 /*! @{ */
77160 
77161 #define PWM_CVAL3_CAPTVAL3_MASK                  (0xFFFFU)
77162 #define PWM_CVAL3_CAPTVAL3_SHIFT                 (0U)
77163 /*! CAPTVAL3 - Capture Value 3 */
77164 #define PWM_CVAL3_CAPTVAL3(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
77165 /*! @} */
77166 
77167 /* The count of PWM_CVAL3 */
77168 #define PWM_CVAL3_COUNT                          (4U)
77169 
77170 /*! @name CVAL3CYC - Capture Value 3 Cycle Register */
77171 /*! @{ */
77172 
77173 #define PWM_CVAL3CYC_CVAL3CYC_MASK               (0xFU)
77174 #define PWM_CVAL3CYC_CVAL3CYC_SHIFT              (0U)
77175 /*! CVAL3CYC - Capture Value 3 Cycle */
77176 #define PWM_CVAL3CYC_CVAL3CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
77177 /*! @} */
77178 
77179 /* The count of PWM_CVAL3CYC */
77180 #define PWM_CVAL3CYC_COUNT                       (4U)
77181 
77182 /*! @name CVAL4 - Capture Value 4 Register */
77183 /*! @{ */
77184 
77185 #define PWM_CVAL4_CAPTVAL4_MASK                  (0xFFFFU)
77186 #define PWM_CVAL4_CAPTVAL4_SHIFT                 (0U)
77187 /*! CAPTVAL4 - Capture Value 4 */
77188 #define PWM_CVAL4_CAPTVAL4(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
77189 /*! @} */
77190 
77191 /* The count of PWM_CVAL4 */
77192 #define PWM_CVAL4_COUNT                          (4U)
77193 
77194 /*! @name CVAL4CYC - Capture Value 4 Cycle Register */
77195 /*! @{ */
77196 
77197 #define PWM_CVAL4CYC_CVAL4CYC_MASK               (0xFU)
77198 #define PWM_CVAL4CYC_CVAL4CYC_SHIFT              (0U)
77199 /*! CVAL4CYC - Capture Value 4 Cycle */
77200 #define PWM_CVAL4CYC_CVAL4CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
77201 /*! @} */
77202 
77203 /* The count of PWM_CVAL4CYC */
77204 #define PWM_CVAL4CYC_COUNT                       (4U)
77205 
77206 /*! @name CVAL5 - Capture Value 5 Register */
77207 /*! @{ */
77208 
77209 #define PWM_CVAL5_CAPTVAL5_MASK                  (0xFFFFU)
77210 #define PWM_CVAL5_CAPTVAL5_SHIFT                 (0U)
77211 /*! CAPTVAL5 - Capture Value 5 */
77212 #define PWM_CVAL5_CAPTVAL5(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
77213 /*! @} */
77214 
77215 /* The count of PWM_CVAL5 */
77216 #define PWM_CVAL5_COUNT                          (4U)
77217 
77218 /*! @name CVAL5CYC - Capture Value 5 Cycle Register */
77219 /*! @{ */
77220 
77221 #define PWM_CVAL5CYC_CVAL5CYC_MASK               (0xFU)
77222 #define PWM_CVAL5CYC_CVAL5CYC_SHIFT              (0U)
77223 /*! CVAL5CYC - Capture Value 5 Cycle */
77224 #define PWM_CVAL5CYC_CVAL5CYC(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
77225 /*! @} */
77226 
77227 /* The count of PWM_CVAL5CYC */
77228 #define PWM_CVAL5CYC_COUNT                       (4U)
77229 
77230 /*! @name OUTEN - Output Enable Register */
77231 /*! @{ */
77232 
77233 #define PWM_OUTEN_PWMX_EN_MASK                   (0xFU)
77234 #define PWM_OUTEN_PWMX_EN_SHIFT                  (0U)
77235 /*! PWMX_EN - PWM_X Output Enables */
77236 #define PWM_OUTEN_PWMX_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
77237 
77238 #define PWM_OUTEN_PWMB_EN_MASK                   (0xF0U)
77239 #define PWM_OUTEN_PWMB_EN_SHIFT                  (4U)
77240 /*! PWMB_EN - PWM_B Output Enables */
77241 #define PWM_OUTEN_PWMB_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
77242 
77243 #define PWM_OUTEN_PWMA_EN_MASK                   (0xF00U)
77244 #define PWM_OUTEN_PWMA_EN_SHIFT                  (8U)
77245 /*! PWMA_EN - PWM_A Output Enables */
77246 #define PWM_OUTEN_PWMA_EN(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
77247 /*! @} */
77248 
77249 /*! @name MASK - Mask Register */
77250 /*! @{ */
77251 
77252 #define PWM_MASK_MASKX_MASK                      (0xFU)
77253 #define PWM_MASK_MASKX_SHIFT                     (0U)
77254 /*! MASKX - PWM_X Masks */
77255 #define PWM_MASK_MASKX(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
77256 
77257 #define PWM_MASK_MASKB_MASK                      (0xF0U)
77258 #define PWM_MASK_MASKB_SHIFT                     (4U)
77259 /*! MASKB - PWM_B Masks */
77260 #define PWM_MASK_MASKB(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
77261 
77262 #define PWM_MASK_MASKA_MASK                      (0xF00U)
77263 #define PWM_MASK_MASKA_SHIFT                     (8U)
77264 /*! MASKA - PWM_A Masks */
77265 #define PWM_MASK_MASKA(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
77266 
77267 #define PWM_MASK_UPDATE_MASK_MASK                (0xF000U)
77268 #define PWM_MASK_UPDATE_MASK_SHIFT               (12U)
77269 /*! UPDATE_MASK - Update Mask Bits Immediately */
77270 #define PWM_MASK_UPDATE_MASK(x)                  (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)
77271 /*! @} */
77272 
77273 /*! @name SWCOUT - Software Controlled Output Register */
77274 /*! @{ */
77275 
77276 #define PWM_SWCOUT_SM0OUT45_MASK                 (0x1U)
77277 #define PWM_SWCOUT_SM0OUT45_SHIFT                (0U)
77278 /*! SM0OUT45 - Submodule 0 Software Controlled Output 45
77279  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.
77280  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.
77281  */
77282 #define PWM_SWCOUT_SM0OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
77283 
77284 #define PWM_SWCOUT_SM0OUT23_MASK                 (0x2U)
77285 #define PWM_SWCOUT_SM0OUT23_SHIFT                (1U)
77286 /*! SM0OUT23 - Submodule 0 Software Controlled Output 23
77287  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.
77288  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.
77289  */
77290 #define PWM_SWCOUT_SM0OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
77291 
77292 #define PWM_SWCOUT_SM1OUT45_MASK                 (0x4U)
77293 #define PWM_SWCOUT_SM1OUT45_SHIFT                (2U)
77294 /*! SM1OUT45 - Submodule 1 Software Controlled Output 45
77295  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.
77296  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.
77297  */
77298 #define PWM_SWCOUT_SM1OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
77299 
77300 #define PWM_SWCOUT_SM1OUT23_MASK                 (0x8U)
77301 #define PWM_SWCOUT_SM1OUT23_SHIFT                (3U)
77302 /*! SM1OUT23 - Submodule 1 Software Controlled Output 23
77303  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
77304  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.
77305  */
77306 #define PWM_SWCOUT_SM1OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
77307 
77308 #define PWM_SWCOUT_SM2OUT45_MASK                 (0x10U)
77309 #define PWM_SWCOUT_SM2OUT45_SHIFT                (4U)
77310 /*! SM2OUT45 - Submodule 2 Software Controlled Output 45
77311  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.
77312  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.
77313  */
77314 #define PWM_SWCOUT_SM2OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
77315 
77316 #define PWM_SWCOUT_SM2OUT23_MASK                 (0x20U)
77317 #define PWM_SWCOUT_SM2OUT23_SHIFT                (5U)
77318 /*! SM2OUT23 - Submodule 2 Software Controlled Output 23
77319  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.
77320  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.
77321  */
77322 #define PWM_SWCOUT_SM2OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
77323 
77324 #define PWM_SWCOUT_SM3OUT45_MASK                 (0x40U)
77325 #define PWM_SWCOUT_SM3OUT45_SHIFT                (6U)
77326 /*! SM3OUT45 - Submodule 3 Software Controlled Output 45
77327  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45.
77328  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.
77329  */
77330 #define PWM_SWCOUT_SM3OUT45(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
77331 
77332 #define PWM_SWCOUT_SM3OUT23_MASK                 (0x80U)
77333 #define PWM_SWCOUT_SM3OUT23_SHIFT                (7U)
77334 /*! SM3OUT23 - Submodule 3 Software Controlled Output 23
77335  *  0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23.
77336  *  0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.
77337  */
77338 #define PWM_SWCOUT_SM3OUT23(x)                   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
77339 /*! @} */
77340 
77341 /*! @name DTSRCSEL - PWM Source Select Register */
77342 /*! @{ */
77343 
77344 #define PWM_DTSRCSEL_SM0SEL45_MASK               (0x3U)
77345 #define PWM_DTSRCSEL_SM0SEL45_SHIFT              (0U)
77346 /*! SM0SEL45 - Submodule 0 PWM45 Control Select
77347  *  0b00..Generated SM0PWM45 signal used by the deadtime logic.
77348  *  0b01..Inverted generated SM0PWM45 signal used by the deadtime logic.
77349  *  0b10..SWCOUT[SM0OUT45] used by the deadtime logic.
77350  *  0b11..Reserved
77351  */
77352 #define PWM_DTSRCSEL_SM0SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
77353 
77354 #define PWM_DTSRCSEL_SM0SEL23_MASK               (0xCU)
77355 #define PWM_DTSRCSEL_SM0SEL23_SHIFT              (2U)
77356 /*! SM0SEL23 - Submodule 0 PWM23 Control Select
77357  *  0b00..Generated SM0PWM23 signal used by the deadtime logic.
77358  *  0b01..Inverted generated SM0PWM23 signal used by the deadtime logic.
77359  *  0b10..SWCOUT[SM0OUT23] used by the deadtime logic.
77360  *  0b11..PWM0_EXTA signal used by the deadtime logic.
77361  */
77362 #define PWM_DTSRCSEL_SM0SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
77363 
77364 #define PWM_DTSRCSEL_SM1SEL45_MASK               (0x30U)
77365 #define PWM_DTSRCSEL_SM1SEL45_SHIFT              (4U)
77366 /*! SM1SEL45 - Submodule 1 PWM45 Control Select
77367  *  0b00..Generated SM1PWM45 signal used by the deadtime logic.
77368  *  0b01..Inverted generated SM1PWM45 signal used by the deadtime logic.
77369  *  0b10..SWCOUT[SM1OUT45] used by the deadtime logic.
77370  *  0b11..Reserved
77371  */
77372 #define PWM_DTSRCSEL_SM1SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
77373 
77374 #define PWM_DTSRCSEL_SM1SEL23_MASK               (0xC0U)
77375 #define PWM_DTSRCSEL_SM1SEL23_SHIFT              (6U)
77376 /*! SM1SEL23 - Submodule 1 PWM23 Control Select
77377  *  0b00..Generated SM1PWM23 signal used by the deadtime logic.
77378  *  0b01..Inverted generated SM1PWM23 signal used by the deadtime logic.
77379  *  0b10..SWCOUT[SM1OUT23] used by the deadtime logic.
77380  *  0b11..PWM1_EXTA signal used by the deadtime logic.
77381  */
77382 #define PWM_DTSRCSEL_SM1SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
77383 
77384 #define PWM_DTSRCSEL_SM2SEL45_MASK               (0x300U)
77385 #define PWM_DTSRCSEL_SM2SEL45_SHIFT              (8U)
77386 /*! SM2SEL45 - Submodule 2 PWM45 Control Select
77387  *  0b00..Generated SM2PWM45 signal used by the deadtime logic.
77388  *  0b01..Inverted generated SM2PWM45 signal used by the deadtime logic.
77389  *  0b10..SWCOUT[SM2OUT45] used by the deadtime logic.
77390  *  0b11..Reserved
77391  */
77392 #define PWM_DTSRCSEL_SM2SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
77393 
77394 #define PWM_DTSRCSEL_SM2SEL23_MASK               (0xC00U)
77395 #define PWM_DTSRCSEL_SM2SEL23_SHIFT              (10U)
77396 /*! SM2SEL23 - Submodule 2 PWM23 Control Select
77397  *  0b00..Generated SM2PWM23 signal used by the deadtime logic.
77398  *  0b01..Inverted generated SM2PWM23 signal used by the deadtime logic.
77399  *  0b10..SWCOUT[SM2OUT23] used by the deadtime logic.
77400  *  0b11..PWM2_EXTA signal used by the deadtime logic.
77401  */
77402 #define PWM_DTSRCSEL_SM2SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
77403 
77404 #define PWM_DTSRCSEL_SM3SEL45_MASK               (0x3000U)
77405 #define PWM_DTSRCSEL_SM3SEL45_SHIFT              (12U)
77406 /*! SM3SEL45 - Submodule 3 PWM45 Control Select
77407  *  0b00..Generated SM3PWM45 signal used by the deadtime logic.
77408  *  0b01..Inverted generated SM3PWM45 signal used by the deadtime logic.
77409  *  0b10..SWCOUT[SM3OUT45] used by the deadtime logic.
77410  *  0b11..Reserved
77411  */
77412 #define PWM_DTSRCSEL_SM3SEL45(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
77413 
77414 #define PWM_DTSRCSEL_SM3SEL23_MASK               (0xC000U)
77415 #define PWM_DTSRCSEL_SM3SEL23_SHIFT              (14U)
77416 /*! SM3SEL23 - Submodule 3 PWM23 Control Select
77417  *  0b00..Generated SM3PWM23 signal used by the deadtime logic.
77418  *  0b01..Inverted generated SM3PWM23 signal used by the deadtime logic.
77419  *  0b10..SWCOUT[SM3OUT23] used by the deadtime logic.
77420  *  0b11..PWM3_EXTA signal used by the deadtime logic.
77421  */
77422 #define PWM_DTSRCSEL_SM3SEL23(x)                 (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
77423 /*! @} */
77424 
77425 /*! @name MCTRL - Master Control Register */
77426 /*! @{ */
77427 
77428 #define PWM_MCTRL_LDOK_MASK                      (0xFU)
77429 #define PWM_MCTRL_LDOK_SHIFT                     (0U)
77430 /*! LDOK - Load Okay
77431  *  0b0000..Do not load new values.
77432  *  0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule.
77433  */
77434 #define PWM_MCTRL_LDOK(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
77435 
77436 #define PWM_MCTRL_CLDOK_MASK                     (0xF0U)
77437 #define PWM_MCTRL_CLDOK_SHIFT                    (4U)
77438 /*! CLDOK - Clear Load Okay */
77439 #define PWM_MCTRL_CLDOK(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
77440 
77441 #define PWM_MCTRL_RUN_MASK                       (0xF00U)
77442 #define PWM_MCTRL_RUN_SHIFT                      (8U)
77443 /*! RUN - Run
77444  *  0b0000..PWM counter is stopped, but PWM outputs hold the current state.
77445  *  0b0001..PWM counter is started in the corresponding submodule.
77446  */
77447 #define PWM_MCTRL_RUN(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
77448 
77449 #define PWM_MCTRL_IPOL_MASK                      (0xF000U)
77450 #define PWM_MCTRL_IPOL_SHIFT                     (12U)
77451 /*! IPOL - Current Polarity
77452  *  0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule.
77453  *  0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule.
77454  */
77455 #define PWM_MCTRL_IPOL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
77456 /*! @} */
77457 
77458 /*! @name FCTRL - Fault Control Register */
77459 /*! @{ */
77460 
77461 #define PWM_FCTRL_FIE_MASK                       (0xFU)
77462 #define PWM_FCTRL_FIE_SHIFT                      (0U)
77463 /*! FIE - Fault Interrupt Enables
77464  *  0b0000..FAULTx CPU interrupt requests disabled.
77465  *  0b0001..FAULTx CPU interrupt requests enabled.
77466  */
77467 #define PWM_FCTRL_FIE(x)                         (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
77468 
77469 #define PWM_FCTRL_FSAFE_MASK                     (0xF0U)
77470 #define PWM_FCTRL_FSAFE_SHIFT                    (4U)
77471 /*! FSAFE - Fault Safety Mode
77472  *  0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the
77473  *          start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard
77474  *          to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set, then the fault condition cannot be
77475  *          cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input
77476  *          signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in
77477  *          DISMAPn).
77478  *  0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and
77479  *          FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and
77480  *          FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared.
77481  */
77482 #define PWM_FCTRL_FSAFE(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
77483 
77484 #define PWM_FCTRL_FAUTO_MASK                     (0xF00U)
77485 #define PWM_FCTRL_FAUTO_SHIFT                    (8U)
77486 /*! FAUTO - Automatic Fault Clearing
77487  *  0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear
77488  *          at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If
77489  *          neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled
77490  *          by FCTRL[FSAFE].
77491  *  0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at
77492  *          the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without
77493  *          regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition
77494  *          cannot be cleared.
77495  */
77496 #define PWM_FCTRL_FAUTO(x)                       (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
77497 
77498 #define PWM_FCTRL_FLVL_MASK                      (0xF000U)
77499 #define PWM_FCTRL_FLVL_SHIFT                     (12U)
77500 /*! FLVL - Fault Level
77501  *  0b0000..A logic 0 on the fault input indicates a fault condition.
77502  *  0b0001..A logic 1 on the fault input indicates a fault condition.
77503  */
77504 #define PWM_FCTRL_FLVL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
77505 /*! @} */
77506 
77507 /*! @name FSTS - Fault Status Register */
77508 /*! @{ */
77509 
77510 #define PWM_FSTS_FFLAG_MASK                      (0xFU)
77511 #define PWM_FSTS_FFLAG_SHIFT                     (0U)
77512 /*! FFLAG - Fault Flags
77513  *  0b0000..No fault on the FAULTx pin.
77514  *  0b0001..Fault on the FAULTx pin.
77515  */
77516 #define PWM_FSTS_FFLAG(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
77517 
77518 #define PWM_FSTS_FFULL_MASK                      (0xF0U)
77519 #define PWM_FSTS_FFULL_SHIFT                     (4U)
77520 /*! FFULL - Full Cycle
77521  *  0b0000..PWM outputs are not re-enabled at the start of a full cycle
77522  *  0b0001..PWM outputs are re-enabled at the start of a full cycle
77523  */
77524 #define PWM_FSTS_FFULL(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
77525 
77526 #define PWM_FSTS_FFPIN_MASK                      (0xF00U)
77527 #define PWM_FSTS_FFPIN_SHIFT                     (8U)
77528 /*! FFPIN - Filtered Fault Pins */
77529 #define PWM_FSTS_FFPIN(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
77530 
77531 #define PWM_FSTS_FHALF_MASK                      (0xF000U)
77532 #define PWM_FSTS_FHALF_SHIFT                     (12U)
77533 /*! FHALF - Half Cycle Fault Recovery
77534  *  0b0000..PWM outputs are not re-enabled at the start of a half cycle.
77535  *  0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
77536  */
77537 #define PWM_FSTS_FHALF(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
77538 /*! @} */
77539 
77540 /*! @name FFILT - Fault Filter Register */
77541 /*! @{ */
77542 
77543 #define PWM_FFILT_FILT_PER_MASK                  (0xFFU)
77544 #define PWM_FFILT_FILT_PER_SHIFT                 (0U)
77545 /*! FILT_PER - Fault Filter Period */
77546 #define PWM_FFILT_FILT_PER(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
77547 
77548 #define PWM_FFILT_FILT_CNT_MASK                  (0x700U)
77549 #define PWM_FFILT_FILT_CNT_SHIFT                 (8U)
77550 /*! FILT_CNT - Fault Filter Count */
77551 #define PWM_FFILT_FILT_CNT(x)                    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
77552 
77553 #define PWM_FFILT_GSTR_MASK                      (0x8000U)
77554 #define PWM_FFILT_GSTR_SHIFT                     (15U)
77555 /*! GSTR - Fault Glitch Stretch Enable
77556  *  0b0..Fault input glitch stretching is disabled.
77557  *  0b1..Input fault signals are stretched to at least 2 IPBus clock cycles.
77558  */
77559 #define PWM_FFILT_GSTR(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
77560 /*! @} */
77561 
77562 /*! @name FTST - Fault Test Register */
77563 /*! @{ */
77564 
77565 #define PWM_FTST_FTEST_MASK                      (0x1U)
77566 #define PWM_FTST_FTEST_SHIFT                     (0U)
77567 /*! FTEST - Fault Test
77568  *  0b0..No fault
77569  *  0b1..Cause a simulated fault
77570  */
77571 #define PWM_FTST_FTEST(x)                        (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
77572 /*! @} */
77573 
77574 /*! @name FCTRL2 - Fault Control 2 Register */
77575 /*! @{ */
77576 
77577 #define PWM_FCTRL2_NOCOMB_MASK                   (0xFU)
77578 #define PWM_FCTRL2_NOCOMB_SHIFT                  (0U)
77579 /*! NOCOMB - No Combinational Path From Fault Input To PWM Output
77580  *  0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined
77581  *          with the filtered and latched fault signals to disable the PWM outputs.
77582  *  0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered
77583  *          and latched fault signals are used to disable the PWM outputs.
77584  */
77585 #define PWM_FCTRL2_NOCOMB(x)                     (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
77586 /*! @} */
77587 
77588 
77589 /*!
77590  * @}
77591  */ /* end of group PWM_Register_Masks */
77592 
77593 
77594 /* PWM - Peripheral instance base addresses */
77595 /** Peripheral PWM1 base address */
77596 #define PWM1_BASE                                (0x4018C000u)
77597 /** Peripheral PWM1 base pointer */
77598 #define PWM1                                     ((PWM_Type *)PWM1_BASE)
77599 /** Peripheral PWM2 base address */
77600 #define PWM2_BASE                                (0x40190000u)
77601 /** Peripheral PWM2 base pointer */
77602 #define PWM2                                     ((PWM_Type *)PWM2_BASE)
77603 /** Peripheral PWM3 base address */
77604 #define PWM3_BASE                                (0x40194000u)
77605 /** Peripheral PWM3 base pointer */
77606 #define PWM3                                     ((PWM_Type *)PWM3_BASE)
77607 /** Peripheral PWM4 base address */
77608 #define PWM4_BASE                                (0x40198000u)
77609 /** Peripheral PWM4 base pointer */
77610 #define PWM4                                     ((PWM_Type *)PWM4_BASE)
77611 /** Array initializer of PWM peripheral base addresses */
77612 #define PWM_BASE_ADDRS                           { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
77613 /** Array initializer of PWM peripheral base pointers */
77614 #define PWM_BASE_PTRS                            { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
77615 /** Interrupt vectors for the PWM peripheral type */
77616 #define PWM_CMP_IRQS                             { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
77617 #define PWM_RELOAD_IRQS                          { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
77618 #define PWM_CAPTURE_IRQS                         { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
77619 #define PWM_FAULT_IRQS                           { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
77620 #define PWM_RELOAD_ERROR_IRQS                    { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
77621 
77622 /*!
77623  * @}
77624  */ /* end of group PWM_Peripheral_Access_Layer */
77625 
77626 
77627 /* ----------------------------------------------------------------------------
77628    -- PXP Peripheral Access Layer
77629    ---------------------------------------------------------------------------- */
77630 
77631 /*!
77632  * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer
77633  * @{
77634  */
77635 
77636 /** PXP - Register Layout Typedef */
77637 typedef struct {
77638   __IO uint32_t CTRL;                              /**< Control Register 0, offset: 0x0 */
77639   __IO uint32_t CTRL_SET;                          /**< Control Register 0, offset: 0x4 */
77640   __IO uint32_t CTRL_CLR;                          /**< Control Register 0, offset: 0x8 */
77641   __IO uint32_t CTRL_TOG;                          /**< Control Register 0, offset: 0xC */
77642   __IO uint32_t STAT;                              /**< Status Register, offset: 0x10 */
77643   __IO uint32_t STAT_SET;                          /**< Status Register, offset: 0x14 */
77644   __IO uint32_t STAT_CLR;                          /**< Status Register, offset: 0x18 */
77645   __IO uint32_t STAT_TOG;                          /**< Status Register, offset: 0x1C */
77646   __IO uint32_t OUT_CTRL;                          /**< Output Buffer Control Register, offset: 0x20 */
77647   __IO uint32_t OUT_CTRL_SET;                      /**< Output Buffer Control Register, offset: 0x24 */
77648   __IO uint32_t OUT_CTRL_CLR;                      /**< Output Buffer Control Register, offset: 0x28 */
77649   __IO uint32_t OUT_CTRL_TOG;                      /**< Output Buffer Control Register, offset: 0x2C */
77650   __IO uint32_t OUT_BUF;                           /**< Output Frame Buffer Pointer, offset: 0x30 */
77651        uint8_t RESERVED_0[12];
77652   __IO uint32_t OUT_BUF2;                          /**< Output Frame Buffer Pointer #2, offset: 0x40 */
77653        uint8_t RESERVED_1[12];
77654   __IO uint32_t OUT_PITCH;                         /**< Output Buffer Pitch, offset: 0x50 */
77655        uint8_t RESERVED_2[12];
77656   __IO uint32_t OUT_LRC;                           /**< Output Surface Lower Right Coordinate, offset: 0x60 */
77657        uint8_t RESERVED_3[12];
77658   __IO uint32_t OUT_PS_ULC;                        /**< Processed Surface Upper Left Coordinate, offset: 0x70 */
77659        uint8_t RESERVED_4[12];
77660   __IO uint32_t OUT_PS_LRC;                        /**< Processed Surface Lower Right Coordinate, offset: 0x80 */
77661        uint8_t RESERVED_5[12];
77662   __IO uint32_t OUT_AS_ULC;                        /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */
77663        uint8_t RESERVED_6[12];
77664   __IO uint32_t OUT_AS_LRC;                        /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */
77665        uint8_t RESERVED_7[12];
77666   __IO uint32_t PS_CTRL;                           /**< Processed Surface (PS) Control Register, offset: 0xB0 */
77667   __IO uint32_t PS_CTRL_SET;                       /**< Processed Surface (PS) Control Register, offset: 0xB4 */
77668   __IO uint32_t PS_CTRL_CLR;                       /**< Processed Surface (PS) Control Register, offset: 0xB8 */
77669   __IO uint32_t PS_CTRL_TOG;                       /**< Processed Surface (PS) Control Register, offset: 0xBC */
77670   __IO uint32_t PS_BUF;                            /**< PS Input Buffer Address, offset: 0xC0 */
77671        uint8_t RESERVED_8[12];
77672   __IO uint32_t PS_UBUF;                           /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */
77673        uint8_t RESERVED_9[12];
77674   __IO uint32_t PS_VBUF;                           /**< PS V/Cr Input Buffer Address, offset: 0xE0 */
77675        uint8_t RESERVED_10[12];
77676   __IO uint32_t PS_PITCH;                          /**< Processed Surface Pitch, offset: 0xF0 */
77677        uint8_t RESERVED_11[12];
77678   __IO uint32_t PS_BACKGROUND;                     /**< PS Background Color, offset: 0x100 */
77679        uint8_t RESERVED_12[12];
77680   __IO uint32_t PS_SCALE;                          /**< PS Scale Factor Register, offset: 0x110 */
77681        uint8_t RESERVED_13[12];
77682   __IO uint32_t PS_OFFSET;                         /**< PS Scale Offset Register, offset: 0x120 */
77683        uint8_t RESERVED_14[12];
77684   __IO uint32_t PS_CLRKEYLOW;                      /**< PS Color Key Low, offset: 0x130 */
77685        uint8_t RESERVED_15[12];
77686   __IO uint32_t PS_CLRKEYHIGH;                     /**< PS Color Key High, offset: 0x140 */
77687        uint8_t RESERVED_16[12];
77688   __IO uint32_t AS_CTRL;                           /**< Alpha Surface Control, offset: 0x150 */
77689        uint8_t RESERVED_17[12];
77690   __IO uint32_t AS_BUF;                            /**< Alpha Surface Buffer Pointer, offset: 0x160 */
77691        uint8_t RESERVED_18[12];
77692   __IO uint32_t AS_PITCH;                          /**< Alpha Surface Pitch, offset: 0x170 */
77693        uint8_t RESERVED_19[12];
77694   __IO uint32_t AS_CLRKEYLOW;                      /**< Overlay Color Key Low, offset: 0x180 */
77695        uint8_t RESERVED_20[12];
77696   __IO uint32_t AS_CLRKEYHIGH;                     /**< Overlay Color Key High, offset: 0x190 */
77697        uint8_t RESERVED_21[12];
77698   __IO uint32_t CSC1_COEF0;                        /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */
77699        uint8_t RESERVED_22[12];
77700   __IO uint32_t CSC1_COEF1;                        /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */
77701        uint8_t RESERVED_23[12];
77702   __IO uint32_t CSC1_COEF2;                        /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */
77703        uint8_t RESERVED_24[348];
77704   __IO uint32_t POWER;                             /**< PXP Power Control Register, offset: 0x320 */
77705        uint8_t RESERVED_25[220];
77706   __IO uint32_t NEXT;                              /**< Next Frame Pointer, offset: 0x400 */
77707        uint8_t RESERVED_26[60];
77708   __IO uint32_t PORTER_DUFF_CTRL;                  /**< PXP Alpha Engine A Control Register., offset: 0x440 */
77709 } PXP_Type;
77710 
77711 /* ----------------------------------------------------------------------------
77712    -- PXP Register Masks
77713    ---------------------------------------------------------------------------- */
77714 
77715 /*!
77716  * @addtogroup PXP_Register_Masks PXP Register Masks
77717  * @{
77718  */
77719 
77720 /*! @name CTRL - Control Register 0 */
77721 /*! @{ */
77722 
77723 #define PXP_CTRL_ENABLE_MASK                     (0x1U)
77724 #define PXP_CTRL_ENABLE_SHIFT                    (0U)
77725 /*! ENABLE
77726  *  0b1..PXP is enabled
77727  *  0b0..PXP is disabled
77728  */
77729 #define PXP_CTRL_ENABLE(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)
77730 
77731 #define PXP_CTRL_IRQ_ENABLE_MASK                 (0x2U)
77732 #define PXP_CTRL_IRQ_ENABLE_SHIFT                (1U)
77733 /*! IRQ_ENABLE
77734  *  0b1..PXP interrupt is enabled
77735  *  0b0..PXP interrupt is disabled
77736  */
77737 #define PXP_CTRL_IRQ_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)
77738 
77739 #define PXP_CTRL_NEXT_IRQ_ENABLE_MASK            (0x4U)
77740 #define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT           (2U)
77741 /*! NEXT_IRQ_ENABLE
77742  *  0b0..Disabled
77743  *  0b1..Enabled
77744  */
77745 #define PXP_CTRL_NEXT_IRQ_ENABLE(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)
77746 
77747 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK       (0x10U)
77748 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT      (4U)
77749 #define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x)         (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
77750 
77751 #define PXP_CTRL_ROTATE_MASK                     (0x300U)
77752 #define PXP_CTRL_ROTATE_SHIFT                    (8U)
77753 /*! ROTATE
77754  *  0b00..ROT_0
77755  *  0b01..ROT_90
77756  *  0b10..ROT_180
77757  *  0b11..ROT_270
77758  */
77759 #define PXP_CTRL_ROTATE(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)
77760 
77761 #define PXP_CTRL_HFLIP_MASK                      (0x400U)
77762 #define PXP_CTRL_HFLIP_SHIFT                     (10U)
77763 /*! HFLIP
77764  *  0b0..Horizontal Flip is disabled
77765  *  0b1..Horizontal Flip is enabled
77766  */
77767 #define PXP_CTRL_HFLIP(x)                        (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)
77768 
77769 #define PXP_CTRL_VFLIP_MASK                      (0x800U)
77770 #define PXP_CTRL_VFLIP_SHIFT                     (11U)
77771 /*! VFLIP
77772  *  0b0..Vertical Flip is disabled
77773  *  0b1..Vertical Flip is enabled
77774  */
77775 #define PXP_CTRL_VFLIP(x)                        (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)
77776 
77777 #define PXP_CTRL_ROT_POS_MASK                    (0x400000U)
77778 #define PXP_CTRL_ROT_POS_SHIFT                   (22U)
77779 #define PXP_CTRL_ROT_POS(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)
77780 
77781 #define PXP_CTRL_BLOCK_SIZE_MASK                 (0x800000U)
77782 #define PXP_CTRL_BLOCK_SIZE_SHIFT                (23U)
77783 /*! BLOCK_SIZE
77784  *  0b0..Process 8x8 pixel blocks.
77785  *  0b1..Process 16x16 pixel blocks.
77786  */
77787 #define PXP_CTRL_BLOCK_SIZE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)
77788 
77789 #define PXP_CTRL_EN_REPEAT_MASK                  (0x10000000U)
77790 #define PXP_CTRL_EN_REPEAT_SHIFT                 (28U)
77791 /*! EN_REPEAT
77792  *  0b1..PXP will repeat based on the current configuration register settings
77793  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
77794  */
77795 #define PXP_CTRL_EN_REPEAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)
77796 
77797 #define PXP_CTRL_CLKGATE_MASK                    (0x40000000U)
77798 #define PXP_CTRL_CLKGATE_SHIFT                   (30U)
77799 /*! CLKGATE
77800  *  0b0..Normal operation
77801  *  0b1..All clocks to PXP is gated-off
77802  */
77803 #define PXP_CTRL_CLKGATE(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)
77804 
77805 #define PXP_CTRL_SFTRST_MASK                     (0x80000000U)
77806 #define PXP_CTRL_SFTRST_SHIFT                    (31U)
77807 /*! SFTRST
77808  *  0b0..Normal PXP operation is enabled
77809  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
77810  */
77811 #define PXP_CTRL_SFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)
77812 /*! @} */
77813 
77814 /*! @name CTRL_SET - Control Register 0 */
77815 /*! @{ */
77816 
77817 #define PXP_CTRL_SET_ENABLE_MASK                 (0x1U)
77818 #define PXP_CTRL_SET_ENABLE_SHIFT                (0U)
77819 /*! ENABLE
77820  *  0b1..PXP is enabled
77821  *  0b0..PXP is disabled
77822  */
77823 #define PXP_CTRL_SET_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)
77824 
77825 #define PXP_CTRL_SET_IRQ_ENABLE_MASK             (0x2U)
77826 #define PXP_CTRL_SET_IRQ_ENABLE_SHIFT            (1U)
77827 /*! IRQ_ENABLE
77828  *  0b1..PXP interrupt is enabled
77829  *  0b0..PXP interrupt is disabled
77830  */
77831 #define PXP_CTRL_SET_IRQ_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)
77832 
77833 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK        (0x4U)
77834 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT       (2U)
77835 /*! NEXT_IRQ_ENABLE
77836  *  0b0..Disabled
77837  *  0b1..Enabled
77838  */
77839 #define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)
77840 
77841 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
77842 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT  (4U)
77843 #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)
77844 
77845 #define PXP_CTRL_SET_ROTATE_MASK                 (0x300U)
77846 #define PXP_CTRL_SET_ROTATE_SHIFT                (8U)
77847 /*! ROTATE
77848  *  0b00..ROT_0
77849  *  0b01..ROT_90
77850  *  0b10..ROT_180
77851  *  0b11..ROT_270
77852  */
77853 #define PXP_CTRL_SET_ROTATE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)
77854 
77855 #define PXP_CTRL_SET_HFLIP_MASK                  (0x400U)
77856 #define PXP_CTRL_SET_HFLIP_SHIFT                 (10U)
77857 /*! HFLIP
77858  *  0b0..Horizontal Flip is disabled
77859  *  0b1..Horizontal Flip is enabled
77860  */
77861 #define PXP_CTRL_SET_HFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)
77862 
77863 #define PXP_CTRL_SET_VFLIP_MASK                  (0x800U)
77864 #define PXP_CTRL_SET_VFLIP_SHIFT                 (11U)
77865 /*! VFLIP
77866  *  0b0..Vertical Flip is disabled
77867  *  0b1..Vertical Flip is enabled
77868  */
77869 #define PXP_CTRL_SET_VFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)
77870 
77871 #define PXP_CTRL_SET_ROT_POS_MASK                (0x400000U)
77872 #define PXP_CTRL_SET_ROT_POS_SHIFT               (22U)
77873 #define PXP_CTRL_SET_ROT_POS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)
77874 
77875 #define PXP_CTRL_SET_BLOCK_SIZE_MASK             (0x800000U)
77876 #define PXP_CTRL_SET_BLOCK_SIZE_SHIFT            (23U)
77877 /*! BLOCK_SIZE
77878  *  0b0..Process 8x8 pixel blocks.
77879  *  0b1..Process 16x16 pixel blocks.
77880  */
77881 #define PXP_CTRL_SET_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)
77882 
77883 #define PXP_CTRL_SET_EN_REPEAT_MASK              (0x10000000U)
77884 #define PXP_CTRL_SET_EN_REPEAT_SHIFT             (28U)
77885 /*! EN_REPEAT
77886  *  0b1..PXP will repeat based on the current configuration register settings
77887  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
77888  */
77889 #define PXP_CTRL_SET_EN_REPEAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)
77890 
77891 #define PXP_CTRL_SET_CLKGATE_MASK                (0x40000000U)
77892 #define PXP_CTRL_SET_CLKGATE_SHIFT               (30U)
77893 /*! CLKGATE
77894  *  0b0..Normal operation
77895  *  0b1..All clocks to PXP is gated-off
77896  */
77897 #define PXP_CTRL_SET_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)
77898 
77899 #define PXP_CTRL_SET_SFTRST_MASK                 (0x80000000U)
77900 #define PXP_CTRL_SET_SFTRST_SHIFT                (31U)
77901 /*! SFTRST
77902  *  0b0..Normal PXP operation is enabled
77903  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
77904  */
77905 #define PXP_CTRL_SET_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)
77906 /*! @} */
77907 
77908 /*! @name CTRL_CLR - Control Register 0 */
77909 /*! @{ */
77910 
77911 #define PXP_CTRL_CLR_ENABLE_MASK                 (0x1U)
77912 #define PXP_CTRL_CLR_ENABLE_SHIFT                (0U)
77913 /*! ENABLE
77914  *  0b1..PXP is enabled
77915  *  0b0..PXP is disabled
77916  */
77917 #define PXP_CTRL_CLR_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)
77918 
77919 #define PXP_CTRL_CLR_IRQ_ENABLE_MASK             (0x2U)
77920 #define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT            (1U)
77921 /*! IRQ_ENABLE
77922  *  0b1..PXP interrupt is enabled
77923  *  0b0..PXP interrupt is disabled
77924  */
77925 #define PXP_CTRL_CLR_IRQ_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)
77926 
77927 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK        (0x4U)
77928 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT       (2U)
77929 /*! NEXT_IRQ_ENABLE
77930  *  0b0..Disabled
77931  *  0b1..Enabled
77932  */
77933 #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)
77934 
77935 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
77936 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT  (4U)
77937 #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)
77938 
77939 #define PXP_CTRL_CLR_ROTATE_MASK                 (0x300U)
77940 #define PXP_CTRL_CLR_ROTATE_SHIFT                (8U)
77941 /*! ROTATE
77942  *  0b00..ROT_0
77943  *  0b01..ROT_90
77944  *  0b10..ROT_180
77945  *  0b11..ROT_270
77946  */
77947 #define PXP_CTRL_CLR_ROTATE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)
77948 
77949 #define PXP_CTRL_CLR_HFLIP_MASK                  (0x400U)
77950 #define PXP_CTRL_CLR_HFLIP_SHIFT                 (10U)
77951 /*! HFLIP
77952  *  0b0..Horizontal Flip is disabled
77953  *  0b1..Horizontal Flip is enabled
77954  */
77955 #define PXP_CTRL_CLR_HFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)
77956 
77957 #define PXP_CTRL_CLR_VFLIP_MASK                  (0x800U)
77958 #define PXP_CTRL_CLR_VFLIP_SHIFT                 (11U)
77959 /*! VFLIP
77960  *  0b0..Vertical Flip is disabled
77961  *  0b1..Vertical Flip is enabled
77962  */
77963 #define PXP_CTRL_CLR_VFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)
77964 
77965 #define PXP_CTRL_CLR_ROT_POS_MASK                (0x400000U)
77966 #define PXP_CTRL_CLR_ROT_POS_SHIFT               (22U)
77967 #define PXP_CTRL_CLR_ROT_POS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)
77968 
77969 #define PXP_CTRL_CLR_BLOCK_SIZE_MASK             (0x800000U)
77970 #define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT            (23U)
77971 /*! BLOCK_SIZE
77972  *  0b0..Process 8x8 pixel blocks.
77973  *  0b1..Process 16x16 pixel blocks.
77974  */
77975 #define PXP_CTRL_CLR_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)
77976 
77977 #define PXP_CTRL_CLR_EN_REPEAT_MASK              (0x10000000U)
77978 #define PXP_CTRL_CLR_EN_REPEAT_SHIFT             (28U)
77979 /*! EN_REPEAT
77980  *  0b1..PXP will repeat based on the current configuration register settings
77981  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
77982  */
77983 #define PXP_CTRL_CLR_EN_REPEAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)
77984 
77985 #define PXP_CTRL_CLR_CLKGATE_MASK                (0x40000000U)
77986 #define PXP_CTRL_CLR_CLKGATE_SHIFT               (30U)
77987 /*! CLKGATE
77988  *  0b0..Normal operation
77989  *  0b1..All clocks to PXP is gated-off
77990  */
77991 #define PXP_CTRL_CLR_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)
77992 
77993 #define PXP_CTRL_CLR_SFTRST_MASK                 (0x80000000U)
77994 #define PXP_CTRL_CLR_SFTRST_SHIFT                (31U)
77995 /*! SFTRST
77996  *  0b0..Normal PXP operation is enabled
77997  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
77998  */
77999 #define PXP_CTRL_CLR_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)
78000 /*! @} */
78001 
78002 /*! @name CTRL_TOG - Control Register 0 */
78003 /*! @{ */
78004 
78005 #define PXP_CTRL_TOG_ENABLE_MASK                 (0x1U)
78006 #define PXP_CTRL_TOG_ENABLE_SHIFT                (0U)
78007 /*! ENABLE
78008  *  0b1..PXP is enabled
78009  *  0b0..PXP is disabled
78010  */
78011 #define PXP_CTRL_TOG_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)
78012 
78013 #define PXP_CTRL_TOG_IRQ_ENABLE_MASK             (0x2U)
78014 #define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT            (1U)
78015 /*! IRQ_ENABLE
78016  *  0b1..PXP interrupt is enabled
78017  *  0b0..PXP interrupt is disabled
78018  */
78019 #define PXP_CTRL_TOG_IRQ_ENABLE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)
78020 
78021 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK        (0x4U)
78022 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT       (2U)
78023 /*! NEXT_IRQ_ENABLE
78024  *  0b0..Disabled
78025  *  0b1..Enabled
78026  */
78027 #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x)          (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)
78028 
78029 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK   (0x10U)
78030 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT  (4U)
78031 #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x)     (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)
78032 
78033 #define PXP_CTRL_TOG_ROTATE_MASK                 (0x300U)
78034 #define PXP_CTRL_TOG_ROTATE_SHIFT                (8U)
78035 /*! ROTATE
78036  *  0b00..ROT_0
78037  *  0b01..ROT_90
78038  *  0b10..ROT_180
78039  *  0b11..ROT_270
78040  */
78041 #define PXP_CTRL_TOG_ROTATE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)
78042 
78043 #define PXP_CTRL_TOG_HFLIP_MASK                  (0x400U)
78044 #define PXP_CTRL_TOG_HFLIP_SHIFT                 (10U)
78045 /*! HFLIP
78046  *  0b0..Horizontal Flip is disabled
78047  *  0b1..Horizontal Flip is enabled
78048  */
78049 #define PXP_CTRL_TOG_HFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)
78050 
78051 #define PXP_CTRL_TOG_VFLIP_MASK                  (0x800U)
78052 #define PXP_CTRL_TOG_VFLIP_SHIFT                 (11U)
78053 /*! VFLIP
78054  *  0b0..Vertical Flip is disabled
78055  *  0b1..Vertical Flip is enabled
78056  */
78057 #define PXP_CTRL_TOG_VFLIP(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)
78058 
78059 #define PXP_CTRL_TOG_ROT_POS_MASK                (0x400000U)
78060 #define PXP_CTRL_TOG_ROT_POS_SHIFT               (22U)
78061 #define PXP_CTRL_TOG_ROT_POS(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)
78062 
78063 #define PXP_CTRL_TOG_BLOCK_SIZE_MASK             (0x800000U)
78064 #define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT            (23U)
78065 /*! BLOCK_SIZE
78066  *  0b0..Process 8x8 pixel blocks.
78067  *  0b1..Process 16x16 pixel blocks.
78068  */
78069 #define PXP_CTRL_TOG_BLOCK_SIZE(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)
78070 
78071 #define PXP_CTRL_TOG_EN_REPEAT_MASK              (0x10000000U)
78072 #define PXP_CTRL_TOG_EN_REPEAT_SHIFT             (28U)
78073 /*! EN_REPEAT
78074  *  0b1..PXP will repeat based on the current configuration register settings
78075  *  0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
78076  */
78077 #define PXP_CTRL_TOG_EN_REPEAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)
78078 
78079 #define PXP_CTRL_TOG_CLKGATE_MASK                (0x40000000U)
78080 #define PXP_CTRL_TOG_CLKGATE_SHIFT               (30U)
78081 /*! CLKGATE
78082  *  0b0..Normal operation
78083  *  0b1..All clocks to PXP is gated-off
78084  */
78085 #define PXP_CTRL_TOG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)
78086 
78087 #define PXP_CTRL_TOG_SFTRST_MASK                 (0x80000000U)
78088 #define PXP_CTRL_TOG_SFTRST_SHIFT                (31U)
78089 /*! SFTRST
78090  *  0b0..Normal PXP operation is enabled
78091  *  0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
78092  */
78093 #define PXP_CTRL_TOG_SFTRST(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)
78094 /*! @} */
78095 
78096 /*! @name STAT - Status Register */
78097 /*! @{ */
78098 
78099 #define PXP_STAT_IRQ_MASK                        (0x1U)
78100 #define PXP_STAT_IRQ_SHIFT                       (0U)
78101 /*! IRQ
78102  *  0b0..No interrupt
78103  *  0b1..Interrupt generated
78104  */
78105 #define PXP_STAT_IRQ(x)                          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)
78106 
78107 #define PXP_STAT_AXI_WRITE_ERROR_MASK            (0x2U)
78108 #define PXP_STAT_AXI_WRITE_ERROR_SHIFT           (1U)
78109 /*! AXI_WRITE_ERROR
78110  *  0b0..AXI write is normal
78111  *  0b1..AXI write error has occurred
78112  */
78113 #define PXP_STAT_AXI_WRITE_ERROR(x)              (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)
78114 
78115 #define PXP_STAT_AXI_READ_ERROR_MASK             (0x4U)
78116 #define PXP_STAT_AXI_READ_ERROR_SHIFT            (2U)
78117 /*! AXI_READ_ERROR
78118  *  0b0..AXI read is normal
78119  *  0b1..AXI read error has occurred
78120  */
78121 #define PXP_STAT_AXI_READ_ERROR(x)               (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)
78122 
78123 #define PXP_STAT_NEXT_IRQ_MASK                   (0x8U)
78124 #define PXP_STAT_NEXT_IRQ_SHIFT                  (3U)
78125 #define PXP_STAT_NEXT_IRQ(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)
78126 
78127 #define PXP_STAT_AXI_ERROR_ID_MASK               (0xF0U)
78128 #define PXP_STAT_AXI_ERROR_ID_SHIFT              (4U)
78129 #define PXP_STAT_AXI_ERROR_ID(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)
78130 
78131 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK      (0x100U)
78132 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT     (8U)
78133 /*! LUT_DMA_LOAD_DONE_IRQ
78134  *  0b0..LUT DMA LOAD transfer is active
78135  *  0b1..LUT DMA LOAD transfer is complete
78136  */
78137 #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)
78138 
78139 #define PXP_STAT_BLOCKY_MASK                     (0xFF0000U)
78140 #define PXP_STAT_BLOCKY_SHIFT                    (16U)
78141 #define PXP_STAT_BLOCKY(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)
78142 
78143 #define PXP_STAT_BLOCKX_MASK                     (0xFF000000U)
78144 #define PXP_STAT_BLOCKX_SHIFT                    (24U)
78145 #define PXP_STAT_BLOCKX(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)
78146 /*! @} */
78147 
78148 /*! @name STAT_SET - Status Register */
78149 /*! @{ */
78150 
78151 #define PXP_STAT_SET_IRQ_MASK                    (0x1U)
78152 #define PXP_STAT_SET_IRQ_SHIFT                   (0U)
78153 /*! IRQ
78154  *  0b0..No interrupt
78155  *  0b1..Interrupt generated
78156  */
78157 #define PXP_STAT_SET_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)
78158 
78159 #define PXP_STAT_SET_AXI_WRITE_ERROR_MASK        (0x2U)
78160 #define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT       (1U)
78161 /*! AXI_WRITE_ERROR
78162  *  0b0..AXI write is normal
78163  *  0b1..AXI write error has occurred
78164  */
78165 #define PXP_STAT_SET_AXI_WRITE_ERROR(x)          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)
78166 
78167 #define PXP_STAT_SET_AXI_READ_ERROR_MASK         (0x4U)
78168 #define PXP_STAT_SET_AXI_READ_ERROR_SHIFT        (2U)
78169 /*! AXI_READ_ERROR
78170  *  0b0..AXI read is normal
78171  *  0b1..AXI read error has occurred
78172  */
78173 #define PXP_STAT_SET_AXI_READ_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)
78174 
78175 #define PXP_STAT_SET_NEXT_IRQ_MASK               (0x8U)
78176 #define PXP_STAT_SET_NEXT_IRQ_SHIFT              (3U)
78177 #define PXP_STAT_SET_NEXT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)
78178 
78179 #define PXP_STAT_SET_AXI_ERROR_ID_MASK           (0xF0U)
78180 #define PXP_STAT_SET_AXI_ERROR_ID_SHIFT          (4U)
78181 #define PXP_STAT_SET_AXI_ERROR_ID(x)             (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)
78182 
78183 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK  (0x100U)
78184 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
78185 /*! LUT_DMA_LOAD_DONE_IRQ
78186  *  0b0..LUT DMA LOAD transfer is active
78187  *  0b1..LUT DMA LOAD transfer is complete
78188  */
78189 #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)
78190 
78191 #define PXP_STAT_SET_BLOCKY_MASK                 (0xFF0000U)
78192 #define PXP_STAT_SET_BLOCKY_SHIFT                (16U)
78193 #define PXP_STAT_SET_BLOCKY(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)
78194 
78195 #define PXP_STAT_SET_BLOCKX_MASK                 (0xFF000000U)
78196 #define PXP_STAT_SET_BLOCKX_SHIFT                (24U)
78197 #define PXP_STAT_SET_BLOCKX(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)
78198 /*! @} */
78199 
78200 /*! @name STAT_CLR - Status Register */
78201 /*! @{ */
78202 
78203 #define PXP_STAT_CLR_IRQ_MASK                    (0x1U)
78204 #define PXP_STAT_CLR_IRQ_SHIFT                   (0U)
78205 /*! IRQ
78206  *  0b0..No interrupt
78207  *  0b1..Interrupt generated
78208  */
78209 #define PXP_STAT_CLR_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)
78210 
78211 #define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK        (0x2U)
78212 #define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT       (1U)
78213 /*! AXI_WRITE_ERROR
78214  *  0b0..AXI write is normal
78215  *  0b1..AXI write error has occurred
78216  */
78217 #define PXP_STAT_CLR_AXI_WRITE_ERROR(x)          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)
78218 
78219 #define PXP_STAT_CLR_AXI_READ_ERROR_MASK         (0x4U)
78220 #define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT        (2U)
78221 /*! AXI_READ_ERROR
78222  *  0b0..AXI read is normal
78223  *  0b1..AXI read error has occurred
78224  */
78225 #define PXP_STAT_CLR_AXI_READ_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)
78226 
78227 #define PXP_STAT_CLR_NEXT_IRQ_MASK               (0x8U)
78228 #define PXP_STAT_CLR_NEXT_IRQ_SHIFT              (3U)
78229 #define PXP_STAT_CLR_NEXT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)
78230 
78231 #define PXP_STAT_CLR_AXI_ERROR_ID_MASK           (0xF0U)
78232 #define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT          (4U)
78233 #define PXP_STAT_CLR_AXI_ERROR_ID(x)             (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)
78234 
78235 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK  (0x100U)
78236 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
78237 /*! LUT_DMA_LOAD_DONE_IRQ
78238  *  0b0..LUT DMA LOAD transfer is active
78239  *  0b1..LUT DMA LOAD transfer is complete
78240  */
78241 #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)
78242 
78243 #define PXP_STAT_CLR_BLOCKY_MASK                 (0xFF0000U)
78244 #define PXP_STAT_CLR_BLOCKY_SHIFT                (16U)
78245 #define PXP_STAT_CLR_BLOCKY(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)
78246 
78247 #define PXP_STAT_CLR_BLOCKX_MASK                 (0xFF000000U)
78248 #define PXP_STAT_CLR_BLOCKX_SHIFT                (24U)
78249 #define PXP_STAT_CLR_BLOCKX(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)
78250 /*! @} */
78251 
78252 /*! @name STAT_TOG - Status Register */
78253 /*! @{ */
78254 
78255 #define PXP_STAT_TOG_IRQ_MASK                    (0x1U)
78256 #define PXP_STAT_TOG_IRQ_SHIFT                   (0U)
78257 /*! IRQ
78258  *  0b0..No interrupt
78259  *  0b1..Interrupt generated
78260  */
78261 #define PXP_STAT_TOG_IRQ(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)
78262 
78263 #define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK        (0x2U)
78264 #define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT       (1U)
78265 /*! AXI_WRITE_ERROR
78266  *  0b0..AXI write is normal
78267  *  0b1..AXI write error has occurred
78268  */
78269 #define PXP_STAT_TOG_AXI_WRITE_ERROR(x)          (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)
78270 
78271 #define PXP_STAT_TOG_AXI_READ_ERROR_MASK         (0x4U)
78272 #define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT        (2U)
78273 /*! AXI_READ_ERROR
78274  *  0b0..AXI read is normal
78275  *  0b1..AXI read error has occurred
78276  */
78277 #define PXP_STAT_TOG_AXI_READ_ERROR(x)           (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)
78278 
78279 #define PXP_STAT_TOG_NEXT_IRQ_MASK               (0x8U)
78280 #define PXP_STAT_TOG_NEXT_IRQ_SHIFT              (3U)
78281 #define PXP_STAT_TOG_NEXT_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)
78282 
78283 #define PXP_STAT_TOG_AXI_ERROR_ID_MASK           (0xF0U)
78284 #define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT          (4U)
78285 #define PXP_STAT_TOG_AXI_ERROR_ID(x)             (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)
78286 
78287 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK  (0x100U)
78288 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
78289 /*! LUT_DMA_LOAD_DONE_IRQ
78290  *  0b0..LUT DMA LOAD transfer is active
78291  *  0b1..LUT DMA LOAD transfer is complete
78292  */
78293 #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x)    (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)
78294 
78295 #define PXP_STAT_TOG_BLOCKY_MASK                 (0xFF0000U)
78296 #define PXP_STAT_TOG_BLOCKY_SHIFT                (16U)
78297 #define PXP_STAT_TOG_BLOCKY(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)
78298 
78299 #define PXP_STAT_TOG_BLOCKX_MASK                 (0xFF000000U)
78300 #define PXP_STAT_TOG_BLOCKX_SHIFT                (24U)
78301 #define PXP_STAT_TOG_BLOCKX(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)
78302 /*! @} */
78303 
78304 /*! @name OUT_CTRL - Output Buffer Control Register */
78305 /*! @{ */
78306 
78307 #define PXP_OUT_CTRL_FORMAT_MASK                 (0x1FU)
78308 #define PXP_OUT_CTRL_FORMAT_SHIFT                (0U)
78309 /*! FORMAT
78310  *  0b00000..32-bit pixels
78311  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
78312  *  0b00101..24-bit pixels (packed 24-bit format)
78313  *  0b01000..16-bit pixels
78314  *  0b01001..16-bit pixels
78315  *  0b01100..16-bit pixels
78316  *  0b01101..16-bit pixels
78317  *  0b01110..16-bit pixels
78318  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
78319  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
78320  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
78321  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
78322  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
78323  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
78324  *  0b11001..16-bit pixels (2-plane UV)
78325  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
78326  *  0b11011..16-bit pixels (2-plane VU)
78327  */
78328 #define PXP_OUT_CTRL_FORMAT(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)
78329 
78330 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK      (0x300U)
78331 #define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT     (8U)
78332 /*! INTERLACED_OUTPUT
78333  *  0b00..All data written in progressive format to the OUTBUF Pointer.
78334  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
78335  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
78336  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
78337  */
78338 #define PXP_OUT_CTRL_INTERLACED_OUTPUT(x)        (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)
78339 
78340 #define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK           (0x800000U)
78341 #define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT          (23U)
78342 /*! ALPHA_OUTPUT
78343  *  0b0..Retain
78344  *  0b1..Overwritten
78345  */
78346 #define PXP_OUT_CTRL_ALPHA_OUTPUT(x)             (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)
78347 
78348 #define PXP_OUT_CTRL_ALPHA_MASK                  (0xFF000000U)
78349 #define PXP_OUT_CTRL_ALPHA_SHIFT                 (24U)
78350 #define PXP_OUT_CTRL_ALPHA(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)
78351 /*! @} */
78352 
78353 /*! @name OUT_CTRL_SET - Output Buffer Control Register */
78354 /*! @{ */
78355 
78356 #define PXP_OUT_CTRL_SET_FORMAT_MASK             (0x1FU)
78357 #define PXP_OUT_CTRL_SET_FORMAT_SHIFT            (0U)
78358 /*! FORMAT
78359  *  0b00000..32-bit pixels
78360  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
78361  *  0b00101..24-bit pixels (packed 24-bit format)
78362  *  0b01000..16-bit pixels
78363  *  0b01001..16-bit pixels
78364  *  0b01100..16-bit pixels
78365  *  0b01101..16-bit pixels
78366  *  0b01110..16-bit pixels
78367  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
78368  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
78369  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
78370  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
78371  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
78372  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
78373  *  0b11001..16-bit pixels (2-plane UV)
78374  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
78375  *  0b11011..16-bit pixels (2-plane VU)
78376  */
78377 #define PXP_OUT_CTRL_SET_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)
78378 
78379 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK  (0x300U)
78380 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)
78381 /*! INTERLACED_OUTPUT
78382  *  0b00..All data written in progressive format to the OUTBUF Pointer.
78383  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
78384  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
78385  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
78386  */
78387 #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)
78388 
78389 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK       (0x800000U)
78390 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT      (23U)
78391 /*! ALPHA_OUTPUT
78392  *  0b0..Retain
78393  *  0b1..Overwritten
78394  */
78395 #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)
78396 
78397 #define PXP_OUT_CTRL_SET_ALPHA_MASK              (0xFF000000U)
78398 #define PXP_OUT_CTRL_SET_ALPHA_SHIFT             (24U)
78399 #define PXP_OUT_CTRL_SET_ALPHA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)
78400 /*! @} */
78401 
78402 /*! @name OUT_CTRL_CLR - Output Buffer Control Register */
78403 /*! @{ */
78404 
78405 #define PXP_OUT_CTRL_CLR_FORMAT_MASK             (0x1FU)
78406 #define PXP_OUT_CTRL_CLR_FORMAT_SHIFT            (0U)
78407 /*! FORMAT
78408  *  0b00000..32-bit pixels
78409  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
78410  *  0b00101..24-bit pixels (packed 24-bit format)
78411  *  0b01000..16-bit pixels
78412  *  0b01001..16-bit pixels
78413  *  0b01100..16-bit pixels
78414  *  0b01101..16-bit pixels
78415  *  0b01110..16-bit pixels
78416  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
78417  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
78418  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
78419  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
78420  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
78421  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
78422  *  0b11001..16-bit pixels (2-plane UV)
78423  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
78424  *  0b11011..16-bit pixels (2-plane VU)
78425  */
78426 #define PXP_OUT_CTRL_CLR_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)
78427 
78428 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK  (0x300U)
78429 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)
78430 /*! INTERLACED_OUTPUT
78431  *  0b00..All data written in progressive format to the OUTBUF Pointer.
78432  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
78433  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
78434  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
78435  */
78436 #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)
78437 
78438 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK       (0x800000U)
78439 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT      (23U)
78440 /*! ALPHA_OUTPUT
78441  *  0b0..Retain
78442  *  0b1..Overwritten
78443  */
78444 #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)
78445 
78446 #define PXP_OUT_CTRL_CLR_ALPHA_MASK              (0xFF000000U)
78447 #define PXP_OUT_CTRL_CLR_ALPHA_SHIFT             (24U)
78448 #define PXP_OUT_CTRL_CLR_ALPHA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)
78449 /*! @} */
78450 
78451 /*! @name OUT_CTRL_TOG - Output Buffer Control Register */
78452 /*! @{ */
78453 
78454 #define PXP_OUT_CTRL_TOG_FORMAT_MASK             (0x1FU)
78455 #define PXP_OUT_CTRL_TOG_FORMAT_SHIFT            (0U)
78456 /*! FORMAT
78457  *  0b00000..32-bit pixels
78458  *  0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
78459  *  0b00101..24-bit pixels (packed 24-bit format)
78460  *  0b01000..16-bit pixels
78461  *  0b01001..16-bit pixels
78462  *  0b01100..16-bit pixels
78463  *  0b01101..16-bit pixels
78464  *  0b01110..16-bit pixels
78465  *  0b10000..32-bit pixels (1-plane XYUV unpacked)
78466  *  0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
78467  *  0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
78468  *  0b10100..8-bit monochrome pixels (1-plane Y luma output)
78469  *  0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
78470  *  0b11000..16-bit pixels (2-plane UV interleaved bytes)
78471  *  0b11001..16-bit pixels (2-plane UV)
78472  *  0b11010..16-bit pixels (2-plane VU interleaved bytes)
78473  *  0b11011..16-bit pixels (2-plane VU)
78474  */
78475 #define PXP_OUT_CTRL_TOG_FORMAT(x)               (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)
78476 
78477 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK  (0x300U)
78478 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)
78479 /*! INTERLACED_OUTPUT
78480  *  0b00..All data written in progressive format to the OUTBUF Pointer.
78481  *  0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
78482  *  0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
78483  *  0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
78484  */
78485 #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x)    (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)
78486 
78487 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK       (0x800000U)
78488 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT      (23U)
78489 /*! ALPHA_OUTPUT
78490  *  0b0..Retain
78491  *  0b1..Overwritten
78492  */
78493 #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x)         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)
78494 
78495 #define PXP_OUT_CTRL_TOG_ALPHA_MASK              (0xFF000000U)
78496 #define PXP_OUT_CTRL_TOG_ALPHA_SHIFT             (24U)
78497 #define PXP_OUT_CTRL_TOG_ALPHA(x)                (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)
78498 /*! @} */
78499 
78500 /*! @name OUT_BUF - Output Frame Buffer Pointer */
78501 /*! @{ */
78502 
78503 #define PXP_OUT_BUF_ADDR_MASK                    (0xFFFFFFFFU)
78504 #define PXP_OUT_BUF_ADDR_SHIFT                   (0U)
78505 #define PXP_OUT_BUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)
78506 /*! @} */
78507 
78508 /*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */
78509 /*! @{ */
78510 
78511 #define PXP_OUT_BUF2_ADDR_MASK                   (0xFFFFFFFFU)
78512 #define PXP_OUT_BUF2_ADDR_SHIFT                  (0U)
78513 #define PXP_OUT_BUF2_ADDR(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)
78514 /*! @} */
78515 
78516 /*! @name OUT_PITCH - Output Buffer Pitch */
78517 /*! @{ */
78518 
78519 #define PXP_OUT_PITCH_PITCH_MASK                 (0xFFFFU)
78520 #define PXP_OUT_PITCH_PITCH_SHIFT                (0U)
78521 #define PXP_OUT_PITCH_PITCH(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)
78522 /*! @} */
78523 
78524 /*! @name OUT_LRC - Output Surface Lower Right Coordinate */
78525 /*! @{ */
78526 
78527 #define PXP_OUT_LRC_Y_MASK                       (0x3FFFU)
78528 #define PXP_OUT_LRC_Y_SHIFT                      (0U)
78529 #define PXP_OUT_LRC_Y(x)                         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)
78530 
78531 #define PXP_OUT_LRC_X_MASK                       (0x3FFF0000U)
78532 #define PXP_OUT_LRC_X_SHIFT                      (16U)
78533 #define PXP_OUT_LRC_X(x)                         (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)
78534 /*! @} */
78535 
78536 /*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */
78537 /*! @{ */
78538 
78539 #define PXP_OUT_PS_ULC_Y_MASK                    (0x3FFFU)
78540 #define PXP_OUT_PS_ULC_Y_SHIFT                   (0U)
78541 #define PXP_OUT_PS_ULC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)
78542 
78543 #define PXP_OUT_PS_ULC_X_MASK                    (0x3FFF0000U)
78544 #define PXP_OUT_PS_ULC_X_SHIFT                   (16U)
78545 #define PXP_OUT_PS_ULC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)
78546 /*! @} */
78547 
78548 /*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */
78549 /*! @{ */
78550 
78551 #define PXP_OUT_PS_LRC_Y_MASK                    (0x3FFFU)
78552 #define PXP_OUT_PS_LRC_Y_SHIFT                   (0U)
78553 #define PXP_OUT_PS_LRC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)
78554 
78555 #define PXP_OUT_PS_LRC_X_MASK                    (0x3FFF0000U)
78556 #define PXP_OUT_PS_LRC_X_SHIFT                   (16U)
78557 #define PXP_OUT_PS_LRC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)
78558 /*! @} */
78559 
78560 /*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */
78561 /*! @{ */
78562 
78563 #define PXP_OUT_AS_ULC_Y_MASK                    (0x3FFFU)
78564 #define PXP_OUT_AS_ULC_Y_SHIFT                   (0U)
78565 #define PXP_OUT_AS_ULC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)
78566 
78567 #define PXP_OUT_AS_ULC_X_MASK                    (0x3FFF0000U)
78568 #define PXP_OUT_AS_ULC_X_SHIFT                   (16U)
78569 #define PXP_OUT_AS_ULC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)
78570 /*! @} */
78571 
78572 /*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */
78573 /*! @{ */
78574 
78575 #define PXP_OUT_AS_LRC_Y_MASK                    (0x3FFFU)
78576 #define PXP_OUT_AS_LRC_Y_SHIFT                   (0U)
78577 #define PXP_OUT_AS_LRC_Y(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)
78578 
78579 #define PXP_OUT_AS_LRC_X_MASK                    (0x3FFF0000U)
78580 #define PXP_OUT_AS_LRC_X_SHIFT                   (16U)
78581 #define PXP_OUT_AS_LRC_X(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)
78582 /*! @} */
78583 
78584 /*! @name PS_CTRL - Processed Surface (PS) Control Register */
78585 /*! @{ */
78586 
78587 #define PXP_PS_CTRL_FORMAT_MASK                  (0x3FU)
78588 #define PXP_PS_CTRL_FORMAT_SHIFT                 (0U)
78589 /*! FORMAT
78590  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
78591  *  0b001100..16-bit pixels with/without alpha at high 1bit
78592  *  0b001101..16-bit pixels with/without alpha at high 4 bits
78593  *  0b001110..16-bit pixels
78594  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
78595  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
78596  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
78597  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
78598  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
78599  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
78600  *  0b011001..16-bit pixels (2-plane UV)
78601  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
78602  *  0b011011..16-bit pixels (2-plane VU)
78603  *  0b011110..16-bit pixels (3-plane format)
78604  *  0b011111..16-bit pixels (3-plane format)
78605  *  0b100100..2-bit pixels with alpha at the low 8 bits
78606  *  0b101100..16-bit pixels with alpha at the low 1bits
78607  *  0b101101..16-bit pixels with alpha at the low 4 bits
78608  */
78609 #define PXP_PS_CTRL_FORMAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)
78610 
78611 #define PXP_PS_CTRL_WB_SWAP_MASK                 (0x40U)
78612 #define PXP_PS_CTRL_WB_SWAP_SHIFT                (6U)
78613 /*! WB_SWAP
78614  *  0b0..Byte swap is disabled
78615  *  0b1..Byte swap is enabled
78616  */
78617 #define PXP_PS_CTRL_WB_SWAP(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)
78618 
78619 #define PXP_PS_CTRL_DECY_MASK                    (0x300U)
78620 #define PXP_PS_CTRL_DECY_SHIFT                   (8U)
78621 /*! DECY
78622  *  0b00..Disable pre-decimation filter.
78623  *  0b01..Decimate PS by 2.
78624  *  0b10..Decimate PS by 4.
78625  *  0b11..Decimate PS by 8.
78626  */
78627 #define PXP_PS_CTRL_DECY(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)
78628 
78629 #define PXP_PS_CTRL_DECX_MASK                    (0xC00U)
78630 #define PXP_PS_CTRL_DECX_SHIFT                   (10U)
78631 /*! DECX
78632  *  0b00..Disable pre-decimation filter.
78633  *  0b01..Decimate PS by 2.
78634  *  0b10..Decimate PS by 4.
78635  *  0b11..Decimate PS by 8.
78636  */
78637 #define PXP_PS_CTRL_DECX(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)
78638 /*! @} */
78639 
78640 /*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */
78641 /*! @{ */
78642 
78643 #define PXP_PS_CTRL_SET_FORMAT_MASK              (0x3FU)
78644 #define PXP_PS_CTRL_SET_FORMAT_SHIFT             (0U)
78645 /*! FORMAT
78646  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
78647  *  0b001100..16-bit pixels with/without alpha at high 1bit
78648  *  0b001101..16-bit pixels with/without alpha at high 4 bits
78649  *  0b001110..16-bit pixels
78650  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
78651  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
78652  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
78653  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
78654  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
78655  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
78656  *  0b011001..16-bit pixels (2-plane UV)
78657  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
78658  *  0b011011..16-bit pixels (2-plane VU)
78659  *  0b011110..16-bit pixels (3-plane format)
78660  *  0b011111..16-bit pixels (3-plane format)
78661  *  0b100100..2-bit pixels with alpha at the low 8 bits
78662  *  0b101100..16-bit pixels with alpha at the low 1bits
78663  *  0b101101..16-bit pixels with alpha at the low 4 bits
78664  */
78665 #define PXP_PS_CTRL_SET_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)
78666 
78667 #define PXP_PS_CTRL_SET_WB_SWAP_MASK             (0x40U)
78668 #define PXP_PS_CTRL_SET_WB_SWAP_SHIFT            (6U)
78669 /*! WB_SWAP
78670  *  0b0..Byte swap is disabled
78671  *  0b1..Byte swap is enabled
78672  */
78673 #define PXP_PS_CTRL_SET_WB_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)
78674 
78675 #define PXP_PS_CTRL_SET_DECY_MASK                (0x300U)
78676 #define PXP_PS_CTRL_SET_DECY_SHIFT               (8U)
78677 /*! DECY
78678  *  0b00..Disable pre-decimation filter.
78679  *  0b01..Decimate PS by 2.
78680  *  0b10..Decimate PS by 4.
78681  *  0b11..Decimate PS by 8.
78682  */
78683 #define PXP_PS_CTRL_SET_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)
78684 
78685 #define PXP_PS_CTRL_SET_DECX_MASK                (0xC00U)
78686 #define PXP_PS_CTRL_SET_DECX_SHIFT               (10U)
78687 /*! DECX
78688  *  0b00..Disable pre-decimation filter.
78689  *  0b01..Decimate PS by 2.
78690  *  0b10..Decimate PS by 4.
78691  *  0b11..Decimate PS by 8.
78692  */
78693 #define PXP_PS_CTRL_SET_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)
78694 /*! @} */
78695 
78696 /*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */
78697 /*! @{ */
78698 
78699 #define PXP_PS_CTRL_CLR_FORMAT_MASK              (0x3FU)
78700 #define PXP_PS_CTRL_CLR_FORMAT_SHIFT             (0U)
78701 /*! FORMAT
78702  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
78703  *  0b001100..16-bit pixels with/without alpha at high 1bit
78704  *  0b001101..16-bit pixels with/without alpha at high 4 bits
78705  *  0b001110..16-bit pixels
78706  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
78707  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
78708  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
78709  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
78710  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
78711  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
78712  *  0b011001..16-bit pixels (2-plane UV)
78713  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
78714  *  0b011011..16-bit pixels (2-plane VU)
78715  *  0b011110..16-bit pixels (3-plane format)
78716  *  0b011111..16-bit pixels (3-plane format)
78717  *  0b100100..2-bit pixels with alpha at the low 8 bits
78718  *  0b101100..16-bit pixels with alpha at the low 1bits
78719  *  0b101101..16-bit pixels with alpha at the low 4 bits
78720  */
78721 #define PXP_PS_CTRL_CLR_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)
78722 
78723 #define PXP_PS_CTRL_CLR_WB_SWAP_MASK             (0x40U)
78724 #define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT            (6U)
78725 /*! WB_SWAP
78726  *  0b0..Byte swap is disabled
78727  *  0b1..Byte swap is enabled
78728  */
78729 #define PXP_PS_CTRL_CLR_WB_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)
78730 
78731 #define PXP_PS_CTRL_CLR_DECY_MASK                (0x300U)
78732 #define PXP_PS_CTRL_CLR_DECY_SHIFT               (8U)
78733 /*! DECY
78734  *  0b00..Disable pre-decimation filter.
78735  *  0b01..Decimate PS by 2.
78736  *  0b10..Decimate PS by 4.
78737  *  0b11..Decimate PS by 8.
78738  */
78739 #define PXP_PS_CTRL_CLR_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)
78740 
78741 #define PXP_PS_CTRL_CLR_DECX_MASK                (0xC00U)
78742 #define PXP_PS_CTRL_CLR_DECX_SHIFT               (10U)
78743 /*! DECX
78744  *  0b00..Disable pre-decimation filter.
78745  *  0b01..Decimate PS by 2.
78746  *  0b10..Decimate PS by 4.
78747  *  0b11..Decimate PS by 8.
78748  */
78749 #define PXP_PS_CTRL_CLR_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)
78750 /*! @} */
78751 
78752 /*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */
78753 /*! @{ */
78754 
78755 #define PXP_PS_CTRL_TOG_FORMAT_MASK              (0x3FU)
78756 #define PXP_PS_CTRL_TOG_FORMAT_SHIFT             (0U)
78757 /*! FORMAT
78758  *  0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
78759  *  0b001100..16-bit pixels with/without alpha at high 1bit
78760  *  0b001101..16-bit pixels with/without alpha at high 4 bits
78761  *  0b001110..16-bit pixels
78762  *  0b010000..32-bit pixels (1-plane XYUV unpacked)
78763  *  0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
78764  *  0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
78765  *  0b010100..8-bit monochrome pixels (1-plane Y luma output)
78766  *  0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
78767  *  0b011000..16-bit pixels (2-plane UV interleaved bytes)
78768  *  0b011001..16-bit pixels (2-plane UV)
78769  *  0b011010..16-bit pixels (2-plane VU interleaved bytes)
78770  *  0b011011..16-bit pixels (2-plane VU)
78771  *  0b011110..16-bit pixels (3-plane format)
78772  *  0b011111..16-bit pixels (3-plane format)
78773  *  0b100100..2-bit pixels with alpha at the low 8 bits
78774  *  0b101100..16-bit pixels with alpha at the low 1bits
78775  *  0b101101..16-bit pixels with alpha at the low 4 bits
78776  */
78777 #define PXP_PS_CTRL_TOG_FORMAT(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)
78778 
78779 #define PXP_PS_CTRL_TOG_WB_SWAP_MASK             (0x40U)
78780 #define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT            (6U)
78781 /*! WB_SWAP
78782  *  0b0..Byte swap is disabled
78783  *  0b1..Byte swap is enabled
78784  */
78785 #define PXP_PS_CTRL_TOG_WB_SWAP(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)
78786 
78787 #define PXP_PS_CTRL_TOG_DECY_MASK                (0x300U)
78788 #define PXP_PS_CTRL_TOG_DECY_SHIFT               (8U)
78789 /*! DECY
78790  *  0b00..Disable pre-decimation filter.
78791  *  0b01..Decimate PS by 2.
78792  *  0b10..Decimate PS by 4.
78793  *  0b11..Decimate PS by 8.
78794  */
78795 #define PXP_PS_CTRL_TOG_DECY(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)
78796 
78797 #define PXP_PS_CTRL_TOG_DECX_MASK                (0xC00U)
78798 #define PXP_PS_CTRL_TOG_DECX_SHIFT               (10U)
78799 /*! DECX
78800  *  0b00..Disable pre-decimation filter.
78801  *  0b01..Decimate PS by 2.
78802  *  0b10..Decimate PS by 4.
78803  *  0b11..Decimate PS by 8.
78804  */
78805 #define PXP_PS_CTRL_TOG_DECX(x)                  (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)
78806 /*! @} */
78807 
78808 /*! @name PS_BUF - PS Input Buffer Address */
78809 /*! @{ */
78810 
78811 #define PXP_PS_BUF_ADDR_MASK                     (0xFFFFFFFFU)
78812 #define PXP_PS_BUF_ADDR_SHIFT                    (0U)
78813 #define PXP_PS_BUF_ADDR(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)
78814 /*! @} */
78815 
78816 /*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */
78817 /*! @{ */
78818 
78819 #define PXP_PS_UBUF_ADDR_MASK                    (0xFFFFFFFFU)
78820 #define PXP_PS_UBUF_ADDR_SHIFT                   (0U)
78821 #define PXP_PS_UBUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)
78822 /*! @} */
78823 
78824 /*! @name PS_VBUF - PS V/Cr Input Buffer Address */
78825 /*! @{ */
78826 
78827 #define PXP_PS_VBUF_ADDR_MASK                    (0xFFFFFFFFU)
78828 #define PXP_PS_VBUF_ADDR_SHIFT                   (0U)
78829 #define PXP_PS_VBUF_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)
78830 /*! @} */
78831 
78832 /*! @name PS_PITCH - Processed Surface Pitch */
78833 /*! @{ */
78834 
78835 #define PXP_PS_PITCH_PITCH_MASK                  (0xFFFFU)
78836 #define PXP_PS_PITCH_PITCH_SHIFT                 (0U)
78837 #define PXP_PS_PITCH_PITCH(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)
78838 /*! @} */
78839 
78840 /*! @name PS_BACKGROUND - PS Background Color */
78841 /*! @{ */
78842 
78843 #define PXP_PS_BACKGROUND_COLOR_MASK             (0xFFFFFFU)
78844 #define PXP_PS_BACKGROUND_COLOR_SHIFT            (0U)
78845 #define PXP_PS_BACKGROUND_COLOR(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)
78846 /*! @} */
78847 
78848 /*! @name PS_SCALE - PS Scale Factor Register */
78849 /*! @{ */
78850 
78851 #define PXP_PS_SCALE_XSCALE_MASK                 (0x7FFFU)
78852 #define PXP_PS_SCALE_XSCALE_SHIFT                (0U)
78853 #define PXP_PS_SCALE_XSCALE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)
78854 
78855 #define PXP_PS_SCALE_YSCALE_MASK                 (0x7FFF0000U)
78856 #define PXP_PS_SCALE_YSCALE_SHIFT                (16U)
78857 #define PXP_PS_SCALE_YSCALE(x)                   (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)
78858 /*! @} */
78859 
78860 /*! @name PS_OFFSET - PS Scale Offset Register */
78861 /*! @{ */
78862 
78863 #define PXP_PS_OFFSET_XOFFSET_MASK               (0xFFFU)
78864 #define PXP_PS_OFFSET_XOFFSET_SHIFT              (0U)
78865 #define PXP_PS_OFFSET_XOFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)
78866 
78867 #define PXP_PS_OFFSET_YOFFSET_MASK               (0xFFF0000U)
78868 #define PXP_PS_OFFSET_YOFFSET_SHIFT              (16U)
78869 #define PXP_PS_OFFSET_YOFFSET(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)
78870 /*! @} */
78871 
78872 /*! @name PS_CLRKEYLOW - PS Color Key Low */
78873 /*! @{ */
78874 
78875 #define PXP_PS_CLRKEYLOW_PIXEL_MASK              (0xFFFFFFU)
78876 #define PXP_PS_CLRKEYLOW_PIXEL_SHIFT             (0U)
78877 #define PXP_PS_CLRKEYLOW_PIXEL(x)                (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)
78878 /*! @} */
78879 
78880 /*! @name PS_CLRKEYHIGH - PS Color Key High */
78881 /*! @{ */
78882 
78883 #define PXP_PS_CLRKEYHIGH_PIXEL_MASK             (0xFFFFFFU)
78884 #define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT            (0U)
78885 #define PXP_PS_CLRKEYHIGH_PIXEL(x)               (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)
78886 /*! @} */
78887 
78888 /*! @name AS_CTRL - Alpha Surface Control */
78889 /*! @{ */
78890 
78891 #define PXP_AS_CTRL_ALPHA_CTRL_MASK              (0x6U)
78892 #define PXP_AS_CTRL_ALPHA_CTRL_SHIFT             (1U)
78893 /*! ALPHA_CTRL
78894  *  0b00..Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored.
78895  *  0b01..Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels.
78896  *  0b10..Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel
78897  *        alpha is multiplied by the value in the ALPHA field.
78898  *  0b11..Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels.
78899  */
78900 #define PXP_AS_CTRL_ALPHA_CTRL(x)                (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)
78901 
78902 #define PXP_AS_CTRL_ENABLE_COLORKEY_MASK         (0x8U)
78903 #define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT        (3U)
78904 /*! ENABLE_COLORKEY
78905  *  0b0..Disabled
78906  *  0b1..Enabled
78907  */
78908 #define PXP_AS_CTRL_ENABLE_COLORKEY(x)           (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)
78909 
78910 #define PXP_AS_CTRL_FORMAT_MASK                  (0xF0U)
78911 #define PXP_AS_CTRL_FORMAT_SHIFT                 (4U)
78912 /*! FORMAT
78913  *  0b0000..32-bit pixels with alpha
78914  *  0b0001..2-bit pixel with alpha at low 8 bits
78915  *  0b0100..32-bit pixels without alpha (unpacked 24-bit format)
78916  *  0b1000..16-bit pixels with alpha
78917  *  0b1001..16-bit pixels with alpha
78918  *  0b1010..16-bit pixel with alpha at low 1 bit
78919  *  0b1011..16-bit pixel with alpha at low 4 bits
78920  *  0b1100..16-bit pixels without alpha
78921  *  0b1101..16-bit pixels without alpha
78922  *  0b1110..16-bit pixels without alpha
78923  */
78924 #define PXP_AS_CTRL_FORMAT(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)
78925 
78926 #define PXP_AS_CTRL_ALPHA_MASK                   (0xFF00U)
78927 #define PXP_AS_CTRL_ALPHA_SHIFT                  (8U)
78928 #define PXP_AS_CTRL_ALPHA(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)
78929 
78930 #define PXP_AS_CTRL_ROP_MASK                     (0xF0000U)
78931 #define PXP_AS_CTRL_ROP_SHIFT                    (16U)
78932 /*! ROP
78933  *  0b0000..AS AND PS
78934  *  0b0001..nAS AND PS
78935  *  0b0010..AS AND nPS
78936  *  0b0011..AS OR PS
78937  *  0b0100..nAS OR PS
78938  *  0b0101..AS OR nPS
78939  *  0b0110..nAS
78940  *  0b0111..nPS
78941  *  0b1000..AS NAND PS
78942  *  0b1001..AS NOR PS
78943  *  0b1010..AS XOR PS
78944  *  0b1011..AS XNOR PS
78945  */
78946 #define PXP_AS_CTRL_ROP(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)
78947 
78948 #define PXP_AS_CTRL_ALPHA_INVERT_MASK            (0x100000U)
78949 #define PXP_AS_CTRL_ALPHA_INVERT_SHIFT           (20U)
78950 /*! ALPHA_INVERT
78951  *  0b0..Not inverted
78952  *  0b1..Inverted
78953  */
78954 #define PXP_AS_CTRL_ALPHA_INVERT(x)              (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)
78955 /*! @} */
78956 
78957 /*! @name AS_BUF - Alpha Surface Buffer Pointer */
78958 /*! @{ */
78959 
78960 #define PXP_AS_BUF_ADDR_MASK                     (0xFFFFFFFFU)
78961 #define PXP_AS_BUF_ADDR_SHIFT                    (0U)
78962 #define PXP_AS_BUF_ADDR(x)                       (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)
78963 /*! @} */
78964 
78965 /*! @name AS_PITCH - Alpha Surface Pitch */
78966 /*! @{ */
78967 
78968 #define PXP_AS_PITCH_PITCH_MASK                  (0xFFFFU)
78969 #define PXP_AS_PITCH_PITCH_SHIFT                 (0U)
78970 #define PXP_AS_PITCH_PITCH(x)                    (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)
78971 /*! @} */
78972 
78973 /*! @name AS_CLRKEYLOW - Overlay Color Key Low */
78974 /*! @{ */
78975 
78976 #define PXP_AS_CLRKEYLOW_PIXEL_MASK              (0xFFFFFFU)
78977 #define PXP_AS_CLRKEYLOW_PIXEL_SHIFT             (0U)
78978 #define PXP_AS_CLRKEYLOW_PIXEL(x)                (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)
78979 /*! @} */
78980 
78981 /*! @name AS_CLRKEYHIGH - Overlay Color Key High */
78982 /*! @{ */
78983 
78984 #define PXP_AS_CLRKEYHIGH_PIXEL_MASK             (0xFFFFFFU)
78985 #define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT            (0U)
78986 #define PXP_AS_CLRKEYHIGH_PIXEL(x)               (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)
78987 /*! @} */
78988 
78989 /*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */
78990 /*! @{ */
78991 
78992 #define PXP_CSC1_COEF0_Y_OFFSET_MASK             (0x1FFU)
78993 #define PXP_CSC1_COEF0_Y_OFFSET_SHIFT            (0U)
78994 #define PXP_CSC1_COEF0_Y_OFFSET(x)               (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)
78995 
78996 #define PXP_CSC1_COEF0_UV_OFFSET_MASK            (0x3FE00U)
78997 #define PXP_CSC1_COEF0_UV_OFFSET_SHIFT           (9U)
78998 #define PXP_CSC1_COEF0_UV_OFFSET(x)              (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)
78999 
79000 #define PXP_CSC1_COEF0_C0_MASK                   (0x1FFC0000U)
79001 #define PXP_CSC1_COEF0_C0_SHIFT                  (18U)
79002 #define PXP_CSC1_COEF0_C0(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)
79003 
79004 #define PXP_CSC1_COEF0_BYPASS_MASK               (0x40000000U)
79005 #define PXP_CSC1_COEF0_BYPASS_SHIFT              (30U)
79006 #define PXP_CSC1_COEF0_BYPASS(x)                 (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)
79007 
79008 #define PXP_CSC1_COEF0_YCBCR_MODE_MASK           (0x80000000U)
79009 #define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT          (31U)
79010 /*! YCBCR_MODE
79011  *  0b0..YUV to RGB
79012  *  0b1..YCbCr to RGB
79013  */
79014 #define PXP_CSC1_COEF0_YCBCR_MODE(x)             (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)
79015 /*! @} */
79016 
79017 /*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */
79018 /*! @{ */
79019 
79020 #define PXP_CSC1_COEF1_C4_MASK                   (0x7FFU)
79021 #define PXP_CSC1_COEF1_C4_SHIFT                  (0U)
79022 #define PXP_CSC1_COEF1_C4(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)
79023 
79024 #define PXP_CSC1_COEF1_C1_MASK                   (0x7FF0000U)
79025 #define PXP_CSC1_COEF1_C1_SHIFT                  (16U)
79026 #define PXP_CSC1_COEF1_C1(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)
79027 /*! @} */
79028 
79029 /*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */
79030 /*! @{ */
79031 
79032 #define PXP_CSC1_COEF2_C3_MASK                   (0x7FFU)
79033 #define PXP_CSC1_COEF2_C3_SHIFT                  (0U)
79034 #define PXP_CSC1_COEF2_C3(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)
79035 
79036 #define PXP_CSC1_COEF2_C2_MASK                   (0x7FF0000U)
79037 #define PXP_CSC1_COEF2_C2_SHIFT                  (16U)
79038 #define PXP_CSC1_COEF2_C2(x)                     (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)
79039 /*! @} */
79040 
79041 /*! @name POWER - PXP Power Control Register */
79042 /*! @{ */
79043 
79044 #define PXP_POWER_ROT_MEM_LP_STATE_MASK          (0xE00U)
79045 #define PXP_POWER_ROT_MEM_LP_STATE_SHIFT         (9U)
79046 /*! ROT_MEM_LP_STATE
79047  *  0b000..Memory is not in low power state.
79048  *  0b001..Light Sleep Mode. Low leakage mode, maintain memory contents.
79049  *  0b010..Deep Sleep Mode. Low leakage mode, maintain memory contents.
79050  *  0b100..Shut Down Mode. Shut Down periphery and core, no memory retention.
79051  */
79052 #define PXP_POWER_ROT_MEM_LP_STATE(x)            (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)
79053 /*! @} */
79054 
79055 /*! @name NEXT - Next Frame Pointer */
79056 /*! @{ */
79057 
79058 #define PXP_NEXT_ENABLED_MASK                    (0x1U)
79059 #define PXP_NEXT_ENABLED_SHIFT                   (0U)
79060 #define PXP_NEXT_ENABLED(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)
79061 
79062 #define PXP_NEXT_POINTER_MASK                    (0xFFFFFFFCU)
79063 #define PXP_NEXT_POINTER_SHIFT                   (2U)
79064 #define PXP_NEXT_POINTER(x)                      (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)
79065 /*! @} */
79066 
79067 /*! @name PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register. */
79068 /*! @{ */
79069 
79070 #define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK (0x1U)
79071 #define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT (0U)
79072 /*! PORTER_DUFF_ENABLE
79073  *  0b0..Disabled
79074  *  0b1..Enabled
79075  */
79076 #define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK)
79077 
79078 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)
79079 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)
79080 /*! S0_S1_FACTOR_MODE
79081  *  0b00..1
79082  *  0b01..0
79083  *  0b10..Straight alpha
79084  *  0b11..Inverse alpha
79085  */
79086 #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)
79087 
79088 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)
79089 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)
79090 /*! S0_GLOBAL_ALPHA_MODE
79091  *  0b00..Global alpha
79092  *  0b01..Local alpha
79093  *  0b10..Scaled alpha
79094  *  0b11..Scaled alpha
79095  */
79096 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)
79097 
79098 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK  (0x20U)
79099 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)
79100 /*! S0_ALPHA_MODE
79101  *  0b0..Straight mode
79102  *  0b1..Inverted mode
79103  */
79104 #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)
79105 
79106 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK  (0x40U)
79107 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)
79108 /*! S0_COLOR_MODE
79109  *  0b0..Original pixel
79110  *  0b1..Scaled pixel
79111  */
79112 #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)
79113 
79114 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)
79115 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)
79116 /*! S1_S0_FACTOR_MODE
79117  *  0b00..1
79118  *  0b01..0
79119  *  0b10..Straight alpha
79120  *  0b11..Inverse alpha
79121  */
79122 #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)
79123 
79124 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)
79125 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)
79126 /*! S1_GLOBAL_ALPHA_MODE
79127  *  0b00..Global alpha
79128  *  0b01..Local alpha
79129  *  0b10..Scaled alpha
79130  *  0b11..Scaled alpha
79131  */
79132 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)
79133 
79134 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK  (0x1000U)
79135 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)
79136 /*! S1_ALPHA_MODE
79137  *  0b0..Straight mode
79138  *  0b1..Inverted mode
79139  */
79140 #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)
79141 
79142 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK  (0x2000U)
79143 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)
79144 /*! S1_COLOR_MODE
79145  *  0b0..Original pixel
79146  *  0b1..Scaled pixel
79147  */
79148 #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x)    (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)
79149 
79150 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)
79151 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)
79152 #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x)  (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)
79153 
79154 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)
79155 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)
79156 #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x)  (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK)
79157 /*! @} */
79158 
79159 
79160 /*!
79161  * @}
79162  */ /* end of group PXP_Register_Masks */
79163 
79164 
79165 /* PXP - Peripheral instance base addresses */
79166 /** Peripheral PXP base address */
79167 #define PXP_BASE                                 (0x40814000u)
79168 /** Peripheral PXP base pointer */
79169 #define PXP                                      ((PXP_Type *)PXP_BASE)
79170 /** Array initializer of PXP peripheral base addresses */
79171 #define PXP_BASE_ADDRS                           { PXP_BASE }
79172 /** Array initializer of PXP peripheral base pointers */
79173 #define PXP_BASE_PTRS                            { PXP }
79174 /** Interrupt vectors for the PXP peripheral type */
79175 #define PXP_IRQ0_IRQS                            { PXP_IRQn }
79176 
79177 /*!
79178  * @}
79179  */ /* end of group PXP_Peripheral_Access_Layer */
79180 
79181 
79182 /* ----------------------------------------------------------------------------
79183    -- RDC Peripheral Access Layer
79184    ---------------------------------------------------------------------------- */
79185 
79186 /*!
79187  * @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer
79188  * @{
79189  */
79190 
79191 /** RDC - Register Layout Typedef */
79192 typedef struct {
79193   __I  uint32_t VIR;                               /**< Version Information, offset: 0x0 */
79194        uint8_t RESERVED_0[32];
79195   __IO uint32_t STAT;                              /**< Status, offset: 0x24 */
79196   __IO uint32_t INTCTRL;                           /**< Interrupt and Control, offset: 0x28 */
79197   __IO uint32_t INTSTAT;                           /**< Interrupt Status, offset: 0x2C */
79198        uint8_t RESERVED_1[464];
79199   __IO uint32_t MDA[12];                           /**< Master Domain Assignment, array offset: 0x200, array step: 0x4 */
79200        uint8_t RESERVED_2[464];
79201   __IO uint32_t PDAP[128];                         /**< Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4 */
79202        uint8_t RESERVED_3[512];
79203   struct {                                         /* offset: 0x800, array step: 0x10 */
79204     __IO uint32_t MRSA;                              /**< Memory Region Start Address, array offset: 0x800, array step: 0x10 */
79205     __IO uint32_t MREA;                              /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */
79206     __IO uint32_t MRC;                               /**< Memory Region Control, array offset: 0x808, array step: 0x10 */
79207     __IO uint32_t MRVS;                              /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */
79208   } MR[59];
79209 } RDC_Type;
79210 
79211 /* ----------------------------------------------------------------------------
79212    -- RDC Register Masks
79213    ---------------------------------------------------------------------------- */
79214 
79215 /*!
79216  * @addtogroup RDC_Register_Masks RDC Register Masks
79217  * @{
79218  */
79219 
79220 /*! @name VIR - Version Information */
79221 /*! @{ */
79222 
79223 #define RDC_VIR_NDID_MASK                        (0xFU)
79224 #define RDC_VIR_NDID_SHIFT                       (0U)
79225 /*! NDID - Number of Domains */
79226 #define RDC_VIR_NDID(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK)
79227 
79228 #define RDC_VIR_NMSTR_MASK                       (0xFF0U)
79229 #define RDC_VIR_NMSTR_SHIFT                      (4U)
79230 /*! NMSTR - Number of Masters */
79231 #define RDC_VIR_NMSTR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK)
79232 
79233 #define RDC_VIR_NPER_MASK                        (0xFF000U)
79234 #define RDC_VIR_NPER_SHIFT                       (12U)
79235 /*! NPER - Number of Peripherals */
79236 #define RDC_VIR_NPER(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK)
79237 
79238 #define RDC_VIR_NRGN_MASK                        (0xFF00000U)
79239 #define RDC_VIR_NRGN_SHIFT                       (20U)
79240 /*! NRGN - Number of Memory Regions */
79241 #define RDC_VIR_NRGN(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK)
79242 /*! @} */
79243 
79244 /*! @name STAT - Status */
79245 /*! @{ */
79246 
79247 #define RDC_STAT_DID_MASK                        (0xFU)
79248 #define RDC_STAT_DID_SHIFT                       (0U)
79249 /*! DID - Domain ID */
79250 #define RDC_STAT_DID(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK)
79251 
79252 #define RDC_STAT_PDS_MASK                        (0x100U)
79253 #define RDC_STAT_PDS_SHIFT                       (8U)
79254 /*! PDS - Power Domain Status
79255  *  0b0..Power Down Domain is OFF
79256  *  0b1..Power Down Domain is ON
79257  */
79258 #define RDC_STAT_PDS(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK)
79259 /*! @} */
79260 
79261 /*! @name INTCTRL - Interrupt and Control */
79262 /*! @{ */
79263 
79264 #define RDC_INTCTRL_RCI_EN_MASK                  (0x1U)
79265 #define RDC_INTCTRL_RCI_EN_SHIFT                 (0U)
79266 /*! RCI_EN - Restoration Complete Interrupt
79267  *  0b0..Interrupt Disabled
79268  *  0b1..Interrupt Enabled
79269  */
79270 #define RDC_INTCTRL_RCI_EN(x)                    (((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK)
79271 /*! @} */
79272 
79273 /*! @name INTSTAT - Interrupt Status */
79274 /*! @{ */
79275 
79276 #define RDC_INTSTAT_INT_MASK                     (0x1U)
79277 #define RDC_INTSTAT_INT_SHIFT                    (0U)
79278 /*! INT - Interrupt Status
79279  *  0b0..No Interrupt Pending
79280  *  0b1..Interrupt Pending
79281  */
79282 #define RDC_INTSTAT_INT(x)                       (((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK)
79283 /*! @} */
79284 
79285 /*! @name MDA - Master Domain Assignment */
79286 /*! @{ */
79287 
79288 #define RDC_MDA_DID_MASK                         (0x3U)
79289 #define RDC_MDA_DID_SHIFT                        (0U)
79290 /*! DID - Domain ID
79291  *  0b00..Master assigned to Processing Domain 0
79292  *  0b01..Master assigned to Processing Domain 1
79293  *  0b10..Reserved
79294  *  0b11..Reserved
79295  */
79296 #define RDC_MDA_DID(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK)
79297 
79298 #define RDC_MDA_LCK_MASK                         (0x80000000U)
79299 #define RDC_MDA_LCK_SHIFT                        (31U)
79300 /*! LCK - Assignment Lock
79301  *  0b0..Not Locked
79302  *  0b1..Locked
79303  */
79304 #define RDC_MDA_LCK(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK)
79305 /*! @} */
79306 
79307 /* The count of RDC_MDA */
79308 #define RDC_MDA_COUNT                            (12U)
79309 
79310 /*! @name PDAP - Peripheral Domain Access Permissions */
79311 /*! @{ */
79312 
79313 #define RDC_PDAP_D0W_MASK                        (0x1U)
79314 #define RDC_PDAP_D0W_SHIFT                       (0U)
79315 /*! D0W - Domain 0 Write Access
79316  *  0b0..No Write Access
79317  *  0b1..Write Access Allowed
79318  */
79319 #define RDC_PDAP_D0W(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK)
79320 
79321 #define RDC_PDAP_D0R_MASK                        (0x2U)
79322 #define RDC_PDAP_D0R_SHIFT                       (1U)
79323 /*! D0R - Domain 0 Read Access
79324  *  0b0..No Read Access
79325  *  0b1..Read Access Allowed
79326  */
79327 #define RDC_PDAP_D0R(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK)
79328 
79329 #define RDC_PDAP_D1W_MASK                        (0x4U)
79330 #define RDC_PDAP_D1W_SHIFT                       (2U)
79331 /*! D1W - Domain 1 Write Access
79332  *  0b0..No Write Access
79333  *  0b1..Write Access Allowed
79334  */
79335 #define RDC_PDAP_D1W(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK)
79336 
79337 #define RDC_PDAP_D1R_MASK                        (0x8U)
79338 #define RDC_PDAP_D1R_SHIFT                       (3U)
79339 /*! D1R - Domain 1 Read Access
79340  *  0b0..No Read Access
79341  *  0b1..Read Access Allowed
79342  */
79343 #define RDC_PDAP_D1R(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK)
79344 
79345 #define RDC_PDAP_SREQ_MASK                       (0x40000000U)
79346 #define RDC_PDAP_SREQ_SHIFT                      (30U)
79347 /*! SREQ - Semaphore Required
79348  *  0b0..Semaphores have no effect
79349  *  0b1..Semaphores are enforced
79350  */
79351 #define RDC_PDAP_SREQ(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK)
79352 
79353 #define RDC_PDAP_LCK_MASK                        (0x80000000U)
79354 #define RDC_PDAP_LCK_SHIFT                       (31U)
79355 /*! LCK - Peripheral Permissions Lock
79356  *  0b0..Not Locked
79357  *  0b1..Locked
79358  */
79359 #define RDC_PDAP_LCK(x)                          (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK)
79360 /*! @} */
79361 
79362 /* The count of RDC_PDAP */
79363 #define RDC_PDAP_COUNT                           (128U)
79364 
79365 /*! @name MRSA - Memory Region Start Address */
79366 /*! @{ */
79367 
79368 #define RDC_MRSA_SADR_MASK                       (0xFFFFFF80U)
79369 #define RDC_MRSA_SADR_SHIFT                      (7U)
79370 /*! SADR - Start address for memory region */
79371 #define RDC_MRSA_SADR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK)
79372 /*! @} */
79373 
79374 /* The count of RDC_MRSA */
79375 #define RDC_MRSA_COUNT                           (59U)
79376 
79377 /*! @name MREA - Memory Region End Address */
79378 /*! @{ */
79379 
79380 #define RDC_MREA_EADR_MASK                       (0xFFFFFF80U)
79381 #define RDC_MREA_EADR_SHIFT                      (7U)
79382 /*! EADR - Upper bound for memory region */
79383 #define RDC_MREA_EADR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK)
79384 /*! @} */
79385 
79386 /* The count of RDC_MREA */
79387 #define RDC_MREA_COUNT                           (59U)
79388 
79389 /*! @name MRC - Memory Region Control */
79390 /*! @{ */
79391 
79392 #define RDC_MRC_D0W_MASK                         (0x1U)
79393 #define RDC_MRC_D0W_SHIFT                        (0U)
79394 /*! D0W - Domain 0 Write Access to Region
79395  *  0b0..Processing Domain 0 does not have Write access to the memory region
79396  *  0b1..Processing Domain 0 has Write access to the memory region
79397  */
79398 #define RDC_MRC_D0W(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK)
79399 
79400 #define RDC_MRC_D0R_MASK                         (0x2U)
79401 #define RDC_MRC_D0R_SHIFT                        (1U)
79402 /*! D0R - Domain 0 Read Access to Region
79403  *  0b0..Processing Domain 0 does not have Read access to the memory region
79404  *  0b1..Processing Domain 0 has Read access to the memory region
79405  */
79406 #define RDC_MRC_D0R(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK)
79407 
79408 #define RDC_MRC_D1W_MASK                         (0x4U)
79409 #define RDC_MRC_D1W_SHIFT                        (2U)
79410 /*! D1W - Domain 1 Write Access to Region
79411  *  0b0..Processing Domain 1 does not have Write access to the memory region
79412  *  0b1..Processing Domain 1 has Write access to the memory region
79413  */
79414 #define RDC_MRC_D1W(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK)
79415 
79416 #define RDC_MRC_D1R_MASK                         (0x8U)
79417 #define RDC_MRC_D1R_SHIFT                        (3U)
79418 /*! D1R - Domain 1 Read Access to Region
79419  *  0b0..Processing Domain 1 does not have Read access to the memory region
79420  *  0b1..Processing Domain 1 has Read access to the memory region
79421  */
79422 #define RDC_MRC_D1R(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK)
79423 
79424 #define RDC_MRC_ENA_MASK                         (0x40000000U)
79425 #define RDC_MRC_ENA_SHIFT                        (30U)
79426 /*! ENA - Region Enable
79427  *  0b0..Memory region is not defined or restricted.
79428  *  0b1..Memory boundaries, domain permissions and controls are in effect.
79429  */
79430 #define RDC_MRC_ENA(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK)
79431 
79432 #define RDC_MRC_LCK_MASK                         (0x80000000U)
79433 #define RDC_MRC_LCK_SHIFT                        (31U)
79434 /*! LCK - Region Lock
79435  *  0b0..No Lock. All fields in this register may be modified.
79436  *  0b1..Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
79437  */
79438 #define RDC_MRC_LCK(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK)
79439 /*! @} */
79440 
79441 /* The count of RDC_MRC */
79442 #define RDC_MRC_COUNT                            (59U)
79443 
79444 /*! @name MRVS - Memory Region Violation Status */
79445 /*! @{ */
79446 
79447 #define RDC_MRVS_VDID_MASK                       (0x3U)
79448 #define RDC_MRVS_VDID_SHIFT                      (0U)
79449 /*! VDID - Violating Domain ID
79450  *  0b00..Processing Domain 0
79451  *  0b01..Processing Domain 1
79452  *  0b10..Reserved
79453  *  0b11..Reserved
79454  */
79455 #define RDC_MRVS_VDID(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK)
79456 
79457 #define RDC_MRVS_AD_MASK                         (0x10U)
79458 #define RDC_MRVS_AD_SHIFT                        (4U)
79459 /*! AD - Access Denied */
79460 #define RDC_MRVS_AD(x)                           (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK)
79461 
79462 #define RDC_MRVS_VADR_MASK                       (0xFFFFFFE0U)
79463 #define RDC_MRVS_VADR_SHIFT                      (5U)
79464 /*! VADR - Violating Address */
79465 #define RDC_MRVS_VADR(x)                         (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK)
79466 /*! @} */
79467 
79468 /* The count of RDC_MRVS */
79469 #define RDC_MRVS_COUNT                           (59U)
79470 
79471 
79472 /*!
79473  * @}
79474  */ /* end of group RDC_Register_Masks */
79475 
79476 
79477 /* RDC - Peripheral instance base addresses */
79478 /** Peripheral RDC base address */
79479 #define RDC_BASE                                 (0x40C78000u)
79480 /** Peripheral RDC base pointer */
79481 #define RDC                                      ((RDC_Type *)RDC_BASE)
79482 /** Array initializer of RDC peripheral base addresses */
79483 #define RDC_BASE_ADDRS                           { RDC_BASE }
79484 /** Array initializer of RDC peripheral base pointers */
79485 #define RDC_BASE_PTRS                            { RDC }
79486 /** Interrupt vectors for the RDC peripheral type */
79487 #define RDC_IRQS                                 { RDC_IRQn }
79488 
79489 /*!
79490  * @}
79491  */ /* end of group RDC_Peripheral_Access_Layer */
79492 
79493 
79494 /* ----------------------------------------------------------------------------
79495    -- RDC_SEMAPHORE Peripheral Access Layer
79496    ---------------------------------------------------------------------------- */
79497 
79498 /*!
79499  * @addtogroup RDC_SEMAPHORE_Peripheral_Access_Layer RDC_SEMAPHORE Peripheral Access Layer
79500  * @{
79501  */
79502 
79503 /** RDC_SEMAPHORE - Register Layout Typedef */
79504 typedef struct {
79505   __IO uint8_t GATE[64];                           /**< Gate Register, array offset: 0x0, array step: 0x1 */
79506        uint8_t RESERVED_0[2];
79507   union {                                          /* offset: 0x42 */
79508     __IO uint16_t RSTGT_R;                           /**< Reset Gate Read, offset: 0x42 */
79509     __IO uint16_t RSTGT_W;                           /**< Reset Gate Write, offset: 0x42 */
79510   };
79511 } RDC_SEMAPHORE_Type;
79512 
79513 /* ----------------------------------------------------------------------------
79514    -- RDC_SEMAPHORE Register Masks
79515    ---------------------------------------------------------------------------- */
79516 
79517 /*!
79518  * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks
79519  * @{
79520  */
79521 
79522 /*! @name GATE - Gate Register */
79523 /*! @{ */
79524 
79525 #define RDC_SEMAPHORE_GATE_GTFSM_MASK            (0xFU)
79526 #define RDC_SEMAPHORE_GATE_GTFSM_SHIFT           (0U)
79527 /*! GTFSM - Gate Finite State Machine.
79528  *  0b0000..The gate is unlocked (free).
79529  *  0b0001..The gate has been locked by processor with master_index = 0.
79530  *  0b0010..The gate has been locked by processor with master_index = 1.
79531  *  0b0011..The gate has been locked by processor with master_index = 2.
79532  *  0b0100..The gate has been locked by processor with master_index = 3.
79533  *  0b0101..The gate has been locked by processor with master_index = 4.
79534  *  0b0110..The gate has been locked by processor with master_index = 5.
79535  *  0b0111..The gate has been locked by processor with master_index = 6.
79536  *  0b1000..The gate has been locked by processor with master_index = 7.
79537  *  0b1001..The gate has been locked by processor with master_index = 8.
79538  *  0b1010..The gate has been locked by processor with master_index = 9.
79539  *  0b1011..The gate has been locked by processor with master_index = 10.
79540  *  0b1100..The gate has been locked by processor with master_index = 11.
79541  *  0b1101..The gate has been locked by processor with master_index = 12.
79542  *  0b1110..The gate has been locked by processor with master_index = 13.
79543  *  0b1111..The gate has been locked by processor with master_index = 14.
79544  */
79545 #define RDC_SEMAPHORE_GATE_GTFSM(x)              (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE_GTFSM_MASK)
79546 
79547 #define RDC_SEMAPHORE_GATE_LDOM_MASK             (0x30U)
79548 #define RDC_SEMAPHORE_GATE_LDOM_SHIFT            (4U)
79549 /*! LDOM
79550  *  0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
79551  *  0b01..The gate has been locked by domain 1.
79552  *  0b10..Reserved
79553  *  0b11..Reserved
79554  */
79555 #define RDC_SEMAPHORE_GATE_LDOM(x)               (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE_LDOM_MASK)
79556 /*! @} */
79557 
79558 /* The count of RDC_SEMAPHORE_GATE */
79559 #define RDC_SEMAPHORE_GATE_COUNT                 (64U)
79560 
79561 /*! @name RSTGT_R - Reset Gate Read */
79562 /*! @{ */
79563 
79564 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK        (0xFU)
79565 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT       (0U)
79566 #define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK)
79567 
79568 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK        (0x30U)
79569 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT       (4U)
79570 /*! RSTGSM
79571  *  0b00..Idle, waiting for the first data pattern write.
79572  *  0b01..Waiting for the second data pattern write.
79573  *  0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed,
79574  *        this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists
79575  *        for only one clock cycle. Software will never be able to observe this state.
79576  *  0b11..This state encoding is never used and therefore reserved.
79577  */
79578 #define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)
79579 
79580 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK        (0xFF00U)
79581 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT       (8U)
79582 #define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK)
79583 /*! @} */
79584 
79585 /*! @name RSTGT_W - Reset Gate Write */
79586 /*! @{ */
79587 
79588 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK        (0xFFU)
79589 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT       (0U)
79590 #define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK)
79591 
79592 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK        (0xFF00U)
79593 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT       (8U)
79594 #define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x)          (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK)
79595 /*! @} */
79596 
79597 
79598 /*!
79599  * @}
79600  */ /* end of group RDC_SEMAPHORE_Register_Masks */
79601 
79602 
79603 /* RDC_SEMAPHORE - Peripheral instance base addresses */
79604 /** Peripheral RDC_SEMAPHORE1 base address */
79605 #define RDC_SEMAPHORE1_BASE                      (0x40C44000u)
79606 /** Peripheral RDC_SEMAPHORE1 base pointer */
79607 #define RDC_SEMAPHORE1                           ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE)
79608 /** Peripheral RDC_SEMAPHORE2 base address */
79609 #define RDC_SEMAPHORE2_BASE                      (0x40CCC000u)
79610 /** Peripheral RDC_SEMAPHORE2 base pointer */
79611 #define RDC_SEMAPHORE2                           ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
79612 /** Array initializer of RDC_SEMAPHORE peripheral base addresses */
79613 #define RDC_SEMAPHORE_BASE_ADDRS                 { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
79614 /** Array initializer of RDC_SEMAPHORE peripheral base pointers */
79615 #define RDC_SEMAPHORE_BASE_PTRS                  { RDC_SEMAPHORE1, RDC_SEMAPHORE2 }
79616 
79617 /*!
79618  * @}
79619  */ /* end of group RDC_SEMAPHORE_Peripheral_Access_Layer */
79620 
79621 
79622 /* ----------------------------------------------------------------------------
79623    -- RTWDOG Peripheral Access Layer
79624    ---------------------------------------------------------------------------- */
79625 
79626 /*!
79627  * @addtogroup RTWDOG_Peripheral_Access_Layer RTWDOG Peripheral Access Layer
79628  * @{
79629  */
79630 
79631 /** RTWDOG - Register Layout Typedef */
79632 typedef struct {
79633   __IO uint32_t CS;                                /**< Watchdog Control and Status Register, offset: 0x0 */
79634   __IO uint32_t CNT;                               /**< Watchdog Counter Register, offset: 0x4 */
79635   __IO uint32_t TOVAL;                             /**< Watchdog Timeout Value Register, offset: 0x8 */
79636   __IO uint32_t WIN;                               /**< Watchdog Window Register, offset: 0xC */
79637 } RTWDOG_Type;
79638 
79639 /* ----------------------------------------------------------------------------
79640    -- RTWDOG Register Masks
79641    ---------------------------------------------------------------------------- */
79642 
79643 /*!
79644  * @addtogroup RTWDOG_Register_Masks RTWDOG Register Masks
79645  * @{
79646  */
79647 
79648 /*! @name CS - Watchdog Control and Status Register */
79649 /*! @{ */
79650 
79651 #define RTWDOG_CS_STOP_MASK                      (0x1U)
79652 #define RTWDOG_CS_STOP_SHIFT                     (0U)
79653 /*! STOP - Stop Enable
79654  *  0b0..Watchdog disabled in chip stop mode.
79655  *  0b1..Watchdog enabled in chip stop mode.
79656  */
79657 #define RTWDOG_CS_STOP(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
79658 
79659 #define RTWDOG_CS_WAIT_MASK                      (0x2U)
79660 #define RTWDOG_CS_WAIT_SHIFT                     (1U)
79661 /*! WAIT - Wait Enable
79662  *  0b0..Watchdog disabled in chip wait mode.
79663  *  0b1..Watchdog enabled in chip wait mode.
79664  */
79665 #define RTWDOG_CS_WAIT(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
79666 
79667 #define RTWDOG_CS_DBG_MASK                       (0x4U)
79668 #define RTWDOG_CS_DBG_SHIFT                      (2U)
79669 /*! DBG - Debug Enable
79670  *  0b0..Watchdog disabled in chip debug mode.
79671  *  0b1..Watchdog enabled in chip debug mode.
79672  */
79673 #define RTWDOG_CS_DBG(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
79674 
79675 #define RTWDOG_CS_TST_MASK                       (0x18U)
79676 #define RTWDOG_CS_TST_SHIFT                      (3U)
79677 /*! TST - Watchdog Test
79678  *  0b00..Watchdog test mode disabled.
79679  *  0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should
79680  *        use this setting to indicate that the watchdog is functioning normally in user mode.
79681  *  0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
79682  *  0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
79683  */
79684 #define RTWDOG_CS_TST(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
79685 
79686 #define RTWDOG_CS_UPDATE_MASK                    (0x20U)
79687 #define RTWDOG_CS_UPDATE_SHIFT                   (5U)
79688 /*! UPDATE - Allow updates
79689  *  0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
79690  *  0b1..Updates allowed. Software can modify the watchdog configuration registers within 255 bus clocks after performing the unlock write sequence.
79691  */
79692 #define RTWDOG_CS_UPDATE(x)                      (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
79693 
79694 #define RTWDOG_CS_INT_MASK                       (0x40U)
79695 #define RTWDOG_CS_INT_SHIFT                      (6U)
79696 /*! INT - Watchdog Interrupt
79697  *  0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed.
79698  *  0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 255 bus clocks from the interrupt vector fetch.
79699  */
79700 #define RTWDOG_CS_INT(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
79701 
79702 #define RTWDOG_CS_EN_MASK                        (0x80U)
79703 #define RTWDOG_CS_EN_SHIFT                       (7U)
79704 /*! EN - Watchdog Enable
79705  *  0b0..Watchdog disabled.
79706  *  0b1..Watchdog enabled.
79707  */
79708 #define RTWDOG_CS_EN(x)                          (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
79709 
79710 #define RTWDOG_CS_CLK_MASK                       (0x300U)
79711 #define RTWDOG_CS_CLK_SHIFT                      (8U)
79712 /*! CLK - Watchdog Clock */
79713 #define RTWDOG_CS_CLK(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
79714 
79715 #define RTWDOG_CS_RCS_MASK                       (0x400U)
79716 #define RTWDOG_CS_RCS_SHIFT                      (10U)
79717 /*! RCS - Reconfiguration Success
79718  *  0b0..Reconfiguring WDOG.
79719  *  0b1..Reconfiguration is successful.
79720  */
79721 #define RTWDOG_CS_RCS(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
79722 
79723 #define RTWDOG_CS_ULK_MASK                       (0x800U)
79724 #define RTWDOG_CS_ULK_SHIFT                      (11U)
79725 /*! ULK - Unlock status
79726  *  0b0..WDOG is locked.
79727  *  0b1..WDOG is unlocked.
79728  */
79729 #define RTWDOG_CS_ULK(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
79730 
79731 #define RTWDOG_CS_PRES_MASK                      (0x1000U)
79732 #define RTWDOG_CS_PRES_SHIFT                     (12U)
79733 /*! PRES - Watchdog prescaler
79734  *  0b0..256 prescaler disabled.
79735  *  0b1..256 prescaler enabled.
79736  */
79737 #define RTWDOG_CS_PRES(x)                        (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
79738 
79739 #define RTWDOG_CS_CMD32EN_MASK                   (0x2000U)
79740 #define RTWDOG_CS_CMD32EN_SHIFT                  (13U)
79741 /*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words
79742  *  0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.
79743  *  0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
79744  */
79745 #define RTWDOG_CS_CMD32EN(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
79746 
79747 #define RTWDOG_CS_FLG_MASK                       (0x4000U)
79748 #define RTWDOG_CS_FLG_SHIFT                      (14U)
79749 /*! FLG - Watchdog Interrupt Flag
79750  *  0b0..No interrupt occurred.
79751  *  0b1..An interrupt occurred.
79752  */
79753 #define RTWDOG_CS_FLG(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
79754 
79755 #define RTWDOG_CS_WIN_MASK                       (0x8000U)
79756 #define RTWDOG_CS_WIN_SHIFT                      (15U)
79757 /*! WIN - Watchdog Window
79758  *  0b0..Window mode disabled.
79759  *  0b1..Window mode enabled.
79760  */
79761 #define RTWDOG_CS_WIN(x)                         (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
79762 /*! @} */
79763 
79764 /*! @name CNT - Watchdog Counter Register */
79765 /*! @{ */
79766 
79767 #define RTWDOG_CNT_CNTLOW_MASK                   (0xFFU)
79768 #define RTWDOG_CNT_CNTLOW_SHIFT                  (0U)
79769 /*! CNTLOW - Low byte of the Watchdog Counter */
79770 #define RTWDOG_CNT_CNTLOW(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)
79771 
79772 #define RTWDOG_CNT_CNTHIGH_MASK                  (0xFF00U)
79773 #define RTWDOG_CNT_CNTHIGH_SHIFT                 (8U)
79774 /*! CNTHIGH - High byte of the Watchdog Counter */
79775 #define RTWDOG_CNT_CNTHIGH(x)                    (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)
79776 /*! @} */
79777 
79778 /*! @name TOVAL - Watchdog Timeout Value Register */
79779 /*! @{ */
79780 
79781 #define RTWDOG_TOVAL_TOVALLOW_MASK               (0xFFU)
79782 #define RTWDOG_TOVAL_TOVALLOW_SHIFT              (0U)
79783 /*! TOVALLOW - Low byte of the timeout value */
79784 #define RTWDOG_TOVAL_TOVALLOW(x)                 (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)
79785 
79786 #define RTWDOG_TOVAL_TOVALHIGH_MASK              (0xFF00U)
79787 #define RTWDOG_TOVAL_TOVALHIGH_SHIFT             (8U)
79788 /*! TOVALHIGH - High byte of the timeout value */
79789 #define RTWDOG_TOVAL_TOVALHIGH(x)                (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)
79790 /*! @} */
79791 
79792 /*! @name WIN - Watchdog Window Register */
79793 /*! @{ */
79794 
79795 #define RTWDOG_WIN_WINLOW_MASK                   (0xFFU)
79796 #define RTWDOG_WIN_WINLOW_SHIFT                  (0U)
79797 /*! WINLOW - Low byte of Watchdog Window */
79798 #define RTWDOG_WIN_WINLOW(x)                     (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)
79799 
79800 #define RTWDOG_WIN_WINHIGH_MASK                  (0xFF00U)
79801 #define RTWDOG_WIN_WINHIGH_SHIFT                 (8U)
79802 /*! WINHIGH - High byte of Watchdog Window */
79803 #define RTWDOG_WIN_WINHIGH(x)                    (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)
79804 /*! @} */
79805 
79806 
79807 /*!
79808  * @}
79809  */ /* end of group RTWDOG_Register_Masks */
79810 
79811 
79812 /* RTWDOG - Peripheral instance base addresses */
79813 /** Peripheral RTWDOG3 base address */
79814 #define RTWDOG3_BASE                             (0x40038000u)
79815 /** Peripheral RTWDOG3 base pointer */
79816 #define RTWDOG3                                  ((RTWDOG_Type *)RTWDOG3_BASE)
79817 /** Peripheral RTWDOG4 base address */
79818 #define RTWDOG4_BASE                             (0x40C10000u)
79819 /** Peripheral RTWDOG4 base pointer */
79820 #define RTWDOG4                                  ((RTWDOG_Type *)RTWDOG4_BASE)
79821 /** Array initializer of RTWDOG peripheral base addresses */
79822 #define RTWDOG_BASE_ADDRS                        { 0u, 0u, 0u, RTWDOG3_BASE, RTWDOG4_BASE }
79823 /** Array initializer of RTWDOG peripheral base pointers */
79824 #define RTWDOG_BASE_PTRS                         { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 }
79825 /** Interrupt vectors for the RTWDOG peripheral type */
79826 #define RTWDOG_IRQS                              { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG3_IRQn, NotAvail_IRQn }
79827 /* Extra definition */
79828 #define RTWDOG_UPDATE_KEY                        (0xD928C520U)
79829 #define RTWDOG_REFRESH_KEY                       (0xB480A602U)
79830 
79831 
79832 /*!
79833  * @}
79834  */ /* end of group RTWDOG_Peripheral_Access_Layer */
79835 
79836 
79837 /* ----------------------------------------------------------------------------
79838    -- SEMA4 Peripheral Access Layer
79839    ---------------------------------------------------------------------------- */
79840 
79841 /*!
79842  * @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer
79843  * @{
79844  */
79845 
79846 /** SEMA4 - Register Layout Typedef */
79847 typedef struct {
79848   __IO uint8_t GATE[16];                           /**< Semaphores Gate n Register, array offset: 0x0, array step: 0x1 */
79849        uint8_t RESERVED_0[48];
79850   struct {                                         /* offset: 0x40, array step: 0x8 */
79851     __IO uint16_t CPINE;                             /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */
79852          uint8_t RESERVED_0[6];
79853   } CPINE[2];
79854        uint8_t RESERVED_1[48];
79855   struct {                                         /* offset: 0x80, array step: 0x8 */
79856     __I  uint16_t CPNTF;                             /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */
79857          uint8_t RESERVED_0[6];
79858   } CPNTF[2];
79859        uint8_t RESERVED_2[112];
79860   __IO uint16_t RSTGT;                             /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */
79861        uint8_t RESERVED_3[2];
79862   __IO uint16_t RSTNTF;                            /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */
79863 } SEMA4_Type;
79864 
79865 /* ----------------------------------------------------------------------------
79866    -- SEMA4 Register Masks
79867    ---------------------------------------------------------------------------- */
79868 
79869 /*!
79870  * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks
79871  * @{
79872  */
79873 
79874 /*! @name GATE - Semaphores Gate n Register */
79875 /*! @{ */
79876 
79877 #define SEMA4_GATE_GTFSM_MASK                    (0x3U)
79878 #define SEMA4_GATE_GTFSM_SHIFT                   (0U)
79879 /*! GTFSM - Gate Finite State Machine.
79880  *  0b00..The gate is unlocked (free).
79881  *  0b01..The gate has been locked by processor 0.
79882  *  0b10..The gate has been locked by processor 1.
79883  *  0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
79884  *        operation" and do not affect the gate state machine.
79885  */
79886 #define SEMA4_GATE_GTFSM(x)                      (((uint8_t)(((uint8_t)(x)) << SEMA4_GATE_GTFSM_SHIFT)) & SEMA4_GATE_GTFSM_MASK)
79887 /*! @} */
79888 
79889 /* The count of SEMA4_GATE */
79890 #define SEMA4_GATE_COUNT                         (16U)
79891 
79892 /*! @name CPINE - Semaphores Processor n IRQ Notification Enable */
79893 /*! @{ */
79894 
79895 #define SEMA4_CPINE_INE7_MASK                    (0x1U)
79896 #define SEMA4_CPINE_INE7_SHIFT                   (0U)
79897 /*! INE7 - Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation
79898  *    of an interrupt notification from a failed attempt to lock gate 7.
79899  *  0b0..The generation of the notification interrupt is disabled.
79900  *  0b1..The generation of the notification interrupt is enabled.
79901  */
79902 #define SEMA4_CPINE_INE7(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK)
79903 
79904 #define SEMA4_CPINE_INE6_MASK                    (0x2U)
79905 #define SEMA4_CPINE_INE6_SHIFT                   (1U)
79906 /*! INE6 - Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation
79907  *    of an interrupt notification from a failed attempt to lock gate 6.
79908  *  0b0..The generation of the notification interrupt is disabled.
79909  *  0b1..The generation of the notification interrupt is enabled.
79910  */
79911 #define SEMA4_CPINE_INE6(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK)
79912 
79913 #define SEMA4_CPINE_INE5_MASK                    (0x4U)
79914 #define SEMA4_CPINE_INE5_SHIFT                   (2U)
79915 /*! INE5 - Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation
79916  *    of an interrupt notification from a failed attempt to lock gate 5.
79917  *  0b0..The generation of the notification interrupt is disabled.
79918  *  0b1..The generation of the notification interrupt is enabled.
79919  */
79920 #define SEMA4_CPINE_INE5(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK)
79921 
79922 #define SEMA4_CPINE_INE4_MASK                    (0x8U)
79923 #define SEMA4_CPINE_INE4_SHIFT                   (3U)
79924 /*! INE4 - Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation
79925  *    of an interrupt notification from a failed attempt to lock gate 4.
79926  *  0b0..The generation of the notification interrupt is disabled.
79927  *  0b1..The generation of the notification interrupt is enabled.
79928  */
79929 #define SEMA4_CPINE_INE4(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK)
79930 
79931 #define SEMA4_CPINE_INE3_MASK                    (0x10U)
79932 #define SEMA4_CPINE_INE3_SHIFT                   (4U)
79933 /*! INE3
79934  *  0b0..The generation of the notification interrupt is disabled.
79935  *  0b1..The generation of the notification interrupt is enabled.
79936  */
79937 #define SEMA4_CPINE_INE3(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK)
79938 
79939 #define SEMA4_CPINE_INE2_MASK                    (0x20U)
79940 #define SEMA4_CPINE_INE2_SHIFT                   (5U)
79941 /*! INE2
79942  *  0b0..The generation of the notification interrupt is disabled.
79943  *  0b1..The generation of the notification interrupt is enabled.
79944  */
79945 #define SEMA4_CPINE_INE2(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK)
79946 
79947 #define SEMA4_CPINE_INE1_MASK                    (0x40U)
79948 #define SEMA4_CPINE_INE1_SHIFT                   (6U)
79949 /*! INE1
79950  *  0b0..The generation of the notification interrupt is disabled.
79951  *  0b1..The generation of the notification interrupt is enabled.
79952  */
79953 #define SEMA4_CPINE_INE1(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK)
79954 
79955 #define SEMA4_CPINE_INE0_MASK                    (0x80U)
79956 #define SEMA4_CPINE_INE0_SHIFT                   (7U)
79957 /*! INE0
79958  *  0b0..The generation of the notification interrupt is disabled.
79959  *  0b1..The generation of the notification interrupt is enabled.
79960  */
79961 #define SEMA4_CPINE_INE0(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK)
79962 
79963 #define SEMA4_CPINE_INE15_MASK                   (0x100U)
79964 #define SEMA4_CPINE_INE15_SHIFT                  (8U)
79965 /*! INE15 - Interrupt Request Notification Enable 15. This field is a bitmap to enable the
79966  *    generation of an interrupt notification from a failed attempt to lock gate 15.
79967  *  0b0..The generation of the notification interrupt is disabled.
79968  *  0b1..The generation of the notification interrupt is enabled.
79969  */
79970 #define SEMA4_CPINE_INE15(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK)
79971 
79972 #define SEMA4_CPINE_INE14_MASK                   (0x200U)
79973 #define SEMA4_CPINE_INE14_SHIFT                  (9U)
79974 /*! INE14 - Interrupt Request Notification Enable 14. This field is a bitmap to enable the
79975  *    generation of an interrupt notification from a failed attempt to lock gate 14.
79976  *  0b0..The generation of the notification interrupt is disabled.
79977  *  0b1..The generation of the notification interrupt is enabled.
79978  */
79979 #define SEMA4_CPINE_INE14(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK)
79980 
79981 #define SEMA4_CPINE_INE13_MASK                   (0x400U)
79982 #define SEMA4_CPINE_INE13_SHIFT                  (10U)
79983 /*! INE13 - Interrupt Request Notification Enable 13. This field is a bitmap to enable the
79984  *    generation of an interrupt notification from a failed attempt to lock gate 13.
79985  *  0b0..The generation of the notification interrupt is disabled.
79986  *  0b1..The generation of the notification interrupt is enabled.
79987  */
79988 #define SEMA4_CPINE_INE13(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK)
79989 
79990 #define SEMA4_CPINE_INE12_MASK                   (0x800U)
79991 #define SEMA4_CPINE_INE12_SHIFT                  (11U)
79992 /*! INE12 - Interrupt Request Notification Enable 12. This field is a bitmap to enable the
79993  *    generation of an interrupt notification from a failed attempt to lock gate 12.
79994  *  0b0..The generation of the notification interrupt is disabled.
79995  *  0b1..The generation of the notification interrupt is enabled.
79996  */
79997 #define SEMA4_CPINE_INE12(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK)
79998 
79999 #define SEMA4_CPINE_INE11_MASK                   (0x1000U)
80000 #define SEMA4_CPINE_INE11_SHIFT                  (12U)
80001 /*! INE11 - Interrupt Request Notification Enable 11. This field is a bitmap to enable the
80002  *    generation of an interrupt notification from a failed attempt to lock gate 11.
80003  *  0b0..The generation of the notification interrupt is disabled.
80004  *  0b1..The generation of the notification interrupt is enabled.
80005  */
80006 #define SEMA4_CPINE_INE11(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK)
80007 
80008 #define SEMA4_CPINE_INE10_MASK                   (0x2000U)
80009 #define SEMA4_CPINE_INE10_SHIFT                  (13U)
80010 /*! INE10 - Interrupt Request Notification Enable 10. This field is a bitmap to enable the
80011  *    generation of an interrupt notification from a failed attempt to lock gate 10.
80012  *  0b0..The generation of the notification interrupt is disabled.
80013  *  0b1..The generation of the notification interrupt is enabled.
80014  */
80015 #define SEMA4_CPINE_INE10(x)                     (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK)
80016 
80017 #define SEMA4_CPINE_INE9_MASK                    (0x4000U)
80018 #define SEMA4_CPINE_INE9_SHIFT                   (14U)
80019 /*! INE9 - Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation
80020  *    of an interrupt notification from a failed attempt to lock gate 9.
80021  *  0b0..The generation of the notification interrupt is disabled.
80022  *  0b1..The generation of the notification interrupt is enabled.
80023  */
80024 #define SEMA4_CPINE_INE9(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK)
80025 
80026 #define SEMA4_CPINE_INE8_MASK                    (0x8000U)
80027 #define SEMA4_CPINE_INE8_SHIFT                   (15U)
80028 /*! INE8 - Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation
80029  *    of an interrupt notification from a failed attempt to lock gate 8.
80030  *  0b0..The generation of the notification interrupt is disabled.
80031  *  0b1..The generation of the notification interrupt is enabled.
80032  */
80033 #define SEMA4_CPINE_INE8(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK)
80034 /*! @} */
80035 
80036 /* The count of SEMA4_CPINE */
80037 #define SEMA4_CPINE_COUNT                        (2U)
80038 
80039 /*! @name CPNTF - Semaphores Processor n IRQ Notification */
80040 /*! @{ */
80041 
80042 #define SEMA4_CPNTF_GN7_MASK                     (0x1U)
80043 #define SEMA4_CPNTF_GN7_SHIFT                    (0U)
80044 #define SEMA4_CPNTF_GN7(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK)
80045 
80046 #define SEMA4_CPNTF_GN6_MASK                     (0x2U)
80047 #define SEMA4_CPNTF_GN6_SHIFT                    (1U)
80048 #define SEMA4_CPNTF_GN6(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK)
80049 
80050 #define SEMA4_CPNTF_GN5_MASK                     (0x4U)
80051 #define SEMA4_CPNTF_GN5_SHIFT                    (2U)
80052 #define SEMA4_CPNTF_GN5(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK)
80053 
80054 #define SEMA4_CPNTF_GN4_MASK                     (0x8U)
80055 #define SEMA4_CPNTF_GN4_SHIFT                    (3U)
80056 #define SEMA4_CPNTF_GN4(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK)
80057 
80058 #define SEMA4_CPNTF_GN3_MASK                     (0x10U)
80059 #define SEMA4_CPNTF_GN3_SHIFT                    (4U)
80060 #define SEMA4_CPNTF_GN3(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK)
80061 
80062 #define SEMA4_CPNTF_GN2_MASK                     (0x20U)
80063 #define SEMA4_CPNTF_GN2_SHIFT                    (5U)
80064 #define SEMA4_CPNTF_GN2(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK)
80065 
80066 #define SEMA4_CPNTF_GN1_MASK                     (0x40U)
80067 #define SEMA4_CPNTF_GN1_SHIFT                    (6U)
80068 #define SEMA4_CPNTF_GN1(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK)
80069 
80070 #define SEMA4_CPNTF_GN0_MASK                     (0x80U)
80071 #define SEMA4_CPNTF_GN0_SHIFT                    (7U)
80072 #define SEMA4_CPNTF_GN0(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK)
80073 
80074 #define SEMA4_CPNTF_GN15_MASK                    (0x100U)
80075 #define SEMA4_CPNTF_GN15_SHIFT                   (8U)
80076 #define SEMA4_CPNTF_GN15(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK)
80077 
80078 #define SEMA4_CPNTF_GN14_MASK                    (0x200U)
80079 #define SEMA4_CPNTF_GN14_SHIFT                   (9U)
80080 #define SEMA4_CPNTF_GN14(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK)
80081 
80082 #define SEMA4_CPNTF_GN13_MASK                    (0x400U)
80083 #define SEMA4_CPNTF_GN13_SHIFT                   (10U)
80084 #define SEMA4_CPNTF_GN13(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK)
80085 
80086 #define SEMA4_CPNTF_GN12_MASK                    (0x800U)
80087 #define SEMA4_CPNTF_GN12_SHIFT                   (11U)
80088 #define SEMA4_CPNTF_GN12(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK)
80089 
80090 #define SEMA4_CPNTF_GN11_MASK                    (0x1000U)
80091 #define SEMA4_CPNTF_GN11_SHIFT                   (12U)
80092 #define SEMA4_CPNTF_GN11(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK)
80093 
80094 #define SEMA4_CPNTF_GN10_MASK                    (0x2000U)
80095 #define SEMA4_CPNTF_GN10_SHIFT                   (13U)
80096 #define SEMA4_CPNTF_GN10(x)                      (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK)
80097 
80098 #define SEMA4_CPNTF_GN9_MASK                     (0x4000U)
80099 #define SEMA4_CPNTF_GN9_SHIFT                    (14U)
80100 #define SEMA4_CPNTF_GN9(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK)
80101 
80102 #define SEMA4_CPNTF_GN8_MASK                     (0x8000U)
80103 #define SEMA4_CPNTF_GN8_SHIFT                    (15U)
80104 #define SEMA4_CPNTF_GN8(x)                       (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK)
80105 /*! @} */
80106 
80107 /* The count of SEMA4_CPNTF */
80108 #define SEMA4_CPNTF_COUNT                        (2U)
80109 
80110 /*! @name RSTGT - Semaphores (Secure) Reset Gate n */
80111 /*! @{ */
80112 
80113 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK    (0xFFU)
80114 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT   (0U)
80115 #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x)      (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK)
80116 
80117 #define SEMA4_RSTGT_RSTGTN_MASK                  (0xFF00U)
80118 #define SEMA4_RSTGT_RSTGTN_SHIFT                 (8U)
80119 #define SEMA4_RSTGT_RSTGTN(x)                    (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK)
80120 /*! @} */
80121 
80122 /*! @name RSTNTF - Semaphores (Secure) Reset IRQ Notification */
80123 /*! @{ */
80124 
80125 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK   (0xFFU)
80126 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT  (0U)
80127 #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x)     (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK)
80128 
80129 #define SEMA4_RSTNTF_RSTNTN_MASK                 (0xFF00U)
80130 #define SEMA4_RSTNTF_RSTNTN_SHIFT                (8U)
80131 #define SEMA4_RSTNTF_RSTNTN(x)                   (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK)
80132 /*! @} */
80133 
80134 
80135 /*!
80136  * @}
80137  */ /* end of group SEMA4_Register_Masks */
80138 
80139 
80140 /* SEMA4 - Peripheral instance base addresses */
80141 /** Peripheral SEMA4 base address */
80142 #define SEMA4_BASE                               (0x40CC8000u)
80143 /** Peripheral SEMA4 base pointer */
80144 #define SEMA4                                    ((SEMA4_Type *)SEMA4_BASE)
80145 /** Array initializer of SEMA4 peripheral base addresses */
80146 #define SEMA4_BASE_ADDRS                         { SEMA4_BASE }
80147 /** Array initializer of SEMA4 peripheral base pointers */
80148 #define SEMA4_BASE_PTRS                          { SEMA4 }
80149 
80150 /*!
80151  * @}
80152  */ /* end of group SEMA4_Peripheral_Access_Layer */
80153 
80154 
80155 /* ----------------------------------------------------------------------------
80156    -- SEMC Peripheral Access Layer
80157    ---------------------------------------------------------------------------- */
80158 
80159 /*!
80160  * @addtogroup SEMC_Peripheral_Access_Layer SEMC Peripheral Access Layer
80161  * @{
80162  */
80163 
80164 /** SEMC - Register Layout Typedef */
80165 typedef struct {
80166   __IO uint32_t MCR;                               /**< Module Control Register, offset: 0x0 */
80167   __IO uint32_t IOCR;                              /**< IO MUX Control Register, offset: 0x4 */
80168   __IO uint32_t BMCR0;                             /**< Bus (AXI) Master Control Register 0, offset: 0x8 */
80169   __IO uint32_t BMCR1;                             /**< Bus (AXI) Master Control Register 1, offset: 0xC */
80170   __IO uint32_t BR[9];                             /**< Base Register 0..Base Register 8, array offset: 0x10, array step: 0x4 */
80171   __IO uint32_t DLLCR;                             /**< DLL Control Register, offset: 0x34 */
80172   __IO uint32_t INTEN;                             /**< Interrupt Enable Register, offset: 0x38 */
80173   __IO uint32_t INTR;                              /**< Interrupt Register, offset: 0x3C */
80174   __IO uint32_t SDRAMCR0;                          /**< SDRAM Control Register 0, offset: 0x40 */
80175   __IO uint32_t SDRAMCR1;                          /**< SDRAM Control Register 1, offset: 0x44 */
80176   __IO uint32_t SDRAMCR2;                          /**< SDRAM Control Register 2, offset: 0x48 */
80177   __IO uint32_t SDRAMCR3;                          /**< SDRAM Control Register 3, offset: 0x4C */
80178   __IO uint32_t NANDCR0;                           /**< NAND Control Register 0, offset: 0x50 */
80179   __IO uint32_t NANDCR1;                           /**< NAND Control Register 1, offset: 0x54 */
80180   __IO uint32_t NANDCR2;                           /**< NAND Control Register 2, offset: 0x58 */
80181   __IO uint32_t NANDCR3;                           /**< NAND Control Register 3, offset: 0x5C */
80182   __IO uint32_t NORCR0;                            /**< NOR Control Register 0, offset: 0x60 */
80183   __IO uint32_t NORCR1;                            /**< NOR Control Register 1, offset: 0x64 */
80184   __IO uint32_t NORCR2;                            /**< NOR Control Register 2, offset: 0x68 */
80185   __IO uint32_t NORCR3;                            /**< NOR Control Register 3, offset: 0x6C */
80186   __IO uint32_t SRAMCR0;                           /**< SRAM Control Register 0, offset: 0x70 */
80187   __IO uint32_t SRAMCR1;                           /**< SRAM Control Register 1, offset: 0x74 */
80188   __IO uint32_t SRAMCR2;                           /**< SRAM Control Register 2, offset: 0x78 */
80189        uint32_t SRAMCR3;                           /**< SRAM Control Register 3, offset: 0x7C */
80190   __IO uint32_t DBICR0;                            /**< DBI-B Control Register 0, offset: 0x80 */
80191   __IO uint32_t DBICR1;                            /**< DBI-B Control Register 1, offset: 0x84 */
80192   __IO uint32_t DBICR2;                            /**< DBI-B Control Register 2, offset: 0x88 */
80193        uint8_t RESERVED_0[4];
80194   __IO uint32_t IPCR0;                             /**< IP Command Control Register 0, offset: 0x90 */
80195   __IO uint32_t IPCR1;                             /**< IP Command Control Register 1, offset: 0x94 */
80196   __IO uint32_t IPCR2;                             /**< IP Command Control Register 2, offset: 0x98 */
80197   __IO uint32_t IPCMD;                             /**< IP Command Register, offset: 0x9C */
80198   __IO uint32_t IPTXDAT;                           /**< TX DATA Register, offset: 0xA0 */
80199        uint8_t RESERVED_1[12];
80200   __I  uint32_t IPRXDAT;                           /**< RX DATA Register, offset: 0xB0 */
80201        uint8_t RESERVED_2[12];
80202   __I  uint32_t STS0;                              /**< Status Register 0, offset: 0xC0 */
80203        uint32_t STS1;                              /**< Status Register 1, offset: 0xC4 */
80204   __I  uint32_t STS2;                              /**< Status Register 2, offset: 0xC8 */
80205        uint32_t STS3;                              /**< Status Register 3, offset: 0xCC */
80206        uint32_t STS4;                              /**< Status Register 4, offset: 0xD0 */
80207        uint32_t STS5;                              /**< Status Register 5, offset: 0xD4 */
80208        uint32_t STS6;                              /**< Status Register 6, offset: 0xD8 */
80209        uint32_t STS7;                              /**< Status Register 7, offset: 0xDC */
80210        uint32_t STS8;                              /**< Status Register 8, offset: 0xE0 */
80211        uint32_t STS9;                              /**< Status Register 9, offset: 0xE4 */
80212        uint32_t STS10;                             /**< Status Register 10, offset: 0xE8 */
80213        uint32_t STS11;                             /**< Status Register 11, offset: 0xEC */
80214   __I  uint32_t STS12;                             /**< Status Register 12, offset: 0xF0 */
80215   __I  uint32_t STS13;                             /**< Status Register 13, offset: 0xF4 */
80216        uint32_t STS14;                             /**< Status Register 14, offset: 0xF8 */
80217        uint32_t STS15;                             /**< Status Register 15, offset: 0xFC */
80218   __IO uint32_t BR9;                               /**< Base Register 9, offset: 0x100 */
80219   __IO uint32_t BR10;                              /**< Base Register 10, offset: 0x104 */
80220   __IO uint32_t BR11;                              /**< Base Register 11, offset: 0x108 */
80221        uint8_t RESERVED_3[20];
80222   __IO uint32_t SRAMCR4;                           /**< SRAM Control Register 4, offset: 0x120 */
80223   __IO uint32_t SRAMCR5;                           /**< SRAM Control Register 5, offset: 0x124 */
80224   __IO uint32_t SRAMCR6;                           /**< SRAM Control Register 6, offset: 0x128 */
80225        uint8_t RESERVED_4[36];
80226   __IO uint32_t DCCR;                              /**< Delay Chain Control Register, offset: 0x150 */
80227 } SEMC_Type;
80228 
80229 /* ----------------------------------------------------------------------------
80230    -- SEMC Register Masks
80231    ---------------------------------------------------------------------------- */
80232 
80233 /*!
80234  * @addtogroup SEMC_Register_Masks SEMC Register Masks
80235  * @{
80236  */
80237 
80238 /*! @name MCR - Module Control Register */
80239 /*! @{ */
80240 
80241 #define SEMC_MCR_SWRST_MASK                      (0x1U)
80242 #define SEMC_MCR_SWRST_SHIFT                     (0U)
80243 /*! SWRST - Software Reset
80244  *  0b0..No reset
80245  *  0b1..Reset
80246  */
80247 #define SEMC_MCR_SWRST(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
80248 
80249 #define SEMC_MCR_MDIS_MASK                       (0x2U)
80250 #define SEMC_MCR_MDIS_SHIFT                      (1U)
80251 /*! MDIS - Module Disable
80252  *  0b0..Module enabled
80253  *  0b1..Module disabled
80254  */
80255 #define SEMC_MCR_MDIS(x)                         (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
80256 
80257 #define SEMC_MCR_DQSMD_MASK                      (0x4U)
80258 #define SEMC_MCR_DQSMD_SHIFT                     (2U)
80259 /*! DQSMD - DQS (read strobe) mode
80260  *  0b0..Dummy read strobe loopbacked internally
80261  *  0b1..Dummy read strobe loopbacked from DQS pad
80262  */
80263 #define SEMC_MCR_DQSMD(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
80264 
80265 #define SEMC_MCR_WPOL0_MASK                      (0x40U)
80266 #define SEMC_MCR_WPOL0_SHIFT                     (6U)
80267 /*! WPOL0 - WAIT/RDY polarity for SRAM/NOR
80268  *  0b0..WAIT/RDY polarity is not changed.
80269  *  0b1..WAIT/RDY polarity is inverted.
80270  */
80271 #define SEMC_MCR_WPOL0(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
80272 
80273 #define SEMC_MCR_WPOL1_MASK                      (0x80U)
80274 #define SEMC_MCR_WPOL1_SHIFT                     (7U)
80275 /*! WPOL1 - R/B# polarity for NAND device
80276  *  0b0..R/B# polarity is not changed.
80277  *  0b1..R/B# polarity is inverted.
80278  */
80279 #define SEMC_MCR_WPOL1(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
80280 
80281 #define SEMC_MCR_CTO_MASK                        (0xFF0000U)
80282 #define SEMC_MCR_CTO_SHIFT                       (16U)
80283 /*! CTO - Command Execution timeout cycles */
80284 #define SEMC_MCR_CTO(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
80285 
80286 #define SEMC_MCR_BTO_MASK                        (0x1F000000U)
80287 #define SEMC_MCR_BTO_SHIFT                       (24U)
80288 /*! BTO - Bus timeout cycles
80289  *  0b00000..255*1
80290  *  0b00001..255*2
80291  *  0b11111..255*2^31
80292  */
80293 #define SEMC_MCR_BTO(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
80294 /*! @} */
80295 
80296 /*! @name IOCR - IO MUX Control Register */
80297 /*! @{ */
80298 
80299 #define SEMC_IOCR_MUX_A8_MASK                    (0xFU)
80300 #define SEMC_IOCR_MUX_A8_SHIFT                   (0U)
80301 /*! MUX_A8 - SEMC_ADDR08 output selection
80302  *  0b0000-0b0011..SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode
80303  *  0b0100..NAND CE#
80304  *  0b0101..NOR CE#
80305  *  0b0110..SRAM CE# 0
80306  *  0b0111..DBI CSX
80307  *  0b1000..SRAM CE# 1
80308  *  0b1001..SRAM CE# 2
80309  *  0b1010..SRAM CE# 3
80310  *  0b1011-0b1111..SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode
80311  */
80312 #define SEMC_IOCR_MUX_A8(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
80313 
80314 #define SEMC_IOCR_MUX_CSX0_MASK                  (0xF0U)
80315 #define SEMC_IOCR_MUX_CSX0_SHIFT                 (4U)
80316 /*! MUX_CSX0 - SEMC_CSX0 output selection
80317  *  0b0000..NOR/SRAM Address bit 24 (A24) in Non-ADMUX mode
80318  *  0b0001..SDRAM CS1
80319  *  0b0010..SDRAM CS2
80320  *  0b0011..SDRAM CS3
80321  *  0b0100..NAND CE#
80322  *  0b0101..NOR CE#
80323  *  0b0110..SRAM CE# 0
80324  *  0b0111..DBI CSX
80325  *  0b1000..SRAM CE# 1
80326  *  0b1001..SRAM CE# 2
80327  *  0b1010..SRAM CE# 3
80328  *  0b1011-0b1111..NOR/SRAM Address bit 24 (A24) in Non-ADMUX mode
80329  */
80330 #define SEMC_IOCR_MUX_CSX0(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
80331 
80332 #define SEMC_IOCR_MUX_CSX1_MASK                  (0xF00U)
80333 #define SEMC_IOCR_MUX_CSX1_SHIFT                 (8U)
80334 /*! MUX_CSX1 - SEMC_CSX1 output selection
80335  *  0b0000..NOR/SRAM Address bit 25 (A25) in Non-ADMUX mode
80336  *  0b0001..SDRAM CS1
80337  *  0b0010..SDRAM CS2
80338  *  0b0011..SDRAM CS3
80339  *  0b0100..NAND CE#
80340  *  0b0101..NOR CE#
80341  *  0b0110..SRAM CE# 0
80342  *  0b0111..DBI CSX
80343  *  0b1000..SRAM CE# 1
80344  *  0b1001..SRAM CE# 2
80345  *  0b1010..SRAM CE# 3
80346  *  0b1011-0b1111..NOR/SRAM Address bit 25 (A25) in Non-ADMUX mode
80347  */
80348 #define SEMC_IOCR_MUX_CSX1(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
80349 
80350 #define SEMC_IOCR_MUX_CSX2_MASK                  (0xF000U)
80351 #define SEMC_IOCR_MUX_CSX2_SHIFT                 (12U)
80352 /*! MUX_CSX2 - SEMC_CSX2 output selection
80353  *  0b0000..NOR/SRAM Address bit 26 (A26) in Non-ADMUX mode
80354  *  0b0001..SDRAM CS1
80355  *  0b0010..SDRAM CS2
80356  *  0b0011..SDRAM CS3
80357  *  0b0100..NAND CE#
80358  *  0b0101..NOR CE#
80359  *  0b0110..SRAM CE# 0
80360  *  0b0111..DBI CSX
80361  *  0b1000..SRAM CE# 1
80362  *  0b1001..SRAM CE# 2
80363  *  0b1010..SRAM CE# 3
80364  *  0b1011-0b1111..NOR/SRAM Address bit 26 (A26) in Non-ADMUX mode
80365  */
80366 #define SEMC_IOCR_MUX_CSX2(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
80367 
80368 #define SEMC_IOCR_MUX_CSX3_MASK                  (0xF0000U)
80369 #define SEMC_IOCR_MUX_CSX3_SHIFT                 (16U)
80370 /*! MUX_CSX3 - SEMC_CSX3 output selection
80371  *  0b0000..NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode
80372  *  0b0001..SDRAM CS1
80373  *  0b0010..SDRAM CS2
80374  *  0b0011..SDRAM CS3
80375  *  0b0100..NAND CE#
80376  *  0b0101..NOR CE#
80377  *  0b0110..SRAM CE# 0
80378  *  0b0111..DBI CSX
80379  *  0b1000..SRAM CE# 1
80380  *  0b1001..SRAM CE# 2
80381  *  0b1010..SRAM CE# 3
80382  *  0b1011-0b1111..NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode
80383  */
80384 #define SEMC_IOCR_MUX_CSX3(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
80385 
80386 #define SEMC_IOCR_MUX_RDY_MASK                   (0xF00000U)
80387 #define SEMC_IOCR_MUX_RDY_SHIFT                  (20U)
80388 /*! MUX_RDY - SEMC_RDY function selection
80389  *  0b0000..NAND R/B# input
80390  *  0b0001..SDRAM CS1
80391  *  0b0010..SDRAM CS2
80392  *  0b0011..SDRAM CS3
80393  *  0b0100..NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode
80394  *  0b0101..NOR CE#
80395  *  0b0110..SRAM CE# 0
80396  *  0b0111..DBI CSX
80397  *  0b1000..SRAM CE# 1
80398  *  0b1001..SRAM CE# 2
80399  *  0b1010..SRAM CE# 3
80400  *  0b1011-0b1111..NOR/SRAM Address bit 27 in Non-ADMUX mode
80401  */
80402 #define SEMC_IOCR_MUX_RDY(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
80403 
80404 #define SEMC_IOCR_MUX_CLKX0_MASK                 (0x3000000U)
80405 #define SEMC_IOCR_MUX_CLKX0_SHIFT                (24U)
80406 /*! MUX_CLKX0 - SEMC_CLKX0 function selection
80407  *  0b00..Keep low
80408  *  0b01..NOR clock
80409  *  0b10..SRAM clock
80410  *  0b11..NOR and SRAM clock, suitable for Multi-Chip Product package
80411  */
80412 #define SEMC_IOCR_MUX_CLKX0(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK)
80413 
80414 #define SEMC_IOCR_MUX_CLKX1_MASK                 (0xC000000U)
80415 #define SEMC_IOCR_MUX_CLKX1_SHIFT                (26U)
80416 /*! MUX_CLKX1 - SEMC_CLKX1 function selection
80417  *  0b00..Keep low
80418  *  0b01..NOR clock
80419  *  0b10..SRAM clock
80420  *  0b11..NOR and SRAM clock, suitable for Multi-Chip Product package
80421  */
80422 #define SEMC_IOCR_MUX_CLKX1(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK)
80423 
80424 #define SEMC_IOCR_CLKX0_AO_MASK                  (0x10000000U)
80425 #define SEMC_IOCR_CLKX0_AO_SHIFT                 (28U)
80426 /*! CLKX0_AO - SEMC_CLKX0 Always On
80427  *  0b0..SEMC_CLKX0 is controlled by MUX_CLKX0
80428  *  0b1..SEMC_CLKX0 is always on
80429  */
80430 #define SEMC_IOCR_CLKX0_AO(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX0_AO_SHIFT)) & SEMC_IOCR_CLKX0_AO_MASK)
80431 
80432 #define SEMC_IOCR_CLKX1_AO_MASK                  (0x20000000U)
80433 #define SEMC_IOCR_CLKX1_AO_SHIFT                 (29U)
80434 /*! CLKX1_AO - SEMC_CLKX1 Always On
80435  *  0b0..SEMC_CLKX1 is controlled by MUX_CLKX1
80436  *  0b1..SEMC_CLKX1 is always on
80437  */
80438 #define SEMC_IOCR_CLKX1_AO(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX1_AO_SHIFT)) & SEMC_IOCR_CLKX1_AO_MASK)
80439 /*! @} */
80440 
80441 /*! @name BMCR0 - Bus (AXI) Master Control Register 0 */
80442 /*! @{ */
80443 
80444 #define SEMC_BMCR0_WQOS_MASK                     (0xFU)
80445 #define SEMC_BMCR0_WQOS_SHIFT                    (0U)
80446 /*! WQOS - Weight of QOS */
80447 #define SEMC_BMCR0_WQOS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
80448 
80449 #define SEMC_BMCR0_WAGE_MASK                     (0xF0U)
80450 #define SEMC_BMCR0_WAGE_SHIFT                    (4U)
80451 /*! WAGE - Weight of AGE */
80452 #define SEMC_BMCR0_WAGE(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
80453 
80454 #define SEMC_BMCR0_WSH_MASK                      (0xFF00U)
80455 #define SEMC_BMCR0_WSH_SHIFT                     (8U)
80456 /*! WSH - Weight of Slave Hit without read/write switch */
80457 #define SEMC_BMCR0_WSH(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
80458 
80459 #define SEMC_BMCR0_WRWS_MASK                     (0xFF0000U)
80460 #define SEMC_BMCR0_WRWS_SHIFT                    (16U)
80461 /*! WRWS - Weight of slave hit with Read/Write Switch */
80462 #define SEMC_BMCR0_WRWS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)
80463 /*! @} */
80464 
80465 /*! @name BMCR1 - Bus (AXI) Master Control Register 1 */
80466 /*! @{ */
80467 
80468 #define SEMC_BMCR1_WQOS_MASK                     (0xFU)
80469 #define SEMC_BMCR1_WQOS_SHIFT                    (0U)
80470 /*! WQOS - Weight of QOS */
80471 #define SEMC_BMCR1_WQOS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
80472 
80473 #define SEMC_BMCR1_WAGE_MASK                     (0xF0U)
80474 #define SEMC_BMCR1_WAGE_SHIFT                    (4U)
80475 /*! WAGE - Weight of AGE */
80476 #define SEMC_BMCR1_WAGE(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
80477 
80478 #define SEMC_BMCR1_WPH_MASK                      (0xFF00U)
80479 #define SEMC_BMCR1_WPH_SHIFT                     (8U)
80480 /*! WPH - Weight of Page Hit */
80481 #define SEMC_BMCR1_WPH(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
80482 
80483 #define SEMC_BMCR1_WRWS_MASK                     (0xFF0000U)
80484 #define SEMC_BMCR1_WRWS_SHIFT                    (16U)
80485 /*! WRWS - Weight of slave hit without Read/Write Switch */
80486 #define SEMC_BMCR1_WRWS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
80487 
80488 #define SEMC_BMCR1_WBR_MASK                      (0xFF000000U)
80489 #define SEMC_BMCR1_WBR_SHIFT                     (24U)
80490 /*! WBR - Weight of Bank Rotation */
80491 #define SEMC_BMCR1_WBR(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)
80492 /*! @} */
80493 
80494 /*! @name BR - Base Register 0..Base Register 8 */
80495 /*! @{ */
80496 
80497 #define SEMC_BR_VLD_MASK                         (0x1U)
80498 #define SEMC_BR_VLD_SHIFT                        (0U)
80499 /*! VLD - Valid
80500  *  0b0..The memory is invalid, can not be accessed.
80501  *  0b1..The memory is valid, can be accessed.
80502  */
80503 #define SEMC_BR_VLD(x)                           (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
80504 
80505 #define SEMC_BR_MS_MASK                          (0x3EU)
80506 #define SEMC_BR_MS_SHIFT                         (1U)
80507 /*! MS - Memory size
80508  *  0b00000..4KB
80509  *  0b00001..8KB
80510  *  0b00010..16KB
80511  *  0b00011..32KB
80512  *  0b00100..64KB
80513  *  0b00101..128KB
80514  *  0b00110..256KB
80515  *  0b00111..512KB
80516  *  0b01000..1MB
80517  *  0b01001..2MB
80518  *  0b01010..4MB
80519  *  0b01011..8MB
80520  *  0b01100..16MB
80521  *  0b01101..32MB
80522  *  0b01110..64MB
80523  *  0b01111..128MB
80524  *  0b10000..256MB
80525  *  0b10001..512MB
80526  *  0b10010..1GB
80527  *  0b10011..2GB
80528  *  0b10100-0b11111..4GB
80529  */
80530 #define SEMC_BR_MS(x)                            (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
80531 
80532 #define SEMC_BR_BA_MASK                          (0xFFFFF000U)
80533 #define SEMC_BR_BA_SHIFT                         (12U)
80534 /*! BA - Base Address */
80535 #define SEMC_BR_BA(x)                            (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)
80536 /*! @} */
80537 
80538 /* The count of SEMC_BR */
80539 #define SEMC_BR_COUNT                            (9U)
80540 
80541 /*! @name DLLCR - DLL Control Register */
80542 /*! @{ */
80543 
80544 #define SEMC_DLLCR_DLLEN_MASK                    (0x1U)
80545 #define SEMC_DLLCR_DLLEN_SHIFT                   (0U)
80546 /*! DLLEN - DLL calibration enable
80547  *  0b0..DLL calibration is disabled.
80548  *  0b1..DLL calibration is enabled.
80549  */
80550 #define SEMC_DLLCR_DLLEN(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK)
80551 
80552 #define SEMC_DLLCR_DLLRESET_MASK                 (0x2U)
80553 #define SEMC_DLLCR_DLLRESET_SHIFT                (1U)
80554 /*! DLLRESET - DLL Reset
80555  *  0b0..DLL is not reset.
80556  *  0b1..DLL is reset.
80557  */
80558 #define SEMC_DLLCR_DLLRESET(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK)
80559 
80560 #define SEMC_DLLCR_SLVDLYTARGET_MASK             (0x78U)
80561 #define SEMC_DLLCR_SLVDLYTARGET_SHIFT            (3U)
80562 /*! SLVDLYTARGET - Delay Target for Slave */
80563 #define SEMC_DLLCR_SLVDLYTARGET(x)               (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK)
80564 
80565 #define SEMC_DLLCR_OVRDEN_MASK                   (0x100U)
80566 #define SEMC_DLLCR_OVRDEN_SHIFT                  (8U)
80567 /*! OVRDEN - Override Enable
80568  *  0b0..The delay cell number is not overridden.
80569  *  0b1..The delay cell number is overridden.
80570  */
80571 #define SEMC_DLLCR_OVRDEN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK)
80572 
80573 #define SEMC_DLLCR_OVRDVAL_MASK                  (0x7E00U)
80574 #define SEMC_DLLCR_OVRDVAL_SHIFT                 (9U)
80575 /*! OVRDVAL - Override Value */
80576 #define SEMC_DLLCR_OVRDVAL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK)
80577 /*! @} */
80578 
80579 /*! @name INTEN - Interrupt Enable Register */
80580 /*! @{ */
80581 
80582 #define SEMC_INTEN_IPCMDDONEEN_MASK              (0x1U)
80583 #define SEMC_INTEN_IPCMDDONEEN_SHIFT             (0U)
80584 /*! IPCMDDONEEN - IP command done interrupt enable
80585  *  0b0..Interrupt is disabled
80586  *  0b1..Interrupt is enabled
80587  */
80588 #define SEMC_INTEN_IPCMDDONEEN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
80589 
80590 #define SEMC_INTEN_IPCMDERREN_MASK               (0x2U)
80591 #define SEMC_INTEN_IPCMDERREN_SHIFT              (1U)
80592 /*! IPCMDERREN - IP command error interrupt enable
80593  *  0b0..Interrupt is disabled
80594  *  0b1..Interrupt is enabled
80595  */
80596 #define SEMC_INTEN_IPCMDERREN(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
80597 
80598 #define SEMC_INTEN_AXICMDERREN_MASK              (0x4U)
80599 #define SEMC_INTEN_AXICMDERREN_SHIFT             (2U)
80600 /*! AXICMDERREN - AXI command error interrupt enable
80601  *  0b0..Interrupt is disabled
80602  *  0b1..Interrupt is enabled
80603  */
80604 #define SEMC_INTEN_AXICMDERREN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
80605 
80606 #define SEMC_INTEN_AXIBUSERREN_MASK              (0x8U)
80607 #define SEMC_INTEN_AXIBUSERREN_SHIFT             (3U)
80608 /*! AXIBUSERREN - AXI bus error interrupt enable
80609  *  0b0..Interrupt is disabled
80610  *  0b1..Interrupt is enabled
80611  */
80612 #define SEMC_INTEN_AXIBUSERREN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
80613 
80614 #define SEMC_INTEN_NDPAGEENDEN_MASK              (0x10U)
80615 #define SEMC_INTEN_NDPAGEENDEN_SHIFT             (4U)
80616 /*! NDPAGEENDEN - NAND page end interrupt enable
80617  *  0b0..Interrupt is disabled
80618  *  0b1..Interrupt is enabled
80619  */
80620 #define SEMC_INTEN_NDPAGEENDEN(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
80621 
80622 #define SEMC_INTEN_NDNOPENDEN_MASK               (0x20U)
80623 #define SEMC_INTEN_NDNOPENDEN_SHIFT              (5U)
80624 /*! NDNOPENDEN - NAND no pending AXI access interrupt enable
80625  *  0b0..Interrupt is disabled
80626  *  0b1..Interrupt is enabled
80627  */
80628 #define SEMC_INTEN_NDNOPENDEN(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
80629 /*! @} */
80630 
80631 /*! @name INTR - Interrupt Register */
80632 /*! @{ */
80633 
80634 #define SEMC_INTR_IPCMDDONE_MASK                 (0x1U)
80635 #define SEMC_INTR_IPCMDDONE_SHIFT                (0U)
80636 /*! IPCMDDONE - IP command normal done interrupt
80637  *  0b0..IP command is not done.
80638  *  0b1..IP command is done.
80639  */
80640 #define SEMC_INTR_IPCMDDONE(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
80641 
80642 #define SEMC_INTR_IPCMDERR_MASK                  (0x2U)
80643 #define SEMC_INTR_IPCMDERR_SHIFT                 (1U)
80644 /*! IPCMDERR - IP command error done interrupt
80645  *  0b0..No IP command error.
80646  *  0b1..IP command error occurs.
80647  */
80648 #define SEMC_INTR_IPCMDERR(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
80649 
80650 #define SEMC_INTR_AXICMDERR_MASK                 (0x4U)
80651 #define SEMC_INTR_AXICMDERR_SHIFT                (2U)
80652 /*! AXICMDERR - AXI command error interrupt
80653  *  0b0..No AXI command error.
80654  *  0b1..AXI command error occurs.
80655  */
80656 #define SEMC_INTR_AXICMDERR(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
80657 
80658 #define SEMC_INTR_AXIBUSERR_MASK                 (0x8U)
80659 #define SEMC_INTR_AXIBUSERR_SHIFT                (3U)
80660 /*! AXIBUSERR - AXI bus error interrupt
80661  *  0b0..No AXI bus error.
80662  *  0b1..AXI bus error occurs.
80663  */
80664 #define SEMC_INTR_AXIBUSERR(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
80665 
80666 #define SEMC_INTR_NDPAGEEND_MASK                 (0x10U)
80667 #define SEMC_INTR_NDPAGEEND_SHIFT                (4U)
80668 /*! NDPAGEEND - NAND page end interrupt
80669  *  0b0..The last address of main space in the NAND is not written by AXI command.
80670  *  0b1..The last address of main space in the NAND is written by AXI command.
80671  */
80672 #define SEMC_INTR_NDPAGEEND(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
80673 
80674 #define SEMC_INTR_NDNOPEND_MASK                  (0x20U)
80675 #define SEMC_INTR_NDNOPEND_SHIFT                 (5U)
80676 /*! NDNOPEND - NAND no pending AXI write transaction interrupt
80677  *  0b0..At least one NAND AXI write transaction is pending or no NAND write transaction is sent to the queue.
80678  *  0b1..All NAND AXI write pending transactions are finished.
80679  */
80680 #define SEMC_INTR_NDNOPEND(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)
80681 /*! @} */
80682 
80683 /*! @name SDRAMCR0 - SDRAM Control Register 0 */
80684 /*! @{ */
80685 
80686 #define SEMC_SDRAMCR0_PS_MASK                    (0x3U)
80687 #define SEMC_SDRAMCR0_PS_SHIFT                   (0U)
80688 /*! PS - Port Size
80689  *  0b00..8bit
80690  *  0b01..16bit
80691  *  0b10..32bit
80692  *  0b11..Reserved
80693  */
80694 #define SEMC_SDRAMCR0_PS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
80695 
80696 #define SEMC_SDRAMCR0_BL_MASK                    (0x70U)
80697 #define SEMC_SDRAMCR0_BL_SHIFT                   (4U)
80698 /*! BL - Burst Length
80699  *  0b000..1
80700  *  0b001..2
80701  *  0b010..4
80702  *  0b011..8
80703  *  0b100..8
80704  *  0b101..8
80705  *  0b110..8
80706  *  0b111..8
80707  */
80708 #define SEMC_SDRAMCR0_BL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
80709 
80710 #define SEMC_SDRAMCR0_COL8_MASK                  (0x80U)
80711 #define SEMC_SDRAMCR0_COL8_SHIFT                 (7U)
80712 /*! COL8 - Column 8 selection
80713  *  0b0..Column address bit number is decided by COL field.
80714  *  0b1..Column address bit number is 8. COL field is ignored.
80715  */
80716 #define SEMC_SDRAMCR0_COL8(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK)
80717 
80718 #define SEMC_SDRAMCR0_COL_MASK                   (0x300U)
80719 #define SEMC_SDRAMCR0_COL_SHIFT                  (8U)
80720 /*! COL - Column address bit number
80721  *  0b00..12
80722  *  0b01..11
80723  *  0b10..10
80724  *  0b11..9
80725  */
80726 #define SEMC_SDRAMCR0_COL(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
80727 
80728 #define SEMC_SDRAMCR0_CL_MASK                    (0xC00U)
80729 #define SEMC_SDRAMCR0_CL_SHIFT                   (10U)
80730 /*! CL - CAS Latency
80731  *  0b00..1
80732  *  0b01..1
80733  *  0b10..2
80734  *  0b11..3
80735  */
80736 #define SEMC_SDRAMCR0_CL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
80737 
80738 #define SEMC_SDRAMCR0_BANK2_MASK                 (0x4000U)
80739 #define SEMC_SDRAMCR0_BANK2_SHIFT                (14U)
80740 /*! BANK2 - 2 Bank selection bit
80741  *  0b0..SDRAM device has 4 banks.
80742  *  0b1..SDRAM device has 2 banks.
80743  */
80744 #define SEMC_SDRAMCR0_BANK2(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK)
80745 /*! @} */
80746 
80747 /*! @name SDRAMCR1 - SDRAM Control Register 1 */
80748 /*! @{ */
80749 
80750 #define SEMC_SDRAMCR1_PRE2ACT_MASK               (0xFU)
80751 #define SEMC_SDRAMCR1_PRE2ACT_SHIFT              (0U)
80752 /*! PRE2ACT - PRECHARGE to ACTIVE/REFRESH command wait time */
80753 #define SEMC_SDRAMCR1_PRE2ACT(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
80754 
80755 #define SEMC_SDRAMCR1_ACT2RW_MASK                (0xF0U)
80756 #define SEMC_SDRAMCR1_ACT2RW_SHIFT               (4U)
80757 /*! ACT2RW - ACTIVE to READ/WRITE delay */
80758 #define SEMC_SDRAMCR1_ACT2RW(x)                  (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
80759 
80760 #define SEMC_SDRAMCR1_RFRC_MASK                  (0x1F00U)
80761 #define SEMC_SDRAMCR1_RFRC_SHIFT                 (8U)
80762 /*! RFRC - REFRESH recovery time */
80763 #define SEMC_SDRAMCR1_RFRC(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
80764 
80765 #define SEMC_SDRAMCR1_WRC_MASK                   (0xE000U)
80766 #define SEMC_SDRAMCR1_WRC_SHIFT                  (13U)
80767 /*! WRC - WRITE recovery time */
80768 #define SEMC_SDRAMCR1_WRC(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
80769 
80770 #define SEMC_SDRAMCR1_CKEOFF_MASK                (0xF0000U)
80771 #define SEMC_SDRAMCR1_CKEOFF_SHIFT               (16U)
80772 /*! CKEOFF - CKE off minimum time */
80773 #define SEMC_SDRAMCR1_CKEOFF(x)                  (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
80774 
80775 #define SEMC_SDRAMCR1_ACT2PRE_MASK               (0xF00000U)
80776 #define SEMC_SDRAMCR1_ACT2PRE_SHIFT              (20U)
80777 /*! ACT2PRE - ACTIVE to PRECHARGE minimum time */
80778 #define SEMC_SDRAMCR1_ACT2PRE(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)
80779 /*! @} */
80780 
80781 /*! @name SDRAMCR2 - SDRAM Control Register 2 */
80782 /*! @{ */
80783 
80784 #define SEMC_SDRAMCR2_SRRC_MASK                  (0xFFU)
80785 #define SEMC_SDRAMCR2_SRRC_SHIFT                 (0U)
80786 /*! SRRC - SELF REFRESH recovery time */
80787 #define SEMC_SDRAMCR2_SRRC(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
80788 
80789 #define SEMC_SDRAMCR2_REF2REF_MASK               (0xFF00U)
80790 #define SEMC_SDRAMCR2_REF2REF_SHIFT              (8U)
80791 /*! REF2REF - REFRESH to REFRESH delay */
80792 #define SEMC_SDRAMCR2_REF2REF(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
80793 
80794 #define SEMC_SDRAMCR2_ACT2ACT_MASK               (0xFF0000U)
80795 #define SEMC_SDRAMCR2_ACT2ACT_SHIFT              (16U)
80796 /*! ACT2ACT - ACTIVE to ACTIVE delay */
80797 #define SEMC_SDRAMCR2_ACT2ACT(x)                 (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
80798 
80799 #define SEMC_SDRAMCR2_ITO_MASK                   (0xFF000000U)
80800 #define SEMC_SDRAMCR2_ITO_SHIFT                  (24U)
80801 /*! ITO - SDRAM idle timeout
80802  *  0b00000000..IDLE timeout period is 256*Prescale period.
80803  *  0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period.
80804  */
80805 #define SEMC_SDRAMCR2_ITO(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
80806 /*! @} */
80807 
80808 /*! @name SDRAMCR3 - SDRAM Control Register 3 */
80809 /*! @{ */
80810 
80811 #define SEMC_SDRAMCR3_REN_MASK                   (0x1U)
80812 #define SEMC_SDRAMCR3_REN_SHIFT                  (0U)
80813 /*! REN - Refresh enable
80814  *  0b0..The SEMC does not send AUTO REFRESH command automatically
80815  *  0b1..The SEMC sends AUTO REFRESH command automatically
80816  */
80817 #define SEMC_SDRAMCR3_REN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
80818 
80819 #define SEMC_SDRAMCR3_REBL_MASK                  (0xEU)
80820 #define SEMC_SDRAMCR3_REBL_SHIFT                 (1U)
80821 /*! REBL - Refresh burst length
80822  *  0b000..1
80823  *  0b001..2
80824  *  0b010..3
80825  *  0b011..4
80826  *  0b100..5
80827  *  0b101..6
80828  *  0b110..7
80829  *  0b111..8
80830  */
80831 #define SEMC_SDRAMCR3_REBL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
80832 
80833 #define SEMC_SDRAMCR3_PRESCALE_MASK              (0xFF00U)
80834 #define SEMC_SDRAMCR3_PRESCALE_SHIFT             (8U)
80835 /*! PRESCALE - Prescaler period
80836  *  0b00000000..(256*16+1) clock cycles
80837  *  0b00000001-0b11111111..(PRESCALE*16+1) clock cycles
80838  */
80839 #define SEMC_SDRAMCR3_PRESCALE(x)                (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
80840 
80841 #define SEMC_SDRAMCR3_RT_MASK                    (0xFF0000U)
80842 #define SEMC_SDRAMCR3_RT_SHIFT                   (16U)
80843 /*! RT - Refresh timer period
80844  *  0b00000000..(256+1)*(Prescaler period)
80845  *  0b00000001-0b11111111..(RT+1)*(Prescaler period)
80846  */
80847 #define SEMC_SDRAMCR3_RT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
80848 
80849 #define SEMC_SDRAMCR3_UT_MASK                    (0xFF000000U)
80850 #define SEMC_SDRAMCR3_UT_SHIFT                   (24U)
80851 /*! UT - Urgent refresh threshold
80852  *  0b00000000..256*(Prescaler period)
80853  *  0b00000001-0b11111111..UT*(Prescaler period)
80854  */
80855 #define SEMC_SDRAMCR3_UT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
80856 /*! @} */
80857 
80858 /*! @name NANDCR0 - NAND Control Register 0 */
80859 /*! @{ */
80860 
80861 #define SEMC_NANDCR0_PS_MASK                     (0x1U)
80862 #define SEMC_NANDCR0_PS_SHIFT                    (0U)
80863 /*! PS - Port Size
80864  *  0b0..8bit
80865  *  0b1..16bit
80866  */
80867 #define SEMC_NANDCR0_PS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
80868 
80869 #define SEMC_NANDCR0_SYNCEN_MASK                 (0x2U)
80870 #define SEMC_NANDCR0_SYNCEN_SHIFT                (1U)
80871 /*! SYNCEN - Synchronous Mode Enable
80872  *  0b0..Asynchronous mode is enabled.
80873  *  0b1..Synchronous mode is enabled.
80874  */
80875 #define SEMC_NANDCR0_SYNCEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK)
80876 
80877 #define SEMC_NANDCR0_BL_MASK                     (0x70U)
80878 #define SEMC_NANDCR0_BL_SHIFT                    (4U)
80879 /*! BL - Burst Length
80880  *  0b000..1
80881  *  0b001..2
80882  *  0b010..4
80883  *  0b011..8
80884  *  0b100..16
80885  *  0b101..32
80886  *  0b110..64
80887  *  0b111..64
80888  */
80889 #define SEMC_NANDCR0_BL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
80890 
80891 #define SEMC_NANDCR0_EDO_MASK                    (0x80U)
80892 #define SEMC_NANDCR0_EDO_SHIFT                   (7U)
80893 /*! EDO - EDO mode enabled
80894  *  0b0..EDO mode disabled
80895  *  0b1..EDO mode enabled
80896  */
80897 #define SEMC_NANDCR0_EDO(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
80898 
80899 #define SEMC_NANDCR0_COL_MASK                    (0x700U)
80900 #define SEMC_NANDCR0_COL_SHIFT                   (8U)
80901 /*! COL - Column address bit number
80902  *  0b000..16
80903  *  0b001..15
80904  *  0b010..14
80905  *  0b011..13
80906  *  0b100..12
80907  *  0b101..11
80908  *  0b110..10
80909  *  0b111..9
80910  */
80911 #define SEMC_NANDCR0_COL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
80912 /*! @} */
80913 
80914 /*! @name NANDCR1 - NAND Control Register 1 */
80915 /*! @{ */
80916 
80917 #define SEMC_NANDCR1_CES_MASK                    (0xFU)
80918 #define SEMC_NANDCR1_CES_SHIFT                   (0U)
80919 /*! CES - CE# setup time */
80920 #define SEMC_NANDCR1_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
80921 
80922 #define SEMC_NANDCR1_CEH_MASK                    (0xF0U)
80923 #define SEMC_NANDCR1_CEH_SHIFT                   (4U)
80924 /*! CEH - CE# hold time */
80925 #define SEMC_NANDCR1_CEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
80926 
80927 #define SEMC_NANDCR1_WEL_MASK                    (0xF00U)
80928 #define SEMC_NANDCR1_WEL_SHIFT                   (8U)
80929 /*! WEL - WE# low time */
80930 #define SEMC_NANDCR1_WEL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
80931 
80932 #define SEMC_NANDCR1_WEH_MASK                    (0xF000U)
80933 #define SEMC_NANDCR1_WEH_SHIFT                   (12U)
80934 /*! WEH - WE# high time */
80935 #define SEMC_NANDCR1_WEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
80936 
80937 #define SEMC_NANDCR1_REL_MASK                    (0xF0000U)
80938 #define SEMC_NANDCR1_REL_SHIFT                   (16U)
80939 /*! REL - RE# low time */
80940 #define SEMC_NANDCR1_REL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
80941 
80942 #define SEMC_NANDCR1_REH_MASK                    (0xF00000U)
80943 #define SEMC_NANDCR1_REH_SHIFT                   (20U)
80944 /*! REH - RE# high time */
80945 #define SEMC_NANDCR1_REH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
80946 
80947 #define SEMC_NANDCR1_TA_MASK                     (0xF000000U)
80948 #define SEMC_NANDCR1_TA_SHIFT                    (24U)
80949 /*! TA - Turnaround time */
80950 #define SEMC_NANDCR1_TA(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
80951 
80952 #define SEMC_NANDCR1_CEITV_MASK                  (0xF0000000U)
80953 #define SEMC_NANDCR1_CEITV_SHIFT                 (28U)
80954 /*! CEITV - CE# interval time */
80955 #define SEMC_NANDCR1_CEITV(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)
80956 /*! @} */
80957 
80958 /*! @name NANDCR2 - NAND Control Register 2 */
80959 /*! @{ */
80960 
80961 #define SEMC_NANDCR2_TWHR_MASK                   (0x3FU)
80962 #define SEMC_NANDCR2_TWHR_SHIFT                  (0U)
80963 /*! TWHR - WE# high to RE# low time */
80964 #define SEMC_NANDCR2_TWHR(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
80965 
80966 #define SEMC_NANDCR2_TRHW_MASK                   (0xFC0U)
80967 #define SEMC_NANDCR2_TRHW_SHIFT                  (6U)
80968 /*! TRHW - RE# high to WE# low time */
80969 #define SEMC_NANDCR2_TRHW(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
80970 
80971 #define SEMC_NANDCR2_TADL_MASK                   (0x3F000U)
80972 #define SEMC_NANDCR2_TADL_SHIFT                  (12U)
80973 /*! TADL - Address cycle to data loading time */
80974 #define SEMC_NANDCR2_TADL(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
80975 
80976 #define SEMC_NANDCR2_TRR_MASK                    (0xFC0000U)
80977 #define SEMC_NANDCR2_TRR_SHIFT                   (18U)
80978 /*! TRR - Ready to RE# low time */
80979 #define SEMC_NANDCR2_TRR(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
80980 
80981 #define SEMC_NANDCR2_TWB_MASK                    (0x3F000000U)
80982 #define SEMC_NANDCR2_TWB_SHIFT                   (24U)
80983 /*! TWB - WE# high to busy time */
80984 #define SEMC_NANDCR2_TWB(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)
80985 /*! @} */
80986 
80987 /*! @name NANDCR3 - NAND Control Register 3 */
80988 /*! @{ */
80989 
80990 #define SEMC_NANDCR3_NDOPT1_MASK                 (0x1U)
80991 #define SEMC_NANDCR3_NDOPT1_SHIFT                (0U)
80992 /*! NDOPT1 - NAND option bit 1 */
80993 #define SEMC_NANDCR3_NDOPT1(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
80994 
80995 #define SEMC_NANDCR3_NDOPT2_MASK                 (0x2U)
80996 #define SEMC_NANDCR3_NDOPT2_SHIFT                (1U)
80997 /*! NDOPT2 - NAND option bit 2 */
80998 #define SEMC_NANDCR3_NDOPT2(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
80999 
81000 #define SEMC_NANDCR3_NDOPT3_MASK                 (0x4U)
81001 #define SEMC_NANDCR3_NDOPT3_SHIFT                (2U)
81002 /*! NDOPT3 - NAND option bit 3 */
81003 #define SEMC_NANDCR3_NDOPT3(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
81004 
81005 #define SEMC_NANDCR3_CLE_MASK                    (0x8U)
81006 #define SEMC_NANDCR3_CLE_SHIFT                   (3U)
81007 /*! CLE - NAND CLE Option */
81008 #define SEMC_NANDCR3_CLE(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK)
81009 
81010 #define SEMC_NANDCR3_RDS_MASK                    (0xF0000U)
81011 #define SEMC_NANDCR3_RDS_SHIFT                   (16U)
81012 /*! RDS - Read Data Setup time */
81013 #define SEMC_NANDCR3_RDS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK)
81014 
81015 #define SEMC_NANDCR3_RDH_MASK                    (0xF00000U)
81016 #define SEMC_NANDCR3_RDH_SHIFT                   (20U)
81017 /*! RDH - Read Data Hold time */
81018 #define SEMC_NANDCR3_RDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK)
81019 
81020 #define SEMC_NANDCR3_WDS_MASK                    (0xF000000U)
81021 #define SEMC_NANDCR3_WDS_SHIFT                   (24U)
81022 /*! WDS - Write Data Setup time */
81023 #define SEMC_NANDCR3_WDS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK)
81024 
81025 #define SEMC_NANDCR3_WDH_MASK                    (0xF0000000U)
81026 #define SEMC_NANDCR3_WDH_SHIFT                   (28U)
81027 /*! WDH - Write Data Hold time */
81028 #define SEMC_NANDCR3_WDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK)
81029 /*! @} */
81030 
81031 /*! @name NORCR0 - NOR Control Register 0 */
81032 /*! @{ */
81033 
81034 #define SEMC_NORCR0_PS_MASK                      (0x1U)
81035 #define SEMC_NORCR0_PS_SHIFT                     (0U)
81036 /*! PS - Port Size
81037  *  0b0..8bit
81038  *  0b1..16bit
81039  */
81040 #define SEMC_NORCR0_PS(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
81041 
81042 #define SEMC_NORCR0_SYNCEN_MASK                  (0x2U)
81043 #define SEMC_NORCR0_SYNCEN_SHIFT                 (1U)
81044 /*! SYNCEN - Synchronous Mode Enable
81045  *  0b0..Asynchronous mode is enabled.
81046  *  0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
81047  */
81048 #define SEMC_NORCR0_SYNCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK)
81049 
81050 #define SEMC_NORCR0_BL_MASK                      (0x70U)
81051 #define SEMC_NORCR0_BL_SHIFT                     (4U)
81052 /*! BL - Burst Length
81053  *  0b000..1
81054  *  0b001..2
81055  *  0b010..4
81056  *  0b011..8
81057  *  0b100..16
81058  *  0b101..32
81059  *  0b110..64
81060  *  0b111..64
81061  */
81062 #define SEMC_NORCR0_BL(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
81063 
81064 #define SEMC_NORCR0_AM_MASK                      (0x300U)
81065 #define SEMC_NORCR0_AM_SHIFT                     (8U)
81066 /*! AM - Address Mode
81067  *  0b00..Address/Data MUX mode (ADMUX)
81068  *  0b01..Advanced Address/Data MUX mode (AADM)
81069  *  0b10..Address/Data non-MUX mode (Non-ADMUX)
81070  *  0b11..Address/Data non-MUX mode (Non-ADMUX)
81071  */
81072 #define SEMC_NORCR0_AM(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
81073 
81074 #define SEMC_NORCR0_ADVP_MASK                    (0x400U)
81075 #define SEMC_NORCR0_ADVP_SHIFT                   (10U)
81076 /*! ADVP - ADV# Polarity
81077  *  0b0..ADV# is active low.
81078  *  0b1..ADV# is active high.
81079  */
81080 #define SEMC_NORCR0_ADVP(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
81081 
81082 #define SEMC_NORCR0_ADVH_MASK                    (0x800U)
81083 #define SEMC_NORCR0_ADVH_SHIFT                   (11U)
81084 /*! ADVH - ADV# level control during address hold state
81085  *  0b0..ADV# is high during address hold state.
81086  *  0b1..ADV# is low during address hold state.
81087  */
81088 #define SEMC_NORCR0_ADVH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK)
81089 
81090 #define SEMC_NORCR0_COL_MASK                     (0xF000U)
81091 #define SEMC_NORCR0_COL_SHIFT                    (12U)
81092 /*! COL - Column Address bit width
81093  *  0b0000..12 Bits
81094  *  0b0001..11 Bits
81095  *  0b0010..10 Bits
81096  *  0b0011..9 Bits
81097  *  0b0100..8 Bits
81098  *  0b0101..7 Bits
81099  *  0b0110..6 Bits
81100  *  0b0111..5 Bits
81101  *  0b1000..4 Bits
81102  *  0b1001..3 Bits
81103  *  0b1010..2 Bits
81104  *  0b1011..12 Bits
81105  *  0b1100..12 Bits
81106  *  0b1101..12 Bits
81107  *  0b1110..12 Bits
81108  *  0b1111..12 Bits
81109  */
81110 #define SEMC_NORCR0_COL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
81111 /*! @} */
81112 
81113 /*! @name NORCR1 - NOR Control Register 1 */
81114 /*! @{ */
81115 
81116 #define SEMC_NORCR1_CES_MASK                     (0xFU)
81117 #define SEMC_NORCR1_CES_SHIFT                    (0U)
81118 /*! CES - CE setup time */
81119 #define SEMC_NORCR1_CES(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
81120 
81121 #define SEMC_NORCR1_CEH_MASK                     (0xF0U)
81122 #define SEMC_NORCR1_CEH_SHIFT                    (4U)
81123 /*! CEH - CE hold time */
81124 #define SEMC_NORCR1_CEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
81125 
81126 #define SEMC_NORCR1_AS_MASK                      (0xF00U)
81127 #define SEMC_NORCR1_AS_SHIFT                     (8U)
81128 /*! AS - Address setup time */
81129 #define SEMC_NORCR1_AS(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
81130 
81131 #define SEMC_NORCR1_AH_MASK                      (0xF000U)
81132 #define SEMC_NORCR1_AH_SHIFT                     (12U)
81133 /*! AH - Address hold time */
81134 #define SEMC_NORCR1_AH(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
81135 
81136 #define SEMC_NORCR1_WEL_MASK                     (0xF0000U)
81137 #define SEMC_NORCR1_WEL_SHIFT                    (16U)
81138 /*! WEL - WE low time */
81139 #define SEMC_NORCR1_WEL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
81140 
81141 #define SEMC_NORCR1_WEH_MASK                     (0xF00000U)
81142 #define SEMC_NORCR1_WEH_SHIFT                    (20U)
81143 /*! WEH - WE high time */
81144 #define SEMC_NORCR1_WEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
81145 
81146 #define SEMC_NORCR1_REL_MASK                     (0xF000000U)
81147 #define SEMC_NORCR1_REL_SHIFT                    (24U)
81148 /*! REL - RE low time */
81149 #define SEMC_NORCR1_REL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
81150 
81151 #define SEMC_NORCR1_REH_MASK                     (0xF0000000U)
81152 #define SEMC_NORCR1_REH_SHIFT                    (28U)
81153 /*! REH - RE high time */
81154 #define SEMC_NORCR1_REH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)
81155 /*! @} */
81156 
81157 /*! @name NORCR2 - NOR Control Register 2 */
81158 /*! @{ */
81159 
81160 #define SEMC_NORCR2_TA_MASK                      (0xF00U)
81161 #define SEMC_NORCR2_TA_SHIFT                     (8U)
81162 /*! TA - Turnaround time */
81163 #define SEMC_NORCR2_TA(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
81164 
81165 #define SEMC_NORCR2_AWDH_MASK                    (0xF000U)
81166 #define SEMC_NORCR2_AWDH_SHIFT                   (12U)
81167 /*! AWDH - Address to write data hold time */
81168 #define SEMC_NORCR2_AWDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
81169 
81170 #define SEMC_NORCR2_LC_MASK                      (0xF0000U)
81171 #define SEMC_NORCR2_LC_SHIFT                     (16U)
81172 /*! LC - Latency count */
81173 #define SEMC_NORCR2_LC(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)
81174 
81175 #define SEMC_NORCR2_RD_MASK                      (0xF00000U)
81176 #define SEMC_NORCR2_RD_SHIFT                     (20U)
81177 /*! RD - Read time */
81178 #define SEMC_NORCR2_RD(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)
81179 
81180 #define SEMC_NORCR2_CEITV_MASK                   (0xF000000U)
81181 #define SEMC_NORCR2_CEITV_SHIFT                  (24U)
81182 /*! CEITV - CE# interval time */
81183 #define SEMC_NORCR2_CEITV(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
81184 
81185 #define SEMC_NORCR2_RDH_MASK                     (0xF0000000U)
81186 #define SEMC_NORCR2_RDH_SHIFT                    (28U)
81187 /*! RDH - Read hold time */
81188 #define SEMC_NORCR2_RDH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
81189 /*! @} */
81190 
81191 /*! @name NORCR3 - NOR Control Register 3 */
81192 /*! @{ */
81193 
81194 #define SEMC_NORCR3_ASSR_MASK                    (0xFU)
81195 #define SEMC_NORCR3_ASSR_SHIFT                   (0U)
81196 /*! ASSR - Address setup time for SYNC read */
81197 #define SEMC_NORCR3_ASSR(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK)
81198 
81199 #define SEMC_NORCR3_AHSR_MASK                    (0xF0U)
81200 #define SEMC_NORCR3_AHSR_SHIFT                   (4U)
81201 /*! AHSR - Address hold time for SYNC read */
81202 #define SEMC_NORCR3_AHSR(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK)
81203 /*! @} */
81204 
81205 /*! @name SRAMCR0 - SRAM Control Register 0 */
81206 /*! @{ */
81207 
81208 #define SEMC_SRAMCR0_PS_MASK                     (0x1U)
81209 #define SEMC_SRAMCR0_PS_SHIFT                    (0U)
81210 /*! PS - Port Size
81211  *  0b0..8bit
81212  *  0b1..16bit
81213  */
81214 #define SEMC_SRAMCR0_PS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
81215 
81216 #define SEMC_SRAMCR0_SYNCEN_MASK                 (0x2U)
81217 #define SEMC_SRAMCR0_SYNCEN_SHIFT                (1U)
81218 /*! SYNCEN - Synchronous Mode Enable
81219  *  0b0..Asynchronous mode is enabled.
81220  *  0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
81221  */
81222 #define SEMC_SRAMCR0_SYNCEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK)
81223 
81224 #define SEMC_SRAMCR0_WAITEN_MASK                 (0x4U)
81225 #define SEMC_SRAMCR0_WAITEN_SHIFT                (2U)
81226 /*! WAITEN - Wait Enable
81227  *  0b0..The SEMC does not monitor wait pin.
81228  *  0b1..The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted.
81229  */
81230 #define SEMC_SRAMCR0_WAITEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITEN_SHIFT)) & SEMC_SRAMCR0_WAITEN_MASK)
81231 
81232 #define SEMC_SRAMCR0_WAITSP_MASK                 (0x8U)
81233 #define SEMC_SRAMCR0_WAITSP_SHIFT                (3U)
81234 /*! WAITSP - Wait Sample
81235  *  0b0..Wait pin is directly used by the SEMC.
81236  *  0b1..Wait pin is sampled by internal clock before it is used.
81237  */
81238 #define SEMC_SRAMCR0_WAITSP(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITSP_SHIFT)) & SEMC_SRAMCR0_WAITSP_MASK)
81239 
81240 #define SEMC_SRAMCR0_BL_MASK                     (0x70U)
81241 #define SEMC_SRAMCR0_BL_SHIFT                    (4U)
81242 /*! BL - Burst Length
81243  *  0b000..1
81244  *  0b001..2
81245  *  0b010..4
81246  *  0b011..8
81247  *  0b100..16
81248  *  0b101..32
81249  *  0b110..64
81250  *  0b111..64
81251  */
81252 #define SEMC_SRAMCR0_BL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
81253 
81254 #define SEMC_SRAMCR0_AM_MASK                     (0x300U)
81255 #define SEMC_SRAMCR0_AM_SHIFT                    (8U)
81256 /*! AM - Address Mode
81257  *  0b00..Address/Data MUX mode (ADMUX)
81258  *  0b01..Advanced Address/Data MUX mode (AADM)
81259  *  0b10..Address/Data non-MUX mode (Non-ADMUX)
81260  *  0b11..Address/Data non-MUX mode (Non-ADMUX)
81261  */
81262 #define SEMC_SRAMCR0_AM(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
81263 
81264 #define SEMC_SRAMCR0_ADVP_MASK                   (0x400U)
81265 #define SEMC_SRAMCR0_ADVP_SHIFT                  (10U)
81266 /*! ADVP - ADV# polarity
81267  *  0b0..ADV# is active low.
81268  *  0b1..ADV# is active high.
81269  */
81270 #define SEMC_SRAMCR0_ADVP(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
81271 
81272 #define SEMC_SRAMCR0_ADVH_MASK                   (0x800U)
81273 #define SEMC_SRAMCR0_ADVH_SHIFT                  (11U)
81274 /*! ADVH - ADV# level control during address hold state
81275  *  0b0..ADV# is high during address hold state.
81276  *  0b1..ADV# is low during address hold state.
81277  */
81278 #define SEMC_SRAMCR0_ADVH(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK)
81279 
81280 #define SEMC_SRAMCR0_COL_MASK                    (0xF000U)
81281 #define SEMC_SRAMCR0_COL_SHIFT                   (12U)
81282 /*! COL - Column Address bit width
81283  *  0b0000..12 Bits
81284  *  0b0001..11 Bits
81285  *  0b0010..10 Bits
81286  *  0b0011..9 Bits
81287  *  0b0100..8 Bits
81288  *  0b0101..7 Bits
81289  *  0b0110..6 Bits
81290  *  0b0111..5 Bits
81291  *  0b1000..4 Bits
81292  *  0b1001..3 Bits
81293  *  0b1010..2 Bits
81294  *  0b1011..12 Bits
81295  *  0b1100..12 Bits
81296  *  0b1101..12 Bits
81297  *  0b1110..12 Bits
81298  *  0b1111..12 Bits
81299  */
81300 #define SEMC_SRAMCR0_COL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
81301 /*! @} */
81302 
81303 /*! @name SRAMCR1 - SRAM Control Register 1 */
81304 /*! @{ */
81305 
81306 #define SEMC_SRAMCR1_CES_MASK                    (0xFU)
81307 #define SEMC_SRAMCR1_CES_SHIFT                   (0U)
81308 /*! CES - CE setup time */
81309 #define SEMC_SRAMCR1_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
81310 
81311 #define SEMC_SRAMCR1_CEH_MASK                    (0xF0U)
81312 #define SEMC_SRAMCR1_CEH_SHIFT                   (4U)
81313 /*! CEH - CE hold time */
81314 #define SEMC_SRAMCR1_CEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
81315 
81316 #define SEMC_SRAMCR1_AS_MASK                     (0xF00U)
81317 #define SEMC_SRAMCR1_AS_SHIFT                    (8U)
81318 /*! AS - Address setup time */
81319 #define SEMC_SRAMCR1_AS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
81320 
81321 #define SEMC_SRAMCR1_AH_MASK                     (0xF000U)
81322 #define SEMC_SRAMCR1_AH_SHIFT                    (12U)
81323 /*! AH - Address hold time */
81324 #define SEMC_SRAMCR1_AH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
81325 
81326 #define SEMC_SRAMCR1_WEL_MASK                    (0xF0000U)
81327 #define SEMC_SRAMCR1_WEL_SHIFT                   (16U)
81328 /*! WEL - WE low time */
81329 #define SEMC_SRAMCR1_WEL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
81330 
81331 #define SEMC_SRAMCR1_WEH_MASK                    (0xF00000U)
81332 #define SEMC_SRAMCR1_WEH_SHIFT                   (20U)
81333 /*! WEH - WE high time */
81334 #define SEMC_SRAMCR1_WEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
81335 
81336 #define SEMC_SRAMCR1_REL_MASK                    (0xF000000U)
81337 #define SEMC_SRAMCR1_REL_SHIFT                   (24U)
81338 /*! REL - RE low time */
81339 #define SEMC_SRAMCR1_REL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
81340 
81341 #define SEMC_SRAMCR1_REH_MASK                    (0xF0000000U)
81342 #define SEMC_SRAMCR1_REH_SHIFT                   (28U)
81343 /*! REH - RE high time */
81344 #define SEMC_SRAMCR1_REH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)
81345 /*! @} */
81346 
81347 /*! @name SRAMCR2 - SRAM Control Register 2 */
81348 /*! @{ */
81349 
81350 #define SEMC_SRAMCR2_WDS_MASK                    (0xFU)
81351 #define SEMC_SRAMCR2_WDS_SHIFT                   (0U)
81352 /*! WDS - Write Data setup time */
81353 #define SEMC_SRAMCR2_WDS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)
81354 
81355 #define SEMC_SRAMCR2_WDH_MASK                    (0xF0U)
81356 #define SEMC_SRAMCR2_WDH_SHIFT                   (4U)
81357 /*! WDH - Write Data hold time */
81358 #define SEMC_SRAMCR2_WDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)
81359 
81360 #define SEMC_SRAMCR2_TA_MASK                     (0xF00U)
81361 #define SEMC_SRAMCR2_TA_SHIFT                    (8U)
81362 /*! TA - Turnaround time */
81363 #define SEMC_SRAMCR2_TA(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
81364 
81365 #define SEMC_SRAMCR2_AWDH_MASK                   (0xF000U)
81366 #define SEMC_SRAMCR2_AWDH_SHIFT                  (12U)
81367 /*! AWDH - Address to write data hold time */
81368 #define SEMC_SRAMCR2_AWDH(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
81369 
81370 #define SEMC_SRAMCR2_LC_MASK                     (0xF0000U)
81371 #define SEMC_SRAMCR2_LC_SHIFT                    (16U)
81372 /*! LC - Latency count */
81373 #define SEMC_SRAMCR2_LC(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)
81374 
81375 #define SEMC_SRAMCR2_RD_MASK                     (0xF00000U)
81376 #define SEMC_SRAMCR2_RD_SHIFT                    (20U)
81377 /*! RD - Read time */
81378 #define SEMC_SRAMCR2_RD(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)
81379 
81380 #define SEMC_SRAMCR2_CEITV_MASK                  (0xF000000U)
81381 #define SEMC_SRAMCR2_CEITV_SHIFT                 (24U)
81382 /*! CEITV - CE# interval time */
81383 #define SEMC_SRAMCR2_CEITV(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
81384 
81385 #define SEMC_SRAMCR2_RDH_MASK                    (0xF0000000U)
81386 #define SEMC_SRAMCR2_RDH_SHIFT                   (28U)
81387 /*! RDH - Read hold time */
81388 #define SEMC_SRAMCR2_RDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK)
81389 /*! @} */
81390 
81391 /*! @name DBICR0 - DBI-B Control Register 0 */
81392 /*! @{ */
81393 
81394 #define SEMC_DBICR0_PS_MASK                      (0x1U)
81395 #define SEMC_DBICR0_PS_SHIFT                     (0U)
81396 /*! PS - Port Size
81397  *  0b0..8bit
81398  *  0b1..16bit
81399  */
81400 #define SEMC_DBICR0_PS(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
81401 
81402 #define SEMC_DBICR0_BL_MASK                      (0x70U)
81403 #define SEMC_DBICR0_BL_SHIFT                     (4U)
81404 /*! BL - Burst Length
81405  *  0b000..1
81406  *  0b001..2
81407  *  0b010..4
81408  *  0b011..8
81409  *  0b100..16
81410  *  0b101..32
81411  *  0b110..64
81412  *  0b111..64
81413  */
81414 #define SEMC_DBICR0_BL(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
81415 
81416 #define SEMC_DBICR0_COL_MASK                     (0xF000U)
81417 #define SEMC_DBICR0_COL_SHIFT                    (12U)
81418 /*! COL - Column Address bit width
81419  *  0b0000..12 Bits
81420  *  0b0001..11 Bits
81421  *  0b0010..10 Bits
81422  *  0b0011..9 Bits
81423  *  0b0100..8 Bits
81424  *  0b0101..7 Bits
81425  *  0b0110..6 Bits
81426  *  0b0111..5 Bits
81427  *  0b1000..4 Bits
81428  *  0b1001..3 Bits
81429  *  0b1010..2 Bits
81430  *  0b1011..12 Bits
81431  *  0b1100..12 Bits
81432  *  0b1101..12 Bits
81433  *  0b1110..12 Bits
81434  *  0b1111..12 Bits
81435  */
81436 #define SEMC_DBICR0_COL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
81437 /*! @} */
81438 
81439 /*! @name DBICR1 - DBI-B Control Register 1 */
81440 /*! @{ */
81441 
81442 #define SEMC_DBICR1_CES_MASK                     (0xFU)
81443 #define SEMC_DBICR1_CES_SHIFT                    (0U)
81444 /*! CES - CSX Setup Time */
81445 #define SEMC_DBICR1_CES(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
81446 
81447 #define SEMC_DBICR1_CEH_MASK                     (0xF0U)
81448 #define SEMC_DBICR1_CEH_SHIFT                    (4U)
81449 /*! CEH - CSX Hold Time */
81450 #define SEMC_DBICR1_CEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
81451 
81452 #define SEMC_DBICR1_WEL_MASK                     (0xF00U)
81453 #define SEMC_DBICR1_WEL_SHIFT                    (8U)
81454 /*! WEL - WRX Low Time */
81455 #define SEMC_DBICR1_WEL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
81456 
81457 #define SEMC_DBICR1_WEH_MASK                     (0xF000U)
81458 #define SEMC_DBICR1_WEH_SHIFT                    (12U)
81459 /*! WEH - WRX High Time */
81460 #define SEMC_DBICR1_WEH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
81461 
81462 #define SEMC_DBICR1_REL_MASK                     (0x7F0000U)
81463 #define SEMC_DBICR1_REL_SHIFT                    (16U)
81464 /*! REL - RDX Low Time */
81465 #define SEMC_DBICR1_REL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
81466 
81467 #define SEMC_DBICR1_REH_MASK                     (0x7F000000U)
81468 #define SEMC_DBICR1_REH_SHIFT                    (24U)
81469 /*! REH - RDX High Time */
81470 #define SEMC_DBICR1_REH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
81471 /*! @} */
81472 
81473 /*! @name DBICR2 - DBI-B Control Register 2 */
81474 /*! @{ */
81475 
81476 #define SEMC_DBICR2_CEITV_MASK                   (0xFU)
81477 #define SEMC_DBICR2_CEITV_SHIFT                  (0U)
81478 /*! CEITV - CSX interval time */
81479 #define SEMC_DBICR2_CEITV(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR2_CEITV_SHIFT)) & SEMC_DBICR2_CEITV_MASK)
81480 /*! @} */
81481 
81482 /*! @name IPCR0 - IP Command Control Register 0 */
81483 /*! @{ */
81484 
81485 #define SEMC_IPCR0_SA_MASK                       (0xFFFFFFFFU)
81486 #define SEMC_IPCR0_SA_SHIFT                      (0U)
81487 /*! SA - Slave address */
81488 #define SEMC_IPCR0_SA(x)                         (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)
81489 /*! @} */
81490 
81491 /*! @name IPCR1 - IP Command Control Register 1 */
81492 /*! @{ */
81493 
81494 #define SEMC_IPCR1_DATSZ_MASK                    (0x7U)
81495 #define SEMC_IPCR1_DATSZ_SHIFT                   (0U)
81496 /*! DATSZ - Data Size in Byte
81497  *  0b000..4
81498  *  0b001..1
81499  *  0b010..2
81500  *  0b011..3
81501  *  0b100..4
81502  *  0b101..4
81503  *  0b110..4
81504  *  0b111..4
81505  */
81506 #define SEMC_IPCR1_DATSZ(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
81507 
81508 #define SEMC_IPCR1_NAND_EXT_ADDR_MASK            (0xFF00U)
81509 #define SEMC_IPCR1_NAND_EXT_ADDR_SHIFT           (8U)
81510 /*! NAND_EXT_ADDR - NAND Extended Address */
81511 #define SEMC_IPCR1_NAND_EXT_ADDR(x)              (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK)
81512 /*! @} */
81513 
81514 /*! @name IPCR2 - IP Command Control Register 2 */
81515 /*! @{ */
81516 
81517 #define SEMC_IPCR2_BM0_MASK                      (0x1U)
81518 #define SEMC_IPCR2_BM0_SHIFT                     (0U)
81519 /*! BM0 - Byte Mask for Byte 0 (IPTXDAT bit 7:0)
81520  *  0b0..Byte is unmasked
81521  *  0b1..Byte is masked
81522  */
81523 #define SEMC_IPCR2_BM0(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
81524 
81525 #define SEMC_IPCR2_BM1_MASK                      (0x2U)
81526 #define SEMC_IPCR2_BM1_SHIFT                     (1U)
81527 /*! BM1 - Byte Mask for Byte 1 (IPTXDAT bit 15:8)
81528  *  0b0..Byte is unmasked
81529  *  0b1..Byte is masked
81530  */
81531 #define SEMC_IPCR2_BM1(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
81532 
81533 #define SEMC_IPCR2_BM2_MASK                      (0x4U)
81534 #define SEMC_IPCR2_BM2_SHIFT                     (2U)
81535 /*! BM2 - Byte Mask for Byte 2 (IPTXDAT bit 23:16)
81536  *  0b0..Byte is unmasked
81537  *  0b1..Byte is masked
81538  */
81539 #define SEMC_IPCR2_BM2(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
81540 
81541 #define SEMC_IPCR2_BM3_MASK                      (0x8U)
81542 #define SEMC_IPCR2_BM3_SHIFT                     (3U)
81543 /*! BM3 - Byte Mask for Byte 3 (IPTXDAT bit 31:24)
81544  *  0b0..Byte is unmasked
81545  *  0b1..Byte is masked
81546  */
81547 #define SEMC_IPCR2_BM3(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
81548 /*! @} */
81549 
81550 /*! @name IPCMD - IP Command Register */
81551 /*! @{ */
81552 
81553 #define SEMC_IPCMD_CMD_MASK                      (0xFFFFU)
81554 #define SEMC_IPCMD_CMD_SHIFT                     (0U)
81555 #define SEMC_IPCMD_CMD(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
81556 
81557 #define SEMC_IPCMD_KEY_MASK                      (0xFFFF0000U)
81558 #define SEMC_IPCMD_KEY_SHIFT                     (16U)
81559 #define SEMC_IPCMD_KEY(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
81560 /*! @} */
81561 
81562 /*! @name IPTXDAT - TX DATA Register */
81563 /*! @{ */
81564 
81565 #define SEMC_IPTXDAT_DAT_MASK                    (0xFFFFFFFFU)
81566 #define SEMC_IPTXDAT_DAT_SHIFT                   (0U)
81567 #define SEMC_IPTXDAT_DAT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)
81568 /*! @} */
81569 
81570 /*! @name IPRXDAT - RX DATA Register */
81571 /*! @{ */
81572 
81573 #define SEMC_IPRXDAT_DAT_MASK                    (0xFFFFFFFFU)
81574 #define SEMC_IPRXDAT_DAT_SHIFT                   (0U)
81575 #define SEMC_IPRXDAT_DAT(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)
81576 /*! @} */
81577 
81578 /*! @name STS0 - Status Register 0 */
81579 /*! @{ */
81580 
81581 #define SEMC_STS0_IDLE_MASK                      (0x1U)
81582 #define SEMC_STS0_IDLE_SHIFT                     (0U)
81583 /*! IDLE - Indicating whether the SEMC is in idle state. */
81584 #define SEMC_STS0_IDLE(x)                        (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
81585 
81586 #define SEMC_STS0_NARDY_MASK                     (0x2U)
81587 #define SEMC_STS0_NARDY_SHIFT                    (1U)
81588 /*! NARDY - Indicating NAND device Ready/WAIT# pin level.
81589  *  0b0..NAND device is not ready
81590  *  0b1..NAND device is ready
81591  */
81592 #define SEMC_STS0_NARDY(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
81593 /*! @} */
81594 
81595 /*! @name STS2 - Status Register 2 */
81596 /*! @{ */
81597 
81598 #define SEMC_STS2_NDWRPEND_MASK                  (0x8U)
81599 #define SEMC_STS2_NDWRPEND_SHIFT                 (3U)
81600 /*! NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device.
81601  *  0b0..No pending
81602  *  0b1..Pending
81603  */
81604 #define SEMC_STS2_NDWRPEND(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
81605 /*! @} */
81606 
81607 /*! @name STS12 - Status Register 12 */
81608 /*! @{ */
81609 
81610 #define SEMC_STS12_NDADDR_MASK                   (0xFFFFFFFFU)
81611 #define SEMC_STS12_NDADDR_SHIFT                  (0U)
81612 /*! NDADDR - This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4). */
81613 #define SEMC_STS12_NDADDR(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)
81614 /*! @} */
81615 
81616 /*! @name STS13 - Status Register 13 */
81617 /*! @{ */
81618 
81619 #define SEMC_STS13_SLVLOCK_MASK                  (0x1U)
81620 #define SEMC_STS13_SLVLOCK_SHIFT                 (0U)
81621 /*! SLVLOCK - Sample clock slave delay line locked.
81622  *  0b0..Slave delay line is not locked.
81623  *  0b1..Slave delay line is locked.
81624  */
81625 #define SEMC_STS13_SLVLOCK(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK)
81626 
81627 #define SEMC_STS13_REFLOCK_MASK                  (0x2U)
81628 #define SEMC_STS13_REFLOCK_SHIFT                 (1U)
81629 /*! REFLOCK - Sample clock reference delay line locked.
81630  *  0b0..Reference delay line is not locked.
81631  *  0b1..Reference delay line is locked.
81632  */
81633 #define SEMC_STS13_REFLOCK(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK)
81634 
81635 #define SEMC_STS13_SLVSEL_MASK                   (0xFCU)
81636 #define SEMC_STS13_SLVSEL_SHIFT                  (2U)
81637 /*! SLVSEL - Sample clock slave delay line delay cell number selection. */
81638 #define SEMC_STS13_SLVSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK)
81639 
81640 #define SEMC_STS13_REFSEL_MASK                   (0x3F00U)
81641 #define SEMC_STS13_REFSEL_SHIFT                  (8U)
81642 /*! REFSEL - Sample clock reference delay line delay cell number selection. */
81643 #define SEMC_STS13_REFSEL(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK)
81644 /*! @} */
81645 
81646 /*! @name BR9 - Base Register 9 */
81647 /*! @{ */
81648 
81649 #define SEMC_BR9_VLD_MASK                        (0x1U)
81650 #define SEMC_BR9_VLD_SHIFT                       (0U)
81651 /*! VLD - Valid
81652  *  0b0..The memory is invalid, can not be accessed.
81653  *  0b1..The memory is valid, can be accessed.
81654  */
81655 #define SEMC_BR9_VLD(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_VLD_SHIFT)) & SEMC_BR9_VLD_MASK)
81656 
81657 #define SEMC_BR9_MS_MASK                         (0x3EU)
81658 #define SEMC_BR9_MS_SHIFT                        (1U)
81659 /*! MS - Memory size
81660  *  0b00000..4KB
81661  *  0b00001..8KB
81662  *  0b00010..16KB
81663  *  0b00011..32KB
81664  *  0b00100..64KB
81665  *  0b00101..128KB
81666  *  0b00110..256KB
81667  *  0b00111..512KB
81668  *  0b01000..1MB
81669  *  0b01001..2MB
81670  *  0b01010..4MB
81671  *  0b01011..8MB
81672  *  0b01100..16MB
81673  *  0b01101..32MB
81674  *  0b01110..64MB
81675  *  0b01111..128MB
81676  *  0b10000..256MB
81677  *  0b10001..512MB
81678  *  0b10010..1GB
81679  *  0b10011..2GB
81680  *  0b10100-0b11111..4GB
81681  */
81682 #define SEMC_BR9_MS(x)                           (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_MS_SHIFT)) & SEMC_BR9_MS_MASK)
81683 
81684 #define SEMC_BR9_BA_MASK                         (0xFFFFF000U)
81685 #define SEMC_BR9_BA_SHIFT                        (12U)
81686 /*! BA - Base Address */
81687 #define SEMC_BR9_BA(x)                           (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_BA_SHIFT)) & SEMC_BR9_BA_MASK)
81688 /*! @} */
81689 
81690 /*! @name BR10 - Base Register 10 */
81691 /*! @{ */
81692 
81693 #define SEMC_BR10_VLD_MASK                       (0x1U)
81694 #define SEMC_BR10_VLD_SHIFT                      (0U)
81695 /*! VLD - Valid
81696  *  0b0..The memory is invalid, can not be accessed.
81697  *  0b1..The memory is valid, can be accessed.
81698  */
81699 #define SEMC_BR10_VLD(x)                         (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_VLD_SHIFT)) & SEMC_BR10_VLD_MASK)
81700 
81701 #define SEMC_BR10_MS_MASK                        (0x3EU)
81702 #define SEMC_BR10_MS_SHIFT                       (1U)
81703 /*! MS - Memory size
81704  *  0b00000..4KB
81705  *  0b00001..8KB
81706  *  0b00010..16KB
81707  *  0b00011..32KB
81708  *  0b00100..64KB
81709  *  0b00101..128KB
81710  *  0b00110..256KB
81711  *  0b00111..512KB
81712  *  0b01000..1MB
81713  *  0b01001..2MB
81714  *  0b01010..4MB
81715  *  0b01011..8MB
81716  *  0b01100..16MB
81717  *  0b01101..32MB
81718  *  0b01110..64MB
81719  *  0b01111..128MB
81720  *  0b10000..256MB
81721  *  0b10001..512MB
81722  *  0b10010..1GB
81723  *  0b10011..2GB
81724  *  0b10100-0b11111..4GB
81725  */
81726 #define SEMC_BR10_MS(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_MS_SHIFT)) & SEMC_BR10_MS_MASK)
81727 
81728 #define SEMC_BR10_BA_MASK                        (0xFFFFF000U)
81729 #define SEMC_BR10_BA_SHIFT                       (12U)
81730 /*! BA - Base Address */
81731 #define SEMC_BR10_BA(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_BA_SHIFT)) & SEMC_BR10_BA_MASK)
81732 /*! @} */
81733 
81734 /*! @name BR11 - Base Register 11 */
81735 /*! @{ */
81736 
81737 #define SEMC_BR11_VLD_MASK                       (0x1U)
81738 #define SEMC_BR11_VLD_SHIFT                      (0U)
81739 /*! VLD - Valid
81740  *  0b0..The memory is invalid, can not be accessed.
81741  *  0b1..The memory is valid, can be accessed.
81742  */
81743 #define SEMC_BR11_VLD(x)                         (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_VLD_SHIFT)) & SEMC_BR11_VLD_MASK)
81744 
81745 #define SEMC_BR11_MS_MASK                        (0x3EU)
81746 #define SEMC_BR11_MS_SHIFT                       (1U)
81747 /*! MS - Memory size
81748  *  0b00000..4KB
81749  *  0b00001..8KB
81750  *  0b00010..16KB
81751  *  0b00011..32KB
81752  *  0b00100..64KB
81753  *  0b00101..128KB
81754  *  0b00110..256KB
81755  *  0b00111..512KB
81756  *  0b01000..1MB
81757  *  0b01001..2MB
81758  *  0b01010..4MB
81759  *  0b01011..8MB
81760  *  0b01100..16MB
81761  *  0b01101..32MB
81762  *  0b01110..64MB
81763  *  0b01111..128MB
81764  *  0b10000..256MB
81765  *  0b10001..512MB
81766  *  0b10010..1GB
81767  *  0b10011..2GB
81768  *  0b10100-0b11111..4GB
81769  */
81770 #define SEMC_BR11_MS(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_MS_SHIFT)) & SEMC_BR11_MS_MASK)
81771 
81772 #define SEMC_BR11_BA_MASK                        (0xFFFFF000U)
81773 #define SEMC_BR11_BA_SHIFT                       (12U)
81774 /*! BA - Base Address */
81775 #define SEMC_BR11_BA(x)                          (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_BA_SHIFT)) & SEMC_BR11_BA_MASK)
81776 /*! @} */
81777 
81778 /*! @name SRAMCR4 - SRAM Control Register 4 */
81779 /*! @{ */
81780 
81781 #define SEMC_SRAMCR4_PS_MASK                     (0x1U)
81782 #define SEMC_SRAMCR4_PS_SHIFT                    (0U)
81783 /*! PS - Port Size
81784  *  0b0..8bit
81785  *  0b1..16bit
81786  */
81787 #define SEMC_SRAMCR4_PS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_PS_SHIFT)) & SEMC_SRAMCR4_PS_MASK)
81788 
81789 #define SEMC_SRAMCR4_SYNCEN_MASK                 (0x2U)
81790 #define SEMC_SRAMCR4_SYNCEN_SHIFT                (1U)
81791 /*! SYNCEN - Synchronous Mode Enable
81792  *  0b0..Asynchronous mode is enabled.
81793  *  0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
81794  */
81795 #define SEMC_SRAMCR4_SYNCEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_SYNCEN_SHIFT)) & SEMC_SRAMCR4_SYNCEN_MASK)
81796 
81797 #define SEMC_SRAMCR4_WAITEN_MASK                 (0x4U)
81798 #define SEMC_SRAMCR4_WAITEN_SHIFT                (2U)
81799 /*! WAITEN - Wait Enable
81800  *  0b0..The SEMC does not monitor wait pin.
81801  *  0b1..The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted.
81802  */
81803 #define SEMC_SRAMCR4_WAITEN(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITEN_SHIFT)) & SEMC_SRAMCR4_WAITEN_MASK)
81804 
81805 #define SEMC_SRAMCR4_WAITSP_MASK                 (0x8U)
81806 #define SEMC_SRAMCR4_WAITSP_SHIFT                (3U)
81807 /*! WAITSP - Wait Sample
81808  *  0b0..Wait pin is directly used by the SEMC.
81809  *  0b1..Wait pin is sampled by internal clock before it is used.
81810  */
81811 #define SEMC_SRAMCR4_WAITSP(x)                   (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITSP_SHIFT)) & SEMC_SRAMCR4_WAITSP_MASK)
81812 
81813 #define SEMC_SRAMCR4_BL_MASK                     (0x70U)
81814 #define SEMC_SRAMCR4_BL_SHIFT                    (4U)
81815 /*! BL - Burst Length
81816  *  0b000..1
81817  *  0b001..2
81818  *  0b010..4
81819  *  0b011..8
81820  *  0b100..16
81821  *  0b101..32
81822  *  0b110..64
81823  *  0b111..64
81824  */
81825 #define SEMC_SRAMCR4_BL(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
81826 
81827 #define SEMC_SRAMCR4_AM_MASK                     (0x300U)
81828 #define SEMC_SRAMCR4_AM_SHIFT                    (8U)
81829 /*! AM - Address Mode
81830  *  0b00..Address/Data MUX mode (ADMUX)
81831  *  0b01..Advanced Address/Data MUX mode (AADM)
81832  *  0b10..Address/Data non-MUX mode (Non-ADMUX)
81833  *  0b11..Address/Data non-MUX mode (Non-ADMUX)
81834  */
81835 #define SEMC_SRAMCR4_AM(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_AM_SHIFT)) & SEMC_SRAMCR4_AM_MASK)
81836 
81837 #define SEMC_SRAMCR4_ADVP_MASK                   (0x400U)
81838 #define SEMC_SRAMCR4_ADVP_SHIFT                  (10U)
81839 /*! ADVP - ADV# polarity
81840  *  0b0..ADV# is active low.
81841  *  0b1..ADV# is active high.
81842  */
81843 #define SEMC_SRAMCR4_ADVP(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVP_SHIFT)) & SEMC_SRAMCR4_ADVP_MASK)
81844 
81845 #define SEMC_SRAMCR4_ADVH_MASK                   (0x800U)
81846 #define SEMC_SRAMCR4_ADVH_SHIFT                  (11U)
81847 /*! ADVH - ADV# level control during address hold state
81848  *  0b0..ADV# is high during address hold state.
81849  *  0b1..ADV# is low during address hold state.
81850  */
81851 #define SEMC_SRAMCR4_ADVH(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVH_SHIFT)) & SEMC_SRAMCR4_ADVH_MASK)
81852 
81853 #define SEMC_SRAMCR4_COL_MASK                    (0xF000U)
81854 #define SEMC_SRAMCR4_COL_SHIFT                   (12U)
81855 /*! COL - Column Address bit width
81856  *  0b0000..12 Bits
81857  *  0b0001..11 Bits
81858  *  0b0010..10 Bits
81859  *  0b0011..9 Bits
81860  *  0b0100..8 Bits
81861  *  0b0101..7 Bits
81862  *  0b0110..6 Bits
81863  *  0b0111..5 Bits
81864  *  0b1000..4 Bits
81865  *  0b1001..3 Bits
81866  *  0b1010..2 Bits
81867  *  0b1011..12 Bits
81868  *  0b1100..12 Bits
81869  *  0b1101..12 Bits
81870  *  0b1110..12 Bits
81871  *  0b1111..12 Bits
81872  */
81873 #define SEMC_SRAMCR4_COL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_COL_SHIFT)) & SEMC_SRAMCR4_COL_MASK)
81874 /*! @} */
81875 
81876 /*! @name SRAMCR5 - SRAM Control Register 5 */
81877 /*! @{ */
81878 
81879 #define SEMC_SRAMCR5_CES_MASK                    (0xFU)
81880 #define SEMC_SRAMCR5_CES_SHIFT                   (0U)
81881 /*! CES - CE setup time */
81882 #define SEMC_SRAMCR5_CES(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CES_SHIFT)) & SEMC_SRAMCR5_CES_MASK)
81883 
81884 #define SEMC_SRAMCR5_CEH_MASK                    (0xF0U)
81885 #define SEMC_SRAMCR5_CEH_SHIFT                   (4U)
81886 /*! CEH - CE hold time */
81887 #define SEMC_SRAMCR5_CEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_SRAMCR5_CEH_MASK)
81888 
81889 #define SEMC_SRAMCR5_AS_MASK                     (0xF00U)
81890 #define SEMC_SRAMCR5_AS_SHIFT                    (8U)
81891 /*! AS - Address setup time */
81892 #define SEMC_SRAMCR5_AS(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AS_SHIFT)) & SEMC_SRAMCR5_AS_MASK)
81893 
81894 #define SEMC_SRAMCR5_AH_MASK                     (0xF000U)
81895 #define SEMC_SRAMCR5_AH_SHIFT                    (12U)
81896 /*! AH - Address hold time */
81897 #define SEMC_SRAMCR5_AH(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AH_SHIFT)) & SEMC_SRAMCR5_AH_MASK)
81898 
81899 #define SEMC_SRAMCR5_WEL_MASK                    (0xF0000U)
81900 #define SEMC_SRAMCR5_WEL_SHIFT                   (16U)
81901 /*! WEL - WE low time */
81902 #define SEMC_SRAMCR5_WEL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEL_SHIFT)) & SEMC_SRAMCR5_WEL_MASK)
81903 
81904 #define SEMC_SRAMCR5_WEH_MASK                    (0xF00000U)
81905 #define SEMC_SRAMCR5_WEH_SHIFT                   (20U)
81906 /*! WEH - WE high time */
81907 #define SEMC_SRAMCR5_WEH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEH_SHIFT)) & SEMC_SRAMCR5_WEH_MASK)
81908 
81909 #define SEMC_SRAMCR5_REL_MASK                    (0xF000000U)
81910 #define SEMC_SRAMCR5_REL_SHIFT                   (24U)
81911 /*! REL - RE low time */
81912 #define SEMC_SRAMCR5_REL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REL_SHIFT)) & SEMC_SRAMCR5_REL_MASK)
81913 
81914 #define SEMC_SRAMCR5_REH_MASK                    (0xF0000000U)
81915 #define SEMC_SRAMCR5_REH_SHIFT                   (28U)
81916 /*! REH - RE high time */
81917 #define SEMC_SRAMCR5_REH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REH_SHIFT)) & SEMC_SRAMCR5_REH_MASK)
81918 /*! @} */
81919 
81920 /*! @name SRAMCR6 - SRAM Control Register 6 */
81921 /*! @{ */
81922 
81923 #define SEMC_SRAMCR6_WDS_MASK                    (0xFU)
81924 #define SEMC_SRAMCR6_WDS_SHIFT                   (0U)
81925 /*! WDS - Write Data setup time */
81926 #define SEMC_SRAMCR6_WDS(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDS_SHIFT)) & SEMC_SRAMCR6_WDS_MASK)
81927 
81928 #define SEMC_SRAMCR6_WDH_MASK                    (0xF0U)
81929 #define SEMC_SRAMCR6_WDH_SHIFT                   (4U)
81930 /*! WDH - Write Data hold time */
81931 #define SEMC_SRAMCR6_WDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDH_SHIFT)) & SEMC_SRAMCR6_WDH_MASK)
81932 
81933 #define SEMC_SRAMCR6_TA_MASK                     (0xF00U)
81934 #define SEMC_SRAMCR6_TA_SHIFT                    (8U)
81935 /*! TA - Turnaround time */
81936 #define SEMC_SRAMCR6_TA(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_TA_SHIFT)) & SEMC_SRAMCR6_TA_MASK)
81937 
81938 #define SEMC_SRAMCR6_AWDH_MASK                   (0xF000U)
81939 #define SEMC_SRAMCR6_AWDH_SHIFT                  (12U)
81940 /*! AWDH - Address to write data hold time */
81941 #define SEMC_SRAMCR6_AWDH(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_AWDH_SHIFT)) & SEMC_SRAMCR6_AWDH_MASK)
81942 
81943 #define SEMC_SRAMCR6_LC_MASK                     (0xF0000U)
81944 #define SEMC_SRAMCR6_LC_SHIFT                    (16U)
81945 /*! LC - Latency count */
81946 #define SEMC_SRAMCR6_LC(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_LC_SHIFT)) & SEMC_SRAMCR6_LC_MASK)
81947 
81948 #define SEMC_SRAMCR6_RD_MASK                     (0xF00000U)
81949 #define SEMC_SRAMCR6_RD_SHIFT                    (20U)
81950 /*! RD - Read time */
81951 #define SEMC_SRAMCR6_RD(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RD_SHIFT)) & SEMC_SRAMCR6_RD_MASK)
81952 
81953 #define SEMC_SRAMCR6_CEITV_MASK                  (0xF000000U)
81954 #define SEMC_SRAMCR6_CEITV_SHIFT                 (24U)
81955 /*! CEITV - CE# interval time */
81956 #define SEMC_SRAMCR6_CEITV(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_CEITV_SHIFT)) & SEMC_SRAMCR6_CEITV_MASK)
81957 
81958 #define SEMC_SRAMCR6_RDH_MASK                    (0xF0000000U)
81959 #define SEMC_SRAMCR6_RDH_SHIFT                   (28U)
81960 /*! RDH - Read hold time */
81961 #define SEMC_SRAMCR6_RDH(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RDH_SHIFT)) & SEMC_SRAMCR6_RDH_MASK)
81962 /*! @} */
81963 
81964 /*! @name DCCR - Delay Chain Control Register */
81965 /*! @{ */
81966 
81967 #define SEMC_DCCR_SDRAMEN_MASK                   (0x1U)
81968 #define SEMC_DCCR_SDRAMEN_SHIFT                  (0U)
81969 /*! SDRAMEN - Delay chain insertion enable for SRAM device.
81970  *  0b0..Delay chain is not inserted.
81971  *  0b1..Delay chain is inserted.
81972  */
81973 #define SEMC_DCCR_SDRAMEN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMEN_SHIFT)) & SEMC_DCCR_SDRAMEN_MASK)
81974 
81975 #define SEMC_DCCR_SDRAMVAL_MASK                  (0x3EU)
81976 #define SEMC_DCCR_SDRAMVAL_SHIFT                 (1U)
81977 /*! SDRAMVAL - Clock delay line delay cell number selection value for SDRAM device. */
81978 #define SEMC_DCCR_SDRAMVAL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMVAL_SHIFT)) & SEMC_DCCR_SDRAMVAL_MASK)
81979 
81980 #define SEMC_DCCR_NOREN_MASK                     (0x100U)
81981 #define SEMC_DCCR_NOREN_SHIFT                    (8U)
81982 /*! NOREN - Delay chain insertion enable for NOR device.
81983  *  0b0..Delay chain is not inserted.
81984  *  0b1..Delay chain is inserted.
81985  */
81986 #define SEMC_DCCR_NOREN(x)                       (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NOREN_SHIFT)) & SEMC_DCCR_NOREN_MASK)
81987 
81988 #define SEMC_DCCR_NORVAL_MASK                    (0x3E00U)
81989 #define SEMC_DCCR_NORVAL_SHIFT                   (9U)
81990 /*! NORVAL - Clock delay line delay cell number selection value for NOR device. */
81991 #define SEMC_DCCR_NORVAL(x)                      (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NORVAL_SHIFT)) & SEMC_DCCR_NORVAL_MASK)
81992 
81993 #define SEMC_DCCR_SRAM0EN_MASK                   (0x10000U)
81994 #define SEMC_DCCR_SRAM0EN_SHIFT                  (16U)
81995 /*! SRAM0EN - Delay chain insertion enable for SRAM device 0.
81996  *  0b0..Delay chain is not inserted.
81997  *  0b1..Delay chain is inserted.
81998  */
81999 #define SEMC_DCCR_SRAM0EN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0EN_SHIFT)) & SEMC_DCCR_SRAM0EN_MASK)
82000 
82001 #define SEMC_DCCR_SRAM0VAL_MASK                  (0x3E0000U)
82002 #define SEMC_DCCR_SRAM0VAL_SHIFT                 (17U)
82003 /*! SRAM0VAL - Clock delay line delay cell number selection value for SRAM device 0. */
82004 #define SEMC_DCCR_SRAM0VAL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0VAL_SHIFT)) & SEMC_DCCR_SRAM0VAL_MASK)
82005 
82006 #define SEMC_DCCR_SRAMXEN_MASK                   (0x1000000U)
82007 #define SEMC_DCCR_SRAMXEN_SHIFT                  (24U)
82008 /*! SRAMXEN - Delay chain insertion enable for SRAM device 1-3.
82009  *  0b0..Delay chain is not inserted.
82010  *  0b1..Delay chain is inserted.
82011  */
82012 #define SEMC_DCCR_SRAMXEN(x)                     (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXEN_SHIFT)) & SEMC_DCCR_SRAMXEN_MASK)
82013 
82014 #define SEMC_DCCR_SRAMXVAL_MASK                  (0x3E000000U)
82015 #define SEMC_DCCR_SRAMXVAL_SHIFT                 (25U)
82016 /*! SRAMXVAL - Clock delay line delay cell number selection value for SRAM device 1-3. */
82017 #define SEMC_DCCR_SRAMXVAL(x)                    (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXVAL_SHIFT)) & SEMC_DCCR_SRAMXVAL_MASK)
82018 /*! @} */
82019 
82020 
82021 /*!
82022  * @}
82023  */ /* end of group SEMC_Register_Masks */
82024 
82025 
82026 /* SEMC - Peripheral instance base addresses */
82027 /** Peripheral SEMC base address */
82028 #define SEMC_BASE                                (0x400D4000u)
82029 /** Peripheral SEMC base pointer */
82030 #define SEMC                                     ((SEMC_Type *)SEMC_BASE)
82031 /** Array initializer of SEMC peripheral base addresses */
82032 #define SEMC_BASE_ADDRS                          { SEMC_BASE }
82033 /** Array initializer of SEMC peripheral base pointers */
82034 #define SEMC_BASE_PTRS                           { SEMC }
82035 /** Interrupt vectors for the SEMC peripheral type */
82036 #define SEMC_IRQS                                { SEMC_IRQn }
82037 
82038 /*!
82039  * @}
82040  */ /* end of group SEMC_Peripheral_Access_Layer */
82041 
82042 
82043 /* ----------------------------------------------------------------------------
82044    -- SNVS Peripheral Access Layer
82045    ---------------------------------------------------------------------------- */
82046 
82047 /*!
82048  * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer
82049  * @{
82050  */
82051 
82052 /** SNVS - Register Layout Typedef */
82053 typedef struct {
82054   __IO uint32_t HPLR;                              /**< SNVS_HP Lock Register, offset: 0x0 */
82055   __IO uint32_t HPCOMR;                            /**< SNVS_HP Command Register, offset: 0x4 */
82056   __IO uint32_t HPCR;                              /**< SNVS_HP Control Register, offset: 0x8 */
82057   __IO uint32_t HPSICR;                            /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */
82058   __IO uint32_t HPSVCR;                            /**< SNVS_HP Security Violation Control Register, offset: 0x10 */
82059   __IO uint32_t HPSR;                              /**< SNVS_HP Status Register, offset: 0x14 */
82060   __IO uint32_t HPSVSR;                            /**< SNVS_HP Security Violation Status Register, offset: 0x18 */
82061   __IO uint32_t HPHACIVR;                          /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */
82062   __I  uint32_t HPHACR;                            /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */
82063   __IO uint32_t HPRTCMR;                           /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */
82064   __IO uint32_t HPRTCLR;                           /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */
82065   __IO uint32_t HPTAMR;                            /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */
82066   __IO uint32_t HPTALR;                            /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */
82067   __IO uint32_t LPLR;                              /**< SNVS_LP Lock Register, offset: 0x34 */
82068   __IO uint32_t LPCR;                              /**< SNVS_LP Control Register, offset: 0x38 */
82069   __IO uint32_t LPMKCR;                            /**< SNVS_LP Master Key Control Register, offset: 0x3C */
82070   __IO uint32_t LPSVCR;                            /**< SNVS_LP Security Violation Control Register, offset: 0x40 */
82071   __IO uint32_t LPTGFCR;                           /**< SNVS_LP Tamper Glitch Filters Configuration Register, offset: 0x44 */
82072   __IO uint32_t LPTDCR;                            /**< SNVS_LP Tamper Detect Configuration Register, offset: 0x48 */
82073   __IO uint32_t LPSR;                              /**< SNVS_LP Status Register, offset: 0x4C */
82074   __IO uint32_t LPSRTCMR;                          /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */
82075   __IO uint32_t LPSRTCLR;                          /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */
82076   __IO uint32_t LPTAR;                             /**< SNVS_LP Time Alarm Register, offset: 0x58 */
82077   __IO uint32_t LPSMCMR;                           /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */
82078   __IO uint32_t LPSMCLR;                           /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */
82079   __IO uint32_t LPLVDR;                            /**< SNVS_LP Digital Low-Voltage Detector Register, offset: 0x64 */
82080   __IO uint32_t LPGPR0_LEGACY_ALIAS;               /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */
82081   __IO uint32_t LPZMKR[8];                         /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */
82082        uint8_t RESERVED_0[4];
82083   __IO uint32_t LPGPR_ALIAS[4];                    /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */
82084   __IO uint32_t LPTDC2R;                           /**< SNVS_LP Tamper Detectors Config 2 Register, offset: 0xA0 */
82085   __IO uint32_t LPTDSR;                            /**< SNVS_LP Tamper Detectors Status Register, offset: 0xA4 */
82086   __IO uint32_t LPTGF1CR;                          /**< SNVS_LP Tamper Glitch Filter 1 Configuration Register, offset: 0xA8 */
82087   __IO uint32_t LPTGF2CR;                          /**< SNVS_LP Tamper Glitch Filter 2 Configuration Register, offset: 0xAC */
82088        uint8_t RESERVED_1[16];
82089   __O  uint32_t LPATCR[5];                         /**< SNVS_LP Active Tamper 1 Configuration Register..SNVS_LP Active Tamper 5 Configuration Register, array offset: 0xC0, array step: 0x4 */
82090        uint8_t RESERVED_2[12];
82091   __IO uint32_t LPATCTLR;                          /**< SNVS_LP Active Tamper Control Register, offset: 0xE0 */
82092   __IO uint32_t LPATCLKR;                          /**< SNVS_LP Active Tamper Clock Control Register, offset: 0xE4 */
82093   __IO uint32_t LPATRC1R;                          /**< SNVS_LP Active Tamper Routing Control 1 Register, offset: 0xE8 */
82094   __IO uint32_t LPATRC2R;                          /**< SNVS_LP Active Tamper Routing Control 2 Register, offset: 0xEC */
82095        uint8_t RESERVED_3[16];
82096   __IO uint32_t LPGPR[4];                          /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4 */
82097        uint8_t RESERVED_4[2792];
82098   __I  uint32_t HPVIDR1;                           /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */
82099   __I  uint32_t HPVIDR2;                           /**< SNVS_HP Version ID Register 2, offset: 0xBFC */
82100 } SNVS_Type;
82101 
82102 /* ----------------------------------------------------------------------------
82103    -- SNVS Register Masks
82104    ---------------------------------------------------------------------------- */
82105 
82106 /*!
82107  * @addtogroup SNVS_Register_Masks SNVS Register Masks
82108  * @{
82109  */
82110 
82111 /*! @name HPLR - SNVS_HP Lock Register */
82112 /*! @{ */
82113 
82114 #define SNVS_HPLR_ZMK_WSL_MASK                   (0x1U)
82115 #define SNVS_HPLR_ZMK_WSL_SHIFT                  (0U)
82116 /*! ZMK_WSL
82117  *  0b0..Write access is allowed
82118  *  0b1..Write access is not allowed
82119  */
82120 #define SNVS_HPLR_ZMK_WSL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
82121 
82122 #define SNVS_HPLR_ZMK_RSL_MASK                   (0x2U)
82123 #define SNVS_HPLR_ZMK_RSL_SHIFT                  (1U)
82124 /*! ZMK_RSL
82125  *  0b0..Read access is allowed (only in software Programming mode)
82126  *  0b1..Read access is not allowed
82127  */
82128 #define SNVS_HPLR_ZMK_RSL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
82129 
82130 #define SNVS_HPLR_SRTC_SL_MASK                   (0x4U)
82131 #define SNVS_HPLR_SRTC_SL_SHIFT                  (2U)
82132 /*! SRTC_SL
82133  *  0b0..Write access is allowed
82134  *  0b1..Write access is not allowed
82135  */
82136 #define SNVS_HPLR_SRTC_SL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
82137 
82138 #define SNVS_HPLR_LPCALB_SL_MASK                 (0x8U)
82139 #define SNVS_HPLR_LPCALB_SL_SHIFT                (3U)
82140 /*! LPCALB_SL
82141  *  0b0..Write access is allowed
82142  *  0b1..Write access is not allowed
82143  */
82144 #define SNVS_HPLR_LPCALB_SL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
82145 
82146 #define SNVS_HPLR_MC_SL_MASK                     (0x10U)
82147 #define SNVS_HPLR_MC_SL_SHIFT                    (4U)
82148 /*! MC_SL
82149  *  0b0..Write access (increment) is allowed
82150  *  0b1..Write access (increment) is not allowed
82151  */
82152 #define SNVS_HPLR_MC_SL(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
82153 
82154 #define SNVS_HPLR_GPR_SL_MASK                    (0x20U)
82155 #define SNVS_HPLR_GPR_SL_SHIFT                   (5U)
82156 /*! GPR_SL
82157  *  0b0..Write access is allowed
82158  *  0b1..Write access is not allowed
82159  */
82160 #define SNVS_HPLR_GPR_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
82161 
82162 #define SNVS_HPLR_LPSVCR_SL_MASK                 (0x40U)
82163 #define SNVS_HPLR_LPSVCR_SL_SHIFT                (6U)
82164 /*! LPSVCR_SL
82165  *  0b0..Write access is allowed
82166  *  0b1..Write access is not allowed
82167  */
82168 #define SNVS_HPLR_LPSVCR_SL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
82169 
82170 #define SNVS_HPLR_LPTGFCR_SL_MASK                (0x80U)
82171 #define SNVS_HPLR_LPTGFCR_SL_SHIFT               (7U)
82172 /*! LPTGFCR_SL
82173  *  0b0..Write access is allowed
82174  *  0b1..Write access is not allowed
82175  */
82176 #define SNVS_HPLR_LPTGFCR_SL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTGFCR_SL_SHIFT)) & SNVS_HPLR_LPTGFCR_SL_MASK)
82177 
82178 #define SNVS_HPLR_LPSECR_SL_MASK                 (0x100U)
82179 #define SNVS_HPLR_LPSECR_SL_SHIFT                (8U)
82180 /*! LPSECR_SL
82181  *  0b0..Write access is allowed
82182  *  0b1..Write access is not allowed
82183  */
82184 #define SNVS_HPLR_LPSECR_SL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK)
82185 
82186 #define SNVS_HPLR_MKS_SL_MASK                    (0x200U)
82187 #define SNVS_HPLR_MKS_SL_SHIFT                   (9U)
82188 /*! MKS_SL
82189  *  0b0..Write access is allowed
82190  *  0b1..Write access is not allowed
82191  */
82192 #define SNVS_HPLR_MKS_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
82193 
82194 #define SNVS_HPLR_HPSVCR_L_MASK                  (0x10000U)
82195 #define SNVS_HPLR_HPSVCR_L_SHIFT                 (16U)
82196 /*! HPSVCR_L
82197  *  0b0..Write access is allowed
82198  *  0b1..Write access is not allowed
82199  */
82200 #define SNVS_HPLR_HPSVCR_L(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
82201 
82202 #define SNVS_HPLR_HPSICR_L_MASK                  (0x20000U)
82203 #define SNVS_HPLR_HPSICR_L_SHIFT                 (17U)
82204 /*! HPSICR_L
82205  *  0b0..Write access is allowed
82206  *  0b1..Write access is not allowed
82207  */
82208 #define SNVS_HPLR_HPSICR_L(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
82209 
82210 #define SNVS_HPLR_HAC_L_MASK                     (0x40000U)
82211 #define SNVS_HPLR_HAC_L_SHIFT                    (18U)
82212 /*! HAC_L
82213  *  0b0..Write access is allowed
82214  *  0b1..Write access is not allowed
82215  */
82216 #define SNVS_HPLR_HAC_L(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
82217 
82218 #define SNVS_HPLR_AT1_SL_MASK                    (0x1000000U)
82219 #define SNVS_HPLR_AT1_SL_SHIFT                   (24U)
82220 /*! AT1_SL
82221  *  0b0..Write access is allowed.
82222  *  0b1..Write access is not allowed.
82223  */
82224 #define SNVS_HPLR_AT1_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT1_SL_SHIFT)) & SNVS_HPLR_AT1_SL_MASK)
82225 
82226 #define SNVS_HPLR_AT2_SL_MASK                    (0x2000000U)
82227 #define SNVS_HPLR_AT2_SL_SHIFT                   (25U)
82228 /*! AT2_SL
82229  *  0b0..Write access is allowed.
82230  *  0b1..Write access is not allowed.
82231  */
82232 #define SNVS_HPLR_AT2_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT2_SL_SHIFT)) & SNVS_HPLR_AT2_SL_MASK)
82233 
82234 #define SNVS_HPLR_AT3_SL_MASK                    (0x4000000U)
82235 #define SNVS_HPLR_AT3_SL_SHIFT                   (26U)
82236 /*! AT3_SL
82237  *  0b0..Write access is allowed.
82238  *  0b1..Write access is not allowed.
82239  */
82240 #define SNVS_HPLR_AT3_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT3_SL_SHIFT)) & SNVS_HPLR_AT3_SL_MASK)
82241 
82242 #define SNVS_HPLR_AT4_SL_MASK                    (0x8000000U)
82243 #define SNVS_HPLR_AT4_SL_SHIFT                   (27U)
82244 /*! AT4_SL
82245  *  0b0..Write access is allowed.
82246  *  0b1..Write access is not allowed.
82247  */
82248 #define SNVS_HPLR_AT4_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT4_SL_SHIFT)) & SNVS_HPLR_AT4_SL_MASK)
82249 
82250 #define SNVS_HPLR_AT5_SL_MASK                    (0x10000000U)
82251 #define SNVS_HPLR_AT5_SL_SHIFT                   (28U)
82252 /*! AT5_SL
82253  *  0b0..Write access is allowed.
82254  *  0b1..Write access is not allowed.
82255  */
82256 #define SNVS_HPLR_AT5_SL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT5_SL_SHIFT)) & SNVS_HPLR_AT5_SL_MASK)
82257 /*! @} */
82258 
82259 /*! @name HPCOMR - SNVS_HP Command Register */
82260 /*! @{ */
82261 
82262 #define SNVS_HPCOMR_SSM_ST_MASK                  (0x1U)
82263 #define SNVS_HPCOMR_SSM_ST_SHIFT                 (0U)
82264 #define SNVS_HPCOMR_SSM_ST(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
82265 
82266 #define SNVS_HPCOMR_SSM_ST_DIS_MASK              (0x2U)
82267 #define SNVS_HPCOMR_SSM_ST_DIS_SHIFT             (1U)
82268 /*! SSM_ST_DIS
82269  *  0b0..Secure to Trusted State transition is enabled
82270  *  0b1..Secure to Trusted State transition is disabled
82271  */
82272 #define SNVS_HPCOMR_SSM_ST_DIS(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
82273 
82274 #define SNVS_HPCOMR_SSM_SFNS_DIS_MASK            (0x4U)
82275 #define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT           (2U)
82276 /*! SSM_SFNS_DIS
82277  *  0b0..Soft Fail to Non-Secure State transition is enabled
82278  *  0b1..Soft Fail to Non-Secure State transition is disabled
82279  */
82280 #define SNVS_HPCOMR_SSM_SFNS_DIS(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
82281 
82282 #define SNVS_HPCOMR_LP_SWR_MASK                  (0x10U)
82283 #define SNVS_HPCOMR_LP_SWR_SHIFT                 (4U)
82284 /*! LP_SWR
82285  *  0b0..No Action
82286  *  0b1..Reset LP section
82287  */
82288 #define SNVS_HPCOMR_LP_SWR(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
82289 
82290 #define SNVS_HPCOMR_LP_SWR_DIS_MASK              (0x20U)
82291 #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT             (5U)
82292 /*! LP_SWR_DIS
82293  *  0b0..LP software reset is enabled
82294  *  0b1..LP software reset is disabled
82295  */
82296 #define SNVS_HPCOMR_LP_SWR_DIS(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
82297 
82298 #define SNVS_HPCOMR_SW_SV_MASK                   (0x100U)
82299 #define SNVS_HPCOMR_SW_SV_SHIFT                  (8U)
82300 #define SNVS_HPCOMR_SW_SV(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
82301 
82302 #define SNVS_HPCOMR_SW_FSV_MASK                  (0x200U)
82303 #define SNVS_HPCOMR_SW_FSV_SHIFT                 (9U)
82304 #define SNVS_HPCOMR_SW_FSV(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
82305 
82306 #define SNVS_HPCOMR_SW_LPSV_MASK                 (0x400U)
82307 #define SNVS_HPCOMR_SW_LPSV_SHIFT                (10U)
82308 #define SNVS_HPCOMR_SW_LPSV(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
82309 
82310 #define SNVS_HPCOMR_PROG_ZMK_MASK                (0x1000U)
82311 #define SNVS_HPCOMR_PROG_ZMK_SHIFT               (12U)
82312 /*! PROG_ZMK
82313  *  0b0..No Action
82314  *  0b1..Activate hardware key programming mechanism
82315  */
82316 #define SNVS_HPCOMR_PROG_ZMK(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
82317 
82318 #define SNVS_HPCOMR_MKS_EN_MASK                  (0x2000U)
82319 #define SNVS_HPCOMR_MKS_EN_SHIFT                 (13U)
82320 /*! MKS_EN
82321  *  0b0..OTP master key is selected as an SNVS master key
82322  *  0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR
82323  */
82324 #define SNVS_HPCOMR_MKS_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
82325 
82326 #define SNVS_HPCOMR_HAC_EN_MASK                  (0x10000U)
82327 #define SNVS_HPCOMR_HAC_EN_SHIFT                 (16U)
82328 /*! HAC_EN
82329  *  0b0..High Assurance Counter is disabled
82330  *  0b1..High Assurance Counter is enabled
82331  */
82332 #define SNVS_HPCOMR_HAC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
82333 
82334 #define SNVS_HPCOMR_HAC_LOAD_MASK                (0x20000U)
82335 #define SNVS_HPCOMR_HAC_LOAD_SHIFT               (17U)
82336 /*! HAC_LOAD
82337  *  0b0..No Action
82338  *  0b1..Load the HAC
82339  */
82340 #define SNVS_HPCOMR_HAC_LOAD(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
82341 
82342 #define SNVS_HPCOMR_HAC_CLEAR_MASK               (0x40000U)
82343 #define SNVS_HPCOMR_HAC_CLEAR_SHIFT              (18U)
82344 /*! HAC_CLEAR
82345  *  0b0..No Action
82346  *  0b1..Clear the HAC
82347  */
82348 #define SNVS_HPCOMR_HAC_CLEAR(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
82349 
82350 #define SNVS_HPCOMR_HAC_STOP_MASK                (0x80000U)
82351 #define SNVS_HPCOMR_HAC_STOP_SHIFT               (19U)
82352 #define SNVS_HPCOMR_HAC_STOP(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
82353 
82354 #define SNVS_HPCOMR_NPSWA_EN_MASK                (0x80000000U)
82355 #define SNVS_HPCOMR_NPSWA_EN_SHIFT               (31U)
82356 #define SNVS_HPCOMR_NPSWA_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
82357 /*! @} */
82358 
82359 /*! @name HPCR - SNVS_HP Control Register */
82360 /*! @{ */
82361 
82362 #define SNVS_HPCR_RTC_EN_MASK                    (0x1U)
82363 #define SNVS_HPCR_RTC_EN_SHIFT                   (0U)
82364 /*! RTC_EN
82365  *  0b0..RTC is disabled
82366  *  0b1..RTC is enabled
82367  */
82368 #define SNVS_HPCR_RTC_EN(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
82369 
82370 #define SNVS_HPCR_HPTA_EN_MASK                   (0x2U)
82371 #define SNVS_HPCR_HPTA_EN_SHIFT                  (1U)
82372 /*! HPTA_EN
82373  *  0b0..HP Time Alarm Interrupt is disabled
82374  *  0b1..HP Time Alarm Interrupt is enabled
82375  */
82376 #define SNVS_HPCR_HPTA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
82377 
82378 #define SNVS_HPCR_DIS_PI_MASK                    (0x4U)
82379 #define SNVS_HPCR_DIS_PI_SHIFT                   (2U)
82380 /*! DIS_PI
82381  *  0b0..Periodic interrupt will trigger a functional interrupt
82382  *  0b1..Disable periodic interrupt in the function interrupt
82383  */
82384 #define SNVS_HPCR_DIS_PI(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
82385 
82386 #define SNVS_HPCR_PI_EN_MASK                     (0x8U)
82387 #define SNVS_HPCR_PI_EN_SHIFT                    (3U)
82388 /*! PI_EN
82389  *  0b0..HP Periodic Interrupt is disabled
82390  *  0b1..HP Periodic Interrupt is enabled
82391  */
82392 #define SNVS_HPCR_PI_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
82393 
82394 #define SNVS_HPCR_PI_FREQ_MASK                   (0xF0U)
82395 #define SNVS_HPCR_PI_FREQ_SHIFT                  (4U)
82396 /*! PI_FREQ
82397  *  0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt
82398  *  0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt
82399  *  0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt
82400  *  0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt
82401  *  0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt
82402  *  0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt
82403  *  0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt
82404  *  0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt
82405  *  0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt
82406  *  0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt
82407  *  0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt
82408  *  0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt
82409  *  0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt
82410  *  0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt
82411  *  0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt
82412  *  0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt
82413  */
82414 #define SNVS_HPCR_PI_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
82415 
82416 #define SNVS_HPCR_HPCALB_EN_MASK                 (0x100U)
82417 #define SNVS_HPCR_HPCALB_EN_SHIFT                (8U)
82418 /*! HPCALB_EN
82419  *  0b0..HP Timer calibration disabled
82420  *  0b1..HP Timer calibration enabled
82421  */
82422 #define SNVS_HPCR_HPCALB_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
82423 
82424 #define SNVS_HPCR_HPCALB_VAL_MASK                (0x7C00U)
82425 #define SNVS_HPCR_HPCALB_VAL_SHIFT               (10U)
82426 /*! HPCALB_VAL
82427  *  0b00000..+0 counts per each 32768 ticks of the counter
82428  *  0b00001..+1 counts per each 32768 ticks of the counter
82429  *  0b00010..+2 counts per each 32768 ticks of the counter
82430  *  0b01111..+15 counts per each 32768 ticks of the counter
82431  *  0b10000..-16 counts per each 32768 ticks of the counter
82432  *  0b10001..-15 counts per each 32768 ticks of the counter
82433  *  0b11110..-2 counts per each 32768 ticks of the counter
82434  *  0b11111..-1 counts per each 32768 ticks of the counter
82435  */
82436 #define SNVS_HPCR_HPCALB_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
82437 
82438 #define SNVS_HPCR_HP_TS_MASK                     (0x10000U)
82439 #define SNVS_HPCR_HP_TS_SHIFT                    (16U)
82440 /*! HP_TS
82441  *  0b0..No Action
82442  *  0b1..Synchronize the HP Time Counter to the LP Time Counter
82443  */
82444 #define SNVS_HPCR_HP_TS(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
82445 
82446 #define SNVS_HPCR_BTN_CONFIG_MASK                (0x7000000U)
82447 #define SNVS_HPCR_BTN_CONFIG_SHIFT               (24U)
82448 #define SNVS_HPCR_BTN_CONFIG(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
82449 
82450 #define SNVS_HPCR_BTN_MASK_MASK                  (0x8000000U)
82451 #define SNVS_HPCR_BTN_MASK_SHIFT                 (27U)
82452 #define SNVS_HPCR_BTN_MASK(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
82453 /*! @} */
82454 
82455 /*! @name HPSICR - SNVS_HP Security Interrupt Control Register */
82456 /*! @{ */
82457 
82458 #define SNVS_HPSICR_CAAM_EN_MASK                 (0x1U)
82459 #define SNVS_HPSICR_CAAM_EN_SHIFT                (0U)
82460 /*! CAAM_EN
82461  *  0b0..CAAM Security Violation Interrupt is Disabled
82462  *  0b1..CAAM Security Violation Interrupt is Enabled
82463  */
82464 #define SNVS_HPSICR_CAAM_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_CAAM_EN_SHIFT)) & SNVS_HPSICR_CAAM_EN_MASK)
82465 
82466 #define SNVS_HPSICR_JTAGC_EN_MASK                (0x2U)
82467 #define SNVS_HPSICR_JTAGC_EN_SHIFT               (1U)
82468 /*! JTAGC_EN
82469  *  0b0..JTAG Active Interrupt is Disabled
82470  *  0b1..JTAG Active Interrupt is Enabled
82471  */
82472 #define SNVS_HPSICR_JTAGC_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_JTAGC_EN_SHIFT)) & SNVS_HPSICR_JTAGC_EN_MASK)
82473 
82474 #define SNVS_HPSICR_WDOG2_EN_MASK                (0x4U)
82475 #define SNVS_HPSICR_WDOG2_EN_SHIFT               (2U)
82476 /*! WDOG2_EN
82477  *  0b0..Watchdog 2 Reset Interrupt is Disabled
82478  *  0b1..Watchdog 2 Reset Interrupt is Enabled
82479  */
82480 #define SNVS_HPSICR_WDOG2_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_WDOG2_EN_SHIFT)) & SNVS_HPSICR_WDOG2_EN_MASK)
82481 
82482 #define SNVS_HPSICR_SRC_EN_MASK                  (0x10U)
82483 #define SNVS_HPSICR_SRC_EN_SHIFT                 (4U)
82484 /*! SRC_EN
82485  *  0b0..Internal Boot Interrupt is Disabled
82486  *  0b1..Internal Boot Interrupt is Enabled
82487  */
82488 #define SNVS_HPSICR_SRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SRC_EN_SHIFT)) & SNVS_HPSICR_SRC_EN_MASK)
82489 
82490 #define SNVS_HPSICR_OCOTP_EN_MASK                (0x20U)
82491 #define SNVS_HPSICR_OCOTP_EN_SHIFT               (5U)
82492 /*! OCOTP_EN
82493  *  0b0..OCOTP attack error Interrupt is Disabled
82494  *  0b1..OCOTP attack error Interrupt is Enabled
82495  */
82496 #define SNVS_HPSICR_OCOTP_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_OCOTP_EN_SHIFT)) & SNVS_HPSICR_OCOTP_EN_MASK)
82497 
82498 #define SNVS_HPSICR_LPSVI_EN_MASK                (0x80000000U)
82499 #define SNVS_HPSICR_LPSVI_EN_SHIFT               (31U)
82500 /*! LPSVI_EN
82501  *  0b0..LP Security Violation Interrupt is Disabled
82502  *  0b1..LP Security Violation Interrupt is Enabled
82503  */
82504 #define SNVS_HPSICR_LPSVI_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
82505 /*! @} */
82506 
82507 /*! @name HPSVCR - SNVS_HP Security Violation Control Register */
82508 /*! @{ */
82509 
82510 #define SNVS_HPSVCR_CAAM_CFG_MASK                (0x1U)
82511 #define SNVS_HPSVCR_CAAM_CFG_SHIFT               (0U)
82512 /*! CAAM_CFG
82513  *  0b0..CAAM Security Violation is a non-fatal violation
82514  *  0b1..CAAM Security Violation is a fatal violation
82515  */
82516 #define SNVS_HPSVCR_CAAM_CFG(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_CAAM_CFG_SHIFT)) & SNVS_HPSVCR_CAAM_CFG_MASK)
82517 
82518 #define SNVS_HPSVCR_JTAGC_CFG_MASK               (0x2U)
82519 #define SNVS_HPSVCR_JTAGC_CFG_SHIFT              (1U)
82520 /*! JTAGC_CFG
82521  *  0b0..JTAG Active is a non-fatal violation
82522  *  0b1..JTAG Active is a fatal violation
82523  */
82524 #define SNVS_HPSVCR_JTAGC_CFG(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_JTAGC_CFG_SHIFT)) & SNVS_HPSVCR_JTAGC_CFG_MASK)
82525 
82526 #define SNVS_HPSVCR_WDOG2_CFG_MASK               (0x4U)
82527 #define SNVS_HPSVCR_WDOG2_CFG_SHIFT              (2U)
82528 /*! WDOG2_CFG
82529  *  0b0..Watchdog 2 Reset is a non-fatal violation
82530  *  0b1..Watchdog 2 Reset is a fatal violation
82531  */
82532 #define SNVS_HPSVCR_WDOG2_CFG(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
82533 
82534 #define SNVS_HPSVCR_SRC_CFG_MASK                 (0x10U)
82535 #define SNVS_HPSVCR_SRC_CFG_SHIFT                (4U)
82536 /*! SRC_CFG
82537  *  0b0..Internal Boot is a non-fatal violation
82538  *  0b1..Internal Boot is a fatal violation
82539  */
82540 #define SNVS_HPSVCR_SRC_CFG(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SRC_CFG_SHIFT)) & SNVS_HPSVCR_SRC_CFG_MASK)
82541 
82542 #define SNVS_HPSVCR_OCOTP_CFG_MASK               (0x60U)
82543 #define SNVS_HPSVCR_OCOTP_CFG_SHIFT              (5U)
82544 /*! OCOTP_CFG
82545  *  0b00..OCOTP attack error is disabled
82546  *  0b01..OCOTP attack error is a non-fatal violation
82547  *  0b1x..OCOTP attack error is a fatal violation
82548  */
82549 #define SNVS_HPSVCR_OCOTP_CFG(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_OCOTP_CFG_SHIFT)) & SNVS_HPSVCR_OCOTP_CFG_MASK)
82550 
82551 #define SNVS_HPSVCR_LPSV_CFG_MASK                (0xC0000000U)
82552 #define SNVS_HPSVCR_LPSV_CFG_SHIFT               (30U)
82553 /*! LPSV_CFG
82554  *  0b00..LP security violation is disabled
82555  *  0b01..LP security violation is a non-fatal violation
82556  *  0b1x..LP security violation is a fatal violation
82557  */
82558 #define SNVS_HPSVCR_LPSV_CFG(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
82559 /*! @} */
82560 
82561 /*! @name HPSR - SNVS_HP Status Register */
82562 /*! @{ */
82563 
82564 #define SNVS_HPSR_HPTA_MASK                      (0x1U)
82565 #define SNVS_HPSR_HPTA_SHIFT                     (0U)
82566 /*! HPTA
82567  *  0b0..No time alarm interrupt occurred.
82568  *  0b1..A time alarm interrupt occurred.
82569  */
82570 #define SNVS_HPSR_HPTA(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
82571 
82572 #define SNVS_HPSR_PI_MASK                        (0x2U)
82573 #define SNVS_HPSR_PI_SHIFT                       (1U)
82574 /*! PI
82575  *  0b0..No periodic interrupt occurred.
82576  *  0b1..A periodic interrupt occurred.
82577  */
82578 #define SNVS_HPSR_PI(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
82579 
82580 #define SNVS_HPSR_LPDIS_MASK                     (0x10U)
82581 #define SNVS_HPSR_LPDIS_SHIFT                    (4U)
82582 #define SNVS_HPSR_LPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
82583 
82584 #define SNVS_HPSR_BTN_MASK                       (0x40U)
82585 #define SNVS_HPSR_BTN_SHIFT                      (6U)
82586 #define SNVS_HPSR_BTN(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
82587 
82588 #define SNVS_HPSR_BI_MASK                        (0x80U)
82589 #define SNVS_HPSR_BI_SHIFT                       (7U)
82590 #define SNVS_HPSR_BI(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
82591 
82592 #define SNVS_HPSR_SSM_STATE_MASK                 (0xF00U)
82593 #define SNVS_HPSR_SSM_STATE_SHIFT                (8U)
82594 /*! SSM_STATE
82595  *  0b0000..Init
82596  *  0b0001..Hard Fail
82597  *  0b0011..Soft Fail
82598  *  0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle)
82599  *  0b1001..Check
82600  *  0b1011..Non-Secure
82601  *  0b1101..Trusted
82602  *  0b1111..Secure
82603  */
82604 #define SNVS_HPSR_SSM_STATE(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
82605 
82606 #define SNVS_HPSR_SYS_SECURITY_CFG_MASK          (0x7000U)
82607 #define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT         (12U)
82608 /*! SYS_SECURITY_CFG
82609  *  0b000..Fab Configuration - the default configuration of newly fabricated chips
82610  *  0b001..Open Configuration - the configuration after NXP-programmable fuses have been blown
82611  *  0b011..Closed Configuration - the configuration after OEM-programmable fuses have been blown
82612  *  0b111..Field Return Configuration - the configuration of chips that are returned to NXP for analysis
82613  */
82614 #define SNVS_HPSR_SYS_SECURITY_CFG(x)            (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)
82615 
82616 #define SNVS_HPSR_SYS_SECURE_BOOT_MASK           (0x8000U)
82617 #define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT          (15U)
82618 #define SNVS_HPSR_SYS_SECURE_BOOT(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK)
82619 
82620 #define SNVS_HPSR_OTPMK_ZERO_MASK                (0x8000000U)
82621 #define SNVS_HPSR_OTPMK_ZERO_SHIFT               (27U)
82622 /*! OTPMK_ZERO
82623  *  0b0..The OTPMK is not zero.
82624  *  0b1..The OTPMK is zero.
82625  */
82626 #define SNVS_HPSR_OTPMK_ZERO(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
82627 
82628 #define SNVS_HPSR_ZMK_ZERO_MASK                  (0x80000000U)
82629 #define SNVS_HPSR_ZMK_ZERO_SHIFT                 (31U)
82630 /*! ZMK_ZERO
82631  *  0b0..The ZMK is not zero.
82632  *  0b1..The ZMK is zero.
82633  */
82634 #define SNVS_HPSR_ZMK_ZERO(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
82635 /*! @} */
82636 
82637 /*! @name HPSVSR - SNVS_HP Security Violation Status Register */
82638 /*! @{ */
82639 
82640 #define SNVS_HPSVSR_CAAM_MASK                    (0x1U)
82641 #define SNVS_HPSVSR_CAAM_SHIFT                   (0U)
82642 /*! CAAM
82643  *  0b0..No CAAM Security Violation security violation was detected.
82644  *  0b1..CAAM Security Violation security violation was detected.
82645  */
82646 #define SNVS_HPSVSR_CAAM(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_CAAM_SHIFT)) & SNVS_HPSVSR_CAAM_MASK)
82647 
82648 #define SNVS_HPSVSR_JTAGC_MASK                   (0x2U)
82649 #define SNVS_HPSVSR_JTAGC_SHIFT                  (1U)
82650 /*! JTAGC
82651  *  0b0..No JTAG Active security violation was detected.
82652  *  0b1..JTAG Active security violation was detected.
82653  */
82654 #define SNVS_HPSVSR_JTAGC(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_JTAGC_SHIFT)) & SNVS_HPSVSR_JTAGC_MASK)
82655 
82656 #define SNVS_HPSVSR_WDOG2_MASK                   (0x4U)
82657 #define SNVS_HPSVSR_WDOG2_SHIFT                  (2U)
82658 /*! WDOG2
82659  *  0b0..No Watchdog 2 Reset security violation was detected.
82660  *  0b1..Watchdog 2 Reset security violation was detected.
82661  */
82662 #define SNVS_HPSVSR_WDOG2(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_WDOG2_SHIFT)) & SNVS_HPSVSR_WDOG2_MASK)
82663 
82664 #define SNVS_HPSVSR_SRC_MASK                     (0x10U)
82665 #define SNVS_HPSVSR_SRC_SHIFT                    (4U)
82666 /*! SRC
82667  *  0b0..No Internal Boot security violation was detected.
82668  *  0b1..Internal Boot security violation was detected.
82669  */
82670 #define SNVS_HPSVSR_SRC(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SRC_SHIFT)) & SNVS_HPSVSR_SRC_MASK)
82671 
82672 #define SNVS_HPSVSR_OCOTP_MASK                   (0x20U)
82673 #define SNVS_HPSVSR_OCOTP_SHIFT                  (5U)
82674 /*! OCOTP
82675  *  0b0..No OCOTP attack error security violation was detected.
82676  *  0b1..OCOTP attack error security violation was detected.
82677  */
82678 #define SNVS_HPSVSR_OCOTP(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_OCOTP_SHIFT)) & SNVS_HPSVSR_OCOTP_MASK)
82679 
82680 #define SNVS_HPSVSR_SW_SV_MASK                   (0x2000U)
82681 #define SNVS_HPSVSR_SW_SV_SHIFT                  (13U)
82682 #define SNVS_HPSVSR_SW_SV(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
82683 
82684 #define SNVS_HPSVSR_SW_FSV_MASK                  (0x4000U)
82685 #define SNVS_HPSVSR_SW_FSV_SHIFT                 (14U)
82686 #define SNVS_HPSVSR_SW_FSV(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
82687 
82688 #define SNVS_HPSVSR_SW_LPSV_MASK                 (0x8000U)
82689 #define SNVS_HPSVSR_SW_LPSV_SHIFT                (15U)
82690 #define SNVS_HPSVSR_SW_LPSV(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
82691 
82692 #define SNVS_HPSVSR_ZMK_SYNDROME_MASK            (0x1FF0000U)
82693 #define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT           (16U)
82694 #define SNVS_HPSVSR_ZMK_SYNDROME(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
82695 
82696 #define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK            (0x8000000U)
82697 #define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT           (27U)
82698 /*! ZMK_ECC_FAIL
82699  *  0b0..ZMK ECC Failure was not detected.
82700  *  0b1..ZMK ECC Failure was detected.
82701  */
82702 #define SNVS_HPSVSR_ZMK_ECC_FAIL(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
82703 
82704 #define SNVS_HPSVSR_LP_SEC_VIO_MASK              (0x80000000U)
82705 #define SNVS_HPSVSR_LP_SEC_VIO_SHIFT             (31U)
82706 #define SNVS_HPSVSR_LP_SEC_VIO(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
82707 /*! @} */
82708 
82709 /*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */
82710 /*! @{ */
82711 
82712 #define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK        (0xFFFFFFFFU)
82713 #define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT       (0U)
82714 #define SNVS_HPHACIVR_HAC_COUNTER_IV(x)          (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
82715 /*! @} */
82716 
82717 /*! @name HPHACR - SNVS_HP High Assurance Counter Register */
82718 /*! @{ */
82719 
82720 #define SNVS_HPHACR_HAC_COUNTER_MASK             (0xFFFFFFFFU)
82721 #define SNVS_HPHACR_HAC_COUNTER_SHIFT            (0U)
82722 #define SNVS_HPHACR_HAC_COUNTER(x)               (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
82723 /*! @} */
82724 
82725 /*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */
82726 /*! @{ */
82727 
82728 #define SNVS_HPRTCMR_RTC_MASK                    (0x7FFFU)
82729 #define SNVS_HPRTCMR_RTC_SHIFT                   (0U)
82730 #define SNVS_HPRTCMR_RTC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
82731 /*! @} */
82732 
82733 /*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */
82734 /*! @{ */
82735 
82736 #define SNVS_HPRTCLR_RTC_MASK                    (0xFFFFFFFFU)
82737 #define SNVS_HPRTCLR_RTC_SHIFT                   (0U)
82738 #define SNVS_HPRTCLR_RTC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
82739 /*! @} */
82740 
82741 /*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */
82742 /*! @{ */
82743 
82744 #define SNVS_HPTAMR_HPTA_MS_MASK                 (0x7FFFU)
82745 #define SNVS_HPTAMR_HPTA_MS_SHIFT                (0U)
82746 #define SNVS_HPTAMR_HPTA_MS(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
82747 /*! @} */
82748 
82749 /*! @name HPTALR - SNVS_HP Time Alarm LSB Register */
82750 /*! @{ */
82751 
82752 #define SNVS_HPTALR_HPTA_LS_MASK                 (0xFFFFFFFFU)
82753 #define SNVS_HPTALR_HPTA_LS_SHIFT                (0U)
82754 #define SNVS_HPTALR_HPTA_LS(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
82755 /*! @} */
82756 
82757 /*! @name LPLR - SNVS_LP Lock Register */
82758 /*! @{ */
82759 
82760 #define SNVS_LPLR_ZMK_WHL_MASK                   (0x1U)
82761 #define SNVS_LPLR_ZMK_WHL_SHIFT                  (0U)
82762 /*! ZMK_WHL
82763  *  0b0..Write access is allowed.
82764  *  0b1..Write access is not allowed.
82765  */
82766 #define SNVS_LPLR_ZMK_WHL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
82767 
82768 #define SNVS_LPLR_ZMK_RHL_MASK                   (0x2U)
82769 #define SNVS_LPLR_ZMK_RHL_SHIFT                  (1U)
82770 /*! ZMK_RHL
82771  *  0b0..Read access is allowed (only in software programming mode).
82772  *  0b1..Read access is not allowed.
82773  */
82774 #define SNVS_LPLR_ZMK_RHL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
82775 
82776 #define SNVS_LPLR_SRTC_HL_MASK                   (0x4U)
82777 #define SNVS_LPLR_SRTC_HL_SHIFT                  (2U)
82778 /*! SRTC_HL
82779  *  0b0..Write access is allowed.
82780  *  0b1..Write access is not allowed.
82781  */
82782 #define SNVS_LPLR_SRTC_HL(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
82783 
82784 #define SNVS_LPLR_LPCALB_HL_MASK                 (0x8U)
82785 #define SNVS_LPLR_LPCALB_HL_SHIFT                (3U)
82786 /*! LPCALB_HL
82787  *  0b0..Write access is allowed.
82788  *  0b1..Write access is not allowed.
82789  */
82790 #define SNVS_LPLR_LPCALB_HL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
82791 
82792 #define SNVS_LPLR_MC_HL_MASK                     (0x10U)
82793 #define SNVS_LPLR_MC_HL_SHIFT                    (4U)
82794 /*! MC_HL
82795  *  0b0..Write access (increment) is allowed.
82796  *  0b1..Write access (increment) is not allowed.
82797  */
82798 #define SNVS_LPLR_MC_HL(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
82799 
82800 #define SNVS_LPLR_GPR_HL_MASK                    (0x20U)
82801 #define SNVS_LPLR_GPR_HL_SHIFT                   (5U)
82802 /*! GPR_HL
82803  *  0b0..Write access is allowed.
82804  *  0b1..Write access is not allowed.
82805  */
82806 #define SNVS_LPLR_GPR_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
82807 
82808 #define SNVS_LPLR_LPSVCR_HL_MASK                 (0x40U)
82809 #define SNVS_LPLR_LPSVCR_HL_SHIFT                (6U)
82810 /*! LPSVCR_HL
82811  *  0b0..Write access is allowed.
82812  *  0b1..Write access is not allowed.
82813  */
82814 #define SNVS_LPLR_LPSVCR_HL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
82815 
82816 #define SNVS_LPLR_LPTGFCR_HL_MASK                (0x80U)
82817 #define SNVS_LPLR_LPTGFCR_HL_SHIFT               (7U)
82818 /*! LPTGFCR_HL
82819  *  0b0..Write access is allowed.
82820  *  0b1..Write access is not allowed.
82821  */
82822 #define SNVS_LPLR_LPTGFCR_HL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTGFCR_HL_SHIFT)) & SNVS_LPLR_LPTGFCR_HL_MASK)
82823 
82824 #define SNVS_LPLR_LPSECR_HL_MASK                 (0x100U)
82825 #define SNVS_LPLR_LPSECR_HL_SHIFT                (8U)
82826 /*! LPSECR_HL
82827  *  0b0..Write access is allowed.
82828  *  0b1..Write access is not allowed.
82829  */
82830 #define SNVS_LPLR_LPSECR_HL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK)
82831 
82832 #define SNVS_LPLR_MKS_HL_MASK                    (0x200U)
82833 #define SNVS_LPLR_MKS_HL_SHIFT                   (9U)
82834 /*! MKS_HL
82835  *  0b0..Write access is allowed.
82836  *  0b1..Write access is not allowed.
82837  */
82838 #define SNVS_LPLR_MKS_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
82839 
82840 #define SNVS_LPLR_AT1_HL_MASK                    (0x1000000U)
82841 #define SNVS_LPLR_AT1_HL_SHIFT                   (24U)
82842 /*! AT1_HL
82843  *  0b0..Write access is allowed.
82844  *  0b1..Write access is not allowed.
82845  */
82846 #define SNVS_LPLR_AT1_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT1_HL_SHIFT)) & SNVS_LPLR_AT1_HL_MASK)
82847 
82848 #define SNVS_LPLR_AT2_HL_MASK                    (0x2000000U)
82849 #define SNVS_LPLR_AT2_HL_SHIFT                   (25U)
82850 /*! AT2_HL
82851  *  0b0..Write access is allowed.
82852  *  0b1..Write access is not allowed.
82853  */
82854 #define SNVS_LPLR_AT2_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT2_HL_SHIFT)) & SNVS_LPLR_AT2_HL_MASK)
82855 
82856 #define SNVS_LPLR_AT3_HL_MASK                    (0x4000000U)
82857 #define SNVS_LPLR_AT3_HL_SHIFT                   (26U)
82858 /*! AT3_HL
82859  *  0b0..Write access is allowed.
82860  *  0b1..Write access is not allowed.
82861  */
82862 #define SNVS_LPLR_AT3_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT3_HL_SHIFT)) & SNVS_LPLR_AT3_HL_MASK)
82863 
82864 #define SNVS_LPLR_AT4_HL_MASK                    (0x8000000U)
82865 #define SNVS_LPLR_AT4_HL_SHIFT                   (27U)
82866 /*! AT4_HL
82867  *  0b0..Write access is allowed.
82868  *  0b1..Write access is not allowed.
82869  */
82870 #define SNVS_LPLR_AT4_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT4_HL_SHIFT)) & SNVS_LPLR_AT4_HL_MASK)
82871 
82872 #define SNVS_LPLR_AT5_HL_MASK                    (0x10000000U)
82873 #define SNVS_LPLR_AT5_HL_SHIFT                   (28U)
82874 /*! AT5_HL
82875  *  0b0..Write access is allowed.
82876  *  0b1..Write access is not allowed.
82877  */
82878 #define SNVS_LPLR_AT5_HL(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT5_HL_SHIFT)) & SNVS_LPLR_AT5_HL_MASK)
82879 /*! @} */
82880 
82881 /*! @name LPCR - SNVS_LP Control Register */
82882 /*! @{ */
82883 
82884 #define SNVS_LPCR_SRTC_ENV_MASK                  (0x1U)
82885 #define SNVS_LPCR_SRTC_ENV_SHIFT                 (0U)
82886 /*! SRTC_ENV
82887  *  0b0..SRTC is disabled or invalid.
82888  *  0b1..SRTC is enabled and valid.
82889  */
82890 #define SNVS_LPCR_SRTC_ENV(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
82891 
82892 #define SNVS_LPCR_LPTA_EN_MASK                   (0x2U)
82893 #define SNVS_LPCR_LPTA_EN_SHIFT                  (1U)
82894 /*! LPTA_EN
82895  *  0b0..LP time alarm interrupt is disabled.
82896  *  0b1..LP time alarm interrupt is enabled.
82897  */
82898 #define SNVS_LPCR_LPTA_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
82899 
82900 #define SNVS_LPCR_MC_ENV_MASK                    (0x4U)
82901 #define SNVS_LPCR_MC_ENV_SHIFT                   (2U)
82902 /*! MC_ENV
82903  *  0b0..MC is disabled or invalid.
82904  *  0b1..MC is enabled and valid.
82905  */
82906 #define SNVS_LPCR_MC_ENV(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
82907 
82908 #define SNVS_LPCR_LPWUI_EN_MASK                  (0x8U)
82909 #define SNVS_LPCR_LPWUI_EN_SHIFT                 (3U)
82910 #define SNVS_LPCR_LPWUI_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
82911 
82912 #define SNVS_LPCR_SRTC_INV_EN_MASK               (0x10U)
82913 #define SNVS_LPCR_SRTC_INV_EN_SHIFT              (4U)
82914 /*! SRTC_INV_EN
82915  *  0b0..SRTC stays valid in the case of security violation (other than a software violation (HPSVSR[SW_LPSV] = 1 or HPCOMR[SW_LPSV] = 1)).
82916  *  0b1..SRTC is invalidated in the case of security violation.
82917  */
82918 #define SNVS_LPCR_SRTC_INV_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
82919 
82920 #define SNVS_LPCR_DP_EN_MASK                     (0x20U)
82921 #define SNVS_LPCR_DP_EN_SHIFT                    (5U)
82922 /*! DP_EN
82923  *  0b0..Smart PMIC enabled.
82924  *  0b1..Dumb PMIC enabled.
82925  */
82926 #define SNVS_LPCR_DP_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
82927 
82928 #define SNVS_LPCR_TOP_MASK                       (0x40U)
82929 #define SNVS_LPCR_TOP_SHIFT                      (6U)
82930 /*! TOP
82931  *  0b0..Leave system power on.
82932  *  0b1..Turn off system power.
82933  */
82934 #define SNVS_LPCR_TOP(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
82935 
82936 #define SNVS_LPCR_LVD_EN_MASK                    (0x80U)
82937 #define SNVS_LPCR_LVD_EN_SHIFT                   (7U)
82938 #define SNVS_LPCR_LVD_EN(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LVD_EN_SHIFT)) & SNVS_LPCR_LVD_EN_MASK)
82939 
82940 #define SNVS_LPCR_LPCALB_EN_MASK                 (0x100U)
82941 #define SNVS_LPCR_LPCALB_EN_SHIFT                (8U)
82942 /*! LPCALB_EN
82943  *  0b0..SRTC Time calibration is disabled.
82944  *  0b1..SRTC Time calibration is enabled.
82945  */
82946 #define SNVS_LPCR_LPCALB_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
82947 
82948 #define SNVS_LPCR_LPCALB_VAL_MASK                (0x7C00U)
82949 #define SNVS_LPCR_LPCALB_VAL_SHIFT               (10U)
82950 /*! LPCALB_VAL
82951  *  0b00000..+0 counts per each 32768 ticks of the counter clock
82952  *  0b00001..+1 counts per each 32768 ticks of the counter clock
82953  *  0b00010..+2 counts per each 32768 ticks of the counter clock
82954  *  0b01111..+15 counts per each 32768 ticks of the counter clock
82955  *  0b10000..-16 counts per each 32768 ticks of the counter clock
82956  *  0b10001..-15 counts per each 32768 ticks of the counter clock
82957  *  0b11110..-2 counts per each 32768 ticks of the counter clock
82958  *  0b11111..-1 counts per each 32768 ticks of the counter clock
82959  */
82960 #define SNVS_LPCR_LPCALB_VAL(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
82961 
82962 #define SNVS_LPCR_BTN_PRESS_TIME_MASK            (0x30000U)
82963 #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT           (16U)
82964 #define SNVS_LPCR_BTN_PRESS_TIME(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
82965 
82966 #define SNVS_LPCR_DEBOUNCE_MASK                  (0xC0000U)
82967 #define SNVS_LPCR_DEBOUNCE_SHIFT                 (18U)
82968 #define SNVS_LPCR_DEBOUNCE(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
82969 
82970 #define SNVS_LPCR_ON_TIME_MASK                   (0x300000U)
82971 #define SNVS_LPCR_ON_TIME_SHIFT                  (20U)
82972 #define SNVS_LPCR_ON_TIME(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
82973 
82974 #define SNVS_LPCR_PK_EN_MASK                     (0x400000U)
82975 #define SNVS_LPCR_PK_EN_SHIFT                    (22U)
82976 #define SNVS_LPCR_PK_EN(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
82977 
82978 #define SNVS_LPCR_PK_OVERRIDE_MASK               (0x800000U)
82979 #define SNVS_LPCR_PK_OVERRIDE_SHIFT              (23U)
82980 #define SNVS_LPCR_PK_OVERRIDE(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
82981 
82982 #define SNVS_LPCR_GPR_Z_DIS_MASK                 (0x1000000U)
82983 #define SNVS_LPCR_GPR_Z_DIS_SHIFT                (24U)
82984 #define SNVS_LPCR_GPR_Z_DIS(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
82985 /*! @} */
82986 
82987 /*! @name LPMKCR - SNVS_LP Master Key Control Register */
82988 /*! @{ */
82989 
82990 #define SNVS_LPMKCR_MASTER_KEY_SEL_MASK          (0x3U)
82991 #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT         (0U)
82992 /*! MASTER_KEY_SEL
82993  *  0b0x..Select one time programmable master key.
82994  *  0b10..Select zeroizable master key when MKS_EN bit is set .
82995  *  0b11..Select combined master key when MKS_EN bit is set .
82996  */
82997 #define SNVS_LPMKCR_MASTER_KEY_SEL(x)            (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
82998 
82999 #define SNVS_LPMKCR_ZMK_HWP_MASK                 (0x4U)
83000 #define SNVS_LPMKCR_ZMK_HWP_SHIFT                (2U)
83001 /*! ZMK_HWP
83002  *  0b0..ZMK is in the software programming mode.
83003  *  0b1..ZMK is in the hardware programming mode.
83004  */
83005 #define SNVS_LPMKCR_ZMK_HWP(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
83006 
83007 #define SNVS_LPMKCR_ZMK_VAL_MASK                 (0x8U)
83008 #define SNVS_LPMKCR_ZMK_VAL_SHIFT                (3U)
83009 /*! ZMK_VAL
83010  *  0b0..ZMK is not valid.
83011  *  0b1..ZMK is valid.
83012  */
83013 #define SNVS_LPMKCR_ZMK_VAL(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
83014 
83015 #define SNVS_LPMKCR_ZMK_ECC_EN_MASK              (0x10U)
83016 #define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT             (4U)
83017 /*! ZMK_ECC_EN
83018  *  0b0..ZMK ECC check is disabled.
83019  *  0b1..ZMK ECC check is enabled.
83020  */
83021 #define SNVS_LPMKCR_ZMK_ECC_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
83022 
83023 #define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK           (0xFF80U)
83024 #define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT          (7U)
83025 #define SNVS_LPMKCR_ZMK_ECC_VALUE(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
83026 /*! @} */
83027 
83028 /*! @name LPSVCR - SNVS_LP Security Violation Control Register */
83029 /*! @{ */
83030 
83031 #define SNVS_LPSVCR_CAAM_EN_MASK                 (0x1U)
83032 #define SNVS_LPSVCR_CAAM_EN_SHIFT                (0U)
83033 /*! CAAM_EN
83034  *  0b0..CAAM Security Violation is disabled in the LP domain.
83035  *  0b1..CAAM Security Violation is enabled in the LP domain.
83036  */
83037 #define SNVS_LPSVCR_CAAM_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_CAAM_EN_SHIFT)) & SNVS_LPSVCR_CAAM_EN_MASK)
83038 
83039 #define SNVS_LPSVCR_JTAGC_EN_MASK                (0x2U)
83040 #define SNVS_LPSVCR_JTAGC_EN_SHIFT               (1U)
83041 /*! JTAGC_EN
83042  *  0b0..JTAG Active is disabled in the LP domain.
83043  *  0b1..JTAG Active is enabled in the LP domain.
83044  */
83045 #define SNVS_LPSVCR_JTAGC_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_JTAGC_EN_SHIFT)) & SNVS_LPSVCR_JTAGC_EN_MASK)
83046 
83047 #define SNVS_LPSVCR_WDOG2_EN_MASK                (0x4U)
83048 #define SNVS_LPSVCR_WDOG2_EN_SHIFT               (2U)
83049 /*! WDOG2_EN
83050  *  0b0..Watchdog 2 Reset is disabled in the LP domain.
83051  *  0b1..Watchdog 2 Reset is enabled in the LP domain.
83052  */
83053 #define SNVS_LPSVCR_WDOG2_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_WDOG2_EN_SHIFT)) & SNVS_LPSVCR_WDOG2_EN_MASK)
83054 
83055 #define SNVS_LPSVCR_SRC_EN_MASK                  (0x10U)
83056 #define SNVS_LPSVCR_SRC_EN_SHIFT                 (4U)
83057 /*! SRC_EN
83058  *  0b0..Internal Boot is disabled in the LP domain.
83059  *  0b1..Internal Boot is enabled in the LP domain.
83060  */
83061 #define SNVS_LPSVCR_SRC_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SRC_EN_SHIFT)) & SNVS_LPSVCR_SRC_EN_MASK)
83062 
83063 #define SNVS_LPSVCR_OCOTP_EN_MASK                (0x20U)
83064 #define SNVS_LPSVCR_OCOTP_EN_SHIFT               (5U)
83065 /*! OCOTP_EN
83066  *  0b0..OCOTP attack error is disabled in the LP domain.
83067  *  0b1..OCOTP attack error is enabled in the LP domain.
83068  */
83069 #define SNVS_LPSVCR_OCOTP_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_OCOTP_EN_SHIFT)) & SNVS_LPSVCR_OCOTP_EN_MASK)
83070 /*! @} */
83071 
83072 /*! @name LPTGFCR - SNVS_LP Tamper Glitch Filters Configuration Register */
83073 /*! @{ */
83074 
83075 #define SNVS_LPTGFCR_WMTGF_MASK                  (0x1FU)
83076 #define SNVS_LPTGFCR_WMTGF_SHIFT                 (0U)
83077 #define SNVS_LPTGFCR_WMTGF(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_SHIFT)) & SNVS_LPTGFCR_WMTGF_MASK)
83078 
83079 #define SNVS_LPTGFCR_WMTGF_EN_MASK               (0x80U)
83080 #define SNVS_LPTGFCR_WMTGF_EN_SHIFT              (7U)
83081 /*! WMTGF_EN
83082  *  0b0..Wire-mesh tamper glitch filter is bypassed.
83083  *  0b1..Wire-mesh tamper glitch filter is enabled.
83084  */
83085 #define SNVS_LPTGFCR_WMTGF_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_EN_SHIFT)) & SNVS_LPTGFCR_WMTGF_EN_MASK)
83086 
83087 #define SNVS_LPTGFCR_ETGF1_MASK                  (0x7F0000U)
83088 #define SNVS_LPTGFCR_ETGF1_SHIFT                 (16U)
83089 #define SNVS_LPTGFCR_ETGF1(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_SHIFT)) & SNVS_LPTGFCR_ETGF1_MASK)
83090 
83091 #define SNVS_LPTGFCR_ETGF1_EN_MASK               (0x800000U)
83092 #define SNVS_LPTGFCR_ETGF1_EN_SHIFT              (23U)
83093 /*! ETGF1_EN
83094  *  0b0..External tamper glitch filter 1 is bypassed.
83095  *  0b1..External tamper glitch filter 1 is enabled.
83096  */
83097 #define SNVS_LPTGFCR_ETGF1_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_EN_SHIFT)) & SNVS_LPTGFCR_ETGF1_EN_MASK)
83098 
83099 #define SNVS_LPTGFCR_ETGF2_MASK                  (0x7F000000U)
83100 #define SNVS_LPTGFCR_ETGF2_SHIFT                 (24U)
83101 #define SNVS_LPTGFCR_ETGF2(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_SHIFT)) & SNVS_LPTGFCR_ETGF2_MASK)
83102 
83103 #define SNVS_LPTGFCR_ETGF2_EN_MASK               (0x80000000U)
83104 #define SNVS_LPTGFCR_ETGF2_EN_SHIFT              (31U)
83105 /*! ETGF2_EN
83106  *  0b0..External tamper glitch filter 2 is bypassed.
83107  *  0b1..External tamper glitch filter 2 is enabled.
83108  */
83109 #define SNVS_LPTGFCR_ETGF2_EN(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_EN_SHIFT)) & SNVS_LPTGFCR_ETGF2_EN_MASK)
83110 /*! @} */
83111 
83112 /*! @name LPTDCR - SNVS_LP Tamper Detect Configuration Register */
83113 /*! @{ */
83114 
83115 #define SNVS_LPTDCR_SRTCR_EN_MASK                (0x2U)
83116 #define SNVS_LPTDCR_SRTCR_EN_SHIFT               (1U)
83117 /*! SRTCR_EN
83118  *  0b0..SRTC rollover is disabled.
83119  *  0b1..SRTC rollover is enabled.
83120  */
83121 #define SNVS_LPTDCR_SRTCR_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)
83122 
83123 #define SNVS_LPTDCR_MCR_EN_MASK                  (0x4U)
83124 #define SNVS_LPTDCR_MCR_EN_SHIFT                 (2U)
83125 /*! MCR_EN
83126  *  0b0..MC rollover is disabled.
83127  *  0b1..MC rollover is enabled.
83128  */
83129 #define SNVS_LPTDCR_MCR_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)
83130 
83131 #define SNVS_LPTDCR_CT_EN_MASK                   (0x10U)
83132 #define SNVS_LPTDCR_CT_EN_SHIFT                  (4U)
83133 /*! CT_EN
83134  *  0b0..Clock tamper is disabled.
83135  *  0b1..Clock tamper is enabled.
83136  */
83137 #define SNVS_LPTDCR_CT_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_CT_EN_SHIFT)) & SNVS_LPTDCR_CT_EN_MASK)
83138 
83139 #define SNVS_LPTDCR_TT_EN_MASK                   (0x20U)
83140 #define SNVS_LPTDCR_TT_EN_SHIFT                  (5U)
83141 /*! TT_EN
83142  *  0b0..Temperature tamper is disabled.
83143  *  0b1..Temperature tamper is enabled.
83144  */
83145 #define SNVS_LPTDCR_TT_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_TT_EN_SHIFT)) & SNVS_LPTDCR_TT_EN_MASK)
83146 
83147 #define SNVS_LPTDCR_VT_EN_MASK                   (0x40U)
83148 #define SNVS_LPTDCR_VT_EN_SHIFT                  (6U)
83149 /*! VT_EN
83150  *  0b0..Voltage tamper is disabled.
83151  *  0b1..Voltage tamper is enabled.
83152  */
83153 #define SNVS_LPTDCR_VT_EN(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VT_EN_SHIFT)) & SNVS_LPTDCR_VT_EN_MASK)
83154 
83155 #define SNVS_LPTDCR_WMT1_EN_MASK                 (0x80U)
83156 #define SNVS_LPTDCR_WMT1_EN_SHIFT                (7U)
83157 /*! WMT1_EN
83158  *  0b0..Wire-mesh tamper 1 is disabled.
83159  *  0b1..Wire-mesh tamper 1 is enabled.
83160  */
83161 #define SNVS_LPTDCR_WMT1_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT1_EN_SHIFT)) & SNVS_LPTDCR_WMT1_EN_MASK)
83162 
83163 #define SNVS_LPTDCR_WMT2_EN_MASK                 (0x100U)
83164 #define SNVS_LPTDCR_WMT2_EN_SHIFT                (8U)
83165 /*! WMT2_EN
83166  *  0b0..Wire-mesh tamper 2 is disabled.
83167  *  0b1..Wire-mesh tamper 2 is enabled.
83168  */
83169 #define SNVS_LPTDCR_WMT2_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT2_EN_SHIFT)) & SNVS_LPTDCR_WMT2_EN_MASK)
83170 
83171 #define SNVS_LPTDCR_ET1_EN_MASK                  (0x200U)
83172 #define SNVS_LPTDCR_ET1_EN_SHIFT                 (9U)
83173 /*! ET1_EN
83174  *  0b0..External tamper 1 is disabled.
83175  *  0b1..External tamper 1 is enabled.
83176  */
83177 #define SNVS_LPTDCR_ET1_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)
83178 
83179 #define SNVS_LPTDCR_ET2_EN_MASK                  (0x400U)
83180 #define SNVS_LPTDCR_ET2_EN_SHIFT                 (10U)
83181 /*! ET2_EN
83182  *  0b0..External tamper 2 is disabled.
83183  *  0b1..External tamper 2 is enabled.
83184  */
83185 #define SNVS_LPTDCR_ET2_EN(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2_EN_SHIFT)) & SNVS_LPTDCR_ET2_EN_MASK)
83186 
83187 #define SNVS_LPTDCR_ET1P_MASK                    (0x800U)
83188 #define SNVS_LPTDCR_ET1P_SHIFT                   (11U)
83189 /*! ET1P
83190  *  0b0..External tamper 1 is active low.
83191  *  0b1..External tamper 1 is active high.
83192  */
83193 #define SNVS_LPTDCR_ET1P(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)
83194 
83195 #define SNVS_LPTDCR_ET2P_MASK                    (0x1000U)
83196 #define SNVS_LPTDCR_ET2P_SHIFT                   (12U)
83197 /*! ET2P
83198  *  0b0..External tamper 2 is active low.
83199  *  0b1..External tamper 2 is active high.
83200  */
83201 #define SNVS_LPTDCR_ET2P(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2P_SHIFT)) & SNVS_LPTDCR_ET2P_MASK)
83202 
83203 #define SNVS_LPTDCR_PFD_OBSERV_MASK              (0x4000U)
83204 #define SNVS_LPTDCR_PFD_OBSERV_SHIFT             (14U)
83205 #define SNVS_LPTDCR_PFD_OBSERV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)
83206 
83207 #define SNVS_LPTDCR_POR_OBSERV_MASK              (0x8000U)
83208 #define SNVS_LPTDCR_POR_OBSERV_SHIFT             (15U)
83209 #define SNVS_LPTDCR_POR_OBSERV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)
83210 
83211 #define SNVS_LPTDCR_LTDC_MASK                    (0x70000U)
83212 #define SNVS_LPTDCR_LTDC_SHIFT                   (16U)
83213 #define SNVS_LPTDCR_LTDC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_LTDC_SHIFT)) & SNVS_LPTDCR_LTDC_MASK)
83214 
83215 #define SNVS_LPTDCR_HTDC_MASK                    (0x700000U)
83216 #define SNVS_LPTDCR_HTDC_SHIFT                   (20U)
83217 #define SNVS_LPTDCR_HTDC(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_HTDC_SHIFT)) & SNVS_LPTDCR_HTDC_MASK)
83218 
83219 #define SNVS_LPTDCR_VRC_MASK                     (0x7000000U)
83220 #define SNVS_LPTDCR_VRC_SHIFT                    (24U)
83221 #define SNVS_LPTDCR_VRC(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VRC_SHIFT)) & SNVS_LPTDCR_VRC_MASK)
83222 
83223 #define SNVS_LPTDCR_OSCB_MASK                    (0x10000000U)
83224 #define SNVS_LPTDCR_OSCB_SHIFT                   (28U)
83225 /*! OSCB
83226  *  0b0..Normal SRTC clock oscillator not bypassed.
83227  *  0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source.
83228  */
83229 #define SNVS_LPTDCR_OSCB(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)
83230 /*! @} */
83231 
83232 /*! @name LPSR - SNVS_LP Status Register */
83233 /*! @{ */
83234 
83235 #define SNVS_LPSR_LPTA_MASK                      (0x1U)
83236 #define SNVS_LPSR_LPTA_SHIFT                     (0U)
83237 /*! LPTA
83238  *  0b0..No time alarm interrupt occurred.
83239  *  0b1..A time alarm interrupt occurred.
83240  */
83241 #define SNVS_LPSR_LPTA(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
83242 
83243 #define SNVS_LPSR_SRTCR_MASK                     (0x2U)
83244 #define SNVS_LPSR_SRTCR_SHIFT                    (1U)
83245 /*! SRTCR
83246  *  0b0..SRTC has not reached its maximum value.
83247  *  0b1..SRTC has reached its maximum value.
83248  */
83249 #define SNVS_LPSR_SRTCR(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
83250 
83251 #define SNVS_LPSR_MCR_MASK                       (0x4U)
83252 #define SNVS_LPSR_MCR_SHIFT                      (2U)
83253 /*! MCR
83254  *  0b0..MC has not reached its maximum value.
83255  *  0b1..MC has reached its maximum value.
83256  */
83257 #define SNVS_LPSR_MCR(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
83258 
83259 #define SNVS_LPSR_LVD_MASK                       (0x8U)
83260 #define SNVS_LPSR_LVD_SHIFT                      (3U)
83261 /*! LVD
83262  *  0b0..No low voltage event detected.
83263  *  0b1..Low voltage event is detected.
83264  */
83265 #define SNVS_LPSR_LVD(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LVD_SHIFT)) & SNVS_LPSR_LVD_MASK)
83266 
83267 #define SNVS_LPSR_CTD_MASK                       (0x10U)
83268 #define SNVS_LPSR_CTD_SHIFT                      (4U)
83269 /*! CTD
83270  *  0b0..No clock tamper.
83271  *  0b1..Clock tamper is detected.
83272  */
83273 #define SNVS_LPSR_CTD(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_CTD_SHIFT)) & SNVS_LPSR_CTD_MASK)
83274 
83275 #define SNVS_LPSR_TTD_MASK                       (0x20U)
83276 #define SNVS_LPSR_TTD_SHIFT                      (5U)
83277 /*! TTD
83278  *  0b0..No temperature tamper.
83279  *  0b1..Temperature tamper is detected.
83280  */
83281 #define SNVS_LPSR_TTD(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_TTD_SHIFT)) & SNVS_LPSR_TTD_MASK)
83282 
83283 #define SNVS_LPSR_VTD_MASK                       (0x40U)
83284 #define SNVS_LPSR_VTD_SHIFT                      (6U)
83285 /*! VTD
83286  *  0b0..Voltage tampering not detected.
83287  *  0b1..Voltage tampering detected.
83288  */
83289 #define SNVS_LPSR_VTD(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
83290 
83291 #define SNVS_LPSR_WMT1D_MASK                     (0x80U)
83292 #define SNVS_LPSR_WMT1D_SHIFT                    (7U)
83293 /*! WMT1D
83294  *  0b0..Wire-mesh tampering 1 not detected.
83295  *  0b1..Wire-mesh tampering 1 detected.
83296  */
83297 #define SNVS_LPSR_WMT1D(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT1D_SHIFT)) & SNVS_LPSR_WMT1D_MASK)
83298 
83299 #define SNVS_LPSR_WMT2D_MASK                     (0x100U)
83300 #define SNVS_LPSR_WMT2D_SHIFT                    (8U)
83301 /*! WMT2D
83302  *  0b0..Wire-mesh tampering 2 not detected.
83303  *  0b1..Wire-mesh tampering 2 detected.
83304  */
83305 #define SNVS_LPSR_WMT2D(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT2D_SHIFT)) & SNVS_LPSR_WMT2D_MASK)
83306 
83307 #define SNVS_LPSR_ET1D_MASK                      (0x200U)
83308 #define SNVS_LPSR_ET1D_SHIFT                     (9U)
83309 /*! ET1D
83310  *  0b0..External tampering 1 not detected.
83311  *  0b1..External tampering 1 detected.
83312  */
83313 #define SNVS_LPSR_ET1D(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)
83314 
83315 #define SNVS_LPSR_ET2D_MASK                      (0x400U)
83316 #define SNVS_LPSR_ET2D_SHIFT                     (10U)
83317 /*! ET2D
83318  *  0b0..External tampering 2 not detected.
83319  *  0b1..External tampering 2 detected.
83320  */
83321 #define SNVS_LPSR_ET2D(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
83322 
83323 #define SNVS_LPSR_ESVD_MASK                      (0x10000U)
83324 #define SNVS_LPSR_ESVD_SHIFT                     (16U)
83325 /*! ESVD
83326  *  0b0..No external security violation.
83327  *  0b1..External security violation is detected.
83328  */
83329 #define SNVS_LPSR_ESVD(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
83330 
83331 #define SNVS_LPSR_EO_MASK                        (0x20000U)
83332 #define SNVS_LPSR_EO_SHIFT                       (17U)
83333 /*! EO
83334  *  0b0..Emergency off was not detected.
83335  *  0b1..Emergency off was detected.
83336  */
83337 #define SNVS_LPSR_EO(x)                          (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
83338 
83339 #define SNVS_LPSR_SPOF_MASK                      (0x40000U)
83340 #define SNVS_LPSR_SPOF_SHIFT                     (18U)
83341 /*! SPOF
83342  *  0b0..Set Power Off was not detected.
83343  *  0b1..Set Power Off was detected.
83344  */
83345 #define SNVS_LPSR_SPOF(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)
83346 
83347 #define SNVS_LPSR_LPNS_MASK                      (0x40000000U)
83348 #define SNVS_LPSR_LPNS_SHIFT                     (30U)
83349 /*! LPNS
83350  *  0b0..LP section was not programmed in the non-secure state.
83351  *  0b1..LP section was programmed in the non-secure state.
83352  */
83353 #define SNVS_LPSR_LPNS(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
83354 
83355 #define SNVS_LPSR_LPS_MASK                       (0x80000000U)
83356 #define SNVS_LPSR_LPS_SHIFT                      (31U)
83357 /*! LPS
83358  *  0b0..LP section was not programmed in secure or trusted state.
83359  *  0b1..LP section was programmed in secure or trusted state.
83360  */
83361 #define SNVS_LPSR_LPS(x)                         (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
83362 /*! @} */
83363 
83364 /*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */
83365 /*! @{ */
83366 
83367 #define SNVS_LPSRTCMR_SRTC_MASK                  (0x7FFFU)
83368 #define SNVS_LPSRTCMR_SRTC_SHIFT                 (0U)
83369 #define SNVS_LPSRTCMR_SRTC(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
83370 /*! @} */
83371 
83372 /*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */
83373 /*! @{ */
83374 
83375 #define SNVS_LPSRTCLR_SRTC_MASK                  (0xFFFFFFFFU)
83376 #define SNVS_LPSRTCLR_SRTC_SHIFT                 (0U)
83377 #define SNVS_LPSRTCLR_SRTC(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
83378 /*! @} */
83379 
83380 /*! @name LPTAR - SNVS_LP Time Alarm Register */
83381 /*! @{ */
83382 
83383 #define SNVS_LPTAR_LPTA_MASK                     (0xFFFFFFFFU)
83384 #define SNVS_LPTAR_LPTA_SHIFT                    (0U)
83385 #define SNVS_LPTAR_LPTA(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
83386 /*! @} */
83387 
83388 /*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */
83389 /*! @{ */
83390 
83391 #define SNVS_LPSMCMR_MON_COUNTER_MASK            (0xFFFFU)
83392 #define SNVS_LPSMCMR_MON_COUNTER_SHIFT           (0U)
83393 #define SNVS_LPSMCMR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
83394 
83395 #define SNVS_LPSMCMR_MC_ERA_BITS_MASK            (0xFFFF0000U)
83396 #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT           (16U)
83397 #define SNVS_LPSMCMR_MC_ERA_BITS(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
83398 /*! @} */
83399 
83400 /*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */
83401 /*! @{ */
83402 
83403 #define SNVS_LPSMCLR_MON_COUNTER_MASK            (0xFFFFFFFFU)
83404 #define SNVS_LPSMCLR_MON_COUNTER_SHIFT           (0U)
83405 #define SNVS_LPSMCLR_MON_COUNTER(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
83406 /*! @} */
83407 
83408 /*! @name LPLVDR - SNVS_LP Digital Low-Voltage Detector Register */
83409 /*! @{ */
83410 
83411 #define SNVS_LPLVDR_LVD_MASK                     (0xFFFFFFFFU)
83412 #define SNVS_LPLVDR_LVD_SHIFT                    (0U)
83413 #define SNVS_LPLVDR_LVD(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPLVDR_LVD_SHIFT)) & SNVS_LPLVDR_LVD_MASK)
83414 /*! @} */
83415 
83416 /*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */
83417 /*! @{ */
83418 
83419 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK        (0xFFFFFFFFU)
83420 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT       (0U)
83421 #define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x)          (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
83422 /*! @} */
83423 
83424 /*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */
83425 /*! @{ */
83426 
83427 #define SNVS_LPZMKR_ZMK_MASK                     (0xFFFFFFFFU)
83428 #define SNVS_LPZMKR_ZMK_SHIFT                    (0U)
83429 #define SNVS_LPZMKR_ZMK(x)                       (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
83430 /*! @} */
83431 
83432 /* The count of SNVS_LPZMKR */
83433 #define SNVS_LPZMKR_COUNT                        (8U)
83434 
83435 /*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */
83436 /*! @{ */
83437 
83438 #define SNVS_LPGPR_ALIAS_GPR_MASK                (0xFFFFFFFFU)
83439 #define SNVS_LPGPR_ALIAS_GPR_SHIFT               (0U)
83440 #define SNVS_LPGPR_ALIAS_GPR(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
83441 /*! @} */
83442 
83443 /* The count of SNVS_LPGPR_ALIAS */
83444 #define SNVS_LPGPR_ALIAS_COUNT                   (4U)
83445 
83446 /*! @name LPTDC2R - SNVS_LP Tamper Detectors Config 2 Register */
83447 /*! @{ */
83448 
83449 #define SNVS_LPTDC2R_ET3_EN_MASK                 (0x1U)
83450 #define SNVS_LPTDC2R_ET3_EN_SHIFT                (0U)
83451 /*! ET3_EN
83452  *  0b0..External tamper 3 is disabled.
83453  *  0b1..External tamper 3 is enabled.
83454  */
83455 #define SNVS_LPTDC2R_ET3_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3_EN_SHIFT)) & SNVS_LPTDC2R_ET3_EN_MASK)
83456 
83457 #define SNVS_LPTDC2R_ET4_EN_MASK                 (0x2U)
83458 #define SNVS_LPTDC2R_ET4_EN_SHIFT                (1U)
83459 /*! ET4_EN
83460  *  0b0..External tamper 4 is disabled.
83461  *  0b1..External tamper 4 is enabled.
83462  */
83463 #define SNVS_LPTDC2R_ET4_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4_EN_SHIFT)) & SNVS_LPTDC2R_ET4_EN_MASK)
83464 
83465 #define SNVS_LPTDC2R_ET5_EN_MASK                 (0x4U)
83466 #define SNVS_LPTDC2R_ET5_EN_SHIFT                (2U)
83467 /*! ET5_EN
83468  *  0b0..External tamper 5 is disabled.
83469  *  0b1..External tamper 5 is enabled.
83470  */
83471 #define SNVS_LPTDC2R_ET5_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5_EN_SHIFT)) & SNVS_LPTDC2R_ET5_EN_MASK)
83472 
83473 #define SNVS_LPTDC2R_ET6_EN_MASK                 (0x8U)
83474 #define SNVS_LPTDC2R_ET6_EN_SHIFT                (3U)
83475 /*! ET6_EN
83476  *  0b0..External tamper 6 is disabled.
83477  *  0b1..External tamper 6 is enabled.
83478  */
83479 #define SNVS_LPTDC2R_ET6_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6_EN_SHIFT)) & SNVS_LPTDC2R_ET6_EN_MASK)
83480 
83481 #define SNVS_LPTDC2R_ET7_EN_MASK                 (0x10U)
83482 #define SNVS_LPTDC2R_ET7_EN_SHIFT                (4U)
83483 /*! ET7_EN
83484  *  0b0..External tamper 7 is disabled.
83485  *  0b1..External tamper 7 is enabled.
83486  */
83487 #define SNVS_LPTDC2R_ET7_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7_EN_SHIFT)) & SNVS_LPTDC2R_ET7_EN_MASK)
83488 
83489 #define SNVS_LPTDC2R_ET8_EN_MASK                 (0x20U)
83490 #define SNVS_LPTDC2R_ET8_EN_SHIFT                (5U)
83491 /*! ET8_EN
83492  *  0b0..External tamper 8 is disabled.
83493  *  0b1..External tamper 8 is enabled.
83494  */
83495 #define SNVS_LPTDC2R_ET8_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8_EN_SHIFT)) & SNVS_LPTDC2R_ET8_EN_MASK)
83496 
83497 #define SNVS_LPTDC2R_ET9_EN_MASK                 (0x40U)
83498 #define SNVS_LPTDC2R_ET9_EN_SHIFT                (6U)
83499 /*! ET9_EN
83500  *  0b0..External tamper 9 is disabled.
83501  *  0b1..External tamper 9 is enabled.
83502  */
83503 #define SNVS_LPTDC2R_ET9_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9_EN_SHIFT)) & SNVS_LPTDC2R_ET9_EN_MASK)
83504 
83505 #define SNVS_LPTDC2R_ET10_EN_MASK                (0x80U)
83506 #define SNVS_LPTDC2R_ET10_EN_SHIFT               (7U)
83507 /*! ET10_EN
83508  *  0b0..External tamper 10 is disabled.
83509  *  0b1..External tamper 10 is enabled.
83510  */
83511 #define SNVS_LPTDC2R_ET10_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10_EN_SHIFT)) & SNVS_LPTDC2R_ET10_EN_MASK)
83512 
83513 #define SNVS_LPTDC2R_ET3P_MASK                   (0x10000U)
83514 #define SNVS_LPTDC2R_ET3P_SHIFT                  (16U)
83515 /*! ET3P
83516  *  0b0..External tamper 3 active low.
83517  *  0b1..External tamper 3 active high.
83518  */
83519 #define SNVS_LPTDC2R_ET3P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3P_SHIFT)) & SNVS_LPTDC2R_ET3P_MASK)
83520 
83521 #define SNVS_LPTDC2R_ET4P_MASK                   (0x20000U)
83522 #define SNVS_LPTDC2R_ET4P_SHIFT                  (17U)
83523 /*! ET4P
83524  *  0b0..External tamper 4 is active low.
83525  *  0b1..External tamper 4 is active high.
83526  */
83527 #define SNVS_LPTDC2R_ET4P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4P_SHIFT)) & SNVS_LPTDC2R_ET4P_MASK)
83528 
83529 #define SNVS_LPTDC2R_ET5P_MASK                   (0x40000U)
83530 #define SNVS_LPTDC2R_ET5P_SHIFT                  (18U)
83531 /*! ET5P
83532  *  0b0..External tamper 5 is active low.
83533  *  0b1..External tamper 5 is active high.
83534  */
83535 #define SNVS_LPTDC2R_ET5P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5P_SHIFT)) & SNVS_LPTDC2R_ET5P_MASK)
83536 
83537 #define SNVS_LPTDC2R_ET6P_MASK                   (0x80000U)
83538 #define SNVS_LPTDC2R_ET6P_SHIFT                  (19U)
83539 /*! ET6P
83540  *  0b0..External tamper 6 is active low.
83541  *  0b1..External tamper 6 is active high.
83542  */
83543 #define SNVS_LPTDC2R_ET6P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6P_SHIFT)) & SNVS_LPTDC2R_ET6P_MASK)
83544 
83545 #define SNVS_LPTDC2R_ET7P_MASK                   (0x100000U)
83546 #define SNVS_LPTDC2R_ET7P_SHIFT                  (20U)
83547 /*! ET7P
83548  *  0b0..External tamper 7 is active low.
83549  *  0b1..External tamper 7 is active high.
83550  */
83551 #define SNVS_LPTDC2R_ET7P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7P_SHIFT)) & SNVS_LPTDC2R_ET7P_MASK)
83552 
83553 #define SNVS_LPTDC2R_ET8P_MASK                   (0x200000U)
83554 #define SNVS_LPTDC2R_ET8P_SHIFT                  (21U)
83555 /*! ET8P
83556  *  0b0..External tamper 8 is active low.
83557  *  0b1..External tamper 8 is active high.
83558  */
83559 #define SNVS_LPTDC2R_ET8P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8P_SHIFT)) & SNVS_LPTDC2R_ET8P_MASK)
83560 
83561 #define SNVS_LPTDC2R_ET9P_MASK                   (0x400000U)
83562 #define SNVS_LPTDC2R_ET9P_SHIFT                  (22U)
83563 /*! ET9P
83564  *  0b0..External tamper 9 is active low.
83565  *  0b1..External tamper 9 is active high.
83566  */
83567 #define SNVS_LPTDC2R_ET9P(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9P_SHIFT)) & SNVS_LPTDC2R_ET9P_MASK)
83568 
83569 #define SNVS_LPTDC2R_ET10P_MASK                  (0x800000U)
83570 #define SNVS_LPTDC2R_ET10P_SHIFT                 (23U)
83571 /*! ET10P
83572  *  0b0..External tamper 10 is active low.
83573  *  0b1..External tamper 10 is active high.
83574  */
83575 #define SNVS_LPTDC2R_ET10P(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10P_SHIFT)) & SNVS_LPTDC2R_ET10P_MASK)
83576 /*! @} */
83577 
83578 /*! @name LPTDSR - SNVS_LP Tamper Detectors Status Register */
83579 /*! @{ */
83580 
83581 #define SNVS_LPTDSR_ET3D_MASK                    (0x1U)
83582 #define SNVS_LPTDSR_ET3D_SHIFT                   (0U)
83583 /*! ET3D
83584  *  0b0..External tamper 3 is not detected.
83585  *  0b1..External tamper 3 is detected.
83586  */
83587 #define SNVS_LPTDSR_ET3D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET3D_SHIFT)) & SNVS_LPTDSR_ET3D_MASK)
83588 
83589 #define SNVS_LPTDSR_ET4D_MASK                    (0x2U)
83590 #define SNVS_LPTDSR_ET4D_SHIFT                   (1U)
83591 /*! ET4D
83592  *  0b0..External tamper 4 is not detected.
83593  *  0b1..External tamper 4 is detected.
83594  */
83595 #define SNVS_LPTDSR_ET4D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET4D_SHIFT)) & SNVS_LPTDSR_ET4D_MASK)
83596 
83597 #define SNVS_LPTDSR_ET5D_MASK                    (0x4U)
83598 #define SNVS_LPTDSR_ET5D_SHIFT                   (2U)
83599 /*! ET5D
83600  *  0b0..External tamper 5 is not detected.
83601  *  0b1..External tamper 5 is detected.
83602  */
83603 #define SNVS_LPTDSR_ET5D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET5D_SHIFT)) & SNVS_LPTDSR_ET5D_MASK)
83604 
83605 #define SNVS_LPTDSR_ET6D_MASK                    (0x8U)
83606 #define SNVS_LPTDSR_ET6D_SHIFT                   (3U)
83607 /*! ET6D
83608  *  0b0..External tamper 6 is not detected.
83609  *  0b1..External tamper 6 is detected.
83610  */
83611 #define SNVS_LPTDSR_ET6D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET6D_SHIFT)) & SNVS_LPTDSR_ET6D_MASK)
83612 
83613 #define SNVS_LPTDSR_ET7D_MASK                    (0x10U)
83614 #define SNVS_LPTDSR_ET7D_SHIFT                   (4U)
83615 /*! ET7D
83616  *  0b0..External tamper 7 is not detected.
83617  *  0b1..External tamper 7 is detected.
83618  */
83619 #define SNVS_LPTDSR_ET7D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET7D_SHIFT)) & SNVS_LPTDSR_ET7D_MASK)
83620 
83621 #define SNVS_LPTDSR_ET8D_MASK                    (0x20U)
83622 #define SNVS_LPTDSR_ET8D_SHIFT                   (5U)
83623 /*! ET8D
83624  *  0b0..External tamper 8 is not detected.
83625  *  0b1..External tamper 8 is detected.
83626  */
83627 #define SNVS_LPTDSR_ET8D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET8D_SHIFT)) & SNVS_LPTDSR_ET8D_MASK)
83628 
83629 #define SNVS_LPTDSR_ET9D_MASK                    (0x40U)
83630 #define SNVS_LPTDSR_ET9D_SHIFT                   (6U)
83631 /*! ET9D
83632  *  0b0..External tamper 9 is not detected.
83633  *  0b1..External tamper 9 is detected.
83634  */
83635 #define SNVS_LPTDSR_ET9D(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET9D_SHIFT)) & SNVS_LPTDSR_ET9D_MASK)
83636 
83637 #define SNVS_LPTDSR_ET10D_MASK                   (0x80U)
83638 #define SNVS_LPTDSR_ET10D_SHIFT                  (7U)
83639 /*! ET10D
83640  *  0b0..External tamper 10 is not detected.
83641  *  0b1..External tamper 10 is detected.
83642  */
83643 #define SNVS_LPTDSR_ET10D(x)                     (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET10D_SHIFT)) & SNVS_LPTDSR_ET10D_MASK)
83644 /*! @} */
83645 
83646 /*! @name LPTGF1CR - SNVS_LP Tamper Glitch Filter 1 Configuration Register */
83647 /*! @{ */
83648 
83649 #define SNVS_LPTGF1CR_ETGF3_MASK                 (0x7FU)
83650 #define SNVS_LPTGF1CR_ETGF3_SHIFT                (0U)
83651 #define SNVS_LPTGF1CR_ETGF3(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_SHIFT)) & SNVS_LPTGF1CR_ETGF3_MASK)
83652 
83653 #define SNVS_LPTGF1CR_ETGF3_EN_MASK              (0x80U)
83654 #define SNVS_LPTGF1CR_ETGF3_EN_SHIFT             (7U)
83655 /*! ETGF3_EN
83656  *  0b0..External tamper glitch filter 3 is bypassed.
83657  *  0b1..External tamper glitch filter 3 is enabled.
83658  */
83659 #define SNVS_LPTGF1CR_ETGF3_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF3_EN_MASK)
83660 
83661 #define SNVS_LPTGF1CR_ETGF4_MASK                 (0x7F00U)
83662 #define SNVS_LPTGF1CR_ETGF4_SHIFT                (8U)
83663 #define SNVS_LPTGF1CR_ETGF4(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_SHIFT)) & SNVS_LPTGF1CR_ETGF4_MASK)
83664 
83665 #define SNVS_LPTGF1CR_ETGF4_EN_MASK              (0x8000U)
83666 #define SNVS_LPTGF1CR_ETGF4_EN_SHIFT             (15U)
83667 /*! ETGF4_EN
83668  *  0b0..External tamper glitch filter 4 is bypassed.
83669  *  0b1..External tamper glitch filter 4 is enabled.
83670  */
83671 #define SNVS_LPTGF1CR_ETGF4_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF4_EN_MASK)
83672 
83673 #define SNVS_LPTGF1CR_ETGF5_MASK                 (0x7F0000U)
83674 #define SNVS_LPTGF1CR_ETGF5_SHIFT                (16U)
83675 #define SNVS_LPTGF1CR_ETGF5(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_SHIFT)) & SNVS_LPTGF1CR_ETGF5_MASK)
83676 
83677 #define SNVS_LPTGF1CR_ETGF5_EN_MASK              (0x800000U)
83678 #define SNVS_LPTGF1CR_ETGF5_EN_SHIFT             (23U)
83679 /*! ETGF5_EN
83680  *  0b0..External tamper glitch filter 5 is bypassed.
83681  *  0b1..External tamper glitch filter 5 is enabled.
83682  */
83683 #define SNVS_LPTGF1CR_ETGF5_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF5_EN_MASK)
83684 
83685 #define SNVS_LPTGF1CR_ETGF6_MASK                 (0x7F000000U)
83686 #define SNVS_LPTGF1CR_ETGF6_SHIFT                (24U)
83687 #define SNVS_LPTGF1CR_ETGF6(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_SHIFT)) & SNVS_LPTGF1CR_ETGF6_MASK)
83688 
83689 #define SNVS_LPTGF1CR_ETGF6_EN_MASK              (0x80000000U)
83690 #define SNVS_LPTGF1CR_ETGF6_EN_SHIFT             (31U)
83691 /*! ETGF6_EN
83692  *  0b0..External tamper glitch filter 6 is bypassed.
83693  *  0b1..External tamper glitch filter 6 is enabled.
83694  */
83695 #define SNVS_LPTGF1CR_ETGF6_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF6_EN_MASK)
83696 /*! @} */
83697 
83698 /*! @name LPTGF2CR - SNVS_LP Tamper Glitch Filter 2 Configuration Register */
83699 /*! @{ */
83700 
83701 #define SNVS_LPTGF2CR_ETGF7_MASK                 (0x7FU)
83702 #define SNVS_LPTGF2CR_ETGF7_SHIFT                (0U)
83703 #define SNVS_LPTGF2CR_ETGF7(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_SHIFT)) & SNVS_LPTGF2CR_ETGF7_MASK)
83704 
83705 #define SNVS_LPTGF2CR_ETGF7_EN_MASK              (0x80U)
83706 #define SNVS_LPTGF2CR_ETGF7_EN_SHIFT             (7U)
83707 /*! ETGF7_EN
83708  *  0b0..External tamper glitch filter 7 is bypassed.
83709  *  0b1..External tamper glitch filter 7 is enabled.
83710  */
83711 #define SNVS_LPTGF2CR_ETGF7_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF7_EN_MASK)
83712 
83713 #define SNVS_LPTGF2CR_ETGF8_MASK                 (0x7F00U)
83714 #define SNVS_LPTGF2CR_ETGF8_SHIFT                (8U)
83715 #define SNVS_LPTGF2CR_ETGF8(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_SHIFT)) & SNVS_LPTGF2CR_ETGF8_MASK)
83716 
83717 #define SNVS_LPTGF2CR_ETGF8_EN_MASK              (0x8000U)
83718 #define SNVS_LPTGF2CR_ETGF8_EN_SHIFT             (15U)
83719 /*! ETGF8_EN
83720  *  0b0..External tamper glitch filter 8 is bypassed.
83721  *  0b1..External tamper glitch filter 8 is enabled.
83722  */
83723 #define SNVS_LPTGF2CR_ETGF8_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF8_EN_MASK)
83724 
83725 #define SNVS_LPTGF2CR_ETGF9_MASK                 (0x7F0000U)
83726 #define SNVS_LPTGF2CR_ETGF9_SHIFT                (16U)
83727 #define SNVS_LPTGF2CR_ETGF9(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_SHIFT)) & SNVS_LPTGF2CR_ETGF9_MASK)
83728 
83729 #define SNVS_LPTGF2CR_ETGF9_EN_MASK              (0x800000U)
83730 #define SNVS_LPTGF2CR_ETGF9_EN_SHIFT             (23U)
83731 /*! ETGF9_EN
83732  *  0b0..External tamper glitch filter 9 is bypassed.
83733  *  0b1..External tamper glitch filter 9 is enabled.
83734  */
83735 #define SNVS_LPTGF2CR_ETGF9_EN(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF9_EN_MASK)
83736 
83737 #define SNVS_LPTGF2CR_ETGF10_MASK                (0x7F000000U)
83738 #define SNVS_LPTGF2CR_ETGF10_SHIFT               (24U)
83739 #define SNVS_LPTGF2CR_ETGF10(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_SHIFT)) & SNVS_LPTGF2CR_ETGF10_MASK)
83740 
83741 #define SNVS_LPTGF2CR_ETGF10_EN_MASK             (0x80000000U)
83742 #define SNVS_LPTGF2CR_ETGF10_EN_SHIFT            (31U)
83743 /*! ETGF10_EN
83744  *  0b0..External tamper glitch filter 10 is bypassed.
83745  *  0b1..External tamper glitch filter 10 is enabled.
83746  */
83747 #define SNVS_LPTGF2CR_ETGF10_EN(x)               (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF10_EN_MASK)
83748 /*! @} */
83749 
83750 /*! @name LPATCR - SNVS_LP Active Tamper 1 Configuration Register..SNVS_LP Active Tamper 5 Configuration Register */
83751 /*! @{ */
83752 
83753 #define SNVS_LPATCR_Seed_MASK                    (0xFFFFU)
83754 #define SNVS_LPATCR_Seed_SHIFT                   (0U)
83755 #define SNVS_LPATCR_Seed(x)                      (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Seed_SHIFT)) & SNVS_LPATCR_Seed_MASK)
83756 
83757 #define SNVS_LPATCR_Polynomial_MASK              (0xFFFF0000U)
83758 #define SNVS_LPATCR_Polynomial_SHIFT             (16U)
83759 #define SNVS_LPATCR_Polynomial(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Polynomial_SHIFT)) & SNVS_LPATCR_Polynomial_MASK)
83760 /*! @} */
83761 
83762 /* The count of SNVS_LPATCR */
83763 #define SNVS_LPATCR_COUNT                        (5U)
83764 
83765 /*! @name LPATCTLR - SNVS_LP Active Tamper Control Register */
83766 /*! @{ */
83767 
83768 #define SNVS_LPATCTLR_AT1_EN_MASK                (0x1U)
83769 #define SNVS_LPATCTLR_AT1_EN_SHIFT               (0U)
83770 /*! AT1_EN
83771  *  0b0..Active Tamper 1 is disabled.
83772  *  0b1..Active Tamper 1 is enabled.
83773  */
83774 #define SNVS_LPATCTLR_AT1_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_EN_SHIFT)) & SNVS_LPATCTLR_AT1_EN_MASK)
83775 
83776 #define SNVS_LPATCTLR_AT2_EN_MASK                (0x2U)
83777 #define SNVS_LPATCTLR_AT2_EN_SHIFT               (1U)
83778 /*! AT2_EN
83779  *  0b0..Active Tamper 2 is disabled.
83780  *  0b1..Active Tamper 2 is enabled.
83781  */
83782 #define SNVS_LPATCTLR_AT2_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_EN_SHIFT)) & SNVS_LPATCTLR_AT2_EN_MASK)
83783 
83784 #define SNVS_LPATCTLR_AT3_EN_MASK                (0x4U)
83785 #define SNVS_LPATCTLR_AT3_EN_SHIFT               (2U)
83786 /*! AT3_EN
83787  *  0b0..Active Tamper 3 is disabled.
83788  *  0b1..Active Tamper 3 is enabled.
83789  */
83790 #define SNVS_LPATCTLR_AT3_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_EN_SHIFT)) & SNVS_LPATCTLR_AT3_EN_MASK)
83791 
83792 #define SNVS_LPATCTLR_AT4_EN_MASK                (0x8U)
83793 #define SNVS_LPATCTLR_AT4_EN_SHIFT               (3U)
83794 /*! AT4_EN
83795  *  0b0..Active Tamper 4 is disabled.
83796  *  0b1..Active Tamper 4 is enabled.
83797  */
83798 #define SNVS_LPATCTLR_AT4_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_EN_SHIFT)) & SNVS_LPATCTLR_AT4_EN_MASK)
83799 
83800 #define SNVS_LPATCTLR_AT5_EN_MASK                (0x10U)
83801 #define SNVS_LPATCTLR_AT5_EN_SHIFT               (4U)
83802 /*! AT5_EN
83803  *  0b0..Active Tamper 5 is disabled.
83804  *  0b1..Active Tamper 5 is enabled.
83805  */
83806 #define SNVS_LPATCTLR_AT5_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_EN_SHIFT)) & SNVS_LPATCTLR_AT5_EN_MASK)
83807 
83808 #define SNVS_LPATCTLR_AT1_PAD_EN_MASK            (0x10000U)
83809 #define SNVS_LPATCTLR_AT1_PAD_EN_SHIFT           (16U)
83810 /*! AT1_PAD_EN
83811  *  0b0..Active Tamper 1 is disabled.
83812  *  0b1..Active Tamper 1 is enabled.
83813  */
83814 #define SNVS_LPATCTLR_AT1_PAD_EN(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT1_PAD_EN_MASK)
83815 
83816 #define SNVS_LPATCTLR_AT2_PAD_EN_MASK            (0x20000U)
83817 #define SNVS_LPATCTLR_AT2_PAD_EN_SHIFT           (17U)
83818 /*! AT2_PAD_EN
83819  *  0b0..Active Tamper 2 is disabled.
83820  *  0b1..Active Tamper 2 is enabled.
83821  */
83822 #define SNVS_LPATCTLR_AT2_PAD_EN(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT2_PAD_EN_MASK)
83823 
83824 #define SNVS_LPATCTLR_AT3_PAD_EN_MASK            (0x40000U)
83825 #define SNVS_LPATCTLR_AT3_PAD_EN_SHIFT           (18U)
83826 /*! AT3_PAD_EN
83827  *  0b0..Active Tamper 3 is disabled.
83828  *  0b1..Active Tamper 3 is enabled
83829  */
83830 #define SNVS_LPATCTLR_AT3_PAD_EN(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT3_PAD_EN_MASK)
83831 
83832 #define SNVS_LPATCTLR_AT4_PAD_EN_MASK            (0x80000U)
83833 #define SNVS_LPATCTLR_AT4_PAD_EN_SHIFT           (19U)
83834 /*! AT4_PAD_EN
83835  *  0b0..Active Tamper 4 is disabled.
83836  *  0b1..Active Tamper 4 is enabled.
83837  */
83838 #define SNVS_LPATCTLR_AT4_PAD_EN(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT4_PAD_EN_MASK)
83839 
83840 #define SNVS_LPATCTLR_AT5_PAD_EN_MASK            (0x100000U)
83841 #define SNVS_LPATCTLR_AT5_PAD_EN_SHIFT           (20U)
83842 /*! AT5_PAD_EN
83843  *  0b0..Active Tamper 5 is disabled.
83844  *  0b1..Active Tamper 5 is enabled.
83845  */
83846 #define SNVS_LPATCTLR_AT5_PAD_EN(x)              (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT5_PAD_EN_MASK)
83847 /*! @} */
83848 
83849 /*! @name LPATCLKR - SNVS_LP Active Tamper Clock Control Register */
83850 /*! @{ */
83851 
83852 #define SNVS_LPATCLKR_AT1_CLK_CTL_MASK           (0x3U)
83853 #define SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT          (0U)
83854 #define SNVS_LPATCLKR_AT1_CLK_CTL(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT1_CLK_CTL_MASK)
83855 
83856 #define SNVS_LPATCLKR_AT2_CLK_CTL_MASK           (0x30U)
83857 #define SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT          (4U)
83858 #define SNVS_LPATCLKR_AT2_CLK_CTL(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT2_CLK_CTL_MASK)
83859 
83860 #define SNVS_LPATCLKR_AT3_CLK_CTL_MASK           (0x300U)
83861 #define SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT          (8U)
83862 #define SNVS_LPATCLKR_AT3_CLK_CTL(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT3_CLK_CTL_MASK)
83863 
83864 #define SNVS_LPATCLKR_AT4_CLK_CTL_MASK           (0x3000U)
83865 #define SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT          (12U)
83866 #define SNVS_LPATCLKR_AT4_CLK_CTL(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT4_CLK_CTL_MASK)
83867 
83868 #define SNVS_LPATCLKR_AT5_CLK_CTL_MASK           (0x30000U)
83869 #define SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT          (16U)
83870 #define SNVS_LPATCLKR_AT5_CLK_CTL(x)             (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT5_CLK_CTL_MASK)
83871 /*! @} */
83872 
83873 /*! @name LPATRC1R - SNVS_LP Active Tamper Routing Control 1 Register */
83874 /*! @{ */
83875 
83876 #define SNVS_LPATRC1R_ET1RCTL_MASK               (0x7U)
83877 #define SNVS_LPATRC1R_ET1RCTL_SHIFT              (0U)
83878 #define SNVS_LPATRC1R_ET1RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET1RCTL_SHIFT)) & SNVS_LPATRC1R_ET1RCTL_MASK)
83879 
83880 #define SNVS_LPATRC1R_ET2RCTL_MASK               (0x70U)
83881 #define SNVS_LPATRC1R_ET2RCTL_SHIFT              (4U)
83882 #define SNVS_LPATRC1R_ET2RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET2RCTL_SHIFT)) & SNVS_LPATRC1R_ET2RCTL_MASK)
83883 
83884 #define SNVS_LPATRC1R_ET3RCTL_MASK               (0x700U)
83885 #define SNVS_LPATRC1R_ET3RCTL_SHIFT              (8U)
83886 #define SNVS_LPATRC1R_ET3RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET3RCTL_SHIFT)) & SNVS_LPATRC1R_ET3RCTL_MASK)
83887 
83888 #define SNVS_LPATRC1R_ET4RCTL_MASK               (0x7000U)
83889 #define SNVS_LPATRC1R_ET4RCTL_SHIFT              (12U)
83890 #define SNVS_LPATRC1R_ET4RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET4RCTL_SHIFT)) & SNVS_LPATRC1R_ET4RCTL_MASK)
83891 
83892 #define SNVS_LPATRC1R_ET5RCTL_MASK               (0x70000U)
83893 #define SNVS_LPATRC1R_ET5RCTL_SHIFT              (16U)
83894 #define SNVS_LPATRC1R_ET5RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET5RCTL_SHIFT)) & SNVS_LPATRC1R_ET5RCTL_MASK)
83895 
83896 #define SNVS_LPATRC1R_ET6RCTL_MASK               (0x700000U)
83897 #define SNVS_LPATRC1R_ET6RCTL_SHIFT              (20U)
83898 #define SNVS_LPATRC1R_ET6RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET6RCTL_SHIFT)) & SNVS_LPATRC1R_ET6RCTL_MASK)
83899 
83900 #define SNVS_LPATRC1R_ET7RCTL_MASK               (0x7000000U)
83901 #define SNVS_LPATRC1R_ET7RCTL_SHIFT              (24U)
83902 #define SNVS_LPATRC1R_ET7RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET7RCTL_SHIFT)) & SNVS_LPATRC1R_ET7RCTL_MASK)
83903 
83904 #define SNVS_LPATRC1R_ET8RCTL_MASK               (0x70000000U)
83905 #define SNVS_LPATRC1R_ET8RCTL_SHIFT              (28U)
83906 #define SNVS_LPATRC1R_ET8RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET8RCTL_SHIFT)) & SNVS_LPATRC1R_ET8RCTL_MASK)
83907 /*! @} */
83908 
83909 /*! @name LPATRC2R - SNVS_LP Active Tamper Routing Control 2 Register */
83910 /*! @{ */
83911 
83912 #define SNVS_LPATRC2R_ET9RCTL_MASK               (0x7U)
83913 #define SNVS_LPATRC2R_ET9RCTL_SHIFT              (0U)
83914 #define SNVS_LPATRC2R_ET9RCTL(x)                 (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET9RCTL_SHIFT)) & SNVS_LPATRC2R_ET9RCTL_MASK)
83915 
83916 #define SNVS_LPATRC2R_ET10RCTL_MASK              (0x70U)
83917 #define SNVS_LPATRC2R_ET10RCTL_SHIFT             (4U)
83918 #define SNVS_LPATRC2R_ET10RCTL(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET10RCTL_SHIFT)) & SNVS_LPATRC2R_ET10RCTL_MASK)
83919 /*! @} */
83920 
83921 /*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */
83922 /*! @{ */
83923 
83924 #define SNVS_LPGPR_GPR_MASK                      (0xFFFFFFFFU)
83925 #define SNVS_LPGPR_GPR_SHIFT                     (0U)
83926 #define SNVS_LPGPR_GPR(x)                        (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
83927 /*! @} */
83928 
83929 /* The count of SNVS_LPGPR */
83930 #define SNVS_LPGPR_COUNT                         (4U)
83931 
83932 /*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */
83933 /*! @{ */
83934 
83935 #define SNVS_HPVIDR1_MINOR_REV_MASK              (0xFFU)
83936 #define SNVS_HPVIDR1_MINOR_REV_SHIFT             (0U)
83937 #define SNVS_HPVIDR1_MINOR_REV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
83938 
83939 #define SNVS_HPVIDR1_MAJOR_REV_MASK              (0xFF00U)
83940 #define SNVS_HPVIDR1_MAJOR_REV_SHIFT             (8U)
83941 #define SNVS_HPVIDR1_MAJOR_REV(x)                (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
83942 
83943 #define SNVS_HPVIDR1_IP_ID_MASK                  (0xFFFF0000U)
83944 #define SNVS_HPVIDR1_IP_ID_SHIFT                 (16U)
83945 #define SNVS_HPVIDR1_IP_ID(x)                    (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
83946 /*! @} */
83947 
83948 /*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */
83949 /*! @{ */
83950 
83951 #define SNVS_HPVIDR2_ECO_REV_MASK                (0xFF00U)
83952 #define SNVS_HPVIDR2_ECO_REV_SHIFT               (8U)
83953 #define SNVS_HPVIDR2_ECO_REV(x)                  (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
83954 
83955 #define SNVS_HPVIDR2_IP_ERA_MASK                 (0xFF000000U)
83956 #define SNVS_HPVIDR2_IP_ERA_SHIFT                (24U)
83957 #define SNVS_HPVIDR2_IP_ERA(x)                   (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
83958 /*! @} */
83959 
83960 
83961 /*!
83962  * @}
83963  */ /* end of group SNVS_Register_Masks */
83964 
83965 
83966 /* SNVS - Peripheral instance base addresses */
83967 /** Peripheral SNVS base address */
83968 #define SNVS_BASE                                (0x40C90000u)
83969 /** Peripheral SNVS base pointer */
83970 #define SNVS                                     ((SNVS_Type *)SNVS_BASE)
83971 /** Array initializer of SNVS peripheral base addresses */
83972 #define SNVS_BASE_ADDRS                          { SNVS_BASE }
83973 /** Array initializer of SNVS peripheral base pointers */
83974 #define SNVS_BASE_PTRS                           { SNVS }
83975 /** Interrupt vectors for the SNVS peripheral type */
83976 #define SNVS_IRQS                                { SNVS_PULSE_EVENT_IRQn }
83977 #define SNVS_CONSOLIDATED_IRQS                   { SNVS_HP_NON_TZ_IRQn }
83978 #define SNVS_SECURITY_IRQS                       { SNVS_HP_TZ_IRQn }
83979 
83980 /*!
83981  * @}
83982  */ /* end of group SNVS_Peripheral_Access_Layer */
83983 
83984 
83985 /* ----------------------------------------------------------------------------
83986    -- SPDIF Peripheral Access Layer
83987    ---------------------------------------------------------------------------- */
83988 
83989 /*!
83990  * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
83991  * @{
83992  */
83993 
83994 /** SPDIF - Register Layout Typedef */
83995 typedef struct {
83996   __IO uint32_t SCR;                               /**< SPDIF Configuration Register, offset: 0x0 */
83997   __IO uint32_t SRCD;                              /**< CDText Control Register, offset: 0x4 */
83998   __IO uint32_t SRPC;                              /**< PhaseConfig Register, offset: 0x8 */
83999   __IO uint32_t SIE;                               /**< InterruptEn Register, offset: 0xC */
84000   union {                                          /* offset: 0x10 */
84001     __O  uint32_t SIC;                               /**< InterruptClear Register, offset: 0x10 */
84002     __I  uint32_t SIS;                               /**< InterruptStat Register, offset: 0x10 */
84003   };
84004   __I  uint32_t SRL;                               /**< SPDIFRxLeft Register, offset: 0x14 */
84005   __I  uint32_t SRR;                               /**< SPDIFRxRight Register, offset: 0x18 */
84006   __I  uint32_t SRCSH;                             /**< SPDIFRxCChannel_h Register, offset: 0x1C */
84007   __I  uint32_t SRCSL;                             /**< SPDIFRxCChannel_l Register, offset: 0x20 */
84008   __I  uint32_t SRU;                               /**< UchannelRx Register, offset: 0x24 */
84009   __I  uint32_t SRQ;                               /**< QchannelRx Register, offset: 0x28 */
84010   __O  uint32_t STL;                               /**< SPDIFTxLeft Register, offset: 0x2C */
84011   __O  uint32_t STR;                               /**< SPDIFTxRight Register, offset: 0x30 */
84012   __IO uint32_t STCSCH;                            /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */
84013   __IO uint32_t STCSCL;                            /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */
84014        uint8_t RESERVED_0[8];
84015   __I  uint32_t SRFM;                              /**< FreqMeas Register, offset: 0x44 */
84016        uint8_t RESERVED_1[8];
84017   __IO uint32_t STC;                               /**< SPDIFTxClk Register, offset: 0x50 */
84018 } SPDIF_Type;
84019 
84020 /* ----------------------------------------------------------------------------
84021    -- SPDIF Register Masks
84022    ---------------------------------------------------------------------------- */
84023 
84024 /*!
84025  * @addtogroup SPDIF_Register_Masks SPDIF Register Masks
84026  * @{
84027  */
84028 
84029 /*! @name SCR - SPDIF Configuration Register */
84030 /*! @{ */
84031 
84032 #define SPDIF_SCR_USRC_SEL_MASK                  (0x3U)
84033 #define SPDIF_SCR_USRC_SEL_SHIFT                 (0U)
84034 /*! USrc_Sel - USrc_Sel
84035  *  0b00..No embedded U channel
84036  *  0b01..U channel from SPDIF receive block (CD mode)
84037  *  0b10..Reserved
84038  *  0b11..U channel from on chip transmitter
84039  */
84040 #define SPDIF_SCR_USRC_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
84041 
84042 #define SPDIF_SCR_TXSEL_MASK                     (0x1CU)
84043 #define SPDIF_SCR_TXSEL_SHIFT                    (2U)
84044 /*! TxSel - TxSel
84045  *  0b000..Off and output 0
84046  *  0b001..Feed-through SPDIFIN
84047  *  0b101..Tx Normal operation
84048  */
84049 #define SPDIF_SCR_TXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
84050 
84051 #define SPDIF_SCR_VALCTRL_MASK                   (0x20U)
84052 #define SPDIF_SCR_VALCTRL_SHIFT                  (5U)
84053 /*! ValCtrl - ValCtrl
84054  *  0b0..Outgoing Validity always set
84055  *  0b1..Outgoing Validity always clear
84056  */
84057 #define SPDIF_SCR_VALCTRL(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
84058 
84059 #define SPDIF_SCR_INPUTSRCSEL_MASK               (0xC0U)
84060 #define SPDIF_SCR_INPUTSRCSEL_SHIFT              (6U)
84061 /*! InputSrcSel - InputSrcSel
84062  *  0b00..SPDIF_IN
84063  *  0b01-0b11..None
84064  */
84065 #define SPDIF_SCR_INPUTSRCSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_INPUTSRCSEL_SHIFT)) & SPDIF_SCR_INPUTSRCSEL_MASK)
84066 
84067 #define SPDIF_SCR_DMA_TX_EN_MASK                 (0x100U)
84068 #define SPDIF_SCR_DMA_TX_EN_SHIFT                (8U)
84069 /*! DMA_TX_En - DMA_TX_En */
84070 #define SPDIF_SCR_DMA_TX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
84071 
84072 #define SPDIF_SCR_DMA_RX_EN_MASK                 (0x200U)
84073 #define SPDIF_SCR_DMA_RX_EN_SHIFT                (9U)
84074 /*! DMA_Rx_En - DMA_Rx_En */
84075 #define SPDIF_SCR_DMA_RX_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
84076 
84077 #define SPDIF_SCR_TXFIFO_CTRL_MASK               (0xC00U)
84078 #define SPDIF_SCR_TXFIFO_CTRL_SHIFT              (10U)
84079 /*! TxFIFO_Ctrl - TxFIFO_Ctrl
84080  *  0b00..Send out digital zero on SPDIF Tx
84081  *  0b01..Tx Normal operation
84082  *  0b10..Reset to 1 sample remaining
84083  *  0b11..Reserved
84084  */
84085 #define SPDIF_SCR_TXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
84086 
84087 #define SPDIF_SCR_SOFT_RESET_MASK                (0x1000U)
84088 #define SPDIF_SCR_SOFT_RESET_SHIFT               (12U)
84089 /*! soft_reset - soft_reset */
84090 #define SPDIF_SCR_SOFT_RESET(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
84091 
84092 #define SPDIF_SCR_LOW_POWER_MASK                 (0x2000U)
84093 #define SPDIF_SCR_LOW_POWER_SHIFT                (13U)
84094 /*! LOW_POWER - LOW_POWER */
84095 #define SPDIF_SCR_LOW_POWER(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
84096 
84097 #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK           (0x18000U)
84098 #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT          (15U)
84099 /*! TxFIFOEmpty_Sel - TxFIFOEmpty_Sel
84100  *  0b00..Empty interrupt if 0 sample in Tx left and right FIFOs
84101  *  0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs
84102  *  0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs
84103  *  0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs
84104  */
84105 #define SPDIF_SCR_TXFIFOEMPTY_SEL(x)             (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
84106 
84107 #define SPDIF_SCR_TXAUTOSYNC_MASK                (0x20000U)
84108 #define SPDIF_SCR_TXAUTOSYNC_SHIFT               (17U)
84109 /*! TxAutoSync - TxAutoSync
84110  *  0b0..Tx FIFO auto sync off
84111  *  0b1..Tx FIFO auto sync on
84112  */
84113 #define SPDIF_SCR_TXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
84114 
84115 #define SPDIF_SCR_RXAUTOSYNC_MASK                (0x40000U)
84116 #define SPDIF_SCR_RXAUTOSYNC_SHIFT               (18U)
84117 /*! RxAutoSync - RxAutoSync
84118  *  0b0..Rx FIFO auto sync off
84119  *  0b1..RxFIFO auto sync on
84120  */
84121 #define SPDIF_SCR_RXAUTOSYNC(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
84122 
84123 #define SPDIF_SCR_RXFIFOFULL_SEL_MASK            (0x180000U)
84124 #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT           (19U)
84125 /*! RxFIFOFull_Sel - RxFIFOFull_Sel
84126  *  0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs
84127  *  0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs
84128  *  0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs
84129  *  0b11..Full interrupt if at least 16 sample in Rx left and right FIFO
84130  */
84131 #define SPDIF_SCR_RXFIFOFULL_SEL(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
84132 
84133 #define SPDIF_SCR_RXFIFO_RST_MASK                (0x200000U)
84134 #define SPDIF_SCR_RXFIFO_RST_SHIFT               (21U)
84135 /*! RxFIFO_Rst - RxFIFO_Rst
84136  *  0b0..Normal operation
84137  *  0b1..Reset register to 1 sample remaining
84138  */
84139 #define SPDIF_SCR_RXFIFO_RST(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
84140 
84141 #define SPDIF_SCR_RXFIFO_OFF_ON_MASK             (0x400000U)
84142 #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT            (22U)
84143 /*! RxFIFO_Off_On - RxFIFO_Off_On
84144  *  0b0..SPDIF Rx FIFO is on
84145  *  0b1..SPDIF Rx FIFO is off. Does not accept data from interface
84146  */
84147 #define SPDIF_SCR_RXFIFO_OFF_ON(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
84148 
84149 #define SPDIF_SCR_RXFIFO_CTRL_MASK               (0x800000U)
84150 #define SPDIF_SCR_RXFIFO_CTRL_SHIFT              (23U)
84151 /*! RxFIFO_Ctrl - RxFIFO_Ctrl
84152  *  0b0..Normal operation
84153  *  0b1..Always read zero from Rx data register
84154  */
84155 #define SPDIF_SCR_RXFIFO_CTRL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
84156 /*! @} */
84157 
84158 /*! @name SRCD - CDText Control Register */
84159 /*! @{ */
84160 
84161 #define SPDIF_SRCD_USYNCMODE_MASK                (0x2U)
84162 #define SPDIF_SRCD_USYNCMODE_SHIFT               (1U)
84163 /*! USyncMode - USyncMode
84164  *  0b0..Non-CD data
84165  *  0b1..CD user channel subcode
84166  */
84167 #define SPDIF_SRCD_USYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
84168 /*! @} */
84169 
84170 /*! @name SRPC - PhaseConfig Register */
84171 /*! @{ */
84172 
84173 #define SPDIF_SRPC_GAINSEL_MASK                  (0x38U)
84174 #define SPDIF_SRPC_GAINSEL_SHIFT                 (3U)
84175 /*! GainSel - GainSel
84176  *  0b000..24*(2**10)
84177  *  0b001..16*(2**10)
84178  *  0b010..12*(2**10)
84179  *  0b011..8*(2**10)
84180  *  0b100..6*(2**10)
84181  *  0b101..4*(2**10)
84182  *  0b110..3*(2**10)
84183  */
84184 #define SPDIF_SRPC_GAINSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
84185 
84186 #define SPDIF_SRPC_LOCK_MASK                     (0x40U)
84187 #define SPDIF_SRPC_LOCK_SHIFT                    (6U)
84188 /*! LOCK - LOCK */
84189 #define SPDIF_SRPC_LOCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
84190 
84191 #define SPDIF_SRPC_CLKSRC_SEL_MASK               (0x780U)
84192 #define SPDIF_SRPC_CLKSRC_SEL_SHIFT              (7U)
84193 /*! ClkSrc_Sel - ClkSrc_Sel
84194  *  0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)
84195  *  0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)
84196  *  0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK
84197  *  0b0101..REF_CLK_32K (XTALOSC)
84198  *  0b0110..tx_clk (SPDIF0_CLK_ROOT)
84199  *  0b1000..SPDIF_EXT_CLK
84200  */
84201 #define SPDIF_SRPC_CLKSRC_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
84202 /*! @} */
84203 
84204 /*! @name SIE - InterruptEn Register */
84205 /*! @{ */
84206 
84207 #define SPDIF_SIE_RXFIFOFUL_MASK                 (0x1U)
84208 #define SPDIF_SIE_RXFIFOFUL_SHIFT                (0U)
84209 /*! RxFIFOFul - RxFIFOFul */
84210 #define SPDIF_SIE_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
84211 
84212 #define SPDIF_SIE_TXEM_MASK                      (0x2U)
84213 #define SPDIF_SIE_TXEM_SHIFT                     (1U)
84214 /*! TxEm - TxEm */
84215 #define SPDIF_SIE_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
84216 
84217 #define SPDIF_SIE_LOCKLOSS_MASK                  (0x4U)
84218 #define SPDIF_SIE_LOCKLOSS_SHIFT                 (2U)
84219 /*! LockLoss - LockLoss */
84220 #define SPDIF_SIE_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
84221 
84222 #define SPDIF_SIE_RXFIFORESYN_MASK               (0x8U)
84223 #define SPDIF_SIE_RXFIFORESYN_SHIFT              (3U)
84224 /*! RxFIFOResyn - RxFIFOResyn */
84225 #define SPDIF_SIE_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
84226 
84227 #define SPDIF_SIE_RXFIFOUNOV_MASK                (0x10U)
84228 #define SPDIF_SIE_RXFIFOUNOV_SHIFT               (4U)
84229 /*! RxFIFOUnOv - RxFIFOUnOv */
84230 #define SPDIF_SIE_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
84231 
84232 #define SPDIF_SIE_UQERR_MASK                     (0x20U)
84233 #define SPDIF_SIE_UQERR_SHIFT                    (5U)
84234 /*! UQErr - UQErr */
84235 #define SPDIF_SIE_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
84236 
84237 #define SPDIF_SIE_UQSYNC_MASK                    (0x40U)
84238 #define SPDIF_SIE_UQSYNC_SHIFT                   (6U)
84239 /*! UQSync - UQSync */
84240 #define SPDIF_SIE_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
84241 
84242 #define SPDIF_SIE_QRXOV_MASK                     (0x80U)
84243 #define SPDIF_SIE_QRXOV_SHIFT                    (7U)
84244 /*! QRxOv - QRxOv */
84245 #define SPDIF_SIE_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
84246 
84247 #define SPDIF_SIE_QRXFUL_MASK                    (0x100U)
84248 #define SPDIF_SIE_QRXFUL_SHIFT                   (8U)
84249 /*! QRxFul - QRxFul */
84250 #define SPDIF_SIE_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
84251 
84252 #define SPDIF_SIE_URXOV_MASK                     (0x200U)
84253 #define SPDIF_SIE_URXOV_SHIFT                    (9U)
84254 /*! URxOv - URxOv */
84255 #define SPDIF_SIE_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
84256 
84257 #define SPDIF_SIE_URXFUL_MASK                    (0x400U)
84258 #define SPDIF_SIE_URXFUL_SHIFT                   (10U)
84259 /*! URxFul - URxFul */
84260 #define SPDIF_SIE_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
84261 
84262 #define SPDIF_SIE_BITERR_MASK                    (0x4000U)
84263 #define SPDIF_SIE_BITERR_SHIFT                   (14U)
84264 /*! BitErr - BitErr */
84265 #define SPDIF_SIE_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
84266 
84267 #define SPDIF_SIE_SYMERR_MASK                    (0x8000U)
84268 #define SPDIF_SIE_SYMERR_SHIFT                   (15U)
84269 /*! SymErr - SymErr */
84270 #define SPDIF_SIE_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
84271 
84272 #define SPDIF_SIE_VALNOGOOD_MASK                 (0x10000U)
84273 #define SPDIF_SIE_VALNOGOOD_SHIFT                (16U)
84274 /*! ValNoGood - ValNoGood */
84275 #define SPDIF_SIE_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
84276 
84277 #define SPDIF_SIE_CNEW_MASK                      (0x20000U)
84278 #define SPDIF_SIE_CNEW_SHIFT                     (17U)
84279 /*! CNew - CNew */
84280 #define SPDIF_SIE_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
84281 
84282 #define SPDIF_SIE_TXRESYN_MASK                   (0x40000U)
84283 #define SPDIF_SIE_TXRESYN_SHIFT                  (18U)
84284 /*! TxResyn - TxResyn */
84285 #define SPDIF_SIE_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
84286 
84287 #define SPDIF_SIE_TXUNOV_MASK                    (0x80000U)
84288 #define SPDIF_SIE_TXUNOV_SHIFT                   (19U)
84289 /*! TxUnOv - TxUnOv */
84290 #define SPDIF_SIE_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
84291 
84292 #define SPDIF_SIE_LOCK_MASK                      (0x100000U)
84293 #define SPDIF_SIE_LOCK_SHIFT                     (20U)
84294 /*! Lock - Lock */
84295 #define SPDIF_SIE_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
84296 /*! @} */
84297 
84298 /*! @name SIC - InterruptClear Register */
84299 /*! @{ */
84300 
84301 #define SPDIF_SIC_LOCKLOSS_MASK                  (0x4U)
84302 #define SPDIF_SIC_LOCKLOSS_SHIFT                 (2U)
84303 /*! LockLoss - LockLoss */
84304 #define SPDIF_SIC_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
84305 
84306 #define SPDIF_SIC_RXFIFORESYN_MASK               (0x8U)
84307 #define SPDIF_SIC_RXFIFORESYN_SHIFT              (3U)
84308 /*! RxFIFOResyn - RxFIFOResyn */
84309 #define SPDIF_SIC_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
84310 
84311 #define SPDIF_SIC_RXFIFOUNOV_MASK                (0x10U)
84312 #define SPDIF_SIC_RXFIFOUNOV_SHIFT               (4U)
84313 /*! RxFIFOUnOv - RxFIFOUnOv */
84314 #define SPDIF_SIC_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
84315 
84316 #define SPDIF_SIC_UQERR_MASK                     (0x20U)
84317 #define SPDIF_SIC_UQERR_SHIFT                    (5U)
84318 /*! UQErr - UQErr */
84319 #define SPDIF_SIC_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
84320 
84321 #define SPDIF_SIC_UQSYNC_MASK                    (0x40U)
84322 #define SPDIF_SIC_UQSYNC_SHIFT                   (6U)
84323 /*! UQSync - UQSync */
84324 #define SPDIF_SIC_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
84325 
84326 #define SPDIF_SIC_QRXOV_MASK                     (0x80U)
84327 #define SPDIF_SIC_QRXOV_SHIFT                    (7U)
84328 /*! QRxOv - QRxOv */
84329 #define SPDIF_SIC_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
84330 
84331 #define SPDIF_SIC_URXOV_MASK                     (0x200U)
84332 #define SPDIF_SIC_URXOV_SHIFT                    (9U)
84333 /*! URxOv - URxOv */
84334 #define SPDIF_SIC_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
84335 
84336 #define SPDIF_SIC_BITERR_MASK                    (0x4000U)
84337 #define SPDIF_SIC_BITERR_SHIFT                   (14U)
84338 /*! BitErr - BitErr */
84339 #define SPDIF_SIC_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
84340 
84341 #define SPDIF_SIC_SYMERR_MASK                    (0x8000U)
84342 #define SPDIF_SIC_SYMERR_SHIFT                   (15U)
84343 /*! SymErr - SymErr */
84344 #define SPDIF_SIC_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
84345 
84346 #define SPDIF_SIC_VALNOGOOD_MASK                 (0x10000U)
84347 #define SPDIF_SIC_VALNOGOOD_SHIFT                (16U)
84348 /*! ValNoGood - ValNoGood */
84349 #define SPDIF_SIC_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
84350 
84351 #define SPDIF_SIC_CNEW_MASK                      (0x20000U)
84352 #define SPDIF_SIC_CNEW_SHIFT                     (17U)
84353 /*! CNew - CNew */
84354 #define SPDIF_SIC_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
84355 
84356 #define SPDIF_SIC_TXRESYN_MASK                   (0x40000U)
84357 #define SPDIF_SIC_TXRESYN_SHIFT                  (18U)
84358 /*! TxResyn - TxResyn */
84359 #define SPDIF_SIC_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
84360 
84361 #define SPDIF_SIC_TXUNOV_MASK                    (0x80000U)
84362 #define SPDIF_SIC_TXUNOV_SHIFT                   (19U)
84363 /*! TxUnOv - TxUnOv */
84364 #define SPDIF_SIC_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
84365 
84366 #define SPDIF_SIC_LOCK_MASK                      (0x100000U)
84367 #define SPDIF_SIC_LOCK_SHIFT                     (20U)
84368 /*! Lock - Lock */
84369 #define SPDIF_SIC_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
84370 /*! @} */
84371 
84372 /*! @name SIS - InterruptStat Register */
84373 /*! @{ */
84374 
84375 #define SPDIF_SIS_RXFIFOFUL_MASK                 (0x1U)
84376 #define SPDIF_SIS_RXFIFOFUL_SHIFT                (0U)
84377 /*! RxFIFOFul - RxFIFOFul */
84378 #define SPDIF_SIS_RXFIFOFUL(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
84379 
84380 #define SPDIF_SIS_TXEM_MASK                      (0x2U)
84381 #define SPDIF_SIS_TXEM_SHIFT                     (1U)
84382 /*! TxEm - TxEm */
84383 #define SPDIF_SIS_TXEM(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
84384 
84385 #define SPDIF_SIS_LOCKLOSS_MASK                  (0x4U)
84386 #define SPDIF_SIS_LOCKLOSS_SHIFT                 (2U)
84387 /*! LockLoss - LockLoss */
84388 #define SPDIF_SIS_LOCKLOSS(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
84389 
84390 #define SPDIF_SIS_RXFIFORESYN_MASK               (0x8U)
84391 #define SPDIF_SIS_RXFIFORESYN_SHIFT              (3U)
84392 /*! RxFIFOResyn - RxFIFOResyn */
84393 #define SPDIF_SIS_RXFIFORESYN(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
84394 
84395 #define SPDIF_SIS_RXFIFOUNOV_MASK                (0x10U)
84396 #define SPDIF_SIS_RXFIFOUNOV_SHIFT               (4U)
84397 /*! RxFIFOUnOv - RxFIFOUnOv */
84398 #define SPDIF_SIS_RXFIFOUNOV(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
84399 
84400 #define SPDIF_SIS_UQERR_MASK                     (0x20U)
84401 #define SPDIF_SIS_UQERR_SHIFT                    (5U)
84402 /*! UQErr - UQErr */
84403 #define SPDIF_SIS_UQERR(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
84404 
84405 #define SPDIF_SIS_UQSYNC_MASK                    (0x40U)
84406 #define SPDIF_SIS_UQSYNC_SHIFT                   (6U)
84407 /*! UQSync - UQSync */
84408 #define SPDIF_SIS_UQSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
84409 
84410 #define SPDIF_SIS_QRXOV_MASK                     (0x80U)
84411 #define SPDIF_SIS_QRXOV_SHIFT                    (7U)
84412 /*! QRxOv - QRxOv */
84413 #define SPDIF_SIS_QRXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
84414 
84415 #define SPDIF_SIS_QRXFUL_MASK                    (0x100U)
84416 #define SPDIF_SIS_QRXFUL_SHIFT                   (8U)
84417 /*! QRxFul - QRxFul */
84418 #define SPDIF_SIS_QRXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
84419 
84420 #define SPDIF_SIS_URXOV_MASK                     (0x200U)
84421 #define SPDIF_SIS_URXOV_SHIFT                    (9U)
84422 /*! URxOv - URxOv */
84423 #define SPDIF_SIS_URXOV(x)                       (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
84424 
84425 #define SPDIF_SIS_URXFUL_MASK                    (0x400U)
84426 #define SPDIF_SIS_URXFUL_SHIFT                   (10U)
84427 /*! URxFul - URxFul */
84428 #define SPDIF_SIS_URXFUL(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
84429 
84430 #define SPDIF_SIS_BITERR_MASK                    (0x4000U)
84431 #define SPDIF_SIS_BITERR_SHIFT                   (14U)
84432 /*! BitErr - BitErr */
84433 #define SPDIF_SIS_BITERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
84434 
84435 #define SPDIF_SIS_SYMERR_MASK                    (0x8000U)
84436 #define SPDIF_SIS_SYMERR_SHIFT                   (15U)
84437 /*! SymErr - SymErr */
84438 #define SPDIF_SIS_SYMERR(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
84439 
84440 #define SPDIF_SIS_VALNOGOOD_MASK                 (0x10000U)
84441 #define SPDIF_SIS_VALNOGOOD_SHIFT                (16U)
84442 /*! ValNoGood - ValNoGood */
84443 #define SPDIF_SIS_VALNOGOOD(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
84444 
84445 #define SPDIF_SIS_CNEW_MASK                      (0x20000U)
84446 #define SPDIF_SIS_CNEW_SHIFT                     (17U)
84447 /*! CNew - CNew */
84448 #define SPDIF_SIS_CNEW(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
84449 
84450 #define SPDIF_SIS_TXRESYN_MASK                   (0x40000U)
84451 #define SPDIF_SIS_TXRESYN_SHIFT                  (18U)
84452 /*! TxResyn - TxResyn */
84453 #define SPDIF_SIS_TXRESYN(x)                     (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
84454 
84455 #define SPDIF_SIS_TXUNOV_MASK                    (0x80000U)
84456 #define SPDIF_SIS_TXUNOV_SHIFT                   (19U)
84457 /*! TxUnOv - TxUnOv */
84458 #define SPDIF_SIS_TXUNOV(x)                      (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
84459 
84460 #define SPDIF_SIS_LOCK_MASK                      (0x100000U)
84461 #define SPDIF_SIS_LOCK_SHIFT                     (20U)
84462 /*! Lock - Lock */
84463 #define SPDIF_SIS_LOCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
84464 /*! @} */
84465 
84466 /*! @name SRL - SPDIFRxLeft Register */
84467 /*! @{ */
84468 
84469 #define SPDIF_SRL_RXDATALEFT_MASK                (0xFFFFFFU)
84470 #define SPDIF_SRL_RXDATALEFT_SHIFT               (0U)
84471 /*! RxDataLeft - RxDataLeft */
84472 #define SPDIF_SRL_RXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
84473 /*! @} */
84474 
84475 /*! @name SRR - SPDIFRxRight Register */
84476 /*! @{ */
84477 
84478 #define SPDIF_SRR_RXDATARIGHT_MASK               (0xFFFFFFU)
84479 #define SPDIF_SRR_RXDATARIGHT_SHIFT              (0U)
84480 /*! RxDataRight - RxDataRight */
84481 #define SPDIF_SRR_RXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
84482 /*! @} */
84483 
84484 /*! @name SRCSH - SPDIFRxCChannel_h Register */
84485 /*! @{ */
84486 
84487 #define SPDIF_SRCSH_RXCCHANNEL_H_MASK            (0xFFFFFFU)
84488 #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT           (0U)
84489 /*! RxCChannel_h - RxCChannel_h */
84490 #define SPDIF_SRCSH_RXCCHANNEL_H(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
84491 /*! @} */
84492 
84493 /*! @name SRCSL - SPDIFRxCChannel_l Register */
84494 /*! @{ */
84495 
84496 #define SPDIF_SRCSL_RXCCHANNEL_L_MASK            (0xFFFFFFU)
84497 #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT           (0U)
84498 /*! RxCChannel_l - RxCChannel_l */
84499 #define SPDIF_SRCSL_RXCCHANNEL_L(x)              (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
84500 /*! @} */
84501 
84502 /*! @name SRU - UchannelRx Register */
84503 /*! @{ */
84504 
84505 #define SPDIF_SRU_RXUCHANNEL_MASK                (0xFFFFFFU)
84506 #define SPDIF_SRU_RXUCHANNEL_SHIFT               (0U)
84507 /*! RxUChannel - RxUChannel */
84508 #define SPDIF_SRU_RXUCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
84509 /*! @} */
84510 
84511 /*! @name SRQ - QchannelRx Register */
84512 /*! @{ */
84513 
84514 #define SPDIF_SRQ_RXQCHANNEL_MASK                (0xFFFFFFU)
84515 #define SPDIF_SRQ_RXQCHANNEL_SHIFT               (0U)
84516 /*! RxQChannel - RxQChannel */
84517 #define SPDIF_SRQ_RXQCHANNEL(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
84518 /*! @} */
84519 
84520 /*! @name STL - SPDIFTxLeft Register */
84521 /*! @{ */
84522 
84523 #define SPDIF_STL_TXDATALEFT_MASK                (0xFFFFFFU)
84524 #define SPDIF_STL_TXDATALEFT_SHIFT               (0U)
84525 /*! TxDataLeft - TxDataLeft */
84526 #define SPDIF_STL_TXDATALEFT(x)                  (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
84527 /*! @} */
84528 
84529 /*! @name STR - SPDIFTxRight Register */
84530 /*! @{ */
84531 
84532 #define SPDIF_STR_TXDATARIGHT_MASK               (0xFFFFFFU)
84533 #define SPDIF_STR_TXDATARIGHT_SHIFT              (0U)
84534 /*! TxDataRight - TxDataRight */
84535 #define SPDIF_STR_TXDATARIGHT(x)                 (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
84536 /*! @} */
84537 
84538 /*! @name STCSCH - SPDIFTxCChannelCons_h Register */
84539 /*! @{ */
84540 
84541 #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK       (0xFFFFFFU)
84542 #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT      (0U)
84543 /*! TxCChannelCons_h - TxCChannelCons_h */
84544 #define SPDIF_STCSCH_TXCCHANNELCONS_H(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
84545 /*! @} */
84546 
84547 /*! @name STCSCL - SPDIFTxCChannelCons_l Register */
84548 /*! @{ */
84549 
84550 #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK       (0xFFFFFFU)
84551 #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT      (0U)
84552 /*! TxCChannelCons_l - TxCChannelCons_l */
84553 #define SPDIF_STCSCL_TXCCHANNELCONS_L(x)         (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
84554 /*! @} */
84555 
84556 /*! @name SRFM - FreqMeas Register */
84557 /*! @{ */
84558 
84559 #define SPDIF_SRFM_FREQMEAS_MASK                 (0xFFFFFFU)
84560 #define SPDIF_SRFM_FREQMEAS_SHIFT                (0U)
84561 /*! FreqMeas - FreqMeas */
84562 #define SPDIF_SRFM_FREQMEAS(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
84563 /*! @} */
84564 
84565 /*! @name STC - SPDIFTxClk Register */
84566 /*! @{ */
84567 
84568 #define SPDIF_STC_TXCLK_DF_MASK                  (0x7FU)
84569 #define SPDIF_STC_TXCLK_DF_SHIFT                 (0U)
84570 /*! TxClk_DF - TxClk_DF
84571  *  0b0000000..divider factor is 1
84572  *  0b0000001..divider factor is 2
84573  *  0b1111111..divider factor is 128
84574  */
84575 #define SPDIF_STC_TXCLK_DF(x)                    (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
84576 
84577 #define SPDIF_STC_TX_ALL_CLK_EN_MASK             (0x80U)
84578 #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT            (7U)
84579 /*! tx_all_clk_en - tx_all_clk_en
84580  *  0b0..disable transfer clock.
84581  *  0b1..enable transfer clock.
84582  */
84583 #define SPDIF_STC_TX_ALL_CLK_EN(x)               (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
84584 
84585 #define SPDIF_STC_TXCLK_SOURCE_MASK              (0x700U)
84586 #define SPDIF_STC_TXCLK_SOURCE_SHIFT             (8U)
84587 /*! TxClk_Source - TxClk_Source
84588  *  0b000..REF_CLK_32K input (XTALOSC 32 kHz clock)
84589  *  0b001..tx_clk input (from SPDIF0_CLK_ROOT. See clock control block for more information.)
84590  *  0b011..SPDIF_EXT_CLK, from pads
84591  *  0b101..ipg_clk input (frequency divided)
84592  */
84593 #define SPDIF_STC_TXCLK_SOURCE(x)                (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
84594 
84595 #define SPDIF_STC_SYSCLK_DF_MASK                 (0xFF800U)
84596 #define SPDIF_STC_SYSCLK_DF_SHIFT                (11U)
84597 /*! SYSCLK_DF - SYSCLK_DF
84598  *  0b000000000..no clock signal
84599  *  0b000000001..divider factor is 2
84600  *  0b111111111..divider factor is 512
84601  */
84602 #define SPDIF_STC_SYSCLK_DF(x)                   (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
84603 /*! @} */
84604 
84605 
84606 /*!
84607  * @}
84608  */ /* end of group SPDIF_Register_Masks */
84609 
84610 
84611 /* SPDIF - Peripheral instance base addresses */
84612 /** Peripheral SPDIF base address */
84613 #define SPDIF_BASE                               (0x40400000u)
84614 /** Peripheral SPDIF base pointer */
84615 #define SPDIF                                    ((SPDIF_Type *)SPDIF_BASE)
84616 /** Array initializer of SPDIF peripheral base addresses */
84617 #define SPDIF_BASE_ADDRS                         { SPDIF_BASE }
84618 /** Array initializer of SPDIF peripheral base pointers */
84619 #define SPDIF_BASE_PTRS                          { SPDIF }
84620 /** Interrupt vectors for the SPDIF peripheral type */
84621 #define SPDIF_IRQS                               { SPDIF_IRQn }
84622 
84623 /*!
84624  * @}
84625  */ /* end of group SPDIF_Peripheral_Access_Layer */
84626 
84627 
84628 /* ----------------------------------------------------------------------------
84629    -- SRAM Peripheral Access Layer
84630    ---------------------------------------------------------------------------- */
84631 
84632 /*!
84633  * @addtogroup SRAM_Peripheral_Access_Layer SRAM Peripheral Access Layer
84634  * @{
84635  */
84636 
84637 /** SRAM - Register Layout Typedef */
84638 typedef struct {
84639        uint8_t RESERVED_0[12288];
84640   __IO uint32_t CTRL;                              /**< Control Register, offset: 0x3000 */
84641 } SRAM_Type;
84642 
84643 /* ----------------------------------------------------------------------------
84644    -- SRAM Register Masks
84645    ---------------------------------------------------------------------------- */
84646 
84647 /*!
84648  * @addtogroup SRAM_Register_Masks SRAM Register Masks
84649  * @{
84650  */
84651 
84652 /*! @name CTRL - Control Register */
84653 /*! @{ */
84654 
84655 #define SRAM_CTRL_RAM_RD_EN_MASK                 (0x1U)
84656 #define SRAM_CTRL_RAM_RD_EN_SHIFT                (0U)
84657 /*! RAM_RD_EN - RAM Read Enable (with lock)
84658  *  0b0..Disable read access
84659  *  0b1..Enable read access
84660  */
84661 #define SRAM_CTRL_RAM_RD_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_RD_EN_SHIFT)) & SRAM_CTRL_RAM_RD_EN_MASK)
84662 
84663 #define SRAM_CTRL_RAM_WR_EN_MASK                 (0x2U)
84664 #define SRAM_CTRL_RAM_WR_EN_SHIFT                (1U)
84665 /*! RAM_WR_EN - RAM Write Enable (with lock)
84666  *  0b0..Disable write access
84667  *  0b1..Enable write access
84668  */
84669 #define SRAM_CTRL_RAM_WR_EN(x)                   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_WR_EN_SHIFT)) & SRAM_CTRL_RAM_WR_EN_MASK)
84670 
84671 #define SRAM_CTRL_PWR_EN_MASK                    (0x3CU)
84672 #define SRAM_CTRL_PWR_EN_SHIFT                   (2U)
84673 /*! PWR_EN - Power Enable (with lock) */
84674 #define SRAM_CTRL_PWR_EN(x)                      (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_PWR_EN_SHIFT)) & SRAM_CTRL_PWR_EN_MASK)
84675 
84676 #define SRAM_CTRL_TAMPER_BLOCK_EN_MASK           (0x40U)
84677 #define SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT          (6U)
84678 /*! TAMPER_BLOCK_EN - Tamper Block Enable (with lock)
84679  *  0b0..Allow R/W access to secure RAM when tamper is detected
84680  *  0b1..Block R/W access to secure RAM when tamper is detected
84681  */
84682 #define SRAM_CTRL_TAMPER_BLOCK_EN(x)             (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT)) & SRAM_CTRL_TAMPER_BLOCK_EN_MASK)
84683 
84684 #define SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK         (0x80U)
84685 #define SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT        (7U)
84686 /*! TAMPER_PWR_OFF_EN - Turn off power on tamper event (with lock)
84687  *  0b0..Disable the turn off function when tamper is detected
84688  *  0b1..Turn off power for all secure RAM banks when tamper is detected
84689  */
84690 #define SRAM_CTRL_TAMPER_PWR_OFF_EN(x)           (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT)) & SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK)
84691 
84692 #define SRAM_CTRL_LOCK_BIT_MASK                  (0xFF0000U)
84693 #define SRAM_CTRL_LOCK_BIT_SHIFT                 (16U)
84694 /*! LOCK_BIT - Lock bits */
84695 #define SRAM_CTRL_LOCK_BIT(x)                    (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_LOCK_BIT_SHIFT)) & SRAM_CTRL_LOCK_BIT_MASK)
84696 /*! @} */
84697 
84698 
84699 /*!
84700  * @}
84701  */ /* end of group SRAM_Register_Masks */
84702 
84703 
84704 /* SRAM - Peripheral instance base addresses */
84705 /** Peripheral SRAM base address */
84706 #define SRAM_BASE                                (0x40C9C000u)
84707 /** Peripheral SRAM base pointer */
84708 #define SRAM                                     ((SRAM_Type *)SRAM_BASE)
84709 /** Array initializer of SRAM peripheral base addresses */
84710 #define SRAM_BASE_ADDRS                          { SRAM_BASE }
84711 /** Array initializer of SRAM peripheral base pointers */
84712 #define SRAM_BASE_PTRS                           { SRAM }
84713 
84714 /*!
84715  * @}
84716  */ /* end of group SRAM_Peripheral_Access_Layer */
84717 
84718 
84719 /* ----------------------------------------------------------------------------
84720    -- SRC Peripheral Access Layer
84721    ---------------------------------------------------------------------------- */
84722 
84723 /*!
84724  * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer
84725  * @{
84726  */
84727 
84728 /** SRC - Register Layout Typedef */
84729 typedef struct {
84730   __IO uint32_t SCR;                               /**< SRC Control Register, offset: 0x0 */
84731   __IO uint32_t SRMR;                              /**< SRC Reset Mode Register, offset: 0x4 */
84732   __I  uint32_t SBMR1;                             /**< SRC Boot Mode Register 1, offset: 0x8 */
84733   __I  uint32_t SBMR2;                             /**< SRC Boot Mode Register 2, offset: 0xC */
84734   __IO uint32_t SRSR;                              /**< SRC Reset Status Register, offset: 0x10 */
84735   __IO uint32_t GPR[20];                           /**< SRC General Purpose Register, array offset: 0x14, array step: 0x4 */
84736        uint8_t RESERVED_0[412];
84737   __IO uint32_t AUTHEN_MEGA;                       /**< Slice Authentication Register, offset: 0x200 */
84738   __IO uint32_t CTRL_MEGA;                         /**< Slice Control Register, offset: 0x204 */
84739   __IO uint32_t SETPOINT_MEGA;                     /**< Slice Setpoint Config Register, offset: 0x208 */
84740   __IO uint32_t DOMAIN_MEGA;                       /**< Slice Domain Config Register, offset: 0x20C */
84741   __IO uint32_t STAT_MEGA;                         /**< Slice Status Register, offset: 0x210 */
84742        uint8_t RESERVED_1[12];
84743   __IO uint32_t AUTHEN_DISPLAY;                    /**< Slice Authentication Register, offset: 0x220 */
84744   __IO uint32_t CTRL_DISPLAY;                      /**< Slice Control Register, offset: 0x224 */
84745   __IO uint32_t SETPOINT_DISPLAY;                  /**< Slice Setpoint Config Register, offset: 0x228 */
84746   __IO uint32_t DOMAIN_DISPLAY;                    /**< Slice Domain Config Register, offset: 0x22C */
84747   __IO uint32_t STAT_DISPLAY;                      /**< Slice Status Register, offset: 0x230 */
84748        uint8_t RESERVED_2[12];
84749   __IO uint32_t AUTHEN_WAKEUP;                     /**< Slice Authentication Register, offset: 0x240 */
84750   __IO uint32_t CTRL_WAKEUP;                       /**< Slice Control Register, offset: 0x244 */
84751   __IO uint32_t SETPOINT_WAKEUP;                   /**< Slice Setpoint Config Register, offset: 0x248 */
84752   __IO uint32_t DOMAIN_WAKEUP;                     /**< Slice Domain Config Register, offset: 0x24C */
84753   __IO uint32_t STAT_WAKEUP;                       /**< Slice Status Register, offset: 0x250 */
84754        uint8_t RESERVED_3[44];
84755   __IO uint32_t AUTHEN_M4CORE;                     /**< Slice Authentication Register, offset: 0x280 */
84756   __IO uint32_t CTRL_M4CORE;                       /**< Slice Control Register, offset: 0x284 */
84757   __IO uint32_t SETPOINT_M4CORE;                   /**< Slice Setpoint Config Register, offset: 0x288 */
84758   __IO uint32_t DOMAIN_M4CORE;                     /**< Slice Domain Config Register, offset: 0x28C */
84759   __IO uint32_t STAT_M4CORE;                       /**< Slice Status Register, offset: 0x290 */
84760        uint8_t RESERVED_4[12];
84761   __IO uint32_t AUTHEN_M7CORE;                     /**< Slice Authentication Register, offset: 0x2A0 */
84762   __IO uint32_t CTRL_M7CORE;                       /**< Slice Control Register, offset: 0x2A4 */
84763   __IO uint32_t SETPOINT_M7CORE;                   /**< Slice Setpoint Config Register, offset: 0x2A8 */
84764   __IO uint32_t DOMAIN_M7CORE;                     /**< Slice Domain Config Register, offset: 0x2AC */
84765   __IO uint32_t STAT_M7CORE;                       /**< Slice Status Register, offset: 0x2B0 */
84766        uint8_t RESERVED_5[12];
84767   __IO uint32_t AUTHEN_M4DEBUG;                    /**< Slice Authentication Register, offset: 0x2C0 */
84768   __IO uint32_t CTRL_M4DEBUG;                      /**< Slice Control Register, offset: 0x2C4 */
84769   __IO uint32_t SETPOINT_M4DEBUG;                  /**< Slice Setpoint Config Register, offset: 0x2C8 */
84770   __IO uint32_t DOMAIN_M4DEBUG;                    /**< Slice Domain Config Register, offset: 0x2CC */
84771   __IO uint32_t STAT_M4DEBUG;                      /**< Slice Status Register, offset: 0x2D0 */
84772        uint8_t RESERVED_6[12];
84773   __IO uint32_t AUTHEN_M7DEBUG;                    /**< Slice Authentication Register, offset: 0x2E0 */
84774   __IO uint32_t CTRL_M7DEBUG;                      /**< Slice Control Register, offset: 0x2E4 */
84775   __IO uint32_t SETPOINT_M7DEBUG;                  /**< Slice Setpoint Config Register, offset: 0x2E8 */
84776   __IO uint32_t DOMAIN_M7DEBUG;                    /**< Slice Domain Config Register, offset: 0x2EC */
84777   __IO uint32_t STAT_M7DEBUG;                      /**< Slice Status Register, offset: 0x2F0 */
84778        uint8_t RESERVED_7[12];
84779   __IO uint32_t AUTHEN_USBPHY1;                    /**< Slice Authentication Register, offset: 0x300 */
84780   __IO uint32_t CTRL_USBPHY1;                      /**< Slice Control Register, offset: 0x304 */
84781   __IO uint32_t SETPOINT_USBPHY1;                  /**< Slice Setpoint Config Register, offset: 0x308 */
84782   __IO uint32_t DOMAIN_USBPHY1;                    /**< Slice Domain Config Register, offset: 0x30C */
84783   __IO uint32_t STAT_USBPHY1;                      /**< Slice Status Register, offset: 0x310 */
84784        uint8_t RESERVED_8[12];
84785   __IO uint32_t AUTHEN_USBPHY2;                    /**< Slice Authentication Register, offset: 0x320 */
84786   __IO uint32_t CTRL_USBPHY2;                      /**< Slice Control Register, offset: 0x324 */
84787   __IO uint32_t SETPOINT_USBPHY2;                  /**< Slice Setpoint Config Register, offset: 0x328 */
84788   __IO uint32_t DOMAIN_USBPHY2;                    /**< Slice Domain Config Register, offset: 0x32C */
84789   __IO uint32_t STAT_USBPHY2;                      /**< Slice Status Register, offset: 0x330 */
84790 } SRC_Type;
84791 
84792 /* ----------------------------------------------------------------------------
84793    -- SRC Register Masks
84794    ---------------------------------------------------------------------------- */
84795 
84796 /*!
84797  * @addtogroup SRC_Register_Masks SRC Register Masks
84798  * @{
84799  */
84800 
84801 /*! @name SCR - SRC Control Register */
84802 /*! @{ */
84803 
84804 #define SRC_SCR_BT_RELEASE_M4_MASK               (0x1U)
84805 #define SRC_SCR_BT_RELEASE_M4_SHIFT              (0U)
84806 /*! BT_RELEASE_M4
84807  *  0b0..cm4 core reset is asserted
84808  *  0b1..cm4 core reset is released
84809  */
84810 #define SRC_SCR_BT_RELEASE_M4(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M4_SHIFT)) & SRC_SCR_BT_RELEASE_M4_MASK)
84811 
84812 #define SRC_SCR_BT_RELEASE_M7_MASK               (0x2U)
84813 #define SRC_SCR_BT_RELEASE_M7_SHIFT              (1U)
84814 /*! BT_RELEASE_M7
84815  *  0b0..cm7 core reset is asserted
84816  *  0b1..cm7 core reset is released
84817  */
84818 #define SRC_SCR_BT_RELEASE_M7(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M7_SHIFT)) & SRC_SCR_BT_RELEASE_M7_MASK)
84819 /*! @} */
84820 
84821 /*! @name SRMR - SRC Reset Mode Register */
84822 /*! @{ */
84823 
84824 #define SRC_SRMR_WDOG_RESET_MODE_MASK            (0x3U)
84825 #define SRC_SRMR_WDOG_RESET_MODE_SHIFT           (0U)
84826 /*! WDOG_RESET_MODE - Wdog reset mode configuration
84827  *  0b00..reset system
84828  *  0b01..reserved
84829  *  0b10..reserved
84830  *  0b11..do not reset anything
84831  */
84832 #define SRC_SRMR_WDOG_RESET_MODE(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG_RESET_MODE_MASK)
84833 
84834 #define SRC_SRMR_WDOG3_RESET_MODE_MASK           (0xCU)
84835 #define SRC_SRMR_WDOG3_RESET_MODE_SHIFT          (2U)
84836 /*! WDOG3_RESET_MODE - Wdog3 reset mode configuration
84837  *  0b00..reset system
84838  *  0b01..reserved
84839  *  0b10..reserved
84840  *  0b11..do not reset anything
84841  */
84842 #define SRC_SRMR_WDOG3_RESET_MODE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG3_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG3_RESET_MODE_MASK)
84843 
84844 #define SRC_SRMR_WDOG4_RESET_MODE_MASK           (0x30U)
84845 #define SRC_SRMR_WDOG4_RESET_MODE_SHIFT          (4U)
84846 /*! WDOG4_RESET_MODE - Wdog4 reset mode configuration
84847  *  0b00..reset system
84848  *  0b01..reserved
84849  *  0b10..reserved
84850  *  0b11..do not reset anything
84851  */
84852 #define SRC_SRMR_WDOG4_RESET_MODE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG4_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG4_RESET_MODE_MASK)
84853 
84854 #define SRC_SRMR_M4LOCKUP_RESET_MODE_MASK        (0xC0U)
84855 #define SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT       (6U)
84856 /*! M4LOCKUP_RESET_MODE - M4 core lockup reset mode configuration
84857  *  0b00..reset system
84858  *  0b01..reserved
84859  *  0b10..reserved
84860  *  0b11..do not reset anything
84861  */
84862 #define SRC_SRMR_M4LOCKUP_RESET_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M4LOCKUP_RESET_MODE_MASK)
84863 
84864 #define SRC_SRMR_M7LOCKUP_RESET_MODE_MASK        (0x300U)
84865 #define SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT       (8U)
84866 /*! M7LOCKUP_RESET_MODE - M7 core lockup reset mode configuration
84867  *  0b00..reset system
84868  *  0b01..reserved
84869  *  0b10..reserved
84870  *  0b11..do not reset anything
84871  */
84872 #define SRC_SRMR_M7LOCKUP_RESET_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M7LOCKUP_RESET_MODE_MASK)
84873 
84874 #define SRC_SRMR_M4REQ_RESET_MODE_MASK           (0xC00U)
84875 #define SRC_SRMR_M4REQ_RESET_MODE_SHIFT          (10U)
84876 /*! M4REQ_RESET_MODE - M4 request reset configuration
84877  *  0b00..reset system
84878  *  0b01..reserved
84879  *  0b10..reserved
84880  *  0b11..do not reset anything
84881  */
84882 #define SRC_SRMR_M4REQ_RESET_MODE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M4REQ_RESET_MODE_MASK)
84883 
84884 #define SRC_SRMR_M7REQ_RESET_MODE_MASK           (0x3000U)
84885 #define SRC_SRMR_M7REQ_RESET_MODE_SHIFT          (12U)
84886 /*! M7REQ_RESET_MODE - M7 request reset configuration
84887  *  0b00..reset system
84888  *  0b01..reserved
84889  *  0b10..reserved
84890  *  0b11..do not reset anything
84891  */
84892 #define SRC_SRMR_M7REQ_RESET_MODE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M7REQ_RESET_MODE_MASK)
84893 
84894 #define SRC_SRMR_TEMPSENSE_RESET_MODE_MASK       (0xC000U)
84895 #define SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT      (14U)
84896 /*! TEMPSENSE_RESET_MODE - Tempsense reset mode configuration
84897  *  0b00..reset system
84898  *  0b01..reserved
84899  *  0b10..reserved
84900  *  0b11..do not reset anything
84901  */
84902 #define SRC_SRMR_TEMPSENSE_RESET_MODE(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT)) & SRC_SRMR_TEMPSENSE_RESET_MODE_MASK)
84903 
84904 #define SRC_SRMR_CSU_RESET_MODE_MASK             (0x30000U)
84905 #define SRC_SRMR_CSU_RESET_MODE_SHIFT            (16U)
84906 /*! CSU_RESET_MODE - CSU reset mode configuration
84907  *  0b00..reset system
84908  *  0b01..reserved
84909  *  0b10..reserved
84910  *  0b11..do not reset anything
84911  */
84912 #define SRC_SRMR_CSU_RESET_MODE(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_CSU_RESET_MODE_SHIFT)) & SRC_SRMR_CSU_RESET_MODE_MASK)
84913 
84914 #define SRC_SRMR_JTAGSW_RESET_MODE_MASK          (0xC0000U)
84915 #define SRC_SRMR_JTAGSW_RESET_MODE_SHIFT         (18U)
84916 /*! JTAGSW_RESET_MODE - Jtag SW reset mode configuration
84917  *  0b00..reset system
84918  *  0b01..reserved
84919  *  0b10..reserved
84920  *  0b11..do not reset anything
84921  */
84922 #define SRC_SRMR_JTAGSW_RESET_MODE(x)            (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_JTAGSW_RESET_MODE_SHIFT)) & SRC_SRMR_JTAGSW_RESET_MODE_MASK)
84923 
84924 #define SRC_SRMR_OVERVOLT_RESET_MODE_MASK        (0x300000U)
84925 #define SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT       (20U)
84926 /*! OVERVOLT_RESET_MODE - Jtag SW reset mode configuration
84927  *  0b00..reset system
84928  *  0b01..reserved
84929  *  0b10..reserved
84930  *  0b11..do not reset anything
84931  */
84932 #define SRC_SRMR_OVERVOLT_RESET_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT)) & SRC_SRMR_OVERVOLT_RESET_MODE_MASK)
84933 /*! @} */
84934 
84935 /*! @name SBMR1 - SRC Boot Mode Register 1 */
84936 /*! @{ */
84937 
84938 #define SRC_SBMR1_BOOT_CFG1_MASK                 (0xFFU)
84939 #define SRC_SBMR1_BOOT_CFG1_SHIFT                (0U)
84940 #define SRC_SBMR1_BOOT_CFG1(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)
84941 
84942 #define SRC_SBMR1_BOOT_CFG2_MASK                 (0xFF00U)
84943 #define SRC_SBMR1_BOOT_CFG2_SHIFT                (8U)
84944 #define SRC_SBMR1_BOOT_CFG2(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)
84945 
84946 #define SRC_SBMR1_BOOT_CFG3_MASK                 (0xFF0000U)
84947 #define SRC_SBMR1_BOOT_CFG3_SHIFT                (16U)
84948 #define SRC_SBMR1_BOOT_CFG3(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)
84949 
84950 #define SRC_SBMR1_BOOT_CFG4_MASK                 (0xFF000000U)
84951 #define SRC_SBMR1_BOOT_CFG4_SHIFT                (24U)
84952 #define SRC_SBMR1_BOOT_CFG4(x)                   (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)
84953 /*! @} */
84954 
84955 /*! @name SBMR2 - SRC Boot Mode Register 2 */
84956 /*! @{ */
84957 
84958 #define SRC_SBMR2_SEC_CONFIG_MASK                (0x3U)
84959 #define SRC_SBMR2_SEC_CONFIG_SHIFT               (0U)
84960 #define SRC_SBMR2_SEC_CONFIG(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
84961 
84962 #define SRC_SBMR2_BT_FUSE_SEL_MASK               (0x10U)
84963 #define SRC_SBMR2_BT_FUSE_SEL_SHIFT              (4U)
84964 #define SRC_SBMR2_BT_FUSE_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
84965 
84966 #define SRC_SBMR2_BMOD_MASK                      (0x3000000U)
84967 #define SRC_SBMR2_BMOD_SHIFT                     (24U)
84968 #define SRC_SBMR2_BMOD(x)                        (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)
84969 /*! @} */
84970 
84971 /*! @name SRSR - SRC Reset Status Register */
84972 /*! @{ */
84973 
84974 #define SRC_SRSR_IPP_RESET_B_M7_MASK             (0x1U)
84975 #define SRC_SRSR_IPP_RESET_B_M7_SHIFT            (0U)
84976 /*! IPP_RESET_B_M7
84977  *  0b0..Reset is not a result of ipp_reset_b pin.
84978  *  0b1..Reset is a result of ipp_reset_b pin.
84979  */
84980 #define SRC_SRSR_IPP_RESET_B_M7(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_RESET_B_M7_MASK)
84981 
84982 #define SRC_SRSR_M7_REQUEST_M7_MASK              (0x2U)
84983 #define SRC_SRSR_M7_REQUEST_M7_SHIFT             (1U)
84984 /*! M7_REQUEST_M7
84985  *  0b0..Reset is not a result of m7 reset request.
84986  *  0b1..Reset is a result of m7 reset request.
84987  */
84988 #define SRC_SRSR_M7_REQUEST_M7(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M7_SHIFT)) & SRC_SRSR_M7_REQUEST_M7_MASK)
84989 
84990 #define SRC_SRSR_M7_LOCKUP_M7_MASK               (0x4U)
84991 #define SRC_SRSR_M7_LOCKUP_M7_SHIFT              (2U)
84992 /*! M7_LOCKUP_M7
84993  *  0b0..Reset is not a result of the mentioned case.
84994  *  0b1..Reset is a result of the mentioned case.
84995  */
84996 #define SRC_SRSR_M7_LOCKUP_M7(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M7_SHIFT)) & SRC_SRSR_M7_LOCKUP_M7_MASK)
84997 
84998 #define SRC_SRSR_CSU_RESET_B_M7_MASK             (0x8U)
84999 #define SRC_SRSR_CSU_RESET_B_M7_SHIFT            (3U)
85000 /*! CSU_RESET_B_M7
85001  *  0b0..Reset is not a result of the csu_reset_b event.
85002  *  0b1..Reset is a result of the csu_reset_b event.
85003  */
85004 #define SRC_SRSR_CSU_RESET_B_M7(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M7_SHIFT)) & SRC_SRSR_CSU_RESET_B_M7_MASK)
85005 
85006 #define SRC_SRSR_IPP_USER_RESET_B_M7_MASK        (0x10U)
85007 #define SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT       (4U)
85008 /*! IPP_USER_RESET_B_M7
85009  *  0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
85010  *  0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
85011  */
85012 #define SRC_SRSR_IPP_USER_RESET_B_M7(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M7_MASK)
85013 
85014 #define SRC_SRSR_WDOG_RST_B_M7_MASK              (0x20U)
85015 #define SRC_SRSR_WDOG_RST_B_M7_SHIFT             (5U)
85016 /*! WDOG_RST_B_M7
85017  *  0b0..Reset is not a result of the watchdog time-out event.
85018  *  0b1..Reset is a result of the watchdog time-out event.
85019  */
85020 #define SRC_SRSR_WDOG_RST_B_M7(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG_RST_B_M7_MASK)
85021 
85022 #define SRC_SRSR_JTAG_RST_B_M7_MASK              (0x40U)
85023 #define SRC_SRSR_JTAG_RST_B_M7_SHIFT             (6U)
85024 /*! JTAG_RST_B_M7
85025  *  0b0..Reset is not a result of HIGH-Z reset from JTAG.
85026  *  0b1..Reset is a result of HIGH-Z reset from JTAG.
85027  */
85028 #define SRC_SRSR_JTAG_RST_B_M7(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M7_SHIFT)) & SRC_SRSR_JTAG_RST_B_M7_MASK)
85029 
85030 #define SRC_SRSR_JTAG_SW_RST_M7_MASK             (0x80U)
85031 #define SRC_SRSR_JTAG_SW_RST_M7_SHIFT            (7U)
85032 /*! JTAG_SW_RST_M7
85033  *  0b0..Reset is not a result of software reset from JTAG.
85034  *  0b1..Reset is a result of software reset from JTAG.
85035  */
85036 #define SRC_SRSR_JTAG_SW_RST_M7(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M7_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M7_MASK)
85037 
85038 #define SRC_SRSR_WDOG3_RST_B_M7_MASK             (0x100U)
85039 #define SRC_SRSR_WDOG3_RST_B_M7_SHIFT            (8U)
85040 /*! WDOG3_RST_B_M7
85041  *  0b0..Reset is not a result of the watchdog3 time-out event.
85042  *  0b1..Reset is a result of the watchdog3 time-out event.
85043  */
85044 #define SRC_SRSR_WDOG3_RST_B_M7(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M7_MASK)
85045 
85046 #define SRC_SRSR_WDOG4_RST_B_M7_MASK             (0x200U)
85047 #define SRC_SRSR_WDOG4_RST_B_M7_SHIFT            (9U)
85048 /*! WDOG4_RST_B_M7
85049  *  0b0..Reset is not a result of the watchdog4 time-out event.
85050  *  0b1..Reset is a result of the watchdog4 time-out event.
85051  */
85052 #define SRC_SRSR_WDOG4_RST_B_M7(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M7_MASK)
85053 
85054 #define SRC_SRSR_TEMPSENSE_RST_B_M7_MASK         (0x400U)
85055 #define SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT        (10U)
85056 /*! TEMPSENSE_RST_B_M7
85057  *  0b0..Reset is not a result of software reset from Temperature Sensor.
85058  *  0b1..Reset is a result of software reset from Temperature Sensor.
85059  */
85060 #define SRC_SRSR_TEMPSENSE_RST_B_M7(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M7_MASK)
85061 
85062 #define SRC_SRSR_M4_REQUEST_M7_MASK              (0x800U)
85063 #define SRC_SRSR_M4_REQUEST_M7_SHIFT             (11U)
85064 /*! M4_REQUEST_M7
85065  *  0b0..Reset is not a result of m4 reset request.
85066  *  0b1..Reset is a result of m4 reset request.
85067  */
85068 #define SRC_SRSR_M4_REQUEST_M7(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M7_SHIFT)) & SRC_SRSR_M4_REQUEST_M7_MASK)
85069 
85070 #define SRC_SRSR_M4_LOCKUP_M7_MASK               (0x1000U)
85071 #define SRC_SRSR_M4_LOCKUP_M7_SHIFT              (12U)
85072 /*! M4_LOCKUP_M7
85073  *  0b0..Reset is not a result of the mentioned case.
85074  *  0b1..Reset is a result of the mentioned case.
85075  */
85076 #define SRC_SRSR_M4_LOCKUP_M7(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M7_SHIFT)) & SRC_SRSR_M4_LOCKUP_M7_MASK)
85077 
85078 #define SRC_SRSR_OVERVOLT_RST_M7_MASK            (0x2000U)
85079 #define SRC_SRSR_OVERVOLT_RST_M7_SHIFT           (13U)
85080 /*! OVERVOLT_RST_M7
85081  *  0b0..Reset is not a result of the mentioned case.
85082  *  0b1..Reset is a result of the mentioned case.
85083  */
85084 #define SRC_SRSR_OVERVOLT_RST_M7(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M7_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M7_MASK)
85085 
85086 #define SRC_SRSR_CDOG_RST_M7_MASK                (0x4000U)
85087 #define SRC_SRSR_CDOG_RST_M7_SHIFT               (14U)
85088 /*! CDOG_RST_M7
85089  *  0b0..Reset is not a result of the mentioned case.
85090  *  0b1..Reset is a result of the mentioned case.
85091  */
85092 #define SRC_SRSR_CDOG_RST_M7(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M7_SHIFT)) & SRC_SRSR_CDOG_RST_M7_MASK)
85093 
85094 #define SRC_SRSR_IPP_RESET_B_M4_MASK             (0x10000U)
85095 #define SRC_SRSR_IPP_RESET_B_M4_SHIFT            (16U)
85096 /*! IPP_RESET_B_M4
85097  *  0b0..Reset is not a result of ipp_reset_b pin.
85098  *  0b1..Reset is a result of ipp_reset_b pin.
85099  */
85100 #define SRC_SRSR_IPP_RESET_B_M4(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_RESET_B_M4_MASK)
85101 
85102 #define SRC_SRSR_M4_REQUEST_M4_MASK              (0x20000U)
85103 #define SRC_SRSR_M4_REQUEST_M4_SHIFT             (17U)
85104 /*! M4_REQUEST_M4
85105  *  0b0..Reset is not a result of m4 reset request.
85106  *  0b1..Reset is a result of m4 reset request.
85107  */
85108 #define SRC_SRSR_M4_REQUEST_M4(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M4_SHIFT)) & SRC_SRSR_M4_REQUEST_M4_MASK)
85109 
85110 #define SRC_SRSR_M4_LOCKUP_M4_MASK               (0x40000U)
85111 #define SRC_SRSR_M4_LOCKUP_M4_SHIFT              (18U)
85112 /*! M4_LOCKUP_M4
85113  *  0b0..Reset is not a result of the mentioned case.
85114  *  0b1..Reset is a result of the mentioned case.
85115  */
85116 #define SRC_SRSR_M4_LOCKUP_M4(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M4_SHIFT)) & SRC_SRSR_M4_LOCKUP_M4_MASK)
85117 
85118 #define SRC_SRSR_CSU_RESET_B_M4_MASK             (0x80000U)
85119 #define SRC_SRSR_CSU_RESET_B_M4_SHIFT            (19U)
85120 /*! CSU_RESET_B_M4
85121  *  0b0..Reset is not a result of the csu_reset_b event.
85122  *  0b1..Reset is a result of the csu_reset_b event.
85123  */
85124 #define SRC_SRSR_CSU_RESET_B_M4(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M4_SHIFT)) & SRC_SRSR_CSU_RESET_B_M4_MASK)
85125 
85126 #define SRC_SRSR_IPP_USER_RESET_B_M4_MASK        (0x100000U)
85127 #define SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT       (20U)
85128 /*! IPP_USER_RESET_B_M4
85129  *  0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
85130  *  0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
85131  */
85132 #define SRC_SRSR_IPP_USER_RESET_B_M4(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M4_MASK)
85133 
85134 #define SRC_SRSR_WDOG_RST_B_M4_MASK              (0x200000U)
85135 #define SRC_SRSR_WDOG_RST_B_M4_SHIFT             (21U)
85136 /*! WDOG_RST_B_M4
85137  *  0b0..Reset is not a result of the watchdog time-out event.
85138  *  0b1..Reset is a result of the watchdog time-out event.
85139  */
85140 #define SRC_SRSR_WDOG_RST_B_M4(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG_RST_B_M4_MASK)
85141 
85142 #define SRC_SRSR_JTAG_RST_B_M4_MASK              (0x400000U)
85143 #define SRC_SRSR_JTAG_RST_B_M4_SHIFT             (22U)
85144 /*! JTAG_RST_B_M4
85145  *  0b0..Reset is not a result of HIGH-Z reset from JTAG.
85146  *  0b1..Reset is a result of HIGH-Z reset from JTAG.
85147  */
85148 #define SRC_SRSR_JTAG_RST_B_M4(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M4_SHIFT)) & SRC_SRSR_JTAG_RST_B_M4_MASK)
85149 
85150 #define SRC_SRSR_JTAG_SW_RST_M4_MASK             (0x800000U)
85151 #define SRC_SRSR_JTAG_SW_RST_M4_SHIFT            (23U)
85152 /*! JTAG_SW_RST_M4
85153  *  0b0..Reset is not a result of software reset from JTAG.
85154  *  0b1..Reset is a result of software reset from JTAG.
85155  */
85156 #define SRC_SRSR_JTAG_SW_RST_M4(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M4_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M4_MASK)
85157 
85158 #define SRC_SRSR_WDOG3_RST_B_M4_MASK             (0x1000000U)
85159 #define SRC_SRSR_WDOG3_RST_B_M4_SHIFT            (24U)
85160 /*! WDOG3_RST_B_M4
85161  *  0b0..Reset is not a result of the watchdog3 time-out event.
85162  *  0b1..Reset is a result of the watchdog3 time-out event.
85163  */
85164 #define SRC_SRSR_WDOG3_RST_B_M4(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M4_MASK)
85165 
85166 #define SRC_SRSR_WDOG4_RST_B_M4_MASK             (0x2000000U)
85167 #define SRC_SRSR_WDOG4_RST_B_M4_SHIFT            (25U)
85168 /*! WDOG4_RST_B_M4
85169  *  0b0..Reset is not a result of the watchdog4 time-out event.
85170  *  0b1..Reset is a result of the watchdog4 time-out event.
85171  */
85172 #define SRC_SRSR_WDOG4_RST_B_M4(x)               (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M4_MASK)
85173 
85174 #define SRC_SRSR_TEMPSENSE_RST_B_M4_MASK         (0x4000000U)
85175 #define SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT        (26U)
85176 /*! TEMPSENSE_RST_B_M4
85177  *  0b0..Reset is not a result of software reset from Temperature Sensor.
85178  *  0b1..Reset is a result of software reset from Temperature Sensor.
85179  */
85180 #define SRC_SRSR_TEMPSENSE_RST_B_M4(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M4_MASK)
85181 
85182 #define SRC_SRSR_M7_REQUEST_M4_MASK              (0x8000000U)
85183 #define SRC_SRSR_M7_REQUEST_M4_SHIFT             (27U)
85184 /*! M7_REQUEST_M4
85185  *  0b0..Reset is not a result of m7 reset request.
85186  *  0b1..Reset is a result of m7 reset request.
85187  */
85188 #define SRC_SRSR_M7_REQUEST_M4(x)                (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M4_SHIFT)) & SRC_SRSR_M7_REQUEST_M4_MASK)
85189 
85190 #define SRC_SRSR_M7_LOCKUP_M4_MASK               (0x10000000U)
85191 #define SRC_SRSR_M7_LOCKUP_M4_SHIFT              (28U)
85192 /*! M7_LOCKUP_M4
85193  *  0b0..Reset is not a result of the mentioned case.
85194  *  0b1..Reset is a result of the mentioned case.
85195  */
85196 #define SRC_SRSR_M7_LOCKUP_M4(x)                 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M4_SHIFT)) & SRC_SRSR_M7_LOCKUP_M4_MASK)
85197 
85198 #define SRC_SRSR_OVERVOLT_RST_M4_MASK            (0x20000000U)
85199 #define SRC_SRSR_OVERVOLT_RST_M4_SHIFT           (29U)
85200 /*! OVERVOLT_RST_M4
85201  *  0b0..Reset is not a result of the mentioned case.
85202  *  0b1..Reset is a result of the mentioned case.
85203  */
85204 #define SRC_SRSR_OVERVOLT_RST_M4(x)              (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M4_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M4_MASK)
85205 
85206 #define SRC_SRSR_CDOG_RST_M4_MASK                (0x40000000U)
85207 #define SRC_SRSR_CDOG_RST_M4_SHIFT               (30U)
85208 /*! CDOG_RST_M4
85209  *  0b0..Reset is not a result of the mentioned case.
85210  *  0b1..Reset is a result of the mentioned case.
85211  */
85212 #define SRC_SRSR_CDOG_RST_M4(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M4_SHIFT)) & SRC_SRSR_CDOG_RST_M4_MASK)
85213 /*! @} */
85214 
85215 /*! @name GPR - SRC General Purpose Register */
85216 /*! @{ */
85217 
85218 #define SRC_GPR_GPR_MASK                         (0xFFFFFFFFU)
85219 #define SRC_GPR_GPR_SHIFT                        (0U)
85220 /*! GPR - General Purpose Register. */
85221 #define SRC_GPR_GPR(x)                           (((uint32_t)(((uint32_t)(x)) << SRC_GPR_GPR_SHIFT)) & SRC_GPR_GPR_MASK)
85222 /*! @} */
85223 
85224 /* The count of SRC_GPR */
85225 #define SRC_GPR_COUNT                            (20U)
85226 
85227 /*! @name AUTHEN_MEGA - Slice Authentication Register */
85228 /*! @{ */
85229 
85230 #define SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK         (0x1U)
85231 #define SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT        (0U)
85232 /*! DOMAIN_MODE
85233  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
85234  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
85235  */
85236 #define SRC_AUTHEN_MEGA_DOMAIN_MODE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK)
85237 
85238 #define SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK       (0x2U)
85239 #define SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT      (1U)
85240 /*! SETPOINT_MODE
85241  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
85242  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
85243  */
85244 #define SRC_AUTHEN_MEGA_SETPOINT_MODE(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK)
85245 
85246 #define SRC_AUTHEN_MEGA_LOCK_MODE_MASK           (0x80U)
85247 #define SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT          (7U)
85248 /*! LOCK_MODE - Domain/Setpoint mode lock */
85249 #define SRC_AUTHEN_MEGA_LOCK_MODE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_MODE_MASK)
85250 
85251 #define SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK         (0xF00U)
85252 #define SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT        (8U)
85253 #define SRC_AUTHEN_MEGA_ASSIGN_LIST(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK)
85254 
85255 #define SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK         (0x8000U)
85256 #define SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT        (15U)
85257 /*! LOCK_ASSIGN - Assign list lock */
85258 #define SRC_AUTHEN_MEGA_LOCK_ASSIGN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK)
85259 
85260 #define SRC_AUTHEN_MEGA_WHITE_LIST_MASK          (0xF0000U)
85261 #define SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT         (16U)
85262 /*! WHITE_LIST - Domain ID white list */
85263 #define SRC_AUTHEN_MEGA_WHITE_LIST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT)) & SRC_AUTHEN_MEGA_WHITE_LIST_MASK)
85264 
85265 #define SRC_AUTHEN_MEGA_LOCK_LIST_MASK           (0x800000U)
85266 #define SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT          (23U)
85267 /*! LOCK_LIST - White list lock */
85268 #define SRC_AUTHEN_MEGA_LOCK_LIST(x)             (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_LIST_MASK)
85269 
85270 #define SRC_AUTHEN_MEGA_USER_MASK                (0x1000000U)
85271 #define SRC_AUTHEN_MEGA_USER_SHIFT               (24U)
85272 /*! USER - Allow user mode access */
85273 #define SRC_AUTHEN_MEGA_USER(x)                  (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_USER_SHIFT)) & SRC_AUTHEN_MEGA_USER_MASK)
85274 
85275 #define SRC_AUTHEN_MEGA_NONSECURE_MASK           (0x2000000U)
85276 #define SRC_AUTHEN_MEGA_NONSECURE_SHIFT          (25U)
85277 /*! NONSECURE - Allow non-secure mode access */
85278 #define SRC_AUTHEN_MEGA_NONSECURE(x)             (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_NONSECURE_SHIFT)) & SRC_AUTHEN_MEGA_NONSECURE_MASK)
85279 
85280 #define SRC_AUTHEN_MEGA_LOCK_SETTING_MASK        (0x80000000U)
85281 #define SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT       (31U)
85282 /*! LOCK_SETTING - Lock NONSECURE and USER */
85283 #define SRC_AUTHEN_MEGA_LOCK_SETTING(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_SETTING_MASK)
85284 /*! @} */
85285 
85286 /*! @name CTRL_MEGA - Slice Control Register */
85287 /*! @{ */
85288 
85289 #define SRC_CTRL_MEGA_SW_RESET_MASK              (0x1U)
85290 #define SRC_CTRL_MEGA_SW_RESET_SHIFT             (0U)
85291 /*! SW_RESET
85292  *  0b0..do not assert slice software reset
85293  *  0b1..assert slice software reset
85294  */
85295 #define SRC_CTRL_MEGA_SW_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_MEGA_SW_RESET_SHIFT)) & SRC_CTRL_MEGA_SW_RESET_MASK)
85296 /*! @} */
85297 
85298 /*! @name SETPOINT_MEGA - Slice Setpoint Config Register */
85299 /*! @{ */
85300 
85301 #define SRC_SETPOINT_MEGA_SETPOINT0_MASK         (0x1U)
85302 #define SRC_SETPOINT_MEGA_SETPOINT0_SHIFT        (0U)
85303 /*! SETPOINT0 - SETPOINT0
85304  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85305  *  0b1..Slice reset will be asserted when system in Setpoint n
85306  */
85307 #define SRC_SETPOINT_MEGA_SETPOINT0(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT0_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT0_MASK)
85308 
85309 #define SRC_SETPOINT_MEGA_SETPOINT1_MASK         (0x2U)
85310 #define SRC_SETPOINT_MEGA_SETPOINT1_SHIFT        (1U)
85311 /*! SETPOINT1 - SETPOINT1
85312  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85313  *  0b1..Slice reset will be asserted when system in Setpoint n
85314  */
85315 #define SRC_SETPOINT_MEGA_SETPOINT1(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT1_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT1_MASK)
85316 
85317 #define SRC_SETPOINT_MEGA_SETPOINT2_MASK         (0x4U)
85318 #define SRC_SETPOINT_MEGA_SETPOINT2_SHIFT        (2U)
85319 /*! SETPOINT2 - SETPOINT2
85320  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85321  *  0b1..Slice reset will be asserted when system in Setpoint n
85322  */
85323 #define SRC_SETPOINT_MEGA_SETPOINT2(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT2_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT2_MASK)
85324 
85325 #define SRC_SETPOINT_MEGA_SETPOINT3_MASK         (0x8U)
85326 #define SRC_SETPOINT_MEGA_SETPOINT3_SHIFT        (3U)
85327 /*! SETPOINT3 - SETPOINT3
85328  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85329  *  0b1..Slice reset will be asserted when system in Setpoint n
85330  */
85331 #define SRC_SETPOINT_MEGA_SETPOINT3(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT3_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT3_MASK)
85332 
85333 #define SRC_SETPOINT_MEGA_SETPOINT4_MASK         (0x10U)
85334 #define SRC_SETPOINT_MEGA_SETPOINT4_SHIFT        (4U)
85335 /*! SETPOINT4 - SETPOINT4
85336  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85337  *  0b1..Slice reset will be asserted when system in Setpoint n
85338  */
85339 #define SRC_SETPOINT_MEGA_SETPOINT4(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT4_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT4_MASK)
85340 
85341 #define SRC_SETPOINT_MEGA_SETPOINT5_MASK         (0x20U)
85342 #define SRC_SETPOINT_MEGA_SETPOINT5_SHIFT        (5U)
85343 /*! SETPOINT5 - SETPOINT5
85344  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85345  *  0b1..Slice reset will be asserted when system in Setpoint n
85346  */
85347 #define SRC_SETPOINT_MEGA_SETPOINT5(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT5_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT5_MASK)
85348 
85349 #define SRC_SETPOINT_MEGA_SETPOINT6_MASK         (0x40U)
85350 #define SRC_SETPOINT_MEGA_SETPOINT6_SHIFT        (6U)
85351 /*! SETPOINT6 - SETPOINT6
85352  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85353  *  0b1..Slice reset will be asserted when system in Setpoint n
85354  */
85355 #define SRC_SETPOINT_MEGA_SETPOINT6(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT6_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT6_MASK)
85356 
85357 #define SRC_SETPOINT_MEGA_SETPOINT7_MASK         (0x80U)
85358 #define SRC_SETPOINT_MEGA_SETPOINT7_SHIFT        (7U)
85359 /*! SETPOINT7 - SETPOINT7
85360  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85361  *  0b1..Slice reset will be asserted when system in Setpoint n
85362  */
85363 #define SRC_SETPOINT_MEGA_SETPOINT7(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT7_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT7_MASK)
85364 
85365 #define SRC_SETPOINT_MEGA_SETPOINT8_MASK         (0x100U)
85366 #define SRC_SETPOINT_MEGA_SETPOINT8_SHIFT        (8U)
85367 /*! SETPOINT8 - SETPOINT8
85368  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85369  *  0b1..Slice reset will be asserted when system in Setpoint n
85370  */
85371 #define SRC_SETPOINT_MEGA_SETPOINT8(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT8_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT8_MASK)
85372 
85373 #define SRC_SETPOINT_MEGA_SETPOINT9_MASK         (0x200U)
85374 #define SRC_SETPOINT_MEGA_SETPOINT9_SHIFT        (9U)
85375 /*! SETPOINT9 - SETPOINT9
85376  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85377  *  0b1..Slice reset will be asserted when system in Setpoint n
85378  */
85379 #define SRC_SETPOINT_MEGA_SETPOINT9(x)           (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT9_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT9_MASK)
85380 
85381 #define SRC_SETPOINT_MEGA_SETPOINT10_MASK        (0x400U)
85382 #define SRC_SETPOINT_MEGA_SETPOINT10_SHIFT       (10U)
85383 /*! SETPOINT10 - SETPOINT10
85384  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85385  *  0b1..Slice reset will be asserted when system in Setpoint n
85386  */
85387 #define SRC_SETPOINT_MEGA_SETPOINT10(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT10_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT10_MASK)
85388 
85389 #define SRC_SETPOINT_MEGA_SETPOINT11_MASK        (0x800U)
85390 #define SRC_SETPOINT_MEGA_SETPOINT11_SHIFT       (11U)
85391 /*! SETPOINT11 - SETPOINT11
85392  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85393  *  0b1..Slice reset will be asserted when system in Setpoint n
85394  */
85395 #define SRC_SETPOINT_MEGA_SETPOINT11(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT11_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT11_MASK)
85396 
85397 #define SRC_SETPOINT_MEGA_SETPOINT12_MASK        (0x1000U)
85398 #define SRC_SETPOINT_MEGA_SETPOINT12_SHIFT       (12U)
85399 /*! SETPOINT12 - SETPOINT12
85400  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85401  *  0b1..Slice reset will be asserted when system in Setpoint n
85402  */
85403 #define SRC_SETPOINT_MEGA_SETPOINT12(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT12_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT12_MASK)
85404 
85405 #define SRC_SETPOINT_MEGA_SETPOINT13_MASK        (0x2000U)
85406 #define SRC_SETPOINT_MEGA_SETPOINT13_SHIFT       (13U)
85407 /*! SETPOINT13 - SETPOINT13
85408  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85409  *  0b1..Slice reset will be asserted when system in Setpoint n
85410  */
85411 #define SRC_SETPOINT_MEGA_SETPOINT13(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT13_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT13_MASK)
85412 
85413 #define SRC_SETPOINT_MEGA_SETPOINT14_MASK        (0x4000U)
85414 #define SRC_SETPOINT_MEGA_SETPOINT14_SHIFT       (14U)
85415 /*! SETPOINT14 - SETPOINT14
85416  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85417  *  0b1..Slice reset will be asserted when system in Setpoint n
85418  */
85419 #define SRC_SETPOINT_MEGA_SETPOINT14(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT14_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT14_MASK)
85420 
85421 #define SRC_SETPOINT_MEGA_SETPOINT15_MASK        (0x8000U)
85422 #define SRC_SETPOINT_MEGA_SETPOINT15_SHIFT       (15U)
85423 /*! SETPOINT15 - SETPOINT15
85424  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85425  *  0b1..Slice reset will be asserted when system in Setpoint n
85426  */
85427 #define SRC_SETPOINT_MEGA_SETPOINT15(x)          (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT15_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT15_MASK)
85428 /*! @} */
85429 
85430 /*! @name DOMAIN_MEGA - Slice Domain Config Register */
85431 /*! @{ */
85432 
85433 #define SRC_DOMAIN_MEGA_CPU0_RUN_MASK            (0x1U)
85434 #define SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT           (0U)
85435 /*! CPU0_RUN - CPU mode setting for RUN
85436  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
85437  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
85438  */
85439 #define SRC_DOMAIN_MEGA_CPU0_RUN(x)              (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_RUN_MASK)
85440 
85441 #define SRC_DOMAIN_MEGA_CPU0_WAIT_MASK           (0x2U)
85442 #define SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT          (1U)
85443 /*! CPU0_WAIT - CPU mode setting for WAIT
85444  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
85445  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
85446  */
85447 #define SRC_DOMAIN_MEGA_CPU0_WAIT(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_WAIT_MASK)
85448 
85449 #define SRC_DOMAIN_MEGA_CPU0_STOP_MASK           (0x4U)
85450 #define SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT          (2U)
85451 /*! CPU0_STOP - CPU mode setting for STOP
85452  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
85453  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
85454  */
85455 #define SRC_DOMAIN_MEGA_CPU0_STOP(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_STOP_MASK)
85456 
85457 #define SRC_DOMAIN_MEGA_CPU0_SUSP_MASK           (0x8U)
85458 #define SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT          (3U)
85459 /*! CPU0_SUSP - CPU mode setting for SUSPEND
85460  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
85461  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
85462  */
85463 #define SRC_DOMAIN_MEGA_CPU0_SUSP(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_SUSP_MASK)
85464 
85465 #define SRC_DOMAIN_MEGA_CPU1_RUN_MASK            (0x10U)
85466 #define SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT           (4U)
85467 /*! CPU1_RUN - CPU mode setting for RUN
85468  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
85469  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
85470  */
85471 #define SRC_DOMAIN_MEGA_CPU1_RUN(x)              (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_RUN_MASK)
85472 
85473 #define SRC_DOMAIN_MEGA_CPU1_WAIT_MASK           (0x20U)
85474 #define SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT          (5U)
85475 /*! CPU1_WAIT - CPU mode setting for WAIT
85476  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
85477  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
85478  */
85479 #define SRC_DOMAIN_MEGA_CPU1_WAIT(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_WAIT_MASK)
85480 
85481 #define SRC_DOMAIN_MEGA_CPU1_STOP_MASK           (0x40U)
85482 #define SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT          (6U)
85483 /*! CPU1_STOP - CPU mode setting for STOP
85484  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
85485  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
85486  */
85487 #define SRC_DOMAIN_MEGA_CPU1_STOP(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_STOP_MASK)
85488 
85489 #define SRC_DOMAIN_MEGA_CPU1_SUSP_MASK           (0x80U)
85490 #define SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT          (7U)
85491 /*! CPU1_SUSP - CPU mode setting for SUSPEND
85492  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
85493  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
85494  */
85495 #define SRC_DOMAIN_MEGA_CPU1_SUSP(x)             (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_SUSP_MASK)
85496 /*! @} */
85497 
85498 /*! @name STAT_MEGA - Slice Status Register */
85499 /*! @{ */
85500 
85501 #define SRC_STAT_MEGA_UNDER_RST_MASK             (0x1U)
85502 #define SRC_STAT_MEGA_UNDER_RST_SHIFT            (0U)
85503 /*! UNDER_RST
85504  *  0b0..the reset is finished
85505  *  0b1..the reset is in process
85506  */
85507 #define SRC_STAT_MEGA_UNDER_RST(x)               (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_UNDER_RST_SHIFT)) & SRC_STAT_MEGA_UNDER_RST_MASK)
85508 
85509 #define SRC_STAT_MEGA_RST_BY_HW_MASK             (0x4U)
85510 #define SRC_STAT_MEGA_RST_BY_HW_SHIFT            (2U)
85511 /*! RST_BY_HW
85512  *  0b0..the reset is not caused by the power mode transfer
85513  *  0b1..the reset is caused by the power mode transfer
85514  */
85515 #define SRC_STAT_MEGA_RST_BY_HW(x)               (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_HW_SHIFT)) & SRC_STAT_MEGA_RST_BY_HW_MASK)
85516 
85517 #define SRC_STAT_MEGA_RST_BY_SW_MASK             (0x8U)
85518 #define SRC_STAT_MEGA_RST_BY_SW_SHIFT            (3U)
85519 /*! RST_BY_SW
85520  *  0b0..the reset is not caused by software setting
85521  *  0b1..the reset is caused by software setting
85522  */
85523 #define SRC_STAT_MEGA_RST_BY_SW(x)               (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_SW_SHIFT)) & SRC_STAT_MEGA_RST_BY_SW_MASK)
85524 /*! @} */
85525 
85526 /*! @name AUTHEN_DISPLAY - Slice Authentication Register */
85527 /*! @{ */
85528 
85529 #define SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK      (0x1U)
85530 #define SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT     (0U)
85531 /*! DOMAIN_MODE
85532  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
85533  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
85534  */
85535 #define SRC_AUTHEN_DISPLAY_DOMAIN_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK)
85536 
85537 #define SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK    (0x2U)
85538 #define SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT   (1U)
85539 /*! SETPOINT_MODE
85540  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
85541  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
85542  */
85543 #define SRC_AUTHEN_DISPLAY_SETPOINT_MODE(x)      (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK)
85544 
85545 #define SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK        (0x80U)
85546 #define SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT       (7U)
85547 /*! LOCK_MODE - Domain/Setpoint mode lock */
85548 #define SRC_AUTHEN_DISPLAY_LOCK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK)
85549 
85550 #define SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK      (0xF00U)
85551 #define SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT     (8U)
85552 #define SRC_AUTHEN_DISPLAY_ASSIGN_LIST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK)
85553 
85554 #define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK      (0x8000U)
85555 #define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT     (15U)
85556 /*! LOCK_ASSIGN - Assign list lock */
85557 #define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK)
85558 
85559 #define SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK       (0xF0000U)
85560 #define SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT      (16U)
85561 /*! WHITE_LIST - Domain ID white list */
85562 #define SRC_AUTHEN_DISPLAY_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK)
85563 
85564 #define SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK        (0x800000U)
85565 #define SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT       (23U)
85566 /*! LOCK_LIST - White list lock */
85567 #define SRC_AUTHEN_DISPLAY_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK)
85568 
85569 #define SRC_AUTHEN_DISPLAY_USER_MASK             (0x1000000U)
85570 #define SRC_AUTHEN_DISPLAY_USER_SHIFT            (24U)
85571 /*! USER - Allow user mode access */
85572 #define SRC_AUTHEN_DISPLAY_USER(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_USER_SHIFT)) & SRC_AUTHEN_DISPLAY_USER_MASK)
85573 
85574 #define SRC_AUTHEN_DISPLAY_NONSECURE_MASK        (0x2000000U)
85575 #define SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT       (25U)
85576 /*! NONSECURE - Allow non-secure mode access */
85577 #define SRC_AUTHEN_DISPLAY_NONSECURE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT)) & SRC_AUTHEN_DISPLAY_NONSECURE_MASK)
85578 
85579 #define SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK     (0x80000000U)
85580 #define SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT    (31U)
85581 /*! LOCK_SETTING - Lock NONSECURE and USER */
85582 #define SRC_AUTHEN_DISPLAY_LOCK_SETTING(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK)
85583 /*! @} */
85584 
85585 /*! @name CTRL_DISPLAY - Slice Control Register */
85586 /*! @{ */
85587 
85588 #define SRC_CTRL_DISPLAY_SW_RESET_MASK           (0x1U)
85589 #define SRC_CTRL_DISPLAY_SW_RESET_SHIFT          (0U)
85590 /*! SW_RESET
85591  *  0b0..do not assert slice software reset
85592  *  0b1..assert slice software reset
85593  */
85594 #define SRC_CTRL_DISPLAY_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_DISPLAY_SW_RESET_SHIFT)) & SRC_CTRL_DISPLAY_SW_RESET_MASK)
85595 /*! @} */
85596 
85597 /*! @name SETPOINT_DISPLAY - Slice Setpoint Config Register */
85598 /*! @{ */
85599 
85600 #define SRC_SETPOINT_DISPLAY_SETPOINT0_MASK      (0x1U)
85601 #define SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT     (0U)
85602 /*! SETPOINT0 - SETPOINT0
85603  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85604  *  0b1..Slice reset will be asserted when system in Setpoint n
85605  */
85606 #define SRC_SETPOINT_DISPLAY_SETPOINT0(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT0_MASK)
85607 
85608 #define SRC_SETPOINT_DISPLAY_SETPOINT1_MASK      (0x2U)
85609 #define SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT     (1U)
85610 /*! SETPOINT1 - SETPOINT1
85611  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85612  *  0b1..Slice reset will be asserted when system in Setpoint n
85613  */
85614 #define SRC_SETPOINT_DISPLAY_SETPOINT1(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT1_MASK)
85615 
85616 #define SRC_SETPOINT_DISPLAY_SETPOINT2_MASK      (0x4U)
85617 #define SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT     (2U)
85618 /*! SETPOINT2 - SETPOINT2
85619  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85620  *  0b1..Slice reset will be asserted when system in Setpoint n
85621  */
85622 #define SRC_SETPOINT_DISPLAY_SETPOINT2(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT2_MASK)
85623 
85624 #define SRC_SETPOINT_DISPLAY_SETPOINT3_MASK      (0x8U)
85625 #define SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT     (3U)
85626 /*! SETPOINT3 - SETPOINT3
85627  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85628  *  0b1..Slice reset will be asserted when system in Setpoint n
85629  */
85630 #define SRC_SETPOINT_DISPLAY_SETPOINT3(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT3_MASK)
85631 
85632 #define SRC_SETPOINT_DISPLAY_SETPOINT4_MASK      (0x10U)
85633 #define SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT     (4U)
85634 /*! SETPOINT4 - SETPOINT4
85635  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85636  *  0b1..Slice reset will be asserted when system in Setpoint n
85637  */
85638 #define SRC_SETPOINT_DISPLAY_SETPOINT4(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT4_MASK)
85639 
85640 #define SRC_SETPOINT_DISPLAY_SETPOINT5_MASK      (0x20U)
85641 #define SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT     (5U)
85642 /*! SETPOINT5 - SETPOINT5
85643  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85644  *  0b1..Slice reset will be asserted when system in Setpoint n
85645  */
85646 #define SRC_SETPOINT_DISPLAY_SETPOINT5(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT5_MASK)
85647 
85648 #define SRC_SETPOINT_DISPLAY_SETPOINT6_MASK      (0x40U)
85649 #define SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT     (6U)
85650 /*! SETPOINT6 - SETPOINT6
85651  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85652  *  0b1..Slice reset will be asserted when system in Setpoint n
85653  */
85654 #define SRC_SETPOINT_DISPLAY_SETPOINT6(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT6_MASK)
85655 
85656 #define SRC_SETPOINT_DISPLAY_SETPOINT7_MASK      (0x80U)
85657 #define SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT     (7U)
85658 /*! SETPOINT7 - SETPOINT7
85659  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85660  *  0b1..Slice reset will be asserted when system in Setpoint n
85661  */
85662 #define SRC_SETPOINT_DISPLAY_SETPOINT7(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT7_MASK)
85663 
85664 #define SRC_SETPOINT_DISPLAY_SETPOINT8_MASK      (0x100U)
85665 #define SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT     (8U)
85666 /*! SETPOINT8 - SETPOINT8
85667  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85668  *  0b1..Slice reset will be asserted when system in Setpoint n
85669  */
85670 #define SRC_SETPOINT_DISPLAY_SETPOINT8(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT8_MASK)
85671 
85672 #define SRC_SETPOINT_DISPLAY_SETPOINT9_MASK      (0x200U)
85673 #define SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT     (9U)
85674 /*! SETPOINT9 - SETPOINT9
85675  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85676  *  0b1..Slice reset will be asserted when system in Setpoint n
85677  */
85678 #define SRC_SETPOINT_DISPLAY_SETPOINT9(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT9_MASK)
85679 
85680 #define SRC_SETPOINT_DISPLAY_SETPOINT10_MASK     (0x400U)
85681 #define SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT    (10U)
85682 /*! SETPOINT10 - SETPOINT10
85683  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85684  *  0b1..Slice reset will be asserted when system in Setpoint n
85685  */
85686 #define SRC_SETPOINT_DISPLAY_SETPOINT10(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT10_MASK)
85687 
85688 #define SRC_SETPOINT_DISPLAY_SETPOINT11_MASK     (0x800U)
85689 #define SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT    (11U)
85690 /*! SETPOINT11 - SETPOINT11
85691  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85692  *  0b1..Slice reset will be asserted when system in Setpoint n
85693  */
85694 #define SRC_SETPOINT_DISPLAY_SETPOINT11(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT11_MASK)
85695 
85696 #define SRC_SETPOINT_DISPLAY_SETPOINT12_MASK     (0x1000U)
85697 #define SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT    (12U)
85698 /*! SETPOINT12 - SETPOINT12
85699  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85700  *  0b1..Slice reset will be asserted when system in Setpoint n
85701  */
85702 #define SRC_SETPOINT_DISPLAY_SETPOINT12(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT12_MASK)
85703 
85704 #define SRC_SETPOINT_DISPLAY_SETPOINT13_MASK     (0x2000U)
85705 #define SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT    (13U)
85706 /*! SETPOINT13 - SETPOINT13
85707  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85708  *  0b1..Slice reset will be asserted when system in Setpoint n
85709  */
85710 #define SRC_SETPOINT_DISPLAY_SETPOINT13(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT13_MASK)
85711 
85712 #define SRC_SETPOINT_DISPLAY_SETPOINT14_MASK     (0x4000U)
85713 #define SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT    (14U)
85714 /*! SETPOINT14 - SETPOINT14
85715  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85716  *  0b1..Slice reset will be asserted when system in Setpoint n
85717  */
85718 #define SRC_SETPOINT_DISPLAY_SETPOINT14(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT14_MASK)
85719 
85720 #define SRC_SETPOINT_DISPLAY_SETPOINT15_MASK     (0x8000U)
85721 #define SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT    (15U)
85722 /*! SETPOINT15 - SETPOINT15
85723  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85724  *  0b1..Slice reset will be asserted when system in Setpoint n
85725  */
85726 #define SRC_SETPOINT_DISPLAY_SETPOINT15(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT15_MASK)
85727 /*! @} */
85728 
85729 /*! @name DOMAIN_DISPLAY - Slice Domain Config Register */
85730 /*! @{ */
85731 
85732 #define SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK         (0x1U)
85733 #define SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT        (0U)
85734 /*! CPU0_RUN - CPU mode setting for RUN
85735  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
85736  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
85737  */
85738 #define SRC_DOMAIN_DISPLAY_CPU0_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK)
85739 
85740 #define SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK        (0x2U)
85741 #define SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT       (1U)
85742 /*! CPU0_WAIT - CPU mode setting for WAIT
85743  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
85744  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
85745  */
85746 #define SRC_DOMAIN_DISPLAY_CPU0_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK)
85747 
85748 #define SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK        (0x4U)
85749 #define SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT       (2U)
85750 /*! CPU0_STOP - CPU mode setting for STOP
85751  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
85752  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
85753  */
85754 #define SRC_DOMAIN_DISPLAY_CPU0_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK)
85755 
85756 #define SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK        (0x8U)
85757 #define SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT       (3U)
85758 /*! CPU0_SUSP - CPU mode setting for SUSPEND
85759  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
85760  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
85761  */
85762 #define SRC_DOMAIN_DISPLAY_CPU0_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK)
85763 
85764 #define SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK         (0x10U)
85765 #define SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT        (4U)
85766 /*! CPU1_RUN - CPU mode setting for RUN
85767  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
85768  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
85769  */
85770 #define SRC_DOMAIN_DISPLAY_CPU1_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK)
85771 
85772 #define SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK        (0x20U)
85773 #define SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT       (5U)
85774 /*! CPU1_WAIT - CPU mode setting for WAIT
85775  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
85776  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
85777  */
85778 #define SRC_DOMAIN_DISPLAY_CPU1_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK)
85779 
85780 #define SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK        (0x40U)
85781 #define SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT       (6U)
85782 /*! CPU1_STOP - CPU mode setting for STOP
85783  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
85784  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
85785  */
85786 #define SRC_DOMAIN_DISPLAY_CPU1_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK)
85787 
85788 #define SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK        (0x80U)
85789 #define SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT       (7U)
85790 /*! CPU1_SUSP - CPU mode setting for SUSPEND
85791  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
85792  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
85793  */
85794 #define SRC_DOMAIN_DISPLAY_CPU1_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK)
85795 /*! @} */
85796 
85797 /*! @name STAT_DISPLAY - Slice Status Register */
85798 /*! @{ */
85799 
85800 #define SRC_STAT_DISPLAY_UNDER_RST_MASK          (0x1U)
85801 #define SRC_STAT_DISPLAY_UNDER_RST_SHIFT         (0U)
85802 /*! UNDER_RST
85803  *  0b0..the reset is finished
85804  *  0b1..the reset is in process
85805  */
85806 #define SRC_STAT_DISPLAY_UNDER_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_UNDER_RST_SHIFT)) & SRC_STAT_DISPLAY_UNDER_RST_MASK)
85807 
85808 #define SRC_STAT_DISPLAY_RST_BY_HW_MASK          (0x4U)
85809 #define SRC_STAT_DISPLAY_RST_BY_HW_SHIFT         (2U)
85810 /*! RST_BY_HW
85811  *  0b0..the reset is not caused by the power mode transfer
85812  *  0b1..the reset is caused by the power mode transfer
85813  */
85814 #define SRC_STAT_DISPLAY_RST_BY_HW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_HW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_HW_MASK)
85815 
85816 #define SRC_STAT_DISPLAY_RST_BY_SW_MASK          (0x8U)
85817 #define SRC_STAT_DISPLAY_RST_BY_SW_SHIFT         (3U)
85818 /*! RST_BY_SW
85819  *  0b0..the reset is not caused by software setting
85820  *  0b1..the reset is caused by software setting
85821  */
85822 #define SRC_STAT_DISPLAY_RST_BY_SW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_SW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_SW_MASK)
85823 /*! @} */
85824 
85825 /*! @name AUTHEN_WAKEUP - Slice Authentication Register */
85826 /*! @{ */
85827 
85828 #define SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK       (0x1U)
85829 #define SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT      (0U)
85830 /*! DOMAIN_MODE
85831  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
85832  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
85833  */
85834 #define SRC_AUTHEN_WAKEUP_DOMAIN_MODE(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK)
85835 
85836 #define SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK     (0x2U)
85837 #define SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT    (1U)
85838 /*! SETPOINT_MODE
85839  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
85840  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
85841  */
85842 #define SRC_AUTHEN_WAKEUP_SETPOINT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK)
85843 
85844 #define SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK         (0x80U)
85845 #define SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT        (7U)
85846 /*! LOCK_MODE - Domain/Setpoint mode lock */
85847 #define SRC_AUTHEN_WAKEUP_LOCK_MODE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK)
85848 
85849 #define SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK       (0xF00U)
85850 #define SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT      (8U)
85851 #define SRC_AUTHEN_WAKEUP_ASSIGN_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK)
85852 
85853 #define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK       (0x8000U)
85854 #define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT      (15U)
85855 /*! LOCK_ASSIGN - Assign list lock */
85856 #define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK)
85857 
85858 #define SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK        (0xF0000U)
85859 #define SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT       (16U)
85860 /*! WHITE_LIST - Domain ID white list */
85861 #define SRC_AUTHEN_WAKEUP_WHITE_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK)
85862 
85863 #define SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK         (0x800000U)
85864 #define SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT        (23U)
85865 /*! LOCK_LIST - White list lock */
85866 #define SRC_AUTHEN_WAKEUP_LOCK_LIST(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK)
85867 
85868 #define SRC_AUTHEN_WAKEUP_USER_MASK              (0x1000000U)
85869 #define SRC_AUTHEN_WAKEUP_USER_SHIFT             (24U)
85870 /*! USER - Allow user mode access */
85871 #define SRC_AUTHEN_WAKEUP_USER(x)                (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_USER_SHIFT)) & SRC_AUTHEN_WAKEUP_USER_MASK)
85872 
85873 #define SRC_AUTHEN_WAKEUP_NONSECURE_MASK         (0x2000000U)
85874 #define SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT        (25U)
85875 /*! NONSECURE - Allow non-secure mode access */
85876 #define SRC_AUTHEN_WAKEUP_NONSECURE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT)) & SRC_AUTHEN_WAKEUP_NONSECURE_MASK)
85877 
85878 #define SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK      (0x80000000U)
85879 #define SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT     (31U)
85880 /*! LOCK_SETTING - Lock NONSECURE and USER */
85881 #define SRC_AUTHEN_WAKEUP_LOCK_SETTING(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK)
85882 /*! @} */
85883 
85884 /*! @name CTRL_WAKEUP - Slice Control Register */
85885 /*! @{ */
85886 
85887 #define SRC_CTRL_WAKEUP_SW_RESET_MASK            (0x1U)
85888 #define SRC_CTRL_WAKEUP_SW_RESET_SHIFT           (0U)
85889 /*! SW_RESET
85890  *  0b0..do not assert slice software reset
85891  *  0b1..assert slice software reset
85892  */
85893 #define SRC_CTRL_WAKEUP_SW_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_WAKEUP_SW_RESET_SHIFT)) & SRC_CTRL_WAKEUP_SW_RESET_MASK)
85894 /*! @} */
85895 
85896 /*! @name SETPOINT_WAKEUP - Slice Setpoint Config Register */
85897 /*! @{ */
85898 
85899 #define SRC_SETPOINT_WAKEUP_SETPOINT0_MASK       (0x1U)
85900 #define SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT      (0U)
85901 /*! SETPOINT0 - SETPOINT0
85902  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85903  *  0b1..Slice reset will be asserted when system in Setpoint n
85904  */
85905 #define SRC_SETPOINT_WAKEUP_SETPOINT0(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT0_MASK)
85906 
85907 #define SRC_SETPOINT_WAKEUP_SETPOINT1_MASK       (0x2U)
85908 #define SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT      (1U)
85909 /*! SETPOINT1 - SETPOINT1
85910  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85911  *  0b1..Slice reset will be asserted when system in Setpoint n
85912  */
85913 #define SRC_SETPOINT_WAKEUP_SETPOINT1(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT1_MASK)
85914 
85915 #define SRC_SETPOINT_WAKEUP_SETPOINT2_MASK       (0x4U)
85916 #define SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT      (2U)
85917 /*! SETPOINT2 - SETPOINT2
85918  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85919  *  0b1..Slice reset will be asserted when system in Setpoint n
85920  */
85921 #define SRC_SETPOINT_WAKEUP_SETPOINT2(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT2_MASK)
85922 
85923 #define SRC_SETPOINT_WAKEUP_SETPOINT3_MASK       (0x8U)
85924 #define SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT      (3U)
85925 /*! SETPOINT3 - SETPOINT3
85926  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85927  *  0b1..Slice reset will be asserted when system in Setpoint n
85928  */
85929 #define SRC_SETPOINT_WAKEUP_SETPOINT3(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT3_MASK)
85930 
85931 #define SRC_SETPOINT_WAKEUP_SETPOINT4_MASK       (0x10U)
85932 #define SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT      (4U)
85933 /*! SETPOINT4 - SETPOINT4
85934  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85935  *  0b1..Slice reset will be asserted when system in Setpoint n
85936  */
85937 #define SRC_SETPOINT_WAKEUP_SETPOINT4(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT4_MASK)
85938 
85939 #define SRC_SETPOINT_WAKEUP_SETPOINT5_MASK       (0x20U)
85940 #define SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT      (5U)
85941 /*! SETPOINT5 - SETPOINT5
85942  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85943  *  0b1..Slice reset will be asserted when system in Setpoint n
85944  */
85945 #define SRC_SETPOINT_WAKEUP_SETPOINT5(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT5_MASK)
85946 
85947 #define SRC_SETPOINT_WAKEUP_SETPOINT6_MASK       (0x40U)
85948 #define SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT      (6U)
85949 /*! SETPOINT6 - SETPOINT6
85950  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85951  *  0b1..Slice reset will be asserted when system in Setpoint n
85952  */
85953 #define SRC_SETPOINT_WAKEUP_SETPOINT6(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT6_MASK)
85954 
85955 #define SRC_SETPOINT_WAKEUP_SETPOINT7_MASK       (0x80U)
85956 #define SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT      (7U)
85957 /*! SETPOINT7 - SETPOINT7
85958  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85959  *  0b1..Slice reset will be asserted when system in Setpoint n
85960  */
85961 #define SRC_SETPOINT_WAKEUP_SETPOINT7(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT7_MASK)
85962 
85963 #define SRC_SETPOINT_WAKEUP_SETPOINT8_MASK       (0x100U)
85964 #define SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT      (8U)
85965 /*! SETPOINT8 - SETPOINT8
85966  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85967  *  0b1..Slice reset will be asserted when system in Setpoint n
85968  */
85969 #define SRC_SETPOINT_WAKEUP_SETPOINT8(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT8_MASK)
85970 
85971 #define SRC_SETPOINT_WAKEUP_SETPOINT9_MASK       (0x200U)
85972 #define SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT      (9U)
85973 /*! SETPOINT9 - SETPOINT9
85974  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85975  *  0b1..Slice reset will be asserted when system in Setpoint n
85976  */
85977 #define SRC_SETPOINT_WAKEUP_SETPOINT9(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT9_MASK)
85978 
85979 #define SRC_SETPOINT_WAKEUP_SETPOINT10_MASK      (0x400U)
85980 #define SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT     (10U)
85981 /*! SETPOINT10 - SETPOINT10
85982  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85983  *  0b1..Slice reset will be asserted when system in Setpoint n
85984  */
85985 #define SRC_SETPOINT_WAKEUP_SETPOINT10(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT10_MASK)
85986 
85987 #define SRC_SETPOINT_WAKEUP_SETPOINT11_MASK      (0x800U)
85988 #define SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT     (11U)
85989 /*! SETPOINT11 - SETPOINT11
85990  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85991  *  0b1..Slice reset will be asserted when system in Setpoint n
85992  */
85993 #define SRC_SETPOINT_WAKEUP_SETPOINT11(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT11_MASK)
85994 
85995 #define SRC_SETPOINT_WAKEUP_SETPOINT12_MASK      (0x1000U)
85996 #define SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT     (12U)
85997 /*! SETPOINT12 - SETPOINT12
85998  *  0b0..Slice reset will be de-asserted when system in Setpoint n
85999  *  0b1..Slice reset will be asserted when system in Setpoint n
86000  */
86001 #define SRC_SETPOINT_WAKEUP_SETPOINT12(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT12_MASK)
86002 
86003 #define SRC_SETPOINT_WAKEUP_SETPOINT13_MASK      (0x2000U)
86004 #define SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT     (13U)
86005 /*! SETPOINT13 - SETPOINT13
86006  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86007  *  0b1..Slice reset will be asserted when system in Setpoint n
86008  */
86009 #define SRC_SETPOINT_WAKEUP_SETPOINT13(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT13_MASK)
86010 
86011 #define SRC_SETPOINT_WAKEUP_SETPOINT14_MASK      (0x4000U)
86012 #define SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT     (14U)
86013 /*! SETPOINT14 - SETPOINT14
86014  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86015  *  0b1..Slice reset will be asserted when system in Setpoint n
86016  */
86017 #define SRC_SETPOINT_WAKEUP_SETPOINT14(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT14_MASK)
86018 
86019 #define SRC_SETPOINT_WAKEUP_SETPOINT15_MASK      (0x8000U)
86020 #define SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT     (15U)
86021 /*! SETPOINT15 - SETPOINT15
86022  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86023  *  0b1..Slice reset will be asserted when system in Setpoint n
86024  */
86025 #define SRC_SETPOINT_WAKEUP_SETPOINT15(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT15_MASK)
86026 /*! @} */
86027 
86028 /*! @name DOMAIN_WAKEUP - Slice Domain Config Register */
86029 /*! @{ */
86030 
86031 #define SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK          (0x1U)
86032 #define SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT         (0U)
86033 /*! CPU0_RUN - CPU mode setting for RUN
86034  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
86035  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
86036  */
86037 #define SRC_DOMAIN_WAKEUP_CPU0_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK)
86038 
86039 #define SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK         (0x2U)
86040 #define SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT        (1U)
86041 /*! CPU0_WAIT - CPU mode setting for WAIT
86042  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
86043  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
86044  */
86045 #define SRC_DOMAIN_WAKEUP_CPU0_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK)
86046 
86047 #define SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK         (0x4U)
86048 #define SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT        (2U)
86049 /*! CPU0_STOP - CPU mode setting for STOP
86050  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
86051  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
86052  */
86053 #define SRC_DOMAIN_WAKEUP_CPU0_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK)
86054 
86055 #define SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK         (0x8U)
86056 #define SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT        (3U)
86057 /*! CPU0_SUSP - CPU mode setting for SUSPEND
86058  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
86059  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
86060  */
86061 #define SRC_DOMAIN_WAKEUP_CPU0_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK)
86062 
86063 #define SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK          (0x10U)
86064 #define SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT         (4U)
86065 /*! CPU1_RUN - CPU mode setting for RUN
86066  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
86067  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
86068  */
86069 #define SRC_DOMAIN_WAKEUP_CPU1_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK)
86070 
86071 #define SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK         (0x20U)
86072 #define SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT        (5U)
86073 /*! CPU1_WAIT - CPU mode setting for WAIT
86074  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
86075  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
86076  */
86077 #define SRC_DOMAIN_WAKEUP_CPU1_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK)
86078 
86079 #define SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK         (0x40U)
86080 #define SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT        (6U)
86081 /*! CPU1_STOP - CPU mode setting for STOP
86082  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
86083  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
86084  */
86085 #define SRC_DOMAIN_WAKEUP_CPU1_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK)
86086 
86087 #define SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK         (0x80U)
86088 #define SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT        (7U)
86089 /*! CPU1_SUSP - CPU mode setting for SUSPEND
86090  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
86091  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
86092  */
86093 #define SRC_DOMAIN_WAKEUP_CPU1_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK)
86094 /*! @} */
86095 
86096 /*! @name STAT_WAKEUP - Slice Status Register */
86097 /*! @{ */
86098 
86099 #define SRC_STAT_WAKEUP_UNDER_RST_MASK           (0x1U)
86100 #define SRC_STAT_WAKEUP_UNDER_RST_SHIFT          (0U)
86101 /*! UNDER_RST
86102  *  0b0..the reset is finished
86103  *  0b1..the reset is in process
86104  */
86105 #define SRC_STAT_WAKEUP_UNDER_RST(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_UNDER_RST_SHIFT)) & SRC_STAT_WAKEUP_UNDER_RST_MASK)
86106 
86107 #define SRC_STAT_WAKEUP_RST_BY_HW_MASK           (0x4U)
86108 #define SRC_STAT_WAKEUP_RST_BY_HW_SHIFT          (2U)
86109 /*! RST_BY_HW
86110  *  0b0..the reset is not caused by the power mode transfer
86111  *  0b1..the reset is caused by the power mode transfer
86112  */
86113 #define SRC_STAT_WAKEUP_RST_BY_HW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_HW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_HW_MASK)
86114 
86115 #define SRC_STAT_WAKEUP_RST_BY_SW_MASK           (0x8U)
86116 #define SRC_STAT_WAKEUP_RST_BY_SW_SHIFT          (3U)
86117 /*! RST_BY_SW
86118  *  0b0..the reset is not caused by software setting
86119  *  0b1..the reset is caused by software setting
86120  */
86121 #define SRC_STAT_WAKEUP_RST_BY_SW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_SW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_SW_MASK)
86122 /*! @} */
86123 
86124 /*! @name AUTHEN_M4CORE - Slice Authentication Register */
86125 /*! @{ */
86126 
86127 #define SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK       (0x1U)
86128 #define SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT      (0U)
86129 /*! DOMAIN_MODE
86130  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
86131  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
86132  */
86133 #define SRC_AUTHEN_M4CORE_DOMAIN_MODE(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK)
86134 
86135 #define SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK     (0x2U)
86136 #define SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT    (1U)
86137 /*! SETPOINT_MODE
86138  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
86139  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
86140  */
86141 #define SRC_AUTHEN_M4CORE_SETPOINT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK)
86142 
86143 #define SRC_AUTHEN_M4CORE_LOCK_MODE_MASK         (0x80U)
86144 #define SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT        (7U)
86145 /*! LOCK_MODE - Domain/Setpoint mode lock */
86146 #define SRC_AUTHEN_M4CORE_LOCK_MODE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_MODE_MASK)
86147 
86148 #define SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK       (0xF00U)
86149 #define SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT      (8U)
86150 #define SRC_AUTHEN_M4CORE_ASSIGN_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK)
86151 
86152 #define SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK       (0x8000U)
86153 #define SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT      (15U)
86154 /*! LOCK_ASSIGN - Assign list lock */
86155 #define SRC_AUTHEN_M4CORE_LOCK_ASSIGN(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK)
86156 
86157 #define SRC_AUTHEN_M4CORE_WHITE_LIST_MASK        (0xF0000U)
86158 #define SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT       (16U)
86159 /*! WHITE_LIST - Domain ID white list */
86160 #define SRC_AUTHEN_M4CORE_WHITE_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_WHITE_LIST_MASK)
86161 
86162 #define SRC_AUTHEN_M4CORE_LOCK_LIST_MASK         (0x800000U)
86163 #define SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT        (23U)
86164 /*! LOCK_LIST - White list lock */
86165 #define SRC_AUTHEN_M4CORE_LOCK_LIST(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_LIST_MASK)
86166 
86167 #define SRC_AUTHEN_M4CORE_USER_MASK              (0x1000000U)
86168 #define SRC_AUTHEN_M4CORE_USER_SHIFT             (24U)
86169 /*! USER - Allow user mode access */
86170 #define SRC_AUTHEN_M4CORE_USER(x)                (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_USER_SHIFT)) & SRC_AUTHEN_M4CORE_USER_MASK)
86171 
86172 #define SRC_AUTHEN_M4CORE_NONSECURE_MASK         (0x2000000U)
86173 #define SRC_AUTHEN_M4CORE_NONSECURE_SHIFT        (25U)
86174 /*! NONSECURE - Allow non-secure mode access */
86175 #define SRC_AUTHEN_M4CORE_NONSECURE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M4CORE_NONSECURE_MASK)
86176 
86177 #define SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK      (0x80000000U)
86178 #define SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT     (31U)
86179 /*! LOCK_SETTING - Lock NONSECURE and USER */
86180 #define SRC_AUTHEN_M4CORE_LOCK_SETTING(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK)
86181 /*! @} */
86182 
86183 /*! @name CTRL_M4CORE - Slice Control Register */
86184 /*! @{ */
86185 
86186 #define SRC_CTRL_M4CORE_SW_RESET_MASK            (0x1U)
86187 #define SRC_CTRL_M4CORE_SW_RESET_SHIFT           (0U)
86188 /*! SW_RESET
86189  *  0b0..do not assert slice software reset
86190  *  0b1..assert slice software reset
86191  */
86192 #define SRC_CTRL_M4CORE_SW_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4CORE_SW_RESET_SHIFT)) & SRC_CTRL_M4CORE_SW_RESET_MASK)
86193 /*! @} */
86194 
86195 /*! @name SETPOINT_M4CORE - Slice Setpoint Config Register */
86196 /*! @{ */
86197 
86198 #define SRC_SETPOINT_M4CORE_SETPOINT0_MASK       (0x1U)
86199 #define SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT      (0U)
86200 /*! SETPOINT0 - SETPOINT0
86201  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86202  *  0b1..Slice reset will be asserted when system in Setpoint n
86203  */
86204 #define SRC_SETPOINT_M4CORE_SETPOINT0(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT0_MASK)
86205 
86206 #define SRC_SETPOINT_M4CORE_SETPOINT1_MASK       (0x2U)
86207 #define SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT      (1U)
86208 /*! SETPOINT1 - SETPOINT1
86209  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86210  *  0b1..Slice reset will be asserted when system in Setpoint n
86211  */
86212 #define SRC_SETPOINT_M4CORE_SETPOINT1(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT1_MASK)
86213 
86214 #define SRC_SETPOINT_M4CORE_SETPOINT2_MASK       (0x4U)
86215 #define SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT      (2U)
86216 /*! SETPOINT2 - SETPOINT2
86217  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86218  *  0b1..Slice reset will be asserted when system in Setpoint n
86219  */
86220 #define SRC_SETPOINT_M4CORE_SETPOINT2(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT2_MASK)
86221 
86222 #define SRC_SETPOINT_M4CORE_SETPOINT3_MASK       (0x8U)
86223 #define SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT      (3U)
86224 /*! SETPOINT3 - SETPOINT3
86225  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86226  *  0b1..Slice reset will be asserted when system in Setpoint n
86227  */
86228 #define SRC_SETPOINT_M4CORE_SETPOINT3(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT3_MASK)
86229 
86230 #define SRC_SETPOINT_M4CORE_SETPOINT4_MASK       (0x10U)
86231 #define SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT      (4U)
86232 /*! SETPOINT4 - SETPOINT4
86233  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86234  *  0b1..Slice reset will be asserted when system in Setpoint n
86235  */
86236 #define SRC_SETPOINT_M4CORE_SETPOINT4(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT4_MASK)
86237 
86238 #define SRC_SETPOINT_M4CORE_SETPOINT5_MASK       (0x20U)
86239 #define SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT      (5U)
86240 /*! SETPOINT5 - SETPOINT5
86241  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86242  *  0b1..Slice reset will be asserted when system in Setpoint n
86243  */
86244 #define SRC_SETPOINT_M4CORE_SETPOINT5(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT5_MASK)
86245 
86246 #define SRC_SETPOINT_M4CORE_SETPOINT6_MASK       (0x40U)
86247 #define SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT      (6U)
86248 /*! SETPOINT6 - SETPOINT6
86249  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86250  *  0b1..Slice reset will be asserted when system in Setpoint n
86251  */
86252 #define SRC_SETPOINT_M4CORE_SETPOINT6(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT6_MASK)
86253 
86254 #define SRC_SETPOINT_M4CORE_SETPOINT7_MASK       (0x80U)
86255 #define SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT      (7U)
86256 /*! SETPOINT7 - SETPOINT7
86257  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86258  *  0b1..Slice reset will be asserted when system in Setpoint n
86259  */
86260 #define SRC_SETPOINT_M4CORE_SETPOINT7(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT7_MASK)
86261 
86262 #define SRC_SETPOINT_M4CORE_SETPOINT8_MASK       (0x100U)
86263 #define SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT      (8U)
86264 /*! SETPOINT8 - SETPOINT8
86265  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86266  *  0b1..Slice reset will be asserted when system in Setpoint n
86267  */
86268 #define SRC_SETPOINT_M4CORE_SETPOINT8(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT8_MASK)
86269 
86270 #define SRC_SETPOINT_M4CORE_SETPOINT9_MASK       (0x200U)
86271 #define SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT      (9U)
86272 /*! SETPOINT9 - SETPOINT9
86273  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86274  *  0b1..Slice reset will be asserted when system in Setpoint n
86275  */
86276 #define SRC_SETPOINT_M4CORE_SETPOINT9(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT9_MASK)
86277 
86278 #define SRC_SETPOINT_M4CORE_SETPOINT10_MASK      (0x400U)
86279 #define SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT     (10U)
86280 /*! SETPOINT10 - SETPOINT10
86281  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86282  *  0b1..Slice reset will be asserted when system in Setpoint n
86283  */
86284 #define SRC_SETPOINT_M4CORE_SETPOINT10(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT10_MASK)
86285 
86286 #define SRC_SETPOINT_M4CORE_SETPOINT11_MASK      (0x800U)
86287 #define SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT     (11U)
86288 /*! SETPOINT11 - SETPOINT11
86289  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86290  *  0b1..Slice reset will be asserted when system in Setpoint n
86291  */
86292 #define SRC_SETPOINT_M4CORE_SETPOINT11(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT11_MASK)
86293 
86294 #define SRC_SETPOINT_M4CORE_SETPOINT12_MASK      (0x1000U)
86295 #define SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT     (12U)
86296 /*! SETPOINT12 - SETPOINT12
86297  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86298  *  0b1..Slice reset will be asserted when system in Setpoint n
86299  */
86300 #define SRC_SETPOINT_M4CORE_SETPOINT12(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT12_MASK)
86301 
86302 #define SRC_SETPOINT_M4CORE_SETPOINT13_MASK      (0x2000U)
86303 #define SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT     (13U)
86304 /*! SETPOINT13 - SETPOINT13
86305  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86306  *  0b1..Slice reset will be asserted when system in Setpoint n
86307  */
86308 #define SRC_SETPOINT_M4CORE_SETPOINT13(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT13_MASK)
86309 
86310 #define SRC_SETPOINT_M4CORE_SETPOINT14_MASK      (0x4000U)
86311 #define SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT     (14U)
86312 /*! SETPOINT14 - SETPOINT14
86313  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86314  *  0b1..Slice reset will be asserted when system in Setpoint n
86315  */
86316 #define SRC_SETPOINT_M4CORE_SETPOINT14(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT14_MASK)
86317 
86318 #define SRC_SETPOINT_M4CORE_SETPOINT15_MASK      (0x8000U)
86319 #define SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT     (15U)
86320 /*! SETPOINT15 - SETPOINT15
86321  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86322  *  0b1..Slice reset will be asserted when system in Setpoint n
86323  */
86324 #define SRC_SETPOINT_M4CORE_SETPOINT15(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT15_MASK)
86325 /*! @} */
86326 
86327 /*! @name DOMAIN_M4CORE - Slice Domain Config Register */
86328 /*! @{ */
86329 
86330 #define SRC_DOMAIN_M4CORE_CPU0_RUN_MASK          (0x1U)
86331 #define SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT         (0U)
86332 /*! CPU0_RUN - CPU mode setting for RUN
86333  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
86334  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
86335  */
86336 #define SRC_DOMAIN_M4CORE_CPU0_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_RUN_MASK)
86337 
86338 #define SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK         (0x2U)
86339 #define SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT        (1U)
86340 /*! CPU0_WAIT - CPU mode setting for WAIT
86341  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
86342  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
86343  */
86344 #define SRC_DOMAIN_M4CORE_CPU0_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK)
86345 
86346 #define SRC_DOMAIN_M4CORE_CPU0_STOP_MASK         (0x4U)
86347 #define SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT        (2U)
86348 /*! CPU0_STOP - CPU mode setting for STOP
86349  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
86350  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
86351  */
86352 #define SRC_DOMAIN_M4CORE_CPU0_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_STOP_MASK)
86353 
86354 #define SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK         (0x8U)
86355 #define SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT        (3U)
86356 /*! CPU0_SUSP - CPU mode setting for SUSPEND
86357  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
86358  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
86359  */
86360 #define SRC_DOMAIN_M4CORE_CPU0_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK)
86361 
86362 #define SRC_DOMAIN_M4CORE_CPU1_RUN_MASK          (0x10U)
86363 #define SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT         (4U)
86364 /*! CPU1_RUN - CPU mode setting for RUN
86365  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
86366  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
86367  */
86368 #define SRC_DOMAIN_M4CORE_CPU1_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_RUN_MASK)
86369 
86370 #define SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK         (0x20U)
86371 #define SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT        (5U)
86372 /*! CPU1_WAIT - CPU mode setting for WAIT
86373  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
86374  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
86375  */
86376 #define SRC_DOMAIN_M4CORE_CPU1_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK)
86377 
86378 #define SRC_DOMAIN_M4CORE_CPU1_STOP_MASK         (0x40U)
86379 #define SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT        (6U)
86380 /*! CPU1_STOP - CPU mode setting for STOP
86381  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
86382  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
86383  */
86384 #define SRC_DOMAIN_M4CORE_CPU1_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_STOP_MASK)
86385 
86386 #define SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK         (0x80U)
86387 #define SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT        (7U)
86388 /*! CPU1_SUSP - CPU mode setting for SUSPEND
86389  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
86390  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
86391  */
86392 #define SRC_DOMAIN_M4CORE_CPU1_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK)
86393 /*! @} */
86394 
86395 /*! @name STAT_M4CORE - Slice Status Register */
86396 /*! @{ */
86397 
86398 #define SRC_STAT_M4CORE_UNDER_RST_MASK           (0x1U)
86399 #define SRC_STAT_M4CORE_UNDER_RST_SHIFT          (0U)
86400 /*! UNDER_RST
86401  *  0b0..the reset is finished
86402  *  0b1..the reset is in process
86403  */
86404 #define SRC_STAT_M4CORE_UNDER_RST(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_UNDER_RST_SHIFT)) & SRC_STAT_M4CORE_UNDER_RST_MASK)
86405 
86406 #define SRC_STAT_M4CORE_RST_BY_HW_MASK           (0x4U)
86407 #define SRC_STAT_M4CORE_RST_BY_HW_SHIFT          (2U)
86408 /*! RST_BY_HW
86409  *  0b0..the reset is not caused by the power mode transfer
86410  *  0b1..the reset is caused by the power mode transfer
86411  */
86412 #define SRC_STAT_M4CORE_RST_BY_HW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_HW_MASK)
86413 
86414 #define SRC_STAT_M4CORE_RST_BY_SW_MASK           (0x8U)
86415 #define SRC_STAT_M4CORE_RST_BY_SW_SHIFT          (3U)
86416 /*! RST_BY_SW
86417  *  0b0..the reset is not caused by software setting
86418  *  0b1..the reset is caused by software setting
86419  */
86420 #define SRC_STAT_M4CORE_RST_BY_SW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_SW_MASK)
86421 /*! @} */
86422 
86423 /*! @name AUTHEN_M7CORE - Slice Authentication Register */
86424 /*! @{ */
86425 
86426 #define SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK       (0x1U)
86427 #define SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT      (0U)
86428 /*! DOMAIN_MODE
86429  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
86430  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
86431  */
86432 #define SRC_AUTHEN_M7CORE_DOMAIN_MODE(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK)
86433 
86434 #define SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK     (0x2U)
86435 #define SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT    (1U)
86436 /*! SETPOINT_MODE
86437  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
86438  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
86439  */
86440 #define SRC_AUTHEN_M7CORE_SETPOINT_MODE(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK)
86441 
86442 #define SRC_AUTHEN_M7CORE_LOCK_MODE_MASK         (0x80U)
86443 #define SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT        (7U)
86444 /*! LOCK_MODE - Domain/Setpoint mode lock */
86445 #define SRC_AUTHEN_M7CORE_LOCK_MODE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_MODE_MASK)
86446 
86447 #define SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK       (0xF00U)
86448 #define SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT      (8U)
86449 #define SRC_AUTHEN_M7CORE_ASSIGN_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK)
86450 
86451 #define SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK       (0x8000U)
86452 #define SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT      (15U)
86453 /*! LOCK_ASSIGN - Assign list lock */
86454 #define SRC_AUTHEN_M7CORE_LOCK_ASSIGN(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK)
86455 
86456 #define SRC_AUTHEN_M7CORE_WHITE_LIST_MASK        (0xF0000U)
86457 #define SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT       (16U)
86458 /*! WHITE_LIST - Domain ID white list */
86459 #define SRC_AUTHEN_M7CORE_WHITE_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_WHITE_LIST_MASK)
86460 
86461 #define SRC_AUTHEN_M7CORE_LOCK_LIST_MASK         (0x800000U)
86462 #define SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT        (23U)
86463 /*! LOCK_LIST - White list lock */
86464 #define SRC_AUTHEN_M7CORE_LOCK_LIST(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_LIST_MASK)
86465 
86466 #define SRC_AUTHEN_M7CORE_USER_MASK              (0x1000000U)
86467 #define SRC_AUTHEN_M7CORE_USER_SHIFT             (24U)
86468 /*! USER - Allow user mode access */
86469 #define SRC_AUTHEN_M7CORE_USER(x)                (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_USER_SHIFT)) & SRC_AUTHEN_M7CORE_USER_MASK)
86470 
86471 #define SRC_AUTHEN_M7CORE_NONSECURE_MASK         (0x2000000U)
86472 #define SRC_AUTHEN_M7CORE_NONSECURE_SHIFT        (25U)
86473 /*! NONSECURE - Allow non-secure mode access */
86474 #define SRC_AUTHEN_M7CORE_NONSECURE(x)           (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M7CORE_NONSECURE_MASK)
86475 
86476 #define SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK      (0x80000000U)
86477 #define SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT     (31U)
86478 /*! LOCK_SETTING - Lock NONSECURE and USER */
86479 #define SRC_AUTHEN_M7CORE_LOCK_SETTING(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK)
86480 /*! @} */
86481 
86482 /*! @name CTRL_M7CORE - Slice Control Register */
86483 /*! @{ */
86484 
86485 #define SRC_CTRL_M7CORE_SW_RESET_MASK            (0x1U)
86486 #define SRC_CTRL_M7CORE_SW_RESET_SHIFT           (0U)
86487 /*! SW_RESET
86488  *  0b0..do not assert slice software reset
86489  *  0b1..assert slice software reset
86490  */
86491 #define SRC_CTRL_M7CORE_SW_RESET(x)              (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7CORE_SW_RESET_SHIFT)) & SRC_CTRL_M7CORE_SW_RESET_MASK)
86492 /*! @} */
86493 
86494 /*! @name SETPOINT_M7CORE - Slice Setpoint Config Register */
86495 /*! @{ */
86496 
86497 #define SRC_SETPOINT_M7CORE_SETPOINT0_MASK       (0x1U)
86498 #define SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT      (0U)
86499 /*! SETPOINT0 - SETPOINT0
86500  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86501  *  0b1..Slice reset will be asserted when system in Setpoint n
86502  */
86503 #define SRC_SETPOINT_M7CORE_SETPOINT0(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT0_MASK)
86504 
86505 #define SRC_SETPOINT_M7CORE_SETPOINT1_MASK       (0x2U)
86506 #define SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT      (1U)
86507 /*! SETPOINT1 - SETPOINT1
86508  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86509  *  0b1..Slice reset will be asserted when system in Setpoint n
86510  */
86511 #define SRC_SETPOINT_M7CORE_SETPOINT1(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT1_MASK)
86512 
86513 #define SRC_SETPOINT_M7CORE_SETPOINT2_MASK       (0x4U)
86514 #define SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT      (2U)
86515 /*! SETPOINT2 - SETPOINT2
86516  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86517  *  0b1..Slice reset will be asserted when system in Setpoint n
86518  */
86519 #define SRC_SETPOINT_M7CORE_SETPOINT2(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT2_MASK)
86520 
86521 #define SRC_SETPOINT_M7CORE_SETPOINT3_MASK       (0x8U)
86522 #define SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT      (3U)
86523 /*! SETPOINT3 - SETPOINT3
86524  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86525  *  0b1..Slice reset will be asserted when system in Setpoint n
86526  */
86527 #define SRC_SETPOINT_M7CORE_SETPOINT3(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT3_MASK)
86528 
86529 #define SRC_SETPOINT_M7CORE_SETPOINT4_MASK       (0x10U)
86530 #define SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT      (4U)
86531 /*! SETPOINT4 - SETPOINT4
86532  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86533  *  0b1..Slice reset will be asserted when system in Setpoint n
86534  */
86535 #define SRC_SETPOINT_M7CORE_SETPOINT4(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT4_MASK)
86536 
86537 #define SRC_SETPOINT_M7CORE_SETPOINT5_MASK       (0x20U)
86538 #define SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT      (5U)
86539 /*! SETPOINT5 - SETPOINT5
86540  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86541  *  0b1..Slice reset will be asserted when system in Setpoint n
86542  */
86543 #define SRC_SETPOINT_M7CORE_SETPOINT5(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT5_MASK)
86544 
86545 #define SRC_SETPOINT_M7CORE_SETPOINT6_MASK       (0x40U)
86546 #define SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT      (6U)
86547 /*! SETPOINT6 - SETPOINT6
86548  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86549  *  0b1..Slice reset will be asserted when system in Setpoint n
86550  */
86551 #define SRC_SETPOINT_M7CORE_SETPOINT6(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT6_MASK)
86552 
86553 #define SRC_SETPOINT_M7CORE_SETPOINT7_MASK       (0x80U)
86554 #define SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT      (7U)
86555 /*! SETPOINT7 - SETPOINT7
86556  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86557  *  0b1..Slice reset will be asserted when system in Setpoint n
86558  */
86559 #define SRC_SETPOINT_M7CORE_SETPOINT7(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT7_MASK)
86560 
86561 #define SRC_SETPOINT_M7CORE_SETPOINT8_MASK       (0x100U)
86562 #define SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT      (8U)
86563 /*! SETPOINT8 - SETPOINT8
86564  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86565  *  0b1..Slice reset will be asserted when system in Setpoint n
86566  */
86567 #define SRC_SETPOINT_M7CORE_SETPOINT8(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT8_MASK)
86568 
86569 #define SRC_SETPOINT_M7CORE_SETPOINT9_MASK       (0x200U)
86570 #define SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT      (9U)
86571 /*! SETPOINT9 - SETPOINT9
86572  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86573  *  0b1..Slice reset will be asserted when system in Setpoint n
86574  */
86575 #define SRC_SETPOINT_M7CORE_SETPOINT9(x)         (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT9_MASK)
86576 
86577 #define SRC_SETPOINT_M7CORE_SETPOINT10_MASK      (0x400U)
86578 #define SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT     (10U)
86579 /*! SETPOINT10 - SETPOINT10
86580  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86581  *  0b1..Slice reset will be asserted when system in Setpoint n
86582  */
86583 #define SRC_SETPOINT_M7CORE_SETPOINT10(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT10_MASK)
86584 
86585 #define SRC_SETPOINT_M7CORE_SETPOINT11_MASK      (0x800U)
86586 #define SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT     (11U)
86587 /*! SETPOINT11 - SETPOINT11
86588  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86589  *  0b1..Slice reset will be asserted when system in Setpoint n
86590  */
86591 #define SRC_SETPOINT_M7CORE_SETPOINT11(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT11_MASK)
86592 
86593 #define SRC_SETPOINT_M7CORE_SETPOINT12_MASK      (0x1000U)
86594 #define SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT     (12U)
86595 /*! SETPOINT12 - SETPOINT12
86596  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86597  *  0b1..Slice reset will be asserted when system in Setpoint n
86598  */
86599 #define SRC_SETPOINT_M7CORE_SETPOINT12(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT12_MASK)
86600 
86601 #define SRC_SETPOINT_M7CORE_SETPOINT13_MASK      (0x2000U)
86602 #define SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT     (13U)
86603 /*! SETPOINT13 - SETPOINT13
86604  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86605  *  0b1..Slice reset will be asserted when system in Setpoint n
86606  */
86607 #define SRC_SETPOINT_M7CORE_SETPOINT13(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT13_MASK)
86608 
86609 #define SRC_SETPOINT_M7CORE_SETPOINT14_MASK      (0x4000U)
86610 #define SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT     (14U)
86611 /*! SETPOINT14 - SETPOINT14
86612  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86613  *  0b1..Slice reset will be asserted when system in Setpoint n
86614  */
86615 #define SRC_SETPOINT_M7CORE_SETPOINT14(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT14_MASK)
86616 
86617 #define SRC_SETPOINT_M7CORE_SETPOINT15_MASK      (0x8000U)
86618 #define SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT     (15U)
86619 /*! SETPOINT15 - SETPOINT15
86620  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86621  *  0b1..Slice reset will be asserted when system in Setpoint n
86622  */
86623 #define SRC_SETPOINT_M7CORE_SETPOINT15(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT15_MASK)
86624 /*! @} */
86625 
86626 /*! @name DOMAIN_M7CORE - Slice Domain Config Register */
86627 /*! @{ */
86628 
86629 #define SRC_DOMAIN_M7CORE_CPU0_RUN_MASK          (0x1U)
86630 #define SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT         (0U)
86631 /*! CPU0_RUN - CPU mode setting for RUN
86632  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
86633  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
86634  */
86635 #define SRC_DOMAIN_M7CORE_CPU0_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_RUN_MASK)
86636 
86637 #define SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK         (0x2U)
86638 #define SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT        (1U)
86639 /*! CPU0_WAIT - CPU mode setting for WAIT
86640  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
86641  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
86642  */
86643 #define SRC_DOMAIN_M7CORE_CPU0_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK)
86644 
86645 #define SRC_DOMAIN_M7CORE_CPU0_STOP_MASK         (0x4U)
86646 #define SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT        (2U)
86647 /*! CPU0_STOP - CPU mode setting for STOP
86648  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
86649  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
86650  */
86651 #define SRC_DOMAIN_M7CORE_CPU0_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_STOP_MASK)
86652 
86653 #define SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK         (0x8U)
86654 #define SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT        (3U)
86655 /*! CPU0_SUSP - CPU mode setting for SUSPEND
86656  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
86657  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
86658  */
86659 #define SRC_DOMAIN_M7CORE_CPU0_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK)
86660 
86661 #define SRC_DOMAIN_M7CORE_CPU1_RUN_MASK          (0x10U)
86662 #define SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT         (4U)
86663 /*! CPU1_RUN - CPU mode setting for RUN
86664  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
86665  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
86666  */
86667 #define SRC_DOMAIN_M7CORE_CPU1_RUN(x)            (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_RUN_MASK)
86668 
86669 #define SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK         (0x20U)
86670 #define SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT        (5U)
86671 /*! CPU1_WAIT - CPU mode setting for WAIT
86672  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
86673  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
86674  */
86675 #define SRC_DOMAIN_M7CORE_CPU1_WAIT(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK)
86676 
86677 #define SRC_DOMAIN_M7CORE_CPU1_STOP_MASK         (0x40U)
86678 #define SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT        (6U)
86679 /*! CPU1_STOP - CPU mode setting for STOP
86680  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
86681  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
86682  */
86683 #define SRC_DOMAIN_M7CORE_CPU1_STOP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_STOP_MASK)
86684 
86685 #define SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK         (0x80U)
86686 #define SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT        (7U)
86687 /*! CPU1_SUSP - CPU mode setting for SUSPEND
86688  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
86689  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
86690  */
86691 #define SRC_DOMAIN_M7CORE_CPU1_SUSP(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK)
86692 /*! @} */
86693 
86694 /*! @name STAT_M7CORE - Slice Status Register */
86695 /*! @{ */
86696 
86697 #define SRC_STAT_M7CORE_UNDER_RST_MASK           (0x1U)
86698 #define SRC_STAT_M7CORE_UNDER_RST_SHIFT          (0U)
86699 /*! UNDER_RST
86700  *  0b0..the reset is finished
86701  *  0b1..the reset is in process
86702  */
86703 #define SRC_STAT_M7CORE_UNDER_RST(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_UNDER_RST_SHIFT)) & SRC_STAT_M7CORE_UNDER_RST_MASK)
86704 
86705 #define SRC_STAT_M7CORE_RST_BY_HW_MASK           (0x4U)
86706 #define SRC_STAT_M7CORE_RST_BY_HW_SHIFT          (2U)
86707 /*! RST_BY_HW
86708  *  0b0..the reset is not caused by the power mode transfer
86709  *  0b1..the reset is caused by the power mode transfer
86710  */
86711 #define SRC_STAT_M7CORE_RST_BY_HW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_HW_MASK)
86712 
86713 #define SRC_STAT_M7CORE_RST_BY_SW_MASK           (0x8U)
86714 #define SRC_STAT_M7CORE_RST_BY_SW_SHIFT          (3U)
86715 /*! RST_BY_SW
86716  *  0b0..the reset is not caused by software setting
86717  *  0b1..the reset is caused by software setting
86718  */
86719 #define SRC_STAT_M7CORE_RST_BY_SW(x)             (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_SW_MASK)
86720 /*! @} */
86721 
86722 /*! @name AUTHEN_M4DEBUG - Slice Authentication Register */
86723 /*! @{ */
86724 
86725 #define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK      (0x1U)
86726 #define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT     (0U)
86727 /*! DOMAIN_MODE
86728  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
86729  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
86730  */
86731 #define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK)
86732 
86733 #define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK    (0x2U)
86734 #define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT   (1U)
86735 /*! SETPOINT_MODE
86736  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
86737  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
86738  */
86739 #define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE(x)      (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK)
86740 
86741 #define SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK        (0x80U)
86742 #define SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT       (7U)
86743 /*! LOCK_MODE - Domain/Setpoint mode lock */
86744 #define SRC_AUTHEN_M4DEBUG_LOCK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK)
86745 
86746 #define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK      (0xF00U)
86747 #define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT     (8U)
86748 #define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK)
86749 
86750 #define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK      (0x8000U)
86751 #define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT     (15U)
86752 /*! LOCK_ASSIGN - Assign list lock */
86753 #define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK)
86754 
86755 #define SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK       (0xF0000U)
86756 #define SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT      (16U)
86757 /*! WHITE_LIST - Domain ID white list */
86758 #define SRC_AUTHEN_M4DEBUG_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK)
86759 
86760 #define SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK        (0x800000U)
86761 #define SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT       (23U)
86762 /*! LOCK_LIST - White list lock */
86763 #define SRC_AUTHEN_M4DEBUG_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK)
86764 
86765 #define SRC_AUTHEN_M4DEBUG_USER_MASK             (0x1000000U)
86766 #define SRC_AUTHEN_M4DEBUG_USER_SHIFT            (24U)
86767 /*! USER - Allow user mode access */
86768 #define SRC_AUTHEN_M4DEBUG_USER(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_USER_SHIFT)) & SRC_AUTHEN_M4DEBUG_USER_MASK)
86769 
86770 #define SRC_AUTHEN_M4DEBUG_NONSECURE_MASK        (0x2000000U)
86771 #define SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT       (25U)
86772 /*! NONSECURE - Allow non-secure mode access */
86773 #define SRC_AUTHEN_M4DEBUG_NONSECURE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M4DEBUG_NONSECURE_MASK)
86774 
86775 #define SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK     (0x80000000U)
86776 #define SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT    (31U)
86777 /*! LOCK_SETTING - Lock NONSECURE and USER */
86778 #define SRC_AUTHEN_M4DEBUG_LOCK_SETTING(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK)
86779 /*! @} */
86780 
86781 /*! @name CTRL_M4DEBUG - Slice Control Register */
86782 /*! @{ */
86783 
86784 #define SRC_CTRL_M4DEBUG_SW_RESET_MASK           (0x1U)
86785 #define SRC_CTRL_M4DEBUG_SW_RESET_SHIFT          (0U)
86786 /*! SW_RESET
86787  *  0b0..do not assert slice software reset
86788  *  0b1..assert slice software reset
86789  */
86790 #define SRC_CTRL_M4DEBUG_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M4DEBUG_SW_RESET_MASK)
86791 /*! @} */
86792 
86793 /*! @name SETPOINT_M4DEBUG - Slice Setpoint Config Register */
86794 /*! @{ */
86795 
86796 #define SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK      (0x1U)
86797 #define SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT     (0U)
86798 /*! SETPOINT0 - SETPOINT0
86799  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86800  *  0b1..Slice reset will be asserted when system in Setpoint n
86801  */
86802 #define SRC_SETPOINT_M4DEBUG_SETPOINT0(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK)
86803 
86804 #define SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK      (0x2U)
86805 #define SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT     (1U)
86806 /*! SETPOINT1 - SETPOINT1
86807  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86808  *  0b1..Slice reset will be asserted when system in Setpoint n
86809  */
86810 #define SRC_SETPOINT_M4DEBUG_SETPOINT1(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK)
86811 
86812 #define SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK      (0x4U)
86813 #define SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT     (2U)
86814 /*! SETPOINT2 - SETPOINT2
86815  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86816  *  0b1..Slice reset will be asserted when system in Setpoint n
86817  */
86818 #define SRC_SETPOINT_M4DEBUG_SETPOINT2(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK)
86819 
86820 #define SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK      (0x8U)
86821 #define SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT     (3U)
86822 /*! SETPOINT3 - SETPOINT3
86823  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86824  *  0b1..Slice reset will be asserted when system in Setpoint n
86825  */
86826 #define SRC_SETPOINT_M4DEBUG_SETPOINT3(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK)
86827 
86828 #define SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK      (0x10U)
86829 #define SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT     (4U)
86830 /*! SETPOINT4 - SETPOINT4
86831  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86832  *  0b1..Slice reset will be asserted when system in Setpoint n
86833  */
86834 #define SRC_SETPOINT_M4DEBUG_SETPOINT4(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK)
86835 
86836 #define SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK      (0x20U)
86837 #define SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT     (5U)
86838 /*! SETPOINT5 - SETPOINT5
86839  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86840  *  0b1..Slice reset will be asserted when system in Setpoint n
86841  */
86842 #define SRC_SETPOINT_M4DEBUG_SETPOINT5(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK)
86843 
86844 #define SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK      (0x40U)
86845 #define SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT     (6U)
86846 /*! SETPOINT6 - SETPOINT6
86847  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86848  *  0b1..Slice reset will be asserted when system in Setpoint n
86849  */
86850 #define SRC_SETPOINT_M4DEBUG_SETPOINT6(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK)
86851 
86852 #define SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK      (0x80U)
86853 #define SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT     (7U)
86854 /*! SETPOINT7 - SETPOINT7
86855  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86856  *  0b1..Slice reset will be asserted when system in Setpoint n
86857  */
86858 #define SRC_SETPOINT_M4DEBUG_SETPOINT7(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK)
86859 
86860 #define SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK      (0x100U)
86861 #define SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT     (8U)
86862 /*! SETPOINT8 - SETPOINT8
86863  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86864  *  0b1..Slice reset will be asserted when system in Setpoint n
86865  */
86866 #define SRC_SETPOINT_M4DEBUG_SETPOINT8(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK)
86867 
86868 #define SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK      (0x200U)
86869 #define SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT     (9U)
86870 /*! SETPOINT9 - SETPOINT9
86871  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86872  *  0b1..Slice reset will be asserted when system in Setpoint n
86873  */
86874 #define SRC_SETPOINT_M4DEBUG_SETPOINT9(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK)
86875 
86876 #define SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK     (0x400U)
86877 #define SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT    (10U)
86878 /*! SETPOINT10 - SETPOINT10
86879  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86880  *  0b1..Slice reset will be asserted when system in Setpoint n
86881  */
86882 #define SRC_SETPOINT_M4DEBUG_SETPOINT10(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK)
86883 
86884 #define SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK     (0x800U)
86885 #define SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT    (11U)
86886 /*! SETPOINT11 - SETPOINT11
86887  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86888  *  0b1..Slice reset will be asserted when system in Setpoint n
86889  */
86890 #define SRC_SETPOINT_M4DEBUG_SETPOINT11(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK)
86891 
86892 #define SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK     (0x1000U)
86893 #define SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT    (12U)
86894 /*! SETPOINT12 - SETPOINT12
86895  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86896  *  0b1..Slice reset will be asserted when system in Setpoint n
86897  */
86898 #define SRC_SETPOINT_M4DEBUG_SETPOINT12(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK)
86899 
86900 #define SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK     (0x2000U)
86901 #define SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT    (13U)
86902 /*! SETPOINT13 - SETPOINT13
86903  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86904  *  0b1..Slice reset will be asserted when system in Setpoint n
86905  */
86906 #define SRC_SETPOINT_M4DEBUG_SETPOINT13(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK)
86907 
86908 #define SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK     (0x4000U)
86909 #define SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT    (14U)
86910 /*! SETPOINT14 - SETPOINT14
86911  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86912  *  0b1..Slice reset will be asserted when system in Setpoint n
86913  */
86914 #define SRC_SETPOINT_M4DEBUG_SETPOINT14(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK)
86915 
86916 #define SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK     (0x8000U)
86917 #define SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT    (15U)
86918 /*! SETPOINT15 - SETPOINT15
86919  *  0b0..Slice reset will be de-asserted when system in Setpoint n
86920  *  0b1..Slice reset will be asserted when system in Setpoint n
86921  */
86922 #define SRC_SETPOINT_M4DEBUG_SETPOINT15(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK)
86923 /*! @} */
86924 
86925 /*! @name DOMAIN_M4DEBUG - Slice Domain Config Register */
86926 /*! @{ */
86927 
86928 #define SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK         (0x1U)
86929 #define SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT        (0U)
86930 /*! CPU0_RUN - CPU mode setting for RUN
86931  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
86932  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
86933  */
86934 #define SRC_DOMAIN_M4DEBUG_CPU0_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK)
86935 
86936 #define SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK        (0x2U)
86937 #define SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT       (1U)
86938 /*! CPU0_WAIT - CPU mode setting for WAIT
86939  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
86940  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
86941  */
86942 #define SRC_DOMAIN_M4DEBUG_CPU0_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK)
86943 
86944 #define SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK        (0x4U)
86945 #define SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT       (2U)
86946 /*! CPU0_STOP - CPU mode setting for STOP
86947  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
86948  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
86949  */
86950 #define SRC_DOMAIN_M4DEBUG_CPU0_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK)
86951 
86952 #define SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK        (0x8U)
86953 #define SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT       (3U)
86954 /*! CPU0_SUSP - CPU mode setting for SUSPEND
86955  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
86956  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
86957  */
86958 #define SRC_DOMAIN_M4DEBUG_CPU0_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK)
86959 
86960 #define SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK         (0x10U)
86961 #define SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT        (4U)
86962 /*! CPU1_RUN - CPU mode setting for RUN
86963  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
86964  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
86965  */
86966 #define SRC_DOMAIN_M4DEBUG_CPU1_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK)
86967 
86968 #define SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK        (0x20U)
86969 #define SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT       (5U)
86970 /*! CPU1_WAIT - CPU mode setting for WAIT
86971  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
86972  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
86973  */
86974 #define SRC_DOMAIN_M4DEBUG_CPU1_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK)
86975 
86976 #define SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK        (0x40U)
86977 #define SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT       (6U)
86978 /*! CPU1_STOP - CPU mode setting for STOP
86979  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
86980  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
86981  */
86982 #define SRC_DOMAIN_M4DEBUG_CPU1_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK)
86983 
86984 #define SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK        (0x80U)
86985 #define SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT       (7U)
86986 /*! CPU1_SUSP - CPU mode setting for SUSPEND
86987  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
86988  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
86989  */
86990 #define SRC_DOMAIN_M4DEBUG_CPU1_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK)
86991 /*! @} */
86992 
86993 /*! @name STAT_M4DEBUG - Slice Status Register */
86994 /*! @{ */
86995 
86996 #define SRC_STAT_M4DEBUG_UNDER_RST_MASK          (0x1U)
86997 #define SRC_STAT_M4DEBUG_UNDER_RST_SHIFT         (0U)
86998 /*! UNDER_RST
86999  *  0b0..the reset is finished
87000  *  0b1..the reset is in process
87001  */
87002 #define SRC_STAT_M4DEBUG_UNDER_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M4DEBUG_UNDER_RST_MASK)
87003 
87004 #define SRC_STAT_M4DEBUG_RST_BY_HW_MASK          (0x4U)
87005 #define SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT         (2U)
87006 /*! RST_BY_HW
87007  *  0b0..the reset is not caused by the power mode transfer
87008  *  0b1..the reset is caused by the power mode transfer
87009  */
87010 #define SRC_STAT_M4DEBUG_RST_BY_HW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_HW_MASK)
87011 
87012 #define SRC_STAT_M4DEBUG_RST_BY_SW_MASK          (0x8U)
87013 #define SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT         (3U)
87014 /*! RST_BY_SW
87015  *  0b0..the reset is not caused by software setting
87016  *  0b1..the reset is caused by software setting
87017  */
87018 #define SRC_STAT_M4DEBUG_RST_BY_SW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_SW_MASK)
87019 /*! @} */
87020 
87021 /*! @name AUTHEN_M7DEBUG - Slice Authentication Register */
87022 /*! @{ */
87023 
87024 #define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK      (0x1U)
87025 #define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT     (0U)
87026 /*! DOMAIN_MODE
87027  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
87028  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
87029  */
87030 #define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK)
87031 
87032 #define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK    (0x2U)
87033 #define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT   (1U)
87034 /*! SETPOINT_MODE
87035  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
87036  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
87037  */
87038 #define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE(x)      (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK)
87039 
87040 #define SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK        (0x80U)
87041 #define SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT       (7U)
87042 /*! LOCK_MODE - Domain/Setpoint mode lock */
87043 #define SRC_AUTHEN_M7DEBUG_LOCK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK)
87044 
87045 #define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK      (0xF00U)
87046 #define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT     (8U)
87047 #define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK)
87048 
87049 #define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK      (0x8000U)
87050 #define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT     (15U)
87051 /*! LOCK_ASSIGN - Assign list lock */
87052 #define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK)
87053 
87054 #define SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK       (0xF0000U)
87055 #define SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT      (16U)
87056 /*! WHITE_LIST - Domain ID white list */
87057 #define SRC_AUTHEN_M7DEBUG_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK)
87058 
87059 #define SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK        (0x800000U)
87060 #define SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT       (23U)
87061 /*! LOCK_LIST - White list lock */
87062 #define SRC_AUTHEN_M7DEBUG_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK)
87063 
87064 #define SRC_AUTHEN_M7DEBUG_USER_MASK             (0x1000000U)
87065 #define SRC_AUTHEN_M7DEBUG_USER_SHIFT            (24U)
87066 /*! USER - Allow user mode access */
87067 #define SRC_AUTHEN_M7DEBUG_USER(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_USER_SHIFT)) & SRC_AUTHEN_M7DEBUG_USER_MASK)
87068 
87069 #define SRC_AUTHEN_M7DEBUG_NONSECURE_MASK        (0x2000000U)
87070 #define SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT       (25U)
87071 /*! NONSECURE - Allow non-secure mode access */
87072 #define SRC_AUTHEN_M7DEBUG_NONSECURE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M7DEBUG_NONSECURE_MASK)
87073 
87074 #define SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK     (0x80000000U)
87075 #define SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT    (31U)
87076 /*! LOCK_SETTING - Lock NONSECURE and USER */
87077 #define SRC_AUTHEN_M7DEBUG_LOCK_SETTING(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK)
87078 /*! @} */
87079 
87080 /*! @name CTRL_M7DEBUG - Slice Control Register */
87081 /*! @{ */
87082 
87083 #define SRC_CTRL_M7DEBUG_SW_RESET_MASK           (0x1U)
87084 #define SRC_CTRL_M7DEBUG_SW_RESET_SHIFT          (0U)
87085 /*! SW_RESET
87086  *  0b0..do not assert slice software reset
87087  *  0b1..assert slice software reset
87088  */
87089 #define SRC_CTRL_M7DEBUG_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M7DEBUG_SW_RESET_MASK)
87090 /*! @} */
87091 
87092 /*! @name SETPOINT_M7DEBUG - Slice Setpoint Config Register */
87093 /*! @{ */
87094 
87095 #define SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK      (0x1U)
87096 #define SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT     (0U)
87097 /*! SETPOINT0 - SETPOINT0
87098  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87099  *  0b1..Slice reset will be asserted when system in Setpoint n
87100  */
87101 #define SRC_SETPOINT_M7DEBUG_SETPOINT0(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK)
87102 
87103 #define SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK      (0x2U)
87104 #define SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT     (1U)
87105 /*! SETPOINT1 - SETPOINT1
87106  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87107  *  0b1..Slice reset will be asserted when system in Setpoint n
87108  */
87109 #define SRC_SETPOINT_M7DEBUG_SETPOINT1(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK)
87110 
87111 #define SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK      (0x4U)
87112 #define SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT     (2U)
87113 /*! SETPOINT2 - SETPOINT2
87114  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87115  *  0b1..Slice reset will be asserted when system in Setpoint n
87116  */
87117 #define SRC_SETPOINT_M7DEBUG_SETPOINT2(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK)
87118 
87119 #define SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK      (0x8U)
87120 #define SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT     (3U)
87121 /*! SETPOINT3 - SETPOINT3
87122  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87123  *  0b1..Slice reset will be asserted when system in Setpoint n
87124  */
87125 #define SRC_SETPOINT_M7DEBUG_SETPOINT3(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK)
87126 
87127 #define SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK      (0x10U)
87128 #define SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT     (4U)
87129 /*! SETPOINT4 - SETPOINT4
87130  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87131  *  0b1..Slice reset will be asserted when system in Setpoint n
87132  */
87133 #define SRC_SETPOINT_M7DEBUG_SETPOINT4(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK)
87134 
87135 #define SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK      (0x20U)
87136 #define SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT     (5U)
87137 /*! SETPOINT5 - SETPOINT5
87138  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87139  *  0b1..Slice reset will be asserted when system in Setpoint n
87140  */
87141 #define SRC_SETPOINT_M7DEBUG_SETPOINT5(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK)
87142 
87143 #define SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK      (0x40U)
87144 #define SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT     (6U)
87145 /*! SETPOINT6 - SETPOINT6
87146  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87147  *  0b1..Slice reset will be asserted when system in Setpoint n
87148  */
87149 #define SRC_SETPOINT_M7DEBUG_SETPOINT6(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK)
87150 
87151 #define SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK      (0x80U)
87152 #define SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT     (7U)
87153 /*! SETPOINT7 - SETPOINT7
87154  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87155  *  0b1..Slice reset will be asserted when system in Setpoint n
87156  */
87157 #define SRC_SETPOINT_M7DEBUG_SETPOINT7(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK)
87158 
87159 #define SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK      (0x100U)
87160 #define SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT     (8U)
87161 /*! SETPOINT8 - SETPOINT8
87162  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87163  *  0b1..Slice reset will be asserted when system in Setpoint n
87164  */
87165 #define SRC_SETPOINT_M7DEBUG_SETPOINT8(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK)
87166 
87167 #define SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK      (0x200U)
87168 #define SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT     (9U)
87169 /*! SETPOINT9 - SETPOINT9
87170  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87171  *  0b1..Slice reset will be asserted when system in Setpoint n
87172  */
87173 #define SRC_SETPOINT_M7DEBUG_SETPOINT9(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK)
87174 
87175 #define SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK     (0x400U)
87176 #define SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT    (10U)
87177 /*! SETPOINT10 - SETPOINT10
87178  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87179  *  0b1..Slice reset will be asserted when system in Setpoint n
87180  */
87181 #define SRC_SETPOINT_M7DEBUG_SETPOINT10(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK)
87182 
87183 #define SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK     (0x800U)
87184 #define SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT    (11U)
87185 /*! SETPOINT11 - SETPOINT11
87186  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87187  *  0b1..Slice reset will be asserted when system in Setpoint n
87188  */
87189 #define SRC_SETPOINT_M7DEBUG_SETPOINT11(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK)
87190 
87191 #define SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK     (0x1000U)
87192 #define SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT    (12U)
87193 /*! SETPOINT12 - SETPOINT12
87194  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87195  *  0b1..Slice reset will be asserted when system in Setpoint n
87196  */
87197 #define SRC_SETPOINT_M7DEBUG_SETPOINT12(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK)
87198 
87199 #define SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK     (0x2000U)
87200 #define SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT    (13U)
87201 /*! SETPOINT13 - SETPOINT13
87202  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87203  *  0b1..Slice reset will be asserted when system in Setpoint n
87204  */
87205 #define SRC_SETPOINT_M7DEBUG_SETPOINT13(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK)
87206 
87207 #define SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK     (0x4000U)
87208 #define SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT    (14U)
87209 /*! SETPOINT14 - SETPOINT14
87210  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87211  *  0b1..Slice reset will be asserted when system in Setpoint n
87212  */
87213 #define SRC_SETPOINT_M7DEBUG_SETPOINT14(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK)
87214 
87215 #define SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK     (0x8000U)
87216 #define SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT    (15U)
87217 /*! SETPOINT15 - SETPOINT15
87218  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87219  *  0b1..Slice reset will be asserted when system in Setpoint n
87220  */
87221 #define SRC_SETPOINT_M7DEBUG_SETPOINT15(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK)
87222 /*! @} */
87223 
87224 /*! @name DOMAIN_M7DEBUG - Slice Domain Config Register */
87225 /*! @{ */
87226 
87227 #define SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK         (0x1U)
87228 #define SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT        (0U)
87229 /*! CPU0_RUN - CPU mode setting for RUN
87230  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
87231  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
87232  */
87233 #define SRC_DOMAIN_M7DEBUG_CPU0_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK)
87234 
87235 #define SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK        (0x2U)
87236 #define SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT       (1U)
87237 /*! CPU0_WAIT - CPU mode setting for WAIT
87238  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
87239  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
87240  */
87241 #define SRC_DOMAIN_M7DEBUG_CPU0_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK)
87242 
87243 #define SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK        (0x4U)
87244 #define SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT       (2U)
87245 /*! CPU0_STOP - CPU mode setting for STOP
87246  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
87247  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
87248  */
87249 #define SRC_DOMAIN_M7DEBUG_CPU0_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK)
87250 
87251 #define SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK        (0x8U)
87252 #define SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT       (3U)
87253 /*! CPU0_SUSP - CPU mode setting for SUSPEND
87254  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
87255  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
87256  */
87257 #define SRC_DOMAIN_M7DEBUG_CPU0_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK)
87258 
87259 #define SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK         (0x10U)
87260 #define SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT        (4U)
87261 /*! CPU1_RUN - CPU mode setting for RUN
87262  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
87263  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
87264  */
87265 #define SRC_DOMAIN_M7DEBUG_CPU1_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK)
87266 
87267 #define SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK        (0x20U)
87268 #define SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT       (5U)
87269 /*! CPU1_WAIT - CPU mode setting for WAIT
87270  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
87271  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
87272  */
87273 #define SRC_DOMAIN_M7DEBUG_CPU1_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK)
87274 
87275 #define SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK        (0x40U)
87276 #define SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT       (6U)
87277 /*! CPU1_STOP - CPU mode setting for STOP
87278  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
87279  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
87280  */
87281 #define SRC_DOMAIN_M7DEBUG_CPU1_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK)
87282 
87283 #define SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK        (0x80U)
87284 #define SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT       (7U)
87285 /*! CPU1_SUSP - CPU mode setting for SUSPEND
87286  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
87287  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
87288  */
87289 #define SRC_DOMAIN_M7DEBUG_CPU1_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK)
87290 /*! @} */
87291 
87292 /*! @name STAT_M7DEBUG - Slice Status Register */
87293 /*! @{ */
87294 
87295 #define SRC_STAT_M7DEBUG_UNDER_RST_MASK          (0x1U)
87296 #define SRC_STAT_M7DEBUG_UNDER_RST_SHIFT         (0U)
87297 /*! UNDER_RST
87298  *  0b0..the reset is finished
87299  *  0b1..the reset is in process
87300  */
87301 #define SRC_STAT_M7DEBUG_UNDER_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M7DEBUG_UNDER_RST_MASK)
87302 
87303 #define SRC_STAT_M7DEBUG_RST_BY_HW_MASK          (0x4U)
87304 #define SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT         (2U)
87305 /*! RST_BY_HW
87306  *  0b0..the reset is not caused by the power mode transfer
87307  *  0b1..the reset is caused by the power mode transfer
87308  */
87309 #define SRC_STAT_M7DEBUG_RST_BY_HW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_HW_MASK)
87310 
87311 #define SRC_STAT_M7DEBUG_RST_BY_SW_MASK          (0x8U)
87312 #define SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT         (3U)
87313 /*! RST_BY_SW
87314  *  0b0..the reset is not caused by software setting
87315  *  0b1..the reset is caused by software setting
87316  */
87317 #define SRC_STAT_M7DEBUG_RST_BY_SW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_SW_MASK)
87318 /*! @} */
87319 
87320 /*! @name AUTHEN_USBPHY1 - Slice Authentication Register */
87321 /*! @{ */
87322 
87323 #define SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK      (0x1U)
87324 #define SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT     (0U)
87325 /*! DOMAIN_MODE
87326  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
87327  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
87328  */
87329 #define SRC_AUTHEN_USBPHY1_DOMAIN_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK)
87330 
87331 #define SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK    (0x2U)
87332 #define SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT   (1U)
87333 /*! SETPOINT_MODE
87334  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
87335  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
87336  */
87337 #define SRC_AUTHEN_USBPHY1_SETPOINT_MODE(x)      (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK)
87338 
87339 #define SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK        (0x80U)
87340 #define SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT       (7U)
87341 /*! LOCK_MODE - Domain/Setpoint mode lock */
87342 #define SRC_AUTHEN_USBPHY1_LOCK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK)
87343 
87344 #define SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK      (0xF00U)
87345 #define SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT     (8U)
87346 #define SRC_AUTHEN_USBPHY1_ASSIGN_LIST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK)
87347 
87348 #define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK      (0x8000U)
87349 #define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT     (15U)
87350 /*! LOCK_ASSIGN - Assign list lock */
87351 #define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK)
87352 
87353 #define SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK       (0xF0000U)
87354 #define SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT      (16U)
87355 /*! WHITE_LIST - Domain ID white list */
87356 #define SRC_AUTHEN_USBPHY1_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK)
87357 
87358 #define SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK        (0x800000U)
87359 #define SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT       (23U)
87360 /*! LOCK_LIST - White list lock */
87361 #define SRC_AUTHEN_USBPHY1_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK)
87362 
87363 #define SRC_AUTHEN_USBPHY1_USER_MASK             (0x1000000U)
87364 #define SRC_AUTHEN_USBPHY1_USER_SHIFT            (24U)
87365 /*! USER - Allow user mode access */
87366 #define SRC_AUTHEN_USBPHY1_USER(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_USER_SHIFT)) & SRC_AUTHEN_USBPHY1_USER_MASK)
87367 
87368 #define SRC_AUTHEN_USBPHY1_NONSECURE_MASK        (0x2000000U)
87369 #define SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT       (25U)
87370 /*! NONSECURE - Allow non-secure mode access */
87371 #define SRC_AUTHEN_USBPHY1_NONSECURE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY1_NONSECURE_MASK)
87372 
87373 #define SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK     (0x80000000U)
87374 #define SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT    (31U)
87375 /*! LOCK_SETTING - Lock NONSECURE and USER */
87376 #define SRC_AUTHEN_USBPHY1_LOCK_SETTING(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK)
87377 /*! @} */
87378 
87379 /*! @name CTRL_USBPHY1 - Slice Control Register */
87380 /*! @{ */
87381 
87382 #define SRC_CTRL_USBPHY1_SW_RESET_MASK           (0x1U)
87383 #define SRC_CTRL_USBPHY1_SW_RESET_SHIFT          (0U)
87384 /*! SW_RESET
87385  *  0b0..do not assert slice software reset
87386  *  0b1..assert slice software reset
87387  */
87388 #define SRC_CTRL_USBPHY1_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY1_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY1_SW_RESET_MASK)
87389 /*! @} */
87390 
87391 /*! @name SETPOINT_USBPHY1 - Slice Setpoint Config Register */
87392 /*! @{ */
87393 
87394 #define SRC_SETPOINT_USBPHY1_SETPOINT0_MASK      (0x1U)
87395 #define SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT     (0U)
87396 /*! SETPOINT0 - SETPOINT0
87397  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87398  *  0b1..Slice reset will be asserted when system in Setpoint n
87399  */
87400 #define SRC_SETPOINT_USBPHY1_SETPOINT0(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT0_MASK)
87401 
87402 #define SRC_SETPOINT_USBPHY1_SETPOINT1_MASK      (0x2U)
87403 #define SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT     (1U)
87404 /*! SETPOINT1 - SETPOINT1
87405  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87406  *  0b1..Slice reset will be asserted when system in Setpoint n
87407  */
87408 #define SRC_SETPOINT_USBPHY1_SETPOINT1(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT1_MASK)
87409 
87410 #define SRC_SETPOINT_USBPHY1_SETPOINT2_MASK      (0x4U)
87411 #define SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT     (2U)
87412 /*! SETPOINT2 - SETPOINT2
87413  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87414  *  0b1..Slice reset will be asserted when system in Setpoint n
87415  */
87416 #define SRC_SETPOINT_USBPHY1_SETPOINT2(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT2_MASK)
87417 
87418 #define SRC_SETPOINT_USBPHY1_SETPOINT3_MASK      (0x8U)
87419 #define SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT     (3U)
87420 /*! SETPOINT3 - SETPOINT3
87421  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87422  *  0b1..Slice reset will be asserted when system in Setpoint n
87423  */
87424 #define SRC_SETPOINT_USBPHY1_SETPOINT3(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT3_MASK)
87425 
87426 #define SRC_SETPOINT_USBPHY1_SETPOINT4_MASK      (0x10U)
87427 #define SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT     (4U)
87428 /*! SETPOINT4 - SETPOINT4
87429  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87430  *  0b1..Slice reset will be asserted when system in Setpoint n
87431  */
87432 #define SRC_SETPOINT_USBPHY1_SETPOINT4(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT4_MASK)
87433 
87434 #define SRC_SETPOINT_USBPHY1_SETPOINT5_MASK      (0x20U)
87435 #define SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT     (5U)
87436 /*! SETPOINT5 - SETPOINT5
87437  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87438  *  0b1..Slice reset will be asserted when system in Setpoint n
87439  */
87440 #define SRC_SETPOINT_USBPHY1_SETPOINT5(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT5_MASK)
87441 
87442 #define SRC_SETPOINT_USBPHY1_SETPOINT6_MASK      (0x40U)
87443 #define SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT     (6U)
87444 /*! SETPOINT6 - SETPOINT6
87445  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87446  *  0b1..Slice reset will be asserted when system in Setpoint n
87447  */
87448 #define SRC_SETPOINT_USBPHY1_SETPOINT6(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT6_MASK)
87449 
87450 #define SRC_SETPOINT_USBPHY1_SETPOINT7_MASK      (0x80U)
87451 #define SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT     (7U)
87452 /*! SETPOINT7 - SETPOINT7
87453  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87454  *  0b1..Slice reset will be asserted when system in Setpoint n
87455  */
87456 #define SRC_SETPOINT_USBPHY1_SETPOINT7(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT7_MASK)
87457 
87458 #define SRC_SETPOINT_USBPHY1_SETPOINT8_MASK      (0x100U)
87459 #define SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT     (8U)
87460 /*! SETPOINT8 - SETPOINT8
87461  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87462  *  0b1..Slice reset will be asserted when system in Setpoint n
87463  */
87464 #define SRC_SETPOINT_USBPHY1_SETPOINT8(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT8_MASK)
87465 
87466 #define SRC_SETPOINT_USBPHY1_SETPOINT9_MASK      (0x200U)
87467 #define SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT     (9U)
87468 /*! SETPOINT9 - SETPOINT9
87469  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87470  *  0b1..Slice reset will be asserted when system in Setpoint n
87471  */
87472 #define SRC_SETPOINT_USBPHY1_SETPOINT9(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT9_MASK)
87473 
87474 #define SRC_SETPOINT_USBPHY1_SETPOINT10_MASK     (0x400U)
87475 #define SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT    (10U)
87476 /*! SETPOINT10 - SETPOINT10
87477  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87478  *  0b1..Slice reset will be asserted when system in Setpoint n
87479  */
87480 #define SRC_SETPOINT_USBPHY1_SETPOINT10(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT10_MASK)
87481 
87482 #define SRC_SETPOINT_USBPHY1_SETPOINT11_MASK     (0x800U)
87483 #define SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT    (11U)
87484 /*! SETPOINT11 - SETPOINT11
87485  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87486  *  0b1..Slice reset will be asserted when system in Setpoint n
87487  */
87488 #define SRC_SETPOINT_USBPHY1_SETPOINT11(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT11_MASK)
87489 
87490 #define SRC_SETPOINT_USBPHY1_SETPOINT12_MASK     (0x1000U)
87491 #define SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT    (12U)
87492 /*! SETPOINT12 - SETPOINT12
87493  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87494  *  0b1..Slice reset will be asserted when system in Setpoint n
87495  */
87496 #define SRC_SETPOINT_USBPHY1_SETPOINT12(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT12_MASK)
87497 
87498 #define SRC_SETPOINT_USBPHY1_SETPOINT13_MASK     (0x2000U)
87499 #define SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT    (13U)
87500 /*! SETPOINT13 - SETPOINT13
87501  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87502  *  0b1..Slice reset will be asserted when system in Setpoint n
87503  */
87504 #define SRC_SETPOINT_USBPHY1_SETPOINT13(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT13_MASK)
87505 
87506 #define SRC_SETPOINT_USBPHY1_SETPOINT14_MASK     (0x4000U)
87507 #define SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT    (14U)
87508 /*! SETPOINT14 - SETPOINT14
87509  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87510  *  0b1..Slice reset will be asserted when system in Setpoint n
87511  */
87512 #define SRC_SETPOINT_USBPHY1_SETPOINT14(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT14_MASK)
87513 
87514 #define SRC_SETPOINT_USBPHY1_SETPOINT15_MASK     (0x8000U)
87515 #define SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT    (15U)
87516 /*! SETPOINT15 - SETPOINT15
87517  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87518  *  0b1..Slice reset will be asserted when system in Setpoint n
87519  */
87520 #define SRC_SETPOINT_USBPHY1_SETPOINT15(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT15_MASK)
87521 /*! @} */
87522 
87523 /*! @name DOMAIN_USBPHY1 - Slice Domain Config Register */
87524 /*! @{ */
87525 
87526 #define SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK         (0x1U)
87527 #define SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT        (0U)
87528 /*! CPU0_RUN - CPU mode setting for RUN
87529  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
87530  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
87531  */
87532 #define SRC_DOMAIN_USBPHY1_CPU0_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK)
87533 
87534 #define SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK        (0x2U)
87535 #define SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT       (1U)
87536 /*! CPU0_WAIT - CPU mode setting for WAIT
87537  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
87538  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
87539  */
87540 #define SRC_DOMAIN_USBPHY1_CPU0_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK)
87541 
87542 #define SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK        (0x4U)
87543 #define SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT       (2U)
87544 /*! CPU0_STOP - CPU mode setting for STOP
87545  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
87546  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
87547  */
87548 #define SRC_DOMAIN_USBPHY1_CPU0_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK)
87549 
87550 #define SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK        (0x8U)
87551 #define SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT       (3U)
87552 /*! CPU0_SUSP - CPU mode setting for SUSPEND
87553  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
87554  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
87555  */
87556 #define SRC_DOMAIN_USBPHY1_CPU0_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK)
87557 
87558 #define SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK         (0x10U)
87559 #define SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT        (4U)
87560 /*! CPU1_RUN - CPU mode setting for RUN
87561  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
87562  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
87563  */
87564 #define SRC_DOMAIN_USBPHY1_CPU1_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK)
87565 
87566 #define SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK        (0x20U)
87567 #define SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT       (5U)
87568 /*! CPU1_WAIT - CPU mode setting for WAIT
87569  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
87570  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
87571  */
87572 #define SRC_DOMAIN_USBPHY1_CPU1_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK)
87573 
87574 #define SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK        (0x40U)
87575 #define SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT       (6U)
87576 /*! CPU1_STOP - CPU mode setting for STOP
87577  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
87578  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
87579  */
87580 #define SRC_DOMAIN_USBPHY1_CPU1_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK)
87581 
87582 #define SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK        (0x80U)
87583 #define SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT       (7U)
87584 /*! CPU1_SUSP - CPU mode setting for SUSPEND
87585  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
87586  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
87587  */
87588 #define SRC_DOMAIN_USBPHY1_CPU1_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK)
87589 /*! @} */
87590 
87591 /*! @name STAT_USBPHY1 - Slice Status Register */
87592 /*! @{ */
87593 
87594 #define SRC_STAT_USBPHY1_UNDER_RST_MASK          (0x1U)
87595 #define SRC_STAT_USBPHY1_UNDER_RST_SHIFT         (0U)
87596 /*! UNDER_RST
87597  *  0b0..the reset is finished
87598  *  0b1..the reset is in process
87599  */
87600 #define SRC_STAT_USBPHY1_UNDER_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY1_UNDER_RST_MASK)
87601 
87602 #define SRC_STAT_USBPHY1_RST_BY_HW_MASK          (0x4U)
87603 #define SRC_STAT_USBPHY1_RST_BY_HW_SHIFT         (2U)
87604 /*! RST_BY_HW
87605  *  0b0..the reset is not caused by the power mode transfer
87606  *  0b1..the reset is caused by the power mode transfer
87607  */
87608 #define SRC_STAT_USBPHY1_RST_BY_HW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_HW_MASK)
87609 
87610 #define SRC_STAT_USBPHY1_RST_BY_SW_MASK          (0x8U)
87611 #define SRC_STAT_USBPHY1_RST_BY_SW_SHIFT         (3U)
87612 /*! RST_BY_SW
87613  *  0b0..the reset is not caused by software setting
87614  *  0b1..the reset is caused by software setting
87615  */
87616 #define SRC_STAT_USBPHY1_RST_BY_SW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_SW_MASK)
87617 /*! @} */
87618 
87619 /*! @name AUTHEN_USBPHY2 - Slice Authentication Register */
87620 /*! @{ */
87621 
87622 #define SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK      (0x1U)
87623 #define SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT     (0U)
87624 /*! DOMAIN_MODE
87625  *  0b0..slice hardware reset will NOT be triggered by CPU power mode transition
87626  *  0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
87627  */
87628 #define SRC_AUTHEN_USBPHY2_DOMAIN_MODE(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK)
87629 
87630 #define SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK    (0x2U)
87631 #define SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT   (1U)
87632 /*! SETPOINT_MODE
87633  *  0b0..slice hardware reset will NOT be triggered by Setpoint transition
87634  *  0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
87635  */
87636 #define SRC_AUTHEN_USBPHY2_SETPOINT_MODE(x)      (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK)
87637 
87638 #define SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK        (0x80U)
87639 #define SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT       (7U)
87640 /*! LOCK_MODE - Domain/Setpoint mode lock */
87641 #define SRC_AUTHEN_USBPHY2_LOCK_MODE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK)
87642 
87643 #define SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK      (0xF00U)
87644 #define SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT     (8U)
87645 #define SRC_AUTHEN_USBPHY2_ASSIGN_LIST(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK)
87646 
87647 #define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK      (0x8000U)
87648 #define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT     (15U)
87649 /*! LOCK_ASSIGN - Assign list lock */
87650 #define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN(x)        (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK)
87651 
87652 #define SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK       (0xF0000U)
87653 #define SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT      (16U)
87654 /*! WHITE_LIST - Domain ID white list */
87655 #define SRC_AUTHEN_USBPHY2_WHITE_LIST(x)         (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK)
87656 
87657 #define SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK        (0x800000U)
87658 #define SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT       (23U)
87659 /*! LOCK_LIST - White list lock */
87660 #define SRC_AUTHEN_USBPHY2_LOCK_LIST(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK)
87661 
87662 #define SRC_AUTHEN_USBPHY2_USER_MASK             (0x1000000U)
87663 #define SRC_AUTHEN_USBPHY2_USER_SHIFT            (24U)
87664 /*! USER - Allow user mode access */
87665 #define SRC_AUTHEN_USBPHY2_USER(x)               (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_USER_SHIFT)) & SRC_AUTHEN_USBPHY2_USER_MASK)
87666 
87667 #define SRC_AUTHEN_USBPHY2_NONSECURE_MASK        (0x2000000U)
87668 #define SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT       (25U)
87669 /*! NONSECURE - Allow non-secure mode access */
87670 #define SRC_AUTHEN_USBPHY2_NONSECURE(x)          (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY2_NONSECURE_MASK)
87671 
87672 #define SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK     (0x80000000U)
87673 #define SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT    (31U)
87674 /*! LOCK_SETTING - Lock NONSECURE and USER */
87675 #define SRC_AUTHEN_USBPHY2_LOCK_SETTING(x)       (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK)
87676 /*! @} */
87677 
87678 /*! @name CTRL_USBPHY2 - Slice Control Register */
87679 /*! @{ */
87680 
87681 #define SRC_CTRL_USBPHY2_SW_RESET_MASK           (0x1U)
87682 #define SRC_CTRL_USBPHY2_SW_RESET_SHIFT          (0U)
87683 /*! SW_RESET
87684  *  0b0..do not assert slice software reset
87685  *  0b1..assert slice software reset
87686  */
87687 #define SRC_CTRL_USBPHY2_SW_RESET(x)             (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY2_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY2_SW_RESET_MASK)
87688 /*! @} */
87689 
87690 /*! @name SETPOINT_USBPHY2 - Slice Setpoint Config Register */
87691 /*! @{ */
87692 
87693 #define SRC_SETPOINT_USBPHY2_SETPOINT0_MASK      (0x1U)
87694 #define SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT     (0U)
87695 /*! SETPOINT0 - SETPOINT0
87696  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87697  *  0b1..Slice reset will be asserted when system in Setpoint n
87698  */
87699 #define SRC_SETPOINT_USBPHY2_SETPOINT0(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT0_MASK)
87700 
87701 #define SRC_SETPOINT_USBPHY2_SETPOINT1_MASK      (0x2U)
87702 #define SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT     (1U)
87703 /*! SETPOINT1 - SETPOINT1
87704  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87705  *  0b1..Slice reset will be asserted when system in Setpoint n
87706  */
87707 #define SRC_SETPOINT_USBPHY2_SETPOINT1(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT1_MASK)
87708 
87709 #define SRC_SETPOINT_USBPHY2_SETPOINT2_MASK      (0x4U)
87710 #define SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT     (2U)
87711 /*! SETPOINT2 - SETPOINT2
87712  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87713  *  0b1..Slice reset will be asserted when system in Setpoint n
87714  */
87715 #define SRC_SETPOINT_USBPHY2_SETPOINT2(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT2_MASK)
87716 
87717 #define SRC_SETPOINT_USBPHY2_SETPOINT3_MASK      (0x8U)
87718 #define SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT     (3U)
87719 /*! SETPOINT3 - SETPOINT3
87720  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87721  *  0b1..Slice reset will be asserted when system in Setpoint n
87722  */
87723 #define SRC_SETPOINT_USBPHY2_SETPOINT3(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT3_MASK)
87724 
87725 #define SRC_SETPOINT_USBPHY2_SETPOINT4_MASK      (0x10U)
87726 #define SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT     (4U)
87727 /*! SETPOINT4 - SETPOINT4
87728  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87729  *  0b1..Slice reset will be asserted when system in Setpoint n
87730  */
87731 #define SRC_SETPOINT_USBPHY2_SETPOINT4(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT4_MASK)
87732 
87733 #define SRC_SETPOINT_USBPHY2_SETPOINT5_MASK      (0x20U)
87734 #define SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT     (5U)
87735 /*! SETPOINT5 - SETPOINT5
87736  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87737  *  0b1..Slice reset will be asserted when system in Setpoint n
87738  */
87739 #define SRC_SETPOINT_USBPHY2_SETPOINT5(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT5_MASK)
87740 
87741 #define SRC_SETPOINT_USBPHY2_SETPOINT6_MASK      (0x40U)
87742 #define SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT     (6U)
87743 /*! SETPOINT6 - SETPOINT6
87744  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87745  *  0b1..Slice reset will be asserted when system in Setpoint n
87746  */
87747 #define SRC_SETPOINT_USBPHY2_SETPOINT6(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT6_MASK)
87748 
87749 #define SRC_SETPOINT_USBPHY2_SETPOINT7_MASK      (0x80U)
87750 #define SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT     (7U)
87751 /*! SETPOINT7 - SETPOINT7
87752  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87753  *  0b1..Slice reset will be asserted when system in Setpoint n
87754  */
87755 #define SRC_SETPOINT_USBPHY2_SETPOINT7(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT7_MASK)
87756 
87757 #define SRC_SETPOINT_USBPHY2_SETPOINT8_MASK      (0x100U)
87758 #define SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT     (8U)
87759 /*! SETPOINT8 - SETPOINT8
87760  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87761  *  0b1..Slice reset will be asserted when system in Setpoint n
87762  */
87763 #define SRC_SETPOINT_USBPHY2_SETPOINT8(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT8_MASK)
87764 
87765 #define SRC_SETPOINT_USBPHY2_SETPOINT9_MASK      (0x200U)
87766 #define SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT     (9U)
87767 /*! SETPOINT9 - SETPOINT9
87768  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87769  *  0b1..Slice reset will be asserted when system in Setpoint n
87770  */
87771 #define SRC_SETPOINT_USBPHY2_SETPOINT9(x)        (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT9_MASK)
87772 
87773 #define SRC_SETPOINT_USBPHY2_SETPOINT10_MASK     (0x400U)
87774 #define SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT    (10U)
87775 /*! SETPOINT10 - SETPOINT10
87776  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87777  *  0b1..Slice reset will be asserted when system in Setpoint n
87778  */
87779 #define SRC_SETPOINT_USBPHY2_SETPOINT10(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT10_MASK)
87780 
87781 #define SRC_SETPOINT_USBPHY2_SETPOINT11_MASK     (0x800U)
87782 #define SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT    (11U)
87783 /*! SETPOINT11 - SETPOINT11
87784  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87785  *  0b1..Slice reset will be asserted when system in Setpoint n
87786  */
87787 #define SRC_SETPOINT_USBPHY2_SETPOINT11(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT11_MASK)
87788 
87789 #define SRC_SETPOINT_USBPHY2_SETPOINT12_MASK     (0x1000U)
87790 #define SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT    (12U)
87791 /*! SETPOINT12 - SETPOINT12
87792  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87793  *  0b1..Slice reset will be asserted when system in Setpoint n
87794  */
87795 #define SRC_SETPOINT_USBPHY2_SETPOINT12(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT12_MASK)
87796 
87797 #define SRC_SETPOINT_USBPHY2_SETPOINT13_MASK     (0x2000U)
87798 #define SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT    (13U)
87799 /*! SETPOINT13 - SETPOINT13
87800  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87801  *  0b1..Slice reset will be asserted when system in Setpoint n
87802  */
87803 #define SRC_SETPOINT_USBPHY2_SETPOINT13(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT13_MASK)
87804 
87805 #define SRC_SETPOINT_USBPHY2_SETPOINT14_MASK     (0x4000U)
87806 #define SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT    (14U)
87807 /*! SETPOINT14 - SETPOINT14
87808  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87809  *  0b1..Slice reset will be asserted when system in Setpoint n
87810  */
87811 #define SRC_SETPOINT_USBPHY2_SETPOINT14(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT14_MASK)
87812 
87813 #define SRC_SETPOINT_USBPHY2_SETPOINT15_MASK     (0x8000U)
87814 #define SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT    (15U)
87815 /*! SETPOINT15 - SETPOINT15
87816  *  0b0..Slice reset will be de-asserted when system in Setpoint n
87817  *  0b1..Slice reset will be asserted when system in Setpoint n
87818  */
87819 #define SRC_SETPOINT_USBPHY2_SETPOINT15(x)       (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT15_MASK)
87820 /*! @} */
87821 
87822 /*! @name DOMAIN_USBPHY2 - Slice Domain Config Register */
87823 /*! @{ */
87824 
87825 #define SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK         (0x1U)
87826 #define SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT        (0U)
87827 /*! CPU0_RUN - CPU mode setting for RUN
87828  *  0b0..Slice reset will be de-asserted when CPU0 in RUN mode
87829  *  0b1..Slice reset will be asserted when CPU0 in RUN mode
87830  */
87831 #define SRC_DOMAIN_USBPHY2_CPU0_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK)
87832 
87833 #define SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK        (0x2U)
87834 #define SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT       (1U)
87835 /*! CPU0_WAIT - CPU mode setting for WAIT
87836  *  0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
87837  *  0b1..Slice reset will be asserted when CPU0 in WAIT mode
87838  */
87839 #define SRC_DOMAIN_USBPHY2_CPU0_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK)
87840 
87841 #define SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK        (0x4U)
87842 #define SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT       (2U)
87843 /*! CPU0_STOP - CPU mode setting for STOP
87844  *  0b0..Slice reset will be de-asserted when CPU0 in STOP mode
87845  *  0b1..Slice reset will be asserted when CPU0 in STOP mode
87846  */
87847 #define SRC_DOMAIN_USBPHY2_CPU0_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK)
87848 
87849 #define SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK        (0x8U)
87850 #define SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT       (3U)
87851 /*! CPU0_SUSP - CPU mode setting for SUSPEND
87852  *  0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
87853  *  0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
87854  */
87855 #define SRC_DOMAIN_USBPHY2_CPU0_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK)
87856 
87857 #define SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK         (0x10U)
87858 #define SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT        (4U)
87859 /*! CPU1_RUN - CPU mode setting for RUN
87860  *  0b0..Slice reset will be de-asserted when CPU1 in RUN mode
87861  *  0b1..Slice reset will be asserted when CPU1 in RUN mode
87862  */
87863 #define SRC_DOMAIN_USBPHY2_CPU1_RUN(x)           (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK)
87864 
87865 #define SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK        (0x20U)
87866 #define SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT       (5U)
87867 /*! CPU1_WAIT - CPU mode setting for WAIT
87868  *  0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
87869  *  0b1..Slice reset will be asserted when CPU1 in WAIT mode
87870  */
87871 #define SRC_DOMAIN_USBPHY2_CPU1_WAIT(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK)
87872 
87873 #define SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK        (0x40U)
87874 #define SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT       (6U)
87875 /*! CPU1_STOP - CPU mode setting for STOP
87876  *  0b0..Slice reset will be de-asserted when CPU1 in STOP mode
87877  *  0b1..Slice reset will be asserted when CPU1 in STOP mode
87878  */
87879 #define SRC_DOMAIN_USBPHY2_CPU1_STOP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK)
87880 
87881 #define SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK        (0x80U)
87882 #define SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT       (7U)
87883 /*! CPU1_SUSP - CPU mode setting for SUSPEND
87884  *  0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
87885  *  0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
87886  */
87887 #define SRC_DOMAIN_USBPHY2_CPU1_SUSP(x)          (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK)
87888 /*! @} */
87889 
87890 /*! @name STAT_USBPHY2 - Slice Status Register */
87891 /*! @{ */
87892 
87893 #define SRC_STAT_USBPHY2_UNDER_RST_MASK          (0x1U)
87894 #define SRC_STAT_USBPHY2_UNDER_RST_SHIFT         (0U)
87895 /*! UNDER_RST
87896  *  0b0..the reset is finished
87897  *  0b1..the reset is in process
87898  */
87899 #define SRC_STAT_USBPHY2_UNDER_RST(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY2_UNDER_RST_MASK)
87900 
87901 #define SRC_STAT_USBPHY2_RST_BY_HW_MASK          (0x4U)
87902 #define SRC_STAT_USBPHY2_RST_BY_HW_SHIFT         (2U)
87903 /*! RST_BY_HW
87904  *  0b0..the reset is not caused by the power mode transfer
87905  *  0b1..the reset is caused by the power mode transfer
87906  */
87907 #define SRC_STAT_USBPHY2_RST_BY_HW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_HW_MASK)
87908 
87909 #define SRC_STAT_USBPHY2_RST_BY_SW_MASK          (0x8U)
87910 #define SRC_STAT_USBPHY2_RST_BY_SW_SHIFT         (3U)
87911 /*! RST_BY_SW
87912  *  0b0..the reset is not caused by software setting
87913  *  0b1..the reset is caused by software setting
87914  */
87915 #define SRC_STAT_USBPHY2_RST_BY_SW(x)            (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_SW_MASK)
87916 /*! @} */
87917 
87918 
87919 /*!
87920  * @}
87921  */ /* end of group SRC_Register_Masks */
87922 
87923 
87924 /* SRC - Peripheral instance base addresses */
87925 /** Peripheral SRC base address */
87926 #define SRC_BASE                                 (0x40C04000u)
87927 /** Peripheral SRC base pointer */
87928 #define SRC                                      ((SRC_Type *)SRC_BASE)
87929 /** Array initializer of SRC peripheral base addresses */
87930 #define SRC_BASE_ADDRS                           { SRC_BASE }
87931 /** Array initializer of SRC peripheral base pointers */
87932 #define SRC_BASE_PTRS                            { SRC }
87933 
87934 /*!
87935  * @}
87936  */ /* end of group SRC_Peripheral_Access_Layer */
87937 
87938 
87939 /* ----------------------------------------------------------------------------
87940    -- SSARC_HP Peripheral Access Layer
87941    ---------------------------------------------------------------------------- */
87942 
87943 /*!
87944  * @addtogroup SSARC_HP_Peripheral_Access_Layer SSARC_HP Peripheral Access Layer
87945  * @{
87946  */
87947 
87948 /** SSARC_HP - Register Layout Typedef */
87949 typedef struct {
87950   struct {                                         /* offset: 0x0, array step: 0x10 */
87951     __IO uint32_t SRAM0;                             /**< Description Address Register, array offset: 0x0, array step: 0x10 */
87952     __IO uint32_t SRAM1;                             /**< Description Data Register, array offset: 0x4, array step: 0x10 */
87953     __IO uint32_t SRAM2;                             /**< Description Control Register, array offset: 0x8, array step: 0x10 */
87954          uint8_t RESERVED_0[4];
87955   } DESC[1024];
87956 } SSARC_HP_Type;
87957 
87958 /* ----------------------------------------------------------------------------
87959    -- SSARC_HP Register Masks
87960    ---------------------------------------------------------------------------- */
87961 
87962 /*!
87963  * @addtogroup SSARC_HP_Register_Masks SSARC_HP Register Masks
87964  * @{
87965  */
87966 
87967 /*! @name SRAM0 - Description Address Register */
87968 /*! @{ */
87969 
87970 #define SSARC_HP_SRAM0_ADDR_MASK                 (0xFFFFFFFFU)
87971 #define SSARC_HP_SRAM0_ADDR_SHIFT                (0U)
87972 /*! ADDR - Address field */
87973 #define SSARC_HP_SRAM0_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM0_ADDR_SHIFT)) & SSARC_HP_SRAM0_ADDR_MASK)
87974 /*! @} */
87975 
87976 /* The count of SSARC_HP_SRAM0 */
87977 #define SSARC_HP_SRAM0_COUNT                     (1024U)
87978 
87979 /*! @name SRAM1 - Description Data Register */
87980 /*! @{ */
87981 
87982 #define SSARC_HP_SRAM1_DATA_MASK                 (0xFFFFFFFFU)
87983 #define SSARC_HP_SRAM1_DATA_SHIFT                (0U)
87984 /*! DATA - Data field */
87985 #define SSARC_HP_SRAM1_DATA(x)                   (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM1_DATA_SHIFT)) & SSARC_HP_SRAM1_DATA_MASK)
87986 /*! @} */
87987 
87988 /* The count of SSARC_HP_SRAM1 */
87989 #define SSARC_HP_SRAM1_COUNT                     (1024U)
87990 
87991 /*! @name SRAM2 - Description Control Register */
87992 /*! @{ */
87993 
87994 #define SSARC_HP_SRAM2_TYPE_MASK                 (0x7U)
87995 #define SSARC_HP_SRAM2_TYPE_SHIFT                (0U)
87996 /*! TYPE - Type field
87997  *  0b000..SR
87998  *  0b001..WO
87999  *  0b010..RMW_OR
88000  *  0b011..RMW_AND
88001  *  0b100..DELAY
88002  *  0b101..POLLING_0
88003  *  0b110..POLLING_1
88004  *  0b111..Reserved
88005  */
88006 #define SSARC_HP_SRAM2_TYPE(x)                   (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_TYPE_SHIFT)) & SSARC_HP_SRAM2_TYPE_MASK)
88007 
88008 #define SSARC_HP_SRAM2_SV_EN_MASK                (0x10U)
88009 #define SSARC_HP_SRAM2_SV_EN_SHIFT               (4U)
88010 /*! SV_EN - Save Enable
88011  *  0b0..Do not use this descriptor in the save operation
88012  *  0b1..Use this descriptor in the save operation
88013  */
88014 #define SSARC_HP_SRAM2_SV_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_SV_EN_SHIFT)) & SSARC_HP_SRAM2_SV_EN_MASK)
88015 
88016 #define SSARC_HP_SRAM2_RT_EN_MASK                (0x20U)
88017 #define SSARC_HP_SRAM2_RT_EN_SHIFT               (5U)
88018 /*! RT_EN - Restore Enable
88019  *  0b0..Do not use this descriptor for the restore operation
88020  *  0b1..Use this descriptor for the restore operation
88021  */
88022 #define SSARC_HP_SRAM2_RT_EN(x)                  (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_RT_EN_SHIFT)) & SSARC_HP_SRAM2_RT_EN_MASK)
88023 
88024 #define SSARC_HP_SRAM2_SIZE_MASK                 (0xC0U)
88025 #define SSARC_HP_SRAM2_SIZE_SHIFT                (6U)
88026 /*! SIZE - Size field
88027  *  0b00..8-bit
88028  *  0b01..16-bit
88029  *  0b10..32-bit
88030  *  0b11..Reserved
88031  */
88032 #define SSARC_HP_SRAM2_SIZE(x)                   (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_SIZE_SHIFT)) & SSARC_HP_SRAM2_SIZE_MASK)
88033 /*! @} */
88034 
88035 /* The count of SSARC_HP_SRAM2 */
88036 #define SSARC_HP_SRAM2_COUNT                     (1024U)
88037 
88038 
88039 /*!
88040  * @}
88041  */ /* end of group SSARC_HP_Register_Masks */
88042 
88043 
88044 /* SSARC_HP - Peripheral instance base addresses */
88045 /** Peripheral SSARC_HP base address */
88046 #define SSARC_HP_BASE                            (0x40CB4000u)
88047 /** Peripheral SSARC_HP base pointer */
88048 #define SSARC_HP                                 ((SSARC_HP_Type *)SSARC_HP_BASE)
88049 /** Array initializer of SSARC_HP peripheral base addresses */
88050 #define SSARC_HP_BASE_ADDRS                      { SSARC_HP_BASE }
88051 /** Array initializer of SSARC_HP peripheral base pointers */
88052 #define SSARC_HP_BASE_PTRS                       { SSARC_HP }
88053 
88054 /*!
88055  * @}
88056  */ /* end of group SSARC_HP_Peripheral_Access_Layer */
88057 
88058 
88059 /* ----------------------------------------------------------------------------
88060    -- SSARC_LP Peripheral Access Layer
88061    ---------------------------------------------------------------------------- */
88062 
88063 /*!
88064  * @addtogroup SSARC_LP_Peripheral_Access_Layer SSARC_LP Peripheral Access Layer
88065  * @{
88066  */
88067 
88068 /** SSARC_LP - Register Layout Typedef */
88069 typedef struct {
88070   struct {                                         /* offset: 0x0, array step: 0x20 */
88071     __IO uint32_t DESC_CTRL0;                        /**< Descriptor Control0 0 Register..Descriptor Control0 15 Register, array offset: 0x0, array step: 0x20 */
88072     __IO uint32_t DESC_CTRL1;                        /**< Descriptor Control1 0 Register..Descriptor Control1 15 Register, array offset: 0x4, array step: 0x20 */
88073     __IO uint32_t DESC_ADDR_UP;                      /**< Descriptor Address Up 0 Register..Descriptor Address Up 15 Register, array offset: 0x8, array step: 0x20 */
88074     __IO uint32_t DESC_ADDR_DOWN;                    /**< Descriptor Address Down 0 Register..Descriptor Address Down 15 Register, array offset: 0xC, array step: 0x20 */
88075          uint8_t RESERVED_0[16];
88076   } GROUPS[16];
88077   __IO uint32_t CTRL;                              /**< Control Register, offset: 0x200 */
88078   __IO uint32_t INT_STATUS;                        /**< Interrupt Status Register, offset: 0x204 */
88079        uint8_t RESERVED_0[4];
88080   __IO uint32_t HP_TIMEOUT;                        /**< HP Timeout Register, offset: 0x20C */
88081        uint8_t RESERVED_1[12];
88082   __I  uint32_t HW_GROUP_PENDING;                  /**< Hardware Request Pending Register, offset: 0x21C */
88083   __I  uint32_t SW_GROUP_PENDING;                  /**< Software Request Pending Register, offset: 0x220 */
88084 } SSARC_LP_Type;
88085 
88086 /* ----------------------------------------------------------------------------
88087    -- SSARC_LP Register Masks
88088    ---------------------------------------------------------------------------- */
88089 
88090 /*!
88091  * @addtogroup SSARC_LP_Register_Masks SSARC_LP Register Masks
88092  * @{
88093  */
88094 
88095 /*! @name DESC_CTRL0 - Descriptor Control0 0 Register..Descriptor Control0 15 Register */
88096 /*! @{ */
88097 
88098 #define SSARC_LP_DESC_CTRL0_START_MASK           (0x3FFU)
88099 #define SSARC_LP_DESC_CTRL0_START_SHIFT          (0U)
88100 /*! START - Start index */
88101 #define SSARC_LP_DESC_CTRL0_START(x)             (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_START_SHIFT)) & SSARC_LP_DESC_CTRL0_START_MASK)
88102 
88103 #define SSARC_LP_DESC_CTRL0_END_MASK             (0xFFC00U)
88104 #define SSARC_LP_DESC_CTRL0_END_SHIFT            (10U)
88105 /*! END - End index */
88106 #define SSARC_LP_DESC_CTRL0_END(x)               (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_END_SHIFT)) & SSARC_LP_DESC_CTRL0_END_MASK)
88107 
88108 #define SSARC_LP_DESC_CTRL0_SV_ORDER_MASK        (0x100000U)
88109 #define SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT       (20U)
88110 /*! SV_ORDER - Save Order
88111  *  0b0..Descriptors within the group are processed from start to end
88112  *  0b1..Descriptors within the group are processed from end to start
88113  */
88114 #define SSARC_LP_DESC_CTRL0_SV_ORDER(x)          (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_SV_ORDER_MASK)
88115 
88116 #define SSARC_LP_DESC_CTRL0_RT_ORDER_MASK        (0x200000U)
88117 #define SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT       (21U)
88118 /*! RT_ORDER - Restore order
88119  *  0b0..Descriptors within the group are processed from start to end
88120  *  0b1..Descriptors within the group are processed from end to start
88121  */
88122 #define SSARC_LP_DESC_CTRL0_RT_ORDER(x)          (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_RT_ORDER_MASK)
88123 /*! @} */
88124 
88125 /* The count of SSARC_LP_DESC_CTRL0 */
88126 #define SSARC_LP_DESC_CTRL0_COUNT                (16U)
88127 
88128 /*! @name DESC_CTRL1 - Descriptor Control1 0 Register..Descriptor Control1 15 Register */
88129 /*! @{ */
88130 
88131 #define SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK      (0x1U)
88132 #define SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT     (0U)
88133 /*! SW_TRIG_SV - Software trigger save
88134  *  0b1..Request a software save operation/software restore operation in progress
88135  *  0b0..No software save request/software restore request complete
88136  */
88137 #define SSARC_LP_DESC_CTRL1_SW_TRIG_SV(x)        (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK)
88138 
88139 #define SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK      (0x2U)
88140 #define SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT     (1U)
88141 /*! SW_TRIG_RT - Software trigger restore
88142  *  0b1..Request a software restore operation/software restore operation in progress
88143  *  0b0..No software restore request/software restore request complete
88144  */
88145 #define SSARC_LP_DESC_CTRL1_SW_TRIG_RT(x)        (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK)
88146 
88147 #define SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK    (0x70U)
88148 #define SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT   (4U)
88149 /*! POWER_DOMAIN
88150  *  0b000..PGMC_BPC0
88151  *  0b001..PGMC_BPC1
88152  *  0b010..PGMC_BPC2
88153  *  0b011..PGMC_BPC3
88154  *  0b100..PGMC_BPC4
88155  *  0b101..PGMC_BPC5
88156  *  0b110..PGMC_BPC6
88157  *  0b111..PGMC_BPC7
88158  */
88159 #define SSARC_LP_DESC_CTRL1_POWER_DOMAIN(x)      (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT)) & SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK)
88160 
88161 #define SSARC_LP_DESC_CTRL1_GP_EN_MASK           (0x80U)
88162 #define SSARC_LP_DESC_CTRL1_GP_EN_SHIFT          (7U)
88163 /*! GP_EN - Group Enable
88164  *  0b0..Group disabled
88165  *  0b1..Group enabled
88166  */
88167 #define SSARC_LP_DESC_CTRL1_GP_EN(x)             (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_GP_EN_SHIFT)) & SSARC_LP_DESC_CTRL1_GP_EN_MASK)
88168 
88169 #define SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK     (0xF00U)
88170 #define SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT    (8U)
88171 /*! SV_PRIORITY - Save Priority */
88172 #define SSARC_LP_DESC_CTRL1_SV_PRIORITY(x)       (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK)
88173 
88174 #define SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK     (0xF000U)
88175 #define SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT    (12U)
88176 /*! RT_PRIORITY - Restore Priority */
88177 #define SSARC_LP_DESC_CTRL1_RT_PRIORITY(x)       (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK)
88178 
88179 #define SSARC_LP_DESC_CTRL1_CPUD_MASK            (0x30000U)
88180 #define SSARC_LP_DESC_CTRL1_CPUD_SHIFT           (16U)
88181 /*! CPUD - CPU Domain */
88182 #define SSARC_LP_DESC_CTRL1_CPUD(x)              (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_CPUD_SHIFT)) & SSARC_LP_DESC_CTRL1_CPUD_MASK)
88183 
88184 #define SSARC_LP_DESC_CTRL1_RL_MASK              (0x40000U)
88185 #define SSARC_LP_DESC_CTRL1_RL_SHIFT             (18U)
88186 /*! RL - Read Lock
88187  *  0b1..Group is locked (read access not allowed)
88188  *  0b0..Group is unlocked (read access allowed)
88189  */
88190 #define SSARC_LP_DESC_CTRL1_RL(x)                (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RL_SHIFT)) & SSARC_LP_DESC_CTRL1_RL_MASK)
88191 
88192 #define SSARC_LP_DESC_CTRL1_WL_MASK              (0x80000U)
88193 #define SSARC_LP_DESC_CTRL1_WL_SHIFT             (19U)
88194 /*! WL - Write Lock
88195  *  0b1..Group is locked (write access not allowed)
88196  *  0b0..Group is unlocked (write access allowed)
88197  */
88198 #define SSARC_LP_DESC_CTRL1_WL(x)                (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_WL_SHIFT)) & SSARC_LP_DESC_CTRL1_WL_MASK)
88199 
88200 #define SSARC_LP_DESC_CTRL1_DL_MASK              (0x100000U)
88201 #define SSARC_LP_DESC_CTRL1_DL_SHIFT             (20U)
88202 /*! DL - Domain lock
88203  *  0b1..Lock
88204  *  0b0..Unlock
88205  */
88206 #define SSARC_LP_DESC_CTRL1_DL(x)                (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_DL_SHIFT)) & SSARC_LP_DESC_CTRL1_DL_MASK)
88207 /*! @} */
88208 
88209 /* The count of SSARC_LP_DESC_CTRL1 */
88210 #define SSARC_LP_DESC_CTRL1_COUNT                (16U)
88211 
88212 /*! @name DESC_ADDR_UP - Descriptor Address Up 0 Register..Descriptor Address Up 15 Register */
88213 /*! @{ */
88214 
88215 #define SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK       (0xFFFFFFFFU)
88216 #define SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT      (0U)
88217 /*! ADDR_UP - Address field (High) */
88218 #define SSARC_LP_DESC_ADDR_UP_ADDR_UP(x)         (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT)) & SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK)
88219 /*! @} */
88220 
88221 /* The count of SSARC_LP_DESC_ADDR_UP */
88222 #define SSARC_LP_DESC_ADDR_UP_COUNT              (16U)
88223 
88224 /*! @name DESC_ADDR_DOWN - Descriptor Address Down 0 Register..Descriptor Address Down 15 Register */
88225 /*! @{ */
88226 
88227 #define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK   (0xFFFFFFFFU)
88228 #define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT  (0U)
88229 /*! ADDR_DOWN - Address field (Low) */
88230 #define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN(x)     (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT)) & SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK)
88231 /*! @} */
88232 
88233 /* The count of SSARC_LP_DESC_ADDR_DOWN */
88234 #define SSARC_LP_DESC_ADDR_DOWN_COUNT            (16U)
88235 
88236 /*! @name CTRL - Control Register */
88237 /*! @{ */
88238 
88239 #define SSARC_LP_CTRL_DIS_HW_REQ_MASK            (0x8000000U)
88240 #define SSARC_LP_CTRL_DIS_HW_REQ_SHIFT           (27U)
88241 /*! DIS_HW_REQ - Save/Restore request disable
88242  *  0b0..PGMC save/restore requests enabled
88243  *  0b1..PGMC save/restore requests disabled
88244  */
88245 #define SSARC_LP_CTRL_DIS_HW_REQ(x)              (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_DIS_HW_REQ_SHIFT)) & SSARC_LP_CTRL_DIS_HW_REQ_MASK)
88246 
88247 #define SSARC_LP_CTRL_SW_RESET_MASK              (0x80000000U)
88248 #define SSARC_LP_CTRL_SW_RESET_SHIFT             (31U)
88249 /*! SW_RESET - Software reset */
88250 #define SSARC_LP_CTRL_SW_RESET(x)                (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_SW_RESET_SHIFT)) & SSARC_LP_CTRL_SW_RESET_MASK)
88251 /*! @} */
88252 
88253 /*! @name INT_STATUS - Interrupt Status Register */
88254 /*! @{ */
88255 
88256 #define SSARC_LP_INT_STATUS_ERR_INDEX_MASK       (0x3FFU)
88257 #define SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT      (0U)
88258 /*! ERR_INDEX - Error Index */
88259 #define SSARC_LP_INT_STATUS_ERR_INDEX(x)         (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT)) & SSARC_LP_INT_STATUS_ERR_INDEX_MASK)
88260 
88261 #define SSARC_LP_INT_STATUS_AHB_RESP_MASK        (0xC00U)
88262 #define SSARC_LP_INT_STATUS_AHB_RESP_SHIFT       (10U)
88263 /*! AHB_RESP - AHB Bus response field */
88264 #define SSARC_LP_INT_STATUS_AHB_RESP(x)          (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_RESP_SHIFT)) & SSARC_LP_INT_STATUS_AHB_RESP_MASK)
88265 
88266 #define SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK  (0x8000000U)
88267 #define SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT (27U)
88268 /*! GROUP_CONFLICT - Group Conflict field
88269  *  0b1..A group conflict error has occurred
88270  *  0b0..No group conflict error
88271  */
88272 #define SSARC_LP_INT_STATUS_GROUP_CONFLICT(x)    (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT)) & SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK)
88273 
88274 #define SSARC_LP_INT_STATUS_TIMEOUT_MASK         (0x10000000U)
88275 #define SSARC_LP_INT_STATUS_TIMEOUT_SHIFT        (28U)
88276 /*! TIMEOUT - Timeout field
88277  *  0b1..A timeout event has occurred
88278  *  0b0..No timeout event
88279  */
88280 #define SSARC_LP_INT_STATUS_TIMEOUT(x)           (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_TIMEOUT_SHIFT)) & SSARC_LP_INT_STATUS_TIMEOUT_MASK)
88281 
88282 #define SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK     (0x20000000U)
88283 #define SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT    (29U)
88284 /*! SW_REQ_DONE - Software Request Done
88285  *  0b1..Atleast one software triggered has been complete
88286  *  0b0..No software triggered requests or software triggered request still in progress
88287  */
88288 #define SSARC_LP_INT_STATUS_SW_REQ_DONE(x)       (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT)) & SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK)
88289 
88290 #define SSARC_LP_INT_STATUS_AHB_ERR_MASK         (0x40000000U)
88291 #define SSARC_LP_INT_STATUS_AHB_ERR_SHIFT        (30U)
88292 /*! AHB_ERR - AHB Error field
88293  *  0b1..An AHB error has occurred
88294  *  0b0..No AHB error
88295  */
88296 #define SSARC_LP_INT_STATUS_AHB_ERR(x)           (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_ERR_SHIFT)) & SSARC_LP_INT_STATUS_AHB_ERR_MASK)
88297 
88298 #define SSARC_LP_INT_STATUS_ADDR_ERR_MASK        (0x80000000U)
88299 #define SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT       (31U)
88300 /*! ADDR_ERR - Address Error field
88301  *  0b1..An address error has occurred
88302  *  0b0..No address error
88303  */
88304 #define SSARC_LP_INT_STATUS_ADDR_ERR(x)          (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT)) & SSARC_LP_INT_STATUS_ADDR_ERR_MASK)
88305 /*! @} */
88306 
88307 /*! @name HP_TIMEOUT - HP Timeout Register */
88308 /*! @{ */
88309 
88310 #define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK   (0xFFFFFFFFU)
88311 #define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT  (0U)
88312 /*! TIMEOUT_VALUE - Time out value */
88313 #define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE(x)     (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT)) & SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK)
88314 /*! @} */
88315 
88316 /*! @name HW_GROUP_PENDING - Hardware Request Pending Register */
88317 /*! @{ */
88318 
88319 #define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK (0xFFFFU)
88320 #define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT (0U)
88321 /*! HW_SAVE_PENDING - This field indicates which groups are pending for save from hardware request */
88322 #define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK)
88323 
88324 #define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK (0xFFFF0000U)
88325 #define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT (16U)
88326 /*! HW_RESTORE_PENDING - This field indicates which groups are pending for restore from hardware request */
88327 #define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK)
88328 /*! @} */
88329 
88330 /*! @name SW_GROUP_PENDING - Software Request Pending Register */
88331 /*! @{ */
88332 
88333 #define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK (0xFFFFU)
88334 #define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT (0U)
88335 /*! SW_SAVE_PENDING - This field indicates which groups are pending for save from software request */
88336 #define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK)
88337 
88338 #define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK (0xFFFF0000U)
88339 #define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT (16U)
88340 /*! SW_RESTORE_PENDING - This field indicates which groups are pending for restore from software request */
88341 #define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK)
88342 /*! @} */
88343 
88344 
88345 /*!
88346  * @}
88347  */ /* end of group SSARC_LP_Register_Masks */
88348 
88349 
88350 /* SSARC_LP - Peripheral instance base addresses */
88351 /** Peripheral SSARC_LP base address */
88352 #define SSARC_LP_BASE                            (0x40CB8000u)
88353 /** Peripheral SSARC_LP base pointer */
88354 #define SSARC_LP                                 ((SSARC_LP_Type *)SSARC_LP_BASE)
88355 /** Array initializer of SSARC_LP peripheral base addresses */
88356 #define SSARC_LP_BASE_ADDRS                      { SSARC_LP_BASE }
88357 /** Array initializer of SSARC_LP peripheral base pointers */
88358 #define SSARC_LP_BASE_PTRS                       { SSARC_LP }
88359 
88360 /*!
88361  * @}
88362  */ /* end of group SSARC_LP_Peripheral_Access_Layer */
88363 
88364 
88365 /* ----------------------------------------------------------------------------
88366    -- TMPSNS Peripheral Access Layer
88367    ---------------------------------------------------------------------------- */
88368 
88369 /*!
88370  * @addtogroup TMPSNS_Peripheral_Access_Layer TMPSNS Peripheral Access Layer
88371  * @{
88372  */
88373 
88374 /** TMPSNS - Register Layout Typedef */
88375 typedef struct {
88376   __IO uint32_t CTRL0;                             /**< Temperature Sensor Control Register 0, offset: 0x0 */
88377   __IO uint32_t CTRL0_SET;                         /**< Temperature Sensor Control Register 0, offset: 0x4 */
88378   __IO uint32_t CTRL0_CLR;                         /**< Temperature Sensor Control Register 0, offset: 0x8 */
88379   __IO uint32_t CTRL0_TOG;                         /**< Temperature Sensor Control Register 0, offset: 0xC */
88380   __IO uint32_t CTRL1;                             /**< Temperature Sensor Control Register 1, offset: 0x10 */
88381   __IO uint32_t CTRL1_SET;                         /**< Temperature Sensor Control Register 1, offset: 0x14 */
88382   __IO uint32_t CTRL1_CLR;                         /**< Temperature Sensor Control Register 1, offset: 0x18 */
88383   __IO uint32_t CTRL1_TOG;                         /**< Temperature Sensor Control Register 1, offset: 0x1C */
88384   __IO uint32_t RANGE0;                            /**< Temperature Sensor Range Register 0, offset: 0x20 */
88385   __IO uint32_t RANGE0_SET;                        /**< Temperature Sensor Range Register 0, offset: 0x24 */
88386   __IO uint32_t RANGE0_CLR;                        /**< Temperature Sensor Range Register 0, offset: 0x28 */
88387   __IO uint32_t RANGE0_TOG;                        /**< Temperature Sensor Range Register 0, offset: 0x2C */
88388   __IO uint32_t RANGE1;                            /**< Temperature Sensor Range Register 1, offset: 0x30 */
88389   __IO uint32_t RANGE1_SET;                        /**< Temperature Sensor Range Register 1, offset: 0x34 */
88390   __IO uint32_t RANGE1_CLR;                        /**< Temperature Sensor Range Register 1, offset: 0x38 */
88391   __IO uint32_t RANGE1_TOG;                        /**< Temperature Sensor Range Register 1, offset: 0x3C */
88392        uint8_t RESERVED_0[16];
88393   __IO uint32_t STATUS0;                           /**< Temperature Sensor Status Register 0, offset: 0x50 */
88394 } TMPSNS_Type;
88395 
88396 /* ----------------------------------------------------------------------------
88397    -- TMPSNS Register Masks
88398    ---------------------------------------------------------------------------- */
88399 
88400 /*!
88401  * @addtogroup TMPSNS_Register_Masks TMPSNS Register Masks
88402  * @{
88403  */
88404 
88405 /*! @name CTRL0 - Temperature Sensor Control Register 0 */
88406 /*! @{ */
88407 
88408 #define TMPSNS_CTRL0_SLOPE_CAL_MASK              (0x3FU)
88409 #define TMPSNS_CTRL0_SLOPE_CAL_SHIFT             (0U)
88410 /*! SLOPE_CAL - Ramp slope calibration control */
88411 #define TMPSNS_CTRL0_SLOPE_CAL(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SLOPE_CAL_MASK)
88412 
88413 #define TMPSNS_CTRL0_V_SEL_MASK                  (0x300U)
88414 #define TMPSNS_CTRL0_V_SEL_SHIFT                 (8U)
88415 /*! V_SEL - Voltage Select
88416  *  0b00..Normal temperature measuring mode
88417  *  0b01-0b10..Reserved
88418  */
88419 #define TMPSNS_CTRL0_V_SEL(x)                    (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_V_SEL_SHIFT)) & TMPSNS_CTRL0_V_SEL_MASK)
88420 
88421 #define TMPSNS_CTRL0_IBIAS_TRIM_MASK             (0xF000U)
88422 #define TMPSNS_CTRL0_IBIAS_TRIM_SHIFT            (12U)
88423 /*! IBIAS_TRIM - Current bias trim value */
88424 #define TMPSNS_CTRL0_IBIAS_TRIM(x)               (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_IBIAS_TRIM_MASK)
88425 /*! @} */
88426 
88427 /*! @name CTRL0_SET - Temperature Sensor Control Register 0 */
88428 /*! @{ */
88429 
88430 #define TMPSNS_CTRL0_SET_SLOPE_CAL_MASK          (0x3FU)
88431 #define TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT         (0U)
88432 /*! SLOPE_CAL - Ramp slope calibration control */
88433 #define TMPSNS_CTRL0_SET_SLOPE_CAL(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SET_SLOPE_CAL_MASK)
88434 
88435 #define TMPSNS_CTRL0_SET_V_SEL_MASK              (0x300U)
88436 #define TMPSNS_CTRL0_SET_V_SEL_SHIFT             (8U)
88437 /*! V_SEL - Voltage Select */
88438 #define TMPSNS_CTRL0_SET_V_SEL(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_V_SEL_SHIFT)) & TMPSNS_CTRL0_SET_V_SEL_MASK)
88439 
88440 #define TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK         (0xF000U)
88441 #define TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT        (12U)
88442 /*! IBIAS_TRIM - Current bias trim value */
88443 #define TMPSNS_CTRL0_SET_IBIAS_TRIM(x)           (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK)
88444 /*! @} */
88445 
88446 /*! @name CTRL0_CLR - Temperature Sensor Control Register 0 */
88447 /*! @{ */
88448 
88449 #define TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK          (0x3FU)
88450 #define TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT         (0U)
88451 /*! SLOPE_CAL - Ramp slope calibration control */
88452 #define TMPSNS_CTRL0_CLR_SLOPE_CAL(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK)
88453 
88454 #define TMPSNS_CTRL0_CLR_V_SEL_MASK              (0x300U)
88455 #define TMPSNS_CTRL0_CLR_V_SEL_SHIFT             (8U)
88456 /*! V_SEL - Voltage Select */
88457 #define TMPSNS_CTRL0_CLR_V_SEL(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_V_SEL_SHIFT)) & TMPSNS_CTRL0_CLR_V_SEL_MASK)
88458 
88459 #define TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK         (0xF000U)
88460 #define TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT        (12U)
88461 /*! IBIAS_TRIM - Current bias trim value */
88462 #define TMPSNS_CTRL0_CLR_IBIAS_TRIM(x)           (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK)
88463 /*! @} */
88464 
88465 /*! @name CTRL0_TOG - Temperature Sensor Control Register 0 */
88466 /*! @{ */
88467 
88468 #define TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK          (0x3FU)
88469 #define TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT         (0U)
88470 /*! SLOPE_CAL - Ramp slope calibration control */
88471 #define TMPSNS_CTRL0_TOG_SLOPE_CAL(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK)
88472 
88473 #define TMPSNS_CTRL0_TOG_V_SEL_MASK              (0x300U)
88474 #define TMPSNS_CTRL0_TOG_V_SEL_SHIFT             (8U)
88475 /*! V_SEL - Voltage Select */
88476 #define TMPSNS_CTRL0_TOG_V_SEL(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_V_SEL_SHIFT)) & TMPSNS_CTRL0_TOG_V_SEL_MASK)
88477 
88478 #define TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK         (0xF000U)
88479 #define TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT        (12U)
88480 /*! IBIAS_TRIM - Current bias trim value */
88481 #define TMPSNS_CTRL0_TOG_IBIAS_TRIM(x)           (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK)
88482 /*! @} */
88483 
88484 /*! @name CTRL1 - Temperature Sensor Control Register 1 */
88485 /*! @{ */
88486 
88487 #define TMPSNS_CTRL1_FREQ_MASK                   (0xFFFFU)
88488 #define TMPSNS_CTRL1_FREQ_SHIFT                  (0U)
88489 /*! FREQ - Temperature Measurement Frequency
88490  *  0b0000000000000000..Single Reading Mode. New reading available every time CTRL1[START] bit is set to 1 from 0.
88491  *  0b0000000000000001-0b1111111111111111..Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete.
88492  */
88493 #define TMPSNS_CTRL1_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FREQ_SHIFT)) & TMPSNS_CTRL1_FREQ_MASK)
88494 
88495 #define TMPSNS_CTRL1_FINISH_IE_MASK              (0x10000U)
88496 #define TMPSNS_CTRL1_FINISH_IE_SHIFT             (16U)
88497 /*! FINISH_IE - Measurement finished interrupt enable
88498  *  0b0..Interrupt is disabled
88499  *  0b1..Interrupt is enabled
88500  */
88501 #define TMPSNS_CTRL1_FINISH_IE(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_FINISH_IE_MASK)
88502 
88503 #define TMPSNS_CTRL1_LOW_TEMP_IE_MASK            (0x20000U)
88504 #define TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT           (17U)
88505 /*! LOW_TEMP_IE - Low temperature interrupt enable
88506  *  0b0..Interrupt is disabled
88507  *  0b1..Interrupt is enabled
88508  */
88509 #define TMPSNS_CTRL1_LOW_TEMP_IE(x)              (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_LOW_TEMP_IE_MASK)
88510 
88511 #define TMPSNS_CTRL1_HIGH_TEMP_IE_MASK           (0x40000U)
88512 #define TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT          (18U)
88513 /*! HIGH_TEMP_IE - High temperature interrupt enable
88514  *  0b0..Interrupt is disabled
88515  *  0b1..Interrupt is enabled
88516  */
88517 #define TMPSNS_CTRL1_HIGH_TEMP_IE(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_HIGH_TEMP_IE_MASK)
88518 
88519 #define TMPSNS_CTRL1_PANIC_TEMP_IE_MASK          (0x80000U)
88520 #define TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT         (19U)
88521 /*! PANIC_TEMP_IE - Panic temperature interrupt enable
88522  *  0b0..Interrupt is disabled
88523  *  0b1..Interrupt is enabled
88524  */
88525 #define TMPSNS_CTRL1_PANIC_TEMP_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_PANIC_TEMP_IE_MASK)
88526 
88527 #define TMPSNS_CTRL1_START_MASK                  (0x400000U)
88528 #define TMPSNS_CTRL1_START_SHIFT                 (22U)
88529 /*! START - Start Temperature Measurement
88530  *  0b0..No new temperature reading taken
88531  *  0b1..Initiate a new temperature reading
88532  */
88533 #define TMPSNS_CTRL1_START(x)                    (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_START_SHIFT)) & TMPSNS_CTRL1_START_MASK)
88534 
88535 #define TMPSNS_CTRL1_PWD_MASK                    (0x800000U)
88536 #define TMPSNS_CTRL1_PWD_SHIFT                   (23U)
88537 /*! PWD - Temperature Sensor Power Down
88538  *  0b0..Sensor is active
88539  *  0b1..Sensor is powered down
88540  */
88541 #define TMPSNS_CTRL1_PWD(x)                      (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_SHIFT)) & TMPSNS_CTRL1_PWD_MASK)
88542 
88543 #define TMPSNS_CTRL1_RFU_MASK                    (0x7F000000U)
88544 #define TMPSNS_CTRL1_RFU_SHIFT                   (24U)
88545 /*! RFU - Read/Writeable field. Reserved for future use */
88546 #define TMPSNS_CTRL1_RFU(x)                      (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_RFU_SHIFT)) & TMPSNS_CTRL1_RFU_MASK)
88547 
88548 #define TMPSNS_CTRL1_PWD_FULL_MASK               (0x80000000U)
88549 #define TMPSNS_CTRL1_PWD_FULL_SHIFT              (31U)
88550 /*! PWD_FULL - Temperature Sensor Full Power Down
88551  *  0b0..Sensor is active
88552  *  0b1..Sensor is powered down
88553  */
88554 #define TMPSNS_CTRL1_PWD_FULL(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_PWD_FULL_MASK)
88555 /*! @} */
88556 
88557 /*! @name CTRL1_SET - Temperature Sensor Control Register 1 */
88558 /*! @{ */
88559 
88560 #define TMPSNS_CTRL1_SET_FREQ_MASK               (0xFFFFU)
88561 #define TMPSNS_CTRL1_SET_FREQ_SHIFT              (0U)
88562 /*! FREQ - Temperature Measurement Frequency */
88563 #define TMPSNS_CTRL1_SET_FREQ(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FREQ_SHIFT)) & TMPSNS_CTRL1_SET_FREQ_MASK)
88564 
88565 #define TMPSNS_CTRL1_SET_FINISH_IE_MASK          (0x10000U)
88566 #define TMPSNS_CTRL1_SET_FINISH_IE_SHIFT         (16U)
88567 /*! FINISH_IE - Measurement finished interrupt enable */
88568 #define TMPSNS_CTRL1_SET_FINISH_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_SET_FINISH_IE_MASK)
88569 
88570 #define TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK        (0x20000U)
88571 #define TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT       (17U)
88572 /*! LOW_TEMP_IE - Low temperature interrupt enable */
88573 #define TMPSNS_CTRL1_SET_LOW_TEMP_IE(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK)
88574 
88575 #define TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK       (0x40000U)
88576 #define TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT      (18U)
88577 /*! HIGH_TEMP_IE - High temperature interrupt enable */
88578 #define TMPSNS_CTRL1_SET_HIGH_TEMP_IE(x)         (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK)
88579 
88580 #define TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK      (0x80000U)
88581 #define TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT     (19U)
88582 /*! PANIC_TEMP_IE - Panic temperature interrupt enable */
88583 #define TMPSNS_CTRL1_SET_PANIC_TEMP_IE(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK)
88584 
88585 #define TMPSNS_CTRL1_SET_START_MASK              (0x400000U)
88586 #define TMPSNS_CTRL1_SET_START_SHIFT             (22U)
88587 /*! START - Start Temperature Measurement */
88588 #define TMPSNS_CTRL1_SET_START(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_START_SHIFT)) & TMPSNS_CTRL1_SET_START_MASK)
88589 
88590 #define TMPSNS_CTRL1_SET_PWD_MASK                (0x800000U)
88591 #define TMPSNS_CTRL1_SET_PWD_SHIFT               (23U)
88592 /*! PWD - Temperature Sensor Power Down */
88593 #define TMPSNS_CTRL1_SET_PWD(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_SHIFT)) & TMPSNS_CTRL1_SET_PWD_MASK)
88594 
88595 #define TMPSNS_CTRL1_SET_RFU_MASK                (0x7F000000U)
88596 #define TMPSNS_CTRL1_SET_RFU_SHIFT               (24U)
88597 /*! RFU - Read/Writeable field. Reserved for future use */
88598 #define TMPSNS_CTRL1_SET_RFU(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_RFU_SHIFT)) & TMPSNS_CTRL1_SET_RFU_MASK)
88599 
88600 #define TMPSNS_CTRL1_SET_PWD_FULL_MASK           (0x80000000U)
88601 #define TMPSNS_CTRL1_SET_PWD_FULL_SHIFT          (31U)
88602 /*! PWD_FULL - Temperature Sensor Full Power Down */
88603 #define TMPSNS_CTRL1_SET_PWD_FULL(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_SET_PWD_FULL_MASK)
88604 /*! @} */
88605 
88606 /*! @name CTRL1_CLR - Temperature Sensor Control Register 1 */
88607 /*! @{ */
88608 
88609 #define TMPSNS_CTRL1_CLR_FREQ_MASK               (0xFFFFU)
88610 #define TMPSNS_CTRL1_CLR_FREQ_SHIFT              (0U)
88611 /*! FREQ - Temperature Measurement Frequency */
88612 #define TMPSNS_CTRL1_CLR_FREQ(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FREQ_SHIFT)) & TMPSNS_CTRL1_CLR_FREQ_MASK)
88613 
88614 #define TMPSNS_CTRL1_CLR_FINISH_IE_MASK          (0x10000U)
88615 #define TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT         (16U)
88616 /*! FINISH_IE - Measurement finished interrupt enable */
88617 #define TMPSNS_CTRL1_CLR_FINISH_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_CLR_FINISH_IE_MASK)
88618 
88619 #define TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK        (0x20000U)
88620 #define TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT       (17U)
88621 /*! LOW_TEMP_IE - Low temperature interrupt enable */
88622 #define TMPSNS_CTRL1_CLR_LOW_TEMP_IE(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK)
88623 
88624 #define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK       (0x40000U)
88625 #define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT      (18U)
88626 /*! HIGH_TEMP_IE - High temperature interrupt enable */
88627 #define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE(x)         (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK)
88628 
88629 #define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK      (0x80000U)
88630 #define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT     (19U)
88631 /*! PANIC_TEMP_IE - Panic temperature interrupt enable */
88632 #define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK)
88633 
88634 #define TMPSNS_CTRL1_CLR_START_MASK              (0x400000U)
88635 #define TMPSNS_CTRL1_CLR_START_SHIFT             (22U)
88636 /*! START - Start Temperature Measurement */
88637 #define TMPSNS_CTRL1_CLR_START(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_START_SHIFT)) & TMPSNS_CTRL1_CLR_START_MASK)
88638 
88639 #define TMPSNS_CTRL1_CLR_PWD_MASK                (0x800000U)
88640 #define TMPSNS_CTRL1_CLR_PWD_SHIFT               (23U)
88641 /*! PWD - Temperature Sensor Power Down */
88642 #define TMPSNS_CTRL1_CLR_PWD(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_MASK)
88643 
88644 #define TMPSNS_CTRL1_CLR_RFU_MASK                (0x7F000000U)
88645 #define TMPSNS_CTRL1_CLR_RFU_SHIFT               (24U)
88646 /*! RFU - Read/Writeable field. Reserved for future use */
88647 #define TMPSNS_CTRL1_CLR_RFU(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_RFU_SHIFT)) & TMPSNS_CTRL1_CLR_RFU_MASK)
88648 
88649 #define TMPSNS_CTRL1_CLR_PWD_FULL_MASK           (0x80000000U)
88650 #define TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT          (31U)
88651 /*! PWD_FULL - Temperature Sensor Full Power Down */
88652 #define TMPSNS_CTRL1_CLR_PWD_FULL(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_FULL_MASK)
88653 /*! @} */
88654 
88655 /*! @name CTRL1_TOG - Temperature Sensor Control Register 1 */
88656 /*! @{ */
88657 
88658 #define TMPSNS_CTRL1_TOG_FREQ_MASK               (0xFFFFU)
88659 #define TMPSNS_CTRL1_TOG_FREQ_SHIFT              (0U)
88660 /*! FREQ - Temperature Measurement Frequency */
88661 #define TMPSNS_CTRL1_TOG_FREQ(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FREQ_SHIFT)) & TMPSNS_CTRL1_TOG_FREQ_MASK)
88662 
88663 #define TMPSNS_CTRL1_TOG_FINISH_IE_MASK          (0x10000U)
88664 #define TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT         (16U)
88665 /*! FINISH_IE - Measurement finished interrupt enable */
88666 #define TMPSNS_CTRL1_TOG_FINISH_IE(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_TOG_FINISH_IE_MASK)
88667 
88668 #define TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK        (0x20000U)
88669 #define TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT       (17U)
88670 /*! LOW_TEMP_IE - Low temperature interrupt enable */
88671 #define TMPSNS_CTRL1_TOG_LOW_TEMP_IE(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK)
88672 
88673 #define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK       (0x40000U)
88674 #define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT      (18U)
88675 /*! HIGH_TEMP_IE - High temperature interrupt enable */
88676 #define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE(x)         (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK)
88677 
88678 #define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK      (0x80000U)
88679 #define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT     (19U)
88680 /*! PANIC_TEMP_IE - Panic temperature interrupt enable */
88681 #define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK)
88682 
88683 #define TMPSNS_CTRL1_TOG_START_MASK              (0x400000U)
88684 #define TMPSNS_CTRL1_TOG_START_SHIFT             (22U)
88685 /*! START - Start Temperature Measurement */
88686 #define TMPSNS_CTRL1_TOG_START(x)                (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_START_SHIFT)) & TMPSNS_CTRL1_TOG_START_MASK)
88687 
88688 #define TMPSNS_CTRL1_TOG_PWD_MASK                (0x800000U)
88689 #define TMPSNS_CTRL1_TOG_PWD_SHIFT               (23U)
88690 /*! PWD - Temperature Sensor Power Down */
88691 #define TMPSNS_CTRL1_TOG_PWD(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_MASK)
88692 
88693 #define TMPSNS_CTRL1_TOG_RFU_MASK                (0x7F000000U)
88694 #define TMPSNS_CTRL1_TOG_RFU_SHIFT               (24U)
88695 /*! RFU - Read/Writeable field. Reserved for future use */
88696 #define TMPSNS_CTRL1_TOG_RFU(x)                  (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_RFU_SHIFT)) & TMPSNS_CTRL1_TOG_RFU_MASK)
88697 
88698 #define TMPSNS_CTRL1_TOG_PWD_FULL_MASK           (0x80000000U)
88699 #define TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT          (31U)
88700 /*! PWD_FULL - Temperature Sensor Full Power Down */
88701 #define TMPSNS_CTRL1_TOG_PWD_FULL(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_FULL_MASK)
88702 /*! @} */
88703 
88704 /*! @name RANGE0 - Temperature Sensor Range Register 0 */
88705 /*! @{ */
88706 
88707 #define TMPSNS_RANGE0_LOW_TEMP_VAL_MASK          (0xFFFU)
88708 #define TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT         (0U)
88709 /*! LOW_TEMP_VAL - Low temperature threshold value */
88710 #define TMPSNS_RANGE0_LOW_TEMP_VAL(x)            (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_LOW_TEMP_VAL_MASK)
88711 
88712 #define TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK         (0xFFF0000U)
88713 #define TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT        (16U)
88714 /*! HIGH_TEMP_VAL - High temperature threshold value */
88715 #define TMPSNS_RANGE0_HIGH_TEMP_VAL(x)           (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK)
88716 /*! @} */
88717 
88718 /*! @name RANGE0_SET - Temperature Sensor Range Register 0 */
88719 /*! @{ */
88720 
88721 #define TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK      (0xFFFU)
88722 #define TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT     (0U)
88723 /*! LOW_TEMP_VAL - Low temperature threshold value */
88724 #define TMPSNS_RANGE0_SET_LOW_TEMP_VAL(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK)
88725 
88726 #define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK     (0xFFF0000U)
88727 #define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT    (16U)
88728 /*! HIGH_TEMP_VAL - High temperature threshold value */
88729 #define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL(x)       (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK)
88730 /*! @} */
88731 
88732 /*! @name RANGE0_CLR - Temperature Sensor Range Register 0 */
88733 /*! @{ */
88734 
88735 #define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK      (0xFFFU)
88736 #define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT     (0U)
88737 /*! LOW_TEMP_VAL - Low temperature threshold value */
88738 #define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK)
88739 
88740 #define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK     (0xFFF0000U)
88741 #define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT    (16U)
88742 /*! HIGH_TEMP_VAL - High temperature threshold value */
88743 #define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL(x)       (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK)
88744 /*! @} */
88745 
88746 /*! @name RANGE0_TOG - Temperature Sensor Range Register 0 */
88747 /*! @{ */
88748 
88749 #define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK      (0xFFFU)
88750 #define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT     (0U)
88751 /*! LOW_TEMP_VAL - Low temperature threshold value */
88752 #define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL(x)        (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK)
88753 
88754 #define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK     (0xFFF0000U)
88755 #define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT    (16U)
88756 /*! HIGH_TEMP_VAL - High temperature threshold value */
88757 #define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL(x)       (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK)
88758 /*! @} */
88759 
88760 /*! @name RANGE1 - Temperature Sensor Range Register 1 */
88761 /*! @{ */
88762 
88763 #define TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK        (0xFFFU)
88764 #define TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT       (0U)
88765 /*! PANIC_TEMP_VAL - Panic temperature threshold value */
88766 #define TMPSNS_RANGE1_PANIC_TEMP_VAL(x)          (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK)
88767 /*! @} */
88768 
88769 /*! @name RANGE1_SET - Temperature Sensor Range Register 1 */
88770 /*! @{ */
88771 
88772 #define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK    (0xFFFU)
88773 #define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT   (0U)
88774 /*! PANIC_TEMP_VAL - Panic temperature threshold value */
88775 #define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL(x)      (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK)
88776 /*! @} */
88777 
88778 /*! @name RANGE1_CLR - Temperature Sensor Range Register 1 */
88779 /*! @{ */
88780 
88781 #define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK    (0xFFFU)
88782 #define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT   (0U)
88783 /*! PANIC_TEMP_VAL - Panic temperature threshold value */
88784 #define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL(x)      (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK)
88785 /*! @} */
88786 
88787 /*! @name RANGE1_TOG - Temperature Sensor Range Register 1 */
88788 /*! @{ */
88789 
88790 #define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK    (0xFFFU)
88791 #define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT   (0U)
88792 /*! PANIC_TEMP_VAL - Panic temperature threshold value */
88793 #define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL(x)      (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK)
88794 /*! @} */
88795 
88796 /*! @name STATUS0 - Temperature Sensor Status Register 0 */
88797 /*! @{ */
88798 
88799 #define TMPSNS_STATUS0_TEMP_VAL_MASK             (0xFFFU)
88800 #define TMPSNS_STATUS0_TEMP_VAL_SHIFT            (0U)
88801 /*! TEMP_VAL - Measured temperature value */
88802 #define TMPSNS_STATUS0_TEMP_VAL(x)               (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_TEMP_VAL_SHIFT)) & TMPSNS_STATUS0_TEMP_VAL_MASK)
88803 
88804 #define TMPSNS_STATUS0_FINISH_MASK               (0x10000U)
88805 #define TMPSNS_STATUS0_FINISH_SHIFT              (16U)
88806 /*! FINISH - Temperature measurement complete
88807  *  0b0..Temperature sensor is busy (if CTRL1[START] = 1)or no new reading has been initiated (if CTRL1[START] = 0)
88808  *  0b1..Temperature reading is complete and new temperature value available for reading
88809  */
88810 #define TMPSNS_STATUS0_FINISH(x)                 (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_FINISH_SHIFT)) & TMPSNS_STATUS0_FINISH_MASK)
88811 
88812 #define TMPSNS_STATUS0_LOW_TEMP_MASK             (0x20000U)
88813 #define TMPSNS_STATUS0_LOW_TEMP_SHIFT            (17U)
88814 /*! LOW_TEMP - Low temperature alarm bit
88815  *  0b0..No Low temperature alert
88816  *  0b1..Low temperature alert
88817  */
88818 #define TMPSNS_STATUS0_LOW_TEMP(x)               (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_LOW_TEMP_SHIFT)) & TMPSNS_STATUS0_LOW_TEMP_MASK)
88819 
88820 #define TMPSNS_STATUS0_HIGH_TEMP_MASK            (0x40000U)
88821 #define TMPSNS_STATUS0_HIGH_TEMP_SHIFT           (18U)
88822 /*! HIGH_TEMP - High temperature alarm bit
88823  *  0b0..No High temperature alert
88824  *  0b1..High temperature alert
88825  */
88826 #define TMPSNS_STATUS0_HIGH_TEMP(x)              (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_HIGH_TEMP_SHIFT)) & TMPSNS_STATUS0_HIGH_TEMP_MASK)
88827 
88828 #define TMPSNS_STATUS0_PANIC_TEMP_MASK           (0x80000U)
88829 #define TMPSNS_STATUS0_PANIC_TEMP_SHIFT          (19U)
88830 /*! PANIC_TEMP - Panic temperature alarm bit
88831  *  0b0..No Panic temperature alert
88832  *  0b1..Panic temperature alert
88833  */
88834 #define TMPSNS_STATUS0_PANIC_TEMP(x)             (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_PANIC_TEMP_SHIFT)) & TMPSNS_STATUS0_PANIC_TEMP_MASK)
88835 /*! @} */
88836 
88837 
88838 /*!
88839  * @}
88840  */ /* end of group TMPSNS_Register_Masks */
88841 
88842 
88843 /* TMPSNS - Peripheral instance base addresses */
88844 /** Peripheral TMPSNS base address */
88845 #define TMPSNS_BASE                              (0u)
88846 /** Peripheral TMPSNS base pointer */
88847 #define TMPSNS                                   ((TMPSNS_Type *)TMPSNS_BASE)
88848 /** Array initializer of TMPSNS peripheral base addresses */
88849 #define TMPSNS_BASE_ADDRS                        { TMPSNS_BASE }
88850 /** Array initializer of TMPSNS peripheral base pointers */
88851 #define TMPSNS_BASE_PTRS                         { TMPSNS }
88852 
88853 /*!
88854  * @}
88855  */ /* end of group TMPSNS_Peripheral_Access_Layer */
88856 
88857 
88858 /* ----------------------------------------------------------------------------
88859    -- TMR Peripheral Access Layer
88860    ---------------------------------------------------------------------------- */
88861 
88862 /*!
88863  * @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer
88864  * @{
88865  */
88866 
88867 /** TMR - Register Layout Typedef */
88868 typedef struct {
88869   struct {                                         /* offset: 0x0, array step: 0x20 */
88870     __IO uint16_t COMP1;                             /**< Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20 */
88871     __IO uint16_t COMP2;                             /**< Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20 */
88872     __IO uint16_t CAPT;                              /**< Timer Channel Capture Register, array offset: 0x4, array step: 0x20 */
88873     __IO uint16_t LOAD;                              /**< Timer Channel Load Register, array offset: 0x6, array step: 0x20 */
88874     __IO uint16_t HOLD;                              /**< Timer Channel Hold Register, array offset: 0x8, array step: 0x20 */
88875     __IO uint16_t CNTR;                              /**< Timer Channel Counter Register, array offset: 0xA, array step: 0x20 */
88876     __IO uint16_t CTRL;                              /**< Timer Channel Control Register, array offset: 0xC, array step: 0x20 */
88877     __IO uint16_t SCTRL;                             /**< Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20 */
88878     __IO uint16_t CMPLD1;                            /**< Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20 */
88879     __IO uint16_t CMPLD2;                            /**< Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20 */
88880     __IO uint16_t CSCTRL;                            /**< Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20 */
88881     __IO uint16_t FILT;                              /**< Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20 */
88882     __IO uint16_t DMA;                               /**< Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20 */
88883          uint8_t RESERVED_0[4];
88884     __IO uint16_t ENBL;                              /**< Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, valid indices: [0] */
88885   } CHANNEL[4];
88886 } TMR_Type;
88887 
88888 /* ----------------------------------------------------------------------------
88889    -- TMR Register Masks
88890    ---------------------------------------------------------------------------- */
88891 
88892 /*!
88893  * @addtogroup TMR_Register_Masks TMR Register Masks
88894  * @{
88895  */
88896 
88897 /*! @name COMP1 - Timer Channel Compare Register 1 */
88898 /*! @{ */
88899 
88900 #define TMR_COMP1_COMPARISON_1_MASK              (0xFFFFU)
88901 #define TMR_COMP1_COMPARISON_1_SHIFT             (0U)
88902 /*! COMPARISON_1 - Comparison Value 1 */
88903 #define TMR_COMP1_COMPARISON_1(x)                (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)
88904 /*! @} */
88905 
88906 /* The count of TMR_COMP1 */
88907 #define TMR_COMP1_COUNT                          (4U)
88908 
88909 /*! @name COMP2 - Timer Channel Compare Register 2 */
88910 /*! @{ */
88911 
88912 #define TMR_COMP2_COMPARISON_2_MASK              (0xFFFFU)
88913 #define TMR_COMP2_COMPARISON_2_SHIFT             (0U)
88914 /*! COMPARISON_2 - Comparison Value 2 */
88915 #define TMR_COMP2_COMPARISON_2(x)                (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)
88916 /*! @} */
88917 
88918 /* The count of TMR_COMP2 */
88919 #define TMR_COMP2_COUNT                          (4U)
88920 
88921 /*! @name CAPT - Timer Channel Capture Register */
88922 /*! @{ */
88923 
88924 #define TMR_CAPT_CAPTURE_MASK                    (0xFFFFU)
88925 #define TMR_CAPT_CAPTURE_SHIFT                   (0U)
88926 /*! CAPTURE - Capture Value */
88927 #define TMR_CAPT_CAPTURE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)
88928 /*! @} */
88929 
88930 /* The count of TMR_CAPT */
88931 #define TMR_CAPT_COUNT                           (4U)
88932 
88933 /*! @name LOAD - Timer Channel Load Register */
88934 /*! @{ */
88935 
88936 #define TMR_LOAD_LOAD_MASK                       (0xFFFFU)
88937 #define TMR_LOAD_LOAD_SHIFT                      (0U)
88938 /*! LOAD - Timer Load Register */
88939 #define TMR_LOAD_LOAD(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)
88940 /*! @} */
88941 
88942 /* The count of TMR_LOAD */
88943 #define TMR_LOAD_COUNT                           (4U)
88944 
88945 /*! @name HOLD - Timer Channel Hold Register */
88946 /*! @{ */
88947 
88948 #define TMR_HOLD_HOLD_MASK                       (0xFFFFU)
88949 #define TMR_HOLD_HOLD_SHIFT                      (0U)
88950 /*! HOLD - HOLD */
88951 #define TMR_HOLD_HOLD(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)
88952 /*! @} */
88953 
88954 /* The count of TMR_HOLD */
88955 #define TMR_HOLD_COUNT                           (4U)
88956 
88957 /*! @name CNTR - Timer Channel Counter Register */
88958 /*! @{ */
88959 
88960 #define TMR_CNTR_COUNTER_MASK                    (0xFFFFU)
88961 #define TMR_CNTR_COUNTER_SHIFT                   (0U)
88962 /*! COUNTER - COUNTER */
88963 #define TMR_CNTR_COUNTER(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)
88964 /*! @} */
88965 
88966 /* The count of TMR_CNTR */
88967 #define TMR_CNTR_COUNT                           (4U)
88968 
88969 /*! @name CTRL - Timer Channel Control Register */
88970 /*! @{ */
88971 
88972 #define TMR_CTRL_OUTMODE_MASK                    (0x7U)
88973 #define TMR_CTRL_OUTMODE_SHIFT                   (0U)
88974 /*! OUTMODE - Output Mode
88975  *  0b000..Asserted while counter is active
88976  *  0b001..Clear OFLAG output on successful compare
88977  *  0b010..Set OFLAG output on successful compare
88978  *  0b011..Toggle OFLAG output on successful compare
88979  *  0b100..Toggle OFLAG output using alternating compare registers
88980  *  0b101..Set on compare, cleared on secondary source input edge
88981  *  0b110..Set on compare, cleared on counter rollover
88982  *  0b111..Enable gated clock output while counter is active
88983  */
88984 #define TMR_CTRL_OUTMODE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
88985 
88986 #define TMR_CTRL_COINIT_MASK                     (0x8U)
88987 #define TMR_CTRL_COINIT_SHIFT                    (3U)
88988 /*! COINIT - Co-Channel Initialization
88989  *  0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer
88990  *  0b1..Co-channel counter/timers may force a re-initialization of this counter/timer
88991  */
88992 #define TMR_CTRL_COINIT(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
88993 
88994 #define TMR_CTRL_DIR_MASK                        (0x10U)
88995 #define TMR_CTRL_DIR_SHIFT                       (4U)
88996 /*! DIR - Count Direction
88997  *  0b0..Count up.
88998  *  0b1..Count down.
88999  */
89000 #define TMR_CTRL_DIR(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
89001 
89002 #define TMR_CTRL_LENGTH_MASK                     (0x20U)
89003 #define TMR_CTRL_LENGTH_SHIFT                    (5U)
89004 /*! LENGTH - Count Length
89005  *  0b0..Count until roll over at $FFFF and continue from $0000.
89006  *  0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter
89007  *       reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value.
89008  *       When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful
89009  *       comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2
89010  *       value is reached, re-initializes, counts until COMP1 value is reached, and so on.
89011  */
89012 #define TMR_CTRL_LENGTH(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
89013 
89014 #define TMR_CTRL_ONCE_MASK                       (0x40U)
89015 #define TMR_CTRL_ONCE_SHIFT                      (6U)
89016 /*! ONCE - Count Once
89017  *  0b0..Count repeatedly.
89018  *  0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a
89019  *       COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When
89020  *       output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to
89021  *       the COMP2 value, and then stops.
89022  */
89023 #define TMR_CTRL_ONCE(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
89024 
89025 #define TMR_CTRL_SCS_MASK                        (0x180U)
89026 #define TMR_CTRL_SCS_SHIFT                       (7U)
89027 /*! SCS - Secondary Count Source
89028  *  0b00..Counter 0 input pin
89029  *  0b01..Counter 1 input pin
89030  *  0b10..Counter 2 input pin
89031  *  0b11..Counter 3 input pin
89032  */
89033 #define TMR_CTRL_SCS(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
89034 
89035 #define TMR_CTRL_PCS_MASK                        (0x1E00U)
89036 #define TMR_CTRL_PCS_SHIFT                       (9U)
89037 /*! PCS - Primary Count Source
89038  *  0b0000..Counter 0 input pin
89039  *  0b0001..Counter 1 input pin
89040  *  0b0010..Counter 2 input pin
89041  *  0b0011..Counter 3 input pin
89042  *  0b0100..Counter 0 output
89043  *  0b0101..Counter 1 output
89044  *  0b0110..Counter 2 output
89045  *  0b0111..Counter 3 output
89046  *  0b1000..IP bus clock divide by 1 prescaler
89047  *  0b1001..IP bus clock divide by 2 prescaler
89048  *  0b1010..IP bus clock divide by 4 prescaler
89049  *  0b1011..IP bus clock divide by 8 prescaler
89050  *  0b1100..IP bus clock divide by 16 prescaler
89051  *  0b1101..IP bus clock divide by 32 prescaler
89052  *  0b1110..IP bus clock divide by 64 prescaler
89053  *  0b1111..IP bus clock divide by 128 prescaler
89054  */
89055 #define TMR_CTRL_PCS(x)                          (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
89056 
89057 #define TMR_CTRL_CM_MASK                         (0xE000U)
89058 #define TMR_CTRL_CM_SHIFT                        (13U)
89059 /*! CM - Count Mode
89060  *  0b000..No operation
89061  *  0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges
89062  *         are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising
89063  *         edges are counted regardless of the value of SCTRL[IPS].
89064  *  0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.
89065  *  0b011..Count rising edges of primary source while secondary input high active
89066  *  0b100..Quadrature count mode, uses primary and secondary sources
89067  *  0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only
89068  *         when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.
89069  *  0b110..Edge of secondary source triggers primary count until compare
89070  *  0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.
89071  */
89072 #define TMR_CTRL_CM(x)                           (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
89073 /*! @} */
89074 
89075 /* The count of TMR_CTRL */
89076 #define TMR_CTRL_COUNT                           (4U)
89077 
89078 /*! @name SCTRL - Timer Channel Status and Control Register */
89079 /*! @{ */
89080 
89081 #define TMR_SCTRL_OEN_MASK                       (0x1U)
89082 #define TMR_SCTRL_OEN_SHIFT                      (0U)
89083 /*! OEN - Output Enable
89084  *  0b0..The external pin is configured as an input.
89085  *  0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as
89086  *       their input see the driven value. The polarity of the signal is determined by OPS.
89087  */
89088 #define TMR_SCTRL_OEN(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
89089 
89090 #define TMR_SCTRL_OPS_MASK                       (0x2U)
89091 #define TMR_SCTRL_OPS_SHIFT                      (1U)
89092 /*! OPS - Output Polarity Select
89093  *  0b0..True polarity.
89094  *  0b1..Inverted polarity.
89095  */
89096 #define TMR_SCTRL_OPS(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
89097 
89098 #define TMR_SCTRL_FORCE_MASK                     (0x4U)
89099 #define TMR_SCTRL_FORCE_SHIFT                    (2U)
89100 /*! FORCE - Force OFLAG Output */
89101 #define TMR_SCTRL_FORCE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
89102 
89103 #define TMR_SCTRL_VAL_MASK                       (0x8U)
89104 #define TMR_SCTRL_VAL_SHIFT                      (3U)
89105 /*! VAL - Forced OFLAG Value */
89106 #define TMR_SCTRL_VAL(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
89107 
89108 #define TMR_SCTRL_EEOF_MASK                      (0x10U)
89109 #define TMR_SCTRL_EEOF_SHIFT                     (4U)
89110 /*! EEOF - Enable External OFLAG Force */
89111 #define TMR_SCTRL_EEOF(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
89112 
89113 #define TMR_SCTRL_MSTR_MASK                      (0x20U)
89114 #define TMR_SCTRL_MSTR_SHIFT                     (5U)
89115 /*! MSTR - Master Mode */
89116 #define TMR_SCTRL_MSTR(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
89117 
89118 #define TMR_SCTRL_CAPTURE_MODE_MASK              (0xC0U)
89119 #define TMR_SCTRL_CAPTURE_MODE_SHIFT             (6U)
89120 /*! CAPTURE_MODE - Input Capture Mode
89121  *  0b00..Capture function is disabled
89122  *  0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input
89123  *  0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input
89124  *  0b11..Load capture register on both edges of input
89125  */
89126 #define TMR_SCTRL_CAPTURE_MODE(x)                (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
89127 
89128 #define TMR_SCTRL_INPUT_MASK                     (0x100U)
89129 #define TMR_SCTRL_INPUT_SHIFT                    (8U)
89130 /*! INPUT - External Input Signal */
89131 #define TMR_SCTRL_INPUT(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
89132 
89133 #define TMR_SCTRL_IPS_MASK                       (0x200U)
89134 #define TMR_SCTRL_IPS_SHIFT                      (9U)
89135 /*! IPS - Input Polarity Select */
89136 #define TMR_SCTRL_IPS(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
89137 
89138 #define TMR_SCTRL_IEFIE_MASK                     (0x400U)
89139 #define TMR_SCTRL_IEFIE_SHIFT                    (10U)
89140 /*! IEFIE - Input Edge Flag Interrupt Enable */
89141 #define TMR_SCTRL_IEFIE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
89142 
89143 #define TMR_SCTRL_IEF_MASK                       (0x800U)
89144 #define TMR_SCTRL_IEF_SHIFT                      (11U)
89145 /*! IEF - Input Edge Flag */
89146 #define TMR_SCTRL_IEF(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
89147 
89148 #define TMR_SCTRL_TOFIE_MASK                     (0x1000U)
89149 #define TMR_SCTRL_TOFIE_SHIFT                    (12U)
89150 /*! TOFIE - Timer Overflow Flag Interrupt Enable */
89151 #define TMR_SCTRL_TOFIE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
89152 
89153 #define TMR_SCTRL_TOF_MASK                       (0x2000U)
89154 #define TMR_SCTRL_TOF_SHIFT                      (13U)
89155 /*! TOF - Timer Overflow Flag */
89156 #define TMR_SCTRL_TOF(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
89157 
89158 #define TMR_SCTRL_TCFIE_MASK                     (0x4000U)
89159 #define TMR_SCTRL_TCFIE_SHIFT                    (14U)
89160 /*! TCFIE - Timer Compare Flag Interrupt Enable */
89161 #define TMR_SCTRL_TCFIE(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
89162 
89163 #define TMR_SCTRL_TCF_MASK                       (0x8000U)
89164 #define TMR_SCTRL_TCF_SHIFT                      (15U)
89165 /*! TCF - Timer Compare Flag */
89166 #define TMR_SCTRL_TCF(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)
89167 /*! @} */
89168 
89169 /* The count of TMR_SCTRL */
89170 #define TMR_SCTRL_COUNT                          (4U)
89171 
89172 /*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */
89173 /*! @{ */
89174 
89175 #define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK        (0xFFFFU)
89176 #define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT       (0U)
89177 /*! COMPARATOR_LOAD_1 - COMPARATOR_LOAD_1 */
89178 #define TMR_CMPLD1_COMPARATOR_LOAD_1(x)          (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)
89179 /*! @} */
89180 
89181 /* The count of TMR_CMPLD1 */
89182 #define TMR_CMPLD1_COUNT                         (4U)
89183 
89184 /*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */
89185 /*! @{ */
89186 
89187 #define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK        (0xFFFFU)
89188 #define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT       (0U)
89189 /*! COMPARATOR_LOAD_2 - COMPARATOR_LOAD_2 */
89190 #define TMR_CMPLD2_COMPARATOR_LOAD_2(x)          (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)
89191 /*! @} */
89192 
89193 /* The count of TMR_CMPLD2 */
89194 #define TMR_CMPLD2_COUNT                         (4U)
89195 
89196 /*! @name CSCTRL - Timer Channel Comparator Status and Control Register */
89197 /*! @{ */
89198 
89199 #define TMR_CSCTRL_CL1_MASK                      (0x3U)
89200 #define TMR_CSCTRL_CL1_SHIFT                     (0U)
89201 /*! CL1 - Compare Load Control 1
89202  *  0b00..Never preload
89203  *  0b01..Load upon successful compare with the value in COMP1
89204  *  0b10..Load upon successful compare with the value in COMP2
89205  *  0b11..Reserved
89206  */
89207 #define TMR_CSCTRL_CL1(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
89208 
89209 #define TMR_CSCTRL_CL2_MASK                      (0xCU)
89210 #define TMR_CSCTRL_CL2_SHIFT                     (2U)
89211 /*! CL2 - Compare Load Control 2
89212  *  0b00..Never preload
89213  *  0b01..Load upon successful compare with the value in COMP1
89214  *  0b10..Load upon successful compare with the value in COMP2
89215  *  0b11..Reserved
89216  */
89217 #define TMR_CSCTRL_CL2(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
89218 
89219 #define TMR_CSCTRL_TCF1_MASK                     (0x10U)
89220 #define TMR_CSCTRL_TCF1_SHIFT                    (4U)
89221 /*! TCF1 - Timer Compare 1 Interrupt Flag */
89222 #define TMR_CSCTRL_TCF1(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
89223 
89224 #define TMR_CSCTRL_TCF2_MASK                     (0x20U)
89225 #define TMR_CSCTRL_TCF2_SHIFT                    (5U)
89226 /*! TCF2 - Timer Compare 2 Interrupt Flag */
89227 #define TMR_CSCTRL_TCF2(x)                       (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
89228 
89229 #define TMR_CSCTRL_TCF1EN_MASK                   (0x40U)
89230 #define TMR_CSCTRL_TCF1EN_SHIFT                  (6U)
89231 /*! TCF1EN - Timer Compare 1 Interrupt Enable */
89232 #define TMR_CSCTRL_TCF1EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
89233 
89234 #define TMR_CSCTRL_TCF2EN_MASK                   (0x80U)
89235 #define TMR_CSCTRL_TCF2EN_SHIFT                  (7U)
89236 /*! TCF2EN - Timer Compare 2 Interrupt Enable */
89237 #define TMR_CSCTRL_TCF2EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
89238 
89239 #define TMR_CSCTRL_OFLAG_MASK                    (0x100U)
89240 #define TMR_CSCTRL_OFLAG_SHIFT                   (8U)
89241 /*! OFLAG - Output flag */
89242 #define TMR_CSCTRL_OFLAG(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_OFLAG_SHIFT)) & TMR_CSCTRL_OFLAG_MASK)
89243 
89244 #define TMR_CSCTRL_UP_MASK                       (0x200U)
89245 #define TMR_CSCTRL_UP_SHIFT                      (9U)
89246 /*! UP - Counting Direction Indicator
89247  *  0b0..The last count was in the DOWN direction.
89248  *  0b1..The last count was in the UP direction.
89249  */
89250 #define TMR_CSCTRL_UP(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
89251 
89252 #define TMR_CSCTRL_TCI_MASK                      (0x400U)
89253 #define TMR_CSCTRL_TCI_SHIFT                     (10U)
89254 /*! TCI - Triggered Count Initialization Control
89255  *  0b0..Stop the counter upon receiving a second trigger event while still counting from the first trigger event.
89256  *  0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event.
89257  */
89258 #define TMR_CSCTRL_TCI(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
89259 
89260 #define TMR_CSCTRL_ROC_MASK                      (0x800U)
89261 #define TMR_CSCTRL_ROC_SHIFT                     (11U)
89262 /*! ROC - Reload on Capture
89263  *  0b0..Disables
89264  *  0b1..Enables
89265  */
89266 #define TMR_CSCTRL_ROC(x)                        (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
89267 
89268 #define TMR_CSCTRL_ALT_LOAD_MASK                 (0x1000U)
89269 #define TMR_CSCTRL_ALT_LOAD_SHIFT                (12U)
89270 /*! ALT_LOAD - Alternative Load Enable
89271  *  0b0..Counter can be re-initialized only with the LOAD register.
89272  *  0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.
89273  */
89274 #define TMR_CSCTRL_ALT_LOAD(x)                   (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
89275 
89276 #define TMR_CSCTRL_FAULT_MASK                    (0x2000U)
89277 #define TMR_CSCTRL_FAULT_SHIFT                   (13U)
89278 /*! FAULT - Fault Enable
89279  *  0b0..Disables
89280  *  0b1..Enables
89281  */
89282 #define TMR_CSCTRL_FAULT(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
89283 
89284 #define TMR_CSCTRL_DBG_EN_MASK                   (0xC000U)
89285 #define TMR_CSCTRL_DBG_EN_SHIFT                  (14U)
89286 /*! DBG_EN - Debug Actions Enable
89287  *  0b00..Continue with normal operation during debug mode. (default)
89288  *  0b01..Halt TMR counter during debug mode.
89289  *  0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).
89290  *  0b11..Both halt counter and force output to 0 during debug mode.
89291  */
89292 #define TMR_CSCTRL_DBG_EN(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
89293 /*! @} */
89294 
89295 /* The count of TMR_CSCTRL */
89296 #define TMR_CSCTRL_COUNT                         (4U)
89297 
89298 /*! @name FILT - Timer Channel Input Filter Register */
89299 /*! @{ */
89300 
89301 #define TMR_FILT_FILT_PER_MASK                   (0xFFU)
89302 #define TMR_FILT_FILT_PER_SHIFT                  (0U)
89303 /*! FILT_PER - Input Filter Sample Period */
89304 #define TMR_FILT_FILT_PER(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
89305 
89306 #define TMR_FILT_FILT_CNT_MASK                   (0x700U)
89307 #define TMR_FILT_FILT_CNT_SHIFT                  (8U)
89308 /*! FILT_CNT - Input Filter Sample Count */
89309 #define TMR_FILT_FILT_CNT(x)                     (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)
89310 /*! @} */
89311 
89312 /* The count of TMR_FILT */
89313 #define TMR_FILT_COUNT                           (4U)
89314 
89315 /*! @name DMA - Timer Channel DMA Enable Register */
89316 /*! @{ */
89317 
89318 #define TMR_DMA_IEFDE_MASK                       (0x1U)
89319 #define TMR_DMA_IEFDE_SHIFT                      (0U)
89320 /*! IEFDE - Input Edge Flag DMA Enable */
89321 #define TMR_DMA_IEFDE(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
89322 
89323 #define TMR_DMA_CMPLD1DE_MASK                    (0x2U)
89324 #define TMR_DMA_CMPLD1DE_SHIFT                   (1U)
89325 /*! CMPLD1DE - Comparator Preload Register 1 DMA Enable */
89326 #define TMR_DMA_CMPLD1DE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
89327 
89328 #define TMR_DMA_CMPLD2DE_MASK                    (0x4U)
89329 #define TMR_DMA_CMPLD2DE_SHIFT                   (2U)
89330 /*! CMPLD2DE - Comparator Preload Register 2 DMA Enable */
89331 #define TMR_DMA_CMPLD2DE(x)                      (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)
89332 /*! @} */
89333 
89334 /* The count of TMR_DMA */
89335 #define TMR_DMA_COUNT                            (4U)
89336 
89337 /*! @name ENBL - Timer Channel Enable Register */
89338 /*! @{ */
89339 
89340 #define TMR_ENBL_ENBL_MASK                       (0xFU)
89341 #define TMR_ENBL_ENBL_SHIFT                      (0U)
89342 /*! ENBL - Timer Channel Enable
89343  *  0b0000..Disables the timer channel.
89344  *  0b0001..Enables the timer channel. (default)
89345  */
89346 #define TMR_ENBL_ENBL(x)                         (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
89347 /*! @} */
89348 
89349 /* The count of TMR_ENBL */
89350 #define TMR_ENBL_COUNT                           (4U)
89351 
89352 
89353 /*!
89354  * @}
89355  */ /* end of group TMR_Register_Masks */
89356 
89357 
89358 /* TMR - Peripheral instance base addresses */
89359 /** Peripheral TMR1 base address */
89360 #define TMR1_BASE                                (0x4015C000u)
89361 /** Peripheral TMR1 base pointer */
89362 #define TMR1                                     ((TMR_Type *)TMR1_BASE)
89363 /** Peripheral TMR2 base address */
89364 #define TMR2_BASE                                (0x40160000u)
89365 /** Peripheral TMR2 base pointer */
89366 #define TMR2                                     ((TMR_Type *)TMR2_BASE)
89367 /** Peripheral TMR3 base address */
89368 #define TMR3_BASE                                (0x40164000u)
89369 /** Peripheral TMR3 base pointer */
89370 #define TMR3                                     ((TMR_Type *)TMR3_BASE)
89371 /** Peripheral TMR4 base address */
89372 #define TMR4_BASE                                (0x40168000u)
89373 /** Peripheral TMR4 base pointer */
89374 #define TMR4                                     ((TMR_Type *)TMR4_BASE)
89375 /** Array initializer of TMR peripheral base addresses */
89376 #define TMR_BASE_ADDRS                           { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
89377 /** Array initializer of TMR peripheral base pointers */
89378 #define TMR_BASE_PTRS                            { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
89379 /** Interrupt vectors for the TMR peripheral type */
89380 #define TMR_IRQS                                 { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
89381 
89382 /*!
89383  * @}
89384  */ /* end of group TMR_Peripheral_Access_Layer */
89385 
89386 
89387 /* ----------------------------------------------------------------------------
89388    -- USB Peripheral Access Layer
89389    ---------------------------------------------------------------------------- */
89390 
89391 /*!
89392  * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
89393  * @{
89394  */
89395 
89396 /** USB - Register Layout Typedef */
89397 typedef struct {
89398   __I  uint32_t ID;                                /**< Identification register, offset: 0x0 */
89399   __I  uint32_t HWGENERAL;                         /**< Hardware General, offset: 0x4 */
89400   __I  uint32_t HWHOST;                            /**< Host Hardware Parameters, offset: 0x8 */
89401   __I  uint32_t HWDEVICE;                          /**< Device Hardware Parameters, offset: 0xC */
89402   __I  uint32_t HWTXBUF;                           /**< TX Buffer Hardware Parameters, offset: 0x10 */
89403   __I  uint32_t HWRXBUF;                           /**< RX Buffer Hardware Parameters, offset: 0x14 */
89404        uint8_t RESERVED_0[104];
89405   __IO uint32_t GPTIMER0LD;                        /**< General Purpose Timer #0 Load, offset: 0x80 */
89406   __IO uint32_t GPTIMER0CTRL;                      /**< General Purpose Timer #0 Controller, offset: 0x84 */
89407   __IO uint32_t GPTIMER1LD;                        /**< General Purpose Timer #1 Load, offset: 0x88 */
89408   __IO uint32_t GPTIMER1CTRL;                      /**< General Purpose Timer #1 Controller, offset: 0x8C */
89409   __IO uint32_t SBUSCFG;                           /**< System Bus Config, offset: 0x90 */
89410        uint8_t RESERVED_1[108];
89411   __I  uint8_t CAPLENGTH;                          /**< Capability Registers Length, offset: 0x100 */
89412        uint8_t RESERVED_2[1];
89413   __I  uint16_t HCIVERSION;                        /**< Host Controller Interface Version, offset: 0x102 */
89414   __I  uint32_t HCSPARAMS;                         /**< Host Controller Structural Parameters, offset: 0x104 */
89415   __I  uint32_t HCCPARAMS;                         /**< Host Controller Capability Parameters, offset: 0x108 */
89416        uint8_t RESERVED_3[20];
89417   __I  uint16_t DCIVERSION;                        /**< Device Controller Interface Version, offset: 0x120 */
89418        uint8_t RESERVED_4[2];
89419   __I  uint32_t DCCPARAMS;                         /**< Device Controller Capability Parameters, offset: 0x124 */
89420        uint8_t RESERVED_5[24];
89421   __IO uint32_t USBCMD;                            /**< USB Command Register, offset: 0x140 */
89422   __IO uint32_t USBSTS;                            /**< USB Status Register, offset: 0x144 */
89423   __IO uint32_t USBINTR;                           /**< Interrupt Enable Register, offset: 0x148 */
89424   __IO uint32_t FRINDEX;                           /**< USB Frame Index, offset: 0x14C */
89425        uint8_t RESERVED_6[4];
89426   union {                                          /* offset: 0x154 */
89427     __IO uint32_t DEVICEADDR;                        /**< Device Address, offset: 0x154 */
89428     __IO uint32_t PERIODICLISTBASE;                  /**< Frame List Base Address, offset: 0x154 */
89429   };
89430   union {                                          /* offset: 0x158 */
89431     __IO uint32_t ASYNCLISTADDR;                     /**< Next Asynch. Address, offset: 0x158 */
89432     __IO uint32_t ENDPTLISTADDR;                     /**< Endpoint List Address, offset: 0x158 */
89433   };
89434        uint8_t RESERVED_7[4];
89435   __IO uint32_t BURSTSIZE;                         /**< Programmable Burst Size, offset: 0x160 */
89436   __IO uint32_t TXFILLTUNING;                      /**< TX FIFO Fill Tuning, offset: 0x164 */
89437        uint8_t RESERVED_8[16];
89438   __IO uint32_t ENDPTNAK;                          /**< Endpoint NAK, offset: 0x178 */
89439   __IO uint32_t ENDPTNAKEN;                        /**< Endpoint NAK Enable, offset: 0x17C */
89440   __I  uint32_t CONFIGFLAG;                        /**< Configure Flag Register, offset: 0x180 */
89441   __IO uint32_t PORTSC1;                           /**< Port Status & Control, offset: 0x184 */
89442        uint8_t RESERVED_9[28];
89443   __IO uint32_t OTGSC;                             /**< On-The-Go Status & control, offset: 0x1A4 */
89444   __IO uint32_t USBMODE;                           /**< USB Device Mode, offset: 0x1A8 */
89445   __IO uint32_t ENDPTSETUPSTAT;                    /**< Endpoint Setup Status, offset: 0x1AC */
89446   __IO uint32_t ENDPTPRIME;                        /**< Endpoint Prime, offset: 0x1B0 */
89447   __IO uint32_t ENDPTFLUSH;                        /**< Endpoint Flush, offset: 0x1B4 */
89448   __I  uint32_t ENDPTSTAT;                         /**< Endpoint Status, offset: 0x1B8 */
89449   __IO uint32_t ENDPTCOMPLETE;                     /**< Endpoint Complete, offset: 0x1BC */
89450   __IO uint32_t ENDPTCTRL0;                        /**< Endpoint Control0, offset: 0x1C0 */
89451   __IO uint32_t ENDPTCTRL[7];                      /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */
89452 } USB_Type;
89453 
89454 /* ----------------------------------------------------------------------------
89455    -- USB Register Masks
89456    ---------------------------------------------------------------------------- */
89457 
89458 /*!
89459  * @addtogroup USB_Register_Masks USB Register Masks
89460  * @{
89461  */
89462 
89463 /*! @name ID - Identification register */
89464 /*! @{ */
89465 
89466 #define USB_ID_ID_MASK                           (0x3FU)
89467 #define USB_ID_ID_SHIFT                          (0U)
89468 /*! ID - ID */
89469 #define USB_ID_ID(x)                             (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
89470 
89471 #define USB_ID_NID_MASK                          (0x3F00U)
89472 #define USB_ID_NID_SHIFT                         (8U)
89473 /*! NID - NID */
89474 #define USB_ID_NID(x)                            (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
89475 
89476 #define USB_ID_REVISION_MASK                     (0xFF0000U)
89477 #define USB_ID_REVISION_SHIFT                    (16U)
89478 /*! REVISION - REVISION */
89479 #define USB_ID_REVISION(x)                       (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
89480 /*! @} */
89481 
89482 /*! @name HWGENERAL - Hardware General */
89483 /*! @{ */
89484 
89485 #define USB_HWGENERAL_PHYW_MASK                  (0x30U)
89486 #define USB_HWGENERAL_PHYW_SHIFT                 (4U)
89487 /*! PHYW - PHYW
89488  *  0b00..8 bit wide data bus (Software non-programmable)
89489  *  0b01..16 bit wide data bus (Software non-programmable)
89490  *  0b10..Reset to 8 bit wide data bus (Software programmable)
89491  *  0b11..Reset to 16 bit wide data bus (Software programmable)
89492  */
89493 #define USB_HWGENERAL_PHYW(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
89494 
89495 #define USB_HWGENERAL_PHYM_MASK                  (0x1C0U)
89496 #define USB_HWGENERAL_PHYM_SHIFT                 (6U)
89497 /*! PHYM - PHYM
89498  *  0b000..UTMI/UMTI+
89499  *  0b001..ULPI DDR
89500  *  0b010..ULPI
89501  *  0b011..Serial Only
89502  *  0b100..Software programmable - reset to UTMI/UTMI+
89503  *  0b101..Software programmable - reset to ULPI DDR
89504  *  0b110..Software programmable - reset to ULPI
89505  *  0b111..Software programmable - reset to Serial
89506  */
89507 #define USB_HWGENERAL_PHYM(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
89508 
89509 #define USB_HWGENERAL_SM_MASK                    (0x600U)
89510 #define USB_HWGENERAL_SM_SHIFT                   (9U)
89511 /*! SM - SM
89512  *  0b00..No Serial Engine, always use parallel signalling.
89513  *  0b01..Serial Engine present, always use serial signalling for FS/LS.
89514  *  0b10..Software programmable - Reset to use parallel signalling for FS/LS
89515  *  0b11..Software programmable - Reset to use serial signalling for FS/LS
89516  */
89517 #define USB_HWGENERAL_SM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
89518 /*! @} */
89519 
89520 /*! @name HWHOST - Host Hardware Parameters */
89521 /*! @{ */
89522 
89523 #define USB_HWHOST_HC_MASK                       (0x1U)
89524 #define USB_HWHOST_HC_SHIFT                      (0U)
89525 /*! HC - HC
89526  *  0b1..Supported
89527  *  0b0..Not supported
89528  */
89529 #define USB_HWHOST_HC(x)                         (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
89530 
89531 #define USB_HWHOST_NPORT_MASK                    (0xEU)
89532 #define USB_HWHOST_NPORT_SHIFT                   (1U)
89533 /*! NPORT - NPORT */
89534 #define USB_HWHOST_NPORT(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
89535 /*! @} */
89536 
89537 /*! @name HWDEVICE - Device Hardware Parameters */
89538 /*! @{ */
89539 
89540 #define USB_HWDEVICE_DC_MASK                     (0x1U)
89541 #define USB_HWDEVICE_DC_SHIFT                    (0U)
89542 /*! DC - DC
89543  *  0b1..Supported
89544  *  0b0..Not supported
89545  */
89546 #define USB_HWDEVICE_DC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
89547 
89548 #define USB_HWDEVICE_DEVEP_MASK                  (0x3EU)
89549 #define USB_HWDEVICE_DEVEP_SHIFT                 (1U)
89550 /*! DEVEP - DEVEP */
89551 #define USB_HWDEVICE_DEVEP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
89552 /*! @} */
89553 
89554 /*! @name HWTXBUF - TX Buffer Hardware Parameters */
89555 /*! @{ */
89556 
89557 #define USB_HWTXBUF_TXBURST_MASK                 (0xFFU)
89558 #define USB_HWTXBUF_TXBURST_SHIFT                (0U)
89559 /*! TXBURST - TXBURST */
89560 #define USB_HWTXBUF_TXBURST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
89561 
89562 #define USB_HWTXBUF_TXCHANADD_MASK               (0xFF0000U)
89563 #define USB_HWTXBUF_TXCHANADD_SHIFT              (16U)
89564 /*! TXCHANADD - TXCHANADD */
89565 #define USB_HWTXBUF_TXCHANADD(x)                 (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
89566 /*! @} */
89567 
89568 /*! @name HWRXBUF - RX Buffer Hardware Parameters */
89569 /*! @{ */
89570 
89571 #define USB_HWRXBUF_RXBURST_MASK                 (0xFFU)
89572 #define USB_HWRXBUF_RXBURST_SHIFT                (0U)
89573 /*! RXBURST - RXBURST */
89574 #define USB_HWRXBUF_RXBURST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
89575 
89576 #define USB_HWRXBUF_RXADD_MASK                   (0xFF00U)
89577 #define USB_HWRXBUF_RXADD_SHIFT                  (8U)
89578 /*! RXADD - RXADD */
89579 #define USB_HWRXBUF_RXADD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
89580 /*! @} */
89581 
89582 /*! @name GPTIMER0LD - General Purpose Timer #0 Load */
89583 /*! @{ */
89584 
89585 #define USB_GPTIMER0LD_GPTLD_MASK                (0xFFFFFFU)
89586 #define USB_GPTIMER0LD_GPTLD_SHIFT               (0U)
89587 /*! GPTLD - GPTLD */
89588 #define USB_GPTIMER0LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
89589 /*! @} */
89590 
89591 /*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */
89592 /*! @{ */
89593 
89594 #define USB_GPTIMER0CTRL_GPTCNT_MASK             (0xFFFFFFU)
89595 #define USB_GPTIMER0CTRL_GPTCNT_SHIFT            (0U)
89596 /*! GPTCNT - GPTCNT */
89597 #define USB_GPTIMER0CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
89598 
89599 #define USB_GPTIMER0CTRL_GPTMODE_MASK            (0x1000000U)
89600 #define USB_GPTIMER0CTRL_GPTMODE_SHIFT           (24U)
89601 /*! GPTMODE - GPTMODE
89602  *  0b0..One Shot Mode
89603  *  0b1..Repeat Mode
89604  */
89605 #define USB_GPTIMER0CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
89606 
89607 #define USB_GPTIMER0CTRL_GPTRST_MASK             (0x40000000U)
89608 #define USB_GPTIMER0CTRL_GPTRST_SHIFT            (30U)
89609 /*! GPTRST - GPTRST
89610  *  0b0..No action
89611  *  0b1..Load counter value from GPTLD bits in n_GPTIMER0LD
89612  */
89613 #define USB_GPTIMER0CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
89614 
89615 #define USB_GPTIMER0CTRL_GPTRUN_MASK             (0x80000000U)
89616 #define USB_GPTIMER0CTRL_GPTRUN_SHIFT            (31U)
89617 /*! GPTRUN - GPTRUN
89618  *  0b0..Stop counting
89619  *  0b1..Run
89620  */
89621 #define USB_GPTIMER0CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
89622 /*! @} */
89623 
89624 /*! @name GPTIMER1LD - General Purpose Timer #1 Load */
89625 /*! @{ */
89626 
89627 #define USB_GPTIMER1LD_GPTLD_MASK                (0xFFFFFFU)
89628 #define USB_GPTIMER1LD_GPTLD_SHIFT               (0U)
89629 /*! GPTLD - GPTLD */
89630 #define USB_GPTIMER1LD_GPTLD(x)                  (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
89631 /*! @} */
89632 
89633 /*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */
89634 /*! @{ */
89635 
89636 #define USB_GPTIMER1CTRL_GPTCNT_MASK             (0xFFFFFFU)
89637 #define USB_GPTIMER1CTRL_GPTCNT_SHIFT            (0U)
89638 /*! GPTCNT - GPTCNT */
89639 #define USB_GPTIMER1CTRL_GPTCNT(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
89640 
89641 #define USB_GPTIMER1CTRL_GPTMODE_MASK            (0x1000000U)
89642 #define USB_GPTIMER1CTRL_GPTMODE_SHIFT           (24U)
89643 /*! GPTMODE - GPTMODE
89644  *  0b0..One Shot Mode
89645  *  0b1..Repeat Mode
89646  */
89647 #define USB_GPTIMER1CTRL_GPTMODE(x)              (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
89648 
89649 #define USB_GPTIMER1CTRL_GPTRST_MASK             (0x40000000U)
89650 #define USB_GPTIMER1CTRL_GPTRST_SHIFT            (30U)
89651 /*! GPTRST - GPTRST
89652  *  0b0..No action
89653  *  0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD
89654  */
89655 #define USB_GPTIMER1CTRL_GPTRST(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
89656 
89657 #define USB_GPTIMER1CTRL_GPTRUN_MASK             (0x80000000U)
89658 #define USB_GPTIMER1CTRL_GPTRUN_SHIFT            (31U)
89659 /*! GPTRUN - GPTRUN
89660  *  0b0..Stop counting
89661  *  0b1..Run
89662  */
89663 #define USB_GPTIMER1CTRL_GPTRUN(x)               (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
89664 /*! @} */
89665 
89666 /*! @name SBUSCFG - System Bus Config */
89667 /*! @{ */
89668 
89669 #define USB_SBUSCFG_AHBBRST_MASK                 (0x7U)
89670 #define USB_SBUSCFG_AHBBRST_SHIFT                (0U)
89671 /*! AHBBRST - AHBBRST
89672  *  0b000..Incremental burst of unspecified length only
89673  *  0b001..INCR4 burst, then single transfer
89674  *  0b010..INCR8 burst, INCR4 burst, then single transfer
89675  *  0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer
89676  *  0b100..Reserved, don't use
89677  *  0b101..INCR4 burst, then incremental burst of unspecified length
89678  *  0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length
89679  *  0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length
89680  */
89681 #define USB_SBUSCFG_AHBBRST(x)                   (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
89682 /*! @} */
89683 
89684 /*! @name CAPLENGTH - Capability Registers Length */
89685 /*! @{ */
89686 
89687 #define USB_CAPLENGTH_CAPLENGTH_MASK             (0xFFU)
89688 #define USB_CAPLENGTH_CAPLENGTH_SHIFT            (0U)
89689 /*! CAPLENGTH - CAPLENGTH */
89690 #define USB_CAPLENGTH_CAPLENGTH(x)               (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
89691 /*! @} */
89692 
89693 /*! @name HCIVERSION - Host Controller Interface Version */
89694 /*! @{ */
89695 
89696 #define USB_HCIVERSION_HCIVERSION_MASK           (0xFFFFU)
89697 #define USB_HCIVERSION_HCIVERSION_SHIFT          (0U)
89698 /*! HCIVERSION - HCIVERSION */
89699 #define USB_HCIVERSION_HCIVERSION(x)             (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
89700 /*! @} */
89701 
89702 /*! @name HCSPARAMS - Host Controller Structural Parameters */
89703 /*! @{ */
89704 
89705 #define USB_HCSPARAMS_N_PORTS_MASK               (0xFU)
89706 #define USB_HCSPARAMS_N_PORTS_SHIFT              (0U)
89707 /*! N_PORTS - N_PORTS */
89708 #define USB_HCSPARAMS_N_PORTS(x)                 (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
89709 
89710 #define USB_HCSPARAMS_PPC_MASK                   (0x10U)
89711 #define USB_HCSPARAMS_PPC_SHIFT                  (4U)
89712 /*! PPC - PPC */
89713 #define USB_HCSPARAMS_PPC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
89714 
89715 #define USB_HCSPARAMS_N_PCC_MASK                 (0xF00U)
89716 #define USB_HCSPARAMS_N_PCC_SHIFT                (8U)
89717 /*! N_PCC - N_PCC */
89718 #define USB_HCSPARAMS_N_PCC(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
89719 
89720 #define USB_HCSPARAMS_N_CC_MASK                  (0xF000U)
89721 #define USB_HCSPARAMS_N_CC_SHIFT                 (12U)
89722 /*! N_CC - N_CC
89723  *  0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported.
89724  *  0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported.
89725  */
89726 #define USB_HCSPARAMS_N_CC(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
89727 
89728 #define USB_HCSPARAMS_PI_MASK                    (0x10000U)
89729 #define USB_HCSPARAMS_PI_SHIFT                   (16U)
89730 /*! PI - PI */
89731 #define USB_HCSPARAMS_PI(x)                      (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
89732 
89733 #define USB_HCSPARAMS_N_PTT_MASK                 (0xF00000U)
89734 #define USB_HCSPARAMS_N_PTT_SHIFT                (20U)
89735 /*! N_PTT - N_PTT */
89736 #define USB_HCSPARAMS_N_PTT(x)                   (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
89737 
89738 #define USB_HCSPARAMS_N_TT_MASK                  (0xF000000U)
89739 #define USB_HCSPARAMS_N_TT_SHIFT                 (24U)
89740 /*! N_TT - N_TT */
89741 #define USB_HCSPARAMS_N_TT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
89742 /*! @} */
89743 
89744 /*! @name HCCPARAMS - Host Controller Capability Parameters */
89745 /*! @{ */
89746 
89747 #define USB_HCCPARAMS_ADC_MASK                   (0x1U)
89748 #define USB_HCCPARAMS_ADC_SHIFT                  (0U)
89749 /*! ADC - ADC */
89750 #define USB_HCCPARAMS_ADC(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
89751 
89752 #define USB_HCCPARAMS_PFL_MASK                   (0x2U)
89753 #define USB_HCCPARAMS_PFL_SHIFT                  (1U)
89754 /*! PFL - PFL */
89755 #define USB_HCCPARAMS_PFL(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
89756 
89757 #define USB_HCCPARAMS_ASP_MASK                   (0x4U)
89758 #define USB_HCCPARAMS_ASP_SHIFT                  (2U)
89759 /*! ASP - ASP */
89760 #define USB_HCCPARAMS_ASP(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
89761 
89762 #define USB_HCCPARAMS_IST_MASK                   (0xF0U)
89763 #define USB_HCCPARAMS_IST_SHIFT                  (4U)
89764 /*! IST - IST */
89765 #define USB_HCCPARAMS_IST(x)                     (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
89766 
89767 #define USB_HCCPARAMS_EECP_MASK                  (0xFF00U)
89768 #define USB_HCCPARAMS_EECP_SHIFT                 (8U)
89769 /*! EECP - EECP */
89770 #define USB_HCCPARAMS_EECP(x)                    (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
89771 /*! @} */
89772 
89773 /*! @name DCIVERSION - Device Controller Interface Version */
89774 /*! @{ */
89775 
89776 #define USB_DCIVERSION_DCIVERSION_MASK           (0xFFFFU)
89777 #define USB_DCIVERSION_DCIVERSION_SHIFT          (0U)
89778 /*! DCIVERSION - DCIVERSION */
89779 #define USB_DCIVERSION_DCIVERSION(x)             (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
89780 /*! @} */
89781 
89782 /*! @name DCCPARAMS - Device Controller Capability Parameters */
89783 /*! @{ */
89784 
89785 #define USB_DCCPARAMS_DEN_MASK                   (0x1FU)
89786 #define USB_DCCPARAMS_DEN_SHIFT                  (0U)
89787 /*! DEN - DEN */
89788 #define USB_DCCPARAMS_DEN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
89789 
89790 #define USB_DCCPARAMS_DC_MASK                    (0x80U)
89791 #define USB_DCCPARAMS_DC_SHIFT                   (7U)
89792 /*! DC - DC */
89793 #define USB_DCCPARAMS_DC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
89794 
89795 #define USB_DCCPARAMS_HC_MASK                    (0x100U)
89796 #define USB_DCCPARAMS_HC_SHIFT                   (8U)
89797 /*! HC - HC */
89798 #define USB_DCCPARAMS_HC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
89799 /*! @} */
89800 
89801 /*! @name USBCMD - USB Command Register */
89802 /*! @{ */
89803 
89804 #define USB_USBCMD_RS_MASK                       (0x1U)
89805 #define USB_USBCMD_RS_SHIFT                      (0U)
89806 /*! RS - RS */
89807 #define USB_USBCMD_RS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
89808 
89809 #define USB_USBCMD_RST_MASK                      (0x2U)
89810 #define USB_USBCMD_RST_SHIFT                     (1U)
89811 /*! RST - RST */
89812 #define USB_USBCMD_RST(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
89813 
89814 #define USB_USBCMD_FS_1_MASK                     (0xCU)
89815 #define USB_USBCMD_FS_1_SHIFT                    (2U)
89816 /*! FS_1 - FS_1 */
89817 #define USB_USBCMD_FS_1(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
89818 
89819 #define USB_USBCMD_PSE_MASK                      (0x10U)
89820 #define USB_USBCMD_PSE_SHIFT                     (4U)
89821 /*! PSE - PSE
89822  *  0b0..Do not process the Periodic Schedule
89823  *  0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule.
89824  */
89825 #define USB_USBCMD_PSE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
89826 
89827 #define USB_USBCMD_ASE_MASK                      (0x20U)
89828 #define USB_USBCMD_ASE_SHIFT                     (5U)
89829 /*! ASE - ASE
89830  *  0b0..Do not process the Asynchronous Schedule.
89831  *  0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
89832  */
89833 #define USB_USBCMD_ASE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
89834 
89835 #define USB_USBCMD_IAA_MASK                      (0x40U)
89836 #define USB_USBCMD_IAA_SHIFT                     (6U)
89837 /*! IAA - IAA */
89838 #define USB_USBCMD_IAA(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
89839 
89840 #define USB_USBCMD_ASP_MASK                      (0x300U)
89841 #define USB_USBCMD_ASP_SHIFT                     (8U)
89842 /*! ASP - ASP */
89843 #define USB_USBCMD_ASP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
89844 
89845 #define USB_USBCMD_ASPE_MASK                     (0x800U)
89846 #define USB_USBCMD_ASPE_SHIFT                    (11U)
89847 /*! ASPE - ASPE */
89848 #define USB_USBCMD_ASPE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
89849 
89850 #define USB_USBCMD_SUTW_MASK                     (0x2000U)
89851 #define USB_USBCMD_SUTW_SHIFT                    (13U)
89852 /*! SUTW - SUTW */
89853 #define USB_USBCMD_SUTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
89854 
89855 #define USB_USBCMD_ATDTW_MASK                    (0x4000U)
89856 #define USB_USBCMD_ATDTW_SHIFT                   (14U)
89857 /*! ATDTW - ATDTW */
89858 #define USB_USBCMD_ATDTW(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
89859 
89860 #define USB_USBCMD_FS_2_MASK                     (0x8000U)
89861 #define USB_USBCMD_FS_2_SHIFT                    (15U)
89862 /*! FS_2 - FS_2 */
89863 #define USB_USBCMD_FS_2(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
89864 
89865 #define USB_USBCMD_ITC_MASK                      (0xFF0000U)
89866 #define USB_USBCMD_ITC_SHIFT                     (16U)
89867 /*! ITC - ITC
89868  *  0b00000000..Immediate (no threshold)
89869  *  0b00000001..1 micro-frame
89870  *  0b00000010..2 micro-frames
89871  *  0b00000100..4 micro-frames
89872  *  0b00001000..8 micro-frames
89873  *  0b00010000..16 micro-frames
89874  *  0b00100000..32 micro-frames
89875  *  0b01000000..64 micro-frames
89876  */
89877 #define USB_USBCMD_ITC(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
89878 /*! @} */
89879 
89880 /*! @name USBSTS - USB Status Register */
89881 /*! @{ */
89882 
89883 #define USB_USBSTS_UI_MASK                       (0x1U)
89884 #define USB_USBSTS_UI_SHIFT                      (0U)
89885 /*! UI - UI */
89886 #define USB_USBSTS_UI(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
89887 
89888 #define USB_USBSTS_UEI_MASK                      (0x2U)
89889 #define USB_USBSTS_UEI_SHIFT                     (1U)
89890 /*! UEI - UEI */
89891 #define USB_USBSTS_UEI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
89892 
89893 #define USB_USBSTS_PCI_MASK                      (0x4U)
89894 #define USB_USBSTS_PCI_SHIFT                     (2U)
89895 /*! PCI - PCI */
89896 #define USB_USBSTS_PCI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
89897 
89898 #define USB_USBSTS_FRI_MASK                      (0x8U)
89899 #define USB_USBSTS_FRI_SHIFT                     (3U)
89900 /*! FRI - FRI */
89901 #define USB_USBSTS_FRI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
89902 
89903 #define USB_USBSTS_SEI_MASK                      (0x10U)
89904 #define USB_USBSTS_SEI_SHIFT                     (4U)
89905 /*! SEI - SEI */
89906 #define USB_USBSTS_SEI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
89907 
89908 #define USB_USBSTS_AAI_MASK                      (0x20U)
89909 #define USB_USBSTS_AAI_SHIFT                     (5U)
89910 /*! AAI - AAI */
89911 #define USB_USBSTS_AAI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
89912 
89913 #define USB_USBSTS_URI_MASK                      (0x40U)
89914 #define USB_USBSTS_URI_SHIFT                     (6U)
89915 /*! URI - URI */
89916 #define USB_USBSTS_URI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
89917 
89918 #define USB_USBSTS_SRI_MASK                      (0x80U)
89919 #define USB_USBSTS_SRI_SHIFT                     (7U)
89920 /*! SRI - SRI */
89921 #define USB_USBSTS_SRI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
89922 
89923 #define USB_USBSTS_SLI_MASK                      (0x100U)
89924 #define USB_USBSTS_SLI_SHIFT                     (8U)
89925 /*! SLI - SLI */
89926 #define USB_USBSTS_SLI(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
89927 
89928 #define USB_USBSTS_ULPII_MASK                    (0x400U)
89929 #define USB_USBSTS_ULPII_SHIFT                   (10U)
89930 /*! ULPII - ULPII */
89931 #define USB_USBSTS_ULPII(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
89932 
89933 #define USB_USBSTS_HCH_MASK                      (0x1000U)
89934 #define USB_USBSTS_HCH_SHIFT                     (12U)
89935 /*! HCH - HCH */
89936 #define USB_USBSTS_HCH(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
89937 
89938 #define USB_USBSTS_RCL_MASK                      (0x2000U)
89939 #define USB_USBSTS_RCL_SHIFT                     (13U)
89940 /*! RCL - RCL */
89941 #define USB_USBSTS_RCL(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
89942 
89943 #define USB_USBSTS_PS_MASK                       (0x4000U)
89944 #define USB_USBSTS_PS_SHIFT                      (14U)
89945 /*! PS - PS */
89946 #define USB_USBSTS_PS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
89947 
89948 #define USB_USBSTS_AS_MASK                       (0x8000U)
89949 #define USB_USBSTS_AS_SHIFT                      (15U)
89950 /*! AS - AS */
89951 #define USB_USBSTS_AS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
89952 
89953 #define USB_USBSTS_NAKI_MASK                     (0x10000U)
89954 #define USB_USBSTS_NAKI_SHIFT                    (16U)
89955 /*! NAKI - NAKI */
89956 #define USB_USBSTS_NAKI(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
89957 
89958 #define USB_USBSTS_TI0_MASK                      (0x1000000U)
89959 #define USB_USBSTS_TI0_SHIFT                     (24U)
89960 /*! TI0 - TI0 */
89961 #define USB_USBSTS_TI0(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
89962 
89963 #define USB_USBSTS_TI1_MASK                      (0x2000000U)
89964 #define USB_USBSTS_TI1_SHIFT                     (25U)
89965 /*! TI1 - TI1 */
89966 #define USB_USBSTS_TI1(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
89967 /*! @} */
89968 
89969 /*! @name USBINTR - Interrupt Enable Register */
89970 /*! @{ */
89971 
89972 #define USB_USBINTR_UE_MASK                      (0x1U)
89973 #define USB_USBINTR_UE_SHIFT                     (0U)
89974 /*! UE - UE */
89975 #define USB_USBINTR_UE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
89976 
89977 #define USB_USBINTR_UEE_MASK                     (0x2U)
89978 #define USB_USBINTR_UEE_SHIFT                    (1U)
89979 /*! UEE - UEE */
89980 #define USB_USBINTR_UEE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
89981 
89982 #define USB_USBINTR_PCE_MASK                     (0x4U)
89983 #define USB_USBINTR_PCE_SHIFT                    (2U)
89984 /*! PCE - PCE */
89985 #define USB_USBINTR_PCE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
89986 
89987 #define USB_USBINTR_FRE_MASK                     (0x8U)
89988 #define USB_USBINTR_FRE_SHIFT                    (3U)
89989 /*! FRE - FRE */
89990 #define USB_USBINTR_FRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
89991 
89992 #define USB_USBINTR_SEE_MASK                     (0x10U)
89993 #define USB_USBINTR_SEE_SHIFT                    (4U)
89994 /*! SEE - SEE */
89995 #define USB_USBINTR_SEE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
89996 
89997 #define USB_USBINTR_AAE_MASK                     (0x20U)
89998 #define USB_USBINTR_AAE_SHIFT                    (5U)
89999 /*! AAE - AAE */
90000 #define USB_USBINTR_AAE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
90001 
90002 #define USB_USBINTR_URE_MASK                     (0x40U)
90003 #define USB_USBINTR_URE_SHIFT                    (6U)
90004 /*! URE - URE */
90005 #define USB_USBINTR_URE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
90006 
90007 #define USB_USBINTR_SRE_MASK                     (0x80U)
90008 #define USB_USBINTR_SRE_SHIFT                    (7U)
90009 /*! SRE - SRE */
90010 #define USB_USBINTR_SRE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
90011 
90012 #define USB_USBINTR_SLE_MASK                     (0x100U)
90013 #define USB_USBINTR_SLE_SHIFT                    (8U)
90014 /*! SLE - SLE */
90015 #define USB_USBINTR_SLE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
90016 
90017 #define USB_USBINTR_ULPIE_MASK                   (0x400U)
90018 #define USB_USBINTR_ULPIE_SHIFT                  (10U)
90019 /*! ULPIE - ULPIE */
90020 #define USB_USBINTR_ULPIE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
90021 
90022 #define USB_USBINTR_NAKE_MASK                    (0x10000U)
90023 #define USB_USBINTR_NAKE_SHIFT                   (16U)
90024 /*! NAKE - NAKE */
90025 #define USB_USBINTR_NAKE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
90026 
90027 #define USB_USBINTR_UAIE_MASK                    (0x40000U)
90028 #define USB_USBINTR_UAIE_SHIFT                   (18U)
90029 /*! UAIE - UAIE */
90030 #define USB_USBINTR_UAIE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
90031 
90032 #define USB_USBINTR_UPIE_MASK                    (0x80000U)
90033 #define USB_USBINTR_UPIE_SHIFT                   (19U)
90034 /*! UPIE - UPIE */
90035 #define USB_USBINTR_UPIE(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
90036 
90037 #define USB_USBINTR_TIE0_MASK                    (0x1000000U)
90038 #define USB_USBINTR_TIE0_SHIFT                   (24U)
90039 /*! TIE0 - TIE0 */
90040 #define USB_USBINTR_TIE0(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
90041 
90042 #define USB_USBINTR_TIE1_MASK                    (0x2000000U)
90043 #define USB_USBINTR_TIE1_SHIFT                   (25U)
90044 /*! TIE1 - TIE1 */
90045 #define USB_USBINTR_TIE1(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
90046 /*! @} */
90047 
90048 /*! @name FRINDEX - USB Frame Index */
90049 /*! @{ */
90050 
90051 #define USB_FRINDEX_FRINDEX_MASK                 (0x3FFFU)
90052 #define USB_FRINDEX_FRINDEX_SHIFT                (0U)
90053 /*! FRINDEX - FRINDEX
90054  *  0b00000000000000..(1024) 12
90055  *  0b00000000000001..(512) 11
90056  *  0b00000000000010..(256) 10
90057  *  0b00000000000011..(128) 9
90058  *  0b00000000000100..(64) 8
90059  *  0b00000000000101..(32) 7
90060  *  0b00000000000110..(16) 6
90061  *  0b00000000000111..(8) 5
90062  */
90063 #define USB_FRINDEX_FRINDEX(x)                   (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
90064 /*! @} */
90065 
90066 /*! @name DEVICEADDR - Device Address */
90067 /*! @{ */
90068 
90069 #define USB_DEVICEADDR_USBADRA_MASK              (0x1000000U)
90070 #define USB_DEVICEADDR_USBADRA_SHIFT             (24U)
90071 /*! USBADRA - USBADRA */
90072 #define USB_DEVICEADDR_USBADRA(x)                (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
90073 
90074 #define USB_DEVICEADDR_USBADR_MASK               (0xFE000000U)
90075 #define USB_DEVICEADDR_USBADR_SHIFT              (25U)
90076 /*! USBADR - USBADR */
90077 #define USB_DEVICEADDR_USBADR(x)                 (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
90078 /*! @} */
90079 
90080 /*! @name PERIODICLISTBASE - Frame List Base Address */
90081 /*! @{ */
90082 
90083 #define USB_PERIODICLISTBASE_BASEADR_MASK        (0xFFFFF000U)
90084 #define USB_PERIODICLISTBASE_BASEADR_SHIFT       (12U)
90085 /*! BASEADR - BASEADR */
90086 #define USB_PERIODICLISTBASE_BASEADR(x)          (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
90087 /*! @} */
90088 
90089 /*! @name ASYNCLISTADDR - Next Asynch. Address */
90090 /*! @{ */
90091 
90092 #define USB_ASYNCLISTADDR_ASYBASE_MASK           (0xFFFFFFE0U)
90093 #define USB_ASYNCLISTADDR_ASYBASE_SHIFT          (5U)
90094 /*! ASYBASE - ASYBASE */
90095 #define USB_ASYNCLISTADDR_ASYBASE(x)             (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
90096 /*! @} */
90097 
90098 /*! @name ENDPTLISTADDR - Endpoint List Address */
90099 /*! @{ */
90100 
90101 #define USB_ENDPTLISTADDR_EPBASE_MASK            (0xFFFFF800U)
90102 #define USB_ENDPTLISTADDR_EPBASE_SHIFT           (11U)
90103 /*! EPBASE - EPBASE */
90104 #define USB_ENDPTLISTADDR_EPBASE(x)              (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
90105 /*! @} */
90106 
90107 /*! @name BURSTSIZE - Programmable Burst Size */
90108 /*! @{ */
90109 
90110 #define USB_BURSTSIZE_RXPBURST_MASK              (0xFFU)
90111 #define USB_BURSTSIZE_RXPBURST_SHIFT             (0U)
90112 /*! RXPBURST - RXPBURST */
90113 #define USB_BURSTSIZE_RXPBURST(x)                (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
90114 
90115 #define USB_BURSTSIZE_TXPBURST_MASK              (0x1FF00U)
90116 #define USB_BURSTSIZE_TXPBURST_SHIFT             (8U)
90117 /*! TXPBURST - TXPBURST */
90118 #define USB_BURSTSIZE_TXPBURST(x)                (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
90119 /*! @} */
90120 
90121 /*! @name TXFILLTUNING - TX FIFO Fill Tuning */
90122 /*! @{ */
90123 
90124 #define USB_TXFILLTUNING_TXSCHOH_MASK            (0xFFU)
90125 #define USB_TXFILLTUNING_TXSCHOH_SHIFT           (0U)
90126 /*! TXSCHOH - TXSCHOH */
90127 #define USB_TXFILLTUNING_TXSCHOH(x)              (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
90128 
90129 #define USB_TXFILLTUNING_TXSCHHEALTH_MASK        (0x1F00U)
90130 #define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT       (8U)
90131 /*! TXSCHHEALTH - TXSCHHEALTH */
90132 #define USB_TXFILLTUNING_TXSCHHEALTH(x)          (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
90133 
90134 #define USB_TXFILLTUNING_TXFIFOTHRES_MASK        (0x3F0000U)
90135 #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT       (16U)
90136 /*! TXFIFOTHRES - TXFIFOTHRES */
90137 #define USB_TXFILLTUNING_TXFIFOTHRES(x)          (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
90138 /*! @} */
90139 
90140 /*! @name ENDPTNAK - Endpoint NAK */
90141 /*! @{ */
90142 
90143 #define USB_ENDPTNAK_EPRN_MASK                   (0xFFU)
90144 #define USB_ENDPTNAK_EPRN_SHIFT                  (0U)
90145 /*! EPRN - EPRN */
90146 #define USB_ENDPTNAK_EPRN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
90147 
90148 #define USB_ENDPTNAK_EPTN_MASK                   (0xFF0000U)
90149 #define USB_ENDPTNAK_EPTN_SHIFT                  (16U)
90150 /*! EPTN - EPTN */
90151 #define USB_ENDPTNAK_EPTN(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
90152 /*! @} */
90153 
90154 /*! @name ENDPTNAKEN - Endpoint NAK Enable */
90155 /*! @{ */
90156 
90157 #define USB_ENDPTNAKEN_EPRNE_MASK                (0xFFU)
90158 #define USB_ENDPTNAKEN_EPRNE_SHIFT               (0U)
90159 /*! EPRNE - EPRNE */
90160 #define USB_ENDPTNAKEN_EPRNE(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
90161 
90162 #define USB_ENDPTNAKEN_EPTNE_MASK                (0xFF0000U)
90163 #define USB_ENDPTNAKEN_EPTNE_SHIFT               (16U)
90164 /*! EPTNE - EPTNE */
90165 #define USB_ENDPTNAKEN_EPTNE(x)                  (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
90166 /*! @} */
90167 
90168 /*! @name CONFIGFLAG - Configure Flag Register */
90169 /*! @{ */
90170 
90171 #define USB_CONFIGFLAG_CF_MASK                   (0x1U)
90172 #define USB_CONFIGFLAG_CF_SHIFT                  (0U)
90173 /*! CF - CF
90174  *  0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller.
90175  *  0b1..Port routing control logic default-routes all ports to this host controller.
90176  */
90177 #define USB_CONFIGFLAG_CF(x)                     (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
90178 /*! @} */
90179 
90180 /*! @name PORTSC1 - Port Status & Control */
90181 /*! @{ */
90182 
90183 #define USB_PORTSC1_CCS_MASK                     (0x1U)
90184 #define USB_PORTSC1_CCS_SHIFT                    (0U)
90185 /*! CCS - CCS */
90186 #define USB_PORTSC1_CCS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
90187 
90188 #define USB_PORTSC1_CSC_MASK                     (0x2U)
90189 #define USB_PORTSC1_CSC_SHIFT                    (1U)
90190 /*! CSC - CSC */
90191 #define USB_PORTSC1_CSC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
90192 
90193 #define USB_PORTSC1_PE_MASK                      (0x4U)
90194 #define USB_PORTSC1_PE_SHIFT                     (2U)
90195 /*! PE - PE */
90196 #define USB_PORTSC1_PE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
90197 
90198 #define USB_PORTSC1_PEC_MASK                     (0x8U)
90199 #define USB_PORTSC1_PEC_SHIFT                    (3U)
90200 /*! PEC - PEC */
90201 #define USB_PORTSC1_PEC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
90202 
90203 #define USB_PORTSC1_OCA_MASK                     (0x10U)
90204 #define USB_PORTSC1_OCA_SHIFT                    (4U)
90205 /*! OCA - OCA
90206  *  0b1..This port currently has an over-current condition
90207  *  0b0..This port does not have an over-current condition.
90208  */
90209 #define USB_PORTSC1_OCA(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
90210 
90211 #define USB_PORTSC1_OCC_MASK                     (0x20U)
90212 #define USB_PORTSC1_OCC_SHIFT                    (5U)
90213 /*! OCC - OCC */
90214 #define USB_PORTSC1_OCC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
90215 
90216 #define USB_PORTSC1_FPR_MASK                     (0x40U)
90217 #define USB_PORTSC1_FPR_SHIFT                    (6U)
90218 /*! FPR - FPR */
90219 #define USB_PORTSC1_FPR(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
90220 
90221 #define USB_PORTSC1_SUSP_MASK                    (0x80U)
90222 #define USB_PORTSC1_SUSP_SHIFT                   (7U)
90223 /*! SUSP - SUSP */
90224 #define USB_PORTSC1_SUSP(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
90225 
90226 #define USB_PORTSC1_PR_MASK                      (0x100U)
90227 #define USB_PORTSC1_PR_SHIFT                     (8U)
90228 /*! PR - PR */
90229 #define USB_PORTSC1_PR(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
90230 
90231 #define USB_PORTSC1_HSP_MASK                     (0x200U)
90232 #define USB_PORTSC1_HSP_SHIFT                    (9U)
90233 /*! HSP - HSP */
90234 #define USB_PORTSC1_HSP(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
90235 
90236 #define USB_PORTSC1_LS_MASK                      (0xC00U)
90237 #define USB_PORTSC1_LS_SHIFT                     (10U)
90238 /*! LS - LS
90239  *  0b00..SE0
90240  *  0b10..J-state
90241  *  0b01..K-state
90242  *  0b11..Undefined
90243  */
90244 #define USB_PORTSC1_LS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
90245 
90246 #define USB_PORTSC1_PP_MASK                      (0x1000U)
90247 #define USB_PORTSC1_PP_SHIFT                     (12U)
90248 /*! PP - PP */
90249 #define USB_PORTSC1_PP(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
90250 
90251 #define USB_PORTSC1_PO_MASK                      (0x2000U)
90252 #define USB_PORTSC1_PO_SHIFT                     (13U)
90253 /*! PO - PO */
90254 #define USB_PORTSC1_PO(x)                        (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
90255 
90256 #define USB_PORTSC1_PIC_MASK                     (0xC000U)
90257 #define USB_PORTSC1_PIC_SHIFT                    (14U)
90258 /*! PIC - PIC
90259  *  0b00..Port indicators are off
90260  *  0b01..Amber
90261  *  0b10..Green
90262  *  0b11..Undefined
90263  */
90264 #define USB_PORTSC1_PIC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
90265 
90266 #define USB_PORTSC1_PTC_MASK                     (0xF0000U)
90267 #define USB_PORTSC1_PTC_SHIFT                    (16U)
90268 /*! PTC - PTC
90269  *  0b0000..TEST_MODE_DISABLE
90270  *  0b0001..J_STATE
90271  *  0b0010..K_STATE
90272  *  0b0011..SE0 (host) / NAK (device)
90273  *  0b0100..Packet
90274  *  0b0101..FORCE_ENABLE_HS
90275  *  0b0110..FORCE_ENABLE_FS
90276  *  0b0111..FORCE_ENABLE_LS
90277  *  0b1000-0b1111..Reserved
90278  */
90279 #define USB_PORTSC1_PTC(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
90280 
90281 #define USB_PORTSC1_WKCN_MASK                    (0x100000U)
90282 #define USB_PORTSC1_WKCN_SHIFT                   (20U)
90283 /*! WKCN - WKCN */
90284 #define USB_PORTSC1_WKCN(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
90285 
90286 #define USB_PORTSC1_WKDC_MASK                    (0x200000U)
90287 #define USB_PORTSC1_WKDC_SHIFT                   (21U)
90288 /*! WKDC - WKDC */
90289 #define USB_PORTSC1_WKDC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
90290 
90291 #define USB_PORTSC1_WKOC_MASK                    (0x400000U)
90292 #define USB_PORTSC1_WKOC_SHIFT                   (22U)
90293 /*! WKOC - WKOC */
90294 #define USB_PORTSC1_WKOC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
90295 
90296 #define USB_PORTSC1_PHCD_MASK                    (0x800000U)
90297 #define USB_PORTSC1_PHCD_SHIFT                   (23U)
90298 /*! PHCD - PHCD
90299  *  0b1..Disable PHY clock
90300  *  0b0..Enable PHY clock
90301  */
90302 #define USB_PORTSC1_PHCD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
90303 
90304 #define USB_PORTSC1_PFSC_MASK                    (0x1000000U)
90305 #define USB_PORTSC1_PFSC_SHIFT                   (24U)
90306 /*! PFSC - PFSC
90307  *  0b1..Forced to full speed
90308  *  0b0..Normal operation
90309  */
90310 #define USB_PORTSC1_PFSC(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
90311 
90312 #define USB_PORTSC1_PTS_2_MASK                   (0x2000000U)
90313 #define USB_PORTSC1_PTS_2_SHIFT                  (25U)
90314 /*! PTS_2 - PTS_2 */
90315 #define USB_PORTSC1_PTS_2(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
90316 
90317 #define USB_PORTSC1_PSPD_MASK                    (0xC000000U)
90318 #define USB_PORTSC1_PSPD_SHIFT                   (26U)
90319 /*! PSPD - PSPD
90320  *  0b00..Full Speed
90321  *  0b01..Low Speed
90322  *  0b10..High Speed
90323  *  0b11..Undefined
90324  */
90325 #define USB_PORTSC1_PSPD(x)                      (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
90326 
90327 #define USB_PORTSC1_PTW_MASK                     (0x10000000U)
90328 #define USB_PORTSC1_PTW_SHIFT                    (28U)
90329 /*! PTW - PTW
90330  *  0b0..Select the 8-bit UTMI interface [60MHz]
90331  *  0b1..Select the 16-bit UTMI interface [30MHz]
90332  */
90333 #define USB_PORTSC1_PTW(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
90334 
90335 #define USB_PORTSC1_STS_MASK                     (0x20000000U)
90336 #define USB_PORTSC1_STS_SHIFT                    (29U)
90337 /*! STS - STS */
90338 #define USB_PORTSC1_STS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
90339 
90340 #define USB_PORTSC1_PTS_1_MASK                   (0xC0000000U)
90341 #define USB_PORTSC1_PTS_1_SHIFT                  (30U)
90342 /*! PTS_1 - PTS_1 */
90343 #define USB_PORTSC1_PTS_1(x)                     (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
90344 /*! @} */
90345 
90346 /*! @name OTGSC - On-The-Go Status & control */
90347 /*! @{ */
90348 
90349 #define USB_OTGSC_VD_MASK                        (0x1U)
90350 #define USB_OTGSC_VD_SHIFT                       (0U)
90351 /*! VD - VD */
90352 #define USB_OTGSC_VD(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
90353 
90354 #define USB_OTGSC_VC_MASK                        (0x2U)
90355 #define USB_OTGSC_VC_SHIFT                       (1U)
90356 /*! VC - VC */
90357 #define USB_OTGSC_VC(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
90358 
90359 #define USB_OTGSC_OT_MASK                        (0x8U)
90360 #define USB_OTGSC_OT_SHIFT                       (3U)
90361 /*! OT - OT */
90362 #define USB_OTGSC_OT(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
90363 
90364 #define USB_OTGSC_DP_MASK                        (0x10U)
90365 #define USB_OTGSC_DP_SHIFT                       (4U)
90366 /*! DP - DP */
90367 #define USB_OTGSC_DP(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
90368 
90369 #define USB_OTGSC_IDPU_MASK                      (0x20U)
90370 #define USB_OTGSC_IDPU_SHIFT                     (5U)
90371 /*! IDPU - IDPU */
90372 #define USB_OTGSC_IDPU(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
90373 
90374 #define USB_OTGSC_ID_MASK                        (0x100U)
90375 #define USB_OTGSC_ID_SHIFT                       (8U)
90376 /*! ID - ID */
90377 #define USB_OTGSC_ID(x)                          (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
90378 
90379 #define USB_OTGSC_AVV_MASK                       (0x200U)
90380 #define USB_OTGSC_AVV_SHIFT                      (9U)
90381 /*! AVV - AVV */
90382 #define USB_OTGSC_AVV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
90383 
90384 #define USB_OTGSC_ASV_MASK                       (0x400U)
90385 #define USB_OTGSC_ASV_SHIFT                      (10U)
90386 /*! ASV - ASV */
90387 #define USB_OTGSC_ASV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
90388 
90389 #define USB_OTGSC_BSV_MASK                       (0x800U)
90390 #define USB_OTGSC_BSV_SHIFT                      (11U)
90391 /*! BSV - BSV */
90392 #define USB_OTGSC_BSV(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
90393 
90394 #define USB_OTGSC_BSE_MASK                       (0x1000U)
90395 #define USB_OTGSC_BSE_SHIFT                      (12U)
90396 /*! BSE - BSE */
90397 #define USB_OTGSC_BSE(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
90398 
90399 #define USB_OTGSC_TOG_1MS_MASK                   (0x2000U)
90400 #define USB_OTGSC_TOG_1MS_SHIFT                  (13U)
90401 /*! TOG_1MS - TOG_1MS */
90402 #define USB_OTGSC_TOG_1MS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
90403 
90404 #define USB_OTGSC_DPS_MASK                       (0x4000U)
90405 #define USB_OTGSC_DPS_SHIFT                      (14U)
90406 /*! DPS - DPS */
90407 #define USB_OTGSC_DPS(x)                         (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
90408 
90409 #define USB_OTGSC_IDIS_MASK                      (0x10000U)
90410 #define USB_OTGSC_IDIS_SHIFT                     (16U)
90411 /*! IDIS - IDIS */
90412 #define USB_OTGSC_IDIS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
90413 
90414 #define USB_OTGSC_AVVIS_MASK                     (0x20000U)
90415 #define USB_OTGSC_AVVIS_SHIFT                    (17U)
90416 /*! AVVIS - AVVIS */
90417 #define USB_OTGSC_AVVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
90418 
90419 #define USB_OTGSC_ASVIS_MASK                     (0x40000U)
90420 #define USB_OTGSC_ASVIS_SHIFT                    (18U)
90421 /*! ASVIS - ASVIS */
90422 #define USB_OTGSC_ASVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
90423 
90424 #define USB_OTGSC_BSVIS_MASK                     (0x80000U)
90425 #define USB_OTGSC_BSVIS_SHIFT                    (19U)
90426 /*! BSVIS - BSVIS */
90427 #define USB_OTGSC_BSVIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
90428 
90429 #define USB_OTGSC_BSEIS_MASK                     (0x100000U)
90430 #define USB_OTGSC_BSEIS_SHIFT                    (20U)
90431 /*! BSEIS - BSEIS */
90432 #define USB_OTGSC_BSEIS(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
90433 
90434 #define USB_OTGSC_STATUS_1MS_MASK                (0x200000U)
90435 #define USB_OTGSC_STATUS_1MS_SHIFT               (21U)
90436 /*! STATUS_1MS - STATUS_1MS */
90437 #define USB_OTGSC_STATUS_1MS(x)                  (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
90438 
90439 #define USB_OTGSC_DPIS_MASK                      (0x400000U)
90440 #define USB_OTGSC_DPIS_SHIFT                     (22U)
90441 /*! DPIS - DPIS */
90442 #define USB_OTGSC_DPIS(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
90443 
90444 #define USB_OTGSC_IDIE_MASK                      (0x1000000U)
90445 #define USB_OTGSC_IDIE_SHIFT                     (24U)
90446 /*! IDIE - IDIE */
90447 #define USB_OTGSC_IDIE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
90448 
90449 #define USB_OTGSC_AVVIE_MASK                     (0x2000000U)
90450 #define USB_OTGSC_AVVIE_SHIFT                    (25U)
90451 /*! AVVIE - AVVIE */
90452 #define USB_OTGSC_AVVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
90453 
90454 #define USB_OTGSC_ASVIE_MASK                     (0x4000000U)
90455 #define USB_OTGSC_ASVIE_SHIFT                    (26U)
90456 /*! ASVIE - ASVIE */
90457 #define USB_OTGSC_ASVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
90458 
90459 #define USB_OTGSC_BSVIE_MASK                     (0x8000000U)
90460 #define USB_OTGSC_BSVIE_SHIFT                    (27U)
90461 /*! BSVIE - BSVIE */
90462 #define USB_OTGSC_BSVIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
90463 
90464 #define USB_OTGSC_BSEIE_MASK                     (0x10000000U)
90465 #define USB_OTGSC_BSEIE_SHIFT                    (28U)
90466 /*! BSEIE - BSEIE */
90467 #define USB_OTGSC_BSEIE(x)                       (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
90468 
90469 #define USB_OTGSC_EN_1MS_MASK                    (0x20000000U)
90470 #define USB_OTGSC_EN_1MS_SHIFT                   (29U)
90471 /*! EN_1MS - EN_1MS */
90472 #define USB_OTGSC_EN_1MS(x)                      (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
90473 
90474 #define USB_OTGSC_DPIE_MASK                      (0x40000000U)
90475 #define USB_OTGSC_DPIE_SHIFT                     (30U)
90476 /*! DPIE - DPIE */
90477 #define USB_OTGSC_DPIE(x)                        (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
90478 /*! @} */
90479 
90480 /*! @name USBMODE - USB Device Mode */
90481 /*! @{ */
90482 
90483 #define USB_USBMODE_CM_MASK                      (0x3U)
90484 #define USB_USBMODE_CM_SHIFT                     (0U)
90485 /*! CM - CM
90486  *  0b00..Idle [Default for combination host/device]
90487  *  0b01..Reserved
90488  *  0b10..Device Controller [Default for device only controller]
90489  *  0b11..Host Controller [Default for host only controller]
90490  */
90491 #define USB_USBMODE_CM(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
90492 
90493 #define USB_USBMODE_ES_MASK                      (0x4U)
90494 #define USB_USBMODE_ES_SHIFT                     (2U)
90495 /*! ES - ES
90496  *  0b0..Little Endian [Default]
90497  *  0b1..Big Endian
90498  */
90499 #define USB_USBMODE_ES(x)                        (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
90500 
90501 #define USB_USBMODE_SLOM_MASK                    (0x8U)
90502 #define USB_USBMODE_SLOM_SHIFT                   (3U)
90503 /*! SLOM - SLOM
90504  *  0b0..Setup Lockouts On (default);
90505  *  0b1..Setup Lockouts Off
90506  */
90507 #define USB_USBMODE_SLOM(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
90508 
90509 #define USB_USBMODE_SDIS_MASK                    (0x10U)
90510 #define USB_USBMODE_SDIS_SHIFT                   (4U)
90511 /*! SDIS - SDIS */
90512 #define USB_USBMODE_SDIS(x)                      (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
90513 /*! @} */
90514 
90515 /*! @name ENDPTSETUPSTAT - Endpoint Setup Status */
90516 /*! @{ */
90517 
90518 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK   (0xFFFFU)
90519 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT  (0U)
90520 /*! ENDPTSETUPSTAT - ENDPTSETUPSTAT */
90521 #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
90522 /*! @} */
90523 
90524 /*! @name ENDPTPRIME - Endpoint Prime */
90525 /*! @{ */
90526 
90527 #define USB_ENDPTPRIME_PERB_MASK                 (0xFFU)
90528 #define USB_ENDPTPRIME_PERB_SHIFT                (0U)
90529 /*! PERB - PERB */
90530 #define USB_ENDPTPRIME_PERB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
90531 
90532 #define USB_ENDPTPRIME_PETB_MASK                 (0xFF0000U)
90533 #define USB_ENDPTPRIME_PETB_SHIFT                (16U)
90534 /*! PETB - PETB */
90535 #define USB_ENDPTPRIME_PETB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
90536 /*! @} */
90537 
90538 /*! @name ENDPTFLUSH - Endpoint Flush */
90539 /*! @{ */
90540 
90541 #define USB_ENDPTFLUSH_FERB_MASK                 (0xFFU)
90542 #define USB_ENDPTFLUSH_FERB_SHIFT                (0U)
90543 /*! FERB - FERB */
90544 #define USB_ENDPTFLUSH_FERB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
90545 
90546 #define USB_ENDPTFLUSH_FETB_MASK                 (0xFF0000U)
90547 #define USB_ENDPTFLUSH_FETB_SHIFT                (16U)
90548 /*! FETB - FETB */
90549 #define USB_ENDPTFLUSH_FETB(x)                   (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
90550 /*! @} */
90551 
90552 /*! @name ENDPTSTAT - Endpoint Status */
90553 /*! @{ */
90554 
90555 #define USB_ENDPTSTAT_ERBR_MASK                  (0xFFU)
90556 #define USB_ENDPTSTAT_ERBR_SHIFT                 (0U)
90557 /*! ERBR - ERBR */
90558 #define USB_ENDPTSTAT_ERBR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
90559 
90560 #define USB_ENDPTSTAT_ETBR_MASK                  (0xFF0000U)
90561 #define USB_ENDPTSTAT_ETBR_SHIFT                 (16U)
90562 /*! ETBR - ETBR */
90563 #define USB_ENDPTSTAT_ETBR(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
90564 /*! @} */
90565 
90566 /*! @name ENDPTCOMPLETE - Endpoint Complete */
90567 /*! @{ */
90568 
90569 #define USB_ENDPTCOMPLETE_ERCE_MASK              (0xFFU)
90570 #define USB_ENDPTCOMPLETE_ERCE_SHIFT             (0U)
90571 /*! ERCE - ERCE */
90572 #define USB_ENDPTCOMPLETE_ERCE(x)                (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
90573 
90574 #define USB_ENDPTCOMPLETE_ETCE_MASK              (0xFF0000U)
90575 #define USB_ENDPTCOMPLETE_ETCE_SHIFT             (16U)
90576 /*! ETCE - ETCE */
90577 #define USB_ENDPTCOMPLETE_ETCE(x)                (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
90578 /*! @} */
90579 
90580 /*! @name ENDPTCTRL0 - Endpoint Control0 */
90581 /*! @{ */
90582 
90583 #define USB_ENDPTCTRL0_RXS_MASK                  (0x1U)
90584 #define USB_ENDPTCTRL0_RXS_SHIFT                 (0U)
90585 /*! RXS - RXS */
90586 #define USB_ENDPTCTRL0_RXS(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)
90587 
90588 #define USB_ENDPTCTRL0_RXT_MASK                  (0xCU)
90589 #define USB_ENDPTCTRL0_RXT_SHIFT                 (2U)
90590 /*! RXT - RXT */
90591 #define USB_ENDPTCTRL0_RXT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)
90592 
90593 #define USB_ENDPTCTRL0_RXE_MASK                  (0x80U)
90594 #define USB_ENDPTCTRL0_RXE_SHIFT                 (7U)
90595 /*! RXE - RXE */
90596 #define USB_ENDPTCTRL0_RXE(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)
90597 
90598 #define USB_ENDPTCTRL0_TXS_MASK                  (0x10000U)
90599 #define USB_ENDPTCTRL0_TXS_SHIFT                 (16U)
90600 /*! TXS - TXS */
90601 #define USB_ENDPTCTRL0_TXS(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)
90602 
90603 #define USB_ENDPTCTRL0_TXT_MASK                  (0xC0000U)
90604 #define USB_ENDPTCTRL0_TXT_SHIFT                 (18U)
90605 /*! TXT - TXT */
90606 #define USB_ENDPTCTRL0_TXT(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)
90607 
90608 #define USB_ENDPTCTRL0_TXE_MASK                  (0x800000U)
90609 #define USB_ENDPTCTRL0_TXE_SHIFT                 (23U)
90610 /*! TXE - TXE */
90611 #define USB_ENDPTCTRL0_TXE(x)                    (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
90612 /*! @} */
90613 
90614 /*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */
90615 /*! @{ */
90616 
90617 #define USB_ENDPTCTRL_RXS_MASK                   (0x1U)
90618 #define USB_ENDPTCTRL_RXS_SHIFT                  (0U)
90619 /*! RXS - RXS */
90620 #define USB_ENDPTCTRL_RXS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
90621 
90622 #define USB_ENDPTCTRL_RXD_MASK                   (0x2U)
90623 #define USB_ENDPTCTRL_RXD_SHIFT                  (1U)
90624 /*! RXD - RXD */
90625 #define USB_ENDPTCTRL_RXD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
90626 
90627 #define USB_ENDPTCTRL_RXT_MASK                   (0xCU)
90628 #define USB_ENDPTCTRL_RXT_SHIFT                  (2U)
90629 /*! RXT - RXT */
90630 #define USB_ENDPTCTRL_RXT(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
90631 
90632 #define USB_ENDPTCTRL_RXI_MASK                   (0x20U)
90633 #define USB_ENDPTCTRL_RXI_SHIFT                  (5U)
90634 /*! RXI - RXI */
90635 #define USB_ENDPTCTRL_RXI(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
90636 
90637 #define USB_ENDPTCTRL_RXR_MASK                   (0x40U)
90638 #define USB_ENDPTCTRL_RXR_SHIFT                  (6U)
90639 /*! RXR - RXR */
90640 #define USB_ENDPTCTRL_RXR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
90641 
90642 #define USB_ENDPTCTRL_RXE_MASK                   (0x80U)
90643 #define USB_ENDPTCTRL_RXE_SHIFT                  (7U)
90644 /*! RXE - RXE */
90645 #define USB_ENDPTCTRL_RXE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
90646 
90647 #define USB_ENDPTCTRL_TXS_MASK                   (0x10000U)
90648 #define USB_ENDPTCTRL_TXS_SHIFT                  (16U)
90649 /*! TXS - TXS */
90650 #define USB_ENDPTCTRL_TXS(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
90651 
90652 #define USB_ENDPTCTRL_TXD_MASK                   (0x20000U)
90653 #define USB_ENDPTCTRL_TXD_SHIFT                  (17U)
90654 /*! TXD - TXD */
90655 #define USB_ENDPTCTRL_TXD(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
90656 
90657 #define USB_ENDPTCTRL_TXT_MASK                   (0xC0000U)
90658 #define USB_ENDPTCTRL_TXT_SHIFT                  (18U)
90659 /*! TXT - TXT */
90660 #define USB_ENDPTCTRL_TXT(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
90661 
90662 #define USB_ENDPTCTRL_TXI_MASK                   (0x200000U)
90663 #define USB_ENDPTCTRL_TXI_SHIFT                  (21U)
90664 /*! TXI - TXI */
90665 #define USB_ENDPTCTRL_TXI(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
90666 
90667 #define USB_ENDPTCTRL_TXR_MASK                   (0x400000U)
90668 #define USB_ENDPTCTRL_TXR_SHIFT                  (22U)
90669 /*! TXR - TXR */
90670 #define USB_ENDPTCTRL_TXR(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
90671 
90672 #define USB_ENDPTCTRL_TXE_MASK                   (0x800000U)
90673 #define USB_ENDPTCTRL_TXE_SHIFT                  (23U)
90674 /*! TXE - TXE */
90675 #define USB_ENDPTCTRL_TXE(x)                     (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
90676 /*! @} */
90677 
90678 /* The count of USB_ENDPTCTRL */
90679 #define USB_ENDPTCTRL_COUNT                      (7U)
90680 
90681 
90682 /*!
90683  * @}
90684  */ /* end of group USB_Register_Masks */
90685 
90686 
90687 /* USB - Peripheral instance base addresses */
90688 /** Peripheral USB_OTG1 base address */
90689 #define USB_OTG1_BASE                            (0x40430000u)
90690 /** Peripheral USB_OTG1 base pointer */
90691 #define USB_OTG1                                 ((USB_Type *)USB_OTG1_BASE)
90692 /** Peripheral USB_OTG2 base address */
90693 #define USB_OTG2_BASE                            (0x4042C000u)
90694 /** Peripheral USB_OTG2 base pointer */
90695 #define USB_OTG2                                 ((USB_Type *)USB_OTG2_BASE)
90696 /** Array initializer of USB peripheral base addresses */
90697 #define USB_BASE_ADDRS                           { 0u, USB_OTG1_BASE, USB_OTG2_BASE }
90698 /** Array initializer of USB peripheral base pointers */
90699 #define USB_BASE_PTRS                            { (USB_Type *)0u, USB_OTG1, USB_OTG2 }
90700 /** Interrupt vectors for the USB peripheral type */
90701 #define USB_IRQS                                 { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }
90702 /* Backward compatibility */
90703 #define GPTIMER0CTL                              GPTIMER0CTRL
90704 #define GPTIMER1CTL                              GPTIMER1CTRL
90705 #define USB_SBUSCFG                              SBUSCFG
90706 #define EPLISTADDR                               ENDPTLISTADDR
90707 #define EPSETUPSR                                ENDPTSETUPSTAT
90708 #define EPPRIME                                  ENDPTPRIME
90709 #define EPFLUSH                                  ENDPTFLUSH
90710 #define EPSR                                     ENDPTSTAT
90711 #define EPCOMPLETE                               ENDPTCOMPLETE
90712 #define EPCR                                     ENDPTCTRL
90713 #define EPCR0                                    ENDPTCTRL0
90714 #define USBHS_ID_ID_MASK                         USB_ID_ID_MASK
90715 #define USBHS_ID_ID_SHIFT                        USB_ID_ID_SHIFT
90716 #define USBHS_ID_ID(x)                           USB_ID_ID(x)
90717 #define USBHS_ID_NID_MASK                        USB_ID_NID_MASK
90718 #define USBHS_ID_NID_SHIFT                       USB_ID_NID_SHIFT
90719 #define USBHS_ID_NID(x)                          USB_ID_NID(x)
90720 #define USBHS_ID_REVISION_MASK                   USB_ID_REVISION_MASK
90721 #define USBHS_ID_REVISION_SHIFT                  USB_ID_REVISION_SHIFT
90722 #define USBHS_ID_REVISION(x)                     USB_ID_REVISION(x)
90723 #define USBHS_HWGENERAL_PHYW_MASK                USB_HWGENERAL_PHYW_MASK
90724 #define USBHS_HWGENERAL_PHYW_SHIFT               USB_HWGENERAL_PHYW_SHIFT
90725 #define USBHS_HWGENERAL_PHYW(x)                  USB_HWGENERAL_PHYW(x)
90726 #define USBHS_HWGENERAL_PHYM_MASK                USB_HWGENERAL_PHYM_MASK
90727 #define USBHS_HWGENERAL_PHYM_SHIFT               USB_HWGENERAL_PHYM_SHIFT
90728 #define USBHS_HWGENERAL_PHYM(x)                  USB_HWGENERAL_PHYM(x)
90729 #define USBHS_HWGENERAL_SM_MASK                  USB_HWGENERAL_SM_MASK
90730 #define USBHS_HWGENERAL_SM_SHIFT                 USB_HWGENERAL_SM_SHIFT
90731 #define USBHS_HWGENERAL_SM(x)                    USB_HWGENERAL_SM(x)
90732 #define USBHS_HWHOST_HC_MASK                     USB_HWHOST_HC_MASK
90733 #define USBHS_HWHOST_HC_SHIFT                    USB_HWHOST_HC_SHIFT
90734 #define USBHS_HWHOST_HC(x)                       USB_HWHOST_HC(x)
90735 #define USBHS_HWHOST_NPORT_MASK                  USB_HWHOST_NPORT_MASK
90736 #define USBHS_HWHOST_NPORT_SHIFT                 USB_HWHOST_NPORT_SHIFT
90737 #define USBHS_HWHOST_NPORT(x)                    USB_HWHOST_NPORT(x)
90738 #define USBHS_HWDEVICE_DC_MASK                   USB_HWDEVICE_DC_MASK
90739 #define USBHS_HWDEVICE_DC_SHIFT                  USB_HWDEVICE_DC_SHIFT
90740 #define USBHS_HWDEVICE_DC(x)                     USB_HWDEVICE_DC(x)
90741 #define USBHS_HWDEVICE_DEVEP_MASK                USB_HWDEVICE_DEVEP_MASK
90742 #define USBHS_HWDEVICE_DEVEP_SHIFT               USB_HWDEVICE_DEVEP_SHIFT
90743 #define USBHS_HWDEVICE_DEVEP(x)                  USB_HWDEVICE_DEVEP(x)
90744 #define USBHS_HWTXBUF_TXBURST_MASK               USB_HWTXBUF_TXBURST_MASK
90745 #define USBHS_HWTXBUF_TXBURST_SHIFT              USB_HWTXBUF_TXBURST_SHIFT
90746 #define USBHS_HWTXBUF_TXBURST(x)                 USB_HWTXBUF_TXBURST(x)
90747 #define USBHS_HWTXBUF_TXCHANADD_MASK             USB_HWTXBUF_TXCHANADD_MASK
90748 #define USBHS_HWTXBUF_TXCHANADD_SHIFT            USB_HWTXBUF_TXCHANADD_SHIFT
90749 #define USBHS_HWTXBUF_TXCHANADD(x)               USB_HWTXBUF_TXCHANADD(x)
90750 #define USBHS_HWRXBUF_RXBURST_MASK               USB_HWRXBUF_RXBURST_MASK
90751 #define USBHS_HWRXBUF_RXBURST_SHIFT              USB_HWRXBUF_RXBURST_SHIFT
90752 #define USBHS_HWRXBUF_RXBURST(x)                 USB_HWRXBUF_RXBURST(x)
90753 #define USBHS_HWRXBUF_RXADD_MASK                 USB_HWRXBUF_RXADD_MASK
90754 #define USBHS_HWRXBUF_RXADD_SHIFT                USB_HWRXBUF_RXADD_SHIFT
90755 #define USBHS_HWRXBUF_RXADD(x)                   USB_HWRXBUF_RXADD(x)
90756 #define USBHS_GPTIMER0LD_GPTLD_MASK              USB_GPTIMER0LD_GPTLD_MASK
90757 #define USBHS_GPTIMER0LD_GPTLD_SHIFT             USB_GPTIMER0LD_GPTLD_SHIFT
90758 #define USBHS_GPTIMER0LD_GPTLD(x)                USB_GPTIMER0LD_GPTLD(x)
90759 #define USBHS_GPTIMER0CTL_GPTCNT_MASK            USB_GPTIMER0CTRL_GPTCNT_MASK
90760 #define USBHS_GPTIMER0CTL_GPTCNT_SHIFT           USB_GPTIMER0CTRL_GPTCNT_SHIFT
90761 #define USBHS_GPTIMER0CTL_GPTCNT(x)              USB_GPTIMER0CTRL_GPTCNT(x)
90762 #define USBHS_GPTIMER0CTL_MODE_MASK              USB_GPTIMER0CTRL_GPTMODE_MASK
90763 #define USBHS_GPTIMER0CTL_MODE_SHIFT             USB_GPTIMER0CTRL_GPTMODE_SHIFT
90764 #define USBHS_GPTIMER0CTL_MODE(x)                USB_GPTIMER0CTRL_GPTMODE(x)
90765 #define USBHS_GPTIMER0CTL_RST_MASK               USB_GPTIMER0CTRL_GPTRST_MASK
90766 #define USBHS_GPTIMER0CTL_RST_SHIFT              USB_GPTIMER0CTRL_GPTRST_SHIFT
90767 #define USBHS_GPTIMER0CTL_RST(x)                 USB_GPTIMER0CTRL_GPTRST(x)
90768 #define USBHS_GPTIMER0CTL_RUN_MASK               USB_GPTIMER0CTRL_GPTRUN_MASK
90769 #define USBHS_GPTIMER0CTL_RUN_SHIFT              USB_GPTIMER0CTRL_GPTRUN_SHIFT
90770 #define USBHS_GPTIMER0CTL_RUN(x)                 USB_GPTIMER0CTRL_GPTRUN(x)
90771 #define USBHS_GPTIMER1LD_GPTLD_MASK              USB_GPTIMER1LD_GPTLD_MASK
90772 #define USBHS_GPTIMER1LD_GPTLD_SHIFT             USB_GPTIMER1LD_GPTLD_SHIFT
90773 #define USBHS_GPTIMER1LD_GPTLD(x)                USB_GPTIMER1LD_GPTLD(x)
90774 #define USBHS_GPTIMER1CTL_GPTCNT_MASK            USB_GPTIMER1CTRL_GPTCNT_MASK
90775 #define USBHS_GPTIMER1CTL_GPTCNT_SHIFT           USB_GPTIMER1CTRL_GPTCNT_SHIFT
90776 #define USBHS_GPTIMER1CTL_GPTCNT(x)              USB_GPTIMER1CTRL_GPTCNT(x)
90777 #define USBHS_GPTIMER1CTL_MODE_MASK              USB_GPTIMER1CTRL_GPTMODE_MASK
90778 #define USBHS_GPTIMER1CTL_MODE_SHIFT             USB_GPTIMER1CTRL_GPTMODE_SHIFT
90779 #define USBHS_GPTIMER1CTL_MODE(x)                USB_GPTIMER1CTRL_GPTMODE(x)
90780 #define USBHS_GPTIMER1CTL_RST_MASK               USB_GPTIMER1CTRL_GPTRST_MASK
90781 #define USBHS_GPTIMER1CTL_RST_SHIFT              USB_GPTIMER1CTRL_GPTRST_SHIFT
90782 #define USBHS_GPTIMER1CTL_RST(x)                 USB_GPTIMER1CTRL_GPTRST(x)
90783 #define USBHS_GPTIMER1CTL_RUN_MASK               USB_GPTIMER1CTRL_GPTRUN_MASK
90784 #define USBHS_GPTIMER1CTL_RUN_SHIFT              USB_GPTIMER1CTRL_GPTRUN_SHIFT
90785 #define USBHS_GPTIMER1CTL_RUN(x)                 USB_GPTIMER1CTRL_GPTRUN(x)
90786 #define USBHS_USB_SBUSCFG_BURSTMODE_MASK         USB_SBUSCFG_AHBBRST_MASK
90787 #define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT        USB_SBUSCFG_AHBBRST_SHIFT
90788 #define USBHS_USB_SBUSCFG_BURSTMODE(x)           USB_SBUSCFG_AHBBRST(x)
90789 #define USBHS_HCIVERSION_CAPLENGTH(x)            USB_HCIVERSION_CAPLENGTH(x)
90790 #define USBHS_HCIVERSION_HCIVERSION_MASK         USB_HCIVERSION_HCIVERSION_MASK
90791 #define USBHS_HCIVERSION_HCIVERSION_SHIFT        USB_HCIVERSION_HCIVERSION_SHIFT
90792 #define USBHS_HCIVERSION_HCIVERSION(x)           USB_HCIVERSION_HCIVERSION(x)
90793 #define USBHS_HCSPARAMS_N_PORTS_MASK             USB_HCSPARAMS_N_PORTS_MASK
90794 #define USBHS_HCSPARAMS_N_PORTS_SHIFT            USB_HCSPARAMS_N_PORTS_SHIFT
90795 #define USBHS_HCSPARAMS_N_PORTS(x)               USB_HCSPARAMS_N_PORTS(x)
90796 #define USBHS_HCSPARAMS_PPC_MASK                 USB_HCSPARAMS_PPC_MASK
90797 #define USBHS_HCSPARAMS_PPC_SHIFT                USB_HCSPARAMS_PPC_SHIFT
90798 #define USBHS_HCSPARAMS_PPC(x)                   USB_HCSPARAMS_PPC(x)
90799 #define USBHS_HCSPARAMS_N_PCC_MASK               USB_HCSPARAMS_N_PCC_MASK
90800 #define USBHS_HCSPARAMS_N_PCC_SHIFT              USB_HCSPARAMS_N_PCC_SHIFT
90801 #define USBHS_HCSPARAMS_N_PCC(x)                 USB_HCSPARAMS_N_PCC(x)
90802 #define USBHS_HCSPARAMS_N_CC_MASK                USB_HCSPARAMS_N_CC_MASK
90803 #define USBHS_HCSPARAMS_N_CC_SHIFT               USB_HCSPARAMS_N_CC_SHIFT
90804 #define USBHS_HCSPARAMS_N_CC(x)                  USB_HCSPARAMS_N_CC(x)
90805 #define USBHS_HCSPARAMS_PI_MASK                  USB_HCSPARAMS_PI_MASK
90806 #define USBHS_HCSPARAMS_PI_SHIFT                 USB_HCSPARAMS_PI_SHIFT
90807 #define USBHS_HCSPARAMS_PI(x)                    USB_HCSPARAMS_PI(x)
90808 #define USBHS_HCSPARAMS_N_PTT_MASK               USB_HCSPARAMS_N_PTT_MASK
90809 #define USBHS_HCSPARAMS_N_PTT_SHIFT              USB_HCSPARAMS_N_PTT_SHIFT
90810 #define USBHS_HCSPARAMS_N_PTT(x)                 USB_HCSPARAMS_N_PTT(x)
90811 #define USBHS_HCSPARAMS_N_TT_MASK                USB_HCSPARAMS_N_TT_MASK
90812 #define USBHS_HCSPARAMS_N_TT_SHIFT               USB_HCSPARAMS_N_TT_SHIFT
90813 #define USBHS_HCSPARAMS_N_TT(x)                  USB_HCSPARAMS_N_TT(x)
90814 #define USBHS_HCCPARAMS_ADC_MASK                 USB_HCCPARAMS_ADC_MASK
90815 #define USBHS_HCCPARAMS_ADC_SHIFT                USB_HCCPARAMS_ADC_SHIFT
90816 #define USBHS_HCCPARAMS_ADC(x)                   USB_HCCPARAMS_ADC(x)
90817 #define USBHS_HCCPARAMS_PFL_MASK                 USB_HCCPARAMS_PFL_MASK
90818 #define USBHS_HCCPARAMS_PFL_SHIFT                USB_HCCPARAMS_PFL_SHIFT
90819 #define USBHS_HCCPARAMS_PFL(x)                   USB_HCCPARAMS_PFL(x)
90820 #define USBHS_HCCPARAMS_ASP_MASK                 USB_HCCPARAMS_ASP_MASK
90821 #define USBHS_HCCPARAMS_ASP_SHIFT                USB_HCCPARAMS_ASP_SHIFT
90822 #define USBHS_HCCPARAMS_ASP(x)                   USB_HCCPARAMS_ASP(x)
90823 #define USBHS_HCCPARAMS_IST_MASK                 USB_HCCPARAMS_IST_MASK
90824 #define USBHS_HCCPARAMS_IST_SHIFT                USB_HCCPARAMS_IST_SHIFT
90825 #define USBHS_HCCPARAMS_IST(x)                   USB_HCCPARAMS_IST(x)
90826 #define USBHS_HCCPARAMS_EECP_MASK                USB_HCCPARAMS_EECP_MASK
90827 #define USBHS_HCCPARAMS_EECP_SHIFT               USB_HCCPARAMS_EECP_SHIFT
90828 #define USBHS_HCCPARAMS_EECP(x)                  USB_HCCPARAMS_EECP(x)
90829 #define USBHS_DCIVERSION_DCIVERSION_MASK         USB_DCIVERSION_DCIVERSION_MASK
90830 #define USBHS_DCIVERSION_DCIVERSION_SHIFT        USB_DCIVERSION_DCIVERSION_SHIFT
90831 #define USBHS_DCIVERSION_DCIVERSION(x)           USB_DCIVERSION_DCIVERSION(x)
90832 #define USBHS_DCCPARAMS_DEN_MASK                 USB_DCCPARAMS_DEN_MASK
90833 #define USBHS_DCCPARAMS_DEN_SHIFT                USB_DCCPARAMS_DEN_SHIFT
90834 #define USBHS_DCCPARAMS_DEN(x)                   USB_DCCPARAMS_DEN(x)
90835 #define USBHS_DCCPARAMS_DC_MASK                  USB_DCCPARAMS_DC_MASK
90836 #define USBHS_DCCPARAMS_DC_SHIFT                 USB_DCCPARAMS_DC_SHIFT
90837 #define USBHS_DCCPARAMS_DC(x)                    USB_DCCPARAMS_DC(x)
90838 #define USBHS_DCCPARAMS_HC_MASK                  USB_DCCPARAMS_HC_MASK
90839 #define USBHS_DCCPARAMS_HC_SHIFT                 USB_DCCPARAMS_HC_SHIFT
90840 #define USBHS_DCCPARAMS_HC(x)                    USB_DCCPARAMS_HC(x)
90841 #define USBHS_USBCMD_RS_MASK                     USB_USBCMD_RS_MASK
90842 #define USBHS_USBCMD_RS_SHIFT                    USB_USBCMD_RS_SHIFT
90843 #define USBHS_USBCMD_RS(x)                       USB_USBCMD_RS(x)
90844 #define USBHS_USBCMD_RST_MASK                    USB_USBCMD_RST_MASK
90845 #define USBHS_USBCMD_RST_SHIFT                   USB_USBCMD_RST_SHIFT
90846 #define USBHS_USBCMD_RST(x)                      USB_USBCMD_RST(x)
90847 #define USBHS_USBCMD_FS_MASK                     USB_USBCMD_FS_1_MASK
90848 #define USBHS_USBCMD_FS_SHIFT                    USB_USBCMD_FS_1_SHIFT
90849 #define USBHS_USBCMD_FS(x)                       USB_USBCMD_FS_1(x)
90850 #define USBHS_USBCMD_PSE_MASK                    USB_USBCMD_PSE_MASK
90851 #define USBHS_USBCMD_PSE_SHIFT                   USB_USBCMD_PSE_SHIFT
90852 #define USBHS_USBCMD_PSE(x)                      USB_USBCMD_PSE(x)
90853 #define USBHS_USBCMD_ASE_MASK                    USB_USBCMD_ASE_MASK
90854 #define USBHS_USBCMD_ASE_SHIFT                   USB_USBCMD_ASE_SHIFT
90855 #define USBHS_USBCMD_ASE(x)                      USB_USBCMD_ASE(x)
90856 #define USBHS_USBCMD_IAA_MASK                    USB_USBCMD_IAA_MASK
90857 #define USBHS_USBCMD_IAA_SHIFT                   USB_USBCMD_IAA_SHIFT
90858 #define USBHS_USBCMD_IAA(x)                      USB_USBCMD_IAA(x)
90859 #define USBHS_USBCMD_ASP_MASK                    USB_USBCMD_ASP_MASK
90860 #define USBHS_USBCMD_ASP_SHIFT                   USB_USBCMD_ASP_SHIFT
90861 #define USBHS_USBCMD_ASP(x)                      USB_USBCMD_ASP(x)
90862 #define USBHS_USBCMD_ASPE_MASK                   USB_USBCMD_ASPE_MASK
90863 #define USBHS_USBCMD_ASPE_SHIFT                  USB_USBCMD_ASPE_SHIFT
90864 #define USBHS_USBCMD_ASPE(x)                     USB_USBCMD_ASPE(x)
90865 #define USBHS_USBCMD_ATDTW_MASK                  USB_USBCMD_ATDTW_MASK
90866 #define USBHS_USBCMD_ATDTW_SHIFT                 USB_USBCMD_ATDTW_SHIFT
90867 #define USBHS_USBCMD_ATDTW(x)                    USB_USBCMD_ATDTW(x)
90868 #define USBHS_USBCMD_SUTW_MASK                   USB_USBCMD_SUTW_MASK
90869 #define USBHS_USBCMD_SUTW_SHIFT                  USB_USBCMD_SUTW_SHIFT
90870 #define USBHS_USBCMD_SUTW(x)                     USB_USBCMD_SUTW(x)
90871 #define USBHS_USBCMD_FS2_MASK                    USB_USBCMD_FS_2_MASK
90872 #define USBHS_USBCMD_FS2_SHIFT                   USB_USBCMD_FS_2_SHIFT
90873 #define USBHS_USBCMD_FS2(x)                      USB_USBCMD_FS_2(x)
90874 #define USBHS_USBCMD_ITC_MASK                    USB_USBCMD_ITC_MASK
90875 #define USBHS_USBCMD_ITC_SHIFT                   USB_USBCMD_ITC_SHIFT
90876 #define USBHS_USBCMD_ITC(x)                      USB_USBCMD_ITC(x)
90877 #define USBHS_USBSTS_UI_MASK                     USB_USBSTS_UI_MASK
90878 #define USBHS_USBSTS_UI_SHIFT                    USB_USBSTS_UI_SHIFT
90879 #define USBHS_USBSTS_UI(x)                       USB_USBSTS_UI(x)
90880 #define USBHS_USBSTS_UEI_MASK                    USB_USBSTS_UEI_MASK
90881 #define USBHS_USBSTS_UEI_SHIFT                   USB_USBSTS_UEI_SHIFT
90882 #define USBHS_USBSTS_UEI(x)                      USB_USBSTS_UEI(x)
90883 #define USBHS_USBSTS_PCI_MASK                    USB_USBSTS_PCI_MASK
90884 #define USBHS_USBSTS_PCI_SHIFT                   USB_USBSTS_PCI_SHIFT
90885 #define USBHS_USBSTS_PCI(x)                      USB_USBSTS_PCI(x)
90886 #define USBHS_USBSTS_FRI_MASK                    USB_USBSTS_FRI_MASK
90887 #define USBHS_USBSTS_FRI_SHIFT                   USB_USBSTS_FRI_SHIFT
90888 #define USBHS_USBSTS_FRI(x)                      USB_USBSTS_FRI(x)
90889 #define USBHS_USBSTS_SEI_MASK                    USB_USBSTS_SEI_MASK
90890 #define USBHS_USBSTS_SEI_SHIFT                   USB_USBSTS_SEI_SHIFT
90891 #define USBHS_USBSTS_SEI(x)                      USB_USBSTS_SEI(x)
90892 #define USBHS_USBSTS_AAI_MASK                    USB_USBSTS_AAI_MASK
90893 #define USBHS_USBSTS_AAI_SHIFT                   USB_USBSTS_AAI_SHIFT
90894 #define USBHS_USBSTS_AAI(x)                      USB_USBSTS_AAI(x)
90895 #define USBHS_USBSTS_URI_MASK                    USB_USBSTS_URI_MASK
90896 #define USBHS_USBSTS_URI_SHIFT                   USB_USBSTS_URI_SHIFT
90897 #define USBHS_USBSTS_URI(x)                      USB_USBSTS_URI(x)
90898 #define USBHS_USBSTS_SRI_MASK                    USB_USBSTS_SRI_MASK
90899 #define USBHS_USBSTS_SRI_SHIFT                   USB_USBSTS_SRI_SHIFT
90900 #define USBHS_USBSTS_SRI(x)                      USB_USBSTS_SRI(x)
90901 #define USBHS_USBSTS_SLI_MASK                    USB_USBSTS_SLI_MASK
90902 #define USBHS_USBSTS_SLI_SHIFT                   USB_USBSTS_SLI_SHIFT
90903 #define USBHS_USBSTS_SLI(x)                      USB_USBSTS_SLI(x)
90904 #define USBHS_USBSTS_ULPII_MASK                  USB_USBSTS_ULPII_MASK
90905 #define USBHS_USBSTS_ULPII_SHIFT                 USB_USBSTS_ULPII_SHIFT
90906 #define USBHS_USBSTS_ULPII(x)                    USB_USBSTS_ULPII(x)
90907 #define USBHS_USBSTS_HCH_MASK                    USB_USBSTS_HCH_MASK
90908 #define USBHS_USBSTS_HCH_SHIFT                   USB_USBSTS_HCH_SHIFT
90909 #define USBHS_USBSTS_HCH(x)                      USB_USBSTS_HCH(x)
90910 #define USBHS_USBSTS_RCL_MASK                    USB_USBSTS_RCL_MASK
90911 #define USBHS_USBSTS_RCL_SHIFT                   USB_USBSTS_RCL_SHIFT
90912 #define USBHS_USBSTS_RCL(x)                      USB_USBSTS_RCL(x)
90913 #define USBHS_USBSTS_PS_MASK                     USB_USBSTS_PS_MASK
90914 #define USBHS_USBSTS_PS_SHIFT                    USB_USBSTS_PS_SHIFT
90915 #define USBHS_USBSTS_PS(x)                       USB_USBSTS_PS(x)
90916 #define USBHS_USBSTS_AS_MASK                     USB_USBSTS_AS_MASK
90917 #define USBHS_USBSTS_AS_SHIFT                    USB_USBSTS_AS_SHIFT
90918 #define USBHS_USBSTS_AS(x)                       USB_USBSTS_AS(x)
90919 #define USBHS_USBSTS_NAKI_MASK                   USB_USBSTS_NAKI_MASK
90920 #define USBHS_USBSTS_NAKI_SHIFT                  USB_USBSTS_NAKI_SHIFT
90921 #define USBHS_USBSTS_NAKI(x)                     USB_USBSTS_NAKI(x)
90922 #define USBHS_USBSTS_TI0_MASK                    USB_USBSTS_TI0_MASK
90923 #define USBHS_USBSTS_TI0_SHIFT                   USB_USBSTS_TI0_SHIFT
90924 #define USBHS_USBSTS_TI0(x)                      USB_USBSTS_TI0(x)
90925 #define USBHS_USBSTS_TI1_MASK                    USB_USBSTS_TI1_MASK
90926 #define USBHS_USBSTS_TI1_SHIFT                   USB_USBSTS_TI1_SHIFT
90927 #define USBHS_USBSTS_TI1(x)                      USB_USBSTS_TI1(x)
90928 #define USBHS_USBINTR_UE_MASK                    USB_USBINTR_UE_MASK
90929 #define USBHS_USBINTR_UE_SHIFT                   USB_USBINTR_UE_SHIFT
90930 #define USBHS_USBINTR_UE(x)                      USB_USBINTR_UE(x)
90931 #define USBHS_USBINTR_UEE_MASK                   USB_USBINTR_UEE_MASK
90932 #define USBHS_USBINTR_UEE_SHIFT                  USB_USBINTR_UEE_SHIFT
90933 #define USBHS_USBINTR_UEE(x)                     USB_USBINTR_UEE(x)
90934 #define USBHS_USBINTR_PCE_MASK                   USB_USBINTR_PCE_MASK
90935 #define USBHS_USBINTR_PCE_SHIFT                  USB_USBINTR_PCE_SHIFT
90936 #define USBHS_USBINTR_PCE(x)                     USB_USBINTR_PCE(x)
90937 #define USBHS_USBINTR_FRE_MASK                   USB_USBINTR_FRE_MASK
90938 #define USBHS_USBINTR_FRE_SHIFT                  USB_USBINTR_FRE_SHIFT
90939 #define USBHS_USBINTR_FRE(x)                     USB_USBINTR_FRE(x)
90940 #define USBHS_USBINTR_SEE_MASK                   USB_USBINTR_SEE_MASK
90941 #define USBHS_USBINTR_SEE_SHIFT                  USB_USBINTR_SEE_SHIFT
90942 #define USBHS_USBINTR_SEE(x)                     USB_USBINTR_SEE(x)
90943 #define USBHS_USBINTR_AAE_MASK                   USB_USBINTR_AAE_MASK
90944 #define USBHS_USBINTR_AAE_SHIFT                  USB_USBINTR_AAE_SHIFT
90945 #define USBHS_USBINTR_AAE(x)                     USB_USBINTR_AAE(x)
90946 #define USBHS_USBINTR_URE_MASK                   USB_USBINTR_URE_MASK
90947 #define USBHS_USBINTR_URE_SHIFT                  USB_USBINTR_URE_SHIFT
90948 #define USBHS_USBINTR_URE(x)                     USB_USBINTR_URE(x)
90949 #define USBHS_USBINTR_SRE_MASK                   USB_USBINTR_SRE_MASK
90950 #define USBHS_USBINTR_SRE_SHIFT                  USB_USBINTR_SRE_SHIFT
90951 #define USBHS_USBINTR_SRE(x)                     USB_USBINTR_SRE(x)
90952 #define USBHS_USBINTR_SLE_MASK                   USB_USBINTR_SLE_MASK
90953 #define USBHS_USBINTR_SLE_SHIFT                  USB_USBINTR_SLE_SHIFT
90954 #define USBHS_USBINTR_SLE(x)                     USB_USBINTR_SLE(x)
90955 #define USBHS_USBINTR_ULPIE_MASK                 USB_USBINTR_ULPIE_MASK
90956 #define USBHS_USBINTR_ULPIE_SHIFT                USB_USBINTR_ULPIE_SHIFT
90957 #define USBHS_USBINTR_ULPIE(x)                   USB_USBINTR_ULPIE(x)
90958 #define USBHS_USBINTR_NAKE_MASK                  USB_USBINTR_NAKE_MASK
90959 #define USBHS_USBINTR_NAKE_SHIFT                 USB_USBINTR_NAKE_SHIFT
90960 #define USBHS_USBINTR_NAKE(x)                    USB_USBINTR_NAKE(x)
90961 #define USBHS_USBINTR_UAIE_MASK                  USB_USBINTR_UAIE_MASK
90962 #define USBHS_USBINTR_UAIE_SHIFT                 USB_USBINTR_UAIE_SHIFT
90963 #define USBHS_USBINTR_UAIE(x)                    USB_USBINTR_UAIE(x)
90964 #define USBHS_USBINTR_UPIE_MASK                  USB_USBINTR_UPIE_MASK
90965 #define USBHS_USBINTR_UPIE_SHIFT                 USB_USBINTR_UPIE_SHIFT
90966 #define USBHS_USBINTR_UPIE(x)                    USB_USBINTR_UPIE(x)
90967 #define USBHS_USBINTR_TIE0_MASK                  USB_USBINTR_TIE0_MASK
90968 #define USBHS_USBINTR_TIE0_SHIFT                 USB_USBINTR_TIE0_SHIFT
90969 #define USBHS_USBINTR_TIE0(x)                    USB_USBINTR_TIE0(x)
90970 #define USBHS_USBINTR_TIE1_MASK                  USB_USBINTR_TIE1_MASK
90971 #define USBHS_USBINTR_TIE1_SHIFT                 USB_USBINTR_TIE1_SHIFT
90972 #define USBHS_USBINTR_TIE1(x)                    USB_USBINTR_TIE1(x)
90973 #define USBHS_FRINDEX_FRINDEX_MASK               USB_FRINDEX_FRINDEX_MASK
90974 #define USBHS_FRINDEX_FRINDEX_SHIFT              USB_FRINDEX_FRINDEX_SHIFT
90975 #define USBHS_FRINDEX_FRINDEX(x)                 USB_FRINDEX_FRINDEX(x)
90976 #define USBHS_DEVICEADDR_USBADRA_MASK            USB_DEVICEADDR_USBADRA_MASK
90977 #define USBHS_DEVICEADDR_USBADRA_SHIFT           USB_DEVICEADDR_USBADRA_SHIFT
90978 #define USBHS_DEVICEADDR_USBADRA(x)              USB_DEVICEADDR_USBADRA(x)
90979 #define USBHS_DEVICEADDR_USBADR_MASK             USB_DEVICEADDR_USBADR_MASK
90980 #define USBHS_DEVICEADDR_USBADR_SHIFT            USB_DEVICEADDR_USBADR_SHIFT
90981 #define USBHS_DEVICEADDR_USBADR(x)               USB_DEVICEADDR_USBADR(x)
90982 #define USBHS_PERIODICLISTBASE_PERBASE_MASK      USB_PERIODICLISTBASE_BASEADR_MASK
90983 #define USBHS_PERIODICLISTBASE_PERBASE_SHIFT     USB_PERIODICLISTBASE_BASEADR_SHIFT
90984 #define USBHS_PERIODICLISTBASE_PERBASE(x)        USB_PERIODICLISTBASE_BASEADR(x)
90985 #define USBHS_ASYNCLISTADDR_ASYBASE_MASK         USB_ASYNCLISTADDR_ASYBASE_MASK
90986 #define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT        USB_ASYNCLISTADDR_ASYBASE_SHIFT
90987 #define USBHS_ASYNCLISTADDR_ASYBASE(x)           USB_ASYNCLISTADDR_ASYBASE(x)
90988 #define USBHS_EPLISTADDR_EPBASE_MASK             USB_ENDPTLISTADDR_EPBASE_MASK
90989 #define USBHS_EPLISTADDR_EPBASE_SHIFT            USB_ENDPTLISTADDR_EPBASE_SHIFT
90990 #define USBHS_EPLISTADDR_EPBASE(x)               USB_ENDPTLISTADDR_EPBASE(x)
90991 #define USBHS_BURSTSIZE_RXPBURST_MASK            USB_BURSTSIZE_RXPBURST_MASK
90992 #define USBHS_BURSTSIZE_RXPBURST_SHIFT           USB_BURSTSIZE_RXPBURST_SHIFT
90993 #define USBHS_BURSTSIZE_RXPBURST(x)              USB_BURSTSIZE_RXPBURST(x)
90994 #define USBHS_BURSTSIZE_TXPBURST_MASK            USB_BURSTSIZE_TXPBURST_MASK
90995 #define USBHS_BURSTSIZE_TXPBURST_SHIFT           USB_BURSTSIZE_TXPBURST_SHIFT
90996 #define USBHS_BURSTSIZE_TXPBURST(x)              USB_BURSTSIZE_TXPBURST(x)
90997 #define USBHS_TXFILLTUNING_TXSCHOH_MASK          USB_TXFILLTUNING_TXSCHOH_MASK
90998 #define USBHS_TXFILLTUNING_TXSCHOH_SHIFT         USB_TXFILLTUNING_TXSCHOH_SHIFT
90999 #define USBHS_TXFILLTUNING_TXSCHOH(x)            USB_TXFILLTUNING_TXSCHOH(x)
91000 #define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK      USB_TXFILLTUNING_TXSCHHEALTH_MASK
91001 #define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT     USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
91002 #define USBHS_TXFILLTUNING_TXSCHHEALTH(x)        USB_TXFILLTUNING_TXSCHHEALTH(x)
91003 #define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK      USB_TXFILLTUNING_TXFIFOTHRES_MASK
91004 #define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT     USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
91005 #define USBHS_TXFILLTUNING_TXFIFOTHRES(x)        USB_TXFILLTUNING_TXFIFOTHRES(x)
91006 #define USBHS_ENDPTNAK_EPRN_MASK                 USB_ENDPTNAK_EPRN_MASK
91007 #define USBHS_ENDPTNAK_EPRN_SHIFT                USB_ENDPTNAK_EPRN_SHIFT
91008 #define USBHS_ENDPTNAK_EPRN(x)                   USB_ENDPTNAK_EPRN(x)
91009 #define USBHS_ENDPTNAK_EPTN_MASK                 USB_ENDPTNAK_EPTN_MASK
91010 #define USBHS_ENDPTNAK_EPTN_SHIFT                USB_ENDPTNAK_EPTN_SHIFT
91011 #define USBHS_ENDPTNAK_EPTN(x)                   USB_ENDPTNAK_EPTN(x)
91012 #define USBHS_ENDPTNAKEN_EPRNE_MASK              USB_ENDPTNAKEN_EPRNE_MASK
91013 #define USBHS_ENDPTNAKEN_EPRNE_SHIFT             USB_ENDPTNAKEN_EPRNE_SHIFT
91014 #define USBHS_ENDPTNAKEN_EPRNE(x)                USB_ENDPTNAKEN_EPRNE(x)
91015 #define USBHS_ENDPTNAKEN_EPTNE_MASK              USB_ENDPTNAKEN_EPTNE_MASK
91016 #define USBHS_ENDPTNAKEN_EPTNE_SHIFT             USB_ENDPTNAKEN_EPTNE_SHIFT
91017 #define USBHS_ENDPTNAKEN_EPTNE(x)                USB_ENDPTNAKEN_EPTNE(x)
91018 #define USBHS_CONFIGFLAG_CF_MASK                 USB_CONFIGFLAG_CF_MASK
91019 #define USBHS_CONFIGFLAG_CF_SHIFT                USB_CONFIGFLAG_CF_SHIFT
91020 #define USBHS_CONFIGFLAG_CF(x)                   USB_CONFIGFLAG_CF(x)
91021 #define USBHS_PORTSC1_CCS_MASK                   USB_PORTSC1_CCS_MASK
91022 #define USBHS_PORTSC1_CCS_SHIFT                  USB_PORTSC1_CCS_SHIFT
91023 #define USBHS_PORTSC1_CCS(x)                     USB_PORTSC1_CCS(x)
91024 #define USBHS_PORTSC1_CSC_MASK                   USB_PORTSC1_CSC_MASK
91025 #define USBHS_PORTSC1_CSC_SHIFT                  USB_PORTSC1_CSC_SHIFT
91026 #define USBHS_PORTSC1_CSC(x)                     USB_PORTSC1_CSC(x)
91027 #define USBHS_PORTSC1_PE_MASK                    USB_PORTSC1_PE_MASK
91028 #define USBHS_PORTSC1_PE_SHIFT                   USB_PORTSC1_PE_SHIFT
91029 #define USBHS_PORTSC1_PE(x)                      USB_PORTSC1_PE(x)
91030 #define USBHS_PORTSC1_PEC_MASK                   USB_PORTSC1_PEC_MASK
91031 #define USBHS_PORTSC1_PEC_SHIFT                  USB_PORTSC1_PEC_SHIFT
91032 #define USBHS_PORTSC1_PEC(x)                     USB_PORTSC1_PEC(x)
91033 #define USBHS_PORTSC1_OCA_MASK                   USB_PORTSC1_OCA_MASK
91034 #define USBHS_PORTSC1_OCA_SHIFT                  USB_PORTSC1_OCA_SHIFT
91035 #define USBHS_PORTSC1_OCA(x)                     USB_PORTSC1_OCA(x)
91036 #define USBHS_PORTSC1_OCC_MASK                   USB_PORTSC1_OCC_MASK
91037 #define USBHS_PORTSC1_OCC_SHIFT                  USB_PORTSC1_OCC_SHIFT
91038 #define USBHS_PORTSC1_OCC(x)                     USB_PORTSC1_OCC(x)
91039 #define USBHS_PORTSC1_FPR_MASK                   USB_PORTSC1_FPR_MASK
91040 #define USBHS_PORTSC1_FPR_SHIFT                  USB_PORTSC1_FPR_SHIFT
91041 #define USBHS_PORTSC1_FPR(x)                     USB_PORTSC1_FPR(x)
91042 #define USBHS_PORTSC1_SUSP_MASK                  USB_PORTSC1_SUSP_MASK
91043 #define USBHS_PORTSC1_SUSP_SHIFT                 USB_PORTSC1_SUSP_SHIFT
91044 #define USBHS_PORTSC1_SUSP(x)                    USB_PORTSC1_SUSP(x)
91045 #define USBHS_PORTSC1_PR_MASK                    USB_PORTSC1_PR_MASK
91046 #define USBHS_PORTSC1_PR_SHIFT                   USB_PORTSC1_PR_SHIFT
91047 #define USBHS_PORTSC1_PR(x)                      USB_PORTSC1_PR(x)
91048 #define USBHS_PORTSC1_HSP_MASK                   USB_PORTSC1_HSP_MASK
91049 #define USBHS_PORTSC1_HSP_SHIFT                  USB_PORTSC1_HSP_SHIFT
91050 #define USBHS_PORTSC1_HSP(x)                     USB_PORTSC1_HSP(x)
91051 #define USBHS_PORTSC1_LS_MASK                    USB_PORTSC1_LS_MASK
91052 #define USBHS_PORTSC1_LS_SHIFT                   USB_PORTSC1_LS_SHIFT
91053 #define USBHS_PORTSC1_LS(x)                      USB_PORTSC1_LS(x)
91054 #define USBHS_PORTSC1_PP_MASK                    USB_PORTSC1_PP_MASK
91055 #define USBHS_PORTSC1_PP_SHIFT                   USB_PORTSC1_PP_SHIFT
91056 #define USBHS_PORTSC1_PP(x)                      USB_PORTSC1_PP(x)
91057 #define USBHS_PORTSC1_PO_MASK                    USB_PORTSC1_PO_MASK
91058 #define USBHS_PORTSC1_PO_SHIFT                   USB_PORTSC1_PO_SHIFT
91059 #define USBHS_PORTSC1_PO(x)                      USB_PORTSC1_PO(x)
91060 #define USBHS_PORTSC1_PIC_MASK                   USB_PORTSC1_PIC_MASK
91061 #define USBHS_PORTSC1_PIC_SHIFT                  USB_PORTSC1_PIC_SHIFT
91062 #define USBHS_PORTSC1_PIC(x)                     USB_PORTSC1_PIC(x)
91063 #define USBHS_PORTSC1_PTC_MASK                   USB_PORTSC1_PTC_MASK
91064 #define USBHS_PORTSC1_PTC_SHIFT                  USB_PORTSC1_PTC_SHIFT
91065 #define USBHS_PORTSC1_PTC(x)                     USB_PORTSC1_PTC(x)
91066 #define USBHS_PORTSC1_WKCN_MASK                  USB_PORTSC1_WKCN_MASK
91067 #define USBHS_PORTSC1_WKCN_SHIFT                 USB_PORTSC1_WKCN_SHIFT
91068 #define USBHS_PORTSC1_WKCN(x)                    USB_PORTSC1_WKCN(x)
91069 #define USBHS_PORTSC1_WKDS_MASK                  USB_PORTSC1_WKDC_MASK
91070 #define USBHS_PORTSC1_WKDS_SHIFT                 USB_PORTSC1_WKDC_SHIFT
91071 #define USBHS_PORTSC1_WKDS(x)                    USB_PORTSC1_WKDC(x)
91072 #define USBHS_PORTSC1_WKOC_MASK                  USB_PORTSC1_WKOC_MASK
91073 #define USBHS_PORTSC1_WKOC_SHIFT                 USB_PORTSC1_WKOC_SHIFT
91074 #define USBHS_PORTSC1_WKOC(x)                    USB_PORTSC1_WKOC(x)
91075 #define USBHS_PORTSC1_PHCD_MASK                  USB_PORTSC1_PHCD_MASK
91076 #define USBHS_PORTSC1_PHCD_SHIFT                 USB_PORTSC1_PHCD_SHIFT
91077 #define USBHS_PORTSC1_PHCD(x)                    USB_PORTSC1_PHCD(x)
91078 #define USBHS_PORTSC1_PFSC_MASK                  USB_PORTSC1_PFSC_MASK
91079 #define USBHS_PORTSC1_PFSC_SHIFT                 USB_PORTSC1_PFSC_SHIFT
91080 #define USBHS_PORTSC1_PFSC(x)                    USB_PORTSC1_PFSC(x)
91081 #define USBHS_PORTSC1_PTS2_MASK                  USB_PORTSC1_PTS_2_MASK
91082 #define USBHS_PORTSC1_PTS2_SHIFT                 USB_PORTSC1_PTS_2_SHIFT
91083 #define USBHS_PORTSC1_PTS2(x)                    USB_PORTSC1_PTS_2(x)
91084 #define USBHS_PORTSC1_PSPD_MASK                  USB_PORTSC1_PSPD_MASK
91085 #define USBHS_PORTSC1_PSPD_SHIFT                 USB_PORTSC1_PSPD_SHIFT
91086 #define USBHS_PORTSC1_PSPD(x)                    USB_PORTSC1_PSPD(x)
91087 #define USBHS_PORTSC1_PTW_MASK                   USB_PORTSC1_PTW_MASK
91088 #define USBHS_PORTSC1_PTW_SHIFT                  USB_PORTSC1_PTW_SHIFT
91089 #define USBHS_PORTSC1_PTW(x)                     USB_PORTSC1_PTW(x)
91090 #define USBHS_PORTSC1_STS_MASK                   USB_PORTSC1_STS_MASK
91091 #define USBHS_PORTSC1_STS_SHIFT                  USB_PORTSC1_STS_SHIFT
91092 #define USBHS_PORTSC1_STS(x)                     USB_PORTSC1_STS(x)
91093 #define USBHS_PORTSC1_PTS_MASK                   USB_PORTSC1_PTS_1_MASK
91094 #define USBHS_PORTSC1_PTS_SHIFT                  USB_PORTSC1_PTS_1_SHIFT
91095 #define USBHS_PORTSC1_PTS(x)                     USB_PORTSC1_PTS_1(x)
91096 #define USBHS_OTGSC_VD_MASK                      USB_OTGSC_VD_MASK
91097 #define USBHS_OTGSC_VD_SHIFT                     USB_OTGSC_VD_SHIFT
91098 #define USBHS_OTGSC_VD(x)                        USB_OTGSC_VD(x)
91099 #define USBHS_OTGSC_VC_MASK                      USB_OTGSC_VC_MASK
91100 #define USBHS_OTGSC_VC_SHIFT                     USB_OTGSC_VC_SHIFT
91101 #define USBHS_OTGSC_VC(x)                        USB_OTGSC_VC(x)
91102 #define USBHS_OTGSC_OT_MASK                      USB_OTGSC_OT_MASK
91103 #define USBHS_OTGSC_OT_SHIFT                     USB_OTGSC_OT_SHIFT
91104 #define USBHS_OTGSC_OT(x)                        USB_OTGSC_OT(x)
91105 #define USBHS_OTGSC_DP_MASK                      USB_OTGSC_DP_MASK
91106 #define USBHS_OTGSC_DP_SHIFT                     USB_OTGSC_DP_SHIFT
91107 #define USBHS_OTGSC_DP(x)                        USB_OTGSC_DP(x)
91108 #define USBHS_OTGSC_IDPU_MASK                    USB_OTGSC_IDPU_MASK
91109 #define USBHS_OTGSC_IDPU_SHIFT                   USB_OTGSC_IDPU_SHIFT
91110 #define USBHS_OTGSC_IDPU(x)                      USB_OTGSC_IDPU(x)
91111 #define USBHS_OTGSC_ID_MASK                      USB_OTGSC_ID_MASK
91112 #define USBHS_OTGSC_ID_SHIFT                     USB_OTGSC_ID_SHIFT
91113 #define USBHS_OTGSC_ID(x)                        USB_OTGSC_ID(x)
91114 #define USBHS_OTGSC_AVV_MASK                     USB_OTGSC_AVV_MASK
91115 #define USBHS_OTGSC_AVV_SHIFT                    USB_OTGSC_AVV_SHIFT
91116 #define USBHS_OTGSC_AVV(x)                       USB_OTGSC_AVV(x)
91117 #define USBHS_OTGSC_ASV_MASK                     USB_OTGSC_ASV_MASK
91118 #define USBHS_OTGSC_ASV_SHIFT                    USB_OTGSC_ASV_SHIFT
91119 #define USBHS_OTGSC_ASV(x)                       USB_OTGSC_ASV(x)
91120 #define USBHS_OTGSC_BSV_MASK                     USB_OTGSC_BSV_MASK
91121 #define USBHS_OTGSC_BSV_SHIFT                    USB_OTGSC_BSV_SHIFT
91122 #define USBHS_OTGSC_BSV(x)                       USB_OTGSC_BSV(x)
91123 #define USBHS_OTGSC_BSE_MASK                     USB_OTGSC_BSE_MASK
91124 #define USBHS_OTGSC_BSE_SHIFT                    USB_OTGSC_BSE_SHIFT
91125 #define USBHS_OTGSC_BSE(x)                       USB_OTGSC_BSE(x)
91126 #define USBHS_OTGSC_MST_MASK                     USB_OTGSC_TOG_1MS_MASK
91127 #define USBHS_OTGSC_MST_SHIFT                    USB_OTGSC_TOG_1MS_SHIFT
91128 #define USBHS_OTGSC_MST(x)                       USB_OTGSC_TOG_1MS(x)
91129 #define USBHS_OTGSC_DPS_MASK                     USB_OTGSC_DPS_MASK
91130 #define USBHS_OTGSC_DPS_SHIFT                    USB_OTGSC_DPS_SHIFT
91131 #define USBHS_OTGSC_DPS(x)                       USB_OTGSC_DPS(x)
91132 #define USBHS_OTGSC_IDIS_MASK                    USB_OTGSC_IDIS_MASK
91133 #define USBHS_OTGSC_IDIS_SHIFT                   USB_OTGSC_IDIS_SHIFT
91134 #define USBHS_OTGSC_IDIS(x)                      USB_OTGSC_IDIS(x)
91135 #define USBHS_OTGSC_AVVIS_MASK                   USB_OTGSC_AVVIS_MASK
91136 #define USBHS_OTGSC_AVVIS_SHIFT                  USB_OTGSC_AVVIS_SHIFT
91137 #define USBHS_OTGSC_AVVIS(x)                     USB_OTGSC_AVVIS(x)
91138 #define USBHS_OTGSC_ASVIS_MASK                   USB_OTGSC_ASVIS_MASK
91139 #define USBHS_OTGSC_ASVIS_SHIFT                  USB_OTGSC_ASVIS_SHIFT
91140 #define USBHS_OTGSC_ASVIS(x)                     USB_OTGSC_ASVIS(x)
91141 #define USBHS_OTGSC_BSVIS_MASK                   USB_OTGSC_BSVIS_MASK
91142 #define USBHS_OTGSC_BSVIS_SHIFT                  USB_OTGSC_BSVIS_SHIFT
91143 #define USBHS_OTGSC_BSVIS(x)                     USB_OTGSC_BSVIS(x)
91144 #define USBHS_OTGSC_BSEIS_MASK                   USB_OTGSC_BSEIS_MASK
91145 #define USBHS_OTGSC_BSEIS_SHIFT                  USB_OTGSC_BSEIS_SHIFT
91146 #define USBHS_OTGSC_BSEIS(x)                     USB_OTGSC_BSEIS(x)
91147 #define USBHS_OTGSC_MSS_MASK                     USB_OTGSC_STATUS_1MS_MASK
91148 #define USBHS_OTGSC_MSS_SHIFT                    USB_OTGSC_STATUS_1MS_SHIFT
91149 #define USBHS_OTGSC_MSS(x)                       USB_OTGSC_STATUS_1MS(x)
91150 #define USBHS_OTGSC_DPIS_MASK                    USB_OTGSC_DPIS_MASK
91151 #define USBHS_OTGSC_DPIS_SHIFT                   USB_OTGSC_DPIS_SHIFT
91152 #define USBHS_OTGSC_DPIS(x)                      USB_OTGSC_DPIS(x)
91153 #define USBHS_OTGSC_IDIE_MASK                    USB_OTGSC_IDIE_MASK
91154 #define USBHS_OTGSC_IDIE_SHIFT                   USB_OTGSC_IDIE_SHIFT
91155 #define USBHS_OTGSC_IDIE(x)                      USB_OTGSC_IDIE(x)
91156 #define USBHS_OTGSC_AVVIE_MASK                   USB_OTGSC_AVVIE_MASK
91157 #define USBHS_OTGSC_AVVIE_SHIFT                  USB_OTGSC_AVVIE_SHIFT
91158 #define USBHS_OTGSC_AVVIE(x)                     USB_OTGSC_AVVIE(x)
91159 #define USBHS_OTGSC_ASVIE_MASK                   USB_OTGSC_ASVIE_MASK
91160 #define USBHS_OTGSC_ASVIE_SHIFT                  USB_OTGSC_ASVIE_SHIFT
91161 #define USBHS_OTGSC_ASVIE(x)                     USB_OTGSC_ASVIE(x)
91162 #define USBHS_OTGSC_BSVIE_MASK                   USB_OTGSC_BSVIE_MASK
91163 #define USBHS_OTGSC_BSVIE_SHIFT                  USB_OTGSC_BSVIE_SHIFT
91164 #define USBHS_OTGSC_BSVIE(x)                     USB_OTGSC_BSVIE(x)
91165 #define USBHS_OTGSC_BSEIE_MASK                   USB_OTGSC_BSEIE_MASK
91166 #define USBHS_OTGSC_BSEIE_SHIFT                  USB_OTGSC_BSEIE_SHIFT
91167 #define USBHS_OTGSC_BSEIE(x)                     USB_OTGSC_BSEIE(x)
91168 #define USBHS_OTGSC_MSE_MASK                     USB_OTGSC_EN_1MS_MASK
91169 #define USBHS_OTGSC_MSE_SHIFT                    USB_OTGSC_EN_1MS_SHIFT
91170 #define USBHS_OTGSC_MSE(x)                       USB_OTGSC_EN_1MS(x)
91171 #define USBHS_OTGSC_DPIE_MASK                    USB_OTGSC_DPIE_MASK
91172 #define USBHS_OTGSC_DPIE_SHIFT                   USB_OTGSC_DPIE_SHIFT
91173 #define USBHS_OTGSC_DPIE(x)                      USB_OTGSC_DPIE(x)
91174 #define USBHS_USBMODE_CM_MASK                    USB_USBMODE_CM_MASK
91175 #define USBHS_USBMODE_CM_SHIFT                   USB_USBMODE_CM_SHIFT
91176 #define USBHS_USBMODE_CM(x)                      USB_USBMODE_CM(x)
91177 #define USBHS_USBMODE_ES_MASK                    USB_USBMODE_ES_MASK
91178 #define USBHS_USBMODE_ES_SHIFT                   USB_USBMODE_ES_SHIFT
91179 #define USBHS_USBMODE_ES(x)                      USB_USBMODE_ES(x)
91180 #define USBHS_USBMODE_SLOM_MASK                  USB_USBMODE_SLOM_MASK
91181 #define USBHS_USBMODE_SLOM_SHIFT                 USB_USBMODE_SLOM_SHIFT
91182 #define USBHS_USBMODE_SLOM(x)                    USB_USBMODE_SLOM(x)
91183 #define USBHS_USBMODE_SDIS_MASK                  USB_USBMODE_SDIS_MASK
91184 #define USBHS_USBMODE_SDIS_SHIFT                 USB_USBMODE_SDIS_SHIFT
91185 #define USBHS_USBMODE_SDIS(x)                    USB_USBMODE_SDIS(x)
91186 #define USBHS_EPSETUPSR_EPSETUPSTAT_MASK         USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
91187 #define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT        USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
91188 #define USBHS_EPSETUPSR_EPSETUPSTAT(x)           USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
91189 #define USBHS_EPPRIME_PERB_MASK                  USB_ENDPTPRIME_PERB_MASK
91190 #define USBHS_EPPRIME_PERB_SHIFT                 USB_ENDPTPRIME_PERB_SHIFT
91191 #define USBHS_EPPRIME_PERB(x)                    USB_ENDPTPRIME_PERB(x)
91192 #define USBHS_EPPRIME_PETB_MASK                  USB_ENDPTPRIME_PETB_MASK
91193 #define USBHS_EPPRIME_PETB_SHIFT                 USB_ENDPTPRIME_PETB_SHIFT
91194 #define USBHS_EPPRIME_PETB(x)                    USB_ENDPTPRIME_PETB(x)
91195 #define USBHS_EPFLUSH_FERB_MASK                  USB_ENDPTFLUSH_FERB_MASK
91196 #define USBHS_EPFLUSH_FERB_SHIFT                 USB_ENDPTFLUSH_FERB_SHIFT
91197 #define USBHS_EPFLUSH_FERB(x)                    USB_ENDPTFLUSH_FERB(x)
91198 #define USBHS_EPFLUSH_FETB_MASK                  USB_ENDPTFLUSH_FETB_MASK
91199 #define USBHS_EPFLUSH_FETB_SHIFT                 USB_ENDPTFLUSH_FETB_SHIFT
91200 #define USBHS_EPFLUSH_FETB(x)                    USB_ENDPTFLUSH_FETB(x)
91201 #define USBHS_EPSR_ERBR_MASK                     USB_ENDPTSTAT_ERBR_MASK
91202 #define USBHS_EPSR_ERBR_SHIFT                    USB_ENDPTSTAT_ERBR_SHIFT
91203 #define USBHS_EPSR_ERBR(x)                       USB_ENDPTSTAT_ERBR(x)
91204 #define USBHS_EPSR_ETBR_MASK                     USB_ENDPTSTAT_ETBR_MASK
91205 #define USBHS_EPSR_ETBR_SHIFT                    USB_ENDPTSTAT_ETBR_SHIFT
91206 #define USBHS_EPSR_ETBR(x)                       USB_ENDPTSTAT_ETBR(x)
91207 #define USBHS_EPCOMPLETE_ERCE_MASK               USB_ENDPTCOMPLETE_ERCE_MASK
91208 #define USBHS_EPCOMPLETE_ERCE_SHIFT              USB_ENDPTCOMPLETE_ERCE_SHIFT
91209 #define USBHS_EPCOMPLETE_ERCE(x)                 USB_ENDPTCOMPLETE_ERCE(x)
91210 #define USBHS_EPCOMPLETE_ETCE_MASK               USB_ENDPTCOMPLETE_ETCE_MASK
91211 #define USBHS_EPCOMPLETE_ETCE_SHIFT              USB_ENDPTCOMPLETE_ETCE_SHIFT
91212 #define USBHS_EPCOMPLETE_ETCE(x)                 USB_ENDPTCOMPLETE_ETCE(x)
91213 #define USBHS_EPCR0_RXS_MASK                     USB_ENDPTCTRL0_RXS_MASK
91214 #define USBHS_EPCR0_RXS_SHIFT                    USB_ENDPTCTRL0_RXS_SHIFT
91215 #define USBHS_EPCR0_RXS(x)                       USB_ENDPTCTRL0_RXS(x)
91216 #define USBHS_EPCR0_RXT_MASK                     USB_ENDPTCTRL0_RXT_MASK
91217 #define USBHS_EPCR0_RXT_SHIFT                    USB_ENDPTCTRL0_RXT_SHIFT
91218 #define USBHS_EPCR0_RXT(x)                       USB_ENDPTCTRL0_RXT(x)
91219 #define USBHS_EPCR0_RXE_MASK                     USB_ENDPTCTRL0_RXE_MASK
91220 #define USBHS_EPCR0_RXE_SHIFT                    USB_ENDPTCTRL0_RXE_SHIFT
91221 #define USBHS_EPCR0_RXE(x)                       USB_ENDPTCTRL0_RXE(x)
91222 #define USBHS_EPCR0_TXS_MASK                     USB_ENDPTCTRL0_TXS_MASK
91223 #define USBHS_EPCR0_TXS_SHIFT                    USB_ENDPTCTRL0_TXS_SHIFT
91224 #define USBHS_EPCR0_TXS(x)                       USB_ENDPTCTRL0_TXS(x)
91225 #define USBHS_EPCR0_TXT_MASK                     USB_ENDPTCTRL0_TXT_MASK
91226 #define USBHS_EPCR0_TXT_SHIFT                    USB_ENDPTCTRL0_TXT_SHIFT
91227 #define USBHS_EPCR0_TXT(x)                       USB_ENDPTCTRL0_TXT(x)
91228 #define USBHS_EPCR0_TXE_MASK                     USB_ENDPTCTRL0_TXE_MASK
91229 #define USBHS_EPCR0_TXE_SHIFT                    USB_ENDPTCTRL0_TXE_SHIFT
91230 #define USBHS_EPCR0_TXE(x)                       USB_ENDPTCTRL0_TXE(x)
91231 #define USBHS_EPCR_RXS_MASK                      USB_ENDPTCTRL_RXS_MASK
91232 #define USBHS_EPCR_RXS_SHIFT                     USB_ENDPTCTRL_RXS_SHIFT
91233 #define USBHS_EPCR_RXS(x)                        USB_ENDPTCTRL_RXS(x)
91234 #define USBHS_EPCR_RXD_MASK                      USB_ENDPTCTRL_RXD_MASK
91235 #define USBHS_EPCR_RXD_SHIFT                     USB_ENDPTCTRL_RXD_SHIFT
91236 #define USBHS_EPCR_RXD(x)                        USB_ENDPTCTRL_RXD(x)
91237 #define USBHS_EPCR_RXT_MASK                      USB_ENDPTCTRL_RXT_MASK
91238 #define USBHS_EPCR_RXT_SHIFT                     USB_ENDPTCTRL_RXT_SHIFT
91239 #define USBHS_EPCR_RXT(x)                        USB_ENDPTCTRL_RXT(x)
91240 #define USBHS_EPCR_RXI_MASK                      USB_ENDPTCTRL_RXI_MASK
91241 #define USBHS_EPCR_RXI_SHIFT                     USB_ENDPTCTRL_RXI_SHIFT
91242 #define USBHS_EPCR_RXI(x)                        USB_ENDPTCTRL_RXI(x)
91243 #define USBHS_EPCR_RXR_MASK                      USB_ENDPTCTRL_RXR_MASK
91244 #define USBHS_EPCR_RXR_SHIFT                     USB_ENDPTCTRL_RXR_SHIFT
91245 #define USBHS_EPCR_RXR(x)                        USB_ENDPTCTRL_RXR(x)
91246 #define USBHS_EPCR_RXE_MASK                      USB_ENDPTCTRL_RXE_MASK
91247 #define USBHS_EPCR_RXE_SHIFT                     USB_ENDPTCTRL_RXE_SHIFT
91248 #define USBHS_EPCR_RXE(x)                        USB_ENDPTCTRL_RXE(x)
91249 #define USBHS_EPCR_TXS_MASK                      USB_ENDPTCTRL_TXS_MASK
91250 #define USBHS_EPCR_TXS_SHIFT                     USB_ENDPTCTRL_TXS_SHIFT
91251 #define USBHS_EPCR_TXS(x)                        USB_ENDPTCTRL_TXS(x)
91252 #define USBHS_EPCR_TXD_MASK                      USB_ENDPTCTRL_TXD_MASK
91253 #define USBHS_EPCR_TXD_SHIFT                     USB_ENDPTCTRL_TXD_SHIFT
91254 #define USBHS_EPCR_TXD(x)                        USB_ENDPTCTRL_TXD(x)
91255 #define USBHS_EPCR_TXT_MASK                      USB_ENDPTCTRL_TXT_MASK
91256 #define USBHS_EPCR_TXT_SHIFT                     USB_ENDPTCTRL_TXT_SHIFT
91257 #define USBHS_EPCR_TXT(x)                        USB_ENDPTCTRL_TXT(x)
91258 #define USBHS_EPCR_TXI_MASK                      USB_ENDPTCTRL_TXI_MASK
91259 #define USBHS_EPCR_TXI_SHIFT                     USB_ENDPTCTRL_TXI_SHIFT
91260 #define USBHS_EPCR_TXI(x)                        USB_ENDPTCTRL_TXI(x)
91261 #define USBHS_EPCR_TXR_MASK                      USB_ENDPTCTRL_TXR_MASK
91262 #define USBHS_EPCR_TXR_SHIFT                     USB_ENDPTCTRL_TXR_SHIFT
91263 #define USBHS_EPCR_TXR(x)                        USB_ENDPTCTRL_TXR(x)
91264 #define USBHS_EPCR_TXE_MASK                      USB_ENDPTCTRL_TXE_MASK
91265 #define USBHS_EPCR_TXE_SHIFT                     USB_ENDPTCTRL_TXE_SHIFT
91266 #define USBHS_EPCR_TXE(x)                        USB_ENDPTCTRL_TXE(x)
91267 #define USBHS_EPCR_COUNT                         USB_ENDPTCTRL_COUNT
91268 #define USBHS_Type                               USB_Type
91269 #define USBHS_BASE_ADDRS                         USB_BASE_ADDRS
91270 #define USBHS_IRQS                               { USB_OTG1_IRQn, USB_OTG2_IRQn }
91271 #define USBHS_IRQHandler                         USB_OTG1_IRQHandler
91272 #define USBHS_STACK_BASE_ADDRS                   { USB_OTG1_BASE, USB_OTG2_BASE }
91273 
91274 
91275 /*!
91276  * @}
91277  */ /* end of group USB_Peripheral_Access_Layer */
91278 
91279 
91280 /* ----------------------------------------------------------------------------
91281    -- USBHSDCD Peripheral Access Layer
91282    ---------------------------------------------------------------------------- */
91283 
91284 /*!
91285  * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer
91286  * @{
91287  */
91288 
91289 /** USBHSDCD - Register Layout Typedef */
91290 typedef struct {
91291   __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
91292   __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
91293   __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
91294   __IO uint32_t SIGNAL_OVERRIDE;                   /**< Signal Override Register, offset: 0xC */
91295   __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
91296   __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
91297   union {                                          /* offset: 0x18 */
91298     __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
91299     __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
91300   };
91301 } USBHSDCD_Type;
91302 
91303 /* ----------------------------------------------------------------------------
91304    -- USBHSDCD Register Masks
91305    ---------------------------------------------------------------------------- */
91306 
91307 /*!
91308  * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks
91309  * @{
91310  */
91311 
91312 /*! @name CONTROL - Control register */
91313 /*! @{ */
91314 
91315 #define USBHSDCD_CONTROL_IACK_MASK               (0x1U)
91316 #define USBHSDCD_CONTROL_IACK_SHIFT              (0U)
91317 /*! IACK - Interrupt Acknowledge
91318  *  0b0..Do not clear the interrupt.
91319  *  0b1..Clear the IF bit (interrupt flag).
91320  */
91321 #define USBHSDCD_CONTROL_IACK(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
91322 
91323 #define USBHSDCD_CONTROL_IF_MASK                 (0x100U)
91324 #define USBHSDCD_CONTROL_IF_SHIFT                (8U)
91325 /*! IF - Interrupt Flag
91326  *  0b0..No interrupt is pending.
91327  *  0b1..An interrupt is pending.
91328  */
91329 #define USBHSDCD_CONTROL_IF(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
91330 
91331 #define USBHSDCD_CONTROL_IE_MASK                 (0x10000U)
91332 #define USBHSDCD_CONTROL_IE_SHIFT                (16U)
91333 /*! IE - Interrupt Enable
91334  *  0b0..Disable interrupts to the system.
91335  *  0b1..Enable interrupts to the system.
91336  */
91337 #define USBHSDCD_CONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
91338 
91339 #define USBHSDCD_CONTROL_BC12_MASK               (0x20000U)
91340 #define USBHSDCD_CONTROL_BC12_SHIFT              (17U)
91341 /*! BC12 - BC12
91342  *  0b0..Compatible with BC1.1 (default)
91343  *  0b1..Compatible with BC1.2
91344  */
91345 #define USBHSDCD_CONTROL_BC12(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
91346 
91347 #define USBHSDCD_CONTROL_START_MASK              (0x1000000U)
91348 #define USBHSDCD_CONTROL_START_SHIFT             (24U)
91349 /*! START - Start Change Detection Sequence
91350  *  0b0..Do not start the sequence. Writes of this value have no effect.
91351  *  0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
91352  */
91353 #define USBHSDCD_CONTROL_START(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
91354 
91355 #define USBHSDCD_CONTROL_SR_MASK                 (0x2000000U)
91356 #define USBHSDCD_CONTROL_SR_SHIFT                (25U)
91357 /*! SR - Software Reset
91358  *  0b0..Do not perform a software reset.
91359  *  0b1..Perform a software reset.
91360  */
91361 #define USBHSDCD_CONTROL_SR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
91362 /*! @} */
91363 
91364 /*! @name CLOCK - Clock register */
91365 /*! @{ */
91366 
91367 #define USBHSDCD_CLOCK_CLOCK_UNIT_MASK           (0x1U)
91368 #define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT          (0U)
91369 /*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
91370  *  0b0..kHz Speed (between 1 kHz and 1023 kHz)
91371  *  0b1..MHz Speed (between 1 MHz and 1023 MHz)
91372  */
91373 #define USBHSDCD_CLOCK_CLOCK_UNIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
91374 
91375 #define USBHSDCD_CLOCK_CLOCK_SPEED_MASK          (0xFFCU)
91376 #define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT         (2U)
91377 /*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary */
91378 #define USBHSDCD_CLOCK_CLOCK_SPEED(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
91379 /*! @} */
91380 
91381 /*! @name STATUS - Status register */
91382 /*! @{ */
91383 
91384 #define USBHSDCD_STATUS_SEQ_RES_MASK             (0x30000U)
91385 #define USBHSDCD_STATUS_SEQ_RES_SHIFT            (16U)
91386 /*! SEQ_RES - Charger Detection Sequence Results
91387  *  0b00..No results to report.
91388  *  0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
91389  *  0b10..Attached to a charging port. The exact meaning depends on bit 18 (value 0: Attached to either a CDP or a
91390  *        DCP. The charger type detection has not completed. value 1: Attached to a CDP. The charger type
91391  *        detection has completed.)
91392  *  0b11..Attached to a DCP.
91393  */
91394 #define USBHSDCD_STATUS_SEQ_RES(x)               (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
91395 
91396 #define USBHSDCD_STATUS_SEQ_STAT_MASK            (0xC0000U)
91397 #define USBHSDCD_STATUS_SEQ_STAT_SHIFT           (18U)
91398 /*! SEQ_STAT - Charger Detection Sequence Status
91399  *  0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
91400  *  0b01..Data pin contact detection is complete.
91401  *  0b10..Charging port detection is complete.
91402  *  0b11..Charger type detection is complete.
91403  */
91404 #define USBHSDCD_STATUS_SEQ_STAT(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
91405 
91406 #define USBHSDCD_STATUS_ERR_MASK                 (0x100000U)
91407 #define USBHSDCD_STATUS_ERR_SHIFT                (20U)
91408 /*! ERR - Error Flag
91409  *  0b0..No sequence errors.
91410  *  0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.
91411  */
91412 #define USBHSDCD_STATUS_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
91413 
91414 #define USBHSDCD_STATUS_TO_MASK                  (0x200000U)
91415 #define USBHSDCD_STATUS_TO_SHIFT                 (21U)
91416 /*! TO - Timeout Flag
91417  *  0b0..The detection sequence has not been running for over 1s.
91418  *  0b1..It has been over 1 s since the data pin contact was detected and debounced.
91419  */
91420 #define USBHSDCD_STATUS_TO(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
91421 
91422 #define USBHSDCD_STATUS_ACTIVE_MASK              (0x400000U)
91423 #define USBHSDCD_STATUS_ACTIVE_SHIFT             (22U)
91424 /*! ACTIVE - Active Status Indicator
91425  *  0b0..The sequence is not running.
91426  *  0b1..The sequence is running.
91427  */
91428 #define USBHSDCD_STATUS_ACTIVE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
91429 /*! @} */
91430 
91431 /*! @name SIGNAL_OVERRIDE - Signal Override Register */
91432 /*! @{ */
91433 
91434 #define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK         (0x3U)
91435 #define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT        (0U)
91436 /*! PS - Phase Selection
91437  *  0b00..No overrides. Bit field must remain at this value during normal USB data communication to prevent
91438  *        unexpected conditions on USB_DP and USB_DM pins. (Default)
91439  *  0b01..Reserved, not for customer use.
91440  *  0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin.
91441  *  0b11..Reserved, not for customer use.
91442  */
91443 #define USBHSDCD_SIGNAL_OVERRIDE_PS(x)           (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
91444 /*! @} */
91445 
91446 /*! @name TIMER0 - TIMER0 register */
91447 /*! @{ */
91448 
91449 #define USBHSDCD_TIMER0_TUNITCON_MASK            (0xFFFU)
91450 #define USBHSDCD_TIMER0_TUNITCON_SHIFT           (0U)
91451 /*! TUNITCON - Unit Connection Timer Elapse (in ms) */
91452 #define USBHSDCD_TIMER0_TUNITCON(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
91453 
91454 #define USBHSDCD_TIMER0_TSEQ_INIT_MASK           (0x3FF0000U)
91455 #define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT          (16U)
91456 /*! TSEQ_INIT - Sequence Initiation Time
91457  *  0b0000000000-0b1111111111..0ms - 1023ms
91458  */
91459 #define USBHSDCD_TIMER0_TSEQ_INIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
91460 /*! @} */
91461 
91462 /*! @name TIMER1 - TIMER1 register */
91463 /*! @{ */
91464 
91465 #define USBHSDCD_TIMER1_TVDPSRC_ON_MASK          (0x3FFU)
91466 #define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT         (0U)
91467 /*! TVDPSRC_ON - Time Period Comparator Enabled
91468  *  0b0000000001-0b1111111111..1ms - 1023ms
91469  */
91470 #define USBHSDCD_TIMER1_TVDPSRC_ON(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
91471 
91472 #define USBHSDCD_TIMER1_TDCD_DBNC_MASK           (0x3FF0000U)
91473 #define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT          (16U)
91474 /*! TDCD_DBNC - Time Period to Debounce D+ Signal
91475  *  0b0000000001-0b1111111111..1ms - 1023ms
91476  */
91477 #define USBHSDCD_TIMER1_TDCD_DBNC(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
91478 /*! @} */
91479 
91480 /*! @name TIMER2_BC11 - TIMER2_BC11 register */
91481 /*! @{ */
91482 
91483 #define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK       (0xFU)
91484 #define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT      (0U)
91485 /*! CHECK_DM - Time Before Check of D- Line
91486  *  0b0001-0b1111..1ms - 15ms
91487  */
91488 #define USBHSDCD_TIMER2_BC11_CHECK_DM(x)         (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
91489 
91490 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK    (0x3FF0000U)
91491 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT   (16U)
91492 /*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup
91493  *  0b0000000001-0b1111111111..1ms - 1023ms
91494  */
91495 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x)      (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
91496 /*! @} */
91497 
91498 /*! @name TIMER2_BC12 - TIMER2_BC12 register */
91499 /*! @{ */
91500 
91501 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK     (0x3FFU)
91502 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT    (0U)
91503 /*! TVDMSRC_ON - TVDMSRC_ON
91504  *  0b0000000000-0b0000101000..0ms - 40ms
91505  */
91506 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x)       (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
91507 
91508 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
91509 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
91510 /*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD
91511  *  0b0000000001-0b1111111111..1ms - 1023ms
91512  */
91513 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)  (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
91514 /*! @} */
91515 
91516 
91517 /*!
91518  * @}
91519  */ /* end of group USBHSDCD_Register_Masks */
91520 
91521 
91522 /* USBHSDCD - Peripheral instance base addresses */
91523 /** Peripheral USBHSDCD1 base address */
91524 #define USBHSDCD1_BASE                           (0x40434800u)
91525 /** Peripheral USBHSDCD1 base pointer */
91526 #define USBHSDCD1                                ((USBHSDCD_Type *)USBHSDCD1_BASE)
91527 /** Peripheral USBHSDCD2 base address */
91528 #define USBHSDCD2_BASE                           (0x40438800u)
91529 /** Peripheral USBHSDCD2 base pointer */
91530 #define USBHSDCD2                                ((USBHSDCD_Type *)USBHSDCD2_BASE)
91531 /** Array initializer of USBHSDCD peripheral base addresses */
91532 #define USBHSDCD_BASE_ADDRS                      { 0u, USBHSDCD1_BASE, USBHSDCD2_BASE }
91533 /** Array initializer of USBHSDCD peripheral base pointers */
91534 #define USBHSDCD_BASE_PTRS                       { (USBHSDCD_Type *)0u, USBHSDCD1, USBHSDCD2 }
91535 /* Backward compatibility */
91536 #define USBHSDCD_STACK_BASE_ADDRS                { USBHSDCD1_BASE, USBHSDCD2_BASE }
91537 
91538 
91539 /*!
91540  * @}
91541  */ /* end of group USBHSDCD_Peripheral_Access_Layer */
91542 
91543 
91544 /* ----------------------------------------------------------------------------
91545    -- USBNC Peripheral Access Layer
91546    ---------------------------------------------------------------------------- */
91547 
91548 /*!
91549  * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer
91550  * @{
91551  */
91552 
91553 /** USBNC - Register Layout Typedef */
91554 typedef struct {
91555   __IO uint32_t CTRL1;                             /**< USB OTG Control 1 Register, offset: 0x0 */
91556   __IO uint32_t CTRL2;                             /**< USB OTG Control 2 Register, offset: 0x4 */
91557        uint8_t RESERVED_0[8];
91558   __IO uint32_t HSIC_CTRL;                         /**< USB Host HSIC Control Register, offset: 0x10 */
91559 } USBNC_Type;
91560 
91561 /* ----------------------------------------------------------------------------
91562    -- USBNC Register Masks
91563    ---------------------------------------------------------------------------- */
91564 
91565 /*!
91566  * @addtogroup USBNC_Register_Masks USBNC Register Masks
91567  * @{
91568  */
91569 
91570 /*! @name CTRL1 - USB OTG Control 1 Register */
91571 /*! @{ */
91572 
91573 #define USBNC_CTRL1_OVER_CUR_DIS_MASK            (0x80U)
91574 #define USBNC_CTRL1_OVER_CUR_DIS_SHIFT           (7U)
91575 /*! OVER_CUR_DIS - OVER_CUR_DIS
91576  *  0b1..Disables overcurrent detection
91577  *  0b0..Enables overcurrent detection
91578  */
91579 #define USBNC_CTRL1_OVER_CUR_DIS(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK)
91580 
91581 #define USBNC_CTRL1_OVER_CUR_POL_MASK            (0x100U)
91582 #define USBNC_CTRL1_OVER_CUR_POL_SHIFT           (8U)
91583 /*! OVER_CUR_POL - OVER_CUR_POL
91584  *  0b1..Low active (low on this signal represents an overcurrent condition)
91585  *  0b0..High active (high on this signal represents an overcurrent condition)
91586  */
91587 #define USBNC_CTRL1_OVER_CUR_POL(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK)
91588 
91589 #define USBNC_CTRL1_PWR_POL_MASK                 (0x200U)
91590 #define USBNC_CTRL1_PWR_POL_SHIFT                (9U)
91591 /*! PWR_POL - PWR_POL
91592  *  0b1..PMIC Power Pin is High active.
91593  *  0b0..PMIC Power Pin is Low active.
91594  */
91595 #define USBNC_CTRL1_PWR_POL(x)                   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK)
91596 
91597 #define USBNC_CTRL1_WIE_MASK                     (0x400U)
91598 #define USBNC_CTRL1_WIE_SHIFT                    (10U)
91599 /*! WIE - WIE
91600  *  0b1..Interrupt Enabled
91601  *  0b0..Interrupt Disabled
91602  */
91603 #define USBNC_CTRL1_WIE(x)                       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK)
91604 
91605 #define USBNC_CTRL1_WKUP_SW_EN_MASK              (0x4000U)
91606 #define USBNC_CTRL1_WKUP_SW_EN_SHIFT             (14U)
91607 /*! WKUP_SW_EN - WKUP_SW_EN
91608  *  0b1..Enable
91609  *  0b0..Disable
91610  */
91611 #define USBNC_CTRL1_WKUP_SW_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK)
91612 
91613 #define USBNC_CTRL1_WKUP_SW_MASK                 (0x8000U)
91614 #define USBNC_CTRL1_WKUP_SW_SHIFT                (15U)
91615 /*! WKUP_SW - WKUP_SW
91616  *  0b1..Force wake-up
91617  *  0b0..Inactive
91618  */
91619 #define USBNC_CTRL1_WKUP_SW(x)                   (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK)
91620 
91621 #define USBNC_CTRL1_WKUP_ID_EN_MASK              (0x10000U)
91622 #define USBNC_CTRL1_WKUP_ID_EN_SHIFT             (16U)
91623 /*! WKUP_ID_EN - WKUP_ID_EN
91624  *  0b1..Enable
91625  *  0b0..Disable
91626  */
91627 #define USBNC_CTRL1_WKUP_ID_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK)
91628 
91629 #define USBNC_CTRL1_WKUP_VBUS_EN_MASK            (0x20000U)
91630 #define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT           (17U)
91631 /*! WKUP_VBUS_EN - WKUP_VBUS_EN
91632  *  0b1..Enable
91633  *  0b0..Disable
91634  */
91635 #define USBNC_CTRL1_WKUP_VBUS_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK)
91636 
91637 #define USBNC_CTRL1_WKUP_DPDM_EN_MASK            (0x20000000U)
91638 #define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT           (29U)
91639 /*! WKUP_DPDM_EN - Wake-up on DPDM change enable
91640  *  0b1..(Default) DPDM changes wake-up to be enabled, it is for device only.
91641  *  0b0..DPDM changes wake-up to be disabled only when VBUS is 0.
91642  */
91643 #define USBNC_CTRL1_WKUP_DPDM_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK)
91644 
91645 #define USBNC_CTRL1_WIR_MASK                     (0x80000000U)
91646 #define USBNC_CTRL1_WIR_SHIFT                    (31U)
91647 /*! WIR - WIR
91648  *  0b1..Wake-up Interrupt Request received
91649  *  0b0..No wake-up interrupt request received
91650  */
91651 #define USBNC_CTRL1_WIR(x)                       (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK)
91652 /*! @} */
91653 
91654 /*! @name CTRL2 - USB OTG Control 2 Register */
91655 /*! @{ */
91656 
91657 #define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK         (0x3U)
91658 #define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT        (0U)
91659 /*! VBUS_SOURCE_SEL - VBUS_SOURCE_SEL
91660  *  0b00..vbus_valid
91661  *  0b01..sess_valid
91662  *  0b10..sess_valid
91663  *  0b11..sess_valid
91664  */
91665 #define USBNC_CTRL2_VBUS_SOURCE_SEL(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK)
91666 
91667 #define USBNC_CTRL2_AUTURESUME_EN_MASK           (0x4U)
91668 #define USBNC_CTRL2_AUTURESUME_EN_SHIFT          (2U)
91669 /*! AUTURESUME_EN - Auto Resume Enable
91670  *  0b0..Default
91671  */
91672 #define USBNC_CTRL2_AUTURESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK)
91673 
91674 #define USBNC_CTRL2_LOWSPEED_EN_MASK             (0x8U)
91675 #define USBNC_CTRL2_LOWSPEED_EN_SHIFT            (3U)
91676 /*! LOWSPEED_EN - LOWSPEED_EN
91677  *  0b0..Default
91678  */
91679 #define USBNC_CTRL2_LOWSPEED_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK)
91680 
91681 #define USBNC_CTRL2_UTMI_CLK_VLD_MASK            (0x80000000U)
91682 #define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT           (31U)
91683 /*! UTMI_CLK_VLD - UTMI_CLK_VLD
91684  *  0b0..Default
91685  */
91686 #define USBNC_CTRL2_UTMI_CLK_VLD(x)              (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK)
91687 /*! @} */
91688 
91689 /*! @name HSIC_CTRL - USB Host HSIC Control Register */
91690 /*! @{ */
91691 
91692 #define USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK         (0x800U)
91693 #define USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT        (11U)
91694 /*! HSIC_CLK_ON - HSIC_CLK_ON
91695  *  0b1..Active
91696  *  0b0..Inactive
91697  */
91698 #define USBNC_HSIC_CTRL_HSIC_CLK_ON(x)           (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK)
91699 
91700 #define USBNC_HSIC_CTRL_HSIC_EN_MASK             (0x1000U)
91701 #define USBNC_HSIC_CTRL_HSIC_EN_SHIFT            (12U)
91702 /*! HSIC_EN - HSIC_EN
91703  *  0b1..Enabled
91704  *  0b0..Disabled
91705  */
91706 #define USBNC_HSIC_CTRL_HSIC_EN(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK)
91707 
91708 #define USBNC_HSIC_CTRL_CLK_VLD_MASK             (0x80000000U)
91709 #define USBNC_HSIC_CTRL_CLK_VLD_SHIFT            (31U)
91710 /*! CLK_VLD - CLK_VLD
91711  *  0b1..Valid
91712  *  0b0..Invalid
91713  */
91714 #define USBNC_HSIC_CTRL_CLK_VLD(x)               (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK)
91715 /*! @} */
91716 
91717 
91718 /*!
91719  * @}
91720  */ /* end of group USBNC_Register_Masks */
91721 
91722 
91723 /* USBNC - Peripheral instance base addresses */
91724 /** Peripheral USBNC_OTG1 base address */
91725 #define USBNC_OTG1_BASE                          (0x40430200u)
91726 /** Peripheral USBNC_OTG1 base pointer */
91727 #define USBNC_OTG1                               ((USBNC_Type *)USBNC_OTG1_BASE)
91728 /** Peripheral USBNC_OTG2 base address */
91729 #define USBNC_OTG2_BASE                          (0x4042C200u)
91730 /** Peripheral USBNC_OTG2 base pointer */
91731 #define USBNC_OTG2                               ((USBNC_Type *)USBNC_OTG2_BASE)
91732 /** Array initializer of USBNC peripheral base addresses */
91733 #define USBNC_BASE_ADDRS                         { 0u, USBNC_OTG1_BASE, USBNC_OTG2_BASE }
91734 /** Array initializer of USBNC peripheral base pointers */
91735 #define USBNC_BASE_PTRS                          { (USBNC_Type *)0u, USBNC_OTG1, USBNC_OTG2 }
91736 /* Backward compatibility */
91737 #define USB_OTGn_CTRL     CTRL1
91738 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK     USBNC_CTRL1_OVER_CUR_DIS_MASK
91739 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT     USBNC_CTRL1_OVER_CUR_DIS_SHIFT
91740 #define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x)     USBNC_CTRL1_OVER_CUR_DIS(x)
91741 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK     USBNC_CTRL1_OVER_CUR_POL_MASK
91742 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT     USBNC_CTRL1_OVER_CUR_POL_SHIFT
91743 #define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x)     USBNC_CTRL1_OVER_CUR_POL(x)
91744 #define USBNC_USB_OTGn_CTRL_PWR_POL_MASK     USBNC_CTRL1_PWR_POL_MASK
91745 #define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT     USBNC_CTRL1_PWR_POL_SHIFT
91746 #define USBNC_USB_OTGn_CTRL_PWR_POL(x)     USBNC_CTRL1_PWR_POL(x)
91747 #define USBNC_USB_OTGn_CTRL_WIE_MASK     USBNC_CTRL1_WIE_MASK
91748 #define USBNC_USB_OTGn_CTRL_WIE_SHIFT     USBNC_CTRL1_WIE_SHIFT
91749 #define USBNC_USB_OTGn_CTRL_WIE(x)     USBNC_CTRL1_WIE(x)
91750 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK     USBNC_CTRL1_WKUP_SW_EN_MASK
91751 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT     USBNC_CTRL1_WKUP_SW_EN_SHIFT
91752 #define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x)     USBNC_CTRL1_WKUP_SW_EN(x)
91753 #define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK     USBNC_CTRL1_WKUP_SW_MASK
91754 #define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT     USBNC_CTRL1_WKUP_SW_SHIFT
91755 #define USBNC_USB_OTGn_CTRL_WKUP_SW(x)     USBNC_CTRL1_WKUP_SW(x)
91756 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK     USBNC_CTRL1_WKUP_ID_EN_MASK
91757 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT     USBNC_CTRL1_WKUP_ID_EN_SHIFT
91758 #define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x)     USBNC_CTRL1_WKUP_ID_EN(x)
91759 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK     USBNC_CTRL1_WKUP_VBUS_EN_MASK
91760 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT     USBNC_CTRL1_WKUP_VBUS_EN_SHIFT
91761 #define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x)     USBNC_CTRL1_WKUP_VBUS_EN(x)
91762 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK     USBNC_CTRL1_WKUP_DPDM_EN_MASK
91763 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT     USBNC_CTRL1_WKUP_DPDM_EN_SHIFT
91764 #define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x)     USBNC_CTRL1_WKUP_DPDM_EN(x)
91765 #define USBNC_USB_OTGn_CTRL_WIR_MASK     USBNC_CTRL1_WIR_MASK
91766 #define USBNC_USB_OTGn_CTRL_WIR_SHIFT     USBNC_CTRL1_WIR_SHIFT
91767 #define USBNC_USB_OTGn_CTRL_WIR(x)     USBNC_CTRL1_WIR(x)
91768 #define USBNC_STACK_BASE_ADDRS                { USBNC_OTG1_BASE, USBNC_OTG2_BASE }
91769 
91770 
91771 /*!
91772  * @}
91773  */ /* end of group USBNC_Peripheral_Access_Layer */
91774 
91775 
91776 /* ----------------------------------------------------------------------------
91777    -- USBPHY Peripheral Access Layer
91778    ---------------------------------------------------------------------------- */
91779 
91780 /*!
91781  * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
91782  * @{
91783  */
91784 
91785 /** USBPHY - Register Layout Typedef */
91786 typedef struct {
91787   __IO uint32_t PWD;                               /**< USB PHY Power-Down Register, offset: 0x0 */
91788   __IO uint32_t PWD_SET;                           /**< USB PHY Power-Down Register, offset: 0x4 */
91789   __IO uint32_t PWD_CLR;                           /**< USB PHY Power-Down Register, offset: 0x8 */
91790   __IO uint32_t PWD_TOG;                           /**< USB PHY Power-Down Register, offset: 0xC */
91791   __IO uint32_t TX;                                /**< USB PHY Transmitter Control Register, offset: 0x10 */
91792   __IO uint32_t TX_SET;                            /**< USB PHY Transmitter Control Register, offset: 0x14 */
91793   __IO uint32_t TX_CLR;                            /**< USB PHY Transmitter Control Register, offset: 0x18 */
91794   __IO uint32_t TX_TOG;                            /**< USB PHY Transmitter Control Register, offset: 0x1C */
91795   __IO uint32_t RX;                                /**< USB PHY Receiver Control Register, offset: 0x20 */
91796   __IO uint32_t RX_SET;                            /**< USB PHY Receiver Control Register, offset: 0x24 */
91797   __IO uint32_t RX_CLR;                            /**< USB PHY Receiver Control Register, offset: 0x28 */
91798   __IO uint32_t RX_TOG;                            /**< USB PHY Receiver Control Register, offset: 0x2C */
91799   __IO uint32_t CTRL;                              /**< USB PHY General Control Register, offset: 0x30 */
91800   __IO uint32_t CTRL_SET;                          /**< USB PHY General Control Register, offset: 0x34 */
91801   __IO uint32_t CTRL_CLR;                          /**< USB PHY General Control Register, offset: 0x38 */
91802   __IO uint32_t CTRL_TOG;                          /**< USB PHY General Control Register, offset: 0x3C */
91803   __IO uint32_t STATUS;                            /**< USB PHY Status Register, offset: 0x40 */
91804        uint8_t RESERVED_0[12];
91805   __IO uint32_t DEBUGr;                            /**< USB PHY Debug Register, offset: 0x50, 'r' suffix has been added to avoid clash with DEBUG symbolic constant */
91806   __IO uint32_t DEBUG_SET;                         /**< USB PHY Debug Register, offset: 0x54 */
91807   __IO uint32_t DEBUG_CLR;                         /**< USB PHY Debug Register, offset: 0x58 */
91808   __IO uint32_t DEBUG_TOG;                         /**< USB PHY Debug Register, offset: 0x5C */
91809   __I  uint32_t DEBUG0_STATUS;                     /**< UTMI Debug Status Register 0, offset: 0x60 */
91810        uint8_t RESERVED_1[12];
91811   __IO uint32_t DEBUG1;                            /**< UTMI Debug Status Register 1, offset: 0x70 */
91812   __IO uint32_t DEBUG1_SET;                        /**< UTMI Debug Status Register 1, offset: 0x74 */
91813   __IO uint32_t DEBUG1_CLR;                        /**< UTMI Debug Status Register 1, offset: 0x78 */
91814   __IO uint32_t DEBUG1_TOG;                        /**< UTMI Debug Status Register 1, offset: 0x7C */
91815   __I  uint32_t VERSION;                           /**< UTMI RTL Version, offset: 0x80 */
91816        uint8_t RESERVED_2[28];
91817   __IO uint32_t PLL_SIC;                           /**< USB PHY PLL Control/Status Register, offset: 0xA0 */
91818   __IO uint32_t PLL_SIC_SET;                       /**< USB PHY PLL Control/Status Register, offset: 0xA4 */
91819   __IO uint32_t PLL_SIC_CLR;                       /**< USB PHY PLL Control/Status Register, offset: 0xA8 */
91820   __IO uint32_t PLL_SIC_TOG;                       /**< USB PHY PLL Control/Status Register, offset: 0xAC */
91821        uint8_t RESERVED_3[16];
91822   __IO uint32_t USB1_VBUS_DETECT;                  /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */
91823   __IO uint32_t USB1_VBUS_DETECT_SET;              /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */
91824   __IO uint32_t USB1_VBUS_DETECT_CLR;              /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */
91825   __IO uint32_t USB1_VBUS_DETECT_TOG;              /**< USB PHY VBUS Detect Control Register, offset: 0xCC */
91826   __I  uint32_t USB1_VBUS_DET_STAT;                /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */
91827        uint8_t RESERVED_4[12];
91828   __IO uint32_t USB1_CHRG_DETECT;                  /**< USB PHY Charger Detect Control Register, offset: 0xE0 */
91829   __IO uint32_t USB1_CHRG_DETECT_SET;              /**< USB PHY Charger Detect Control Register, offset: 0xE4 */
91830   __IO uint32_t USB1_CHRG_DETECT_CLR;              /**< USB PHY Charger Detect Control Register, offset: 0xE8 */
91831   __IO uint32_t USB1_CHRG_DETECT_TOG;              /**< USB PHY Charger Detect Control Register, offset: 0xEC */
91832   __I  uint32_t USB1_CHRG_DET_STAT;                /**< USB PHY Charger Detect Status Register, offset: 0xF0 */
91833        uint8_t RESERVED_5[12];
91834   __IO uint32_t ANACTRL;                           /**< USB PHY Analog Control Register, offset: 0x100 */
91835   __IO uint32_t ANACTRL_SET;                       /**< USB PHY Analog Control Register, offset: 0x104 */
91836   __IO uint32_t ANACTRL_CLR;                       /**< USB PHY Analog Control Register, offset: 0x108 */
91837   __IO uint32_t ANACTRL_TOG;                       /**< USB PHY Analog Control Register, offset: 0x10C */
91838   __IO uint32_t USB1_LOOPBACK;                     /**< USB PHY Loopback Control/Status Register, offset: 0x110 */
91839   __IO uint32_t USB1_LOOPBACK_SET;                 /**< USB PHY Loopback Control/Status Register, offset: 0x114 */
91840   __IO uint32_t USB1_LOOPBACK_CLR;                 /**< USB PHY Loopback Control/Status Register, offset: 0x118 */
91841   __IO uint32_t USB1_LOOPBACK_TOG;                 /**< USB PHY Loopback Control/Status Register, offset: 0x11C */
91842   __IO uint32_t USB1_LOOPBACK_HSFSCNT;             /**< USB PHY Loopback Packet Number Select Register, offset: 0x120 */
91843   __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x124 */
91844   __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x128 */
91845   __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x12C */
91846   __IO uint32_t TRIM_OVERRIDE_EN;                  /**< USB PHY Trim Override Enable Register, offset: 0x130 */
91847   __IO uint32_t TRIM_OVERRIDE_EN_SET;              /**< USB PHY Trim Override Enable Register, offset: 0x134 */
91848   __IO uint32_t TRIM_OVERRIDE_EN_CLR;              /**< USB PHY Trim Override Enable Register, offset: 0x138 */
91849   __IO uint32_t TRIM_OVERRIDE_EN_TOG;              /**< USB PHY Trim Override Enable Register, offset: 0x13C */
91850 } USBPHY_Type;
91851 
91852 /* ----------------------------------------------------------------------------
91853    -- USBPHY Register Masks
91854    ---------------------------------------------------------------------------- */
91855 
91856 /*!
91857  * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
91858  * @{
91859  */
91860 
91861 /*! @name PWD - USB PHY Power-Down Register */
91862 /*! @{ */
91863 
91864 #define USBPHY_PWD_TXPWDFS_MASK                  (0x400U)
91865 #define USBPHY_PWD_TXPWDFS_SHIFT                 (10U)
91866 /*! TXPWDFS - TXPWDFS
91867  *  0b0..Normal operation.
91868  *  0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
91869  */
91870 #define USBPHY_PWD_TXPWDFS(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
91871 
91872 #define USBPHY_PWD_TXPWDIBIAS_MASK               (0x800U)
91873 #define USBPHY_PWD_TXPWDIBIAS_SHIFT              (11U)
91874 /*! TXPWDIBIAS - TXPWDIBIAS
91875  *  0b0..Normal operation
91876  *  0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB
91877  *       is in suspend mode. This effectively powers down the entire USB transmit path
91878  */
91879 #define USBPHY_PWD_TXPWDIBIAS(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
91880 
91881 #define USBPHY_PWD_TXPWDV2I_MASK                 (0x1000U)
91882 #define USBPHY_PWD_TXPWDV2I_SHIFT                (12U)
91883 /*! TXPWDV2I - TXPWDV2I
91884  *  0b0..Normal operation.
91885  *  0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
91886  */
91887 #define USBPHY_PWD_TXPWDV2I(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
91888 
91889 #define USBPHY_PWD_RXPWDENV_MASK                 (0x20000U)
91890 #define USBPHY_PWD_RXPWDENV_SHIFT                (17U)
91891 /*! RXPWDENV - RXPWDENV
91892  *  0b0..Normal operation.
91893  *  0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
91894  */
91895 #define USBPHY_PWD_RXPWDENV(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
91896 
91897 #define USBPHY_PWD_RXPWD1PT1_MASK                (0x40000U)
91898 #define USBPHY_PWD_RXPWD1PT1_SHIFT               (18U)
91899 /*! RXPWD1PT1 - RXPWD1PT1
91900  *  0b0..Normal operation
91901  *  0b1..Power-down the USB full-speed differential receiver.
91902  */
91903 #define USBPHY_PWD_RXPWD1PT1(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
91904 
91905 #define USBPHY_PWD_RXPWDDIFF_MASK                (0x80000U)
91906 #define USBPHY_PWD_RXPWDDIFF_SHIFT               (19U)
91907 /*! RXPWDDIFF - RXPWDDIFF
91908  *  0b0..Normal operation.
91909  *  0b1..Power-down the USB high-speed differential receiver
91910  */
91911 #define USBPHY_PWD_RXPWDDIFF(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
91912 
91913 #define USBPHY_PWD_RXPWDRX_MASK                  (0x100000U)
91914 #define USBPHY_PWD_RXPWDRX_SHIFT                 (20U)
91915 /*! RXPWDRX - RXPWDRX
91916  *  0b0..Normal operation
91917  *  0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
91918  */
91919 #define USBPHY_PWD_RXPWDRX(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
91920 /*! @} */
91921 
91922 /*! @name PWD_SET - USB PHY Power-Down Register */
91923 /*! @{ */
91924 
91925 #define USBPHY_PWD_SET_TXPWDFS_MASK              (0x400U)
91926 #define USBPHY_PWD_SET_TXPWDFS_SHIFT             (10U)
91927 /*! TXPWDFS - TXPWDFS */
91928 #define USBPHY_PWD_SET_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
91929 
91930 #define USBPHY_PWD_SET_TXPWDIBIAS_MASK           (0x800U)
91931 #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT          (11U)
91932 /*! TXPWDIBIAS - TXPWDIBIAS */
91933 #define USBPHY_PWD_SET_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
91934 
91935 #define USBPHY_PWD_SET_TXPWDV2I_MASK             (0x1000U)
91936 #define USBPHY_PWD_SET_TXPWDV2I_SHIFT            (12U)
91937 /*! TXPWDV2I - TXPWDV2I */
91938 #define USBPHY_PWD_SET_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
91939 
91940 #define USBPHY_PWD_SET_RXPWDENV_MASK             (0x20000U)
91941 #define USBPHY_PWD_SET_RXPWDENV_SHIFT            (17U)
91942 /*! RXPWDENV - RXPWDENV */
91943 #define USBPHY_PWD_SET_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
91944 
91945 #define USBPHY_PWD_SET_RXPWD1PT1_MASK            (0x40000U)
91946 #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT           (18U)
91947 /*! RXPWD1PT1 - RXPWD1PT1 */
91948 #define USBPHY_PWD_SET_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
91949 
91950 #define USBPHY_PWD_SET_RXPWDDIFF_MASK            (0x80000U)
91951 #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT           (19U)
91952 /*! RXPWDDIFF - RXPWDDIFF */
91953 #define USBPHY_PWD_SET_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
91954 
91955 #define USBPHY_PWD_SET_RXPWDRX_MASK              (0x100000U)
91956 #define USBPHY_PWD_SET_RXPWDRX_SHIFT             (20U)
91957 /*! RXPWDRX - RXPWDRX */
91958 #define USBPHY_PWD_SET_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
91959 /*! @} */
91960 
91961 /*! @name PWD_CLR - USB PHY Power-Down Register */
91962 /*! @{ */
91963 
91964 #define USBPHY_PWD_CLR_TXPWDFS_MASK              (0x400U)
91965 #define USBPHY_PWD_CLR_TXPWDFS_SHIFT             (10U)
91966 /*! TXPWDFS - TXPWDFS */
91967 #define USBPHY_PWD_CLR_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
91968 
91969 #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK           (0x800U)
91970 #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT          (11U)
91971 /*! TXPWDIBIAS - TXPWDIBIAS */
91972 #define USBPHY_PWD_CLR_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
91973 
91974 #define USBPHY_PWD_CLR_TXPWDV2I_MASK             (0x1000U)
91975 #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT            (12U)
91976 /*! TXPWDV2I - TXPWDV2I */
91977 #define USBPHY_PWD_CLR_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
91978 
91979 #define USBPHY_PWD_CLR_RXPWDENV_MASK             (0x20000U)
91980 #define USBPHY_PWD_CLR_RXPWDENV_SHIFT            (17U)
91981 /*! RXPWDENV - RXPWDENV */
91982 #define USBPHY_PWD_CLR_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
91983 
91984 #define USBPHY_PWD_CLR_RXPWD1PT1_MASK            (0x40000U)
91985 #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT           (18U)
91986 /*! RXPWD1PT1 - RXPWD1PT1 */
91987 #define USBPHY_PWD_CLR_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
91988 
91989 #define USBPHY_PWD_CLR_RXPWDDIFF_MASK            (0x80000U)
91990 #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT           (19U)
91991 /*! RXPWDDIFF - RXPWDDIFF */
91992 #define USBPHY_PWD_CLR_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
91993 
91994 #define USBPHY_PWD_CLR_RXPWDRX_MASK              (0x100000U)
91995 #define USBPHY_PWD_CLR_RXPWDRX_SHIFT             (20U)
91996 /*! RXPWDRX - RXPWDRX */
91997 #define USBPHY_PWD_CLR_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
91998 /*! @} */
91999 
92000 /*! @name PWD_TOG - USB PHY Power-Down Register */
92001 /*! @{ */
92002 
92003 #define USBPHY_PWD_TOG_TXPWDFS_MASK              (0x400U)
92004 #define USBPHY_PWD_TOG_TXPWDFS_SHIFT             (10U)
92005 /*! TXPWDFS - TXPWDFS */
92006 #define USBPHY_PWD_TOG_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
92007 
92008 #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK           (0x800U)
92009 #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT          (11U)
92010 /*! TXPWDIBIAS - TXPWDIBIAS */
92011 #define USBPHY_PWD_TOG_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
92012 
92013 #define USBPHY_PWD_TOG_TXPWDV2I_MASK             (0x1000U)
92014 #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT            (12U)
92015 /*! TXPWDV2I - TXPWDV2I */
92016 #define USBPHY_PWD_TOG_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
92017 
92018 #define USBPHY_PWD_TOG_RXPWDENV_MASK             (0x20000U)
92019 #define USBPHY_PWD_TOG_RXPWDENV_SHIFT            (17U)
92020 /*! RXPWDENV - RXPWDENV */
92021 #define USBPHY_PWD_TOG_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
92022 
92023 #define USBPHY_PWD_TOG_RXPWD1PT1_MASK            (0x40000U)
92024 #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT           (18U)
92025 /*! RXPWD1PT1 - RXPWD1PT1 */
92026 #define USBPHY_PWD_TOG_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
92027 
92028 #define USBPHY_PWD_TOG_RXPWDDIFF_MASK            (0x80000U)
92029 #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT           (19U)
92030 /*! RXPWDDIFF - RXPWDDIFF */
92031 #define USBPHY_PWD_TOG_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
92032 
92033 #define USBPHY_PWD_TOG_RXPWDRX_MASK              (0x100000U)
92034 #define USBPHY_PWD_TOG_RXPWDRX_SHIFT             (20U)
92035 /*! RXPWDRX - RXPWDRX */
92036 #define USBPHY_PWD_TOG_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
92037 /*! @} */
92038 
92039 /*! @name TX - USB PHY Transmitter Control Register */
92040 /*! @{ */
92041 
92042 #define USBPHY_TX_D_CAL_MASK                     (0xFU)
92043 #define USBPHY_TX_D_CAL_SHIFT                    (0U)
92044 /*! D_CAL - D_CAL
92045  *  0b0000..Maximum current, approximately 19% above nominal.
92046  *  0b0111..Nominal
92047  *  0b1111..Minimum current, approximately 19% below nominal.
92048  */
92049 #define USBPHY_TX_D_CAL(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
92050 
92051 #define USBPHY_TX_TXCAL45DN_MASK                 (0xF00U)
92052 #define USBPHY_TX_TXCAL45DN_SHIFT                (8U)
92053 /*! TXCAL45DN - TXCAL45DN */
92054 #define USBPHY_TX_TXCAL45DN(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)
92055 
92056 #define USBPHY_TX_TXCAL45DP_MASK                 (0xF0000U)
92057 #define USBPHY_TX_TXCAL45DP_SHIFT                (16U)
92058 /*! TXCAL45DP - TXCAL45DP */
92059 #define USBPHY_TX_TXCAL45DP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
92060 /*! @} */
92061 
92062 /*! @name TX_SET - USB PHY Transmitter Control Register */
92063 /*! @{ */
92064 
92065 #define USBPHY_TX_SET_D_CAL_MASK                 (0xFU)
92066 #define USBPHY_TX_SET_D_CAL_SHIFT                (0U)
92067 /*! D_CAL - D_CAL */
92068 #define USBPHY_TX_SET_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
92069 
92070 #define USBPHY_TX_SET_TXCAL45DN_MASK             (0xF00U)
92071 #define USBPHY_TX_SET_TXCAL45DN_SHIFT            (8U)
92072 /*! TXCAL45DN - TXCAL45DN */
92073 #define USBPHY_TX_SET_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)
92074 
92075 #define USBPHY_TX_SET_TXCAL45DP_MASK             (0xF0000U)
92076 #define USBPHY_TX_SET_TXCAL45DP_SHIFT            (16U)
92077 /*! TXCAL45DP - TXCAL45DP */
92078 #define USBPHY_TX_SET_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
92079 /*! @} */
92080 
92081 /*! @name TX_CLR - USB PHY Transmitter Control Register */
92082 /*! @{ */
92083 
92084 #define USBPHY_TX_CLR_D_CAL_MASK                 (0xFU)
92085 #define USBPHY_TX_CLR_D_CAL_SHIFT                (0U)
92086 /*! D_CAL - D_CAL */
92087 #define USBPHY_TX_CLR_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
92088 
92089 #define USBPHY_TX_CLR_TXCAL45DN_MASK             (0xF00U)
92090 #define USBPHY_TX_CLR_TXCAL45DN_SHIFT            (8U)
92091 /*! TXCAL45DN - TXCAL45DN */
92092 #define USBPHY_TX_CLR_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)
92093 
92094 #define USBPHY_TX_CLR_TXCAL45DP_MASK             (0xF0000U)
92095 #define USBPHY_TX_CLR_TXCAL45DP_SHIFT            (16U)
92096 /*! TXCAL45DP - TXCAL45DP */
92097 #define USBPHY_TX_CLR_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
92098 /*! @} */
92099 
92100 /*! @name TX_TOG - USB PHY Transmitter Control Register */
92101 /*! @{ */
92102 
92103 #define USBPHY_TX_TOG_D_CAL_MASK                 (0xFU)
92104 #define USBPHY_TX_TOG_D_CAL_SHIFT                (0U)
92105 /*! D_CAL - D_CAL */
92106 #define USBPHY_TX_TOG_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
92107 
92108 #define USBPHY_TX_TOG_TXCAL45DN_MASK             (0xF00U)
92109 #define USBPHY_TX_TOG_TXCAL45DN_SHIFT            (8U)
92110 /*! TXCAL45DN - TXCAL45DN */
92111 #define USBPHY_TX_TOG_TXCAL45DN(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)
92112 
92113 #define USBPHY_TX_TOG_TXCAL45DP_MASK             (0xF0000U)
92114 #define USBPHY_TX_TOG_TXCAL45DP_SHIFT            (16U)
92115 /*! TXCAL45DP - TXCAL45DP */
92116 #define USBPHY_TX_TOG_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
92117 /*! @} */
92118 
92119 /*! @name RX - USB PHY Receiver Control Register */
92120 /*! @{ */
92121 
92122 #define USBPHY_RX_ENVADJ_MASK                    (0x7U)
92123 #define USBPHY_RX_ENVADJ_SHIFT                   (0U)
92124 /*! ENVADJ - ENVADJ
92125  *  0b000..Trip-Level Voltage is 0.1000 V
92126  *  0b001..Trip-Level Voltage is 0.1125 V
92127  *  0b010..Trip-Level Voltage is 0.1250 V
92128  *  0b011..Trip-Level Voltage is 0.0875 V
92129  *  0b1xx..Reserved
92130  */
92131 #define USBPHY_RX_ENVADJ(x)                      (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
92132 
92133 #define USBPHY_RX_DISCONADJ_MASK                 (0x70U)
92134 #define USBPHY_RX_DISCONADJ_SHIFT                (4U)
92135 /*! DISCONADJ - DISCONADJ
92136  *  0b000..Trip-Level Voltage is 0.56875 V
92137  *  0b001..Trip-Level Voltage is 0.55000 V
92138  *  0b010..Trip-Level Voltage is 0.58125 V
92139  *  0b011..Trip-Level Voltage is 0.60000 V
92140  *  0b1xx..Reserved
92141  */
92142 #define USBPHY_RX_DISCONADJ(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
92143 
92144 #define USBPHY_RX_RXDBYPASS_MASK                 (0x400000U)
92145 #define USBPHY_RX_RXDBYPASS_SHIFT                (22U)
92146 /*! RXDBYPASS - RXDBYPASS
92147  *  0b0..Normal operation.
92148  *  0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
92149  */
92150 #define USBPHY_RX_RXDBYPASS(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
92151 /*! @} */
92152 
92153 /*! @name RX_SET - USB PHY Receiver Control Register */
92154 /*! @{ */
92155 
92156 #define USBPHY_RX_SET_ENVADJ_MASK                (0x7U)
92157 #define USBPHY_RX_SET_ENVADJ_SHIFT               (0U)
92158 /*! ENVADJ - ENVADJ */
92159 #define USBPHY_RX_SET_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
92160 
92161 #define USBPHY_RX_SET_DISCONADJ_MASK             (0x70U)
92162 #define USBPHY_RX_SET_DISCONADJ_SHIFT            (4U)
92163 /*! DISCONADJ - DISCONADJ */
92164 #define USBPHY_RX_SET_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
92165 
92166 #define USBPHY_RX_SET_RXDBYPASS_MASK             (0x400000U)
92167 #define USBPHY_RX_SET_RXDBYPASS_SHIFT            (22U)
92168 /*! RXDBYPASS - RXDBYPASS */
92169 #define USBPHY_RX_SET_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
92170 /*! @} */
92171 
92172 /*! @name RX_CLR - USB PHY Receiver Control Register */
92173 /*! @{ */
92174 
92175 #define USBPHY_RX_CLR_ENVADJ_MASK                (0x7U)
92176 #define USBPHY_RX_CLR_ENVADJ_SHIFT               (0U)
92177 /*! ENVADJ - ENVADJ */
92178 #define USBPHY_RX_CLR_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
92179 
92180 #define USBPHY_RX_CLR_DISCONADJ_MASK             (0x70U)
92181 #define USBPHY_RX_CLR_DISCONADJ_SHIFT            (4U)
92182 /*! DISCONADJ - DISCONADJ */
92183 #define USBPHY_RX_CLR_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
92184 
92185 #define USBPHY_RX_CLR_RXDBYPASS_MASK             (0x400000U)
92186 #define USBPHY_RX_CLR_RXDBYPASS_SHIFT            (22U)
92187 /*! RXDBYPASS - RXDBYPASS */
92188 #define USBPHY_RX_CLR_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
92189 /*! @} */
92190 
92191 /*! @name RX_TOG - USB PHY Receiver Control Register */
92192 /*! @{ */
92193 
92194 #define USBPHY_RX_TOG_ENVADJ_MASK                (0x7U)
92195 #define USBPHY_RX_TOG_ENVADJ_SHIFT               (0U)
92196 /*! ENVADJ - ENVADJ */
92197 #define USBPHY_RX_TOG_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
92198 
92199 #define USBPHY_RX_TOG_DISCONADJ_MASK             (0x70U)
92200 #define USBPHY_RX_TOG_DISCONADJ_SHIFT            (4U)
92201 /*! DISCONADJ - DISCONADJ */
92202 #define USBPHY_RX_TOG_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
92203 
92204 #define USBPHY_RX_TOG_RXDBYPASS_MASK             (0x400000U)
92205 #define USBPHY_RX_TOG_RXDBYPASS_SHIFT            (22U)
92206 /*! RXDBYPASS - RXDBYPASS */
92207 #define USBPHY_RX_TOG_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
92208 /*! @} */
92209 
92210 /*! @name CTRL - USB PHY General Control Register */
92211 /*! @{ */
92212 
92213 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK        (0x1U)
92214 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT       (0U)
92215 /*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ */
92216 #define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)
92217 
92218 #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK      (0x2U)
92219 #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT     (1U)
92220 /*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT */
92221 #define USBPHY_CTRL_ENHOSTDISCONDETECT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
92222 
92223 #define USBPHY_CTRL_ENIRQHOSTDISCON_MASK         (0x4U)
92224 #define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT        (2U)
92225 /*! ENIRQHOSTDISCON - ENIRQHOSTDISCON */
92226 #define USBPHY_CTRL_ENIRQHOSTDISCON(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
92227 
92228 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK    (0x8U)
92229 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT   (3U)
92230 /*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ */
92231 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
92232 
92233 #define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK       (0x10U)
92234 #define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT      (4U)
92235 /*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection
92236  *  0b0..Disables 200kohm pullup resistors on DP and DN pins
92237  *  0b1..Enables 200kohm pullup resistors on DP and DN pins
92238  */
92239 #define USBPHY_CTRL_ENDEVPLUGINDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)
92240 
92241 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK      (0x20U)
92242 #define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT     (5U)
92243 /*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY */
92244 #define USBPHY_CTRL_DEVPLUGIN_POLARITY(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
92245 
92246 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK          (0x40U)
92247 #define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT         (6U)
92248 /*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ */
92249 #define USBPHY_CTRL_OTG_ID_CHG_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)
92250 
92251 #define USBPHY_CTRL_ENOTGIDDETECT_MASK           (0x80U)
92252 #define USBPHY_CTRL_ENOTGIDDETECT_SHIFT          (7U)
92253 /*! ENOTGIDDETECT - ENOTGIDDETECT */
92254 #define USBPHY_CTRL_ENOTGIDDETECT(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)
92255 
92256 #define USBPHY_CTRL_RESUMEIRQSTICKY_MASK         (0x100U)
92257 #define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT        (8U)
92258 /*! RESUMEIRQSTICKY - RESUMEIRQSTICKY */
92259 #define USBPHY_CTRL_RESUMEIRQSTICKY(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
92260 
92261 #define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK       (0x200U)
92262 #define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT      (9U)
92263 /*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT */
92264 #define USBPHY_CTRL_ENIRQRESUMEDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
92265 
92266 #define USBPHY_CTRL_RESUME_IRQ_MASK              (0x400U)
92267 #define USBPHY_CTRL_RESUME_IRQ_SHIFT             (10U)
92268 /*! RESUME_IRQ - RESUME_IRQ */
92269 #define USBPHY_CTRL_RESUME_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
92270 
92271 #define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK          (0x800U)
92272 #define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT         (11U)
92273 /*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN */
92274 #define USBPHY_CTRL_ENIRQDEVPLUGIN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)
92275 
92276 #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK           (0x1000U)
92277 #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT          (12U)
92278 /*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ */
92279 #define USBPHY_CTRL_DEVPLUGIN_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
92280 
92281 #define USBPHY_CTRL_ENUTMILEVEL2_MASK            (0x4000U)
92282 #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT           (14U)
92283 /*! ENUTMILEVEL2 - ENUTMILEVEL2 */
92284 #define USBPHY_CTRL_ENUTMILEVEL2(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
92285 
92286 #define USBPHY_CTRL_ENUTMILEVEL3_MASK            (0x8000U)
92287 #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT           (15U)
92288 /*! ENUTMILEVEL3 - ENUTMILEVEL3 */
92289 #define USBPHY_CTRL_ENUTMILEVEL3(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
92290 
92291 #define USBPHY_CTRL_ENIRQWAKEUP_MASK             (0x10000U)
92292 #define USBPHY_CTRL_ENIRQWAKEUP_SHIFT            (16U)
92293 /*! ENIRQWAKEUP - ENIRQWAKEUP */
92294 #define USBPHY_CTRL_ENIRQWAKEUP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
92295 
92296 #define USBPHY_CTRL_WAKEUP_IRQ_MASK              (0x20000U)
92297 #define USBPHY_CTRL_WAKEUP_IRQ_SHIFT             (17U)
92298 /*! WAKEUP_IRQ - WAKEUP_IRQ */
92299 #define USBPHY_CTRL_WAKEUP_IRQ(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
92300 
92301 #define USBPHY_CTRL_AUTORESUME_EN_MASK           (0x40000U)
92302 #define USBPHY_CTRL_AUTORESUME_EN_SHIFT          (18U)
92303 /*! AUTORESUME_EN - AUTORESUME_EN */
92304 #define USBPHY_CTRL_AUTORESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
92305 
92306 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK       (0x80000U)
92307 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT      (19U)
92308 /*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE */
92309 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
92310 
92311 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK       (0x100000U)
92312 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT      (20U)
92313 /*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD */
92314 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
92315 
92316 #define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK          (0x200000U)
92317 #define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT         (21U)
92318 /*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP */
92319 #define USBPHY_CTRL_ENDPDMCHG_WKUP(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
92320 
92321 #define USBPHY_CTRL_ENIDCHG_WKUP_MASK            (0x400000U)
92322 #define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT           (22U)
92323 /*! ENIDCHG_WKUP - ENIDCHG_WKUP */
92324 #define USBPHY_CTRL_ENIDCHG_WKUP(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)
92325 
92326 #define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK          (0x800000U)
92327 #define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT         (23U)
92328 /*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP */
92329 #define USBPHY_CTRL_ENVBUSCHG_WKUP(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
92330 
92331 #define USBPHY_CTRL_FSDLL_RST_EN_MASK            (0x1000000U)
92332 #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT           (24U)
92333 /*! FSDLL_RST_EN - FSDLL_RST_EN */
92334 #define USBPHY_CTRL_FSDLL_RST_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
92335 
92336 #define USBPHY_CTRL_OTG_ID_VALUE_MASK            (0x8000000U)
92337 #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT           (27U)
92338 /*! OTG_ID_VALUE - OTG_ID_VALUE */
92339 #define USBPHY_CTRL_OTG_ID_VALUE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
92340 
92341 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK       (0x10000000U)
92342 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT      (28U)
92343 /*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0 */
92344 #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
92345 
92346 #define USBPHY_CTRL_UTMI_SUSPENDM_MASK           (0x20000000U)
92347 #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT          (29U)
92348 /*! UTMI_SUSPENDM - UTMI_SUSPENDM */
92349 #define USBPHY_CTRL_UTMI_SUSPENDM(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
92350 
92351 #define USBPHY_CTRL_CLKGATE_MASK                 (0x40000000U)
92352 #define USBPHY_CTRL_CLKGATE_SHIFT                (30U)
92353 /*! CLKGATE - CLKGATE */
92354 #define USBPHY_CTRL_CLKGATE(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
92355 
92356 #define USBPHY_CTRL_SFTRST_MASK                  (0x80000000U)
92357 #define USBPHY_CTRL_SFTRST_SHIFT                 (31U)
92358 /*! SFTRST - SFTRST */
92359 #define USBPHY_CTRL_SFTRST(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
92360 /*! @} */
92361 
92362 /*! @name CTRL_SET - USB PHY General Control Register */
92363 /*! @{ */
92364 
92365 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
92366 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
92367 /*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ */
92368 #define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)
92369 
92370 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK  (0x2U)
92371 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
92372 /*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT */
92373 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
92374 
92375 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK     (0x4U)
92376 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT    (2U)
92377 /*! ENIRQHOSTDISCON - ENIRQHOSTDISCON */
92378 #define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
92379 
92380 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
92381 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
92382 /*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ */
92383 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
92384 
92385 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK   (0x10U)
92386 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT  (4U)
92387 /*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection */
92388 #define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)
92389 
92390 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK  (0x20U)
92391 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
92392 /*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY */
92393 #define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
92394 
92395 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK      (0x40U)
92396 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT     (6U)
92397 /*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ */
92398 #define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)
92399 
92400 #define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK       (0x80U)
92401 #define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT      (7U)
92402 /*! ENOTGIDDETECT - ENOTGIDDETECT */
92403 #define USBPHY_CTRL_SET_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)
92404 
92405 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK     (0x100U)
92406 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT    (8U)
92407 /*! RESUMEIRQSTICKY - RESUMEIRQSTICKY */
92408 #define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
92409 
92410 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK   (0x200U)
92411 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT  (9U)
92412 /*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT */
92413 #define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
92414 
92415 #define USBPHY_CTRL_SET_RESUME_IRQ_MASK          (0x400U)
92416 #define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT         (10U)
92417 /*! RESUME_IRQ - RESUME_IRQ */
92418 #define USBPHY_CTRL_SET_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
92419 
92420 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK      (0x800U)
92421 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT     (11U)
92422 /*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN */
92423 #define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)
92424 
92425 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK       (0x1000U)
92426 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT      (12U)
92427 /*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ */
92428 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
92429 
92430 #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK        (0x4000U)
92431 #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT       (14U)
92432 /*! ENUTMILEVEL2 - ENUTMILEVEL2 */
92433 #define USBPHY_CTRL_SET_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
92434 
92435 #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK        (0x8000U)
92436 #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT       (15U)
92437 /*! ENUTMILEVEL3 - ENUTMILEVEL3 */
92438 #define USBPHY_CTRL_SET_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
92439 
92440 #define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK         (0x10000U)
92441 #define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT        (16U)
92442 /*! ENIRQWAKEUP - ENIRQWAKEUP */
92443 #define USBPHY_CTRL_SET_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
92444 
92445 #define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK          (0x20000U)
92446 #define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT         (17U)
92447 /*! WAKEUP_IRQ - WAKEUP_IRQ */
92448 #define USBPHY_CTRL_SET_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
92449 
92450 #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK       (0x40000U)
92451 #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT      (18U)
92452 /*! AUTORESUME_EN - AUTORESUME_EN */
92453 #define USBPHY_CTRL_SET_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
92454 
92455 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
92456 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT  (19U)
92457 /*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE */
92458 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
92459 
92460 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
92461 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
92462 /*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD */
92463 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
92464 
92465 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK      (0x200000U)
92466 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT     (21U)
92467 /*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP */
92468 #define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
92469 
92470 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK        (0x400000U)
92471 #define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT       (22U)
92472 /*! ENIDCHG_WKUP - ENIDCHG_WKUP */
92473 #define USBPHY_CTRL_SET_ENIDCHG_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)
92474 
92475 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK      (0x800000U)
92476 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT     (23U)
92477 /*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP */
92478 #define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
92479 
92480 #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK        (0x1000000U)
92481 #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT       (24U)
92482 /*! FSDLL_RST_EN - FSDLL_RST_EN */
92483 #define USBPHY_CTRL_SET_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
92484 
92485 #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK        (0x8000000U)
92486 #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT       (27U)
92487 /*! OTG_ID_VALUE - OTG_ID_VALUE */
92488 #define USBPHY_CTRL_SET_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
92489 
92490 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
92491 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT  (28U)
92492 /*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0 */
92493 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
92494 
92495 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK       (0x20000000U)
92496 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT      (29U)
92497 /*! UTMI_SUSPENDM - UTMI_SUSPENDM */
92498 #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
92499 
92500 #define USBPHY_CTRL_SET_CLKGATE_MASK             (0x40000000U)
92501 #define USBPHY_CTRL_SET_CLKGATE_SHIFT            (30U)
92502 /*! CLKGATE - CLKGATE */
92503 #define USBPHY_CTRL_SET_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
92504 
92505 #define USBPHY_CTRL_SET_SFTRST_MASK              (0x80000000U)
92506 #define USBPHY_CTRL_SET_SFTRST_SHIFT             (31U)
92507 /*! SFTRST - SFTRST */
92508 #define USBPHY_CTRL_SET_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
92509 /*! @} */
92510 
92511 /*! @name CTRL_CLR - USB PHY General Control Register */
92512 /*! @{ */
92513 
92514 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
92515 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
92516 /*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ */
92517 #define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)
92518 
92519 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK  (0x2U)
92520 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
92521 /*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT */
92522 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
92523 
92524 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK     (0x4U)
92525 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT    (2U)
92526 /*! ENIRQHOSTDISCON - ENIRQHOSTDISCON */
92527 #define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
92528 
92529 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
92530 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
92531 /*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ */
92532 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
92533 
92534 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK   (0x10U)
92535 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT  (4U)
92536 /*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection */
92537 #define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)
92538 
92539 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK  (0x20U)
92540 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
92541 /*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY */
92542 #define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
92543 
92544 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK      (0x40U)
92545 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT     (6U)
92546 /*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ */
92547 #define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)
92548 
92549 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK       (0x80U)
92550 #define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT      (7U)
92551 /*! ENOTGIDDETECT - ENOTGIDDETECT */
92552 #define USBPHY_CTRL_CLR_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)
92553 
92554 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK     (0x100U)
92555 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT    (8U)
92556 /*! RESUMEIRQSTICKY - RESUMEIRQSTICKY */
92557 #define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
92558 
92559 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK   (0x200U)
92560 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT  (9U)
92561 /*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT */
92562 #define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
92563 
92564 #define USBPHY_CTRL_CLR_RESUME_IRQ_MASK          (0x400U)
92565 #define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT         (10U)
92566 /*! RESUME_IRQ - RESUME_IRQ */
92567 #define USBPHY_CTRL_CLR_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
92568 
92569 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK      (0x800U)
92570 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT     (11U)
92571 /*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN */
92572 #define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)
92573 
92574 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK       (0x1000U)
92575 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT      (12U)
92576 /*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ */
92577 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
92578 
92579 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK        (0x4000U)
92580 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT       (14U)
92581 /*! ENUTMILEVEL2 - ENUTMILEVEL2 */
92582 #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
92583 
92584 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK        (0x8000U)
92585 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT       (15U)
92586 /*! ENUTMILEVEL3 - ENUTMILEVEL3 */
92587 #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
92588 
92589 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK         (0x10000U)
92590 #define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT        (16U)
92591 /*! ENIRQWAKEUP - ENIRQWAKEUP */
92592 #define USBPHY_CTRL_CLR_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
92593 
92594 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK          (0x20000U)
92595 #define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT         (17U)
92596 /*! WAKEUP_IRQ - WAKEUP_IRQ */
92597 #define USBPHY_CTRL_CLR_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
92598 
92599 #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK       (0x40000U)
92600 #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT      (18U)
92601 /*! AUTORESUME_EN - AUTORESUME_EN */
92602 #define USBPHY_CTRL_CLR_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
92603 
92604 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
92605 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT  (19U)
92606 /*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE */
92607 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
92608 
92609 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
92610 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
92611 /*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD */
92612 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
92613 
92614 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK      (0x200000U)
92615 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT     (21U)
92616 /*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP */
92617 #define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
92618 
92619 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK        (0x400000U)
92620 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT       (22U)
92621 /*! ENIDCHG_WKUP - ENIDCHG_WKUP */
92622 #define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)
92623 
92624 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK      (0x800000U)
92625 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT     (23U)
92626 /*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP */
92627 #define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
92628 
92629 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK        (0x1000000U)
92630 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT       (24U)
92631 /*! FSDLL_RST_EN - FSDLL_RST_EN */
92632 #define USBPHY_CTRL_CLR_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
92633 
92634 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK        (0x8000000U)
92635 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT       (27U)
92636 /*! OTG_ID_VALUE - OTG_ID_VALUE */
92637 #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
92638 
92639 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
92640 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT  (28U)
92641 /*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0 */
92642 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
92643 
92644 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK       (0x20000000U)
92645 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT      (29U)
92646 /*! UTMI_SUSPENDM - UTMI_SUSPENDM */
92647 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
92648 
92649 #define USBPHY_CTRL_CLR_CLKGATE_MASK             (0x40000000U)
92650 #define USBPHY_CTRL_CLR_CLKGATE_SHIFT            (30U)
92651 /*! CLKGATE - CLKGATE */
92652 #define USBPHY_CTRL_CLR_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
92653 
92654 #define USBPHY_CTRL_CLR_SFTRST_MASK              (0x80000000U)
92655 #define USBPHY_CTRL_CLR_SFTRST_SHIFT             (31U)
92656 /*! SFTRST - SFTRST */
92657 #define USBPHY_CTRL_CLR_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
92658 /*! @} */
92659 
92660 /*! @name CTRL_TOG - USB PHY General Control Register */
92661 /*! @{ */
92662 
92663 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK    (0x1U)
92664 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT   (0U)
92665 /*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ */
92666 #define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)
92667 
92668 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK  (0x2U)
92669 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
92670 /*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT */
92671 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
92672 
92673 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK     (0x4U)
92674 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT    (2U)
92675 /*! ENIRQHOSTDISCON - ENIRQHOSTDISCON */
92676 #define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
92677 
92678 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
92679 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
92680 /*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ */
92681 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
92682 
92683 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK   (0x10U)
92684 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT  (4U)
92685 /*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection */
92686 #define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)
92687 
92688 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK  (0x20U)
92689 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
92690 /*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY */
92691 #define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
92692 
92693 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK      (0x40U)
92694 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT     (6U)
92695 /*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ */
92696 #define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)
92697 
92698 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK       (0x80U)
92699 #define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT      (7U)
92700 /*! ENOTGIDDETECT - ENOTGIDDETECT */
92701 #define USBPHY_CTRL_TOG_ENOTGIDDETECT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)
92702 
92703 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK     (0x100U)
92704 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT    (8U)
92705 /*! RESUMEIRQSTICKY - RESUMEIRQSTICKY */
92706 #define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
92707 
92708 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK   (0x200U)
92709 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT  (9U)
92710 /*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT */
92711 #define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
92712 
92713 #define USBPHY_CTRL_TOG_RESUME_IRQ_MASK          (0x400U)
92714 #define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT         (10U)
92715 /*! RESUME_IRQ - RESUME_IRQ */
92716 #define USBPHY_CTRL_TOG_RESUME_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
92717 
92718 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK      (0x800U)
92719 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT     (11U)
92720 /*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN */
92721 #define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)
92722 
92723 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK       (0x1000U)
92724 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT      (12U)
92725 /*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ */
92726 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
92727 
92728 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK        (0x4000U)
92729 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT       (14U)
92730 /*! ENUTMILEVEL2 - ENUTMILEVEL2 */
92731 #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
92732 
92733 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK        (0x8000U)
92734 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT       (15U)
92735 /*! ENUTMILEVEL3 - ENUTMILEVEL3 */
92736 #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
92737 
92738 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK         (0x10000U)
92739 #define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT        (16U)
92740 /*! ENIRQWAKEUP - ENIRQWAKEUP */
92741 #define USBPHY_CTRL_TOG_ENIRQWAKEUP(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
92742 
92743 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK          (0x20000U)
92744 #define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT         (17U)
92745 /*! WAKEUP_IRQ - WAKEUP_IRQ */
92746 #define USBPHY_CTRL_TOG_WAKEUP_IRQ(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
92747 
92748 #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK       (0x40000U)
92749 #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT      (18U)
92750 /*! AUTORESUME_EN - AUTORESUME_EN */
92751 #define USBPHY_CTRL_TOG_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
92752 
92753 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
92754 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT  (19U)
92755 /*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE */
92756 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
92757 
92758 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
92759 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
92760 /*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD */
92761 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
92762 
92763 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK      (0x200000U)
92764 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT     (21U)
92765 /*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP */
92766 #define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
92767 
92768 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK        (0x400000U)
92769 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT       (22U)
92770 /*! ENIDCHG_WKUP - ENIDCHG_WKUP */
92771 #define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)
92772 
92773 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK      (0x800000U)
92774 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT     (23U)
92775 /*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP */
92776 #define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
92777 
92778 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK        (0x1000000U)
92779 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT       (24U)
92780 /*! FSDLL_RST_EN - FSDLL_RST_EN */
92781 #define USBPHY_CTRL_TOG_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
92782 
92783 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK        (0x8000000U)
92784 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT       (27U)
92785 /*! OTG_ID_VALUE - OTG_ID_VALUE */
92786 #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
92787 
92788 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
92789 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT  (28U)
92790 /*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0 */
92791 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
92792 
92793 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK       (0x20000000U)
92794 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT      (29U)
92795 /*! UTMI_SUSPENDM - UTMI_SUSPENDM */
92796 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
92797 
92798 #define USBPHY_CTRL_TOG_CLKGATE_MASK             (0x40000000U)
92799 #define USBPHY_CTRL_TOG_CLKGATE_SHIFT            (30U)
92800 /*! CLKGATE - CLKGATE */
92801 #define USBPHY_CTRL_TOG_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
92802 
92803 #define USBPHY_CTRL_TOG_SFTRST_MASK              (0x80000000U)
92804 #define USBPHY_CTRL_TOG_SFTRST_SHIFT             (31U)
92805 /*! SFTRST - SFTRST */
92806 #define USBPHY_CTRL_TOG_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
92807 /*! @} */
92808 
92809 /*! @name STATUS - USB PHY Status Register */
92810 /*! @{ */
92811 
92812 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
92813 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
92814 /*! HOSTDISCONDETECT_STATUS - HOSTDISCONDETECT_STATUS
92815  *  0b0..USB cable disconnect has not been detected at the local host
92816  *  0b1..USB cable disconnect has been detected at the local host
92817  */
92818 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
92819 
92820 #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK      (0x40U)
92821 #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT     (6U)
92822 /*! DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection
92823  *  0b0..No attachment to a USB host is detected
92824  *  0b1..Cable attachment to a USB host is detected
92825  */
92826 #define USBPHY_STATUS_DEVPLUGIN_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
92827 
92828 #define USBPHY_STATUS_OTGID_STATUS_MASK          (0x100U)
92829 #define USBPHY_STATUS_OTGID_STATUS_SHIFT         (8U)
92830 /*! OTGID_STATUS - OTGID_STATUS */
92831 #define USBPHY_STATUS_OTGID_STATUS(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
92832 
92833 #define USBPHY_STATUS_RESUME_STATUS_MASK         (0x400U)
92834 #define USBPHY_STATUS_RESUME_STATUS_SHIFT        (10U)
92835 /*! RESUME_STATUS - RESUME_STATUS */
92836 #define USBPHY_STATUS_RESUME_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
92837 /*! @} */
92838 
92839 /*! @name DEBUG - USB PHY Debug Register */
92840 /*! @{ */
92841 
92842 #define USBPHY_DEBUG_OTGIDPIOLOCK_MASK           (0x1U)
92843 #define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT          (0U)
92844 /*! OTGIDPIOLOCK - OTGIDPIOLOCK */
92845 #define USBPHY_DEBUG_OTGIDPIOLOCK(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
92846 
92847 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK   (0x2U)
92848 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT  (1U)
92849 /*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD */
92850 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
92851 
92852 #define USBPHY_DEBUG_HSTPULLDOWN_MASK            (0xCU)
92853 #define USBPHY_DEBUG_HSTPULLDOWN_SHIFT           (2U)
92854 /*! HSTPULLDOWN - HSTPULLDOWN */
92855 #define USBPHY_DEBUG_HSTPULLDOWN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
92856 
92857 #define USBPHY_DEBUG_ENHSTPULLDOWN_MASK          (0x30U)
92858 #define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT         (4U)
92859 /*! ENHSTPULLDOWN - ENHSTPULLDOWN */
92860 #define USBPHY_DEBUG_ENHSTPULLDOWN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
92861 
92862 #define USBPHY_DEBUG_TX2RXCOUNT_MASK             (0xF00U)
92863 #define USBPHY_DEBUG_TX2RXCOUNT_SHIFT            (8U)
92864 /*! TX2RXCOUNT - TX2RXCOUNT */
92865 #define USBPHY_DEBUG_TX2RXCOUNT(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
92866 
92867 #define USBPHY_DEBUG_ENTX2RXCOUNT_MASK           (0x1000U)
92868 #define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT          (12U)
92869 /*! ENTX2RXCOUNT - ENTX2RXCOUNT */
92870 #define USBPHY_DEBUG_ENTX2RXCOUNT(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
92871 
92872 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK      (0x1F0000U)
92873 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT     (16U)
92874 /*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT */
92875 #define USBPHY_DEBUG_SQUELCHRESETCOUNT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
92876 
92877 #define USBPHY_DEBUG_ENSQUELCHRESET_MASK         (0x1000000U)
92878 #define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT        (24U)
92879 /*! ENSQUELCHRESET - ENSQUELCHRESET */
92880 #define USBPHY_DEBUG_ENSQUELCHRESET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
92881 
92882 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK     (0x1E000000U)
92883 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT    (25U)
92884 /*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH */
92885 #define USBPHY_DEBUG_SQUELCHRESETLENGTH(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
92886 
92887 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK      (0x20000000U)
92888 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT     (29U)
92889 /*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG */
92890 #define USBPHY_DEBUG_HOST_RESUME_DEBUG(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
92891 
92892 #define USBPHY_DEBUG_CLKGATE_MASK                (0x40000000U)
92893 #define USBPHY_DEBUG_CLKGATE_SHIFT               (30U)
92894 /*! CLKGATE - CLKGATE */
92895 #define USBPHY_DEBUG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
92896 /*! @} */
92897 
92898 /*! @name DEBUG_SET - USB PHY Debug Register */
92899 /*! @{ */
92900 
92901 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK       (0x1U)
92902 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT      (0U)
92903 /*! OTGIDPIOLOCK - OTGIDPIOLOCK */
92904 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
92905 
92906 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
92907 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
92908 /*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD */
92909 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
92910 
92911 #define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK        (0xCU)
92912 #define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT       (2U)
92913 /*! HSTPULLDOWN - HSTPULLDOWN */
92914 #define USBPHY_DEBUG_SET_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
92915 
92916 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK      (0x30U)
92917 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT     (4U)
92918 /*! ENHSTPULLDOWN - ENHSTPULLDOWN */
92919 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
92920 
92921 #define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK         (0xF00U)
92922 #define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT        (8U)
92923 /*! TX2RXCOUNT - TX2RXCOUNT */
92924 #define USBPHY_DEBUG_SET_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
92925 
92926 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK       (0x1000U)
92927 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT      (12U)
92928 /*! ENTX2RXCOUNT - ENTX2RXCOUNT */
92929 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
92930 
92931 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
92932 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
92933 /*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT */
92934 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
92935 
92936 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK     (0x1000000U)
92937 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT    (24U)
92938 /*! ENSQUELCHRESET - ENSQUELCHRESET */
92939 #define USBPHY_DEBUG_SET_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
92940 
92941 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
92942 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
92943 /*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH */
92944 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
92945 
92946 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK  (0x20000000U)
92947 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
92948 /*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG */
92949 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
92950 
92951 #define USBPHY_DEBUG_SET_CLKGATE_MASK            (0x40000000U)
92952 #define USBPHY_DEBUG_SET_CLKGATE_SHIFT           (30U)
92953 /*! CLKGATE - CLKGATE */
92954 #define USBPHY_DEBUG_SET_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
92955 /*! @} */
92956 
92957 /*! @name DEBUG_CLR - USB PHY Debug Register */
92958 /*! @{ */
92959 
92960 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK       (0x1U)
92961 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT      (0U)
92962 /*! OTGIDPIOLOCK - OTGIDPIOLOCK */
92963 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
92964 
92965 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
92966 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
92967 /*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD */
92968 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
92969 
92970 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK        (0xCU)
92971 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT       (2U)
92972 /*! HSTPULLDOWN - HSTPULLDOWN */
92973 #define USBPHY_DEBUG_CLR_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
92974 
92975 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK      (0x30U)
92976 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT     (4U)
92977 /*! ENHSTPULLDOWN - ENHSTPULLDOWN */
92978 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
92979 
92980 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK         (0xF00U)
92981 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT        (8U)
92982 /*! TX2RXCOUNT - TX2RXCOUNT */
92983 #define USBPHY_DEBUG_CLR_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
92984 
92985 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK       (0x1000U)
92986 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT      (12U)
92987 /*! ENTX2RXCOUNT - ENTX2RXCOUNT */
92988 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
92989 
92990 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
92991 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
92992 /*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT */
92993 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
92994 
92995 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK     (0x1000000U)
92996 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT    (24U)
92997 /*! ENSQUELCHRESET - ENSQUELCHRESET */
92998 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
92999 
93000 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
93001 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
93002 /*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH */
93003 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
93004 
93005 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK  (0x20000000U)
93006 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
93007 /*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG */
93008 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
93009 
93010 #define USBPHY_DEBUG_CLR_CLKGATE_MASK            (0x40000000U)
93011 #define USBPHY_DEBUG_CLR_CLKGATE_SHIFT           (30U)
93012 /*! CLKGATE - CLKGATE */
93013 #define USBPHY_DEBUG_CLR_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
93014 /*! @} */
93015 
93016 /*! @name DEBUG_TOG - USB PHY Debug Register */
93017 /*! @{ */
93018 
93019 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK       (0x1U)
93020 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT      (0U)
93021 /*! OTGIDPIOLOCK - OTGIDPIOLOCK */
93022 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
93023 
93024 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
93025 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
93026 /*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD */
93027 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
93028 
93029 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK        (0xCU)
93030 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT       (2U)
93031 /*! HSTPULLDOWN - HSTPULLDOWN */
93032 #define USBPHY_DEBUG_TOG_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
93033 
93034 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK      (0x30U)
93035 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT     (4U)
93036 /*! ENHSTPULLDOWN - ENHSTPULLDOWN */
93037 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
93038 
93039 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK         (0xF00U)
93040 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT        (8U)
93041 /*! TX2RXCOUNT - TX2RXCOUNT */
93042 #define USBPHY_DEBUG_TOG_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
93043 
93044 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK       (0x1000U)
93045 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT      (12U)
93046 /*! ENTX2RXCOUNT - ENTX2RXCOUNT */
93047 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
93048 
93049 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
93050 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
93051 /*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT */
93052 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
93053 
93054 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK     (0x1000000U)
93055 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT    (24U)
93056 /*! ENSQUELCHRESET - ENSQUELCHRESET */
93057 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
93058 
93059 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
93060 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
93061 /*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH */
93062 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
93063 
93064 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK  (0x20000000U)
93065 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
93066 /*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG */
93067 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
93068 
93069 #define USBPHY_DEBUG_TOG_CLKGATE_MASK            (0x40000000U)
93070 #define USBPHY_DEBUG_TOG_CLKGATE_SHIFT           (30U)
93071 /*! CLKGATE - CLKGATE */
93072 #define USBPHY_DEBUG_TOG_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
93073 /*! @} */
93074 
93075 /*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */
93076 /*! @{ */
93077 
93078 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
93079 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
93080 /*! LOOP_BACK_FAIL_COUNT - LOOP_BACK_FAIL_COUNT */
93081 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
93082 
93083 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
93084 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
93085 /*! UTMI_RXERROR_FAIL_COUNT - UTMI_RXERROR_FAIL_COUNT */
93086 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
93087 
93088 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK  (0xFC000000U)
93089 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
93090 /*! SQUELCH_COUNT - SQUELCH_COUNT */
93091 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
93092 /*! @} */
93093 
93094 /*! @name DEBUG1 - UTMI Debug Status Register 1 */
93095 /*! @{ */
93096 
93097 #define USBPHY_DEBUG1_ENTAILADJVD_MASK           (0x6000U)
93098 #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT          (13U)
93099 /*! ENTAILADJVD - ENTAILADJVD
93100  *  0b00..Delay is nominal
93101  *  0b01..Delay is +20%
93102  *  0b10..Delay is -20%
93103  *  0b11..Delay is -40%
93104  */
93105 #define USBPHY_DEBUG1_ENTAILADJVD(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
93106 
93107 #define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
93108 #define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
93109 /*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. */
93110 #define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK)
93111 
93112 #define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
93113 #define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
93114 /*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register. */
93115 #define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK)
93116 
93117 #define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK   (0x20000U)
93118 #define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT  (17U)
93119 /*! USB2_REFBIAS_LOWPWR - to be added */
93120 #define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK)
93121 
93122 #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK   (0x1C0000U)
93123 #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT  (18U)
93124 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */
93125 #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK)
93126 
93127 #define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK      (0x600000U)
93128 #define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT     (21U)
93129 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy */
93130 #define USBPHY_DEBUG1_USB2_REFBIAS_TST(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK)
93131 /*! @} */
93132 
93133 /*! @name DEBUG1_SET - UTMI Debug Status Register 1 */
93134 /*! @{ */
93135 
93136 #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK       (0x6000U)
93137 #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT      (13U)
93138 /*! ENTAILADJVD - ENTAILADJVD */
93139 #define USBPHY_DEBUG1_SET_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
93140 
93141 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
93142 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
93143 /*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. */
93144 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK)
93145 
93146 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
93147 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
93148 /*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register. */
93149 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK)
93150 
93151 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
93152 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT (17U)
93153 /*! USB2_REFBIAS_LOWPWR - to be added */
93154 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK)
93155 
93156 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
93157 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U)
93158 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */
93159 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK)
93160 
93161 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK  (0x600000U)
93162 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U)
93163 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy */
93164 #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK)
93165 /*! @} */
93166 
93167 /*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */
93168 /*! @{ */
93169 
93170 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK       (0x6000U)
93171 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT      (13U)
93172 /*! ENTAILADJVD - ENTAILADJVD */
93173 #define USBPHY_DEBUG1_CLR_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
93174 
93175 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
93176 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
93177 /*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. */
93178 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK)
93179 
93180 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
93181 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
93182 /*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register. */
93183 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK)
93184 
93185 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
93186 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT (17U)
93187 /*! USB2_REFBIAS_LOWPWR - to be added */
93188 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK)
93189 
93190 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
93191 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U)
93192 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */
93193 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK)
93194 
93195 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK  (0x600000U)
93196 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U)
93197 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy */
93198 #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK)
93199 /*! @} */
93200 
93201 /*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */
93202 /*! @{ */
93203 
93204 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK       (0x6000U)
93205 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT      (13U)
93206 /*! ENTAILADJVD - ENTAILADJVD */
93207 #define USBPHY_DEBUG1_TOG_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
93208 
93209 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
93210 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
93211 /*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. */
93212 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK)
93213 
93214 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
93215 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
93216 /*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register. */
93217 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK)
93218 
93219 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
93220 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT (17U)
93221 /*! USB2_REFBIAS_LOWPWR - to be added */
93222 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK)
93223 
93224 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
93225 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U)
93226 /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */
93227 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK)
93228 
93229 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK  (0x600000U)
93230 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U)
93231 /*! USB2_REFBIAS_TST - Bias current control for usb2_phy */
93232 #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK)
93233 /*! @} */
93234 
93235 /*! @name VERSION - UTMI RTL Version */
93236 /*! @{ */
93237 
93238 #define USBPHY_VERSION_STEP_MASK                 (0xFFFFU)
93239 #define USBPHY_VERSION_STEP_SHIFT                (0U)
93240 /*! STEP - STEP */
93241 #define USBPHY_VERSION_STEP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
93242 
93243 #define USBPHY_VERSION_MINOR_MASK                (0xFF0000U)
93244 #define USBPHY_VERSION_MINOR_SHIFT               (16U)
93245 /*! MINOR - MINOR */
93246 #define USBPHY_VERSION_MINOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
93247 
93248 #define USBPHY_VERSION_MAJOR_MASK                (0xFF000000U)
93249 #define USBPHY_VERSION_MAJOR_SHIFT               (24U)
93250 /*! MAJOR - MAJOR */
93251 #define USBPHY_VERSION_MAJOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
93252 /*! @} */
93253 
93254 /*! @name PLL_SIC - USB PHY PLL Control/Status Register */
93255 /*! @{ */
93256 
93257 #define USBPHY_PLL_SIC_PLL_POSTDIV_MASK          (0x1CU)
93258 #define USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT         (2U)
93259 /*! PLL_POSTDIV - PLL_POSTDIV */
93260 #define USBPHY_PLL_SIC_PLL_POSTDIV(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_POSTDIV_MASK)
93261 
93262 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK      (0x40U)
93263 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT     (6U)
93264 /*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS */
93265 #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
93266 
93267 #define USBPHY_PLL_SIC_PLL_POWER_MASK            (0x1000U)
93268 #define USBPHY_PLL_SIC_PLL_POWER_SHIFT           (12U)
93269 /*! PLL_POWER - PLL_POWER */
93270 #define USBPHY_PLL_SIC_PLL_POWER(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
93271 
93272 #define USBPHY_PLL_SIC_PLL_ENABLE_MASK           (0x2000U)
93273 #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT          (13U)
93274 /*! PLL_ENABLE - PLL_ENABLE */
93275 #define USBPHY_PLL_SIC_PLL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
93276 
93277 #define USBPHY_PLL_SIC_PLL_BYPASS_MASK           (0x10000U)
93278 #define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT          (16U)
93279 /*! PLL_BYPASS - PLL_BYPASS */
93280 #define USBPHY_PLL_SIC_PLL_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
93281 
93282 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK      (0x80000U)
93283 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT     (19U)
93284 /*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
93285  *  0b0..Selects PLL_POWER to control the reference bias
93286  *  0b1..Selects REFBIAS_PWD to control the reference bias.
93287  */
93288 #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK)
93289 
93290 #define USBPHY_PLL_SIC_REFBIAS_PWD_MASK          (0x100000U)
93291 #define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT         (20U)
93292 /*! REFBIAS_PWD - Power down the reference bias */
93293 #define USBPHY_PLL_SIC_REFBIAS_PWD(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK)
93294 
93295 #define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK       (0x200000U)
93296 #define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT      (21U)
93297 /*! PLL_REG_ENABLE - PLL_REG_ENABLE */
93298 #define USBPHY_PLL_SIC_PLL_REG_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK)
93299 
93300 #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK          (0x1C00000U)
93301 #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT         (22U)
93302 /*! PLL_DIV_SEL - PLL_DIV_SEL
93303  *  0b000..Divide by 13
93304  *  0b001..Divide by 15
93305  *  0b010..Divide by 16
93306  *  0b011..Divide by 20
93307  *  0b100..Divide by 22
93308  *  0b101..Divide by 25
93309  *  0b110..Divide by 30
93310  *  0b111..Divide by 240
93311  */
93312 #define USBPHY_PLL_SIC_PLL_DIV_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
93313 
93314 #define USBPHY_PLL_SIC_PLL_LOCK_MASK             (0x80000000U)
93315 #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT            (31U)
93316 /*! PLL_LOCK - PLL_LOCK
93317  *  0b0..PLL is not currently locked
93318  *  0b1..PLL is currently locked
93319  */
93320 #define USBPHY_PLL_SIC_PLL_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
93321 /*! @} */
93322 
93323 /*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */
93324 /*! @{ */
93325 
93326 #define USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK      (0x1CU)
93327 #define USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT     (2U)
93328 /*! PLL_POSTDIV - PLL_POSTDIV */
93329 #define USBPHY_PLL_SIC_SET_PLL_POSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK)
93330 
93331 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK  (0x40U)
93332 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
93333 /*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS */
93334 #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
93335 
93336 #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK        (0x1000U)
93337 #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT       (12U)
93338 /*! PLL_POWER - PLL_POWER */
93339 #define USBPHY_PLL_SIC_SET_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
93340 
93341 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK       (0x2000U)
93342 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT      (13U)
93343 /*! PLL_ENABLE - PLL_ENABLE */
93344 #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
93345 
93346 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK       (0x10000U)
93347 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT      (16U)
93348 /*! PLL_BYPASS - PLL_BYPASS */
93349 #define USBPHY_PLL_SIC_SET_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
93350 
93351 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK  (0x80000U)
93352 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U)
93353 /*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL */
93354 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK)
93355 
93356 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK      (0x100000U)
93357 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT     (20U)
93358 /*! REFBIAS_PWD - Power down the reference bias */
93359 #define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK)
93360 
93361 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK   (0x200000U)
93362 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT  (21U)
93363 /*! PLL_REG_ENABLE - PLL_REG_ENABLE */
93364 #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK)
93365 
93366 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK      (0x1C00000U)
93367 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT     (22U)
93368 /*! PLL_DIV_SEL - PLL_DIV_SEL */
93369 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
93370 
93371 #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK         (0x80000000U)
93372 #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT        (31U)
93373 /*! PLL_LOCK - PLL_LOCK */
93374 #define USBPHY_PLL_SIC_SET_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
93375 /*! @} */
93376 
93377 /*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */
93378 /*! @{ */
93379 
93380 #define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK      (0x1CU)
93381 #define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT     (2U)
93382 /*! PLL_POSTDIV - PLL_POSTDIV */
93383 #define USBPHY_PLL_SIC_CLR_PLL_POSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK)
93384 
93385 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK  (0x40U)
93386 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
93387 /*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS */
93388 #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
93389 
93390 #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK        (0x1000U)
93391 #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT       (12U)
93392 /*! PLL_POWER - PLL_POWER */
93393 #define USBPHY_PLL_SIC_CLR_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
93394 
93395 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK       (0x2000U)
93396 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT      (13U)
93397 /*! PLL_ENABLE - PLL_ENABLE */
93398 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
93399 
93400 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK       (0x10000U)
93401 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT      (16U)
93402 /*! PLL_BYPASS - PLL_BYPASS */
93403 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
93404 
93405 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK  (0x80000U)
93406 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U)
93407 /*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL */
93408 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK)
93409 
93410 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK      (0x100000U)
93411 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT     (20U)
93412 /*! REFBIAS_PWD - Power down the reference bias */
93413 #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK)
93414 
93415 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK   (0x200000U)
93416 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT  (21U)
93417 /*! PLL_REG_ENABLE - PLL_REG_ENABLE */
93418 #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK)
93419 
93420 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK      (0x1C00000U)
93421 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT     (22U)
93422 /*! PLL_DIV_SEL - PLL_DIV_SEL */
93423 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
93424 
93425 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK         (0x80000000U)
93426 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT        (31U)
93427 /*! PLL_LOCK - PLL_LOCK */
93428 #define USBPHY_PLL_SIC_CLR_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
93429 /*! @} */
93430 
93431 /*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */
93432 /*! @{ */
93433 
93434 #define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK      (0x1CU)
93435 #define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT     (2U)
93436 /*! PLL_POSTDIV - PLL_POSTDIV */
93437 #define USBPHY_PLL_SIC_TOG_PLL_POSTDIV(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK)
93438 
93439 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK  (0x40U)
93440 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
93441 /*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS */
93442 #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
93443 
93444 #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK        (0x1000U)
93445 #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT       (12U)
93446 /*! PLL_POWER - PLL_POWER */
93447 #define USBPHY_PLL_SIC_TOG_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
93448 
93449 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK       (0x2000U)
93450 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT      (13U)
93451 /*! PLL_ENABLE - PLL_ENABLE */
93452 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
93453 
93454 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK       (0x10000U)
93455 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT      (16U)
93456 /*! PLL_BYPASS - PLL_BYPASS */
93457 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
93458 
93459 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK  (0x80000U)
93460 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U)
93461 /*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL */
93462 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK)
93463 
93464 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK      (0x100000U)
93465 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT     (20U)
93466 /*! REFBIAS_PWD - Power down the reference bias */
93467 #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK)
93468 
93469 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK   (0x200000U)
93470 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT  (21U)
93471 /*! PLL_REG_ENABLE - PLL_REG_ENABLE */
93472 #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK)
93473 
93474 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK      (0x1C00000U)
93475 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT     (22U)
93476 /*! PLL_DIV_SEL - PLL_DIV_SEL */
93477 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
93478 
93479 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK         (0x80000000U)
93480 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT        (31U)
93481 /*! PLL_LOCK - PLL_LOCK */
93482 #define USBPHY_PLL_SIC_TOG_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
93483 /*! @} */
93484 
93485 /*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */
93486 /*! @{ */
93487 
93488 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
93489 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
93490 /*! VBUSVALID_THRESH - VBUSVALID_THRESH
93491  *  0b000..4.0 V
93492  *  0b001..4.1 V
93493  *  0b010..4.2 V
93494  *  0b011..4.3 V
93495  *  0b100..4.4 V (Default)
93496  *  0b101..4.5 V
93497  *  0b110..4.6 V
93498  *  0b111..4.7 V
93499  */
93500 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
93501 
93502 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
93503 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
93504 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
93505  *  0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
93506  *  0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
93507  */
93508 #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
93509 
93510 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
93511 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
93512 /*! SESSEND_OVERRIDE - Override value for SESSEND */
93513 #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
93514 
93515 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
93516 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
93517 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */
93518 #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
93519 
93520 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
93521 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
93522 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */
93523 #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
93524 
93525 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
93526 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
93527 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */
93528 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
93529 
93530 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
93531 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
93532 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
93533  *  0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
93534  *  0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
93535  */
93536 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
93537 
93538 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
93539 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
93540 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
93541  *  0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
93542  *  0b01..Use the Session Valid comparator results for signal reported to the USB controller
93543  *  0b10..Use the Session Valid comparator results for signal reported to the USB controller
93544  *  0b11..Reserved, do not use
93545  */
93546 #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
93547 
93548 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U)
93549 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U)
93550 /*! ID_OVERRIDE_EN - TBA */
93551 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK)
93552 
93553 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U)
93554 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U)
93555 /*! ID_OVERRIDE - TBA */
93556 #define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK)
93557 
93558 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
93559 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
93560 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
93561  *  0b0..Use the VBUS_VALID comparator for VBUS_VALID results
93562  *  0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
93563  */
93564 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
93565 
93566 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK  (0x700000U)
93567 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
93568 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator
93569  *  0b000..Powers down the VBUS_VALID comparator
93570  *  0b001..Enables the SESS_VALID comparator (default)
93571  *  0b010..Enables the 3Vdetect (default)
93572  */
93573 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
93574 
93575 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
93576 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
93577 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor
93578  *  0b0..VBUS discharge resistor is disabled (Default)
93579  *  0b1..VBUS discharge resistor is enabled
93580  */
93581 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
93582 
93583 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)
93584 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)
93585 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
93586  *  0b0..Disable resistive charger detection resistors on DP and DP
93587  *  0b1..Enable resistive charger detection resistors on DP and DP
93588  */
93589 #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)
93590 /*! @} */
93591 
93592 /*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */
93593 /*! @{ */
93594 
93595 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
93596 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
93597 /*! VBUSVALID_THRESH - VBUSVALID_THRESH */
93598 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
93599 
93600 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
93601 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
93602 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable */
93603 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
93604 
93605 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
93606 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
93607 /*! SESSEND_OVERRIDE - Override value for SESSEND */
93608 #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
93609 
93610 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
93611 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
93612 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */
93613 #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
93614 
93615 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
93616 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
93617 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */
93618 #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
93619 
93620 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
93621 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
93622 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */
93623 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
93624 
93625 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
93626 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
93627 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller */
93628 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
93629 
93630 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
93631 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
93632 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller */
93633 #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
93634 
93635 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U)
93636 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U)
93637 /*! ID_OVERRIDE_EN - TBA */
93638 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK)
93639 
93640 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U)
93641 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U)
93642 /*! ID_OVERRIDE - TBA */
93643 #define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK)
93644 
93645 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
93646 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
93647 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID */
93648 #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
93649 
93650 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U)
93651 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
93652 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator */
93653 #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
93654 
93655 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
93656 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
93657 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor */
93658 #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
93659 
93660 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)
93661 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)
93662 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection */
93663 #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)
93664 /*! @} */
93665 
93666 /*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */
93667 /*! @{ */
93668 
93669 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
93670 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
93671 /*! VBUSVALID_THRESH - VBUSVALID_THRESH */
93672 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
93673 
93674 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
93675 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
93676 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable */
93677 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
93678 
93679 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
93680 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
93681 /*! SESSEND_OVERRIDE - Override value for SESSEND */
93682 #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
93683 
93684 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
93685 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
93686 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */
93687 #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
93688 
93689 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
93690 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
93691 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */
93692 #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
93693 
93694 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
93695 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
93696 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */
93697 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
93698 
93699 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
93700 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
93701 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller */
93702 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
93703 
93704 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
93705 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
93706 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller */
93707 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
93708 
93709 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U)
93710 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U)
93711 /*! ID_OVERRIDE_EN - TBA */
93712 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK)
93713 
93714 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U)
93715 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U)
93716 /*! ID_OVERRIDE - TBA */
93717 #define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK)
93718 
93719 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
93720 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
93721 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID */
93722 #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
93723 
93724 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U)
93725 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
93726 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator */
93727 #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
93728 
93729 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
93730 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
93731 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor */
93732 #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
93733 
93734 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)
93735 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)
93736 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection */
93737 #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)
93738 /*! @} */
93739 
93740 /*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */
93741 /*! @{ */
93742 
93743 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
93744 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
93745 /*! VBUSVALID_THRESH - VBUSVALID_THRESH */
93746 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
93747 
93748 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
93749 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
93750 /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable */
93751 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
93752 
93753 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
93754 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
93755 /*! SESSEND_OVERRIDE - Override value for SESSEND */
93756 #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
93757 
93758 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
93759 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
93760 /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */
93761 #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
93762 
93763 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
93764 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
93765 /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */
93766 #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
93767 
93768 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
93769 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
93770 /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */
93771 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
93772 
93773 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
93774 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
93775 /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller */
93776 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
93777 
93778 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
93779 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
93780 /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller */
93781 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
93782 
93783 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U)
93784 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U)
93785 /*! ID_OVERRIDE_EN - TBA */
93786 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK)
93787 
93788 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U)
93789 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U)
93790 /*! ID_OVERRIDE - TBA */
93791 #define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK)
93792 
93793 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
93794 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
93795 /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID */
93796 #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
93797 
93798 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U)
93799 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
93800 /*! PWRUP_CMPS - Enables the VBUS_VALID comparator */
93801 #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
93802 
93803 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
93804 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
93805 /*! DISCHARGE_VBUS - Controls VBUS discharge resistor */
93806 #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
93807 
93808 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)
93809 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)
93810 /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection */
93811 #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)
93812 /*! @} */
93813 
93814 /*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */
93815 /*! @{ */
93816 
93817 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK   (0x1U)
93818 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT  (0U)
93819 /*! SESSEND - Session End indicator
93820  *  0b0..The VBUS voltage is above the Session Valid threshold
93821  *  0b1..The VBUS voltage is below the Session Valid threshold
93822  */
93823 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
93824 
93825 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK    (0x2U)
93826 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT   (1U)
93827 /*! BVALID - B-Device Session Valid status
93828  *  0b0..The VBUS voltage is below the Session Valid threshold
93829  *  0b1..The VBUS voltage is above the Session Valid threshold
93830  */
93831 #define USBPHY_USB1_VBUS_DET_STAT_BVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
93832 
93833 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK    (0x4U)
93834 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT   (2U)
93835 /*! AVALID - A-Device Session Valid status
93836  *  0b0..The VBUS voltage is below the Session Valid threshold
93837  *  0b1..The VBUS voltage is above the Session Valid threshold
93838  */
93839 #define USBPHY_USB1_VBUS_DET_STAT_AVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
93840 
93841 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
93842 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
93843 /*! VBUS_VALID - VBUS voltage status
93844  *  0b0..VBUS is below the comparator threshold
93845  *  0b1..VBUS is above the comparator threshold
93846  */
93847 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)
93848 
93849 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
93850 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
93851 /*! VBUS_VALID_3V - VBUS_VALID_3V detector status
93852  *  0b0..VBUS voltage is below VBUS_VALID_3V threshold
93853  *  0b1..VBUS voltage is above VBUS_VALID_3V threshold
93854  */
93855 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
93856 /*! @} */
93857 
93858 /*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */
93859 /*! @{ */
93860 
93861 #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK   (0x4U)
93862 #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT  (2U)
93863 /*! PULLUP_DP - PULLUP_DP */
93864 #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK)
93865 
93866 #define USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK    (0x800000U)
93867 #define USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT   (23U)
93868 /*! BGR_BIAS - BGR_BIAS
93869  *  0b0..Use local bias powered from USB1_VBUS for 10uA reference (Default)
93870  *  0b1..Use bandgap bias powered from VREGIN0/VREGIN1 for 10uA reference
93871  */
93872 #define USBPHY_USB1_CHRG_DETECT_BGR_BIAS(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK)
93873 /*! @} */
93874 
93875 /*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */
93876 /*! @{ */
93877 
93878 #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U)
93879 #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U)
93880 /*! PULLUP_DP - PULLUP_DP */
93881 #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK)
93882 
93883 #define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK (0x800000U)
93884 #define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT (23U)
93885 /*! BGR_BIAS - BGR_BIAS */
93886 #define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK)
93887 /*! @} */
93888 
93889 /*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */
93890 /*! @{ */
93891 
93892 #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U)
93893 #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U)
93894 /*! PULLUP_DP - PULLUP_DP */
93895 #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK)
93896 
93897 #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK (0x800000U)
93898 #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT (23U)
93899 /*! BGR_BIAS - BGR_BIAS */
93900 #define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK)
93901 /*! @} */
93902 
93903 /*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */
93904 /*! @{ */
93905 
93906 #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U)
93907 #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U)
93908 /*! PULLUP_DP - PULLUP_DP */
93909 #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK)
93910 
93911 #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK (0x800000U)
93912 #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT (23U)
93913 /*! BGR_BIAS - BGR_BIAS */
93914 #define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK)
93915 /*! @} */
93916 
93917 /*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */
93918 /*! @{ */
93919 
93920 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
93921 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
93922 /*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output
93923  *  0b0..No USB cable attachment has been detected
93924  *  0b1..A USB cable attachment between the device and host has been detected
93925  */
93926 #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)
93927 
93928 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
93929 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
93930 /*! CHRG_DETECTED - Battery Charging Primary Detection phase output
93931  *  0b0..Standard Downstream Port (SDP) has been detected
93932  *  0b1..Charging Port has been detected
93933  */
93934 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)
93935 
93936 #define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK  (0x4U)
93937 #define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT (2U)
93938 /*! DN_STATE - DN_STATE
93939  *  0b0..DN pin voltage is < 0.8V
93940  *  0b1..DN pin voltage is > 2.0V
93941  */
93942 #define USBPHY_USB1_CHRG_DET_STAT_DN_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK)
93943 
93944 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK  (0x8U)
93945 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
93946 /*! DP_STATE - DP_STATE
93947  *  0b0..DP pin voltage is < 0.8V
93948  *  0b1..DP pin voltage is > 2.0V
93949  */
93950 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
93951 
93952 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
93953 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
93954 /*! SECDET_DCP - Battery Charging Secondary Detection phase output
93955  *  0b0..Charging Downstream Port (CDP) has been detected
93956  *  0b1..Downstream Charging Port (DCP) has been detected
93957  */
93958 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
93959 /*! @} */
93960 
93961 /*! @name ANACTRL - USB PHY Analog Control Register */
93962 /*! @{ */
93963 
93964 #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK         (0x400U)
93965 #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT        (10U)
93966 /*! DEV_PULLDOWN - DEV_PULLDOWN
93967  *  0b0..The 15kohm nominal pulldowns on the DP and DN pinsare disabled in device mode.
93968  *  0b1..The 15kohm nominal pulldowns on the DP and DN pinsare enabled in device mode.
93969  */
93970 #define USBPHY_ANACTRL_DEV_PULLDOWN(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
93971 /*! @} */
93972 
93973 /*! @name ANACTRL_SET - USB PHY Analog Control Register */
93974 /*! @{ */
93975 
93976 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK     (0x400U)
93977 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT    (10U)
93978 /*! DEV_PULLDOWN - DEV_PULLDOWN */
93979 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
93980 /*! @} */
93981 
93982 /*! @name ANACTRL_CLR - USB PHY Analog Control Register */
93983 /*! @{ */
93984 
93985 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK     (0x400U)
93986 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT    (10U)
93987 /*! DEV_PULLDOWN - DEV_PULLDOWN */
93988 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
93989 /*! @} */
93990 
93991 /*! @name ANACTRL_TOG - USB PHY Analog Control Register */
93992 /*! @{ */
93993 
93994 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK     (0x400U)
93995 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT    (10U)
93996 /*! DEV_PULLDOWN - DEV_PULLDOWN */
93997 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
93998 /*! @} */
93999 
94000 /*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status Register */
94001 /*! @{ */
94002 
94003 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
94004 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
94005 /*! UTMI_TESTSTART - UTMI_TESTSTART */
94006 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)
94007 
94008 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK  (0x2U)
94009 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
94010 /*! UTMI_DIG_TST0 - UTMI_DIG_TST0 */
94011 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)
94012 
94013 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK  (0x4U)
94014 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
94015 /*! UTMI_DIG_TST1 - UTMI_DIG_TST1 */
94016 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)
94017 
94018 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
94019 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
94020 /*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE */
94021 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)
94022 
94023 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U)
94024 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U)
94025 /*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE */
94026 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)
94027 
94028 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK     (0x20U)
94029 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT    (5U)
94030 /*! TSTI_TX_EN - TSTI_TX_EN */
94031 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)
94032 
94033 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK    (0x40U)
94034 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT   (6U)
94035 /*! TSTI_TX_HIZ - TSTI_TX_HIZ */
94036 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)
94037 
94038 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK  (0x80U)
94039 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
94040 /*! UTMO_DIG_TST0 - UTMO_DIG_TST0 */
94041 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)
94042 
94043 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK  (0x100U)
94044 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
94045 /*! UTMO_DIG_TST1 - UTMO_DIG_TST1 */
94046 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)
94047 
94048 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
94049 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
94050 /*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN */
94051 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)
94052 
94053 #define USBPHY_USB1_LOOPBACK_TSTPKT_MASK         (0xFF0000U)
94054 #define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT        (16U)
94055 /*! TSTPKT - TSTPKT */
94056 #define USBPHY_USB1_LOOPBACK_TSTPKT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
94057 /*! @} */
94058 
94059 /*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register */
94060 /*! @{ */
94061 
94062 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
94063 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
94064 /*! UTMI_TESTSTART - UTMI_TESTSTART */
94065 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK)
94066 
94067 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U)
94068 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U)
94069 /*! UTMI_DIG_TST0 - UTMI_DIG_TST0 */
94070 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK)
94071 
94072 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U)
94073 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U)
94074 /*! UTMI_DIG_TST1 - UTMI_DIG_TST1 */
94075 #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK)
94076 
94077 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U)
94078 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U)
94079 /*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE */
94080 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK)
94081 
94082 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U)
94083 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U)
94084 /*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE */
94085 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK)
94086 
94087 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U)
94088 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U)
94089 /*! TSTI_TX_EN - TSTI_TX_EN */
94090 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK)
94091 
94092 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U)
94093 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U)
94094 /*! TSTI_TX_HIZ - TSTI_TX_HIZ */
94095 #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK)
94096 
94097 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U)
94098 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U)
94099 /*! UTMO_DIG_TST0 - UTMO_DIG_TST0 */
94100 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK)
94101 
94102 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U)
94103 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U)
94104 /*! UTMO_DIG_TST1 - UTMO_DIG_TST1 */
94105 #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK)
94106 
94107 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U)
94108 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U)
94109 /*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN */
94110 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)
94111 
94112 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK     (0xFF0000U)
94113 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT    (16U)
94114 /*! TSTPKT - TSTPKT */
94115 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
94116 /*! @} */
94117 
94118 /*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register */
94119 /*! @{ */
94120 
94121 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
94122 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
94123 /*! UTMI_TESTSTART - UTMI_TESTSTART */
94124 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
94125 
94126 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U)
94127 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U)
94128 /*! UTMI_DIG_TST0 - UTMI_DIG_TST0 */
94129 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK)
94130 
94131 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U)
94132 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U)
94133 /*! UTMI_DIG_TST1 - UTMI_DIG_TST1 */
94134 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK)
94135 
94136 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U)
94137 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U)
94138 /*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE */
94139 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK)
94140 
94141 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U)
94142 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U)
94143 /*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE */
94144 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK)
94145 
94146 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U)
94147 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U)
94148 /*! TSTI_TX_EN - TSTI_TX_EN */
94149 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK)
94150 
94151 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U)
94152 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U)
94153 /*! TSTI_TX_HIZ - TSTI_TX_HIZ */
94154 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK)
94155 
94156 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U)
94157 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U)
94158 /*! UTMO_DIG_TST0 - UTMO_DIG_TST0 */
94159 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK)
94160 
94161 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U)
94162 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U)
94163 /*! UTMO_DIG_TST1 - UTMO_DIG_TST1 */
94164 #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK)
94165 
94166 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U)
94167 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U)
94168 /*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN */
94169 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)
94170 
94171 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK     (0xFF0000U)
94172 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT    (16U)
94173 /*! TSTPKT - TSTPKT */
94174 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
94175 /*! @} */
94176 
94177 /*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register */
94178 /*! @{ */
94179 
94180 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
94181 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
94182 /*! UTMI_TESTSTART - UTMI_TESTSTART */
94183 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
94184 
94185 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U)
94186 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U)
94187 /*! UTMI_DIG_TST0 - UTMI_DIG_TST0 */
94188 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK)
94189 
94190 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U)
94191 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U)
94192 /*! UTMI_DIG_TST1 - UTMI_DIG_TST1 */
94193 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK)
94194 
94195 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U)
94196 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U)
94197 /*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE */
94198 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK)
94199 
94200 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U)
94201 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U)
94202 /*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE */
94203 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK)
94204 
94205 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U)
94206 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U)
94207 /*! TSTI_TX_EN - TSTI_TX_EN */
94208 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK)
94209 
94210 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U)
94211 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U)
94212 /*! TSTI_TX_HIZ - TSTI_TX_HIZ */
94213 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK)
94214 
94215 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U)
94216 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U)
94217 /*! UTMO_DIG_TST0 - UTMO_DIG_TST0 */
94218 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK)
94219 
94220 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U)
94221 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U)
94222 /*! UTMO_DIG_TST1 - UTMO_DIG_TST1 */
94223 #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK)
94224 
94225 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U)
94226 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U)
94227 /*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN */
94228 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)
94229 
94230 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK     (0xFF0000U)
94231 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT    (16U)
94232 /*! TSTPKT - TSTPKT */
94233 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
94234 /*! @} */
94235 
94236 /*! @name USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register */
94237 /*! @{ */
94238 
94239 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
94240 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U)
94241 /*! TSTI_HS_NUMBER - TSTI_HS_NUMBER */
94242 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK)
94243 
94244 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
94245 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U)
94246 /*! TSTI_FS_NUMBER - TSTI_FS_NUMBER */
94247 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK)
94248 /*! @} */
94249 
94250 /*! @name USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register */
94251 /*! @{ */
94252 
94253 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU)
94254 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U)
94255 /*! TSTI_HS_NUMBER - TSTI_HS_NUMBER */
94256 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK)
94257 
94258 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
94259 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U)
94260 /*! TSTI_FS_NUMBER - TSTI_FS_NUMBER */
94261 #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK)
94262 /*! @} */
94263 
94264 /*! @name USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register */
94265 /*! @{ */
94266 
94267 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU)
94268 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U)
94269 /*! TSTI_HS_NUMBER - TSTI_HS_NUMBER */
94270 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK)
94271 
94272 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
94273 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U)
94274 /*! TSTI_FS_NUMBER - TSTI_FS_NUMBER */
94275 #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK)
94276 /*! @} */
94277 
94278 /*! @name USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register */
94279 /*! @{ */
94280 
94281 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU)
94282 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U)
94283 /*! TSTI_HS_NUMBER - TSTI_HS_NUMBER */
94284 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK)
94285 
94286 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
94287 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U)
94288 /*! TSTI_FS_NUMBER - TSTI_FS_NUMBER */
94289 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK)
94290 /*! @} */
94291 
94292 /*! @name TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register */
94293 /*! @{ */
94294 
94295 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
94296 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
94297 /*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE */
94298 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK)
94299 
94300 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
94301 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
94302 /*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE */
94303 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
94304 
94305 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
94306 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
94307 /*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE */
94308 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK)
94309 
94310 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
94311 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
94312 /*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE */
94313 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK)
94314 
94315 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
94316 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
94317 /*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE */
94318 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK)
94319 
94320 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
94321 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
94322 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */
94323 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
94324 
94325 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
94326 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
94327 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */
94328 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK)
94329 
94330 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
94331 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
94332 /*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ */
94333 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK)
94334 
94335 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
94336 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
94337 /*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST */
94338 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK)
94339 
94340 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
94341 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
94342 /*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL */
94343 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK)
94344 
94345 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
94346 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
94347 /*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD */
94348 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
94349 
94350 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
94351 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
94352 /*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL */
94353 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK)
94354 
94355 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
94356 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
94357 /*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP */
94358 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK)
94359 
94360 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
94361 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
94362 /*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN */
94363 #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK)
94364 /*! @} */
94365 
94366 /*! @name TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register */
94367 /*! @{ */
94368 
94369 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
94370 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
94371 /*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE */
94372 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK)
94373 
94374 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
94375 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
94376 /*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE */
94377 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
94378 
94379 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
94380 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
94381 /*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE */
94382 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK)
94383 
94384 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
94385 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
94386 /*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE */
94387 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK)
94388 
94389 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
94390 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
94391 /*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE */
94392 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK)
94393 
94394 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
94395 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
94396 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */
94397 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
94398 
94399 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
94400 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
94401 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */
94402 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK)
94403 
94404 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
94405 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
94406 /*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ */
94407 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK)
94408 
94409 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
94410 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
94411 /*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST */
94412 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK)
94413 
94414 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
94415 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
94416 /*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL */
94417 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK)
94418 
94419 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
94420 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
94421 /*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD */
94422 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
94423 
94424 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
94425 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
94426 /*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL */
94427 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK)
94428 
94429 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
94430 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
94431 /*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP */
94432 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK)
94433 
94434 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
94435 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
94436 /*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN */
94437 #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK)
94438 /*! @} */
94439 
94440 /*! @name TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register */
94441 /*! @{ */
94442 
94443 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
94444 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
94445 /*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE */
94446 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK)
94447 
94448 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
94449 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
94450 /*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE */
94451 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
94452 
94453 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
94454 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
94455 /*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE */
94456 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK)
94457 
94458 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
94459 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
94460 /*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE */
94461 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK)
94462 
94463 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
94464 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
94465 /*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE */
94466 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK)
94467 
94468 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
94469 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
94470 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */
94471 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
94472 
94473 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
94474 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
94475 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */
94476 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK)
94477 
94478 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
94479 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
94480 /*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ */
94481 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK)
94482 
94483 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
94484 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
94485 /*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST */
94486 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK)
94487 
94488 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
94489 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
94490 /*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL */
94491 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK)
94492 
94493 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
94494 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
94495 /*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD */
94496 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
94497 
94498 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
94499 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
94500 /*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL */
94501 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK)
94502 
94503 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
94504 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
94505 /*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP */
94506 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK)
94507 
94508 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
94509 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
94510 /*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN */
94511 #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK)
94512 /*! @} */
94513 
94514 /*! @name TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register */
94515 /*! @{ */
94516 
94517 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
94518 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
94519 /*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE */
94520 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK)
94521 
94522 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
94523 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
94524 /*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE */
94525 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
94526 
94527 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
94528 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
94529 /*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE */
94530 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK)
94531 
94532 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
94533 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
94534 /*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE */
94535 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK)
94536 
94537 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
94538 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
94539 /*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE */
94540 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK)
94541 
94542 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
94543 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
94544 /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */
94545 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
94546 
94547 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
94548 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
94549 /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */
94550 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK)
94551 
94552 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
94553 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
94554 /*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ */
94555 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK)
94556 
94557 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
94558 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
94559 /*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST */
94560 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK)
94561 
94562 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
94563 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
94564 /*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL */
94565 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK)
94566 
94567 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
94568 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
94569 /*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD */
94570 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
94571 
94572 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
94573 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
94574 /*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL */
94575 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK)
94576 
94577 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
94578 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
94579 /*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP */
94580 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK)
94581 
94582 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
94583 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
94584 /*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN */
94585 #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK)
94586 /*! @} */
94587 
94588 
94589 /*!
94590  * @}
94591  */ /* end of group USBPHY_Register_Masks */
94592 
94593 
94594 /* USBPHY - Peripheral instance base addresses */
94595 /** Peripheral USBPHY1 base address */
94596 #define USBPHY1_BASE                             (0x40434000u)
94597 /** Peripheral USBPHY1 base pointer */
94598 #define USBPHY1                                  ((USBPHY_Type *)USBPHY1_BASE)
94599 /** Peripheral USBPHY2 base address */
94600 #define USBPHY2_BASE                             (0x40438000u)
94601 /** Peripheral USBPHY2 base pointer */
94602 #define USBPHY2                                  ((USBPHY_Type *)USBPHY2_BASE)
94603 /** Array initializer of USBPHY peripheral base addresses */
94604 #define USBPHY_BASE_ADDRS                        { 0u, USBPHY1_BASE, USBPHY2_BASE }
94605 /** Array initializer of USBPHY peripheral base pointers */
94606 #define USBPHY_BASE_PTRS                         { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
94607 /** Interrupt vectors for the USBPHY peripheral type */
94608 #define USBPHY_IRQS                              { NotAvail_IRQn, USBPHY1_IRQn, USBPHY2_IRQn }
94609 /* Backward compatibility */
94610 #define USBPHY_CTRL_ENDEVPLUGINDET_MASK     USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
94611 #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT    USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
94612 #define USBPHY_CTRL_ENDEVPLUGINDET(x)       USBPHY_CTRL_ENDEVPLUGINDETECT(x)
94613 #define USBPHY_TX_TXCAL45DM_MASK            USBPHY_TX_TXCAL45DN_MASK
94614 #define USBPHY_TX_TXCAL45DM_SHIFT           USBPHY_TX_TXCAL45DN_SHIFT
94615 #define USBPHY_TX_TXCAL45DM(x)              USBPHY_TX_TXCAL45DN(x)
94616 
94617 #define USBPHY_STACK_BASE_ADDRS             { USBPHY1_BASE, USBPHY2_BASE }
94618 
94619 
94620 /*!
94621  * @}
94622  */ /* end of group USBPHY_Peripheral_Access_Layer */
94623 
94624 
94625 /* ----------------------------------------------------------------------------
94626    -- USDHC Peripheral Access Layer
94627    ---------------------------------------------------------------------------- */
94628 
94629 /*!
94630  * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
94631  * @{
94632  */
94633 
94634 /** USDHC - Register Layout Typedef */
94635 typedef struct {
94636   __IO uint32_t DS_ADDR;                           /**< DMA System Address, offset: 0x0 */
94637   __IO uint32_t BLK_ATT;                           /**< Block Attributes, offset: 0x4 */
94638   __IO uint32_t CMD_ARG;                           /**< Command Argument, offset: 0x8 */
94639   __IO uint32_t CMD_XFR_TYP;                       /**< Command Transfer Type, offset: 0xC */
94640   __I  uint32_t CMD_RSP0;                          /**< Command Response0, offset: 0x10 */
94641   __I  uint32_t CMD_RSP1;                          /**< Command Response1, offset: 0x14 */
94642   __I  uint32_t CMD_RSP2;                          /**< Command Response2, offset: 0x18 */
94643   __I  uint32_t CMD_RSP3;                          /**< Command Response3, offset: 0x1C */
94644   __IO uint32_t DATA_BUFF_ACC_PORT;                /**< Data Buffer Access Port, offset: 0x20 */
94645   __I  uint32_t PRES_STATE;                        /**< Present State, offset: 0x24 */
94646   __IO uint32_t PROT_CTRL;                         /**< Protocol Control, offset: 0x28 */
94647   __IO uint32_t SYS_CTRL;                          /**< System Control, offset: 0x2C */
94648   __IO uint32_t INT_STATUS;                        /**< Interrupt Status, offset: 0x30 */
94649   __IO uint32_t INT_STATUS_EN;                     /**< Interrupt Status Enable, offset: 0x34 */
94650   __IO uint32_t INT_SIGNAL_EN;                     /**< Interrupt Signal Enable, offset: 0x38 */
94651   __IO uint32_t AUTOCMD12_ERR_STATUS;              /**< Auto CMD12 Error Status, offset: 0x3C */
94652   __IO uint32_t HOST_CTRL_CAP;                     /**< Host Controller Capabilities, offset: 0x40 */
94653   __IO uint32_t WTMK_LVL;                          /**< Watermark Level, offset: 0x44 */
94654   __IO uint32_t MIX_CTRL;                          /**< Mixer Control, offset: 0x48 */
94655        uint8_t RESERVED_0[4];
94656   __O  uint32_t FORCE_EVENT;                       /**< Force Event, offset: 0x50 */
94657   __I  uint32_t ADMA_ERR_STATUS;                   /**< ADMA Error Status, offset: 0x54 */
94658   __IO uint32_t ADMA_SYS_ADDR;                     /**< ADMA System Address, offset: 0x58 */
94659        uint8_t RESERVED_1[4];
94660   __IO uint32_t DLL_CTRL;                          /**< DLL (Delay Line) Control, offset: 0x60 */
94661   __I  uint32_t DLL_STATUS;                        /**< DLL Status, offset: 0x64 */
94662   __IO uint32_t CLK_TUNE_CTRL_STATUS;              /**< CLK Tuning Control and Status, offset: 0x68 */
94663        uint8_t RESERVED_2[4];
94664   __IO uint32_t STROBE_DLL_CTRL;                   /**< Strobe DLL control, offset: 0x70 */
94665   __I  uint32_t STROBE_DLL_STATUS;                 /**< Strobe DLL status, offset: 0x74 */
94666        uint8_t RESERVED_3[72];
94667   __IO uint32_t VEND_SPEC;                         /**< Vendor Specific Register, offset: 0xC0 */
94668   __IO uint32_t MMC_BOOT;                          /**< MMC Boot, offset: 0xC4 */
94669   __IO uint32_t VEND_SPEC2;                        /**< Vendor Specific 2 Register, offset: 0xC8 */
94670   __IO uint32_t TUNING_CTRL;                       /**< Tuning Control, offset: 0xCC */
94671 } USDHC_Type;
94672 
94673 /* ----------------------------------------------------------------------------
94674    -- USDHC Register Masks
94675    ---------------------------------------------------------------------------- */
94676 
94677 /*!
94678  * @addtogroup USDHC_Register_Masks USDHC Register Masks
94679  * @{
94680  */
94681 
94682 /*! @name DS_ADDR - DMA System Address */
94683 /*! @{ */
94684 
94685 #define USDHC_DS_ADDR_DS_ADDR_MASK               (0xFFFFFFFFU)
94686 #define USDHC_DS_ADDR_DS_ADDR_SHIFT              (0U)
94687 /*! DS_ADDR - System address */
94688 #define USDHC_DS_ADDR_DS_ADDR(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
94689 /*! @} */
94690 
94691 /*! @name BLK_ATT - Block Attributes */
94692 /*! @{ */
94693 
94694 #define USDHC_BLK_ATT_BLKSIZE_MASK               (0x1FFFU)
94695 #define USDHC_BLK_ATT_BLKSIZE_SHIFT              (0U)
94696 /*! BLKSIZE - Transfer block size
94697  *  0b1000000000000..4096 bytes
94698  *  0b0100000000000..2048 bytes
94699  *  0b0001000000000..512 bytes
94700  *  0b0000111111111..511 bytes
94701  *  0b0000000000100..4 bytes
94702  *  0b0000000000011..3 bytes
94703  *  0b0000000000010..2 bytes
94704  *  0b0000000000001..1 byte
94705  *  0b0000000000000..No data transfer
94706  */
94707 #define USDHC_BLK_ATT_BLKSIZE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
94708 
94709 #define USDHC_BLK_ATT_BLKCNT_MASK                (0xFFFF0000U)
94710 #define USDHC_BLK_ATT_BLKCNT_SHIFT               (16U)
94711 /*! BLKCNT - Blocks count for current transfer
94712  *  0b1111111111111111..65535 blocks
94713  *  0b0000000000000010..2 blocks
94714  *  0b0000000000000001..1 block
94715  *  0b0000000000000000..Stop count
94716  */
94717 #define USDHC_BLK_ATT_BLKCNT(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
94718 /*! @} */
94719 
94720 /*! @name CMD_ARG - Command Argument */
94721 /*! @{ */
94722 
94723 #define USDHC_CMD_ARG_CMDARG_MASK                (0xFFFFFFFFU)
94724 #define USDHC_CMD_ARG_CMDARG_SHIFT               (0U)
94725 /*! CMDARG - Command argument */
94726 #define USDHC_CMD_ARG_CMDARG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
94727 /*! @} */
94728 
94729 /*! @name CMD_XFR_TYP - Command Transfer Type */
94730 /*! @{ */
94731 
94732 #define USDHC_CMD_XFR_TYP_RSPTYP_MASK            (0x30000U)
94733 #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT           (16U)
94734 /*! RSPTYP - Response type select
94735  *  0b00..No response
94736  *  0b01..Response length 136
94737  *  0b10..Response length 48
94738  *  0b11..Response length 48, check busy after response
94739  */
94740 #define USDHC_CMD_XFR_TYP_RSPTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
94741 
94742 #define USDHC_CMD_XFR_TYP_CCCEN_MASK             (0x80000U)
94743 #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT            (19U)
94744 /*! CCCEN - Command CRC check enable
94745  *  0b1..Enables command CRC check
94746  *  0b0..Disables command CRC check
94747  */
94748 #define USDHC_CMD_XFR_TYP_CCCEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
94749 
94750 #define USDHC_CMD_XFR_TYP_CICEN_MASK             (0x100000U)
94751 #define USDHC_CMD_XFR_TYP_CICEN_SHIFT            (20U)
94752 /*! CICEN - Command index check enable
94753  *  0b1..Enables command index check
94754  *  0b0..Disable command index check
94755  */
94756 #define USDHC_CMD_XFR_TYP_CICEN(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
94757 
94758 #define USDHC_CMD_XFR_TYP_DPSEL_MASK             (0x200000U)
94759 #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT            (21U)
94760 /*! DPSEL - Data present select
94761  *  0b1..Data present
94762  *  0b0..No data present
94763  */
94764 #define USDHC_CMD_XFR_TYP_DPSEL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
94765 
94766 #define USDHC_CMD_XFR_TYP_CMDTYP_MASK            (0xC00000U)
94767 #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT           (22U)
94768 /*! CMDTYP - Command type
94769  *  0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
94770  *  0b10..Resume CMD52 for writing function select in CCCR
94771  *  0b01..Suspend CMD52 for writing bus suspend in CCCR
94772  *  0b00..Normal other commands
94773  */
94774 #define USDHC_CMD_XFR_TYP_CMDTYP(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
94775 
94776 #define USDHC_CMD_XFR_TYP_CMDINX_MASK            (0x3F000000U)
94777 #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT           (24U)
94778 /*! CMDINX - Command index */
94779 #define USDHC_CMD_XFR_TYP_CMDINX(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
94780 /*! @} */
94781 
94782 /*! @name CMD_RSP0 - Command Response0 */
94783 /*! @{ */
94784 
94785 #define USDHC_CMD_RSP0_CMDRSP0_MASK              (0xFFFFFFFFU)
94786 #define USDHC_CMD_RSP0_CMDRSP0_SHIFT             (0U)
94787 /*! CMDRSP0 - Command response 0 */
94788 #define USDHC_CMD_RSP0_CMDRSP0(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
94789 /*! @} */
94790 
94791 /*! @name CMD_RSP1 - Command Response1 */
94792 /*! @{ */
94793 
94794 #define USDHC_CMD_RSP1_CMDRSP1_MASK              (0xFFFFFFFFU)
94795 #define USDHC_CMD_RSP1_CMDRSP1_SHIFT             (0U)
94796 /*! CMDRSP1 - Command response 1 */
94797 #define USDHC_CMD_RSP1_CMDRSP1(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
94798 /*! @} */
94799 
94800 /*! @name CMD_RSP2 - Command Response2 */
94801 /*! @{ */
94802 
94803 #define USDHC_CMD_RSP2_CMDRSP2_MASK              (0xFFFFFFFFU)
94804 #define USDHC_CMD_RSP2_CMDRSP2_SHIFT             (0U)
94805 /*! CMDRSP2 - Command response 2 */
94806 #define USDHC_CMD_RSP2_CMDRSP2(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
94807 /*! @} */
94808 
94809 /*! @name CMD_RSP3 - Command Response3 */
94810 /*! @{ */
94811 
94812 #define USDHC_CMD_RSP3_CMDRSP3_MASK              (0xFFFFFFFFU)
94813 #define USDHC_CMD_RSP3_CMDRSP3_SHIFT             (0U)
94814 /*! CMDRSP3 - Command response 3 */
94815 #define USDHC_CMD_RSP3_CMDRSP3(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
94816 /*! @} */
94817 
94818 /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
94819 /*! @{ */
94820 
94821 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK    (0xFFFFFFFFU)
94822 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT   (0U)
94823 /*! DATCONT - Data content */
94824 #define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
94825 /*! @} */
94826 
94827 /*! @name PRES_STATE - Present State */
94828 /*! @{ */
94829 
94830 #define USDHC_PRES_STATE_CIHB_MASK               (0x1U)
94831 #define USDHC_PRES_STATE_CIHB_SHIFT              (0U)
94832 /*! CIHB - Command inhibit (CMD)
94833  *  0b1..Cannot issue command
94834  *  0b0..Can issue command using only CMD line
94835  */
94836 #define USDHC_PRES_STATE_CIHB(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
94837 
94838 #define USDHC_PRES_STATE_CDIHB_MASK              (0x2U)
94839 #define USDHC_PRES_STATE_CDIHB_SHIFT             (1U)
94840 /*! CDIHB - Command Inhibit Data (DATA)
94841  *  0b1..Cannot issue command that uses the DATA line
94842  *  0b0..Can issue command that uses the DATA line
94843  */
94844 #define USDHC_PRES_STATE_CDIHB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
94845 
94846 #define USDHC_PRES_STATE_DLA_MASK                (0x4U)
94847 #define USDHC_PRES_STATE_DLA_SHIFT               (2U)
94848 /*! DLA - Data line active
94849  *  0b1..DATA line active
94850  *  0b0..DATA line inactive
94851  */
94852 #define USDHC_PRES_STATE_DLA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
94853 
94854 #define USDHC_PRES_STATE_SDSTB_MASK              (0x8U)
94855 #define USDHC_PRES_STATE_SDSTB_SHIFT             (3U)
94856 /*! SDSTB - SD clock stable
94857  *  0b1..Clock is stable.
94858  *  0b0..Clock is changing frequency and not stable.
94859  */
94860 #define USDHC_PRES_STATE_SDSTB(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
94861 
94862 #define USDHC_PRES_STATE_IPGOFF_MASK             (0x10U)
94863 #define USDHC_PRES_STATE_IPGOFF_SHIFT            (4U)
94864 /*! IPGOFF - Peripheral clock gated off internally
94865  *  0b1..Peripheral clock is gated off.
94866  *  0b0..Peripheral clock is active.
94867  */
94868 #define USDHC_PRES_STATE_IPGOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
94869 
94870 #define USDHC_PRES_STATE_HCKOFF_MASK             (0x20U)
94871 #define USDHC_PRES_STATE_HCKOFF_SHIFT            (5U)
94872 /*! HCKOFF - HCLK gated off internally
94873  *  0b1..HCLK is gated off.
94874  *  0b0..HCLK is active.
94875  */
94876 #define USDHC_PRES_STATE_HCKOFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
94877 
94878 #define USDHC_PRES_STATE_PEROFF_MASK             (0x40U)
94879 #define USDHC_PRES_STATE_PEROFF_SHIFT            (6U)
94880 /*! PEROFF - IPG_PERCLK gated off internally
94881  *  0b1..IPG_PERCLK is gated off.
94882  *  0b0..IPG_PERCLK is active.
94883  */
94884 #define USDHC_PRES_STATE_PEROFF(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
94885 
94886 #define USDHC_PRES_STATE_SDOFF_MASK              (0x80U)
94887 #define USDHC_PRES_STATE_SDOFF_SHIFT             (7U)
94888 /*! SDOFF - SD clock gated off internally
94889  *  0b1..SD clock is gated off.
94890  *  0b0..SD clock is active.
94891  */
94892 #define USDHC_PRES_STATE_SDOFF(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
94893 
94894 #define USDHC_PRES_STATE_WTA_MASK                (0x100U)
94895 #define USDHC_PRES_STATE_WTA_SHIFT               (8U)
94896 /*! WTA - Write transfer active
94897  *  0b1..Transferring data
94898  *  0b0..No valid data
94899  */
94900 #define USDHC_PRES_STATE_WTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
94901 
94902 #define USDHC_PRES_STATE_RTA_MASK                (0x200U)
94903 #define USDHC_PRES_STATE_RTA_SHIFT               (9U)
94904 /*! RTA - Read transfer active
94905  *  0b1..Transferring data
94906  *  0b0..No valid data
94907  */
94908 #define USDHC_PRES_STATE_RTA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
94909 
94910 #define USDHC_PRES_STATE_BWEN_MASK               (0x400U)
94911 #define USDHC_PRES_STATE_BWEN_SHIFT              (10U)
94912 /*! BWEN - Buffer write enable
94913  *  0b1..Write enable
94914  *  0b0..Write disable
94915  */
94916 #define USDHC_PRES_STATE_BWEN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
94917 
94918 #define USDHC_PRES_STATE_BREN_MASK               (0x800U)
94919 #define USDHC_PRES_STATE_BREN_SHIFT              (11U)
94920 /*! BREN - Buffer read enable
94921  *  0b1..Read enable
94922  *  0b0..Read disable
94923  */
94924 #define USDHC_PRES_STATE_BREN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
94925 
94926 #define USDHC_PRES_STATE_RTR_MASK                (0x1000U)
94927 #define USDHC_PRES_STATE_RTR_SHIFT               (12U)
94928 /*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode,and EMMC HS200 mode)
94929  *  0b1..Sampling clock needs re-tuning
94930  *  0b0..Fixed or well tuned sampling clock
94931  */
94932 #define USDHC_PRES_STATE_RTR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
94933 
94934 #define USDHC_PRES_STATE_TSCD_MASK               (0x8000U)
94935 #define USDHC_PRES_STATE_TSCD_SHIFT              (15U)
94936 /*! TSCD - Tap select change done
94937  *  0b1..Delay cell select change is finished.
94938  *  0b0..Delay cell select change is not finished.
94939  */
94940 #define USDHC_PRES_STATE_TSCD(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
94941 
94942 #define USDHC_PRES_STATE_CINST_MASK              (0x10000U)
94943 #define USDHC_PRES_STATE_CINST_SHIFT             (16U)
94944 /*! CINST - Card inserted
94945  *  0b1..Card inserted
94946  *  0b0..Power on reset or no card
94947  */
94948 #define USDHC_PRES_STATE_CINST(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
94949 
94950 #define USDHC_PRES_STATE_CDPL_MASK               (0x40000U)
94951 #define USDHC_PRES_STATE_CDPL_SHIFT              (18U)
94952 /*! CDPL - Card detect pin level
94953  *  0b1..Card present (CD_B = 0)
94954  *  0b0..No card present (CD_B = 1)
94955  */
94956 #define USDHC_PRES_STATE_CDPL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
94957 
94958 #define USDHC_PRES_STATE_WPSPL_MASK              (0x80000U)
94959 #define USDHC_PRES_STATE_WPSPL_SHIFT             (19U)
94960 /*! WPSPL - Write protect switch pin level
94961  *  0b1..Write enabled (WP = 0)
94962  *  0b0..Write protected (WP = 1)
94963  */
94964 #define USDHC_PRES_STATE_WPSPL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
94965 
94966 #define USDHC_PRES_STATE_CLSL_MASK               (0x800000U)
94967 #define USDHC_PRES_STATE_CLSL_SHIFT              (23U)
94968 /*! CLSL - CMD line signal level */
94969 #define USDHC_PRES_STATE_CLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
94970 
94971 #define USDHC_PRES_STATE_DLSL_MASK               (0xFF000000U)
94972 #define USDHC_PRES_STATE_DLSL_SHIFT              (24U)
94973 /*! DLSL - DATA[7:0] line signal level
94974  *  0b00000111..Data 7 line signal level
94975  *  0b00000110..Data 6 line signal level
94976  *  0b00000101..Data 5 line signal level
94977  *  0b00000100..Data 4 line signal level
94978  *  0b00000011..Data 3 line signal level
94979  *  0b00000010..Data 2 line signal level
94980  *  0b00000001..Data 1 line signal level
94981  *  0b00000000..Data 0 line signal level
94982  */
94983 #define USDHC_PRES_STATE_DLSL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
94984 /*! @} */
94985 
94986 /*! @name PROT_CTRL - Protocol Control */
94987 /*! @{ */
94988 
94989 #define USDHC_PROT_CTRL_DTW_MASK                 (0x6U)
94990 #define USDHC_PROT_CTRL_DTW_SHIFT                (1U)
94991 /*! DTW - Data transfer width
94992  *  0b10..8-bit mode
94993  *  0b01..4-bit mode
94994  *  0b00..1-bit mode
94995  *  0b11..Reserved
94996  */
94997 #define USDHC_PROT_CTRL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
94998 
94999 #define USDHC_PROT_CTRL_D3CD_MASK                (0x8U)
95000 #define USDHC_PROT_CTRL_D3CD_SHIFT               (3U)
95001 /*! D3CD - DATA3 as card detection pin
95002  *  0b1..DATA3 as card detection pin
95003  *  0b0..DATA3 does not monitor card insertion
95004  */
95005 #define USDHC_PROT_CTRL_D3CD(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
95006 
95007 #define USDHC_PROT_CTRL_EMODE_MASK               (0x30U)
95008 #define USDHC_PROT_CTRL_EMODE_SHIFT              (4U)
95009 /*! EMODE - Endian mode
95010  *  0b00..Big endian mode
95011  *  0b01..Half word big endian mode
95012  *  0b10..Little endian mode
95013  *  0b11..Reserved
95014  */
95015 #define USDHC_PROT_CTRL_EMODE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
95016 
95017 #define USDHC_PROT_CTRL_CDTL_MASK                (0x40U)
95018 #define USDHC_PROT_CTRL_CDTL_SHIFT               (6U)
95019 /*! CDTL - Card detect test level
95020  *  0b1..Card detect test level is 1, card inserted
95021  *  0b0..Card detect test level is 0, no card inserted
95022  */
95023 #define USDHC_PROT_CTRL_CDTL(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
95024 
95025 #define USDHC_PROT_CTRL_CDSS_MASK                (0x80U)
95026 #define USDHC_PROT_CTRL_CDSS_SHIFT               (7U)
95027 /*! CDSS - Card detect signal selection
95028  *  0b1..Card detection test level is selected (for test purpose).
95029  *  0b0..Card detection level is selected (for normal purpose).
95030  */
95031 #define USDHC_PROT_CTRL_CDSS(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
95032 
95033 #define USDHC_PROT_CTRL_DMASEL_MASK              (0x300U)
95034 #define USDHC_PROT_CTRL_DMASEL_SHIFT             (8U)
95035 /*! DMASEL - DMA select
95036  *  0b00..No DMA or simple DMA is selected.
95037  *  0b01..ADMA1 is selected.
95038  *  0b10..ADMA2 is selected.
95039  *  0b11..Reserved
95040  */
95041 #define USDHC_PROT_CTRL_DMASEL(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
95042 
95043 #define USDHC_PROT_CTRL_SABGREQ_MASK             (0x10000U)
95044 #define USDHC_PROT_CTRL_SABGREQ_SHIFT            (16U)
95045 /*! SABGREQ - Stop at block gap request
95046  *  0b1..Stop
95047  *  0b0..Transfer
95048  */
95049 #define USDHC_PROT_CTRL_SABGREQ(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
95050 
95051 #define USDHC_PROT_CTRL_CREQ_MASK                (0x20000U)
95052 #define USDHC_PROT_CTRL_CREQ_SHIFT               (17U)
95053 /*! CREQ - Continue request
95054  *  0b1..Restart
95055  *  0b0..No effect
95056  */
95057 #define USDHC_PROT_CTRL_CREQ(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
95058 
95059 #define USDHC_PROT_CTRL_RWCTL_MASK               (0x40000U)
95060 #define USDHC_PROT_CTRL_RWCTL_SHIFT              (18U)
95061 /*! RWCTL - Read wait control
95062  *  0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set
95063  *  0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set
95064  */
95065 #define USDHC_PROT_CTRL_RWCTL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
95066 
95067 #define USDHC_PROT_CTRL_IABG_MASK                (0x80000U)
95068 #define USDHC_PROT_CTRL_IABG_SHIFT               (19U)
95069 /*! IABG - Interrupt at block gap
95070  *  0b1..Enables interrupt at block gap
95071  *  0b0..Disables interrupt at block gap
95072  */
95073 #define USDHC_PROT_CTRL_IABG(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
95074 
95075 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK     (0x100000U)
95076 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT    (20U)
95077 /*! RD_DONE_NO_8CLK - Read performed number 8 clock */
95078 #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
95079 
95080 #define USDHC_PROT_CTRL_WECINT_MASK              (0x1000000U)
95081 #define USDHC_PROT_CTRL_WECINT_SHIFT             (24U)
95082 /*! WECINT - Wakeup event enable on card interrupt
95083  *  0b1..Enables wakeup event enable on card interrupt
95084  *  0b0..Disables wakeup event enable on card interrupt
95085  */
95086 #define USDHC_PROT_CTRL_WECINT(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
95087 
95088 #define USDHC_PROT_CTRL_WECINS_MASK              (0x2000000U)
95089 #define USDHC_PROT_CTRL_WECINS_SHIFT             (25U)
95090 /*! WECINS - Wakeup event enable on SD card insertion
95091  *  0b1..Enable wakeup event enable on SD card insertion
95092  *  0b0..Disable wakeup event enable on SD card insertion
95093  */
95094 #define USDHC_PROT_CTRL_WECINS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
95095 
95096 #define USDHC_PROT_CTRL_WECRM_MASK               (0x4000000U)
95097 #define USDHC_PROT_CTRL_WECRM_SHIFT              (26U)
95098 /*! WECRM - Wakeup event enable on SD card removal
95099  *  0b1..Enables wakeup event enable on SD card removal
95100  *  0b0..Disables wakeup event enable on SD card removal
95101  */
95102 #define USDHC_PROT_CTRL_WECRM(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
95103 
95104 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK    (0x40000000U)
95105 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT   (30U)
95106 /*! NON_EXACT_BLK_RD - Non-exact block read
95107  *  0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
95108  *  0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.
95109  */
95110 #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
95111 /*! @} */
95112 
95113 /*! @name SYS_CTRL - System Control */
95114 /*! @{ */
95115 
95116 #define USDHC_SYS_CTRL_DVS_MASK                  (0xF0U)
95117 #define USDHC_SYS_CTRL_DVS_SHIFT                 (4U)
95118 /*! DVS - Divisor
95119  *  0b0000..Divide-by-1
95120  *  0b0001..Divide-by-2
95121  *  0b1110..Divide-by-15
95122  *  0b1111..Divide-by-16
95123  */
95124 #define USDHC_SYS_CTRL_DVS(x)                    (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
95125 
95126 #define USDHC_SYS_CTRL_SDCLKFS_MASK              (0xFF00U)
95127 #define USDHC_SYS_CTRL_SDCLKFS_SHIFT             (8U)
95128 /*! SDCLKFS - SDCLK frequency select */
95129 #define USDHC_SYS_CTRL_SDCLKFS(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
95130 
95131 #define USDHC_SYS_CTRL_DTOCV_MASK                (0xF0000U)
95132 #define USDHC_SYS_CTRL_DTOCV_SHIFT               (16U)
95133 /*! DTOCV - Data timeout counter value
95134  *  0b1111..SDCLK x 2 29
95135  *  0b1110..SDCLK x 2 28
95136  *  0b1101..SDCLK x 2 27
95137  *  0b1100..SDCLK x 2 26
95138  *  0b1011..SDCLK x 2 25
95139  *  0b1010..SDCLK x 2 24
95140  *  0b1001..SDCLK x 2 23
95141  *  0b1000..SDCLK x 2 22
95142  *  0b0111..SDCLK x 2 21
95143  *  0b0110..SDCLK x 2 20
95144  *  0b0101..SDCLK x 2 19
95145  *  0b0100..SDCLK x 2 18
95146  *  0b0011..SDCLK x 2 17
95147  *  0b0010..SDCLK x 2 16
95148  *  0b0001..SDCLK x 2 15
95149  *  0b0000..SDCLK x 2 14
95150  */
95151 #define USDHC_SYS_CTRL_DTOCV(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
95152 
95153 #define USDHC_SYS_CTRL_IPP_RST_N_MASK            (0x800000U)
95154 #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT           (23U)
95155 /*! IPP_RST_N - Hardware reset */
95156 #define USDHC_SYS_CTRL_IPP_RST_N(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
95157 
95158 #define USDHC_SYS_CTRL_RSTA_MASK                 (0x1000000U)
95159 #define USDHC_SYS_CTRL_RSTA_SHIFT                (24U)
95160 /*! RSTA - Software reset for all
95161  *  0b1..Reset
95162  *  0b0..No reset
95163  */
95164 #define USDHC_SYS_CTRL_RSTA(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
95165 
95166 #define USDHC_SYS_CTRL_RSTC_MASK                 (0x2000000U)
95167 #define USDHC_SYS_CTRL_RSTC_SHIFT                (25U)
95168 /*! RSTC - Software reset for CMD line
95169  *  0b1..Reset
95170  *  0b0..No reset
95171  */
95172 #define USDHC_SYS_CTRL_RSTC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
95173 
95174 #define USDHC_SYS_CTRL_RSTD_MASK                 (0x4000000U)
95175 #define USDHC_SYS_CTRL_RSTD_SHIFT                (26U)
95176 /*! RSTD - Software reset for data line
95177  *  0b1..Reset
95178  *  0b0..No reset
95179  */
95180 #define USDHC_SYS_CTRL_RSTD(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
95181 
95182 #define USDHC_SYS_CTRL_INITA_MASK                (0x8000000U)
95183 #define USDHC_SYS_CTRL_INITA_SHIFT               (27U)
95184 /*! INITA - Initialization active */
95185 #define USDHC_SYS_CTRL_INITA(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
95186 
95187 #define USDHC_SYS_CTRL_RSTT_MASK                 (0x10000000U)
95188 #define USDHC_SYS_CTRL_RSTT_SHIFT                (28U)
95189 /*! RSTT - Reset tuning */
95190 #define USDHC_SYS_CTRL_RSTT(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
95191 /*! @} */
95192 
95193 /*! @name INT_STATUS - Interrupt Status */
95194 /*! @{ */
95195 
95196 #define USDHC_INT_STATUS_CC_MASK                 (0x1U)
95197 #define USDHC_INT_STATUS_CC_SHIFT                (0U)
95198 /*! CC - Command complete
95199  *  0b1..Command complete
95200  *  0b0..Command not complete
95201  */
95202 #define USDHC_INT_STATUS_CC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
95203 
95204 #define USDHC_INT_STATUS_TC_MASK                 (0x2U)
95205 #define USDHC_INT_STATUS_TC_SHIFT                (1U)
95206 /*! TC - Transfer complete
95207  *  0b1..Transfer complete
95208  *  0b0..Transfer does not complete
95209  */
95210 #define USDHC_INT_STATUS_TC(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
95211 
95212 #define USDHC_INT_STATUS_BGE_MASK                (0x4U)
95213 #define USDHC_INT_STATUS_BGE_SHIFT               (2U)
95214 /*! BGE - Block gap event
95215  *  0b1..Transaction stopped at block gap
95216  *  0b0..No block gap event
95217  */
95218 #define USDHC_INT_STATUS_BGE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
95219 
95220 #define USDHC_INT_STATUS_DINT_MASK               (0x8U)
95221 #define USDHC_INT_STATUS_DINT_SHIFT              (3U)
95222 /*! DINT - DMA interrupt
95223  *  0b1..DMA interrupt is generated.
95224  *  0b0..No DMA interrupt
95225  */
95226 #define USDHC_INT_STATUS_DINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
95227 
95228 #define USDHC_INT_STATUS_BWR_MASK                (0x10U)
95229 #define USDHC_INT_STATUS_BWR_SHIFT               (4U)
95230 /*! BWR - Buffer write ready
95231  *  0b1..Ready to write buffer
95232  *  0b0..Not ready to write buffer
95233  */
95234 #define USDHC_INT_STATUS_BWR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
95235 
95236 #define USDHC_INT_STATUS_BRR_MASK                (0x20U)
95237 #define USDHC_INT_STATUS_BRR_SHIFT               (5U)
95238 /*! BRR - Buffer read ready
95239  *  0b1..Ready to read buffer
95240  *  0b0..Not ready to read buffer
95241  */
95242 #define USDHC_INT_STATUS_BRR(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
95243 
95244 #define USDHC_INT_STATUS_CINS_MASK               (0x40U)
95245 #define USDHC_INT_STATUS_CINS_SHIFT              (6U)
95246 /*! CINS - Card insertion
95247  *  0b1..Card inserted
95248  *  0b0..Card state unstable or removed
95249  */
95250 #define USDHC_INT_STATUS_CINS(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
95251 
95252 #define USDHC_INT_STATUS_CRM_MASK                (0x80U)
95253 #define USDHC_INT_STATUS_CRM_SHIFT               (7U)
95254 /*! CRM - Card removal
95255  *  0b1..Card removed
95256  *  0b0..Card state unstable or inserted
95257  */
95258 #define USDHC_INT_STATUS_CRM(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
95259 
95260 #define USDHC_INT_STATUS_CINT_MASK               (0x100U)
95261 #define USDHC_INT_STATUS_CINT_SHIFT              (8U)
95262 /*! CINT - Card interrupt
95263  *  0b1..Generate card interrupt
95264  *  0b0..No card interrupt
95265  */
95266 #define USDHC_INT_STATUS_CINT(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
95267 
95268 #define USDHC_INT_STATUS_RTE_MASK                (0x1000U)
95269 #define USDHC_INT_STATUS_RTE_SHIFT               (12U)
95270 /*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
95271  *  0b1..Re-tuning should be performed.
95272  *  0b0..Re-tuning is not required.
95273  */
95274 #define USDHC_INT_STATUS_RTE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
95275 
95276 #define USDHC_INT_STATUS_TP_MASK                 (0x4000U)
95277 #define USDHC_INT_STATUS_TP_SHIFT                (14U)
95278 /*! TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode) */
95279 #define USDHC_INT_STATUS_TP(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
95280 
95281 #define USDHC_INT_STATUS_CTOE_MASK               (0x10000U)
95282 #define USDHC_INT_STATUS_CTOE_SHIFT              (16U)
95283 /*! CTOE - Command timeout error
95284  *  0b1..Time out
95285  *  0b0..No error
95286  */
95287 #define USDHC_INT_STATUS_CTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
95288 
95289 #define USDHC_INT_STATUS_CCE_MASK                (0x20000U)
95290 #define USDHC_INT_STATUS_CCE_SHIFT               (17U)
95291 /*! CCE - Command CRC error
95292  *  0b1..CRC error generated
95293  *  0b0..No error
95294  */
95295 #define USDHC_INT_STATUS_CCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
95296 
95297 #define USDHC_INT_STATUS_CEBE_MASK               (0x40000U)
95298 #define USDHC_INT_STATUS_CEBE_SHIFT              (18U)
95299 /*! CEBE - Command end bit error
95300  *  0b1..End bit error generated
95301  *  0b0..No error
95302  */
95303 #define USDHC_INT_STATUS_CEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
95304 
95305 #define USDHC_INT_STATUS_CIE_MASK                (0x80000U)
95306 #define USDHC_INT_STATUS_CIE_SHIFT               (19U)
95307 /*! CIE - Command index error
95308  *  0b1..Error
95309  *  0b0..No error
95310  */
95311 #define USDHC_INT_STATUS_CIE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
95312 
95313 #define USDHC_INT_STATUS_DTOE_MASK               (0x100000U)
95314 #define USDHC_INT_STATUS_DTOE_SHIFT              (20U)
95315 /*! DTOE - Data timeout error
95316  *  0b1..Time out
95317  *  0b0..No error
95318  */
95319 #define USDHC_INT_STATUS_DTOE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
95320 
95321 #define USDHC_INT_STATUS_DCE_MASK                (0x200000U)
95322 #define USDHC_INT_STATUS_DCE_SHIFT               (21U)
95323 /*! DCE - Data CRC error
95324  *  0b1..Error
95325  *  0b0..No error
95326  */
95327 #define USDHC_INT_STATUS_DCE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
95328 
95329 #define USDHC_INT_STATUS_DEBE_MASK               (0x400000U)
95330 #define USDHC_INT_STATUS_DEBE_SHIFT              (22U)
95331 /*! DEBE - Data end bit error
95332  *  0b1..Error
95333  *  0b0..No error
95334  */
95335 #define USDHC_INT_STATUS_DEBE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
95336 
95337 #define USDHC_INT_STATUS_AC12E_MASK              (0x1000000U)
95338 #define USDHC_INT_STATUS_AC12E_SHIFT             (24U)
95339 /*! AC12E - Auto CMD12 error
95340  *  0b1..Error
95341  *  0b0..No error
95342  */
95343 #define USDHC_INT_STATUS_AC12E(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
95344 
95345 #define USDHC_INT_STATUS_TNE_MASK                (0x4000000U)
95346 #define USDHC_INT_STATUS_TNE_SHIFT               (26U)
95347 /*! TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode) */
95348 #define USDHC_INT_STATUS_TNE(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
95349 
95350 #define USDHC_INT_STATUS_DMAE_MASK               (0x10000000U)
95351 #define USDHC_INT_STATUS_DMAE_SHIFT              (28U)
95352 /*! DMAE - DMA error
95353  *  0b1..Error
95354  *  0b0..No error
95355  */
95356 #define USDHC_INT_STATUS_DMAE(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
95357 /*! @} */
95358 
95359 /*! @name INT_STATUS_EN - Interrupt Status Enable */
95360 /*! @{ */
95361 
95362 #define USDHC_INT_STATUS_EN_CCSEN_MASK           (0x1U)
95363 #define USDHC_INT_STATUS_EN_CCSEN_SHIFT          (0U)
95364 /*! CCSEN - Command complete status enable
95365  *  0b1..Enabled
95366  *  0b0..Masked
95367  */
95368 #define USDHC_INT_STATUS_EN_CCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
95369 
95370 #define USDHC_INT_STATUS_EN_TCSEN_MASK           (0x2U)
95371 #define USDHC_INT_STATUS_EN_TCSEN_SHIFT          (1U)
95372 /*! TCSEN - Transfer complete status enable
95373  *  0b1..Enabled
95374  *  0b0..Masked
95375  */
95376 #define USDHC_INT_STATUS_EN_TCSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
95377 
95378 #define USDHC_INT_STATUS_EN_BGESEN_MASK          (0x4U)
95379 #define USDHC_INT_STATUS_EN_BGESEN_SHIFT         (2U)
95380 /*! BGESEN - Block gap event status enable
95381  *  0b1..Enabled
95382  *  0b0..Masked
95383  */
95384 #define USDHC_INT_STATUS_EN_BGESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
95385 
95386 #define USDHC_INT_STATUS_EN_DINTSEN_MASK         (0x8U)
95387 #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT        (3U)
95388 /*! DINTSEN - DMA interrupt status enable
95389  *  0b1..Enabled
95390  *  0b0..Masked
95391  */
95392 #define USDHC_INT_STATUS_EN_DINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
95393 
95394 #define USDHC_INT_STATUS_EN_BWRSEN_MASK          (0x10U)
95395 #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT         (4U)
95396 /*! BWRSEN - Buffer write ready status enable
95397  *  0b1..Enabled
95398  *  0b0..Masked
95399  */
95400 #define USDHC_INT_STATUS_EN_BWRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
95401 
95402 #define USDHC_INT_STATUS_EN_BRRSEN_MASK          (0x20U)
95403 #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT         (5U)
95404 /*! BRRSEN - Buffer read ready status enable
95405  *  0b1..Enabled
95406  *  0b0..Masked
95407  */
95408 #define USDHC_INT_STATUS_EN_BRRSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
95409 
95410 #define USDHC_INT_STATUS_EN_CINSSEN_MASK         (0x40U)
95411 #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT        (6U)
95412 /*! CINSSEN - Card insertion status enable
95413  *  0b1..Enabled
95414  *  0b0..Masked
95415  */
95416 #define USDHC_INT_STATUS_EN_CINSSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
95417 
95418 #define USDHC_INT_STATUS_EN_CRMSEN_MASK          (0x80U)
95419 #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT         (7U)
95420 /*! CRMSEN - Card removal status enable
95421  *  0b1..Enabled
95422  *  0b0..Masked
95423  */
95424 #define USDHC_INT_STATUS_EN_CRMSEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
95425 
95426 #define USDHC_INT_STATUS_EN_CINTSEN_MASK         (0x100U)
95427 #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT        (8U)
95428 /*! CINTSEN - Card interrupt status enable
95429  *  0b1..Enabled
95430  *  0b0..Masked
95431  */
95432 #define USDHC_INT_STATUS_EN_CINTSEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
95433 
95434 #define USDHC_INT_STATUS_EN_RTESEN_MASK          (0x1000U)
95435 #define USDHC_INT_STATUS_EN_RTESEN_SHIFT         (12U)
95436 /*! RTESEN - Re-tuning event status enable
95437  *  0b1..Enabled
95438  *  0b0..Masked
95439  */
95440 #define USDHC_INT_STATUS_EN_RTESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
95441 
95442 #define USDHC_INT_STATUS_EN_TPSEN_MASK           (0x4000U)
95443 #define USDHC_INT_STATUS_EN_TPSEN_SHIFT          (14U)
95444 /*! TPSEN - Tuning pass status enable
95445  *  0b1..Enabled
95446  *  0b0..Masked
95447  */
95448 #define USDHC_INT_STATUS_EN_TPSEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
95449 
95450 #define USDHC_INT_STATUS_EN_CTOESEN_MASK         (0x10000U)
95451 #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT        (16U)
95452 /*! CTOESEN - Command timeout error status enable
95453  *  0b1..Enabled
95454  *  0b0..Masked
95455  */
95456 #define USDHC_INT_STATUS_EN_CTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
95457 
95458 #define USDHC_INT_STATUS_EN_CCESEN_MASK          (0x20000U)
95459 #define USDHC_INT_STATUS_EN_CCESEN_SHIFT         (17U)
95460 /*! CCESEN - Command CRC error status enable
95461  *  0b1..Enabled
95462  *  0b0..Masked
95463  */
95464 #define USDHC_INT_STATUS_EN_CCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
95465 
95466 #define USDHC_INT_STATUS_EN_CEBESEN_MASK         (0x40000U)
95467 #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT        (18U)
95468 /*! CEBESEN - Command end bit error status enable
95469  *  0b1..Enabled
95470  *  0b0..Masked
95471  */
95472 #define USDHC_INT_STATUS_EN_CEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
95473 
95474 #define USDHC_INT_STATUS_EN_CIESEN_MASK          (0x80000U)
95475 #define USDHC_INT_STATUS_EN_CIESEN_SHIFT         (19U)
95476 /*! CIESEN - Command index error status enable
95477  *  0b1..Enabled
95478  *  0b0..Masked
95479  */
95480 #define USDHC_INT_STATUS_EN_CIESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
95481 
95482 #define USDHC_INT_STATUS_EN_DTOESEN_MASK         (0x100000U)
95483 #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT        (20U)
95484 /*! DTOESEN - Data timeout error status enable
95485  *  0b1..Enabled
95486  *  0b0..Masked
95487  */
95488 #define USDHC_INT_STATUS_EN_DTOESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
95489 
95490 #define USDHC_INT_STATUS_EN_DCESEN_MASK          (0x200000U)
95491 #define USDHC_INT_STATUS_EN_DCESEN_SHIFT         (21U)
95492 /*! DCESEN - Data CRC error status enable
95493  *  0b1..Enabled
95494  *  0b0..Masked
95495  */
95496 #define USDHC_INT_STATUS_EN_DCESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
95497 
95498 #define USDHC_INT_STATUS_EN_DEBESEN_MASK         (0x400000U)
95499 #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT        (22U)
95500 /*! DEBESEN - Data end bit error status enable
95501  *  0b1..Enabled
95502  *  0b0..Masked
95503  */
95504 #define USDHC_INT_STATUS_EN_DEBESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
95505 
95506 #define USDHC_INT_STATUS_EN_AC12ESEN_MASK        (0x1000000U)
95507 #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT       (24U)
95508 /*! AC12ESEN - Auto CMD12 error status enable
95509  *  0b1..Enabled
95510  *  0b0..Masked
95511  */
95512 #define USDHC_INT_STATUS_EN_AC12ESEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
95513 
95514 #define USDHC_INT_STATUS_EN_TNESEN_MASK          (0x4000000U)
95515 #define USDHC_INT_STATUS_EN_TNESEN_SHIFT         (26U)
95516 /*! TNESEN - Tuning error status enable
95517  *  0b1..Enabled
95518  *  0b0..Masked
95519  */
95520 #define USDHC_INT_STATUS_EN_TNESEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
95521 
95522 #define USDHC_INT_STATUS_EN_DMAESEN_MASK         (0x10000000U)
95523 #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT        (28U)
95524 /*! DMAESEN - DMA error status enable
95525  *  0b1..Enabled
95526  *  0b0..Masked
95527  */
95528 #define USDHC_INT_STATUS_EN_DMAESEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
95529 /*! @} */
95530 
95531 /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
95532 /*! @{ */
95533 
95534 #define USDHC_INT_SIGNAL_EN_CCIEN_MASK           (0x1U)
95535 #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT          (0U)
95536 /*! CCIEN - Command complete interrupt enable
95537  *  0b1..Enabled
95538  *  0b0..Masked
95539  */
95540 #define USDHC_INT_SIGNAL_EN_CCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
95541 
95542 #define USDHC_INT_SIGNAL_EN_TCIEN_MASK           (0x2U)
95543 #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT          (1U)
95544 /*! TCIEN - Transfer complete interrupt enable
95545  *  0b1..Enabled
95546  *  0b0..Masked
95547  */
95548 #define USDHC_INT_SIGNAL_EN_TCIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
95549 
95550 #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK          (0x4U)
95551 #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT         (2U)
95552 /*! BGEIEN - Block gap event interrupt enable
95553  *  0b1..Enabled
95554  *  0b0..Masked
95555  */
95556 #define USDHC_INT_SIGNAL_EN_BGEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
95557 
95558 #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK         (0x8U)
95559 #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT        (3U)
95560 /*! DINTIEN - DMA interrupt enable
95561  *  0b1..Enabled
95562  *  0b0..Masked
95563  */
95564 #define USDHC_INT_SIGNAL_EN_DINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
95565 
95566 #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK          (0x10U)
95567 #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT         (4U)
95568 /*! BWRIEN - Buffer write ready interrupt enable
95569  *  0b1..Enabled
95570  *  0b0..Masked
95571  */
95572 #define USDHC_INT_SIGNAL_EN_BWRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
95573 
95574 #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK          (0x20U)
95575 #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT         (5U)
95576 /*! BRRIEN - Buffer read ready interrupt enable
95577  *  0b1..Enabled
95578  *  0b0..Masked
95579  */
95580 #define USDHC_INT_SIGNAL_EN_BRRIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
95581 
95582 #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK         (0x40U)
95583 #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT        (6U)
95584 /*! CINSIEN - Card insertion interrupt enable
95585  *  0b1..Enabled
95586  *  0b0..Masked
95587  */
95588 #define USDHC_INT_SIGNAL_EN_CINSIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
95589 
95590 #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK          (0x80U)
95591 #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT         (7U)
95592 /*! CRMIEN - Card removal interrupt enable
95593  *  0b1..Enabled
95594  *  0b0..Masked
95595  */
95596 #define USDHC_INT_SIGNAL_EN_CRMIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
95597 
95598 #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK         (0x100U)
95599 #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT        (8U)
95600 /*! CINTIEN - Card interrupt enable
95601  *  0b1..Enabled
95602  *  0b0..Masked
95603  */
95604 #define USDHC_INT_SIGNAL_EN_CINTIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
95605 
95606 #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK          (0x1000U)
95607 #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT         (12U)
95608 /*! RTEIEN - Re-tuning event interrupt enable
95609  *  0b1..Enabled
95610  *  0b0..Masked
95611  */
95612 #define USDHC_INT_SIGNAL_EN_RTEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
95613 
95614 #define USDHC_INT_SIGNAL_EN_TPIEN_MASK           (0x4000U)
95615 #define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT          (14U)
95616 /*! TPIEN - Tuning Pass interrupt enable
95617  *  0b1..Enabled
95618  *  0b0..Masked
95619  */
95620 #define USDHC_INT_SIGNAL_EN_TPIEN(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
95621 
95622 #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK         (0x10000U)
95623 #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT        (16U)
95624 /*! CTOEIEN - Command timeout error interrupt enable
95625  *  0b1..Enabled
95626  *  0b0..Masked
95627  */
95628 #define USDHC_INT_SIGNAL_EN_CTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
95629 
95630 #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK          (0x20000U)
95631 #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT         (17U)
95632 /*! CCEIEN - Command CRC error interrupt enable
95633  *  0b1..Enabled
95634  *  0b0..Masked
95635  */
95636 #define USDHC_INT_SIGNAL_EN_CCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
95637 
95638 #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK         (0x40000U)
95639 #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT        (18U)
95640 /*! CEBEIEN - Command end bit error interrupt enable
95641  *  0b1..Enabled
95642  *  0b0..Masked
95643  */
95644 #define USDHC_INT_SIGNAL_EN_CEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
95645 
95646 #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK          (0x80000U)
95647 #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT         (19U)
95648 /*! CIEIEN - Command index error interrupt enable
95649  *  0b1..Enabled
95650  *  0b0..Masked
95651  */
95652 #define USDHC_INT_SIGNAL_EN_CIEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
95653 
95654 #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK         (0x100000U)
95655 #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT        (20U)
95656 /*! DTOEIEN - Data timeout error interrupt enable
95657  *  0b1..Enabled
95658  *  0b0..Masked
95659  */
95660 #define USDHC_INT_SIGNAL_EN_DTOEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
95661 
95662 #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK          (0x200000U)
95663 #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT         (21U)
95664 /*! DCEIEN - Data CRC error interrupt enable
95665  *  0b1..Enabled
95666  *  0b0..Masked
95667  */
95668 #define USDHC_INT_SIGNAL_EN_DCEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
95669 
95670 #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK         (0x400000U)
95671 #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT        (22U)
95672 /*! DEBEIEN - Data end bit error interrupt enable
95673  *  0b1..Enabled
95674  *  0b0..Masked
95675  */
95676 #define USDHC_INT_SIGNAL_EN_DEBEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
95677 
95678 #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK        (0x1000000U)
95679 #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT       (24U)
95680 /*! AC12EIEN - Auto CMD12 error interrupt enable
95681  *  0b1..Enabled
95682  *  0b0..Masked
95683  */
95684 #define USDHC_INT_SIGNAL_EN_AC12EIEN(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
95685 
95686 #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK          (0x4000000U)
95687 #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT         (26U)
95688 /*! TNEIEN - Tuning error interrupt enable
95689  *  0b1..Enabled
95690  *  0b0..Masked
95691  */
95692 #define USDHC_INT_SIGNAL_EN_TNEIEN(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
95693 
95694 #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK         (0x10000000U)
95695 #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT        (28U)
95696 /*! DMAEIEN - DMA error interrupt enable
95697  *  0b1..Enable
95698  *  0b0..Masked
95699  */
95700 #define USDHC_INT_SIGNAL_EN_DMAEIEN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
95701 /*! @} */
95702 
95703 /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
95704 /*! @{ */
95705 
95706 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK   (0x1U)
95707 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT  (0U)
95708 /*! AC12NE - Auto CMD12 not executed
95709  *  0b1..Not executed
95710  *  0b0..Executed
95711  */
95712 #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
95713 
95714 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK  (0x2U)
95715 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
95716 /*! AC12TOE - Auto CMD12 / 23 timeout error
95717  *  0b1..Time out
95718  *  0b0..No error
95719  */
95720 #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
95721 
95722 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK  (0x4U)
95723 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
95724 /*! AC12EBE - Auto CMD12 / 23 end bit error
95725  *  0b1..End bit error generated
95726  *  0b0..No error
95727  */
95728 #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
95729 
95730 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK   (0x8U)
95731 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT  (3U)
95732 /*! AC12CE - Auto CMD12 / 23 CRC error
95733  *  0b1..CRC error met in Auto CMD12/23 response
95734  *  0b0..No CRC error
95735  */
95736 #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
95737 
95738 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK   (0x10U)
95739 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT  (4U)
95740 /*! AC12IE - Auto CMD12 / 23 index error
95741  *  0b1..Error, the CMD index in response is not CMD12/23
95742  *  0b0..No error
95743  */
95744 #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
95745 
95746 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
95747 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
95748 /*! CNIBAC12E - Command not issued by Auto CMD12 error
95749  *  0b1..Not issued
95750  *  0b0..No error
95751  */
95752 #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
95753 
95754 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
95755 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
95756 /*! EXECUTE_TUNING - Execute tuning
95757  *  0b1..Start tuning procedure
95758  *  0b0..Tuning procedure is aborted
95759  */
95760 #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
95761 
95762 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
95763 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
95764 /*! SMP_CLK_SEL - Sample clock select
95765  *  0b1..Tuned clock is used to sample data
95766  *  0b0..Fixed clock is used to sample data
95767  */
95768 #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
95769 /*! @} */
95770 
95771 /*! @name HOST_CTRL_CAP - Host Controller Capabilities */
95772 /*! @{ */
95773 
95774 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK   (0x1U)
95775 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT  (0U)
95776 /*! SDR50_SUPPORT - SDR50 support */
95777 #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
95778 
95779 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK  (0x2U)
95780 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
95781 /*! SDR104_SUPPORT - SDR104 support */
95782 #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
95783 
95784 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK   (0x4U)
95785 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT  (2U)
95786 /*! DDR50_SUPPORT - DDR50 support */
95787 #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
95788 
95789 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
95790 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
95791 /*! USE_TUNING_SDR50 - Use Tuning for SDR50
95792  *  0b1..SDR50 supports tuning
95793  *  0b0..SDR50 does not support tuning
95794  */
95795 #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
95796 
95797 #define USDHC_HOST_CTRL_CAP_MBL_MASK             (0x70000U)
95798 #define USDHC_HOST_CTRL_CAP_MBL_SHIFT            (16U)
95799 /*! MBL - Max block length
95800  *  0b000..512 bytes
95801  *  0b001..1024 bytes
95802  *  0b010..2048 bytes
95803  *  0b011..4096 bytes
95804  */
95805 #define USDHC_HOST_CTRL_CAP_MBL(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
95806 
95807 #define USDHC_HOST_CTRL_CAP_ADMAS_MASK           (0x100000U)
95808 #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT          (20U)
95809 /*! ADMAS - ADMA support
95810  *  0b1..Advanced DMA supported
95811  *  0b0..Advanced DMA not supported
95812  */
95813 #define USDHC_HOST_CTRL_CAP_ADMAS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
95814 
95815 #define USDHC_HOST_CTRL_CAP_HSS_MASK             (0x200000U)
95816 #define USDHC_HOST_CTRL_CAP_HSS_SHIFT            (21U)
95817 /*! HSS - High speed support
95818  *  0b1..High speed supported
95819  *  0b0..High speed not supported
95820  */
95821 #define USDHC_HOST_CTRL_CAP_HSS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
95822 
95823 #define USDHC_HOST_CTRL_CAP_DMAS_MASK            (0x400000U)
95824 #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT           (22U)
95825 /*! DMAS - DMA support
95826  *  0b1..DMA supported
95827  *  0b0..DMA not supported
95828  */
95829 #define USDHC_HOST_CTRL_CAP_DMAS(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
95830 
95831 #define USDHC_HOST_CTRL_CAP_SRS_MASK             (0x800000U)
95832 #define USDHC_HOST_CTRL_CAP_SRS_SHIFT            (23U)
95833 /*! SRS - Suspend / resume support
95834  *  0b1..Supported
95835  *  0b0..Not supported
95836  */
95837 #define USDHC_HOST_CTRL_CAP_SRS(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
95838 
95839 #define USDHC_HOST_CTRL_CAP_VS33_MASK            (0x1000000U)
95840 #define USDHC_HOST_CTRL_CAP_VS33_SHIFT           (24U)
95841 /*! VS33 - Voltage support 3.3 V
95842  *  0b1..3.3 V supported
95843  *  0b0..3.3 V not supported
95844  */
95845 #define USDHC_HOST_CTRL_CAP_VS33(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
95846 
95847 #define USDHC_HOST_CTRL_CAP_VS30_MASK            (0x2000000U)
95848 #define USDHC_HOST_CTRL_CAP_VS30_SHIFT           (25U)
95849 /*! VS30 - Voltage support 3.0 V
95850  *  0b1..3.0 V supported
95851  *  0b0..3.0 V not supported
95852  */
95853 #define USDHC_HOST_CTRL_CAP_VS30(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
95854 
95855 #define USDHC_HOST_CTRL_CAP_VS18_MASK            (0x4000000U)
95856 #define USDHC_HOST_CTRL_CAP_VS18_SHIFT           (26U)
95857 /*! VS18 - Voltage support 1.8 V
95858  *  0b1..1.8 V supported
95859  *  0b0..1.8 V not supported
95860  */
95861 #define USDHC_HOST_CTRL_CAP_VS18(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
95862 /*! @} */
95863 
95864 /*! @name WTMK_LVL - Watermark Level */
95865 /*! @{ */
95866 
95867 #define USDHC_WTMK_LVL_RD_WML_MASK               (0xFFU)
95868 #define USDHC_WTMK_LVL_RD_WML_SHIFT              (0U)
95869 /*! RD_WML - Read watermark level */
95870 #define USDHC_WTMK_LVL_RD_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
95871 
95872 #define USDHC_WTMK_LVL_WR_WML_MASK               (0xFF0000U)
95873 #define USDHC_WTMK_LVL_WR_WML_SHIFT              (16U)
95874 /*! WR_WML - Write watermark level */
95875 #define USDHC_WTMK_LVL_WR_WML(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
95876 /*! @} */
95877 
95878 /*! @name MIX_CTRL - Mixer Control */
95879 /*! @{ */
95880 
95881 #define USDHC_MIX_CTRL_DMAEN_MASK                (0x1U)
95882 #define USDHC_MIX_CTRL_DMAEN_SHIFT               (0U)
95883 /*! DMAEN - DMA enable
95884  *  0b1..Enable
95885  *  0b0..Disable
95886  */
95887 #define USDHC_MIX_CTRL_DMAEN(x)                  (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
95888 
95889 #define USDHC_MIX_CTRL_BCEN_MASK                 (0x2U)
95890 #define USDHC_MIX_CTRL_BCEN_SHIFT                (1U)
95891 /*! BCEN - Block count enable
95892  *  0b1..Enable
95893  *  0b0..Disable
95894  */
95895 #define USDHC_MIX_CTRL_BCEN(x)                   (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
95896 
95897 #define USDHC_MIX_CTRL_AC12EN_MASK               (0x4U)
95898 #define USDHC_MIX_CTRL_AC12EN_SHIFT              (2U)
95899 /*! AC12EN - Auto CMD12 enable
95900  *  0b1..Enable
95901  *  0b0..Disable
95902  */
95903 #define USDHC_MIX_CTRL_AC12EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
95904 
95905 #define USDHC_MIX_CTRL_DDR_EN_MASK               (0x8U)
95906 #define USDHC_MIX_CTRL_DDR_EN_SHIFT              (3U)
95907 /*! DDR_EN - Dual data rate mode selection */
95908 #define USDHC_MIX_CTRL_DDR_EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
95909 
95910 #define USDHC_MIX_CTRL_DTDSEL_MASK               (0x10U)
95911 #define USDHC_MIX_CTRL_DTDSEL_SHIFT              (4U)
95912 /*! DTDSEL - Data transfer direction select
95913  *  0b1..Read (Card to host)
95914  *  0b0..Write (Host to card)
95915  */
95916 #define USDHC_MIX_CTRL_DTDSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
95917 
95918 #define USDHC_MIX_CTRL_MSBSEL_MASK               (0x20U)
95919 #define USDHC_MIX_CTRL_MSBSEL_SHIFT              (5U)
95920 /*! MSBSEL - Multi / Single block select
95921  *  0b1..Multiple blocks
95922  *  0b0..Single block
95923  */
95924 #define USDHC_MIX_CTRL_MSBSEL(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
95925 
95926 #define USDHC_MIX_CTRL_NIBBLE_POS_MASK           (0x40U)
95927 #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT          (6U)
95928 /*! NIBBLE_POS - Nibble position indication */
95929 #define USDHC_MIX_CTRL_NIBBLE_POS(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
95930 
95931 #define USDHC_MIX_CTRL_AC23EN_MASK               (0x80U)
95932 #define USDHC_MIX_CTRL_AC23EN_SHIFT              (7U)
95933 /*! AC23EN - Auto CMD23 enable */
95934 #define USDHC_MIX_CTRL_AC23EN(x)                 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
95935 
95936 #define USDHC_MIX_CTRL_EXE_TUNE_MASK             (0x400000U)
95937 #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT            (22U)
95938 /*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
95939  *  0b1..Execute tuning
95940  *  0b0..Not tuned or tuning completed
95941  */
95942 #define USDHC_MIX_CTRL_EXE_TUNE(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
95943 
95944 #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK          (0x800000U)
95945 #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT         (23U)
95946 /*! SMP_CLK_SEL - Clock selection
95947  *  0b1..Tuned clock is used to sample data / cmd
95948  *  0b0..Fixed clock is used to sample data / cmd
95949  */
95950 #define USDHC_MIX_CTRL_SMP_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
95951 
95952 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK         (0x1000000U)
95953 #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT        (24U)
95954 /*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)
95955  *  0b1..Enable auto tuning
95956  *  0b0..Disable auto tuning
95957  */
95958 #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
95959 
95960 #define USDHC_MIX_CTRL_FBCLK_SEL_MASK            (0x2000000U)
95961 #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT           (25U)
95962 /*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
95963  *  0b1..Feedback clock comes from the ipp_card_clk_out
95964  *  0b0..Feedback clock comes from the loopback CLK
95965  */
95966 #define USDHC_MIX_CTRL_FBCLK_SEL(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
95967 
95968 #define USDHC_MIX_CTRL_HS400_MODE_MASK           (0x4000000U)
95969 #define USDHC_MIX_CTRL_HS400_MODE_SHIFT          (26U)
95970 /*! HS400_MODE - Enable HS400 mode */
95971 #define USDHC_MIX_CTRL_HS400_MODE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)
95972 /*! @} */
95973 
95974 /*! @name FORCE_EVENT - Force Event */
95975 /*! @{ */
95976 
95977 #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK        (0x1U)
95978 #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT       (0U)
95979 /*! FEVTAC12NE - Force event auto command 12 not executed */
95980 #define USDHC_FORCE_EVENT_FEVTAC12NE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
95981 
95982 #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK       (0x2U)
95983 #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT      (1U)
95984 /*! FEVTAC12TOE - Force event auto command 12 time out error */
95985 #define USDHC_FORCE_EVENT_FEVTAC12TOE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
95986 
95987 #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK        (0x4U)
95988 #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT       (2U)
95989 /*! FEVTAC12CE - Force event auto command 12 CRC error */
95990 #define USDHC_FORCE_EVENT_FEVTAC12CE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
95991 
95992 #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK       (0x8U)
95993 #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT      (3U)
95994 /*! FEVTAC12EBE - Force event Auto Command 12 end bit error */
95995 #define USDHC_FORCE_EVENT_FEVTAC12EBE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
95996 
95997 #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK        (0x10U)
95998 #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT       (4U)
95999 /*! FEVTAC12IE - Force event Auto Command 12 index error */
96000 #define USDHC_FORCE_EVENT_FEVTAC12IE(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
96001 
96002 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK     (0x80U)
96003 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT    (7U)
96004 /*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error */
96005 #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
96006 
96007 #define USDHC_FORCE_EVENT_FEVTCTOE_MASK          (0x10000U)
96008 #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT         (16U)
96009 /*! FEVTCTOE - Force event command time out error */
96010 #define USDHC_FORCE_EVENT_FEVTCTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
96011 
96012 #define USDHC_FORCE_EVENT_FEVTCCE_MASK           (0x20000U)
96013 #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT          (17U)
96014 /*! FEVTCCE - Force event command CRC error */
96015 #define USDHC_FORCE_EVENT_FEVTCCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
96016 
96017 #define USDHC_FORCE_EVENT_FEVTCEBE_MASK          (0x40000U)
96018 #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT         (18U)
96019 /*! FEVTCEBE - Force event command end bit error */
96020 #define USDHC_FORCE_EVENT_FEVTCEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
96021 
96022 #define USDHC_FORCE_EVENT_FEVTCIE_MASK           (0x80000U)
96023 #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT          (19U)
96024 /*! FEVTCIE - Force event command index error */
96025 #define USDHC_FORCE_EVENT_FEVTCIE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
96026 
96027 #define USDHC_FORCE_EVENT_FEVTDTOE_MASK          (0x100000U)
96028 #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT         (20U)
96029 /*! FEVTDTOE - Force event data time out error */
96030 #define USDHC_FORCE_EVENT_FEVTDTOE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
96031 
96032 #define USDHC_FORCE_EVENT_FEVTDCE_MASK           (0x200000U)
96033 #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT          (21U)
96034 /*! FEVTDCE - Force event data CRC error */
96035 #define USDHC_FORCE_EVENT_FEVTDCE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
96036 
96037 #define USDHC_FORCE_EVENT_FEVTDEBE_MASK          (0x400000U)
96038 #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT         (22U)
96039 /*! FEVTDEBE - Force event data end bit error */
96040 #define USDHC_FORCE_EVENT_FEVTDEBE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
96041 
96042 #define USDHC_FORCE_EVENT_FEVTAC12E_MASK         (0x1000000U)
96043 #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT        (24U)
96044 /*! FEVTAC12E - Force event Auto Command 12 error */
96045 #define USDHC_FORCE_EVENT_FEVTAC12E(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
96046 
96047 #define USDHC_FORCE_EVENT_FEVTTNE_MASK           (0x4000000U)
96048 #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT          (26U)
96049 /*! FEVTTNE - Force tuning error */
96050 #define USDHC_FORCE_EVENT_FEVTTNE(x)             (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
96051 
96052 #define USDHC_FORCE_EVENT_FEVTDMAE_MASK          (0x10000000U)
96053 #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT         (28U)
96054 /*! FEVTDMAE - Force event DMA error */
96055 #define USDHC_FORCE_EVENT_FEVTDMAE(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
96056 
96057 #define USDHC_FORCE_EVENT_FEVTCINT_MASK          (0x80000000U)
96058 #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT         (31U)
96059 /*! FEVTCINT - Force event card interrupt */
96060 #define USDHC_FORCE_EVENT_FEVTCINT(x)            (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
96061 /*! @} */
96062 
96063 /*! @name ADMA_ERR_STATUS - ADMA Error Status */
96064 /*! @{ */
96065 
96066 #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK        (0x3U)
96067 #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT       (0U)
96068 /*! ADMAES - ADMA error state (when ADMA error is occurred) */
96069 #define USDHC_ADMA_ERR_STATUS_ADMAES(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
96070 
96071 #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK       (0x4U)
96072 #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT      (2U)
96073 /*! ADMALME - ADMA length mismatch error
96074  *  0b1..Error
96075  *  0b0..No error
96076  */
96077 #define USDHC_ADMA_ERR_STATUS_ADMALME(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
96078 
96079 #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK       (0x8U)
96080 #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT      (3U)
96081 /*! ADMADCE - ADMA descriptor error
96082  *  0b1..Error
96083  *  0b0..No error
96084  */
96085 #define USDHC_ADMA_ERR_STATUS_ADMADCE(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
96086 /*! @} */
96087 
96088 /*! @name ADMA_SYS_ADDR - ADMA System Address */
96089 /*! @{ */
96090 
96091 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK        (0xFFFFFFFCU)
96092 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT       (2U)
96093 /*! ADS_ADDR - ADMA system address */
96094 #define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
96095 /*! @} */
96096 
96097 /*! @name DLL_CTRL - DLL (Delay Line) Control */
96098 /*! @{ */
96099 
96100 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK      (0x1U)
96101 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT     (0U)
96102 /*! DLL_CTRL_ENABLE - DLL and delay chain */
96103 #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
96104 
96105 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK       (0x2U)
96106 #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT      (1U)
96107 /*! DLL_CTRL_RESET - DLL reset */
96108 #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
96109 
96110 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
96111 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
96112 /*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line */
96113 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
96114 
96115 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
96116 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
96117 /*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0 */
96118 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
96119 
96120 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
96121 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
96122 /*! DLL_CTRL_GATE_UPDATE - DLL gate update */
96123 #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x)   (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
96124 
96125 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
96126 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
96127 /*! DLL_CTRL_SLV_OVERRIDE - DLL slave override */
96128 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x)  (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
96129 
96130 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
96131 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
96132 /*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val */
96133 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
96134 
96135 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
96136 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
96137 /*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1 */
96138 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
96139 
96140 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
96141 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
96142 /*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval */
96143 #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
96144 
96145 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
96146 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
96147 /*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval */
96148 #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
96149 /*! @} */
96150 
96151 /*! @name DLL_STATUS - DLL Status */
96152 /*! @{ */
96153 
96154 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK   (0x1U)
96155 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT  (0U)
96156 /*! DLL_STS_SLV_LOCK - Slave delay-line lock status */
96157 #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
96158 
96159 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK   (0x2U)
96160 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT  (1U)
96161 /*! DLL_STS_REF_LOCK - Reference DLL lock status */
96162 #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
96163 
96164 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK    (0x1FCU)
96165 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT   (2U)
96166 /*! DLL_STS_SLV_SEL - Slave delay line select status */
96167 #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
96168 
96169 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK    (0xFE00U)
96170 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT   (9U)
96171 /*! DLL_STS_REF_SEL - Reference delay line select taps */
96172 #define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
96173 /*! @} */
96174 
96175 /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
96176 /*! @{ */
96177 
96178 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
96179 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
96180 /*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST */
96181 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
96182 
96183 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
96184 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
96185 /*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT */
96186 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
96187 
96188 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
96189 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
96190 /*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE */
96191 #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
96192 
96193 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK  (0x8000U)
96194 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
96195 /*! NXT_ERR - NXT error */
96196 #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
96197 
96198 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
96199 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
96200 /*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST */
96201 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
96202 
96203 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
96204 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
96205 /*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT */
96206 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
96207 
96208 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
96209 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
96210 /*! TAP_SEL_PRE - TAP_SEL_PRE */
96211 #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
96212 
96213 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK  (0x80000000U)
96214 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
96215 /*! PRE_ERR - PRE error */
96216 #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
96217 /*! @} */
96218 
96219 /*! @name STROBE_DLL_CTRL - Strobe DLL control */
96220 /*! @{ */
96221 
96222 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
96223 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
96224 /*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable */
96225 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)
96226 
96227 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
96228 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
96229 /*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset */
96230 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)
96231 
96232 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
96233 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
96234 /*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated */
96235 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)
96236 
96237 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
96238 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
96239 /*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target */
96240 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)
96241 
96242 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
96243 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
96244 /*! STROBE_DLL_CTRL_GATE_UPDATE - Strobe DLL control gate update */
96245 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK)
96246 
96247 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
96248 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
96249 /*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override */
96250 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)
96251 
96252 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
96253 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
96254 /*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value */
96255 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
96256 
96257 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
96258 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
96259 /*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval */
96260 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)
96261 
96262 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
96263 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
96264 /*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval */
96265 #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
96266 /*! @} */
96267 
96268 /*! @name STROBE_DLL_STATUS - Strobe DLL status */
96269 /*! @{ */
96270 
96271 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
96272 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
96273 /*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock */
96274 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)
96275 
96276 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
96277 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
96278 /*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock */
96279 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)
96280 
96281 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
96282 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
96283 /*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select */
96284 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)
96285 
96286 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
96287 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
96288 /*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select */
96289 #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
96290 /*! @} */
96291 
96292 /*! @name VEND_SPEC - Vendor Specific Register */
96293 /*! @{ */
96294 
96295 #define USDHC_VEND_SPEC_VSELECT_MASK             (0x2U)
96296 #define USDHC_VEND_SPEC_VSELECT_SHIFT            (1U)
96297 /*! VSELECT - Voltage selection
96298  *  0b1..Change the voltage to low voltage range, around 1.8 V
96299  *  0b0..Change the voltage to high voltage range, around 3.0 V
96300  */
96301 #define USDHC_VEND_SPEC_VSELECT(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
96302 
96303 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK     (0x4U)
96304 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT    (2U)
96305 /*! CONFLICT_CHK_EN - Conflict check enable
96306  *  0b0..Conflict check disable
96307  *  0b1..Conflict check enable
96308  */
96309 #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
96310 
96311 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK  (0x8U)
96312 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
96313 /*! AC12_WR_CHKBUSY_EN - Check busy enable
96314  *  0b0..Do not check busy after auto CMD12 for write data packet
96315  *  0b1..Check busy after auto CMD12 for write data packet
96316  */
96317 #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
96318 
96319 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK        (0x100U)
96320 #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT       (8U)
96321 /*! FRC_SDCLK_ON - Force CLK
96322  *  0b0..CLK active or inactive is fully controlled by the hardware.
96323  *  0b1..Force CLK active
96324  */
96325 #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x)          (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
96326 
96327 #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK         (0x8000U)
96328 #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT        (15U)
96329 /*! CRC_CHK_DIS - CRC Check Disable
96330  *  0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet
96331  *  0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet
96332  */
96333 #define USDHC_VEND_SPEC_CRC_CHK_DIS(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
96334 
96335 #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK         (0x80000000U)
96336 #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT        (31U)
96337 /*! CMD_BYTE_EN - Byte access
96338  *  0b0..Disable
96339  *  0b1..Enable
96340  */
96341 #define USDHC_VEND_SPEC_CMD_BYTE_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
96342 /*! @} */
96343 
96344 /*! @name MMC_BOOT - MMC Boot */
96345 /*! @{ */
96346 
96347 #define USDHC_MMC_BOOT_DTOCV_ACK_MASK            (0xFU)
96348 #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT           (0U)
96349 /*! DTOCV_ACK - Boot ACK time out
96350  *  0b0000..SDCLK x 2^14
96351  *  0b0001..SDCLK x 2^15
96352  *  0b0010..SDCLK x 2^16
96353  *  0b0011..SDCLK x 2^17
96354  *  0b0100..SDCLK x 2^18
96355  *  0b0101..SDCLK x 2^19
96356  *  0b0110..SDCLK x 2^20
96357  *  0b0111..SDCLK x 2^21
96358  *  0b1110..SDCLK x 2^28
96359  *  0b1111..SDCLK x 2^29
96360  */
96361 #define USDHC_MMC_BOOT_DTOCV_ACK(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
96362 
96363 #define USDHC_MMC_BOOT_BOOT_ACK_MASK             (0x10U)
96364 #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT            (4U)
96365 /*! BOOT_ACK - BOOT ACK
96366  *  0b0..No ack
96367  *  0b1..Ack
96368  */
96369 #define USDHC_MMC_BOOT_BOOT_ACK(x)               (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
96370 
96371 #define USDHC_MMC_BOOT_BOOT_MODE_MASK            (0x20U)
96372 #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT           (5U)
96373 /*! BOOT_MODE - Boot mode
96374  *  0b0..Normal boot
96375  *  0b1..Alternative boot
96376  */
96377 #define USDHC_MMC_BOOT_BOOT_MODE(x)              (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
96378 
96379 #define USDHC_MMC_BOOT_BOOT_EN_MASK              (0x40U)
96380 #define USDHC_MMC_BOOT_BOOT_EN_SHIFT             (6U)
96381 /*! BOOT_EN - Boot enable
96382  *  0b0..Fast boot disable
96383  *  0b1..Fast boot enable
96384  */
96385 #define USDHC_MMC_BOOT_BOOT_EN(x)                (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
96386 
96387 #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK         (0x80U)
96388 #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT        (7U)
96389 /*! AUTO_SABG_EN - Auto stop at block gap */
96390 #define USDHC_MMC_BOOT_AUTO_SABG_EN(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
96391 
96392 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK     (0x100U)
96393 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT    (8U)
96394 /*! DISABLE_TIME_OUT - Time out
96395  *  0b0..Enable time out
96396  *  0b1..Disable time out
96397  */
96398 #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
96399 
96400 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK         (0xFFFF0000U)
96401 #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT        (16U)
96402 /*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode */
96403 #define USDHC_MMC_BOOT_BOOT_BLK_CNT(x)           (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
96404 /*! @} */
96405 
96406 /*! @name VEND_SPEC2 - Vendor Specific 2 Register */
96407 /*! @{ */
96408 
96409 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK   (0x8U)
96410 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT  (3U)
96411 /*! CARD_INT_D3_TEST - Card interrupt detection test
96412  *  0b0..Check the card interrupt only when DATA3 is high.
96413  *  0b1..Check the card interrupt by ignoring the status of DATA3.
96414  */
96415 #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x)     (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
96416 
96417 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK     (0x10U)
96418 #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT    (4U)
96419 /*! TUNING_8bit_EN - Tuning 8bit enable */
96420 #define USDHC_VEND_SPEC2_TUNING_8bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
96421 
96422 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK     (0x20U)
96423 #define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT    (5U)
96424 /*! TUNING_1bit_EN - Tuning 1bit enable */
96425 #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
96426 
96427 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK      (0x40U)
96428 #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT     (6U)
96429 /*! TUNING_CMD_EN - Tuning command enable
96430  *  0b0..Auto tuning circuit does not check the CMD line.
96431  *  0b1..Auto tuning circuit checks the CMD line.
96432  */
96433 #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x)        (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
96434 
96435 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
96436 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
96437 /*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable */
96438 #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)
96439 
96440 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
96441 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
96442 /*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable */
96443 #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)
96444 
96445 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK    (0x1000U)
96446 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT   (12U)
96447 /*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
96448  *  0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.
96449  *  0b0..Disable
96450  */
96451 #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
96452 /*! @} */
96453 
96454 /*! @name TUNING_CTRL - Tuning Control */
96455 /*! @{ */
96456 
96457 #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK  (0x7FU)
96458 #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
96459 /*! TUNING_START_TAP - Tuning start */
96460 #define USDHC_TUNING_CTRL_TUNING_START_TAP(x)    (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
96461 
96462 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U)
96463 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U)
96464 /*! DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning */
96465 #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK)
96466 
96467 #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK    (0xFF00U)
96468 #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT   (8U)
96469 /*! TUNING_COUNTER - Tuning counter */
96470 #define USDHC_TUNING_CTRL_TUNING_COUNTER(x)      (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
96471 
96472 #define USDHC_TUNING_CTRL_TUNING_STEP_MASK       (0x70000U)
96473 #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT      (16U)
96474 /*! TUNING_STEP - TUNING_STEP */
96475 #define USDHC_TUNING_CTRL_TUNING_STEP(x)         (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
96476 
96477 #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK     (0x700000U)
96478 #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT    (20U)
96479 /*! TUNING_WINDOW - Data window */
96480 #define USDHC_TUNING_CTRL_TUNING_WINDOW(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
96481 
96482 #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK     (0x1000000U)
96483 #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT    (24U)
96484 /*! STD_TUNING_EN - Standard tuning circuit and procedure enable */
96485 #define USDHC_TUNING_CTRL_STD_TUNING_EN(x)       (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
96486 /*! @} */
96487 
96488 
96489 /*!
96490  * @}
96491  */ /* end of group USDHC_Register_Masks */
96492 
96493 
96494 /* USDHC - Peripheral instance base addresses */
96495 /** Peripheral USDHC1 base address */
96496 #define USDHC1_BASE                              (0x40418000u)
96497 /** Peripheral USDHC1 base pointer */
96498 #define USDHC1                                   ((USDHC_Type *)USDHC1_BASE)
96499 /** Peripheral USDHC2 base address */
96500 #define USDHC2_BASE                              (0x4041C000u)
96501 /** Peripheral USDHC2 base pointer */
96502 #define USDHC2                                   ((USDHC_Type *)USDHC2_BASE)
96503 /** Array initializer of USDHC peripheral base addresses */
96504 #define USDHC_BASE_ADDRS                         { 0u, USDHC1_BASE, USDHC2_BASE }
96505 /** Array initializer of USDHC peripheral base pointers */
96506 #define USDHC_BASE_PTRS                          { (USDHC_Type *)0u, USDHC1, USDHC2 }
96507 /** Interrupt vectors for the USDHC peripheral type */
96508 #define USDHC_IRQS                               { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
96509 
96510 /*!
96511  * @}
96512  */ /* end of group USDHC_Peripheral_Access_Layer */
96513 
96514 
96515 /* ----------------------------------------------------------------------------
96516    -- VIDEO_MUX Peripheral Access Layer
96517    ---------------------------------------------------------------------------- */
96518 
96519 /*!
96520  * @addtogroup VIDEO_MUX_Peripheral_Access_Layer VIDEO_MUX Peripheral Access Layer
96521  * @{
96522  */
96523 
96524 /** VIDEO_MUX - Register Layout Typedef */
96525 typedef struct {
96526   struct {                                         /* offset: 0x0 */
96527     __IO uint32_t RW;                                /**< Video mux Control Register, offset: 0x0 */
96528     __IO uint32_t SET;                               /**< Video mux Control Register, offset: 0x4 */
96529     __IO uint32_t CLR;                               /**< Video mux Control Register, offset: 0x8 */
96530     __IO uint32_t TOG;                               /**< Video mux Control Register, offset: 0xC */
96531   } VID_MUX_CTRL;
96532        uint8_t RESERVED_0[16];
96533   struct {                                         /* offset: 0x20 */
96534     __IO uint32_t RW;                                /**< Pixel Link Master(PLM) Control Register, offset: 0x20 */
96535     __IO uint32_t SET;                               /**< Pixel Link Master(PLM) Control Register, offset: 0x24 */
96536     __IO uint32_t CLR;                               /**< Pixel Link Master(PLM) Control Register, offset: 0x28 */
96537     __IO uint32_t TOG;                               /**< Pixel Link Master(PLM) Control Register, offset: 0x2C */
96538   } PLM_CTRL;
96539   struct {                                         /* offset: 0x30 */
96540     __IO uint32_t RW;                                /**< YUV420 Control Register, offset: 0x30 */
96541     __IO uint32_t SET;                               /**< YUV420 Control Register, offset: 0x34 */
96542     __IO uint32_t CLR;                               /**< YUV420 Control Register, offset: 0x38 */
96543     __IO uint32_t TOG;                               /**< YUV420 Control Register, offset: 0x3C */
96544   } YUV420_CTRL;
96545        uint8_t RESERVED_1[16];
96546   struct {                                         /* offset: 0x50 */
96547     __IO uint32_t RW;                                /**< Data Disable Register, offset: 0x50 */
96548     __IO uint32_t SET;                               /**< Data Disable Register, offset: 0x54 */
96549     __IO uint32_t CLR;                               /**< Data Disable Register, offset: 0x58 */
96550     __IO uint32_t TOG;                               /**< Data Disable Register, offset: 0x5C */
96551   } CFG_DT_DISABLE;
96552        uint8_t RESERVED_2[16];
96553   struct {                                         /* offset: 0x70 */
96554     __IO uint32_t RW;                                /**< MIPI DSI Control Register, offset: 0x70 */
96555     __IO uint32_t SET;                               /**< MIPI DSI Control Register, offset: 0x74 */
96556     __IO uint32_t CLR;                               /**< MIPI DSI Control Register, offset: 0x78 */
96557     __IO uint32_t TOG;                               /**< MIPI DSI Control Register, offset: 0x7C */
96558   } MIPI_DSI_CTRL;
96559 } VIDEO_MUX_Type;
96560 
96561 /* ----------------------------------------------------------------------------
96562    -- VIDEO_MUX Register Masks
96563    ---------------------------------------------------------------------------- */
96564 
96565 /*!
96566  * @addtogroup VIDEO_MUX_Register_Masks VIDEO_MUX Register Masks
96567  * @{
96568  */
96569 
96570 /*! @name VID_MUX_CTRL - Video mux Control Register */
96571 /*! @{ */
96572 
96573 #define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK      (0x1U)
96574 #define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT     (0U)
96575 /*! CSI_SEL - CSI sensor data input mux selector
96576  *  0b0..CSI sensor data is from Parallel CSI
96577  *  0b1..CSI sensor data is from MIPI CSI
96578  */
96579 #define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL(x)        (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK)
96580 
96581 #define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK   (0x2U)
96582 #define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT  (1U)
96583 /*! LCDIF2_SEL - LCDIF2 sensor data input mux selector
96584  *  0b0..LCDIFv2 sensor data is from Parallel CSI
96585  *  0b1..LCDIFv2 sensor data is from MIPI CSI
96586  */
96587 #define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL(x)     (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK)
96588 
96589 #define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK (0x4U)
96590 #define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT (2U)
96591 /*! MIPI_DSI_SEL - MIPI DSI video data input mux selector
96592  *  0b0..MIPI DSI video data is from eLCDIF
96593  *  0b1..MIPI DSI video data is from LCDIFv2
96594  */
96595 #define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK)
96596 
96597 #define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK (0x8U)
96598 #define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT (3U)
96599 /*! PARA_LCD_SEL - Parallel LCDIF video data input mux selector
96600  *  0b0..Parallel LCDIF video data is from eLCDIF
96601  *  0b1..Parallel LCDIF video data is from LCDIFv2
96602  */
96603 #define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL(x)   (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK)
96604 /*! @} */
96605 
96606 /*! @name PLM_CTRL - Pixel Link Master(PLM) Control Register */
96607 /*! @{ */
96608 
96609 #define VIDEO_MUX_PLM_CTRL_ENABLE_MASK           (0x1U)
96610 #define VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT          (0U)
96611 /*! ENABLE - Enable the output of HYSNC and VSYNC
96612  *  0b0..No active HSYNC and VSYNC output
96613  *  0b1..Active HSYNC and VSYNC output
96614  */
96615 #define VIDEO_MUX_PLM_CTRL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT)) & VIDEO_MUX_PLM_CTRL_ENABLE_MASK)
96616 
96617 #define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK   (0x2U)
96618 #define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT  (1U)
96619 /*! VSYNC_OVERRIDE - VSYNC override
96620  *  0b1..VSYNC is asserted
96621  *  0b0..VSYNC is not asserted
96622  */
96623 #define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE(x)     (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK)
96624 
96625 #define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK   (0x4U)
96626 #define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT  (2U)
96627 /*! HSYNC_OVERRIDE - HSYNC override
96628  *  0b1..HSYNC is asserted
96629  *  0b0..HSYNC is not asserted
96630  */
96631 #define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE(x)     (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK)
96632 
96633 #define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK   (0x8U)
96634 #define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT  (3U)
96635 /*! VALID_OVERRIDE - Valid override
96636  *  0b0..HSYNC and VSYNC is asserted
96637  *  0b1..HSYNC and VSYNC is not asserted
96638  */
96639 #define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE(x)     (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK)
96640 
96641 #define VIDEO_MUX_PLM_CTRL_POLARITY_MASK         (0x10U)
96642 #define VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT        (4U)
96643 /*! POLARITY - Polarity of HYSNC/VSYNC
96644  *  0b0..Keep the current polarity of HSYNC and VSYNC
96645  *  0b1..Invert the polarity of HSYNC and VSYNC
96646  */
96647 #define VIDEO_MUX_PLM_CTRL_POLARITY(x)           (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT)) & VIDEO_MUX_PLM_CTRL_POLARITY_MASK)
96648 /*! @} */
96649 
96650 /*! @name YUV420_CTRL - YUV420 Control Register */
96651 /*! @{ */
96652 
96653 #define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK (0x1U)
96654 #define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT (0U)
96655 /*! FST_LN_DATA_TYPE - Data type of First Line
96656  *  0b0..Odd (default)
96657  *  0b1..Even
96658  */
96659 #define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT)) & VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK)
96660 /*! @} */
96661 
96662 /*! @name CFG_DT_DISABLE - Data Disable Register */
96663 /*! @{ */
96664 
96665 #define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK (0xFFFFFFU)
96666 #define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT (0U)
96667 /*! CFG_DT_DISABLE - Data Type Disable */
96668 #define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT)) & VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK)
96669 /*! @} */
96670 
96671 /*! @name MIPI_DSI_CTRL - MIPI DSI Control Register */
96672 /*! @{ */
96673 
96674 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK      (0x1U)
96675 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT     (0U)
96676 /*! DPI_SD - Shut Down - Control to shutdown display (type 4 only)
96677  *  0b0..No effect
96678  *  0b1..Send shutdown command
96679  */
96680 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD(x)        (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK)
96681 
96682 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK      (0x2U)
96683 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT     (1U)
96684 /*! DPI_CM - Color Mode control
96685  *  0b0..Normal Mode
96686  *  0b1..Low-color mode
96687  */
96688 #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM(x)        (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK)
96689 /*! @} */
96690 
96691 
96692 /*!
96693  * @}
96694  */ /* end of group VIDEO_MUX_Register_Masks */
96695 
96696 
96697 /* VIDEO_MUX - Peripheral instance base addresses */
96698 /** Peripheral VIDEO_MUX base address */
96699 #define VIDEO_MUX_BASE                           (0x40818000u)
96700 /** Peripheral VIDEO_MUX base pointer */
96701 #define VIDEO_MUX                                ((VIDEO_MUX_Type *)VIDEO_MUX_BASE)
96702 /** Array initializer of VIDEO_MUX peripheral base addresses */
96703 #define VIDEO_MUX_BASE_ADDRS                     { VIDEO_MUX_BASE }
96704 /** Array initializer of VIDEO_MUX peripheral base pointers */
96705 #define VIDEO_MUX_BASE_PTRS                      { VIDEO_MUX }
96706 
96707 /*!
96708  * @}
96709  */ /* end of group VIDEO_MUX_Peripheral_Access_Layer */
96710 
96711 
96712 /* ----------------------------------------------------------------------------
96713    -- VIDEO_PLL Peripheral Access Layer
96714    ---------------------------------------------------------------------------- */
96715 
96716 /*!
96717  * @addtogroup VIDEO_PLL_Peripheral_Access_Layer VIDEO_PLL Peripheral Access Layer
96718  * @{
96719  */
96720 
96721 /** VIDEO_PLL - Register Layout Typedef */
96722 typedef struct {
96723   struct {                                         /* offset: 0x0 */
96724     __IO uint32_t RW;                                /**< Fractional PLL Control Register, offset: 0x0 */
96725     __IO uint32_t SET;                               /**< Fractional PLL Control Register, offset: 0x4 */
96726     __IO uint32_t CLR;                               /**< Fractional PLL Control Register, offset: 0x8 */
96727     __IO uint32_t TOG;                               /**< Fractional PLL Control Register, offset: 0xC */
96728   } CTRL0;
96729   struct {                                         /* offset: 0x10 */
96730     __IO uint32_t RW;                                /**< Fractional PLL Spread Spectrum Control Register, offset: 0x10 */
96731     __IO uint32_t SET;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x14 */
96732     __IO uint32_t CLR;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x18 */
96733     __IO uint32_t TOG;                               /**< Fractional PLL Spread Spectrum Control Register, offset: 0x1C */
96734   } SPREAD_SPECTRUM;
96735   struct {                                         /* offset: 0x20 */
96736     __IO uint32_t RW;                                /**< Fractional PLL Numerator Control Register, offset: 0x20 */
96737     __IO uint32_t SET;                               /**< Fractional PLL Numerator Control Register, offset: 0x24 */
96738     __IO uint32_t CLR;                               /**< Fractional PLL Numerator Control Register, offset: 0x28 */
96739     __IO uint32_t TOG;                               /**< Fractional PLL Numerator Control Register, offset: 0x2C */
96740   } NUMERATOR;
96741   struct {                                         /* offset: 0x30 */
96742     __IO uint32_t RW;                                /**< Fractional PLL Denominator Control Register, offset: 0x30 */
96743     __IO uint32_t SET;                               /**< Fractional PLL Denominator Control Register, offset: 0x34 */
96744     __IO uint32_t CLR;                               /**< Fractional PLL Denominator Control Register, offset: 0x38 */
96745     __IO uint32_t TOG;                               /**< Fractional PLL Denominator Control Register, offset: 0x3C */
96746   } DENOMINATOR;
96747 } VIDEO_PLL_Type;
96748 
96749 /* ----------------------------------------------------------------------------
96750    -- VIDEO_PLL Register Masks
96751    ---------------------------------------------------------------------------- */
96752 
96753 /*!
96754  * @addtogroup VIDEO_PLL_Register_Masks VIDEO_PLL Register Masks
96755  * @{
96756  */
96757 
96758 /*! @name CTRL0 - Fractional PLL Control Register */
96759 /*! @{ */
96760 
96761 #define VIDEO_PLL_CTRL0_DIV_SELECT_MASK          (0x7FU)
96762 #define VIDEO_PLL_CTRL0_DIV_SELECT_SHIFT         (0U)
96763 /*! DIV_SELECT - DIV_SELECT */
96764 #define VIDEO_PLL_CTRL0_DIV_SELECT(x)            (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DIV_SELECT_SHIFT)) & VIDEO_PLL_CTRL0_DIV_SELECT_MASK)
96765 
96766 #define VIDEO_PLL_CTRL0_ENABLE_ALT_MASK          (0x100U)
96767 #define VIDEO_PLL_CTRL0_ENABLE_ALT_SHIFT         (8U)
96768 /*! ENABLE_ALT - ENABLE_ALT
96769  *  0b0..Disable the alternate clock output
96770  *  0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed
96771  */
96772 #define VIDEO_PLL_CTRL0_ENABLE_ALT(x)            (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_ENABLE_ALT_SHIFT)) & VIDEO_PLL_CTRL0_ENABLE_ALT_MASK)
96773 
96774 #define VIDEO_PLL_CTRL0_HOLD_RING_OFF_MASK       (0x2000U)
96775 #define VIDEO_PLL_CTRL0_HOLD_RING_OFF_SHIFT      (13U)
96776 /*! HOLD_RING_OFF - PLL Start up initialization
96777  *  0b0..Normal operation
96778  *  0b1..Initialize PLL start up
96779  */
96780 #define VIDEO_PLL_CTRL0_HOLD_RING_OFF(x)         (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & VIDEO_PLL_CTRL0_HOLD_RING_OFF_MASK)
96781 
96782 #define VIDEO_PLL_CTRL0_POWERUP_MASK             (0x4000U)
96783 #define VIDEO_PLL_CTRL0_POWERUP_SHIFT            (14U)
96784 /*! POWERUP - POWERUP
96785  *  0b1..Power Up the PLL
96786  *  0b0..Power down the PLL
96787  */
96788 #define VIDEO_PLL_CTRL0_POWERUP(x)               (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_POWERUP_SHIFT)) & VIDEO_PLL_CTRL0_POWERUP_MASK)
96789 
96790 #define VIDEO_PLL_CTRL0_ENABLE_MASK              (0x8000U)
96791 #define VIDEO_PLL_CTRL0_ENABLE_SHIFT             (15U)
96792 /*! ENABLE - ENABLE
96793  *  0b1..Enable the clock output
96794  *  0b0..Disable the clock output
96795  */
96796 #define VIDEO_PLL_CTRL0_ENABLE(x)                (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_ENABLE_SHIFT)) & VIDEO_PLL_CTRL0_ENABLE_MASK)
96797 
96798 #define VIDEO_PLL_CTRL0_BYPASS_MASK              (0x10000U)
96799 #define VIDEO_PLL_CTRL0_BYPASS_SHIFT             (16U)
96800 /*! BYPASS - BYPASS
96801  *  0b1..Bypass the PLL
96802  *  0b0..No Bypass
96803  */
96804 #define VIDEO_PLL_CTRL0_BYPASS(x)                (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BYPASS_SHIFT)) & VIDEO_PLL_CTRL0_BYPASS_MASK)
96805 
96806 #define VIDEO_PLL_CTRL0_DITHER_EN_MASK           (0x20000U)
96807 #define VIDEO_PLL_CTRL0_DITHER_EN_SHIFT          (17U)
96808 /*! DITHER_EN - DITHER_EN
96809  *  0b0..Disable Dither
96810  *  0b1..Enable Dither
96811  */
96812 #define VIDEO_PLL_CTRL0_DITHER_EN(x)             (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DITHER_EN_SHIFT)) & VIDEO_PLL_CTRL0_DITHER_EN_MASK)
96813 
96814 #define VIDEO_PLL_CTRL0_BIAS_TRIM_MASK           (0x380000U)
96815 #define VIDEO_PLL_CTRL0_BIAS_TRIM_SHIFT          (19U)
96816 /*! BIAS_TRIM - BIAS_TRIM */
96817 #define VIDEO_PLL_CTRL0_BIAS_TRIM(x)             (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BIAS_TRIM_SHIFT)) & VIDEO_PLL_CTRL0_BIAS_TRIM_MASK)
96818 
96819 #define VIDEO_PLL_CTRL0_PLL_REG_EN_MASK          (0x400000U)
96820 #define VIDEO_PLL_CTRL0_PLL_REG_EN_SHIFT         (22U)
96821 /*! PLL_REG_EN - PLL_REG_EN */
96822 #define VIDEO_PLL_CTRL0_PLL_REG_EN(x)            (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_PLL_REG_EN_SHIFT)) & VIDEO_PLL_CTRL0_PLL_REG_EN_MASK)
96823 
96824 #define VIDEO_PLL_CTRL0_POST_DIV_SEL_MASK        (0xE000000U)
96825 #define VIDEO_PLL_CTRL0_POST_DIV_SEL_SHIFT       (25U)
96826 /*! POST_DIV_SEL - Post Divide Select
96827  *  0b000..Divide by 1
96828  *  0b001..Divide by 2
96829  *  0b010..Divide by 4
96830  *  0b011..Divide by 8
96831  *  0b100..Divide by 16
96832  *  0b101..Divide by 32
96833  */
96834 #define VIDEO_PLL_CTRL0_POST_DIV_SEL(x)          (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & VIDEO_PLL_CTRL0_POST_DIV_SEL_MASK)
96835 
96836 #define VIDEO_PLL_CTRL0_BIAS_SELECT_MASK         (0x20000000U)
96837 #define VIDEO_PLL_CTRL0_BIAS_SELECT_SHIFT        (29U)
96838 /*! BIAS_SELECT - BIAS_SELECT
96839  *  0b0..Used in SoCs with a bias current of 10uA
96840  *  0b1..Used in SoCs with a bias current of 2uA
96841  */
96842 #define VIDEO_PLL_CTRL0_BIAS_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BIAS_SELECT_SHIFT)) & VIDEO_PLL_CTRL0_BIAS_SELECT_MASK)
96843 /*! @} */
96844 
96845 /*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */
96846 /*! @{ */
96847 
96848 #define VIDEO_PLL_SPREAD_SPECTRUM_STEP_MASK      (0x7FFFU)
96849 #define VIDEO_PLL_SPREAD_SPECTRUM_STEP_SHIFT     (0U)
96850 /*! STEP - Step */
96851 #define VIDEO_PLL_SPREAD_SPECTRUM_STEP(x)        (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_STEP_MASK)
96852 
96853 #define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_MASK    (0x8000U)
96854 #define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT   (15U)
96855 /*! ENABLE - Enable */
96856 #define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE(x)      (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_MASK)
96857 
96858 #define VIDEO_PLL_SPREAD_SPECTRUM_STOP_MASK      (0xFFFF0000U)
96859 #define VIDEO_PLL_SPREAD_SPECTRUM_STOP_SHIFT     (16U)
96860 /*! STOP - Stop */
96861 #define VIDEO_PLL_SPREAD_SPECTRUM_STOP(x)        (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_STOP_MASK)
96862 /*! @} */
96863 
96864 /*! @name NUMERATOR - Fractional PLL Numerator Control Register */
96865 /*! @{ */
96866 
96867 #define VIDEO_PLL_NUMERATOR_NUM_MASK             (0x3FFFFFFFU)
96868 #define VIDEO_PLL_NUMERATOR_NUM_SHIFT            (0U)
96869 /*! NUM - Numerator */
96870 #define VIDEO_PLL_NUMERATOR_NUM(x)               (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_NUMERATOR_NUM_SHIFT)) & VIDEO_PLL_NUMERATOR_NUM_MASK)
96871 /*! @} */
96872 
96873 /*! @name DENOMINATOR - Fractional PLL Denominator Control Register */
96874 /*! @{ */
96875 
96876 #define VIDEO_PLL_DENOMINATOR_DENOM_MASK         (0x3FFFFFFFU)
96877 #define VIDEO_PLL_DENOMINATOR_DENOM_SHIFT        (0U)
96878 /*! DENOM - Denominator */
96879 #define VIDEO_PLL_DENOMINATOR_DENOM(x)           (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_DENOMINATOR_DENOM_SHIFT)) & VIDEO_PLL_DENOMINATOR_DENOM_MASK)
96880 /*! @} */
96881 
96882 
96883 /*!
96884  * @}
96885  */ /* end of group VIDEO_PLL_Register_Masks */
96886 
96887 
96888 /* VIDEO_PLL - Peripheral instance base addresses */
96889 /** Peripheral VIDEO_PLL base address */
96890 #define VIDEO_PLL_BASE                           (0u)
96891 /** Peripheral VIDEO_PLL base pointer */
96892 #define VIDEO_PLL                                ((VIDEO_PLL_Type *)VIDEO_PLL_BASE)
96893 /** Array initializer of VIDEO_PLL peripheral base addresses */
96894 #define VIDEO_PLL_BASE_ADDRS                     { VIDEO_PLL_BASE }
96895 /** Array initializer of VIDEO_PLL peripheral base pointers */
96896 #define VIDEO_PLL_BASE_PTRS                      { VIDEO_PLL }
96897 
96898 /*!
96899  * @}
96900  */ /* end of group VIDEO_PLL_Peripheral_Access_Layer */
96901 
96902 
96903 /* ----------------------------------------------------------------------------
96904    -- VMBANDGAP Peripheral Access Layer
96905    ---------------------------------------------------------------------------- */
96906 
96907 /*!
96908  * @addtogroup VMBANDGAP_Peripheral_Access_Layer VMBANDGAP Peripheral Access Layer
96909  * @{
96910  */
96911 
96912 /** VMBANDGAP - Register Layout Typedef */
96913 typedef struct {
96914   struct {                                         /* offset: 0x0 */
96915     __IO uint32_t RW;                                /**< Analog Control Register CTRL0, offset: 0x0 */
96916     __IO uint32_t SET;                               /**< Analog Control Register CTRL0, offset: 0x4 */
96917     __IO uint32_t CLR;                               /**< Analog Control Register CTRL0, offset: 0x8 */
96918     __IO uint32_t TOG;                               /**< Analog Control Register CTRL0, offset: 0xC */
96919   } CTRL0;
96920        uint8_t RESERVED_0[64];
96921   struct {                                         /* offset: 0x50 */
96922     __I  uint32_t RW;                                /**< Analog Status Register STAT0, offset: 0x50 */
96923     __I  uint32_t SET;                               /**< Analog Status Register STAT0, offset: 0x54 */
96924     __I  uint32_t CLR;                               /**< Analog Status Register STAT0, offset: 0x58 */
96925     __I  uint32_t TOG;                               /**< Analog Status Register STAT0, offset: 0x5C */
96926   } STAT0;
96927 } VMBANDGAP_Type;
96928 
96929 /* ----------------------------------------------------------------------------
96930    -- VMBANDGAP Register Masks
96931    ---------------------------------------------------------------------------- */
96932 
96933 /*!
96934  * @addtogroup VMBANDGAP_Register_Masks VMBANDGAP Register Masks
96935  * @{
96936  */
96937 
96938 /*! @name CTRL0 - Analog Control Register CTRL0 */
96939 /*! @{ */
96940 
96941 #define VMBANDGAP_CTRL0_REFTOP_PWD_MASK          (0x1U)
96942 #define VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT         (0U)
96943 /*! REFTOP_PWD - Master power-down for bandgap module */
96944 #define VMBANDGAP_CTRL0_REFTOP_PWD(x)            (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWD_MASK)
96945 
96946 #define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U)
96947 #define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U)
96948 /*! REFTOP_LINREGREF_PWD - Power-down for bandgap voltage-reference buffer */
96949 #define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x)  (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK)
96950 
96951 #define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK     (0x4U)
96952 #define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT    (2U)
96953 /*! REFTOP_PWDVBGUP - Power-down VBGUP detector in bandgap */
96954 #define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP(x)       (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK)
96955 
96956 #define VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK     (0x8U)
96957 #define VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT    (3U)
96958 /*! REFTOP_LOWPOWER - Low-power control bit */
96959 #define VMBANDGAP_CTRL0_REFTOP_LOWPOWER(x)       (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK)
96960 
96961 #define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK  (0x10U)
96962 #define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U)
96963 /*! REFTOP_SELFBIASOFF - bandgap self-bias control bit */
96964 #define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF(x)    (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK)
96965 /*! @} */
96966 
96967 /*! @name STAT0 - Analog Status Register STAT0 */
96968 /*! @{ */
96969 
96970 #define VMBANDGAP_STAT0_REFTOP_VBGUP_MASK        (0x1U)
96971 #define VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT       (0U)
96972 /*! REFTOP_VBGUP - Brief description here */
96973 #define VMBANDGAP_STAT0_REFTOP_VBGUP(x)          (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT)) & VMBANDGAP_STAT0_REFTOP_VBGUP_MASK)
96974 
96975 #define VMBANDGAP_STAT0_VDD1_PORB_MASK           (0x2U)
96976 #define VMBANDGAP_STAT0_VDD1_PORB_SHIFT          (1U)
96977 /*! VDD1_PORB - Brief description here */
96978 #define VMBANDGAP_STAT0_VDD1_PORB(x)             (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD1_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD1_PORB_MASK)
96979 
96980 #define VMBANDGAP_STAT0_VDD2_PORB_MASK           (0x4U)
96981 #define VMBANDGAP_STAT0_VDD2_PORB_SHIFT          (2U)
96982 /*! VDD2_PORB - Brief description here */
96983 #define VMBANDGAP_STAT0_VDD2_PORB(x)             (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD2_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD2_PORB_MASK)
96984 
96985 #define VMBANDGAP_STAT0_VDD3_PORB_MASK           (0x8U)
96986 #define VMBANDGAP_STAT0_VDD3_PORB_SHIFT          (3U)
96987 /*! VDD3_PORB - Brief description here */
96988 #define VMBANDGAP_STAT0_VDD3_PORB(x)             (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD3_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD3_PORB_MASK)
96989 /*! @} */
96990 
96991 
96992 /*!
96993  * @}
96994  */ /* end of group VMBANDGAP_Register_Masks */
96995 
96996 
96997 /* VMBANDGAP - Peripheral instance base addresses */
96998 /** Peripheral VMBANDGAP base address */
96999 #define VMBANDGAP_BASE                           (0u)
97000 /** Peripheral VMBANDGAP base pointer */
97001 #define VMBANDGAP                                ((VMBANDGAP_Type *)VMBANDGAP_BASE)
97002 /** Array initializer of VMBANDGAP peripheral base addresses */
97003 #define VMBANDGAP_BASE_ADDRS                     { VMBANDGAP_BASE }
97004 /** Array initializer of VMBANDGAP peripheral base pointers */
97005 #define VMBANDGAP_BASE_PTRS                      { VMBANDGAP }
97006 
97007 /*!
97008  * @}
97009  */ /* end of group VMBANDGAP_Peripheral_Access_Layer */
97010 
97011 
97012 /* ----------------------------------------------------------------------------
97013    -- WDOG Peripheral Access Layer
97014    ---------------------------------------------------------------------------- */
97015 
97016 /*!
97017  * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
97018  * @{
97019  */
97020 
97021 /** WDOG - Register Layout Typedef */
97022 typedef struct {
97023   __IO uint16_t WCR;                               /**< Watchdog Control Register, offset: 0x0 */
97024   __IO uint16_t WSR;                               /**< Watchdog Service Register, offset: 0x2 */
97025   __I  uint16_t WRSR;                              /**< Watchdog Reset Status Register, offset: 0x4 */
97026   __IO uint16_t WICR;                              /**< Watchdog Interrupt Control Register, offset: 0x6 */
97027   __IO uint16_t WMCR;                              /**< Watchdog Miscellaneous Control Register, offset: 0x8 */
97028 } WDOG_Type;
97029 
97030 /* ----------------------------------------------------------------------------
97031    -- WDOG Register Masks
97032    ---------------------------------------------------------------------------- */
97033 
97034 /*!
97035  * @addtogroup WDOG_Register_Masks WDOG Register Masks
97036  * @{
97037  */
97038 
97039 /*! @name WCR - Watchdog Control Register */
97040 /*! @{ */
97041 
97042 #define WDOG_WCR_WDZST_MASK                      (0x1U)
97043 #define WDOG_WCR_WDZST_SHIFT                     (0U)
97044 /*! WDZST - WDZST
97045  *  0b0..Continue timer operation (Default).
97046  *  0b1..Suspend the watchdog timer.
97047  */
97048 #define WDOG_WCR_WDZST(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
97049 
97050 #define WDOG_WCR_WDBG_MASK                       (0x2U)
97051 #define WDOG_WCR_WDBG_SHIFT                      (1U)
97052 /*! WDBG - WDBG
97053  *  0b0..Continue WDOG timer operation (Default).
97054  *  0b1..Suspend the watchdog timer.
97055  */
97056 #define WDOG_WCR_WDBG(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
97057 
97058 #define WDOG_WCR_WDE_MASK                        (0x4U)
97059 #define WDOG_WCR_WDE_SHIFT                       (2U)
97060 /*! WDE - WDE
97061  *  0b0..Disable the Watchdog (Default).
97062  *  0b1..Enable the Watchdog.
97063  */
97064 #define WDOG_WCR_WDE(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
97065 
97066 #define WDOG_WCR_WDT_MASK                        (0x8U)
97067 #define WDOG_WCR_WDT_SHIFT                       (3U)
97068 /*! WDT - WDT
97069  *  0b0..No effect on WDOG_B (Default).
97070  *  0b1..Assert WDOG_B upon a Watchdog Time-out event.
97071  */
97072 #define WDOG_WCR_WDT(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
97073 
97074 #define WDOG_WCR_SRS_MASK                        (0x10U)
97075 #define WDOG_WCR_SRS_SHIFT                       (4U)
97076 /*! SRS - SRS
97077  *  0b0..Assert system reset signal.
97078  *  0b1..No effect on the system (Default).
97079  */
97080 #define WDOG_WCR_SRS(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
97081 
97082 #define WDOG_WCR_WDA_MASK                        (0x20U)
97083 #define WDOG_WCR_WDA_SHIFT                       (5U)
97084 /*! WDA - WDA
97085  *  0b0..Assert WDOG_B output.
97086  *  0b1..No effect on system (Default).
97087  */
97088 #define WDOG_WCR_WDA(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
97089 
97090 #define WDOG_WCR_SRE_MASK                        (0x40U)
97091 #define WDOG_WCR_SRE_SHIFT                       (6U)
97092 /*! SRE - Software Reset Extension, an optional way to generate software reset
97093  *  0b0..using original way to generate software reset (default)
97094  *  0b1..using new way to generate software reset.
97095  */
97096 #define WDOG_WCR_SRE(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
97097 
97098 #define WDOG_WCR_WDW_MASK                        (0x80U)
97099 #define WDOG_WCR_WDW_SHIFT                       (7U)
97100 /*! WDW - WDW
97101  *  0b0..Continue WDOG timer operation (Default).
97102  *  0b1..Suspend WDOG timer operation.
97103  */
97104 #define WDOG_WCR_WDW(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
97105 
97106 #define WDOG_WCR_WT_MASK                         (0xFF00U)
97107 #define WDOG_WCR_WT_SHIFT                        (8U)
97108 /*! WT - WT
97109  *  0b00000000..- 0.5 Seconds (Default).
97110  *  0b00000001..- 1.0 Seconds.
97111  *  0b00000010..- 1.5 Seconds.
97112  *  0b00000011..- 2.0 Seconds.
97113  *  0b11111111..- 128 Seconds.
97114  */
97115 #define WDOG_WCR_WT(x)                           (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
97116 /*! @} */
97117 
97118 /*! @name WSR - Watchdog Service Register */
97119 /*! @{ */
97120 
97121 #define WDOG_WSR_WSR_MASK                        (0xFFFFU)
97122 #define WDOG_WSR_WSR_SHIFT                       (0U)
97123 /*! WSR - WSR
97124  *  0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR).
97125  *  0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).
97126  */
97127 #define WDOG_WSR_WSR(x)                          (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
97128 /*! @} */
97129 
97130 /*! @name WRSR - Watchdog Reset Status Register */
97131 /*! @{ */
97132 
97133 #define WDOG_WRSR_SFTW_MASK                      (0x1U)
97134 #define WDOG_WRSR_SFTW_SHIFT                     (0U)
97135 /*! SFTW - SFTW
97136  *  0b0..Reset is not the result of a software reset.
97137  *  0b1..Reset is the result of a software reset.
97138  */
97139 #define WDOG_WRSR_SFTW(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
97140 
97141 #define WDOG_WRSR_TOUT_MASK                      (0x2U)
97142 #define WDOG_WRSR_TOUT_SHIFT                     (1U)
97143 /*! TOUT - TOUT
97144  *  0b0..Reset is not the result of a WDOG timeout.
97145  *  0b1..Reset is the result of a WDOG timeout.
97146  */
97147 #define WDOG_WRSR_TOUT(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
97148 
97149 #define WDOG_WRSR_POR_MASK                       (0x10U)
97150 #define WDOG_WRSR_POR_SHIFT                      (4U)
97151 /*! POR - POR
97152  *  0b0..Reset is not the result of a power on reset.
97153  *  0b1..Reset is the result of a power on reset.
97154  */
97155 #define WDOG_WRSR_POR(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
97156 /*! @} */
97157 
97158 /*! @name WICR - Watchdog Interrupt Control Register */
97159 /*! @{ */
97160 
97161 #define WDOG_WICR_WICT_MASK                      (0xFFU)
97162 #define WDOG_WICR_WICT_SHIFT                     (0U)
97163 /*! WICT - WICT
97164  *  0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
97165  *  0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
97166  *  0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
97167  *  0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
97168  */
97169 #define WDOG_WICR_WICT(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
97170 
97171 #define WDOG_WICR_WTIS_MASK                      (0x4000U)
97172 #define WDOG_WICR_WTIS_SHIFT                     (14U)
97173 /*! WTIS - WTIS
97174  *  0b0..No interrupt has occurred (Default).
97175  *  0b1..Interrupt has occurred
97176  */
97177 #define WDOG_WICR_WTIS(x)                        (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
97178 
97179 #define WDOG_WICR_WIE_MASK                       (0x8000U)
97180 #define WDOG_WICR_WIE_SHIFT                      (15U)
97181 /*! WIE - WIE
97182  *  0b0..Disable Interrupt (Default).
97183  *  0b1..Enable Interrupt.
97184  */
97185 #define WDOG_WICR_WIE(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
97186 /*! @} */
97187 
97188 /*! @name WMCR - Watchdog Miscellaneous Control Register */
97189 /*! @{ */
97190 
97191 #define WDOG_WMCR_PDE_MASK                       (0x1U)
97192 #define WDOG_WMCR_PDE_SHIFT                      (0U)
97193 /*! PDE - PDE
97194  *  0b0..Power Down Counter of WDOG is disabled.
97195  *  0b1..Power Down Counter of WDOG is enabled (Default).
97196  */
97197 #define WDOG_WMCR_PDE(x)                         (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
97198 /*! @} */
97199 
97200 
97201 /*!
97202  * @}
97203  */ /* end of group WDOG_Register_Masks */
97204 
97205 
97206 /* WDOG - Peripheral instance base addresses */
97207 /** Peripheral WDOG1 base address */
97208 #define WDOG1_BASE                               (0x40030000u)
97209 /** Peripheral WDOG1 base pointer */
97210 #define WDOG1                                    ((WDOG_Type *)WDOG1_BASE)
97211 /** Peripheral WDOG2 base address */
97212 #define WDOG2_BASE                               (0x40034000u)
97213 /** Peripheral WDOG2 base pointer */
97214 #define WDOG2                                    ((WDOG_Type *)WDOG2_BASE)
97215 /** Array initializer of WDOG peripheral base addresses */
97216 #define WDOG_BASE_ADDRS                          { 0u, WDOG1_BASE, WDOG2_BASE }
97217 /** Array initializer of WDOG peripheral base pointers */
97218 #define WDOG_BASE_PTRS                           { (WDOG_Type *)0u, WDOG1, WDOG2 }
97219 /** Interrupt vectors for the WDOG peripheral type */
97220 #define WDOG_IRQS                                { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }
97221 
97222 /*!
97223  * @}
97224  */ /* end of group WDOG_Peripheral_Access_Layer */
97225 
97226 
97227 /* ----------------------------------------------------------------------------
97228    -- XBARA Peripheral Access Layer
97229    ---------------------------------------------------------------------------- */
97230 
97231 /*!
97232  * @addtogroup XBARA_Peripheral_Access_Layer XBARA Peripheral Access Layer
97233  * @{
97234  */
97235 
97236 /** XBARA - Register Layout Typedef */
97237 typedef struct {
97238   __IO uint16_t SEL0;                              /**< Crossbar A Select Register 0, offset: 0x0 */
97239   __IO uint16_t SEL1;                              /**< Crossbar A Select Register 1, offset: 0x2 */
97240   __IO uint16_t SEL2;                              /**< Crossbar A Select Register 2, offset: 0x4 */
97241   __IO uint16_t SEL3;                              /**< Crossbar A Select Register 3, offset: 0x6 */
97242   __IO uint16_t SEL4;                              /**< Crossbar A Select Register 4, offset: 0x8 */
97243   __IO uint16_t SEL5;                              /**< Crossbar A Select Register 5, offset: 0xA */
97244   __IO uint16_t SEL6;                              /**< Crossbar A Select Register 6, offset: 0xC */
97245   __IO uint16_t SEL7;                              /**< Crossbar A Select Register 7, offset: 0xE */
97246   __IO uint16_t SEL8;                              /**< Crossbar A Select Register 8, offset: 0x10 */
97247   __IO uint16_t SEL9;                              /**< Crossbar A Select Register 9, offset: 0x12 */
97248   __IO uint16_t SEL10;                             /**< Crossbar A Select Register 10, offset: 0x14 */
97249   __IO uint16_t SEL11;                             /**< Crossbar A Select Register 11, offset: 0x16 */
97250   __IO uint16_t SEL12;                             /**< Crossbar A Select Register 12, offset: 0x18 */
97251   __IO uint16_t SEL13;                             /**< Crossbar A Select Register 13, offset: 0x1A */
97252   __IO uint16_t SEL14;                             /**< Crossbar A Select Register 14, offset: 0x1C */
97253   __IO uint16_t SEL15;                             /**< Crossbar A Select Register 15, offset: 0x1E */
97254   __IO uint16_t SEL16;                             /**< Crossbar A Select Register 16, offset: 0x20 */
97255   __IO uint16_t SEL17;                             /**< Crossbar A Select Register 17, offset: 0x22 */
97256   __IO uint16_t SEL18;                             /**< Crossbar A Select Register 18, offset: 0x24 */
97257   __IO uint16_t SEL19;                             /**< Crossbar A Select Register 19, offset: 0x26 */
97258   __IO uint16_t SEL20;                             /**< Crossbar A Select Register 20, offset: 0x28 */
97259   __IO uint16_t SEL21;                             /**< Crossbar A Select Register 21, offset: 0x2A */
97260   __IO uint16_t SEL22;                             /**< Crossbar A Select Register 22, offset: 0x2C */
97261   __IO uint16_t SEL23;                             /**< Crossbar A Select Register 23, offset: 0x2E */
97262   __IO uint16_t SEL24;                             /**< Crossbar A Select Register 24, offset: 0x30 */
97263   __IO uint16_t SEL25;                             /**< Crossbar A Select Register 25, offset: 0x32 */
97264   __IO uint16_t SEL26;                             /**< Crossbar A Select Register 26, offset: 0x34 */
97265   __IO uint16_t SEL27;                             /**< Crossbar A Select Register 27, offset: 0x36 */
97266   __IO uint16_t SEL28;                             /**< Crossbar A Select Register 28, offset: 0x38 */
97267   __IO uint16_t SEL29;                             /**< Crossbar A Select Register 29, offset: 0x3A */
97268   __IO uint16_t SEL30;                             /**< Crossbar A Select Register 30, offset: 0x3C */
97269   __IO uint16_t SEL31;                             /**< Crossbar A Select Register 31, offset: 0x3E */
97270   __IO uint16_t SEL32;                             /**< Crossbar A Select Register 32, offset: 0x40 */
97271   __IO uint16_t SEL33;                             /**< Crossbar A Select Register 33, offset: 0x42 */
97272   __IO uint16_t SEL34;                             /**< Crossbar A Select Register 34, offset: 0x44 */
97273   __IO uint16_t SEL35;                             /**< Crossbar A Select Register 35, offset: 0x46 */
97274   __IO uint16_t SEL36;                             /**< Crossbar A Select Register 36, offset: 0x48 */
97275   __IO uint16_t SEL37;                             /**< Crossbar A Select Register 37, offset: 0x4A */
97276   __IO uint16_t SEL38;                             /**< Crossbar A Select Register 38, offset: 0x4C */
97277   __IO uint16_t SEL39;                             /**< Crossbar A Select Register 39, offset: 0x4E */
97278   __IO uint16_t SEL40;                             /**< Crossbar A Select Register 40, offset: 0x50 */
97279   __IO uint16_t SEL41;                             /**< Crossbar A Select Register 41, offset: 0x52 */
97280   __IO uint16_t SEL42;                             /**< Crossbar A Select Register 42, offset: 0x54 */
97281   __IO uint16_t SEL43;                             /**< Crossbar A Select Register 43, offset: 0x56 */
97282   __IO uint16_t SEL44;                             /**< Crossbar A Select Register 44, offset: 0x58 */
97283   __IO uint16_t SEL45;                             /**< Crossbar A Select Register 45, offset: 0x5A */
97284   __IO uint16_t SEL46;                             /**< Crossbar A Select Register 46, offset: 0x5C */
97285   __IO uint16_t SEL47;                             /**< Crossbar A Select Register 47, offset: 0x5E */
97286   __IO uint16_t SEL48;                             /**< Crossbar A Select Register 48, offset: 0x60 */
97287   __IO uint16_t SEL49;                             /**< Crossbar A Select Register 49, offset: 0x62 */
97288   __IO uint16_t SEL50;                             /**< Crossbar A Select Register 50, offset: 0x64 */
97289   __IO uint16_t SEL51;                             /**< Crossbar A Select Register 51, offset: 0x66 */
97290   __IO uint16_t SEL52;                             /**< Crossbar A Select Register 52, offset: 0x68 */
97291   __IO uint16_t SEL53;                             /**< Crossbar A Select Register 53, offset: 0x6A */
97292   __IO uint16_t SEL54;                             /**< Crossbar A Select Register 54, offset: 0x6C */
97293   __IO uint16_t SEL55;                             /**< Crossbar A Select Register 55, offset: 0x6E */
97294   __IO uint16_t SEL56;                             /**< Crossbar A Select Register 56, offset: 0x70 */
97295   __IO uint16_t SEL57;                             /**< Crossbar A Select Register 57, offset: 0x72 */
97296   __IO uint16_t SEL58;                             /**< Crossbar A Select Register 58, offset: 0x74 */
97297   __IO uint16_t SEL59;                             /**< Crossbar A Select Register 59, offset: 0x76 */
97298   __IO uint16_t SEL60;                             /**< Crossbar A Select Register 60, offset: 0x78 */
97299   __IO uint16_t SEL61;                             /**< Crossbar A Select Register 61, offset: 0x7A */
97300   __IO uint16_t SEL62;                             /**< Crossbar A Select Register 62, offset: 0x7C */
97301   __IO uint16_t SEL63;                             /**< Crossbar A Select Register 63, offset: 0x7E */
97302   __IO uint16_t SEL64;                             /**< Crossbar A Select Register 64, offset: 0x80 */
97303   __IO uint16_t SEL65;                             /**< Crossbar A Select Register 65, offset: 0x82 */
97304   __IO uint16_t SEL66;                             /**< Crossbar A Select Register 66, offset: 0x84 */
97305   __IO uint16_t SEL67;                             /**< Crossbar A Select Register 67, offset: 0x86 */
97306   __IO uint16_t SEL68;                             /**< Crossbar A Select Register 68, offset: 0x88 */
97307   __IO uint16_t SEL69;                             /**< Crossbar A Select Register 69, offset: 0x8A */
97308   __IO uint16_t SEL70;                             /**< Crossbar A Select Register 70, offset: 0x8C */
97309   __IO uint16_t SEL71;                             /**< Crossbar A Select Register 71, offset: 0x8E */
97310   __IO uint16_t SEL72;                             /**< Crossbar A Select Register 72, offset: 0x90 */
97311   __IO uint16_t SEL73;                             /**< Crossbar A Select Register 73, offset: 0x92 */
97312   __IO uint16_t SEL74;                             /**< Crossbar A Select Register 74, offset: 0x94 */
97313   __IO uint16_t SEL75;                             /**< Crossbar A Select Register 75, offset: 0x96 */
97314   __IO uint16_t SEL76;                             /**< Crossbar A Select Register 76, offset: 0x98 */
97315   __IO uint16_t SEL77;                             /**< Crossbar A Select Register 77, offset: 0x9A */
97316   __IO uint16_t SEL78;                             /**< Crossbar A Select Register 78, offset: 0x9C */
97317   __IO uint16_t SEL79;                             /**< Crossbar A Select Register 79, offset: 0x9E */
97318   __IO uint16_t SEL80;                             /**< Crossbar A Select Register 80, offset: 0xA0 */
97319   __IO uint16_t SEL81;                             /**< Crossbar A Select Register 81, offset: 0xA2 */
97320   __IO uint16_t SEL82;                             /**< Crossbar A Select Register 82, offset: 0xA4 */
97321   __IO uint16_t SEL83;                             /**< Crossbar A Select Register 83, offset: 0xA6 */
97322   __IO uint16_t SEL84;                             /**< Crossbar A Select Register 84, offset: 0xA8 */
97323   __IO uint16_t SEL85;                             /**< Crossbar A Select Register 85, offset: 0xAA */
97324   __IO uint16_t SEL86;                             /**< Crossbar A Select Register 86, offset: 0xAC */
97325   __IO uint16_t SEL87;                             /**< Crossbar A Select Register 87, offset: 0xAE */
97326   __IO uint16_t CTRL0;                             /**< Crossbar A Control Register 0, offset: 0xB0 */
97327   __IO uint16_t CTRL1;                             /**< Crossbar A Control Register 1, offset: 0xB2 */
97328 } XBARA_Type;
97329 
97330 /* ----------------------------------------------------------------------------
97331    -- XBARA Register Masks
97332    ---------------------------------------------------------------------------- */
97333 
97334 /*!
97335  * @addtogroup XBARA_Register_Masks XBARA Register Masks
97336  * @{
97337  */
97338 
97339 /*! @name SEL0 - Crossbar A Select Register 0 */
97340 /*! @{ */
97341 
97342 #define XBARA_SEL0_SEL0_MASK                     (0xFFU)
97343 #define XBARA_SEL0_SEL0_SHIFT                    (0U)
97344 #define XBARA_SEL0_SEL0(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)
97345 
97346 #define XBARA_SEL0_SEL1_MASK                     (0xFF00U)
97347 #define XBARA_SEL0_SEL1_SHIFT                    (8U)
97348 #define XBARA_SEL0_SEL1(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)
97349 /*! @} */
97350 
97351 /*! @name SEL1 - Crossbar A Select Register 1 */
97352 /*! @{ */
97353 
97354 #define XBARA_SEL1_SEL2_MASK                     (0xFFU)
97355 #define XBARA_SEL1_SEL2_SHIFT                    (0U)
97356 #define XBARA_SEL1_SEL2(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)
97357 
97358 #define XBARA_SEL1_SEL3_MASK                     (0xFF00U)
97359 #define XBARA_SEL1_SEL3_SHIFT                    (8U)
97360 #define XBARA_SEL1_SEL3(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)
97361 /*! @} */
97362 
97363 /*! @name SEL2 - Crossbar A Select Register 2 */
97364 /*! @{ */
97365 
97366 #define XBARA_SEL2_SEL4_MASK                     (0xFFU)
97367 #define XBARA_SEL2_SEL4_SHIFT                    (0U)
97368 #define XBARA_SEL2_SEL4(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)
97369 
97370 #define XBARA_SEL2_SEL5_MASK                     (0xFF00U)
97371 #define XBARA_SEL2_SEL5_SHIFT                    (8U)
97372 #define XBARA_SEL2_SEL5(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)
97373 /*! @} */
97374 
97375 /*! @name SEL3 - Crossbar A Select Register 3 */
97376 /*! @{ */
97377 
97378 #define XBARA_SEL3_SEL6_MASK                     (0xFFU)
97379 #define XBARA_SEL3_SEL6_SHIFT                    (0U)
97380 #define XBARA_SEL3_SEL6(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)
97381 
97382 #define XBARA_SEL3_SEL7_MASK                     (0xFF00U)
97383 #define XBARA_SEL3_SEL7_SHIFT                    (8U)
97384 #define XBARA_SEL3_SEL7(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)
97385 /*! @} */
97386 
97387 /*! @name SEL4 - Crossbar A Select Register 4 */
97388 /*! @{ */
97389 
97390 #define XBARA_SEL4_SEL8_MASK                     (0xFFU)
97391 #define XBARA_SEL4_SEL8_SHIFT                    (0U)
97392 #define XBARA_SEL4_SEL8(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)
97393 
97394 #define XBARA_SEL4_SEL9_MASK                     (0xFF00U)
97395 #define XBARA_SEL4_SEL9_SHIFT                    (8U)
97396 #define XBARA_SEL4_SEL9(x)                       (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)
97397 /*! @} */
97398 
97399 /*! @name SEL5 - Crossbar A Select Register 5 */
97400 /*! @{ */
97401 
97402 #define XBARA_SEL5_SEL10_MASK                    (0xFFU)
97403 #define XBARA_SEL5_SEL10_SHIFT                   (0U)
97404 #define XBARA_SEL5_SEL10(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)
97405 
97406 #define XBARA_SEL5_SEL11_MASK                    (0xFF00U)
97407 #define XBARA_SEL5_SEL11_SHIFT                   (8U)
97408 #define XBARA_SEL5_SEL11(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)
97409 /*! @} */
97410 
97411 /*! @name SEL6 - Crossbar A Select Register 6 */
97412 /*! @{ */
97413 
97414 #define XBARA_SEL6_SEL12_MASK                    (0xFFU)
97415 #define XBARA_SEL6_SEL12_SHIFT                   (0U)
97416 #define XBARA_SEL6_SEL12(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)
97417 
97418 #define XBARA_SEL6_SEL13_MASK                    (0xFF00U)
97419 #define XBARA_SEL6_SEL13_SHIFT                   (8U)
97420 #define XBARA_SEL6_SEL13(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)
97421 /*! @} */
97422 
97423 /*! @name SEL7 - Crossbar A Select Register 7 */
97424 /*! @{ */
97425 
97426 #define XBARA_SEL7_SEL14_MASK                    (0xFFU)
97427 #define XBARA_SEL7_SEL14_SHIFT                   (0U)
97428 #define XBARA_SEL7_SEL14(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)
97429 
97430 #define XBARA_SEL7_SEL15_MASK                    (0xFF00U)
97431 #define XBARA_SEL7_SEL15_SHIFT                   (8U)
97432 #define XBARA_SEL7_SEL15(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)
97433 /*! @} */
97434 
97435 /*! @name SEL8 - Crossbar A Select Register 8 */
97436 /*! @{ */
97437 
97438 #define XBARA_SEL8_SEL16_MASK                    (0xFFU)
97439 #define XBARA_SEL8_SEL16_SHIFT                   (0U)
97440 #define XBARA_SEL8_SEL16(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)
97441 
97442 #define XBARA_SEL8_SEL17_MASK                    (0xFF00U)
97443 #define XBARA_SEL8_SEL17_SHIFT                   (8U)
97444 #define XBARA_SEL8_SEL17(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)
97445 /*! @} */
97446 
97447 /*! @name SEL9 - Crossbar A Select Register 9 */
97448 /*! @{ */
97449 
97450 #define XBARA_SEL9_SEL18_MASK                    (0xFFU)
97451 #define XBARA_SEL9_SEL18_SHIFT                   (0U)
97452 #define XBARA_SEL9_SEL18(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)
97453 
97454 #define XBARA_SEL9_SEL19_MASK                    (0xFF00U)
97455 #define XBARA_SEL9_SEL19_SHIFT                   (8U)
97456 #define XBARA_SEL9_SEL19(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)
97457 /*! @} */
97458 
97459 /*! @name SEL10 - Crossbar A Select Register 10 */
97460 /*! @{ */
97461 
97462 #define XBARA_SEL10_SEL20_MASK                   (0xFFU)
97463 #define XBARA_SEL10_SEL20_SHIFT                  (0U)
97464 #define XBARA_SEL10_SEL20(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)
97465 
97466 #define XBARA_SEL10_SEL21_MASK                   (0xFF00U)
97467 #define XBARA_SEL10_SEL21_SHIFT                  (8U)
97468 #define XBARA_SEL10_SEL21(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)
97469 /*! @} */
97470 
97471 /*! @name SEL11 - Crossbar A Select Register 11 */
97472 /*! @{ */
97473 
97474 #define XBARA_SEL11_SEL22_MASK                   (0xFFU)
97475 #define XBARA_SEL11_SEL22_SHIFT                  (0U)
97476 #define XBARA_SEL11_SEL22(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)
97477 
97478 #define XBARA_SEL11_SEL23_MASK                   (0xFF00U)
97479 #define XBARA_SEL11_SEL23_SHIFT                  (8U)
97480 #define XBARA_SEL11_SEL23(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)
97481 /*! @} */
97482 
97483 /*! @name SEL12 - Crossbar A Select Register 12 */
97484 /*! @{ */
97485 
97486 #define XBARA_SEL12_SEL24_MASK                   (0xFFU)
97487 #define XBARA_SEL12_SEL24_SHIFT                  (0U)
97488 #define XBARA_SEL12_SEL24(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)
97489 
97490 #define XBARA_SEL12_SEL25_MASK                   (0xFF00U)
97491 #define XBARA_SEL12_SEL25_SHIFT                  (8U)
97492 #define XBARA_SEL12_SEL25(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)
97493 /*! @} */
97494 
97495 /*! @name SEL13 - Crossbar A Select Register 13 */
97496 /*! @{ */
97497 
97498 #define XBARA_SEL13_SEL26_MASK                   (0xFFU)
97499 #define XBARA_SEL13_SEL26_SHIFT                  (0U)
97500 #define XBARA_SEL13_SEL26(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)
97501 
97502 #define XBARA_SEL13_SEL27_MASK                   (0xFF00U)
97503 #define XBARA_SEL13_SEL27_SHIFT                  (8U)
97504 #define XBARA_SEL13_SEL27(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)
97505 /*! @} */
97506 
97507 /*! @name SEL14 - Crossbar A Select Register 14 */
97508 /*! @{ */
97509 
97510 #define XBARA_SEL14_SEL28_MASK                   (0xFFU)
97511 #define XBARA_SEL14_SEL28_SHIFT                  (0U)
97512 #define XBARA_SEL14_SEL28(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)
97513 
97514 #define XBARA_SEL14_SEL29_MASK                   (0xFF00U)
97515 #define XBARA_SEL14_SEL29_SHIFT                  (8U)
97516 #define XBARA_SEL14_SEL29(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)
97517 /*! @} */
97518 
97519 /*! @name SEL15 - Crossbar A Select Register 15 */
97520 /*! @{ */
97521 
97522 #define XBARA_SEL15_SEL30_MASK                   (0xFFU)
97523 #define XBARA_SEL15_SEL30_SHIFT                  (0U)
97524 #define XBARA_SEL15_SEL30(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)
97525 
97526 #define XBARA_SEL15_SEL31_MASK                   (0xFF00U)
97527 #define XBARA_SEL15_SEL31_SHIFT                  (8U)
97528 #define XBARA_SEL15_SEL31(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)
97529 /*! @} */
97530 
97531 /*! @name SEL16 - Crossbar A Select Register 16 */
97532 /*! @{ */
97533 
97534 #define XBARA_SEL16_SEL32_MASK                   (0xFFU)
97535 #define XBARA_SEL16_SEL32_SHIFT                  (0U)
97536 #define XBARA_SEL16_SEL32(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)
97537 
97538 #define XBARA_SEL16_SEL33_MASK                   (0xFF00U)
97539 #define XBARA_SEL16_SEL33_SHIFT                  (8U)
97540 #define XBARA_SEL16_SEL33(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)
97541 /*! @} */
97542 
97543 /*! @name SEL17 - Crossbar A Select Register 17 */
97544 /*! @{ */
97545 
97546 #define XBARA_SEL17_SEL34_MASK                   (0xFFU)
97547 #define XBARA_SEL17_SEL34_SHIFT                  (0U)
97548 #define XBARA_SEL17_SEL34(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)
97549 
97550 #define XBARA_SEL17_SEL35_MASK                   (0xFF00U)
97551 #define XBARA_SEL17_SEL35_SHIFT                  (8U)
97552 #define XBARA_SEL17_SEL35(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)
97553 /*! @} */
97554 
97555 /*! @name SEL18 - Crossbar A Select Register 18 */
97556 /*! @{ */
97557 
97558 #define XBARA_SEL18_SEL36_MASK                   (0xFFU)
97559 #define XBARA_SEL18_SEL36_SHIFT                  (0U)
97560 #define XBARA_SEL18_SEL36(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)
97561 
97562 #define XBARA_SEL18_SEL37_MASK                   (0xFF00U)
97563 #define XBARA_SEL18_SEL37_SHIFT                  (8U)
97564 #define XBARA_SEL18_SEL37(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)
97565 /*! @} */
97566 
97567 /*! @name SEL19 - Crossbar A Select Register 19 */
97568 /*! @{ */
97569 
97570 #define XBARA_SEL19_SEL38_MASK                   (0xFFU)
97571 #define XBARA_SEL19_SEL38_SHIFT                  (0U)
97572 #define XBARA_SEL19_SEL38(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)
97573 
97574 #define XBARA_SEL19_SEL39_MASK                   (0xFF00U)
97575 #define XBARA_SEL19_SEL39_SHIFT                  (8U)
97576 #define XBARA_SEL19_SEL39(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)
97577 /*! @} */
97578 
97579 /*! @name SEL20 - Crossbar A Select Register 20 */
97580 /*! @{ */
97581 
97582 #define XBARA_SEL20_SEL40_MASK                   (0xFFU)
97583 #define XBARA_SEL20_SEL40_SHIFT                  (0U)
97584 #define XBARA_SEL20_SEL40(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)
97585 
97586 #define XBARA_SEL20_SEL41_MASK                   (0xFF00U)
97587 #define XBARA_SEL20_SEL41_SHIFT                  (8U)
97588 #define XBARA_SEL20_SEL41(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)
97589 /*! @} */
97590 
97591 /*! @name SEL21 - Crossbar A Select Register 21 */
97592 /*! @{ */
97593 
97594 #define XBARA_SEL21_SEL42_MASK                   (0xFFU)
97595 #define XBARA_SEL21_SEL42_SHIFT                  (0U)
97596 #define XBARA_SEL21_SEL42(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)
97597 
97598 #define XBARA_SEL21_SEL43_MASK                   (0xFF00U)
97599 #define XBARA_SEL21_SEL43_SHIFT                  (8U)
97600 #define XBARA_SEL21_SEL43(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)
97601 /*! @} */
97602 
97603 /*! @name SEL22 - Crossbar A Select Register 22 */
97604 /*! @{ */
97605 
97606 #define XBARA_SEL22_SEL44_MASK                   (0xFFU)
97607 #define XBARA_SEL22_SEL44_SHIFT                  (0U)
97608 #define XBARA_SEL22_SEL44(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)
97609 
97610 #define XBARA_SEL22_SEL45_MASK                   (0xFF00U)
97611 #define XBARA_SEL22_SEL45_SHIFT                  (8U)
97612 #define XBARA_SEL22_SEL45(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)
97613 /*! @} */
97614 
97615 /*! @name SEL23 - Crossbar A Select Register 23 */
97616 /*! @{ */
97617 
97618 #define XBARA_SEL23_SEL46_MASK                   (0xFFU)
97619 #define XBARA_SEL23_SEL46_SHIFT                  (0U)
97620 #define XBARA_SEL23_SEL46(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)
97621 
97622 #define XBARA_SEL23_SEL47_MASK                   (0xFF00U)
97623 #define XBARA_SEL23_SEL47_SHIFT                  (8U)
97624 #define XBARA_SEL23_SEL47(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)
97625 /*! @} */
97626 
97627 /*! @name SEL24 - Crossbar A Select Register 24 */
97628 /*! @{ */
97629 
97630 #define XBARA_SEL24_SEL48_MASK                   (0xFFU)
97631 #define XBARA_SEL24_SEL48_SHIFT                  (0U)
97632 #define XBARA_SEL24_SEL48(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)
97633 
97634 #define XBARA_SEL24_SEL49_MASK                   (0xFF00U)
97635 #define XBARA_SEL24_SEL49_SHIFT                  (8U)
97636 #define XBARA_SEL24_SEL49(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)
97637 /*! @} */
97638 
97639 /*! @name SEL25 - Crossbar A Select Register 25 */
97640 /*! @{ */
97641 
97642 #define XBARA_SEL25_SEL50_MASK                   (0xFFU)
97643 #define XBARA_SEL25_SEL50_SHIFT                  (0U)
97644 #define XBARA_SEL25_SEL50(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)
97645 
97646 #define XBARA_SEL25_SEL51_MASK                   (0xFF00U)
97647 #define XBARA_SEL25_SEL51_SHIFT                  (8U)
97648 #define XBARA_SEL25_SEL51(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)
97649 /*! @} */
97650 
97651 /*! @name SEL26 - Crossbar A Select Register 26 */
97652 /*! @{ */
97653 
97654 #define XBARA_SEL26_SEL52_MASK                   (0xFFU)
97655 #define XBARA_SEL26_SEL52_SHIFT                  (0U)
97656 #define XBARA_SEL26_SEL52(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)
97657 
97658 #define XBARA_SEL26_SEL53_MASK                   (0xFF00U)
97659 #define XBARA_SEL26_SEL53_SHIFT                  (8U)
97660 #define XBARA_SEL26_SEL53(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)
97661 /*! @} */
97662 
97663 /*! @name SEL27 - Crossbar A Select Register 27 */
97664 /*! @{ */
97665 
97666 #define XBARA_SEL27_SEL54_MASK                   (0xFFU)
97667 #define XBARA_SEL27_SEL54_SHIFT                  (0U)
97668 #define XBARA_SEL27_SEL54(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)
97669 
97670 #define XBARA_SEL27_SEL55_MASK                   (0xFF00U)
97671 #define XBARA_SEL27_SEL55_SHIFT                  (8U)
97672 #define XBARA_SEL27_SEL55(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)
97673 /*! @} */
97674 
97675 /*! @name SEL28 - Crossbar A Select Register 28 */
97676 /*! @{ */
97677 
97678 #define XBARA_SEL28_SEL56_MASK                   (0xFFU)
97679 #define XBARA_SEL28_SEL56_SHIFT                  (0U)
97680 #define XBARA_SEL28_SEL56(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)
97681 
97682 #define XBARA_SEL28_SEL57_MASK                   (0xFF00U)
97683 #define XBARA_SEL28_SEL57_SHIFT                  (8U)
97684 #define XBARA_SEL28_SEL57(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)
97685 /*! @} */
97686 
97687 /*! @name SEL29 - Crossbar A Select Register 29 */
97688 /*! @{ */
97689 
97690 #define XBARA_SEL29_SEL58_MASK                   (0xFFU)
97691 #define XBARA_SEL29_SEL58_SHIFT                  (0U)
97692 #define XBARA_SEL29_SEL58(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)
97693 
97694 #define XBARA_SEL29_SEL59_MASK                   (0xFF00U)
97695 #define XBARA_SEL29_SEL59_SHIFT                  (8U)
97696 #define XBARA_SEL29_SEL59(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)
97697 /*! @} */
97698 
97699 /*! @name SEL30 - Crossbar A Select Register 30 */
97700 /*! @{ */
97701 
97702 #define XBARA_SEL30_SEL60_MASK                   (0xFFU)
97703 #define XBARA_SEL30_SEL60_SHIFT                  (0U)
97704 #define XBARA_SEL30_SEL60(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)
97705 
97706 #define XBARA_SEL30_SEL61_MASK                   (0xFF00U)
97707 #define XBARA_SEL30_SEL61_SHIFT                  (8U)
97708 #define XBARA_SEL30_SEL61(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)
97709 /*! @} */
97710 
97711 /*! @name SEL31 - Crossbar A Select Register 31 */
97712 /*! @{ */
97713 
97714 #define XBARA_SEL31_SEL62_MASK                   (0xFFU)
97715 #define XBARA_SEL31_SEL62_SHIFT                  (0U)
97716 #define XBARA_SEL31_SEL62(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)
97717 
97718 #define XBARA_SEL31_SEL63_MASK                   (0xFF00U)
97719 #define XBARA_SEL31_SEL63_SHIFT                  (8U)
97720 #define XBARA_SEL31_SEL63(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)
97721 /*! @} */
97722 
97723 /*! @name SEL32 - Crossbar A Select Register 32 */
97724 /*! @{ */
97725 
97726 #define XBARA_SEL32_SEL64_MASK                   (0xFFU)
97727 #define XBARA_SEL32_SEL64_SHIFT                  (0U)
97728 #define XBARA_SEL32_SEL64(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)
97729 
97730 #define XBARA_SEL32_SEL65_MASK                   (0xFF00U)
97731 #define XBARA_SEL32_SEL65_SHIFT                  (8U)
97732 #define XBARA_SEL32_SEL65(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)
97733 /*! @} */
97734 
97735 /*! @name SEL33 - Crossbar A Select Register 33 */
97736 /*! @{ */
97737 
97738 #define XBARA_SEL33_SEL66_MASK                   (0xFFU)
97739 #define XBARA_SEL33_SEL66_SHIFT                  (0U)
97740 #define XBARA_SEL33_SEL66(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)
97741 
97742 #define XBARA_SEL33_SEL67_MASK                   (0xFF00U)
97743 #define XBARA_SEL33_SEL67_SHIFT                  (8U)
97744 #define XBARA_SEL33_SEL67(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)
97745 /*! @} */
97746 
97747 /*! @name SEL34 - Crossbar A Select Register 34 */
97748 /*! @{ */
97749 
97750 #define XBARA_SEL34_SEL68_MASK                   (0xFFU)
97751 #define XBARA_SEL34_SEL68_SHIFT                  (0U)
97752 #define XBARA_SEL34_SEL68(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)
97753 
97754 #define XBARA_SEL34_SEL69_MASK                   (0xFF00U)
97755 #define XBARA_SEL34_SEL69_SHIFT                  (8U)
97756 #define XBARA_SEL34_SEL69(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)
97757 /*! @} */
97758 
97759 /*! @name SEL35 - Crossbar A Select Register 35 */
97760 /*! @{ */
97761 
97762 #define XBARA_SEL35_SEL70_MASK                   (0xFFU)
97763 #define XBARA_SEL35_SEL70_SHIFT                  (0U)
97764 #define XBARA_SEL35_SEL70(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)
97765 
97766 #define XBARA_SEL35_SEL71_MASK                   (0xFF00U)
97767 #define XBARA_SEL35_SEL71_SHIFT                  (8U)
97768 #define XBARA_SEL35_SEL71(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)
97769 /*! @} */
97770 
97771 /*! @name SEL36 - Crossbar A Select Register 36 */
97772 /*! @{ */
97773 
97774 #define XBARA_SEL36_SEL72_MASK                   (0xFFU)
97775 #define XBARA_SEL36_SEL72_SHIFT                  (0U)
97776 #define XBARA_SEL36_SEL72(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)
97777 
97778 #define XBARA_SEL36_SEL73_MASK                   (0xFF00U)
97779 #define XBARA_SEL36_SEL73_SHIFT                  (8U)
97780 #define XBARA_SEL36_SEL73(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)
97781 /*! @} */
97782 
97783 /*! @name SEL37 - Crossbar A Select Register 37 */
97784 /*! @{ */
97785 
97786 #define XBARA_SEL37_SEL74_MASK                   (0xFFU)
97787 #define XBARA_SEL37_SEL74_SHIFT                  (0U)
97788 #define XBARA_SEL37_SEL74(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)
97789 
97790 #define XBARA_SEL37_SEL75_MASK                   (0xFF00U)
97791 #define XBARA_SEL37_SEL75_SHIFT                  (8U)
97792 #define XBARA_SEL37_SEL75(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)
97793 /*! @} */
97794 
97795 /*! @name SEL38 - Crossbar A Select Register 38 */
97796 /*! @{ */
97797 
97798 #define XBARA_SEL38_SEL76_MASK                   (0xFFU)
97799 #define XBARA_SEL38_SEL76_SHIFT                  (0U)
97800 #define XBARA_SEL38_SEL76(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)
97801 
97802 #define XBARA_SEL38_SEL77_MASK                   (0xFF00U)
97803 #define XBARA_SEL38_SEL77_SHIFT                  (8U)
97804 #define XBARA_SEL38_SEL77(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)
97805 /*! @} */
97806 
97807 /*! @name SEL39 - Crossbar A Select Register 39 */
97808 /*! @{ */
97809 
97810 #define XBARA_SEL39_SEL78_MASK                   (0xFFU)
97811 #define XBARA_SEL39_SEL78_SHIFT                  (0U)
97812 #define XBARA_SEL39_SEL78(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)
97813 
97814 #define XBARA_SEL39_SEL79_MASK                   (0xFF00U)
97815 #define XBARA_SEL39_SEL79_SHIFT                  (8U)
97816 #define XBARA_SEL39_SEL79(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)
97817 /*! @} */
97818 
97819 /*! @name SEL40 - Crossbar A Select Register 40 */
97820 /*! @{ */
97821 
97822 #define XBARA_SEL40_SEL80_MASK                   (0xFFU)
97823 #define XBARA_SEL40_SEL80_SHIFT                  (0U)
97824 #define XBARA_SEL40_SEL80(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)
97825 
97826 #define XBARA_SEL40_SEL81_MASK                   (0xFF00U)
97827 #define XBARA_SEL40_SEL81_SHIFT                  (8U)
97828 #define XBARA_SEL40_SEL81(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)
97829 /*! @} */
97830 
97831 /*! @name SEL41 - Crossbar A Select Register 41 */
97832 /*! @{ */
97833 
97834 #define XBARA_SEL41_SEL82_MASK                   (0xFFU)
97835 #define XBARA_SEL41_SEL82_SHIFT                  (0U)
97836 #define XBARA_SEL41_SEL82(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)
97837 
97838 #define XBARA_SEL41_SEL83_MASK                   (0xFF00U)
97839 #define XBARA_SEL41_SEL83_SHIFT                  (8U)
97840 #define XBARA_SEL41_SEL83(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)
97841 /*! @} */
97842 
97843 /*! @name SEL42 - Crossbar A Select Register 42 */
97844 /*! @{ */
97845 
97846 #define XBARA_SEL42_SEL84_MASK                   (0xFFU)
97847 #define XBARA_SEL42_SEL84_SHIFT                  (0U)
97848 #define XBARA_SEL42_SEL84(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)
97849 
97850 #define XBARA_SEL42_SEL85_MASK                   (0xFF00U)
97851 #define XBARA_SEL42_SEL85_SHIFT                  (8U)
97852 #define XBARA_SEL42_SEL85(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)
97853 /*! @} */
97854 
97855 /*! @name SEL43 - Crossbar A Select Register 43 */
97856 /*! @{ */
97857 
97858 #define XBARA_SEL43_SEL86_MASK                   (0xFFU)
97859 #define XBARA_SEL43_SEL86_SHIFT                  (0U)
97860 #define XBARA_SEL43_SEL86(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)
97861 
97862 #define XBARA_SEL43_SEL87_MASK                   (0xFF00U)
97863 #define XBARA_SEL43_SEL87_SHIFT                  (8U)
97864 #define XBARA_SEL43_SEL87(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)
97865 /*! @} */
97866 
97867 /*! @name SEL44 - Crossbar A Select Register 44 */
97868 /*! @{ */
97869 
97870 #define XBARA_SEL44_SEL88_MASK                   (0xFFU)
97871 #define XBARA_SEL44_SEL88_SHIFT                  (0U)
97872 #define XBARA_SEL44_SEL88(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)
97873 
97874 #define XBARA_SEL44_SEL89_MASK                   (0xFF00U)
97875 #define XBARA_SEL44_SEL89_SHIFT                  (8U)
97876 #define XBARA_SEL44_SEL89(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)
97877 /*! @} */
97878 
97879 /*! @name SEL45 - Crossbar A Select Register 45 */
97880 /*! @{ */
97881 
97882 #define XBARA_SEL45_SEL90_MASK                   (0xFFU)
97883 #define XBARA_SEL45_SEL90_SHIFT                  (0U)
97884 #define XBARA_SEL45_SEL90(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)
97885 
97886 #define XBARA_SEL45_SEL91_MASK                   (0xFF00U)
97887 #define XBARA_SEL45_SEL91_SHIFT                  (8U)
97888 #define XBARA_SEL45_SEL91(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)
97889 /*! @} */
97890 
97891 /*! @name SEL46 - Crossbar A Select Register 46 */
97892 /*! @{ */
97893 
97894 #define XBARA_SEL46_SEL92_MASK                   (0xFFU)
97895 #define XBARA_SEL46_SEL92_SHIFT                  (0U)
97896 #define XBARA_SEL46_SEL92(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)
97897 
97898 #define XBARA_SEL46_SEL93_MASK                   (0xFF00U)
97899 #define XBARA_SEL46_SEL93_SHIFT                  (8U)
97900 #define XBARA_SEL46_SEL93(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)
97901 /*! @} */
97902 
97903 /*! @name SEL47 - Crossbar A Select Register 47 */
97904 /*! @{ */
97905 
97906 #define XBARA_SEL47_SEL94_MASK                   (0xFFU)
97907 #define XBARA_SEL47_SEL94_SHIFT                  (0U)
97908 #define XBARA_SEL47_SEL94(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)
97909 
97910 #define XBARA_SEL47_SEL95_MASK                   (0xFF00U)
97911 #define XBARA_SEL47_SEL95_SHIFT                  (8U)
97912 #define XBARA_SEL47_SEL95(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)
97913 /*! @} */
97914 
97915 /*! @name SEL48 - Crossbar A Select Register 48 */
97916 /*! @{ */
97917 
97918 #define XBARA_SEL48_SEL96_MASK                   (0xFFU)
97919 #define XBARA_SEL48_SEL96_SHIFT                  (0U)
97920 #define XBARA_SEL48_SEL96(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)
97921 
97922 #define XBARA_SEL48_SEL97_MASK                   (0xFF00U)
97923 #define XBARA_SEL48_SEL97_SHIFT                  (8U)
97924 #define XBARA_SEL48_SEL97(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)
97925 /*! @} */
97926 
97927 /*! @name SEL49 - Crossbar A Select Register 49 */
97928 /*! @{ */
97929 
97930 #define XBARA_SEL49_SEL98_MASK                   (0xFFU)
97931 #define XBARA_SEL49_SEL98_SHIFT                  (0U)
97932 #define XBARA_SEL49_SEL98(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)
97933 
97934 #define XBARA_SEL49_SEL99_MASK                   (0xFF00U)
97935 #define XBARA_SEL49_SEL99_SHIFT                  (8U)
97936 #define XBARA_SEL49_SEL99(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)
97937 /*! @} */
97938 
97939 /*! @name SEL50 - Crossbar A Select Register 50 */
97940 /*! @{ */
97941 
97942 #define XBARA_SEL50_SEL100_MASK                  (0xFFU)
97943 #define XBARA_SEL50_SEL100_SHIFT                 (0U)
97944 #define XBARA_SEL50_SEL100(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)
97945 
97946 #define XBARA_SEL50_SEL101_MASK                  (0xFF00U)
97947 #define XBARA_SEL50_SEL101_SHIFT                 (8U)
97948 #define XBARA_SEL50_SEL101(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)
97949 /*! @} */
97950 
97951 /*! @name SEL51 - Crossbar A Select Register 51 */
97952 /*! @{ */
97953 
97954 #define XBARA_SEL51_SEL102_MASK                  (0xFFU)
97955 #define XBARA_SEL51_SEL102_SHIFT                 (0U)
97956 #define XBARA_SEL51_SEL102(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)
97957 
97958 #define XBARA_SEL51_SEL103_MASK                  (0xFF00U)
97959 #define XBARA_SEL51_SEL103_SHIFT                 (8U)
97960 #define XBARA_SEL51_SEL103(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)
97961 /*! @} */
97962 
97963 /*! @name SEL52 - Crossbar A Select Register 52 */
97964 /*! @{ */
97965 
97966 #define XBARA_SEL52_SEL104_MASK                  (0xFFU)
97967 #define XBARA_SEL52_SEL104_SHIFT                 (0U)
97968 #define XBARA_SEL52_SEL104(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)
97969 
97970 #define XBARA_SEL52_SEL105_MASK                  (0xFF00U)
97971 #define XBARA_SEL52_SEL105_SHIFT                 (8U)
97972 #define XBARA_SEL52_SEL105(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)
97973 /*! @} */
97974 
97975 /*! @name SEL53 - Crossbar A Select Register 53 */
97976 /*! @{ */
97977 
97978 #define XBARA_SEL53_SEL106_MASK                  (0xFFU)
97979 #define XBARA_SEL53_SEL106_SHIFT                 (0U)
97980 #define XBARA_SEL53_SEL106(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)
97981 
97982 #define XBARA_SEL53_SEL107_MASK                  (0xFF00U)
97983 #define XBARA_SEL53_SEL107_SHIFT                 (8U)
97984 #define XBARA_SEL53_SEL107(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)
97985 /*! @} */
97986 
97987 /*! @name SEL54 - Crossbar A Select Register 54 */
97988 /*! @{ */
97989 
97990 #define XBARA_SEL54_SEL108_MASK                  (0xFFU)
97991 #define XBARA_SEL54_SEL108_SHIFT                 (0U)
97992 #define XBARA_SEL54_SEL108(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)
97993 
97994 #define XBARA_SEL54_SEL109_MASK                  (0xFF00U)
97995 #define XBARA_SEL54_SEL109_SHIFT                 (8U)
97996 #define XBARA_SEL54_SEL109(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)
97997 /*! @} */
97998 
97999 /*! @name SEL55 - Crossbar A Select Register 55 */
98000 /*! @{ */
98001 
98002 #define XBARA_SEL55_SEL110_MASK                  (0xFFU)
98003 #define XBARA_SEL55_SEL110_SHIFT                 (0U)
98004 #define XBARA_SEL55_SEL110(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)
98005 
98006 #define XBARA_SEL55_SEL111_MASK                  (0xFF00U)
98007 #define XBARA_SEL55_SEL111_SHIFT                 (8U)
98008 #define XBARA_SEL55_SEL111(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)
98009 /*! @} */
98010 
98011 /*! @name SEL56 - Crossbar A Select Register 56 */
98012 /*! @{ */
98013 
98014 #define XBARA_SEL56_SEL112_MASK                  (0xFFU)
98015 #define XBARA_SEL56_SEL112_SHIFT                 (0U)
98016 #define XBARA_SEL56_SEL112(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)
98017 
98018 #define XBARA_SEL56_SEL113_MASK                  (0xFF00U)
98019 #define XBARA_SEL56_SEL113_SHIFT                 (8U)
98020 #define XBARA_SEL56_SEL113(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)
98021 /*! @} */
98022 
98023 /*! @name SEL57 - Crossbar A Select Register 57 */
98024 /*! @{ */
98025 
98026 #define XBARA_SEL57_SEL114_MASK                  (0xFFU)
98027 #define XBARA_SEL57_SEL114_SHIFT                 (0U)
98028 #define XBARA_SEL57_SEL114(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)
98029 
98030 #define XBARA_SEL57_SEL115_MASK                  (0xFF00U)
98031 #define XBARA_SEL57_SEL115_SHIFT                 (8U)
98032 #define XBARA_SEL57_SEL115(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)
98033 /*! @} */
98034 
98035 /*! @name SEL58 - Crossbar A Select Register 58 */
98036 /*! @{ */
98037 
98038 #define XBARA_SEL58_SEL116_MASK                  (0xFFU)
98039 #define XBARA_SEL58_SEL116_SHIFT                 (0U)
98040 #define XBARA_SEL58_SEL116(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)
98041 
98042 #define XBARA_SEL58_SEL117_MASK                  (0xFF00U)
98043 #define XBARA_SEL58_SEL117_SHIFT                 (8U)
98044 #define XBARA_SEL58_SEL117(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)
98045 /*! @} */
98046 
98047 /*! @name SEL59 - Crossbar A Select Register 59 */
98048 /*! @{ */
98049 
98050 #define XBARA_SEL59_SEL118_MASK                  (0xFFU)
98051 #define XBARA_SEL59_SEL118_SHIFT                 (0U)
98052 #define XBARA_SEL59_SEL118(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)
98053 
98054 #define XBARA_SEL59_SEL119_MASK                  (0xFF00U)
98055 #define XBARA_SEL59_SEL119_SHIFT                 (8U)
98056 #define XBARA_SEL59_SEL119(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)
98057 /*! @} */
98058 
98059 /*! @name SEL60 - Crossbar A Select Register 60 */
98060 /*! @{ */
98061 
98062 #define XBARA_SEL60_SEL120_MASK                  (0xFFU)
98063 #define XBARA_SEL60_SEL120_SHIFT                 (0U)
98064 #define XBARA_SEL60_SEL120(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)
98065 
98066 #define XBARA_SEL60_SEL121_MASK                  (0xFF00U)
98067 #define XBARA_SEL60_SEL121_SHIFT                 (8U)
98068 #define XBARA_SEL60_SEL121(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)
98069 /*! @} */
98070 
98071 /*! @name SEL61 - Crossbar A Select Register 61 */
98072 /*! @{ */
98073 
98074 #define XBARA_SEL61_SEL122_MASK                  (0xFFU)
98075 #define XBARA_SEL61_SEL122_SHIFT                 (0U)
98076 #define XBARA_SEL61_SEL122(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)
98077 
98078 #define XBARA_SEL61_SEL123_MASK                  (0xFF00U)
98079 #define XBARA_SEL61_SEL123_SHIFT                 (8U)
98080 #define XBARA_SEL61_SEL123(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)
98081 /*! @} */
98082 
98083 /*! @name SEL62 - Crossbar A Select Register 62 */
98084 /*! @{ */
98085 
98086 #define XBARA_SEL62_SEL124_MASK                  (0xFFU)
98087 #define XBARA_SEL62_SEL124_SHIFT                 (0U)
98088 #define XBARA_SEL62_SEL124(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)
98089 
98090 #define XBARA_SEL62_SEL125_MASK                  (0xFF00U)
98091 #define XBARA_SEL62_SEL125_SHIFT                 (8U)
98092 #define XBARA_SEL62_SEL125(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)
98093 /*! @} */
98094 
98095 /*! @name SEL63 - Crossbar A Select Register 63 */
98096 /*! @{ */
98097 
98098 #define XBARA_SEL63_SEL126_MASK                  (0xFFU)
98099 #define XBARA_SEL63_SEL126_SHIFT                 (0U)
98100 #define XBARA_SEL63_SEL126(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)
98101 
98102 #define XBARA_SEL63_SEL127_MASK                  (0xFF00U)
98103 #define XBARA_SEL63_SEL127_SHIFT                 (8U)
98104 #define XBARA_SEL63_SEL127(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)
98105 /*! @} */
98106 
98107 /*! @name SEL64 - Crossbar A Select Register 64 */
98108 /*! @{ */
98109 
98110 #define XBARA_SEL64_SEL128_MASK                  (0xFFU)
98111 #define XBARA_SEL64_SEL128_SHIFT                 (0U)
98112 #define XBARA_SEL64_SEL128(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)
98113 
98114 #define XBARA_SEL64_SEL129_MASK                  (0xFF00U)
98115 #define XBARA_SEL64_SEL129_SHIFT                 (8U)
98116 #define XBARA_SEL64_SEL129(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)
98117 /*! @} */
98118 
98119 /*! @name SEL65 - Crossbar A Select Register 65 */
98120 /*! @{ */
98121 
98122 #define XBARA_SEL65_SEL130_MASK                  (0xFFU)
98123 #define XBARA_SEL65_SEL130_SHIFT                 (0U)
98124 #define XBARA_SEL65_SEL130(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)
98125 
98126 #define XBARA_SEL65_SEL131_MASK                  (0xFF00U)
98127 #define XBARA_SEL65_SEL131_SHIFT                 (8U)
98128 #define XBARA_SEL65_SEL131(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)
98129 /*! @} */
98130 
98131 /*! @name SEL66 - Crossbar A Select Register 66 */
98132 /*! @{ */
98133 
98134 #define XBARA_SEL66_SEL132_MASK                  (0xFFU)
98135 #define XBARA_SEL66_SEL132_SHIFT                 (0U)
98136 #define XBARA_SEL66_SEL132(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL132_SHIFT)) & XBARA_SEL66_SEL132_MASK)
98137 
98138 #define XBARA_SEL66_SEL133_MASK                  (0xFF00U)
98139 #define XBARA_SEL66_SEL133_SHIFT                 (8U)
98140 #define XBARA_SEL66_SEL133(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL133_SHIFT)) & XBARA_SEL66_SEL133_MASK)
98141 /*! @} */
98142 
98143 /*! @name SEL67 - Crossbar A Select Register 67 */
98144 /*! @{ */
98145 
98146 #define XBARA_SEL67_SEL134_MASK                  (0xFFU)
98147 #define XBARA_SEL67_SEL134_SHIFT                 (0U)
98148 #define XBARA_SEL67_SEL134(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL134_SHIFT)) & XBARA_SEL67_SEL134_MASK)
98149 
98150 #define XBARA_SEL67_SEL135_MASK                  (0xFF00U)
98151 #define XBARA_SEL67_SEL135_SHIFT                 (8U)
98152 #define XBARA_SEL67_SEL135(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL135_SHIFT)) & XBARA_SEL67_SEL135_MASK)
98153 /*! @} */
98154 
98155 /*! @name SEL68 - Crossbar A Select Register 68 */
98156 /*! @{ */
98157 
98158 #define XBARA_SEL68_SEL136_MASK                  (0xFFU)
98159 #define XBARA_SEL68_SEL136_SHIFT                 (0U)
98160 #define XBARA_SEL68_SEL136(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL136_SHIFT)) & XBARA_SEL68_SEL136_MASK)
98161 
98162 #define XBARA_SEL68_SEL137_MASK                  (0xFF00U)
98163 #define XBARA_SEL68_SEL137_SHIFT                 (8U)
98164 #define XBARA_SEL68_SEL137(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL137_SHIFT)) & XBARA_SEL68_SEL137_MASK)
98165 /*! @} */
98166 
98167 /*! @name SEL69 - Crossbar A Select Register 69 */
98168 /*! @{ */
98169 
98170 #define XBARA_SEL69_SEL138_MASK                  (0xFFU)
98171 #define XBARA_SEL69_SEL138_SHIFT                 (0U)
98172 #define XBARA_SEL69_SEL138(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL138_SHIFT)) & XBARA_SEL69_SEL138_MASK)
98173 
98174 #define XBARA_SEL69_SEL139_MASK                  (0xFF00U)
98175 #define XBARA_SEL69_SEL139_SHIFT                 (8U)
98176 #define XBARA_SEL69_SEL139(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL139_SHIFT)) & XBARA_SEL69_SEL139_MASK)
98177 /*! @} */
98178 
98179 /*! @name SEL70 - Crossbar A Select Register 70 */
98180 /*! @{ */
98181 
98182 #define XBARA_SEL70_SEL140_MASK                  (0xFFU)
98183 #define XBARA_SEL70_SEL140_SHIFT                 (0U)
98184 #define XBARA_SEL70_SEL140(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL140_SHIFT)) & XBARA_SEL70_SEL140_MASK)
98185 
98186 #define XBARA_SEL70_SEL141_MASK                  (0xFF00U)
98187 #define XBARA_SEL70_SEL141_SHIFT                 (8U)
98188 #define XBARA_SEL70_SEL141(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL141_SHIFT)) & XBARA_SEL70_SEL141_MASK)
98189 /*! @} */
98190 
98191 /*! @name SEL71 - Crossbar A Select Register 71 */
98192 /*! @{ */
98193 
98194 #define XBARA_SEL71_SEL142_MASK                  (0xFFU)
98195 #define XBARA_SEL71_SEL142_SHIFT                 (0U)
98196 #define XBARA_SEL71_SEL142(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL142_SHIFT)) & XBARA_SEL71_SEL142_MASK)
98197 
98198 #define XBARA_SEL71_SEL143_MASK                  (0xFF00U)
98199 #define XBARA_SEL71_SEL143_SHIFT                 (8U)
98200 #define XBARA_SEL71_SEL143(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL143_SHIFT)) & XBARA_SEL71_SEL143_MASK)
98201 /*! @} */
98202 
98203 /*! @name SEL72 - Crossbar A Select Register 72 */
98204 /*! @{ */
98205 
98206 #define XBARA_SEL72_SEL144_MASK                  (0xFFU)
98207 #define XBARA_SEL72_SEL144_SHIFT                 (0U)
98208 #define XBARA_SEL72_SEL144(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL144_SHIFT)) & XBARA_SEL72_SEL144_MASK)
98209 
98210 #define XBARA_SEL72_SEL145_MASK                  (0xFF00U)
98211 #define XBARA_SEL72_SEL145_SHIFT                 (8U)
98212 #define XBARA_SEL72_SEL145(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL145_SHIFT)) & XBARA_SEL72_SEL145_MASK)
98213 /*! @} */
98214 
98215 /*! @name SEL73 - Crossbar A Select Register 73 */
98216 /*! @{ */
98217 
98218 #define XBARA_SEL73_SEL146_MASK                  (0xFFU)
98219 #define XBARA_SEL73_SEL146_SHIFT                 (0U)
98220 #define XBARA_SEL73_SEL146(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL146_SHIFT)) & XBARA_SEL73_SEL146_MASK)
98221 
98222 #define XBARA_SEL73_SEL147_MASK                  (0xFF00U)
98223 #define XBARA_SEL73_SEL147_SHIFT                 (8U)
98224 #define XBARA_SEL73_SEL147(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL147_SHIFT)) & XBARA_SEL73_SEL147_MASK)
98225 /*! @} */
98226 
98227 /*! @name SEL74 - Crossbar A Select Register 74 */
98228 /*! @{ */
98229 
98230 #define XBARA_SEL74_SEL148_MASK                  (0xFFU)
98231 #define XBARA_SEL74_SEL148_SHIFT                 (0U)
98232 #define XBARA_SEL74_SEL148(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL148_SHIFT)) & XBARA_SEL74_SEL148_MASK)
98233 
98234 #define XBARA_SEL74_SEL149_MASK                  (0xFF00U)
98235 #define XBARA_SEL74_SEL149_SHIFT                 (8U)
98236 #define XBARA_SEL74_SEL149(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL149_SHIFT)) & XBARA_SEL74_SEL149_MASK)
98237 /*! @} */
98238 
98239 /*! @name SEL75 - Crossbar A Select Register 75 */
98240 /*! @{ */
98241 
98242 #define XBARA_SEL75_SEL150_MASK                  (0xFFU)
98243 #define XBARA_SEL75_SEL150_SHIFT                 (0U)
98244 #define XBARA_SEL75_SEL150(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL150_SHIFT)) & XBARA_SEL75_SEL150_MASK)
98245 
98246 #define XBARA_SEL75_SEL151_MASK                  (0xFF00U)
98247 #define XBARA_SEL75_SEL151_SHIFT                 (8U)
98248 #define XBARA_SEL75_SEL151(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL151_SHIFT)) & XBARA_SEL75_SEL151_MASK)
98249 /*! @} */
98250 
98251 /*! @name SEL76 - Crossbar A Select Register 76 */
98252 /*! @{ */
98253 
98254 #define XBARA_SEL76_SEL152_MASK                  (0xFFU)
98255 #define XBARA_SEL76_SEL152_SHIFT                 (0U)
98256 #define XBARA_SEL76_SEL152(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL152_SHIFT)) & XBARA_SEL76_SEL152_MASK)
98257 
98258 #define XBARA_SEL76_SEL153_MASK                  (0xFF00U)
98259 #define XBARA_SEL76_SEL153_SHIFT                 (8U)
98260 #define XBARA_SEL76_SEL153(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL153_SHIFT)) & XBARA_SEL76_SEL153_MASK)
98261 /*! @} */
98262 
98263 /*! @name SEL77 - Crossbar A Select Register 77 */
98264 /*! @{ */
98265 
98266 #define XBARA_SEL77_SEL154_MASK                  (0xFFU)
98267 #define XBARA_SEL77_SEL154_SHIFT                 (0U)
98268 #define XBARA_SEL77_SEL154(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL154_SHIFT)) & XBARA_SEL77_SEL154_MASK)
98269 
98270 #define XBARA_SEL77_SEL155_MASK                  (0xFF00U)
98271 #define XBARA_SEL77_SEL155_SHIFT                 (8U)
98272 #define XBARA_SEL77_SEL155(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL155_SHIFT)) & XBARA_SEL77_SEL155_MASK)
98273 /*! @} */
98274 
98275 /*! @name SEL78 - Crossbar A Select Register 78 */
98276 /*! @{ */
98277 
98278 #define XBARA_SEL78_SEL156_MASK                  (0xFFU)
98279 #define XBARA_SEL78_SEL156_SHIFT                 (0U)
98280 #define XBARA_SEL78_SEL156(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL156_SHIFT)) & XBARA_SEL78_SEL156_MASK)
98281 
98282 #define XBARA_SEL78_SEL157_MASK                  (0xFF00U)
98283 #define XBARA_SEL78_SEL157_SHIFT                 (8U)
98284 #define XBARA_SEL78_SEL157(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL157_SHIFT)) & XBARA_SEL78_SEL157_MASK)
98285 /*! @} */
98286 
98287 /*! @name SEL79 - Crossbar A Select Register 79 */
98288 /*! @{ */
98289 
98290 #define XBARA_SEL79_SEL158_MASK                  (0xFFU)
98291 #define XBARA_SEL79_SEL158_SHIFT                 (0U)
98292 #define XBARA_SEL79_SEL158(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL158_SHIFT)) & XBARA_SEL79_SEL158_MASK)
98293 
98294 #define XBARA_SEL79_SEL159_MASK                  (0xFF00U)
98295 #define XBARA_SEL79_SEL159_SHIFT                 (8U)
98296 #define XBARA_SEL79_SEL159(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL159_SHIFT)) & XBARA_SEL79_SEL159_MASK)
98297 /*! @} */
98298 
98299 /*! @name SEL80 - Crossbar A Select Register 80 */
98300 /*! @{ */
98301 
98302 #define XBARA_SEL80_SEL160_MASK                  (0xFFU)
98303 #define XBARA_SEL80_SEL160_SHIFT                 (0U)
98304 #define XBARA_SEL80_SEL160(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL160_SHIFT)) & XBARA_SEL80_SEL160_MASK)
98305 
98306 #define XBARA_SEL80_SEL161_MASK                  (0xFF00U)
98307 #define XBARA_SEL80_SEL161_SHIFT                 (8U)
98308 #define XBARA_SEL80_SEL161(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL161_SHIFT)) & XBARA_SEL80_SEL161_MASK)
98309 /*! @} */
98310 
98311 /*! @name SEL81 - Crossbar A Select Register 81 */
98312 /*! @{ */
98313 
98314 #define XBARA_SEL81_SEL162_MASK                  (0xFFU)
98315 #define XBARA_SEL81_SEL162_SHIFT                 (0U)
98316 #define XBARA_SEL81_SEL162(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL162_SHIFT)) & XBARA_SEL81_SEL162_MASK)
98317 
98318 #define XBARA_SEL81_SEL163_MASK                  (0xFF00U)
98319 #define XBARA_SEL81_SEL163_SHIFT                 (8U)
98320 #define XBARA_SEL81_SEL163(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL163_SHIFT)) & XBARA_SEL81_SEL163_MASK)
98321 /*! @} */
98322 
98323 /*! @name SEL82 - Crossbar A Select Register 82 */
98324 /*! @{ */
98325 
98326 #define XBARA_SEL82_SEL164_MASK                  (0xFFU)
98327 #define XBARA_SEL82_SEL164_SHIFT                 (0U)
98328 #define XBARA_SEL82_SEL164(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL164_SHIFT)) & XBARA_SEL82_SEL164_MASK)
98329 
98330 #define XBARA_SEL82_SEL165_MASK                  (0xFF00U)
98331 #define XBARA_SEL82_SEL165_SHIFT                 (8U)
98332 #define XBARA_SEL82_SEL165(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL165_SHIFT)) & XBARA_SEL82_SEL165_MASK)
98333 /*! @} */
98334 
98335 /*! @name SEL83 - Crossbar A Select Register 83 */
98336 /*! @{ */
98337 
98338 #define XBARA_SEL83_SEL166_MASK                  (0xFFU)
98339 #define XBARA_SEL83_SEL166_SHIFT                 (0U)
98340 #define XBARA_SEL83_SEL166(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL166_SHIFT)) & XBARA_SEL83_SEL166_MASK)
98341 
98342 #define XBARA_SEL83_SEL167_MASK                  (0xFF00U)
98343 #define XBARA_SEL83_SEL167_SHIFT                 (8U)
98344 #define XBARA_SEL83_SEL167(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL167_SHIFT)) & XBARA_SEL83_SEL167_MASK)
98345 /*! @} */
98346 
98347 /*! @name SEL84 - Crossbar A Select Register 84 */
98348 /*! @{ */
98349 
98350 #define XBARA_SEL84_SEL168_MASK                  (0xFFU)
98351 #define XBARA_SEL84_SEL168_SHIFT                 (0U)
98352 #define XBARA_SEL84_SEL168(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL168_SHIFT)) & XBARA_SEL84_SEL168_MASK)
98353 
98354 #define XBARA_SEL84_SEL169_MASK                  (0xFF00U)
98355 #define XBARA_SEL84_SEL169_SHIFT                 (8U)
98356 #define XBARA_SEL84_SEL169(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL169_SHIFT)) & XBARA_SEL84_SEL169_MASK)
98357 /*! @} */
98358 
98359 /*! @name SEL85 - Crossbar A Select Register 85 */
98360 /*! @{ */
98361 
98362 #define XBARA_SEL85_SEL170_MASK                  (0xFFU)
98363 #define XBARA_SEL85_SEL170_SHIFT                 (0U)
98364 #define XBARA_SEL85_SEL170(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL170_SHIFT)) & XBARA_SEL85_SEL170_MASK)
98365 
98366 #define XBARA_SEL85_SEL171_MASK                  (0xFF00U)
98367 #define XBARA_SEL85_SEL171_SHIFT                 (8U)
98368 #define XBARA_SEL85_SEL171(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL171_SHIFT)) & XBARA_SEL85_SEL171_MASK)
98369 /*! @} */
98370 
98371 /*! @name SEL86 - Crossbar A Select Register 86 */
98372 /*! @{ */
98373 
98374 #define XBARA_SEL86_SEL172_MASK                  (0xFFU)
98375 #define XBARA_SEL86_SEL172_SHIFT                 (0U)
98376 #define XBARA_SEL86_SEL172(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL172_SHIFT)) & XBARA_SEL86_SEL172_MASK)
98377 
98378 #define XBARA_SEL86_SEL173_MASK                  (0xFF00U)
98379 #define XBARA_SEL86_SEL173_SHIFT                 (8U)
98380 #define XBARA_SEL86_SEL173(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL173_SHIFT)) & XBARA_SEL86_SEL173_MASK)
98381 /*! @} */
98382 
98383 /*! @name SEL87 - Crossbar A Select Register 87 */
98384 /*! @{ */
98385 
98386 #define XBARA_SEL87_SEL174_MASK                  (0xFFU)
98387 #define XBARA_SEL87_SEL174_SHIFT                 (0U)
98388 #define XBARA_SEL87_SEL174(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL174_SHIFT)) & XBARA_SEL87_SEL174_MASK)
98389 
98390 #define XBARA_SEL87_SEL175_MASK                  (0xFF00U)
98391 #define XBARA_SEL87_SEL175_SHIFT                 (8U)
98392 #define XBARA_SEL87_SEL175(x)                    (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL175_SHIFT)) & XBARA_SEL87_SEL175_MASK)
98393 /*! @} */
98394 
98395 /*! @name CTRL0 - Crossbar A Control Register 0 */
98396 /*! @{ */
98397 
98398 #define XBARA_CTRL0_DEN0_MASK                    (0x1U)
98399 #define XBARA_CTRL0_DEN0_SHIFT                   (0U)
98400 /*! DEN0 - DMA Enable for XBAR_OUT0
98401  *  0b0..DMA disabled
98402  *  0b1..DMA enabled
98403  */
98404 #define XBARA_CTRL0_DEN0(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
98405 
98406 #define XBARA_CTRL0_IEN0_MASK                    (0x2U)
98407 #define XBARA_CTRL0_IEN0_SHIFT                   (1U)
98408 /*! IEN0 - Interrupt Enable for XBAR_OUT0
98409  *  0b0..Interrupt disabled
98410  *  0b1..Interrupt enabled
98411  */
98412 #define XBARA_CTRL0_IEN0(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
98413 
98414 #define XBARA_CTRL0_EDGE0_MASK                   (0xCU)
98415 #define XBARA_CTRL0_EDGE0_SHIFT                  (2U)
98416 /*! EDGE0 - Active edge for edge detection on XBAR_OUT0
98417  *  0b00..STS0 never asserts
98418  *  0b01..STS0 asserts on rising edges of XBAR_OUT0
98419  *  0b10..STS0 asserts on falling edges of XBAR_OUT0
98420  *  0b11..STS0 asserts on rising and falling edges of XBAR_OUT0
98421  */
98422 #define XBARA_CTRL0_EDGE0(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
98423 
98424 #define XBARA_CTRL0_STS0_MASK                    (0x10U)
98425 #define XBARA_CTRL0_STS0_SHIFT                   (4U)
98426 /*! STS0 - Edge detection status for XBAR_OUT0
98427  *  0b0..Active edge not yet detected on XBAR_OUT0
98428  *  0b1..Active edge detected on XBAR_OUT0
98429  */
98430 #define XBARA_CTRL0_STS0(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
98431 
98432 #define XBARA_CTRL0_DEN1_MASK                    (0x100U)
98433 #define XBARA_CTRL0_DEN1_SHIFT                   (8U)
98434 /*! DEN1 - DMA Enable for XBAR_OUT1
98435  *  0b0..DMA disabled
98436  *  0b1..DMA enabled
98437  */
98438 #define XBARA_CTRL0_DEN1(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
98439 
98440 #define XBARA_CTRL0_IEN1_MASK                    (0x200U)
98441 #define XBARA_CTRL0_IEN1_SHIFT                   (9U)
98442 /*! IEN1 - Interrupt Enable for XBAR_OUT1
98443  *  0b0..Interrupt disabled
98444  *  0b1..Interrupt enabled
98445  */
98446 #define XBARA_CTRL0_IEN1(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
98447 
98448 #define XBARA_CTRL0_EDGE1_MASK                   (0xC00U)
98449 #define XBARA_CTRL0_EDGE1_SHIFT                  (10U)
98450 /*! EDGE1 - Active edge for edge detection on XBAR_OUT1
98451  *  0b00..STS1 never asserts
98452  *  0b01..STS1 asserts on rising edges of XBAR_OUT1
98453  *  0b10..STS1 asserts on falling edges of XBAR_OUT1
98454  *  0b11..STS1 asserts on rising and falling edges of XBAR_OUT1
98455  */
98456 #define XBARA_CTRL0_EDGE1(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
98457 
98458 #define XBARA_CTRL0_STS1_MASK                    (0x1000U)
98459 #define XBARA_CTRL0_STS1_SHIFT                   (12U)
98460 /*! STS1 - Edge detection status for XBAR_OUT1
98461  *  0b0..Active edge not yet detected on XBAR_OUT1
98462  *  0b1..Active edge detected on XBAR_OUT1
98463  */
98464 #define XBARA_CTRL0_STS1(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
98465 /*! @} */
98466 
98467 /*! @name CTRL1 - Crossbar A Control Register 1 */
98468 /*! @{ */
98469 
98470 #define XBARA_CTRL1_DEN2_MASK                    (0x1U)
98471 #define XBARA_CTRL1_DEN2_SHIFT                   (0U)
98472 /*! DEN2 - DMA Enable for XBAR_OUT2
98473  *  0b0..DMA disabled
98474  *  0b1..DMA enabled
98475  */
98476 #define XBARA_CTRL1_DEN2(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
98477 
98478 #define XBARA_CTRL1_IEN2_MASK                    (0x2U)
98479 #define XBARA_CTRL1_IEN2_SHIFT                   (1U)
98480 /*! IEN2 - Interrupt Enable for XBAR_OUT2
98481  *  0b0..Interrupt disabled
98482  *  0b1..Interrupt enabled
98483  */
98484 #define XBARA_CTRL1_IEN2(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
98485 
98486 #define XBARA_CTRL1_EDGE2_MASK                   (0xCU)
98487 #define XBARA_CTRL1_EDGE2_SHIFT                  (2U)
98488 /*! EDGE2 - Active edge for edge detection on XBAR_OUT2
98489  *  0b00..STS2 never asserts
98490  *  0b01..STS2 asserts on rising edges of XBAR_OUT2
98491  *  0b10..STS2 asserts on falling edges of XBAR_OUT2
98492  *  0b11..STS2 asserts on rising and falling edges of XBAR_OUT2
98493  */
98494 #define XBARA_CTRL1_EDGE2(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
98495 
98496 #define XBARA_CTRL1_STS2_MASK                    (0x10U)
98497 #define XBARA_CTRL1_STS2_SHIFT                   (4U)
98498 /*! STS2 - Edge detection status for XBAR_OUT2
98499  *  0b0..Active edge not yet detected on XBAR_OUT2
98500  *  0b1..Active edge detected on XBAR_OUT2
98501  */
98502 #define XBARA_CTRL1_STS2(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
98503 
98504 #define XBARA_CTRL1_DEN3_MASK                    (0x100U)
98505 #define XBARA_CTRL1_DEN3_SHIFT                   (8U)
98506 /*! DEN3 - DMA Enable for XBAR_OUT3
98507  *  0b0..DMA disabled
98508  *  0b1..DMA enabled
98509  */
98510 #define XBARA_CTRL1_DEN3(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
98511 
98512 #define XBARA_CTRL1_IEN3_MASK                    (0x200U)
98513 #define XBARA_CTRL1_IEN3_SHIFT                   (9U)
98514 /*! IEN3 - Interrupt Enable for XBAR_OUT3
98515  *  0b0..Interrupt disabled
98516  *  0b1..Interrupt enabled
98517  */
98518 #define XBARA_CTRL1_IEN3(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
98519 
98520 #define XBARA_CTRL1_EDGE3_MASK                   (0xC00U)
98521 #define XBARA_CTRL1_EDGE3_SHIFT                  (10U)
98522 /*! EDGE3 - Active edge for edge detection on XBAR_OUT3
98523  *  0b00..STS3 never asserts
98524  *  0b01..STS3 asserts on rising edges of XBAR_OUT3
98525  *  0b10..STS3 asserts on falling edges of XBAR_OUT3
98526  *  0b11..STS3 asserts on rising and falling edges of XBAR_OUT3
98527  */
98528 #define XBARA_CTRL1_EDGE3(x)                     (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
98529 
98530 #define XBARA_CTRL1_STS3_MASK                    (0x1000U)
98531 #define XBARA_CTRL1_STS3_SHIFT                   (12U)
98532 /*! STS3 - Edge detection status for XBAR_OUT3
98533  *  0b0..Active edge not yet detected on XBAR_OUT3
98534  *  0b1..Active edge detected on XBAR_OUT3
98535  */
98536 #define XBARA_CTRL1_STS3(x)                      (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)
98537 /*! @} */
98538 
98539 
98540 /*!
98541  * @}
98542  */ /* end of group XBARA_Register_Masks */
98543 
98544 
98545 /* XBARA - Peripheral instance base addresses */
98546 /** Peripheral XBARA1 base address */
98547 #define XBARA1_BASE                              (0x4003C000u)
98548 /** Peripheral XBARA1 base pointer */
98549 #define XBARA1                                   ((XBARA_Type *)XBARA1_BASE)
98550 /** Array initializer of XBARA peripheral base addresses */
98551 #define XBARA_BASE_ADDRS                         { 0u, XBARA1_BASE }
98552 /** Array initializer of XBARA peripheral base pointers */
98553 #define XBARA_BASE_PTRS                          { (XBARA_Type *)0u, XBARA1 }
98554 
98555 /*!
98556  * @}
98557  */ /* end of group XBARA_Peripheral_Access_Layer */
98558 
98559 
98560 /* ----------------------------------------------------------------------------
98561    -- XBARB Peripheral Access Layer
98562    ---------------------------------------------------------------------------- */
98563 
98564 /*!
98565  * @addtogroup XBARB_Peripheral_Access_Layer XBARB Peripheral Access Layer
98566  * @{
98567  */
98568 
98569 /** XBARB - Register Layout Typedef */
98570 typedef struct {
98571   __IO uint16_t SEL0;                              /**< Crossbar B Select Register 0, offset: 0x0 */
98572   __IO uint16_t SEL1;                              /**< Crossbar B Select Register 1, offset: 0x2 */
98573   __IO uint16_t SEL2;                              /**< Crossbar B Select Register 2, offset: 0x4 */
98574   __IO uint16_t SEL3;                              /**< Crossbar B Select Register 3, offset: 0x6 */
98575   __IO uint16_t SEL4;                              /**< Crossbar B Select Register 4, offset: 0x8 */
98576   __IO uint16_t SEL5;                              /**< Crossbar B Select Register 5, offset: 0xA */
98577   __IO uint16_t SEL6;                              /**< Crossbar B Select Register 6, offset: 0xC */
98578   __IO uint16_t SEL7;                              /**< Crossbar B Select Register 7, offset: 0xE */
98579 } XBARB_Type;
98580 
98581 /* ----------------------------------------------------------------------------
98582    -- XBARB Register Masks
98583    ---------------------------------------------------------------------------- */
98584 
98585 /*!
98586  * @addtogroup XBARB_Register_Masks XBARB Register Masks
98587  * @{
98588  */
98589 
98590 /*! @name SEL0 - Crossbar B Select Register 0 */
98591 /*! @{ */
98592 
98593 #define XBARB_SEL0_SEL0_MASK                     (0x7FU)
98594 #define XBARB_SEL0_SEL0_SHIFT                    (0U)
98595 #define XBARB_SEL0_SEL0(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)
98596 
98597 #define XBARB_SEL0_SEL1_MASK                     (0x7F00U)
98598 #define XBARB_SEL0_SEL1_SHIFT                    (8U)
98599 #define XBARB_SEL0_SEL1(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)
98600 /*! @} */
98601 
98602 /*! @name SEL1 - Crossbar B Select Register 1 */
98603 /*! @{ */
98604 
98605 #define XBARB_SEL1_SEL2_MASK                     (0x7FU)
98606 #define XBARB_SEL1_SEL2_SHIFT                    (0U)
98607 #define XBARB_SEL1_SEL2(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)
98608 
98609 #define XBARB_SEL1_SEL3_MASK                     (0x7F00U)
98610 #define XBARB_SEL1_SEL3_SHIFT                    (8U)
98611 #define XBARB_SEL1_SEL3(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)
98612 /*! @} */
98613 
98614 /*! @name SEL2 - Crossbar B Select Register 2 */
98615 /*! @{ */
98616 
98617 #define XBARB_SEL2_SEL4_MASK                     (0x7FU)
98618 #define XBARB_SEL2_SEL4_SHIFT                    (0U)
98619 #define XBARB_SEL2_SEL4(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)
98620 
98621 #define XBARB_SEL2_SEL5_MASK                     (0x7F00U)
98622 #define XBARB_SEL2_SEL5_SHIFT                    (8U)
98623 #define XBARB_SEL2_SEL5(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)
98624 /*! @} */
98625 
98626 /*! @name SEL3 - Crossbar B Select Register 3 */
98627 /*! @{ */
98628 
98629 #define XBARB_SEL3_SEL6_MASK                     (0x7FU)
98630 #define XBARB_SEL3_SEL6_SHIFT                    (0U)
98631 #define XBARB_SEL3_SEL6(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)
98632 
98633 #define XBARB_SEL3_SEL7_MASK                     (0x7F00U)
98634 #define XBARB_SEL3_SEL7_SHIFT                    (8U)
98635 #define XBARB_SEL3_SEL7(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)
98636 /*! @} */
98637 
98638 /*! @name SEL4 - Crossbar B Select Register 4 */
98639 /*! @{ */
98640 
98641 #define XBARB_SEL4_SEL8_MASK                     (0x7FU)
98642 #define XBARB_SEL4_SEL8_SHIFT                    (0U)
98643 #define XBARB_SEL4_SEL8(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)
98644 
98645 #define XBARB_SEL4_SEL9_MASK                     (0x7F00U)
98646 #define XBARB_SEL4_SEL9_SHIFT                    (8U)
98647 #define XBARB_SEL4_SEL9(x)                       (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)
98648 /*! @} */
98649 
98650 /*! @name SEL5 - Crossbar B Select Register 5 */
98651 /*! @{ */
98652 
98653 #define XBARB_SEL5_SEL10_MASK                    (0x7FU)
98654 #define XBARB_SEL5_SEL10_SHIFT                   (0U)
98655 #define XBARB_SEL5_SEL10(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)
98656 
98657 #define XBARB_SEL5_SEL11_MASK                    (0x7F00U)
98658 #define XBARB_SEL5_SEL11_SHIFT                   (8U)
98659 #define XBARB_SEL5_SEL11(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)
98660 /*! @} */
98661 
98662 /*! @name SEL6 - Crossbar B Select Register 6 */
98663 /*! @{ */
98664 
98665 #define XBARB_SEL6_SEL12_MASK                    (0x7FU)
98666 #define XBARB_SEL6_SEL12_SHIFT                   (0U)
98667 #define XBARB_SEL6_SEL12(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)
98668 
98669 #define XBARB_SEL6_SEL13_MASK                    (0x7F00U)
98670 #define XBARB_SEL6_SEL13_SHIFT                   (8U)
98671 #define XBARB_SEL6_SEL13(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)
98672 /*! @} */
98673 
98674 /*! @name SEL7 - Crossbar B Select Register 7 */
98675 /*! @{ */
98676 
98677 #define XBARB_SEL7_SEL14_MASK                    (0x7FU)
98678 #define XBARB_SEL7_SEL14_SHIFT                   (0U)
98679 #define XBARB_SEL7_SEL14(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)
98680 
98681 #define XBARB_SEL7_SEL15_MASK                    (0x7F00U)
98682 #define XBARB_SEL7_SEL15_SHIFT                   (8U)
98683 #define XBARB_SEL7_SEL15(x)                      (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)
98684 /*! @} */
98685 
98686 
98687 /*!
98688  * @}
98689  */ /* end of group XBARB_Register_Masks */
98690 
98691 
98692 /* XBARB - Peripheral instance base addresses */
98693 /** Peripheral XBARB2 base address */
98694 #define XBARB2_BASE                              (0x40040000u)
98695 /** Peripheral XBARB2 base pointer */
98696 #define XBARB2                                   ((XBARB_Type *)XBARB2_BASE)
98697 /** Peripheral XBARB3 base address */
98698 #define XBARB3_BASE                              (0x40044000u)
98699 /** Peripheral XBARB3 base pointer */
98700 #define XBARB3                                   ((XBARB_Type *)XBARB3_BASE)
98701 /** Array initializer of XBARB peripheral base addresses */
98702 #define XBARB_BASE_ADDRS                         { 0u, 0u, XBARB2_BASE, XBARB3_BASE }
98703 /** Array initializer of XBARB peripheral base pointers */
98704 #define XBARB_BASE_PTRS                          { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }
98705 
98706 /*!
98707  * @}
98708  */ /* end of group XBARB_Peripheral_Access_Layer */
98709 
98710 
98711 /* ----------------------------------------------------------------------------
98712    -- XECC Peripheral Access Layer
98713    ---------------------------------------------------------------------------- */
98714 
98715 /*!
98716  * @addtogroup XECC_Peripheral_Access_Layer XECC Peripheral Access Layer
98717  * @{
98718  */
98719 
98720 /** XECC - Register Layout Typedef */
98721 typedef struct {
98722   __IO uint32_t ECC_CTRL;                          /**< ECC Control Register, offset: 0x0 */
98723   __IO uint32_t ERR_STATUS;                        /**< Error Interrupt Status Register, offset: 0x4 */
98724   __IO uint32_t ERR_STAT_EN;                       /**< Error Interrupt Status Enable Register, offset: 0x8 */
98725   __IO uint32_t ERR_SIG_EN;                        /**< Error Interrupt Enable Register, offset: 0xC */
98726   __IO uint32_t ERR_DATA_INJ;                      /**< Error Injection On Write Data, offset: 0x10 */
98727   __IO uint32_t ERR_ECC_INJ;                       /**< Error Injection On ECC Code of Write Data, offset: 0x14 */
98728   __I  uint32_t SINGLE_ERR_ADDR;                   /**< Single Error Address, offset: 0x18 */
98729   __I  uint32_t SINGLE_ERR_DATA;                   /**< Single Error Read Data, offset: 0x1C */
98730   __I  uint32_t SINGLE_ERR_ECC;                    /**< Single Error ECC Code, offset: 0x20 */
98731   __I  uint32_t SINGLE_ERR_POS;                    /**< Single Error Bit Position, offset: 0x24 */
98732   __I  uint32_t SINGLE_ERR_BIT_FIELD;              /**< Single Error Bit Field, offset: 0x28 */
98733   __I  uint32_t MULTI_ERR_ADDR;                    /**< Multiple Error Address, offset: 0x2C */
98734   __I  uint32_t MULTI_ERR_DATA;                    /**< Multiple Error Read Data, offset: 0x30 */
98735   __I  uint32_t MULTI_ERR_ECC;                     /**< Multiple Error ECC code, offset: 0x34 */
98736   __I  uint32_t MULTI_ERR_BIT_FIELD;               /**< Multiple Error Bit Field, offset: 0x38 */
98737   __IO uint32_t ECC_BASE_ADDR0;                    /**< ECC Region 0 Base Address, offset: 0x3C */
98738   __IO uint32_t ECC_END_ADDR0;                     /**< ECC Region 0 End Address, offset: 0x40 */
98739   __IO uint32_t ECC_BASE_ADDR1;                    /**< ECC Region 1 Base Address, offset: 0x44 */
98740   __IO uint32_t ECC_END_ADDR1;                     /**< ECC Region 1 End Address, offset: 0x48 */
98741   __IO uint32_t ECC_BASE_ADDR2;                    /**< ECC Region 2 Base Address, offset: 0x4C */
98742   __IO uint32_t ECC_END_ADDR2;                     /**< ECC Region 2 End Address, offset: 0x50 */
98743   __IO uint32_t ECC_BASE_ADDR3;                    /**< ECC Region 3 Base Address, offset: 0x54 */
98744   __IO uint32_t ECC_END_ADDR3;                     /**< ECC Region 3 End Address, offset: 0x58 */
98745 } XECC_Type;
98746 
98747 /* ----------------------------------------------------------------------------
98748    -- XECC Register Masks
98749    ---------------------------------------------------------------------------- */
98750 
98751 /*!
98752  * @addtogroup XECC_Register_Masks XECC Register Masks
98753  * @{
98754  */
98755 
98756 /*! @name ECC_CTRL - ECC Control Register */
98757 /*! @{ */
98758 
98759 #define XECC_ECC_CTRL_ECC_EN_MASK                (0x1U)
98760 #define XECC_ECC_CTRL_ECC_EN_SHIFT               (0U)
98761 /*! ECC_EN - ECC Function Enable
98762  *  0b0..Disable
98763  *  0b1..Enable
98764  */
98765 #define XECC_ECC_CTRL_ECC_EN(x)                  (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_ECC_EN_SHIFT)) & XECC_ECC_CTRL_ECC_EN_MASK)
98766 
98767 #define XECC_ECC_CTRL_WECC_EN_MASK               (0x2U)
98768 #define XECC_ECC_CTRL_WECC_EN_SHIFT              (1U)
98769 /*! WECC_EN - Write ECC Encode Function Enable
98770  *  0b0..Disable
98771  *  0b1..Enable
98772  */
98773 #define XECC_ECC_CTRL_WECC_EN(x)                 (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_WECC_EN_SHIFT)) & XECC_ECC_CTRL_WECC_EN_MASK)
98774 
98775 #define XECC_ECC_CTRL_RECC_EN_MASK               (0x4U)
98776 #define XECC_ECC_CTRL_RECC_EN_SHIFT              (2U)
98777 /*! RECC_EN - Read ECC Function Enable
98778  *  0b0..Disable
98779  *  0b1..Enable
98780  */
98781 #define XECC_ECC_CTRL_RECC_EN(x)                 (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_RECC_EN_SHIFT)) & XECC_ECC_CTRL_RECC_EN_MASK)
98782 
98783 #define XECC_ECC_CTRL_SWAP_EN_MASK               (0x8U)
98784 #define XECC_ECC_CTRL_SWAP_EN_SHIFT              (3U)
98785 /*! SWAP_EN - Swap Data Enable
98786  *  0b0..Disable
98787  *  0b1..Enable
98788  */
98789 #define XECC_ECC_CTRL_SWAP_EN(x)                 (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_SWAP_EN_SHIFT)) & XECC_ECC_CTRL_SWAP_EN_MASK)
98790 /*! @} */
98791 
98792 /*! @name ERR_STATUS - Error Interrupt Status Register */
98793 /*! @{ */
98794 
98795 #define XECC_ERR_STATUS_SINGLE_ERR_MASK          (0x1U)
98796 #define XECC_ERR_STATUS_SINGLE_ERR_SHIFT         (0U)
98797 /*! SINGLE_ERR - Single Bit Error
98798  *  0b0..Single bit error does not happen.
98799  *  0b1..Single bit error happens.
98800  */
98801 #define XECC_ERR_STATUS_SINGLE_ERR(x)            (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_SINGLE_ERR_SHIFT)) & XECC_ERR_STATUS_SINGLE_ERR_MASK)
98802 
98803 #define XECC_ERR_STATUS_MULTI_ERR_MASK           (0x2U)
98804 #define XECC_ERR_STATUS_MULTI_ERR_SHIFT          (1U)
98805 /*! MULTI_ERR - Multiple Bits Error
98806  *  0b0..Multiple bits error does not happen.
98807  *  0b1..Multiple bits error happens.
98808  */
98809 #define XECC_ERR_STATUS_MULTI_ERR(x)             (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_MULTI_ERR_SHIFT)) & XECC_ERR_STATUS_MULTI_ERR_MASK)
98810 
98811 #define XECC_ERR_STATUS_Reserved1_MASK           (0xFFFFFFFCU)
98812 #define XECC_ERR_STATUS_Reserved1_SHIFT          (2U)
98813 /*! Reserved1 - Reserved */
98814 #define XECC_ERR_STATUS_Reserved1(x)             (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_Reserved1_SHIFT)) & XECC_ERR_STATUS_Reserved1_MASK)
98815 /*! @} */
98816 
98817 /*! @name ERR_STAT_EN - Error Interrupt Status Enable Register */
98818 /*! @{ */
98819 
98820 #define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK (0x1U)
98821 #define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT (0U)
98822 /*! SINGLE_ERR_STAT_EN - Single Bit Error Status Enable
98823  *  0b0..Masked
98824  *  0b1..Enabled
98825  */
98826 #define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN(x)   (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK)
98827 
98828 #define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK  (0x2U)
98829 #define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT (1U)
98830 /*! MULIT_ERR_STAT_EN - Multiple Bits Error Status Enable
98831  *  0b0..Masked
98832  *  0b1..Enabled
98833  */
98834 #define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN(x)    (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK)
98835 
98836 #define XECC_ERR_STAT_EN_Reserved1_MASK          (0xFFFFFFFCU)
98837 #define XECC_ERR_STAT_EN_Reserved1_SHIFT         (2U)
98838 /*! Reserved1 - Reserved */
98839 #define XECC_ERR_STAT_EN_Reserved1(x)            (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_Reserved1_SHIFT)) & XECC_ERR_STAT_EN_Reserved1_MASK)
98840 /*! @} */
98841 
98842 /*! @name ERR_SIG_EN - Error Interrupt Enable Register */
98843 /*! @{ */
98844 
98845 #define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK   (0x1U)
98846 #define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT  (0U)
98847 /*! SINGLE_ERR_SIG_EN - Single Bit Error Interrupt Enable
98848  *  0b0..Masked
98849  *  0b1..Enabled
98850  */
98851 #define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN(x)     (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK)
98852 
98853 #define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK    (0x2U)
98854 #define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT   (1U)
98855 /*! MULTI_ERR_SIG_EN - Multiple Bits Error Interrupt Enable
98856  *  0b0..Masked
98857  *  0b1..Enabled
98858  */
98859 #define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN(x)      (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK)
98860 
98861 #define XECC_ERR_SIG_EN_Reserved1_MASK           (0xFFFFFFFCU)
98862 #define XECC_ERR_SIG_EN_Reserved1_SHIFT          (2U)
98863 /*! Reserved1 - Reserved */
98864 #define XECC_ERR_SIG_EN_Reserved1(x)             (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_Reserved1_SHIFT)) & XECC_ERR_SIG_EN_Reserved1_MASK)
98865 /*! @} */
98866 
98867 /*! @name ERR_DATA_INJ - Error Injection On Write Data */
98868 /*! @{ */
98869 
98870 #define XECC_ERR_DATA_INJ_ERR_DATA_INJ_MASK      (0xFFFFFFFFU)
98871 #define XECC_ERR_DATA_INJ_ERR_DATA_INJ_SHIFT     (0U)
98872 /*! ERR_DATA_INJ - Error Injection On Write Data */
98873 #define XECC_ERR_DATA_INJ_ERR_DATA_INJ(x)        (((uint32_t)(((uint32_t)(x)) << XECC_ERR_DATA_INJ_ERR_DATA_INJ_SHIFT)) & XECC_ERR_DATA_INJ_ERR_DATA_INJ_MASK)
98874 /*! @} */
98875 
98876 /*! @name ERR_ECC_INJ - Error Injection On ECC Code of Write Data */
98877 /*! @{ */
98878 
98879 #define XECC_ERR_ECC_INJ_ERR_ECC_INJ_MASK        (0xFFFFFFFFU)
98880 #define XECC_ERR_ECC_INJ_ERR_ECC_INJ_SHIFT       (0U)
98881 /*! ERR_ECC_INJ - Error Injection On ECC Code of Write Data */
98882 #define XECC_ERR_ECC_INJ_ERR_ECC_INJ(x)          (((uint32_t)(((uint32_t)(x)) << XECC_ERR_ECC_INJ_ERR_ECC_INJ_SHIFT)) & XECC_ERR_ECC_INJ_ERR_ECC_INJ_MASK)
98883 /*! @} */
98884 
98885 /*! @name SINGLE_ERR_ADDR - Single Error Address */
98886 /*! @{ */
98887 
98888 #define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_MASK (0xFFFFFFFFU)
98889 #define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_SHIFT (0U)
98890 /*! SINGLE_ERR_ADDR - Single Error Address */
98891 #define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR(x)  (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_SHIFT)) & XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_MASK)
98892 /*! @} */
98893 
98894 /*! @name SINGLE_ERR_DATA - Single Error Read Data */
98895 /*! @{ */
98896 
98897 #define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
98898 #define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_SHIFT (0U)
98899 /*! SINGLE_ERR_DATA - Single Error Read Data */
98900 #define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA(x)  (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_SHIFT)) & XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_MASK)
98901 /*! @} */
98902 
98903 /*! @name SINGLE_ERR_ECC - Single Error ECC Code */
98904 /*! @{ */
98905 
98906 #define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_MASK  (0xFFFFFFFFU)
98907 #define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_SHIFT (0U)
98908 /*! SINGLE_ERR_ECC - Single Error ECC code */
98909 #define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC(x)    (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_SHIFT)) & XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_MASK)
98910 /*! @} */
98911 
98912 /*! @name SINGLE_ERR_POS - Single Error Bit Position */
98913 /*! @{ */
98914 
98915 #define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_MASK  (0xFFFFFFFFU)
98916 #define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_SHIFT (0U)
98917 /*! SINGLE_ERR_POS - Single Error bit Position */
98918 #define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS(x)    (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_SHIFT)) & XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_MASK)
98919 /*! @} */
98920 
98921 /*! @name SINGLE_ERR_BIT_FIELD - Single Error Bit Field */
98922 /*! @{ */
98923 
98924 #define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_MASK (0xFFU)
98925 #define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_SHIFT (0U)
98926 /*! SINGLE_ERR_BIT_FIELD - Single Error Bit Field */
98927 #define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_SHIFT)) & XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_MASK)
98928 
98929 #define XECC_SINGLE_ERR_BIT_FIELD_Reserved1_MASK (0xFFFFFF00U)
98930 #define XECC_SINGLE_ERR_BIT_FIELD_Reserved1_SHIFT (8U)
98931 /*! Reserved1 - Reserved */
98932 #define XECC_SINGLE_ERR_BIT_FIELD_Reserved1(x)   (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_BIT_FIELD_Reserved1_SHIFT)) & XECC_SINGLE_ERR_BIT_FIELD_Reserved1_MASK)
98933 /*! @} */
98934 
98935 /*! @name MULTI_ERR_ADDR - Multiple Error Address */
98936 /*! @{ */
98937 
98938 #define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_MASK  (0xFFFFFFFFU)
98939 #define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_SHIFT (0U)
98940 /*! MULTI_ERR_ADDR - Multiple Error Address */
98941 #define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR(x)    (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_SHIFT)) & XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_MASK)
98942 /*! @} */
98943 
98944 /*! @name MULTI_ERR_DATA - Multiple Error Read Data */
98945 /*! @{ */
98946 
98947 #define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_MASK  (0xFFFFFFFFU)
98948 #define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_SHIFT (0U)
98949 /*! MULTI_ERR_DATA - Multiple Error Read Data */
98950 #define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA(x)    (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_SHIFT)) & XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_MASK)
98951 /*! @} */
98952 
98953 /*! @name MULTI_ERR_ECC - Multiple Error ECC code */
98954 /*! @{ */
98955 
98956 #define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_MASK    (0xFFFFFFFFU)
98957 #define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_SHIFT   (0U)
98958 /*! MULTI_ERR_ECC - Multiple Error ECC code */
98959 #define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC(x)      (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_SHIFT)) & XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_MASK)
98960 /*! @} */
98961 
98962 /*! @name MULTI_ERR_BIT_FIELD - Multiple Error Bit Field */
98963 /*! @{ */
98964 
98965 #define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_MASK (0xFFU)
98966 #define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_SHIFT (0U)
98967 /*! MULTI_ERR_BIT_FIELD - Multiple Error Bit Field */
98968 #define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_SHIFT)) & XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_MASK)
98969 
98970 #define XECC_MULTI_ERR_BIT_FIELD_Reserved1_MASK  (0xFFFFFF00U)
98971 #define XECC_MULTI_ERR_BIT_FIELD_Reserved1_SHIFT (8U)
98972 /*! Reserved1 - Reserved */
98973 #define XECC_MULTI_ERR_BIT_FIELD_Reserved1(x)    (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_BIT_FIELD_Reserved1_SHIFT)) & XECC_MULTI_ERR_BIT_FIELD_Reserved1_MASK)
98974 /*! @} */
98975 
98976 /*! @name ECC_BASE_ADDR0 - ECC Region 0 Base Address */
98977 /*! @{ */
98978 
98979 #define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_MASK  (0xFFFFFFFFU)
98980 #define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_SHIFT (0U)
98981 /*! ECC_BASE_ADDR0 - ECC Region 0 Base Address */
98982 #define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0(x)    (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_SHIFT)) & XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_MASK)
98983 /*! @} */
98984 
98985 /*! @name ECC_END_ADDR0 - ECC Region 0 End Address */
98986 /*! @{ */
98987 
98988 #define XECC_ECC_END_ADDR0_ECC_END_ADDR0_MASK    (0xFFFFFFFFU)
98989 #define XECC_ECC_END_ADDR0_ECC_END_ADDR0_SHIFT   (0U)
98990 /*! ECC_END_ADDR0 - ECC Region 0 End Address */
98991 #define XECC_ECC_END_ADDR0_ECC_END_ADDR0(x)      (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR0_ECC_END_ADDR0_SHIFT)) & XECC_ECC_END_ADDR0_ECC_END_ADDR0_MASK)
98992 /*! @} */
98993 
98994 /*! @name ECC_BASE_ADDR1 - ECC Region 1 Base Address */
98995 /*! @{ */
98996 
98997 #define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_MASK  (0xFFFFFFFFU)
98998 #define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_SHIFT (0U)
98999 /*! ECC_BASE_ADDR1 - ECC Region 1 Base Address */
99000 #define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1(x)    (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_SHIFT)) & XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_MASK)
99001 /*! @} */
99002 
99003 /*! @name ECC_END_ADDR1 - ECC Region 1 End Address */
99004 /*! @{ */
99005 
99006 #define XECC_ECC_END_ADDR1_ECC_END_ADDR1_MASK    (0xFFFFFFFFU)
99007 #define XECC_ECC_END_ADDR1_ECC_END_ADDR1_SHIFT   (0U)
99008 /*! ECC_END_ADDR1 - ECC Region 1 End Address */
99009 #define XECC_ECC_END_ADDR1_ECC_END_ADDR1(x)      (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR1_ECC_END_ADDR1_SHIFT)) & XECC_ECC_END_ADDR1_ECC_END_ADDR1_MASK)
99010 /*! @} */
99011 
99012 /*! @name ECC_BASE_ADDR2 - ECC Region 2 Base Address */
99013 /*! @{ */
99014 
99015 #define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_MASK  (0xFFFFFFFFU)
99016 #define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_SHIFT (0U)
99017 /*! ECC_BASE_ADDR2 - ECC Region 2 Base Address */
99018 #define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2(x)    (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_SHIFT)) & XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_MASK)
99019 /*! @} */
99020 
99021 /*! @name ECC_END_ADDR2 - ECC Region 2 End Address */
99022 /*! @{ */
99023 
99024 #define XECC_ECC_END_ADDR2_ECC_END_ADDR2_MASK    (0xFFFFFFFFU)
99025 #define XECC_ECC_END_ADDR2_ECC_END_ADDR2_SHIFT   (0U)
99026 /*! ECC_END_ADDR2 - ECC Region 2 End Address */
99027 #define XECC_ECC_END_ADDR2_ECC_END_ADDR2(x)      (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR2_ECC_END_ADDR2_SHIFT)) & XECC_ECC_END_ADDR2_ECC_END_ADDR2_MASK)
99028 /*! @} */
99029 
99030 /*! @name ECC_BASE_ADDR3 - ECC Region 3 Base Address */
99031 /*! @{ */
99032 
99033 #define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_MASK  (0xFFFFFFFFU)
99034 #define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_SHIFT (0U)
99035 /*! ECC_BASE_ADDR3 - ECC Region 3 Base Address */
99036 #define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3(x)    (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_SHIFT)) & XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_MASK)
99037 /*! @} */
99038 
99039 /*! @name ECC_END_ADDR3 - ECC Region 3 End Address */
99040 /*! @{ */
99041 
99042 #define XECC_ECC_END_ADDR3_ECC_END_ADDR3_MASK    (0xFFFFFFFFU)
99043 #define XECC_ECC_END_ADDR3_ECC_END_ADDR3_SHIFT   (0U)
99044 /*! ECC_END_ADDR3 - ECC Region 3 End Address */
99045 #define XECC_ECC_END_ADDR3_ECC_END_ADDR3(x)      (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR3_ECC_END_ADDR3_SHIFT)) & XECC_ECC_END_ADDR3_ECC_END_ADDR3_MASK)
99046 /*! @} */
99047 
99048 
99049 /*!
99050  * @}
99051  */ /* end of group XECC_Register_Masks */
99052 
99053 
99054 /* XECC - Peripheral instance base addresses */
99055 /** Peripheral XECC_FLEXSPI1 base address */
99056 #define XECC_FLEXSPI1_BASE                       (0x4001C000u)
99057 /** Peripheral XECC_FLEXSPI1 base pointer */
99058 #define XECC_FLEXSPI1                            ((XECC_Type *)XECC_FLEXSPI1_BASE)
99059 /** Peripheral XECC_FLEXSPI2 base address */
99060 #define XECC_FLEXSPI2_BASE                       (0x40020000u)
99061 /** Peripheral XECC_FLEXSPI2 base pointer */
99062 #define XECC_FLEXSPI2                            ((XECC_Type *)XECC_FLEXSPI2_BASE)
99063 /** Peripheral XECC_SEMC base address */
99064 #define XECC_SEMC_BASE                           (0x40024000u)
99065 /** Peripheral XECC_SEMC base pointer */
99066 #define XECC_SEMC                                ((XECC_Type *)XECC_SEMC_BASE)
99067 /** Array initializer of XECC peripheral base addresses */
99068 #define XECC_BASE_ADDRS                          { 0u, XECC_FLEXSPI1_BASE, XECC_FLEXSPI2_BASE, XECC_SEMC_BASE }
99069 /** Array initializer of XECC peripheral base pointers */
99070 #define XECC_BASE_PTRS                           { (XECC_Type *)0u, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC }
99071 
99072 /*!
99073  * @}
99074  */ /* end of group XECC_Peripheral_Access_Layer */
99075 
99076 
99077 /* ----------------------------------------------------------------------------
99078    -- XRDC2 Peripheral Access Layer
99079    ---------------------------------------------------------------------------- */
99080 
99081 /*!
99082  * @addtogroup XRDC2_Peripheral_Access_Layer XRDC2 Peripheral Access Layer
99083  * @{
99084  */
99085 
99086 /** XRDC2 - Register Layout Typedef */
99087 typedef struct {
99088   __IO uint32_t MCR;                               /**< Module Control Register, offset: 0x0 */
99089   __I  uint32_t SR;                                /**< Status Register, offset: 0x4 */
99090        uint8_t RESERVED_0[4088];
99091   struct {                                         /* offset: 0x1000, array step: 0x8 */
99092     __IO uint32_t MSC_MSAC_W0;                       /**< Memory Slot Access Control, array offset: 0x1000, array step: 0x8 */
99093     __IO uint32_t MSC_MSAC_W1;                       /**< Memory Slot Access Control, array offset: 0x1004, array step: 0x8 */
99094   } MSCI_MSAC_WK[128];
99095        uint8_t RESERVED_1[3072];
99096   struct {                                         /* offset: 0x2000, array step: index*0x100, index2*0x8 */
99097     __IO uint32_t MDAC_MDA_W0;                       /**< Master Domain Assignment, array offset: 0x2000, array step: index*0x100, index2*0x8 */
99098     __IO uint32_t MDAC_MDA_W1;                       /**< Master Domain Assignment, array offset: 0x2004, array step: index*0x100, index2*0x8 */
99099   } MDACI_MDAJ[32][32];
99100   struct {                                         /* offset: 0x4000, array step: index*0x800, index2*0x8 */
99101     __IO uint32_t PAC_PDAC_W0;                       /**< Peripheral Domain Access Control, array offset: 0x4000, array step: index*0x800, index2*0x8 */
99102     __IO uint32_t PAC_PDAC_W1;                       /**< Peripheral Domain Access Control, array offset: 0x4004, array step: index*0x800, index2*0x8 */
99103   } PACI_PDACJ[8][256];
99104   struct {                                         /* offset: 0x8000, array step: index*0x400, index2*0x20 */
99105     __IO uint32_t MRC_MRGD_W0;                       /**< Memory Region Descriptor, array offset: 0x8000, array step: index*0x400, index2*0x20 */
99106     __IO uint32_t MRC_MRGD_W1;                       /**< Memory Region Descriptor, array offset: 0x8004, array step: index*0x400, index2*0x20 */
99107     __IO uint32_t MRC_MRGD_W2;                       /**< Memory Region Descriptor, array offset: 0x8008, array step: index*0x400, index2*0x20 */
99108     __IO uint32_t MRC_MRGD_W3;                       /**< Memory Region Descriptor, array offset: 0x800C, array step: index*0x400, index2*0x20 */
99109          uint8_t RESERVED_0[4];
99110     __IO uint32_t MRC_MRGD_W5;                       /**< Memory Region Descriptor, array offset: 0x8014, array step: index*0x400, index2*0x20 */
99111     __IO uint32_t MRC_MRGD_W6;                       /**< Memory Region Descriptor, array offset: 0x8018, array step: index*0x400, index2*0x20 */
99112          uint8_t RESERVED_1[4];
99113   } MRCI_MRGDJ[32][32];
99114 } XRDC2_Type;
99115 
99116 /* ----------------------------------------------------------------------------
99117    -- XRDC2 Register Masks
99118    ---------------------------------------------------------------------------- */
99119 
99120 /*!
99121  * @addtogroup XRDC2_Register_Masks XRDC2 Register Masks
99122  * @{
99123  */
99124 
99125 /*! @name MCR - Module Control Register */
99126 /*! @{ */
99127 
99128 #define XRDC2_MCR_GVLDM_MASK                     (0x1U)
99129 #define XRDC2_MCR_GVLDM_SHIFT                    (0U)
99130 /*! GVLDM - Global Valid MDAC
99131  *  0b0..MDACs are disabled.
99132  *  0b1..MDACs are enabled.
99133  */
99134 #define XRDC2_MCR_GVLDM(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK)
99135 
99136 #define XRDC2_MCR_GVLDC_MASK                     (0x2U)
99137 #define XRDC2_MCR_GVLDC_SHIFT                    (1U)
99138 /*! GVLDC - Global Valid Access Control
99139  *  0b0..Access controls are disabled, XRDC2 allows all transactions.
99140  *  0b1..Access controls are enabled.
99141  */
99142 #define XRDC2_MCR_GVLDC(x)                       (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK)
99143 
99144 #define XRDC2_MCR_GCL_MASK                       (0x30U)
99145 #define XRDC2_MCR_GCL_SHIFT                      (4U)
99146 /*! GCL - Global Configuration Lock
99147  *  0b00..Lock disabled, registers can be written by any domain.
99148  *  0b01..Lock disabled until the next reset, registers can be written by any domain.
99149  *  0b10..Lock enabled, only the global configuration lock owner (SR[GCLO]) can write to registers.
99150  *  0b11..Lock enabled, all registers are read only until the next reset.
99151  */
99152 #define XRDC2_MCR_GCL(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GCL_SHIFT)) & XRDC2_MCR_GCL_MASK)
99153 /*! @} */
99154 
99155 /*! @name SR - Status Register */
99156 /*! @{ */
99157 
99158 #define XRDC2_SR_DIN_MASK                        (0xFU)
99159 #define XRDC2_SR_DIN_SHIFT                       (0U)
99160 /*! DIN - Domain Identifier Number */
99161 #define XRDC2_SR_DIN(x)                          (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DIN_SHIFT)) & XRDC2_SR_DIN_MASK)
99162 
99163 #define XRDC2_SR_HRL_MASK                        (0xF0U)
99164 #define XRDC2_SR_HRL_SHIFT                       (4U)
99165 /*! HRL - Hardware Revision Level */
99166 #define XRDC2_SR_HRL(x)                          (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK)
99167 
99168 #define XRDC2_SR_GCLO_MASK                       (0xF00U)
99169 #define XRDC2_SR_GCLO_SHIFT                      (8U)
99170 /*! GCLO - Global Configuration Lock Owner */
99171 #define XRDC2_SR_GCLO(x)                         (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_GCLO_SHIFT)) & XRDC2_SR_GCLO_MASK)
99172 /*! @} */
99173 
99174 /*! @name MSC_MSAC_W0 - Memory Slot Access Control */
99175 /*! @{ */
99176 
99177 #define XRDC2_MSC_MSAC_W0_D0ACP_MASK             (0x7U)
99178 #define XRDC2_MSC_MSAC_W0_D0ACP_SHIFT            (0U)
99179 /*! D0ACP - Domain "x" access control policy */
99180 #define XRDC2_MSC_MSAC_W0_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D0ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D0ACP_MASK)
99181 
99182 #define XRDC2_MSC_MSAC_W0_D1ACP_MASK             (0x38U)
99183 #define XRDC2_MSC_MSAC_W0_D1ACP_SHIFT            (3U)
99184 /*! D1ACP - Domain "x" access control policy */
99185 #define XRDC2_MSC_MSAC_W0_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D1ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D1ACP_MASK)
99186 
99187 #define XRDC2_MSC_MSAC_W0_D2ACP_MASK             (0x1C0U)
99188 #define XRDC2_MSC_MSAC_W0_D2ACP_SHIFT            (6U)
99189 /*! D2ACP - Domain "x" access control policy */
99190 #define XRDC2_MSC_MSAC_W0_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D2ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D2ACP_MASK)
99191 
99192 #define XRDC2_MSC_MSAC_W0_D3ACP_MASK             (0xE00U)
99193 #define XRDC2_MSC_MSAC_W0_D3ACP_SHIFT            (9U)
99194 /*! D3ACP - Domain "x" access control policy */
99195 #define XRDC2_MSC_MSAC_W0_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D3ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D3ACP_MASK)
99196 
99197 #define XRDC2_MSC_MSAC_W0_D4ACP_MASK             (0x7000U)
99198 #define XRDC2_MSC_MSAC_W0_D4ACP_SHIFT            (12U)
99199 /*! D4ACP - Domain "x" access control policy */
99200 #define XRDC2_MSC_MSAC_W0_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D4ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D4ACP_MASK)
99201 
99202 #define XRDC2_MSC_MSAC_W0_D5ACP_MASK             (0x38000U)
99203 #define XRDC2_MSC_MSAC_W0_D5ACP_SHIFT            (15U)
99204 /*! D5ACP - Domain "x" access control policy */
99205 #define XRDC2_MSC_MSAC_W0_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D5ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D5ACP_MASK)
99206 
99207 #define XRDC2_MSC_MSAC_W0_D6ACP_MASK             (0x1C0000U)
99208 #define XRDC2_MSC_MSAC_W0_D6ACP_SHIFT            (18U)
99209 /*! D6ACP - Domain "x" access control policy */
99210 #define XRDC2_MSC_MSAC_W0_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D6ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D6ACP_MASK)
99211 
99212 #define XRDC2_MSC_MSAC_W0_D7ACP_MASK             (0xE00000U)
99213 #define XRDC2_MSC_MSAC_W0_D7ACP_SHIFT            (21U)
99214 /*! D7ACP - Domain "x" access control policy */
99215 #define XRDC2_MSC_MSAC_W0_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D7ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D7ACP_MASK)
99216 
99217 #define XRDC2_MSC_MSAC_W0_EALO_MASK              (0xF000000U)
99218 #define XRDC2_MSC_MSAC_W0_EALO_SHIFT             (24U)
99219 /*! EALO - Exclusive Access Lock Owner */
99220 #define XRDC2_MSC_MSAC_W0_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_EALO_SHIFT)) & XRDC2_MSC_MSAC_W0_EALO_MASK)
99221 /*! @} */
99222 
99223 /* The count of XRDC2_MSC_MSAC_W0 */
99224 #define XRDC2_MSC_MSAC_W0_COUNT                  (128U)
99225 
99226 /*! @name MSC_MSAC_W1 - Memory Slot Access Control */
99227 /*! @{ */
99228 
99229 #define XRDC2_MSC_MSAC_W1_D8ACP_MASK             (0x7U)
99230 #define XRDC2_MSC_MSAC_W1_D8ACP_SHIFT            (0U)
99231 /*! D8ACP - Domain "x" access control policy */
99232 #define XRDC2_MSC_MSAC_W1_D8ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D8ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D8ACP_MASK)
99233 
99234 #define XRDC2_MSC_MSAC_W1_D9ACP_MASK             (0x38U)
99235 #define XRDC2_MSC_MSAC_W1_D9ACP_SHIFT            (3U)
99236 /*! D9ACP - Domain "x" access control policy */
99237 #define XRDC2_MSC_MSAC_W1_D9ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D9ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D9ACP_MASK)
99238 
99239 #define XRDC2_MSC_MSAC_W1_D10ACP_MASK            (0x1C0U)
99240 #define XRDC2_MSC_MSAC_W1_D10ACP_SHIFT           (6U)
99241 /*! D10ACP - Domain "x" access control policy */
99242 #define XRDC2_MSC_MSAC_W1_D10ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D10ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D10ACP_MASK)
99243 
99244 #define XRDC2_MSC_MSAC_W1_D11ACP_MASK            (0xE00U)
99245 #define XRDC2_MSC_MSAC_W1_D11ACP_SHIFT           (9U)
99246 /*! D11ACP - Domain "x" access control policy */
99247 #define XRDC2_MSC_MSAC_W1_D11ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D11ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D11ACP_MASK)
99248 
99249 #define XRDC2_MSC_MSAC_W1_D12ACP_MASK            (0x7000U)
99250 #define XRDC2_MSC_MSAC_W1_D12ACP_SHIFT           (12U)
99251 /*! D12ACP - Domain "x" access control policy */
99252 #define XRDC2_MSC_MSAC_W1_D12ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D12ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D12ACP_MASK)
99253 
99254 #define XRDC2_MSC_MSAC_W1_D13ACP_MASK            (0x38000U)
99255 #define XRDC2_MSC_MSAC_W1_D13ACP_SHIFT           (15U)
99256 /*! D13ACP - Domain "x" access control policy */
99257 #define XRDC2_MSC_MSAC_W1_D13ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D13ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D13ACP_MASK)
99258 
99259 #define XRDC2_MSC_MSAC_W1_D14ACP_MASK            (0x1C0000U)
99260 #define XRDC2_MSC_MSAC_W1_D14ACP_SHIFT           (18U)
99261 /*! D14ACP - Domain "x" access control policy */
99262 #define XRDC2_MSC_MSAC_W1_D14ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D14ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D14ACP_MASK)
99263 
99264 #define XRDC2_MSC_MSAC_W1_D15ACP_MASK            (0xE00000U)
99265 #define XRDC2_MSC_MSAC_W1_D15ACP_SHIFT           (21U)
99266 /*! D15ACP - Domain "x" access control policy */
99267 #define XRDC2_MSC_MSAC_W1_D15ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D15ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D15ACP_MASK)
99268 
99269 #define XRDC2_MSC_MSAC_W1_EAL_MASK               (0x3000000U)
99270 #define XRDC2_MSC_MSAC_W1_EAL_SHIFT              (24U)
99271 /*! EAL - Exclusive Access Lock
99272  *  0b00..Lock disabled.
99273  *  0b01..Lock disabled until next reset.
99274  *  0b10..Lock enabled, lock state = available.
99275  *  0b11..Lock enabled, lock state = not available.
99276  */
99277 #define XRDC2_MSC_MSAC_W1_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_EAL_SHIFT)) & XRDC2_MSC_MSAC_W1_EAL_MASK)
99278 
99279 #define XRDC2_MSC_MSAC_W1_DL2_MASK               (0x60000000U)
99280 #define XRDC2_MSC_MSAC_W1_DL2_SHIFT              (29U)
99281 /*! DL2 - Descriptor Lock
99282  *  0b00..Lock disabled, descriptor registers can be written.
99283  *  0b01..Lock disabled until the next reset, descriptor registers can be written.
99284  *  0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written.
99285  *  0b11..Lock enabled, descriptor registers are read-only until the next reset.
99286  */
99287 #define XRDC2_MSC_MSAC_W1_DL2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_DL2_SHIFT)) & XRDC2_MSC_MSAC_W1_DL2_MASK)
99288 
99289 #define XRDC2_MSC_MSAC_W1_VLD_MASK               (0x80000000U)
99290 #define XRDC2_MSC_MSAC_W1_VLD_SHIFT              (31U)
99291 /*! VLD - Valid
99292  *  0b0..The MSAC assignment is invalid.
99293  *  0b1..The MSAC assignment is valid.
99294  */
99295 #define XRDC2_MSC_MSAC_W1_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_VLD_SHIFT)) & XRDC2_MSC_MSAC_W1_VLD_MASK)
99296 /*! @} */
99297 
99298 /* The count of XRDC2_MSC_MSAC_W1 */
99299 #define XRDC2_MSC_MSAC_W1_COUNT                  (128U)
99300 
99301 /*! @name MDAC_MDA_W0 - Master Domain Assignment */
99302 /*! @{ */
99303 
99304 #define XRDC2_MDAC_MDA_W0_MASK_MASK              (0xFFFFU)
99305 #define XRDC2_MDAC_MDA_W0_MASK_SHIFT             (0U)
99306 /*! MASK - Mask */
99307 #define XRDC2_MDAC_MDA_W0_MASK(x)                (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MASK_SHIFT)) & XRDC2_MDAC_MDA_W0_MASK_MASK)
99308 
99309 #define XRDC2_MDAC_MDA_W0_MATCH_MASK             (0xFFFF0000U)
99310 #define XRDC2_MDAC_MDA_W0_MATCH_SHIFT            (16U)
99311 /*! MATCH - Match */
99312 #define XRDC2_MDAC_MDA_W0_MATCH(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MATCH_SHIFT)) & XRDC2_MDAC_MDA_W0_MATCH_MASK)
99313 /*! @} */
99314 
99315 /* The count of XRDC2_MDAC_MDA_W0 */
99316 #define XRDC2_MDAC_MDA_W0_COUNT                  (32U)
99317 
99318 /* The count of XRDC2_MDAC_MDA_W0 */
99319 #define XRDC2_MDAC_MDA_W0_COUNT2                 (32U)
99320 
99321 /*! @name MDAC_MDA_W1 - Master Domain Assignment */
99322 /*! @{ */
99323 
99324 #define XRDC2_MDAC_MDA_W1_DID_MASK               (0xF0000U)
99325 #define XRDC2_MDAC_MDA_W1_DID_SHIFT              (16U)
99326 /*! DID - Domain Identifier */
99327 #define XRDC2_MDAC_MDA_W1_DID(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DID_SHIFT)) & XRDC2_MDAC_MDA_W1_DID_MASK)
99328 
99329 #define XRDC2_MDAC_MDA_W1_PA_MASK                (0x3000000U)
99330 #define XRDC2_MDAC_MDA_W1_PA_SHIFT               (24U)
99331 /*! PA - Privileged attribute
99332  *  0b00..Use the bus master's privileged/user attribute directly.
99333  *  0b01..Use the bus master's privileged/user attribute directly.
99334  *  0b10..Force the bus attribute for this master to user.
99335  *  0b11..Force the bus attribute for this master to privileged.
99336  */
99337 #define XRDC2_MDAC_MDA_W1_PA(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_PA_SHIFT)) & XRDC2_MDAC_MDA_W1_PA_MASK)
99338 
99339 #define XRDC2_MDAC_MDA_W1_SA_MASK                (0xC000000U)
99340 #define XRDC2_MDAC_MDA_W1_SA_SHIFT               (26U)
99341 /*! SA - Secure attribute
99342  *  0b00..Use the bus master's secure/nonsecure attribute directly.
99343  *  0b01..Use the bus master's secure/nonsecure attribute directly.
99344  *  0b10..Force the bus attribute for this master to secure.
99345  *  0b11..Force the bus attribute for this master to nonsecure.
99346  */
99347 #define XRDC2_MDAC_MDA_W1_SA(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_SA_SHIFT)) & XRDC2_MDAC_MDA_W1_SA_MASK)
99348 
99349 #define XRDC2_MDAC_MDA_W1_DL_MASK                (0x40000000U)
99350 #define XRDC2_MDAC_MDA_W1_DL_SHIFT               (30U)
99351 /*! DL - Descriptor Lock
99352  *  0b0..Lock disabled, registers can be written.
99353  *  0b1..Lock enabled, registers are read-only until the next reset.
99354  */
99355 #define XRDC2_MDAC_MDA_W1_DL(x)                  (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DL_SHIFT)) & XRDC2_MDAC_MDA_W1_DL_MASK)
99356 
99357 #define XRDC2_MDAC_MDA_W1_VLD_MASK               (0x80000000U)
99358 #define XRDC2_MDAC_MDA_W1_VLD_SHIFT              (31U)
99359 /*! VLD - Valid
99360  *  0b0..The MDA is invalid.
99361  *  0b1..The MDA is valid.
99362  */
99363 #define XRDC2_MDAC_MDA_W1_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_VLD_SHIFT)) & XRDC2_MDAC_MDA_W1_VLD_MASK)
99364 /*! @} */
99365 
99366 /* The count of XRDC2_MDAC_MDA_W1 */
99367 #define XRDC2_MDAC_MDA_W1_COUNT                  (32U)
99368 
99369 /* The count of XRDC2_MDAC_MDA_W1 */
99370 #define XRDC2_MDAC_MDA_W1_COUNT2                 (32U)
99371 
99372 /*! @name PAC_PDAC_W0 - Peripheral Domain Access Control */
99373 /*! @{ */
99374 
99375 #define XRDC2_PAC_PDAC_W0_D0ACP_MASK             (0x7U)
99376 #define XRDC2_PAC_PDAC_W0_D0ACP_SHIFT            (0U)
99377 /*! D0ACP - Domain "x" access control policy */
99378 #define XRDC2_PAC_PDAC_W0_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D0ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D0ACP_MASK)
99379 
99380 #define XRDC2_PAC_PDAC_W0_D1ACP_MASK             (0x38U)
99381 #define XRDC2_PAC_PDAC_W0_D1ACP_SHIFT            (3U)
99382 /*! D1ACP - Domain "x" access control policy */
99383 #define XRDC2_PAC_PDAC_W0_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D1ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D1ACP_MASK)
99384 
99385 #define XRDC2_PAC_PDAC_W0_D2ACP_MASK             (0x1C0U)
99386 #define XRDC2_PAC_PDAC_W0_D2ACP_SHIFT            (6U)
99387 /*! D2ACP - Domain "x" access control policy */
99388 #define XRDC2_PAC_PDAC_W0_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D2ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D2ACP_MASK)
99389 
99390 #define XRDC2_PAC_PDAC_W0_D3ACP_MASK             (0xE00U)
99391 #define XRDC2_PAC_PDAC_W0_D3ACP_SHIFT            (9U)
99392 /*! D3ACP - Domain "x" access control policy */
99393 #define XRDC2_PAC_PDAC_W0_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D3ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D3ACP_MASK)
99394 
99395 #define XRDC2_PAC_PDAC_W0_D4ACP_MASK             (0x7000U)
99396 #define XRDC2_PAC_PDAC_W0_D4ACP_SHIFT            (12U)
99397 /*! D4ACP - Domain "x" access control policy */
99398 #define XRDC2_PAC_PDAC_W0_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D4ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D4ACP_MASK)
99399 
99400 #define XRDC2_PAC_PDAC_W0_D5ACP_MASK             (0x38000U)
99401 #define XRDC2_PAC_PDAC_W0_D5ACP_SHIFT            (15U)
99402 /*! D5ACP - Domain "x" access control policy */
99403 #define XRDC2_PAC_PDAC_W0_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D5ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D5ACP_MASK)
99404 
99405 #define XRDC2_PAC_PDAC_W0_D6ACP_MASK             (0x1C0000U)
99406 #define XRDC2_PAC_PDAC_W0_D6ACP_SHIFT            (18U)
99407 /*! D6ACP - Domain "x" access control policy */
99408 #define XRDC2_PAC_PDAC_W0_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D6ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D6ACP_MASK)
99409 
99410 #define XRDC2_PAC_PDAC_W0_D7ACP_MASK             (0xE00000U)
99411 #define XRDC2_PAC_PDAC_W0_D7ACP_SHIFT            (21U)
99412 /*! D7ACP - Domain "x" access control policy */
99413 #define XRDC2_PAC_PDAC_W0_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D7ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D7ACP_MASK)
99414 
99415 #define XRDC2_PAC_PDAC_W0_EALO_MASK              (0xF000000U)
99416 #define XRDC2_PAC_PDAC_W0_EALO_SHIFT             (24U)
99417 /*! EALO - Exclusive Access Lock Owner */
99418 #define XRDC2_PAC_PDAC_W0_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_EALO_SHIFT)) & XRDC2_PAC_PDAC_W0_EALO_MASK)
99419 /*! @} */
99420 
99421 /* The count of XRDC2_PAC_PDAC_W0 */
99422 #define XRDC2_PAC_PDAC_W0_COUNT                  (8U)
99423 
99424 /* The count of XRDC2_PAC_PDAC_W0 */
99425 #define XRDC2_PAC_PDAC_W0_COUNT2                 (256U)
99426 
99427 /*! @name PAC_PDAC_W1 - Peripheral Domain Access Control */
99428 /*! @{ */
99429 
99430 #define XRDC2_PAC_PDAC_W1_D8ACP_MASK             (0x7U)
99431 #define XRDC2_PAC_PDAC_W1_D8ACP_SHIFT            (0U)
99432 /*! D8ACP - Domain "x" access control policy */
99433 #define XRDC2_PAC_PDAC_W1_D8ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D8ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D8ACP_MASK)
99434 
99435 #define XRDC2_PAC_PDAC_W1_D9ACP_MASK             (0x38U)
99436 #define XRDC2_PAC_PDAC_W1_D9ACP_SHIFT            (3U)
99437 /*! D9ACP - Domain "x" access control policy */
99438 #define XRDC2_PAC_PDAC_W1_D9ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D9ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D9ACP_MASK)
99439 
99440 #define XRDC2_PAC_PDAC_W1_D10ACP_MASK            (0x1C0U)
99441 #define XRDC2_PAC_PDAC_W1_D10ACP_SHIFT           (6U)
99442 /*! D10ACP - Domain "x" access control policy */
99443 #define XRDC2_PAC_PDAC_W1_D10ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D10ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D10ACP_MASK)
99444 
99445 #define XRDC2_PAC_PDAC_W1_D11ACP_MASK            (0xE00U)
99446 #define XRDC2_PAC_PDAC_W1_D11ACP_SHIFT           (9U)
99447 /*! D11ACP - Domain "x" access control policy */
99448 #define XRDC2_PAC_PDAC_W1_D11ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D11ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D11ACP_MASK)
99449 
99450 #define XRDC2_PAC_PDAC_W1_D12ACP_MASK            (0x7000U)
99451 #define XRDC2_PAC_PDAC_W1_D12ACP_SHIFT           (12U)
99452 /*! D12ACP - Domain "x" access control policy */
99453 #define XRDC2_PAC_PDAC_W1_D12ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D12ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D12ACP_MASK)
99454 
99455 #define XRDC2_PAC_PDAC_W1_D13ACP_MASK            (0x38000U)
99456 #define XRDC2_PAC_PDAC_W1_D13ACP_SHIFT           (15U)
99457 /*! D13ACP - Domain "x" access control policy */
99458 #define XRDC2_PAC_PDAC_W1_D13ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D13ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D13ACP_MASK)
99459 
99460 #define XRDC2_PAC_PDAC_W1_D14ACP_MASK            (0x1C0000U)
99461 #define XRDC2_PAC_PDAC_W1_D14ACP_SHIFT           (18U)
99462 /*! D14ACP - Domain "x" access control policy */
99463 #define XRDC2_PAC_PDAC_W1_D14ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D14ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D14ACP_MASK)
99464 
99465 #define XRDC2_PAC_PDAC_W1_D15ACP_MASK            (0xE00000U)
99466 #define XRDC2_PAC_PDAC_W1_D15ACP_SHIFT           (21U)
99467 /*! D15ACP - Domain "x" access control policy */
99468 #define XRDC2_PAC_PDAC_W1_D15ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D15ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D15ACP_MASK)
99469 
99470 #define XRDC2_PAC_PDAC_W1_EAL_MASK               (0x3000000U)
99471 #define XRDC2_PAC_PDAC_W1_EAL_SHIFT              (24U)
99472 /*! EAL - Exclusive Access Lock
99473  *  0b00..Lock disabled.
99474  *  0b01..Lock disabled until next reset.
99475  *  0b10..Lock enabled, lock state = available.
99476  *  0b11..Lock enabled, lock state = not available.
99477  */
99478 #define XRDC2_PAC_PDAC_W1_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_EAL_SHIFT)) & XRDC2_PAC_PDAC_W1_EAL_MASK)
99479 
99480 #define XRDC2_PAC_PDAC_W1_DL2_MASK               (0x60000000U)
99481 #define XRDC2_PAC_PDAC_W1_DL2_SHIFT              (29U)
99482 /*! DL2 - Descriptor Lock
99483  *  0b00..Lock disabled, descriptor registers can be written..
99484  *  0b01..Lock disabled until the next reset, descriptor registers can be written..
99485  *  0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written..
99486  *  0b11..Lock enabled, descriptor registers are read-only until the next reset.
99487  */
99488 #define XRDC2_PAC_PDAC_W1_DL2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_DL2_SHIFT)) & XRDC2_PAC_PDAC_W1_DL2_MASK)
99489 
99490 #define XRDC2_PAC_PDAC_W1_VLD_MASK               (0x80000000U)
99491 #define XRDC2_PAC_PDAC_W1_VLD_SHIFT              (31U)
99492 /*! VLD - Valid
99493  *  0b0..The PDAC assignment is invalid.
99494  *  0b1..The PDAC assignment is valid.
99495  */
99496 #define XRDC2_PAC_PDAC_W1_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_VLD_SHIFT)) & XRDC2_PAC_PDAC_W1_VLD_MASK)
99497 /*! @} */
99498 
99499 /* The count of XRDC2_PAC_PDAC_W1 */
99500 #define XRDC2_PAC_PDAC_W1_COUNT                  (8U)
99501 
99502 /* The count of XRDC2_PAC_PDAC_W1 */
99503 #define XRDC2_PAC_PDAC_W1_COUNT2                 (256U)
99504 
99505 /*! @name MRC_MRGD_W0 - Memory Region Descriptor */
99506 /*! @{ */
99507 
99508 #define XRDC2_MRC_MRGD_W0_SRTADDR_MASK           (0xFFFFF000U)
99509 #define XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT          (12U)
99510 /*! SRTADDR - Start Address */
99511 #define XRDC2_MRC_MRGD_W0_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W0_SRTADDR_MASK)
99512 /*! @} */
99513 
99514 /* The count of XRDC2_MRC_MRGD_W0 */
99515 #define XRDC2_MRC_MRGD_W0_COUNT                  (32U)
99516 
99517 /* The count of XRDC2_MRC_MRGD_W0 */
99518 #define XRDC2_MRC_MRGD_W0_COUNT2                 (32U)
99519 
99520 /*! @name MRC_MRGD_W1 - Memory Region Descriptor */
99521 /*! @{ */
99522 
99523 #define XRDC2_MRC_MRGD_W1_SRTADDR_MASK           (0xFU)
99524 #define XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT          (0U)
99525 /*! SRTADDR - Start Address */
99526 #define XRDC2_MRC_MRGD_W1_SRTADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W1_SRTADDR_MASK)
99527 /*! @} */
99528 
99529 /* The count of XRDC2_MRC_MRGD_W1 */
99530 #define XRDC2_MRC_MRGD_W1_COUNT                  (32U)
99531 
99532 /* The count of XRDC2_MRC_MRGD_W1 */
99533 #define XRDC2_MRC_MRGD_W1_COUNT2                 (32U)
99534 
99535 /*! @name MRC_MRGD_W2 - Memory Region Descriptor */
99536 /*! @{ */
99537 
99538 #define XRDC2_MRC_MRGD_W2_ENDADDR_MASK           (0xFFFFF000U)
99539 #define XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT          (12U)
99540 /*! ENDADDR - End Address */
99541 #define XRDC2_MRC_MRGD_W2_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W2_ENDADDR_MASK)
99542 /*! @} */
99543 
99544 /* The count of XRDC2_MRC_MRGD_W2 */
99545 #define XRDC2_MRC_MRGD_W2_COUNT                  (32U)
99546 
99547 /* The count of XRDC2_MRC_MRGD_W2 */
99548 #define XRDC2_MRC_MRGD_W2_COUNT2                 (32U)
99549 
99550 /*! @name MRC_MRGD_W3 - Memory Region Descriptor */
99551 /*! @{ */
99552 
99553 #define XRDC2_MRC_MRGD_W3_ENDADDR_MASK           (0xFU)
99554 #define XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT          (0U)
99555 /*! ENDADDR - End Address */
99556 #define XRDC2_MRC_MRGD_W3_ENDADDR(x)             (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W3_ENDADDR_MASK)
99557 /*! @} */
99558 
99559 /* The count of XRDC2_MRC_MRGD_W3 */
99560 #define XRDC2_MRC_MRGD_W3_COUNT                  (32U)
99561 
99562 /* The count of XRDC2_MRC_MRGD_W3 */
99563 #define XRDC2_MRC_MRGD_W3_COUNT2                 (32U)
99564 
99565 /*! @name MRC_MRGD_W5 - Memory Region Descriptor */
99566 /*! @{ */
99567 
99568 #define XRDC2_MRC_MRGD_W5_D0ACP_MASK             (0x7U)
99569 #define XRDC2_MRC_MRGD_W5_D0ACP_SHIFT            (0U)
99570 /*! D0ACP - Domain "x" access control policy */
99571 #define XRDC2_MRC_MRGD_W5_D0ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D0ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D0ACP_MASK)
99572 
99573 #define XRDC2_MRC_MRGD_W5_D1ACP_MASK             (0x38U)
99574 #define XRDC2_MRC_MRGD_W5_D1ACP_SHIFT            (3U)
99575 /*! D1ACP - Domain "x" access control policy */
99576 #define XRDC2_MRC_MRGD_W5_D1ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D1ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D1ACP_MASK)
99577 
99578 #define XRDC2_MRC_MRGD_W5_D2ACP_MASK             (0x1C0U)
99579 #define XRDC2_MRC_MRGD_W5_D2ACP_SHIFT            (6U)
99580 /*! D2ACP - Domain "x" access control policy */
99581 #define XRDC2_MRC_MRGD_W5_D2ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D2ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D2ACP_MASK)
99582 
99583 #define XRDC2_MRC_MRGD_W5_D3ACP_MASK             (0xE00U)
99584 #define XRDC2_MRC_MRGD_W5_D3ACP_SHIFT            (9U)
99585 /*! D3ACP - Domain "x" access control policy */
99586 #define XRDC2_MRC_MRGD_W5_D3ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D3ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D3ACP_MASK)
99587 
99588 #define XRDC2_MRC_MRGD_W5_D4ACP_MASK             (0x7000U)
99589 #define XRDC2_MRC_MRGD_W5_D4ACP_SHIFT            (12U)
99590 /*! D4ACP - Domain "x" access control policy */
99591 #define XRDC2_MRC_MRGD_W5_D4ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D4ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D4ACP_MASK)
99592 
99593 #define XRDC2_MRC_MRGD_W5_D5ACP_MASK             (0x38000U)
99594 #define XRDC2_MRC_MRGD_W5_D5ACP_SHIFT            (15U)
99595 /*! D5ACP - Domain "x" access control policy */
99596 #define XRDC2_MRC_MRGD_W5_D5ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D5ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D5ACP_MASK)
99597 
99598 #define XRDC2_MRC_MRGD_W5_D6ACP_MASK             (0x1C0000U)
99599 #define XRDC2_MRC_MRGD_W5_D6ACP_SHIFT            (18U)
99600 /*! D6ACP - Domain "x" access control policy */
99601 #define XRDC2_MRC_MRGD_W5_D6ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D6ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D6ACP_MASK)
99602 
99603 #define XRDC2_MRC_MRGD_W5_D7ACP_MASK             (0xE00000U)
99604 #define XRDC2_MRC_MRGD_W5_D7ACP_SHIFT            (21U)
99605 /*! D7ACP - Domain "x" access control policy */
99606 #define XRDC2_MRC_MRGD_W5_D7ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D7ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D7ACP_MASK)
99607 
99608 #define XRDC2_MRC_MRGD_W5_EALO_MASK              (0xF000000U)
99609 #define XRDC2_MRC_MRGD_W5_EALO_SHIFT             (24U)
99610 /*! EALO - Exclusive Access Lock Owner */
99611 #define XRDC2_MRC_MRGD_W5_EALO(x)                (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_EALO_SHIFT)) & XRDC2_MRC_MRGD_W5_EALO_MASK)
99612 /*! @} */
99613 
99614 /* The count of XRDC2_MRC_MRGD_W5 */
99615 #define XRDC2_MRC_MRGD_W5_COUNT                  (32U)
99616 
99617 /* The count of XRDC2_MRC_MRGD_W5 */
99618 #define XRDC2_MRC_MRGD_W5_COUNT2                 (32U)
99619 
99620 /*! @name MRC_MRGD_W6 - Memory Region Descriptor */
99621 /*! @{ */
99622 
99623 #define XRDC2_MRC_MRGD_W6_D8ACP_MASK             (0x7U)
99624 #define XRDC2_MRC_MRGD_W6_D8ACP_SHIFT            (0U)
99625 /*! D8ACP - Domain "x" access control policy */
99626 #define XRDC2_MRC_MRGD_W6_D8ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D8ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D8ACP_MASK)
99627 
99628 #define XRDC2_MRC_MRGD_W6_D9ACP_MASK             (0x38U)
99629 #define XRDC2_MRC_MRGD_W6_D9ACP_SHIFT            (3U)
99630 /*! D9ACP - Domain "x" access control policy */
99631 #define XRDC2_MRC_MRGD_W6_D9ACP(x)               (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D9ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D9ACP_MASK)
99632 
99633 #define XRDC2_MRC_MRGD_W6_D10ACP_MASK            (0x1C0U)
99634 #define XRDC2_MRC_MRGD_W6_D10ACP_SHIFT           (6U)
99635 /*! D10ACP - Domain "x" access control policy */
99636 #define XRDC2_MRC_MRGD_W6_D10ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D10ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D10ACP_MASK)
99637 
99638 #define XRDC2_MRC_MRGD_W6_D11ACP_MASK            (0xE00U)
99639 #define XRDC2_MRC_MRGD_W6_D11ACP_SHIFT           (9U)
99640 /*! D11ACP - Domain "x" access control policy */
99641 #define XRDC2_MRC_MRGD_W6_D11ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D11ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D11ACP_MASK)
99642 
99643 #define XRDC2_MRC_MRGD_W6_D12ACP_MASK            (0x7000U)
99644 #define XRDC2_MRC_MRGD_W6_D12ACP_SHIFT           (12U)
99645 /*! D12ACP - Domain "x" access control policy */
99646 #define XRDC2_MRC_MRGD_W6_D12ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D12ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D12ACP_MASK)
99647 
99648 #define XRDC2_MRC_MRGD_W6_D13ACP_MASK            (0x38000U)
99649 #define XRDC2_MRC_MRGD_W6_D13ACP_SHIFT           (15U)
99650 /*! D13ACP - Domain "x" access control policy */
99651 #define XRDC2_MRC_MRGD_W6_D13ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D13ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D13ACP_MASK)
99652 
99653 #define XRDC2_MRC_MRGD_W6_D14ACP_MASK            (0x1C0000U)
99654 #define XRDC2_MRC_MRGD_W6_D14ACP_SHIFT           (18U)
99655 /*! D14ACP - Domain "x" access control policy */
99656 #define XRDC2_MRC_MRGD_W6_D14ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D14ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D14ACP_MASK)
99657 
99658 #define XRDC2_MRC_MRGD_W6_D15ACP_MASK            (0xE00000U)
99659 #define XRDC2_MRC_MRGD_W6_D15ACP_SHIFT           (21U)
99660 /*! D15ACP - Domain "x" access control policy */
99661 #define XRDC2_MRC_MRGD_W6_D15ACP(x)              (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D15ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D15ACP_MASK)
99662 
99663 #define XRDC2_MRC_MRGD_W6_EAL_MASK               (0x3000000U)
99664 #define XRDC2_MRC_MRGD_W6_EAL_SHIFT              (24U)
99665 /*! EAL - Exclusive Access Lock
99666  *  0b00..Lock disabled.
99667  *  0b01..Lock disabled until next reset.
99668  *  0b10..Lock enabled, lock state = available.
99669  *  0b11..Lock enabled, lock state = not available.
99670  */
99671 #define XRDC2_MRC_MRGD_W6_EAL(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_EAL_SHIFT)) & XRDC2_MRC_MRGD_W6_EAL_MASK)
99672 
99673 #define XRDC2_MRC_MRGD_W6_DL2_MASK               (0x60000000U)
99674 #define XRDC2_MRC_MRGD_W6_DL2_SHIFT              (29U)
99675 /*! DL2 - Descriptor Lock
99676  *  0b00..Lock disabled, descriptor registers can be written.
99677  *  0b01..Lock disabled until the next reset, descriptor registers can be written.
99678  *  0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written.
99679  *  0b11..Lock enabled, descriptor registers are read-only until the next reset.
99680  */
99681 #define XRDC2_MRC_MRGD_W6_DL2(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_DL2_SHIFT)) & XRDC2_MRC_MRGD_W6_DL2_MASK)
99682 
99683 #define XRDC2_MRC_MRGD_W6_VLD_MASK               (0x80000000U)
99684 #define XRDC2_MRC_MRGD_W6_VLD_SHIFT              (31U)
99685 /*! VLD - Valid
99686  *  0b0..The MRGD is invalid.
99687  *  0b1..The MRGD is valid.
99688  */
99689 #define XRDC2_MRC_MRGD_W6_VLD(x)                 (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_VLD_SHIFT)) & XRDC2_MRC_MRGD_W6_VLD_MASK)
99690 /*! @} */
99691 
99692 /* The count of XRDC2_MRC_MRGD_W6 */
99693 #define XRDC2_MRC_MRGD_W6_COUNT                  (32U)
99694 
99695 /* The count of XRDC2_MRC_MRGD_W6 */
99696 #define XRDC2_MRC_MRGD_W6_COUNT2                 (32U)
99697 
99698 
99699 /*!
99700  * @}
99701  */ /* end of group XRDC2_Register_Masks */
99702 
99703 
99704 /* XRDC2 - Peripheral instance base addresses */
99705 /** Peripheral XRDC2_D0 base address */
99706 #define XRDC2_D0_BASE                            (0x40CE0000u)
99707 /** Peripheral XRDC2_D0 base pointer */
99708 #define XRDC2_D0                                 ((XRDC2_Type *)XRDC2_D0_BASE)
99709 /** Peripheral XRDC2_D1 base address */
99710 #define XRDC2_D1_BASE                            (0x40CD0000u)
99711 /** Peripheral XRDC2_D1 base pointer */
99712 #define XRDC2_D1                                 ((XRDC2_Type *)XRDC2_D1_BASE)
99713 /** Array initializer of XRDC2 peripheral base addresses */
99714 #define XRDC2_BASE_ADDRS                         { XRDC2_D0_BASE, XRDC2_D1_BASE }
99715 /** Array initializer of XRDC2 peripheral base pointers */
99716 #define XRDC2_BASE_PTRS                          { XRDC2_D0, XRDC2_D1 }
99717 
99718 /*!
99719  * @}
99720  */ /* end of group XRDC2_Peripheral_Access_Layer */
99721 
99722 
99723 /*
99724 ** End of section using anonymous unions
99725 */
99726 
99727 #if defined(__ARMCC_VERSION)
99728   #if (__ARMCC_VERSION >= 6010050)
99729     #pragma clang diagnostic pop
99730   #else
99731     #pragma pop
99732   #endif
99733 #elif defined(__CWCC__)
99734   #pragma pop
99735 #elif defined(__GNUC__)
99736   /* leave anonymous unions enabled */
99737 #elif defined(__IAR_SYSTEMS_ICC__)
99738   #pragma language=default
99739 #else
99740   #error Not supported compiler type
99741 #endif
99742 
99743 /*!
99744  * @}
99745  */ /* end of group Peripheral_access_layer */
99746 
99747 
99748 /* ----------------------------------------------------------------------------
99749    -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
99750    ---------------------------------------------------------------------------- */
99751 
99752 /*!
99753  * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
99754  * @{
99755  */
99756 
99757 #if defined(__ARMCC_VERSION)
99758   #if (__ARMCC_VERSION >= 6010050)
99759     #pragma clang system_header
99760   #endif
99761 #elif defined(__IAR_SYSTEMS_ICC__)
99762   #pragma system_include
99763 #endif
99764 
99765 /**
99766  * @brief Mask and left-shift a bit field value for use in a register bit range.
99767  * @param field Name of the register bit field.
99768  * @param value Value of the bit field.
99769  * @return Masked and shifted value.
99770  */
99771 #define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
99772 /**
99773  * @brief Mask and right-shift a register value to extract a bit field value.
99774  * @param field Name of the register bit field.
99775  * @param value Value of the register.
99776  * @return Masked and shifted bit field value.
99777  */
99778 #define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
99779 
99780 /*!
99781  * @}
99782  */ /* end of group Bit_Field_Generic_Macros */
99783 
99784 
99785 /* ----------------------------------------------------------------------------
99786    -- SDK Compatibility
99787    ---------------------------------------------------------------------------- */
99788 
99789 /*!
99790  * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
99791  * @{
99792  */
99793 
99794 /* No SDK compatibility issues. */
99795 
99796 /*!
99797  * @}
99798  */ /* end of group SDK_Compatibility_Symbols */
99799 
99800 
99801 #endif  /* _MIMXRT1176_CM7_H_ */
99802 
99803