1 /*
2 * Copyright 2020-2021, 2023 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef __FSL_DCDC_H__
10 #define __FSL_DCDC_H__
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup dcdc_soc
16 * @{
17 */
18
19 /*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22 /*! @brief DCDC driver version. */
23 #define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2. */
24
25 /*! @brief The array of VDD1P0 target voltage in standby mode. */
26 #define STANDBY_MODE_VDD1P0_TARGET_VOLTAGE \
27 { \
28 625, 650, 675, 700, 725, 750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, 1125, \
29 1150, 1175, 1200, 1225, 1250, 1275, 1300, 1325, 1350, 1375, 1400 \
30 }
31
32 /*! @brief The array of VDD1P8 target voltage in standby mode. */
33 #define STANDBY_MODE_VDD1P8_TARGET_VOLTAGE \
34 { \
35 1525, 1550, 1575, 1600, 1625, 1650, 1675, 1700, 1725, 1750, 1775, 1800, 1825, 1850, 1875, 1900, 1925, 1950, \
36 1975, 2000, 2025, 2050, 2075, 2100, 2125, 2150, 2175, 2200, 2225, 2250, 2275, 2300 \
37 }
38
39 /*! @brief The array of VDD1P0 target voltage in buck mode. */
40 #define BUCK_MODE_VDD1P0_TARGET_VOLTAGE \
41 { \
42 600, 625, 650, 675, 700, 725, 750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, \
43 1125, 1150, 1175, 1200, 1225, 1250, 1275, 1300, 1325, 1350, 1375 \
44 }
45
46 /*! @brief The array of VDD1P8 target voltage in buck mode. */
47 #define BUCK_MODE_VDD1P8_TARGET_VOLTAGE \
48 { \
49 1500, 1525, 1550, 1575, 1600, 1625, 1650, 1675, 1700, 1725, 1750, 1775, 1800, 1825, 1850, 1875, 1900, 1925, \
50 1950, 1975, 2000, 2025, 2050, 2075, 2100, 2125, 2150, 2175, 2200, 2225, 2250, 2275 \
51 }
52
53 /*!
54 * @brief The enumeration of DCDC status flags.
55 */
56 enum _dcdc_status_flags
57 {
58 kDCDC_AlreadySettledStatusFlag = DCDC_REG0_STS_DC_OK_MASK, /*!< Indicate DCDC status.
59 1'b1: DCDC already settled
60 1'b0: DCDC is settling. */
61 };
62
63 /*!
64 * @brief System setpoints enumeration.
65 */
66 enum _dcdc_setpoint_map
67 {
68 kDCDC_SetPoint0 = 1UL << 0UL, /*!< Set point 0. */
69 kDCDC_SetPoint1 = 1UL << 1UL, /*!< Set point 1. */
70 kDCDC_SetPoint2 = 1UL << 2UL, /*!< Set point 2. */
71 kDCDC_SetPoint3 = 1UL << 3UL, /*!< Set point 3. */
72 kDCDC_SetPoint4 = 1UL << 4UL, /*!< Set point 4. */
73 kDCDC_SetPoint5 = 1UL << 5UL, /*!< Set point 5. */
74 kDCDC_SetPoint6 = 1UL << 6UL, /*!< Set point 6. */
75 kDCDC_SetPoint7 = 1UL << 7UL, /*!< Set point 7. */
76 kDCDC_SetPoint8 = 1UL << 8UL, /*!< Set point 8. */
77 kDCDC_SetPoint9 = 1UL << 9UL, /*!< Set point 9. */
78 kDCDC_SetPoint10 = 1UL << 10UL, /*!< Set point 10. */
79 kDCDC_SetPoint11 = 1UL << 11UL, /*!< Set point 11. */
80 kDCDC_SetPoint12 = 1UL << 12UL, /*!< Set point 12. */
81 kDCDC_SetPoint13 = 1UL << 13UL, /*!< Set point 13. */
82 kDCDC_SetPoint14 = 1UL << 14UL, /*!< Set point 14. */
83 kDCDC_SetPoint15 = 1UL << 15UL /*!< Set point 15. */
84 };
85
86 /*!
87 * @brief DCDC control mode, including setpoint control mode and static control mode.
88 */
89 typedef enum _dcdc_control_mode
90 {
91 kDCDC_StaticControl = 0U, /*!< Static control. */
92 kDCDC_SetPointControl = 1U, /*!< Controlled by GPC set points. */
93 } dcdc_control_mode_t;
94
95 /*!
96 * @brief DCDC trim input mode, including sample trim input and hold trim input.
97 */
98 typedef enum _dcdc_trim_input_mode
99 {
100 kDCDC_SampleTrimInput = 0U, /*!< Sample trim input. */
101 kDCDC_HoldTrimInput = 1U, /*!< Hold trim input. */
102 } dcdc_trim_input_mode_t;
103
104 /*!
105 * @brief The enumeration VDD1P0's target voltage value in standby mode.
106 */
107 typedef enum _dcdc_standby_mode_1P0_target_vol
108 {
109 kDCDC_1P0StbyTarget0P625V = 0U, /*!< In standby mode, the target voltage value of VDD1P0 is 0.625V. */
110 kDCDC_1P0StbyTarget0P65V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.65V. */
111 kDCDC_1P0StbyTarget0P675V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.675V. */
112
113 kDCDC_1P0StbyTarget0P7V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.7V. */
114 kDCDC_1P0StbyTarget0P725V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.725V. */
115 kDCDC_1P0StbyTarget0P75V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.75V. */
116 kDCDC_1P0StbyTarget0P775V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.775V. */
117
118 kDCDC_1P0StbyTarget0P8V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.8V. */
119 kDCDC_1P0StbyTarget0P825V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.825V. */
120 kDCDC_1P0StbyTarget0P85V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.85V. */
121 kDCDC_1P0StbyTarget0P875V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.875V. */
122
123 kDCDC_1P0StbyTarget0P9V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.9V. */
124 kDCDC_1P0StbyTarget0P925V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.925V. */
125 kDCDC_1P0StbyTarget0P95V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.95V. */
126 kDCDC_1P0StbyTarget0P975V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.975V. */
127
128 kDCDC_1P0StbyTarget1P0V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.0V. */
129 kDCDC_1P0StbyTarget1P025V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.025V. */
130 kDCDC_1P0StbyTarget1P05V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.05V. */
131 kDCDC_1P0StbyTarget1P075V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.075V. */
132
133 kDCDC_1P0StbyTarget1P1V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.1V. */
134 kDCDC_1P0StbyTarget1P125V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.125V. */
135 kDCDC_1P0StbyTarget1P15V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.15V. */
136 kDCDC_1P0StbyTarget1P175V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.175V. */
137
138 kDCDC_1P0StbyTarget1P2V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.2V. */
139 kDCDC_1P0StbyTarget1P225V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.225V. */
140 kDCDC_1P0StbyTarget1P25V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.25V. */
141 kDCDC_1P0StbyTarget1P275V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.275V. */
142
143 kDCDC_1P0StbyTarget1P3V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.3V. */
144 kDCDC_1P0StbyTarget1P325V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.325V. */
145 kDCDC_1P0StbyTarget1P35V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.35V. */
146 kDCDC_1P0StbyTarget1P375V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.375V. */
147
148 kDCDC_1P0StbyTarget1P4V = 0x1FU, /*!< In standby mode, The target voltage value of VDD1P0 is 1.4V */
149 } dcdc_standby_mode_1P0_target_vol_t;
150
151 /*!
152 * @brief The enumeration VDD1P8's target voltage value in standby mode.
153 */
154 typedef enum _dcdc_standby_mode_1P8_target_vol
155 {
156 kDCDC_1P8StbyTarget1P525V = 0U, /*!< In standby mode, the target voltage value of VDD1P8 is 1.525V. */
157 kDCDC_1P8StbyTarget1P55V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.55V. */
158 kDCDC_1P8StbyTarget1P575V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.575V. */
159
160 kDCDC_1P8StbyTarget1P6V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.6V. */
161 kDCDC_1P8StbyTarget1P625V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.625V. */
162 kDCDC_1P8StbyTarget1P65V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.65V. */
163 kDCDC_1P8StbyTarget1P675V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.675V. */
164
165 kDCDC_1P8StbyTarget1P7V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.7V. */
166 kDCDC_1P8StbyTarget1P725V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.725V. */
167 kDCDC_1P8StbyTarget1P75V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.75V. */
168 kDCDC_1P8StbyTarget1P775V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.775V. */
169
170 kDCDC_1P8StbyTarget1P8V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.8V. */
171 kDCDC_1P8StbyTarget1P825V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.825V. */
172 kDCDC_1P8StbyTarget1P85V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.85V. */
173 kDCDC_1P8StbyTarget1P875V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.875V. */
174
175 kDCDC_1P8StbyTarget1P9V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.9V. */
176 kDCDC_1P8StbyTarget1P925V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.925V. */
177 kDCDC_1P8StbyTarget1P95V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.95V. */
178 kDCDC_1P8StbyTarget1P975V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.975V. */
179
180 kDCDC_1P8StbyTarget2P0V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.0V. */
181 kDCDC_1P8StbyTarget2P025V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.025V. */
182 kDCDC_1P8StbyTarget2P05V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.05V. */
183 kDCDC_1P8StbyTarget2P075V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.075V. */
184
185 kDCDC_1P8StbyTarget2P1V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.1V. */
186 kDCDC_1P8StbyTarget2P125V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.125V. */
187 kDCDC_1P8StbyTarget2P15V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.15V. */
188 kDCDC_1P8StbyTarget2P175V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.175V. */
189
190 kDCDC_1P8StbyTarget2P2V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.2V. */
191 kDCDC_1P8StbyTarget2P225V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.225V. */
192 kDCDC_1P8StbyTarget2P25V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.25V. */
193 kDCDC_1P8StbyTarget2P275V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.275V. */
194
195 kDCDC_1P8StbyTarget2P3V = 0x1FU, /*!< In standby mode, the target voltage value is 2.3V. */
196 } dcdc_standby_mode_1P8_target_vol_t;
197
198 /*!
199 * @brief The enumeration VDD1P0's target voltage value in buck mode.
200 */
201 typedef enum _dcdc_buck_mode_1P0_target_vol
202 {
203 kDCDC_1P0BuckTarget0P6V = 0U, /*!< In buck mode, the target voltage value of VDD1P0 is 0.6V. */
204 kDCDC_1P0BuckTarget0P625V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.625V. */
205 kDCDC_1P0BuckTarget0P65V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.65V. */
206 kDCDC_1P0BuckTarget0P675V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.675V. */
207
208 kDCDC_1P0BuckTarget0P7V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.7V. */
209 kDCDC_1P0BuckTarget0P725V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.725V. */
210 kDCDC_1P0BuckTarget0P75V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.75V. */
211 kDCDC_1P0BuckTarget0P775V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.775V. */
212
213 kDCDC_1P0BuckTarget0P8V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.8V. */
214 kDCDC_1P0BuckTarget0P825V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.825V. */
215 kDCDC_1P0BuckTarget0P85V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.85V. */
216 kDCDC_1P0BuckTarget0P875V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.875V. */
217
218 kDCDC_1P0BuckTarget0P9V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.9V. */
219 kDCDC_1P0BuckTarget0P925V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.925V. */
220 kDCDC_1P0BuckTarget0P95V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.95V. */
221 kDCDC_1P0BuckTarget0P975V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.975V. */
222
223 kDCDC_1P0BuckTarget1P0V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.0V. */
224 kDCDC_1P0BuckTarget1P025V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.025V. */
225 kDCDC_1P0BuckTarget1P05V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.05V. */
226 kDCDC_1P0BuckTarget1P075V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.075V. */
227
228 kDCDC_1P0BuckTarget1P1V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.1V. */
229 kDCDC_1P0BuckTarget1P125V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.125V. */
230 kDCDC_1P0BuckTarget1P15V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.15V. */
231 kDCDC_1P0BuckTarget1P175V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.175V. */
232
233 kDCDC_1P0BuckTarget1P2V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.2V. */
234 kDCDC_1P0BuckTarget1P225V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.225V. */
235 kDCDC_1P0BuckTarget1P25V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.25V. */
236 kDCDC_1P0BuckTarget1P275V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.275V. */
237
238 kDCDC_1P0BuckTarget1P3V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.3V. */
239 kDCDC_1P0BuckTarget1P325V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.325V. */
240 kDCDC_1P0BuckTarget1P35V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.35V. */
241 kDCDC_1P0BuckTarget1P375V = 0x1FU, /*!< In buck mode, the target voltage value of VDD1P0 is 1.375V. */
242 } dcdc_buck_mode_1P0_target_vol_t;
243
244 /*!
245 * @brief The enumeration VDD1P8's target voltage value in buck mode.
246 */
247 typedef enum _dcdc_buck_mode_1P8_target_vol
248 {
249 kDCDC_1P8BuckTarget1P5V = 0U, /*!< In buck mode, the target voltage value of VDD1P0 is 1.5V. */
250 kDCDC_1P8BuckTarget1P525V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.525V. */
251 kDCDC_1P8BuckTarget1P55V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.55V. */
252 kDCDC_1P8BuckTarget1P575V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.575V. */
253
254 kDCDC_1P8BuckTarget1P6V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.6V. */
255 kDCDC_1P8BuckTarget1P625V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.625V. */
256 kDCDC_1P8BuckTarget1P65V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.65V. */
257 kDCDC_1P8BuckTarget1P675V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.675V. */
258
259 kDCDC_1P8BuckTarget1P7V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.7V. */
260 kDCDC_1P8BuckTarget1P725V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.725V. */
261 kDCDC_1P8BuckTarget1P75V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.75V. */
262 kDCDC_1P8BuckTarget1P775V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.775V. */
263
264 kDCDC_1P8BuckTarget1P8V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.8V. */
265 kDCDC_1P8BuckTarget1P825V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.825V. */
266 kDCDC_1P8BuckTarget1P85V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.85V. */
267 kDCDC_1P8BuckTarget1P875V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.875V. */
268
269 kDCDC_1P8BuckTarget1P9V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.9V. */
270 kDCDC_1P8BuckTarget1P925V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.925V. */
271 kDCDC_1P8BuckTarget1P95V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.95V. */
272 kDCDC_1P8BuckTarget1P975V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.975V. */
273
274 kDCDC_1P8BuckTarget2P0V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.0V. */
275 kDCDC_1P8BuckTarget2P025V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.025V. */
276 kDCDC_1P8BuckTarget2P05V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.05V. */
277 kDCDC_1P8BuckTarget2P075V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.075V. */
278
279 kDCDC_1P8BuckTarget2P1V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.1V. */
280 kDCDC_1P8BuckTarget2P125V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.125V. */
281 kDCDC_1P8BuckTarget2P15V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.15V. */
282 kDCDC_1P8BuckTarget2P175V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.175V. */
283
284 kDCDC_1P8BuckTarget2P2V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.2V. */
285 kDCDC_1P8BuckTarget2P225V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.225V. */
286 kDCDC_1P8BuckTarget2P25V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.25V. */
287 kDCDC_1P8BuckTarget2P275V = 0x1FU, /*!< In buck mode, the target voltage value of VDD1P0 is 2.275V. */
288 } dcdc_buck_mode_1P8_target_vol_t;
289
290 /*!
291 * @brief The current bias of low power comparator.
292 */
293 typedef enum _dcdc_comparator_current_bias
294 {
295 kDCDC_ComparatorCurrentBias50nA = 0U, /*!< The current bias of low power comparator is 50nA. */
296 kDCDC_ComparatorCurrentBias100nA = 1U, /*!< The current bias of low power comparator is 100nA. */
297 kDCDC_ComparatorCurrentBias200nA = 2U, /*!< The current bias of low power comparator is 200nA. */
298 kDCDC_ComparatorCurrentBias400nA = 3U, /*!< The current bias of low power comparator is 400nA. */
299 } dcdc_comparator_current_bias_t;
300
301 /*!
302 * @brief The threshold if peak current detection.
303 */
304 typedef enum _dcdc_peak_current_threshold
305 {
306 kDCDC_PeakCurrentRunMode250mALPMode1P5A = 0U, /*!< Over peak current threshold in low power mode is 250mA,
307 in run mode is 1.5A */
308 kDCDC_PeakCurrentRunMode200mALPMode1P5A, /*!< Over peak current threshold in low power mode is 200mA,
309 in run mode is 1.5A */
310 kDCDC_PeakCurrentRunMode250mALPMode2A, /*!< Over peak current threshold in low power mode is 250mA,
311 in run mode is 2A */
312 kDCDC_PeakCurrentRunMode200mALPMode2A, /*!< Over peak current threshold in low power mode is 200mA,
313 in run mode is 2A */
314 } dcdc_peak_current_threshold_t;
315
316 /*!
317 * @brief Oscillator clock option.
318 */
319 typedef enum _dcdc_clock_source
320 {
321 kDCDC_ClockAutoSwitch = 0U, /*!< Automatic clock switch from internal oscillator to external clock. */
322 kDCDC_ClockInternalOsc = 1U, /*!< Use internal oscillator. */
323 kDCDC_ClockExternalOsc = 2U, /*!< Use external 24M crystal oscillator. */
324 } dcdc_clock_source_t;
325
326 /*!
327 * @brief Voltage output option.
328 */
329 typedef enum _dcdc_voltage_output_sel
330 {
331 kDCDC_VoltageOutput1P8 = 0U, /*!< 1.8V output. */
332 kDCDC_VoltageOutput1P0 = 1U, /*!< 1.0V output. */
333 } dcdc_voltage_output_sel_t;
334
335 /*!
336 * @brief Configuration for DCDC.
337 */
338 typedef struct _dcdc_config
339 {
340 dcdc_control_mode_t controlMode; /*!< DCDC control mode. */
341 dcdc_trim_input_mode_t trimInputMode; /*!< Hold trim input. */
342 bool enableDcdcTimeout; /*!< Enable internal count for DCDC_OK timeout. */
343 bool enableSwitchingConverterOutput; /*!< Enable the VDDIO switching converter output.*/
344 } dcdc_config_t;
345
346 /*!
347 * @brief Configuration for min power setting.
348 */
349 typedef struct _dcdc_min_power_config
350 {
351 bool enableUseHalfFreqForContinuous; /*!< Set DCDC clock to half frequency for the continuous mode. */
352 } dcdc_min_power_config_t;
353
354 /*!
355 * @brief Configuration for DCDC detection.
356 */
357 typedef struct _dcdc_detection_config
358 {
359 bool enableXtalokDetection; /*!< Enable xtalok detection circuit. */
360 bool powerDownOverVoltageVdd1P8Detection; /*!< Power down over-voltage detection comparator for VDD1P8. */
361 bool powerDownOverVoltageVdd1P0Detection; /*!< Power down over-voltage detection comparator for VDD1P0. */
362 bool powerDownLowVoltageDetection; /*!< Power down low-voltage detection comparator. */
363 bool powerDownOverCurrentDetection; /*!< Power down over-current detection. */
364 bool powerDownPeakCurrentDetection; /*!< Power down peak-current detection. */
365 bool powerDownZeroCrossDetection; /*!< Power down the zero cross detection function for discontinuous conductor
366 mode. */
367 dcdc_peak_current_threshold_t PeakCurrentThreshold; /*!< The threshold of peak current detection. */
368 } dcdc_detection_config_t;
369
370 /*!
371 * @brief Configuration for the loop control.
372 */
373 typedef struct _dcdc_loop_control_config
374 {
375 bool enableCommonHysteresis; /*!< Enable hysteresis in switching converter common mode analog comparators.
376 This feature will improve transient supply ripple and efficiency. */
377 bool enableCommonThresholdDetection; /*!< Increase the threshold detection for common mode analog comparator. */
378 bool enableDifferentialHysteresis; /*!< Enable hysteresis in switching converter differential mode analog
379 comparators. This feature will improve transient supply ripple and
380 efficiency. */
381 bool enableDifferentialThresholdDetection; /*!< Increase the threshold detection for differential mode analog
382 comparators. */
383 bool enableInvertHysteresisSign; /*!< Invert the sign of the hysteresis in DC-DC analog comparators. */
384 bool enableRCThresholdDetection; /*!< Increase the threshold detection for RC scale circuit. */
385 uint32_t enableRCScaleCircuit; /*!< Available range is 0~7. Enable analog circuit of DC-DC converter to respond
386 faster under transient load conditions. */
387 uint32_t complementFeedForwardStep; /*!< Available range is 0~7. Two's complement feed forward step in duty cycle in
388 the switching DC-DC converter. Each time this field makes a transition from
389 0x0, the loop filter of the DC-DC converter is stepped once by a value
390 proportional to the change. This can be used to force a certain control loop
391 behavior, such as improving response under known heavy load transients. */
392 uint32_t controlParameterMagnitude; /*!< Available range is 0~15. Magnitude of proportional control parameter in the
393 switching DC-DC converter control loop. */
394 uint32_t integralProportionalRatio; /*!< Available range is 0~3.Ratio of integral control parameter to proportional
395 control parameter in the switching DC-DC converter, and can be used to
396 optimize efficiency and loop response. */
397 } dcdc_loop_control_config_t;
398
399 /*!
400 * @brief Configuration for DCDC internal regulator.
401 */
402 typedef struct _dcdc_internal_regulator_config
403 {
404 uint32_t feedbackPoint; /*!< Available range is 0~3. Select the feedback point of the internal regulator. */
405 } dcdc_internal_regulator_config_t;
406
407 /*!
408 * @brief Configuration for DCDC low power.
409 */
410 typedef struct _dcdc_low_power_config
411 {
412 bool enableAdjustHystereticValue; /*!< Adjust hysteretic value in low power from 12.5mV to 25mV. */
413 } dcdc_low_power_config_t;
414
415 /*!
416 * @brief DCDC configuration in set point mode.
417 */
418 typedef struct _dcdc_setpoint_config
419 {
420 uint32_t enableDCDCMap; /*!< The setpoint map that enable the DCDC module. Should be the OR'ed value of @ref
421 _dcdc_setpoint_map. */
422 uint32_t enableDigLogicMap; /*!< The setpoint map that enable the DCDC dig logic. Should be the OR'ed value of @ref
423 _dcdc_setpoint_map. */
424 uint32_t lowpowerMap; /*!< The setpoint map that enable the DCDC Low powermode. Should be the OR'ed value of @ref
425 _dcdc_setpoint_map. */
426 uint32_t standbyMap; /*!< The setpoint map that enable the DCDC standby mode. Should be the OR'ed value of @ref
427 _dcdc_setpoint_map. */
428 uint32_t standbyLowpowerMap; /*!< The setpoint map that enable the DCDC low power mode, when the related setpoint is
429 in standby mode. Please refer to @ref _dcdc_setpoint_map. */
430 dcdc_buck_mode_1P8_target_vol_t *buckVDD1P8TargetVoltage; /*!< Point to the array that store the target voltage
431 level of VDD1P8 in buck mode, please refer to
432 @ref dcdc_buck_mode_1P8_target_vol_t. Note that the
433 pointed array must have 16 elements. */
434 dcdc_buck_mode_1P0_target_vol_t *buckVDD1P0TargetVoltage; /*!< Point to the array that store the target voltage
435 level of VDD1P0 in buck mode, please refer to
436 @ref dcdc_buck_mode_1P0_target_vol_t. Note that the
437 pointed array must have 16 elements. */
438 dcdc_standby_mode_1P8_target_vol_t *standbyVDD1P8TargetVoltage; /*!< Point to the array that store the target
439 voltage level of VDD1P8 in standby mode, please
440 refer to @ref dcdc_standby_mode_1P8_target_vol_t.
441 Note that the pointed array must have 16 elements. */
442 dcdc_standby_mode_1P0_target_vol_t *standbyVDD1P0TargetVoltage; /*!< Point to the array that store the target
443 voltage level of VDD1P0 in standby mode, please
444 refer to @ref dcdc_standby_mode_1P0_target_vol_t.
445 Note that the pointed array must have 16 elements. */
446 } dcdc_setpoint_config_t;
447
448 /*******************************************************************************
449 * API
450 ******************************************************************************/
451 /*!
452 * @name Initialization and De-initialization Interfaces
453 * @{
454 */
455
456 /*!
457 * @brief Initializes the basic resource of DCDC module, such as control mode, etc.
458 *
459 * @param base DCDC peripheral base address.
460 * @param config Pointer to the @ref dcdc_config_t structure.
461 */
462 void DCDC_Init(DCDC_Type *base, const dcdc_config_t *config);
463
464 /*!
465 * @brief De-initializes the DCDC module.
466 *
467 * @param base DCDC peripheral base address.
468 */
469 void DCDC_Deinit(DCDC_Type *base);
470
471 /*!
472 * @brief Gets the default setting for DCDC, such as control mode, etc.
473 *
474 * This function initializes the user configuration structure to a default value. The default values are:
475 * @code
476 * config->controlMode = kDCDC_StaticControl;
477 * config->trimInputMode = kDCDC_SampleTrimInput;
478 * config->enableDcdcTimeout = false;
479 * config->enableSwitchingConverterOutput = false;
480 * @endcode
481 *
482 * @param config Pointer to configuration structure. See to @ref dcdc_config_t.
483 */
484 void DCDC_GetDefaultConfig(dcdc_config_t *config);
485
486 /*! @} */
487
488 /*!
489 * @name Power Mode Related Interfaces
490 * @{
491 */
492
493 /*!
494 * @brief Makes the DCDC enter into low power mode for GPC standby request or not.
495 *
496 * @param base DCDC peripheral base address.
497 * @param enable Used to control the behavior.
498 * - \b true Makes DCDC enter into low power mode for GPC standby mode.
499 */
DCDC_EnterLowPowerModeViaStandbyRequest(DCDC_Type * base,bool enable)500 static inline void DCDC_EnterLowPowerModeViaStandbyRequest(DCDC_Type *base, bool enable)
501 {
502 if (enable)
503 {
504 base->CTRL0 |= DCDC_CTRL0_STBY_LP_MODE_EN_MASK;
505 }
506 else
507 {
508 base->CTRL0 &= ~DCDC_CTRL0_STBY_LP_MODE_EN_MASK;
509 }
510 }
511
512 /*!
513 * @brief Makes DCDC enter into low power mode or not, before entering low power mode must disable stepping for VDD1P8
514 * and VDD1P0.
515 *
516 * @param base DCDC peripheral base address.
517 * @param enable Used to control the behavior.
518 * - \b true Makes DCDC enter into low power mode.
519 */
DCDC_EnterLowPowerMode(DCDC_Type * base,bool enable)520 static inline void DCDC_EnterLowPowerMode(DCDC_Type *base, bool enable)
521 {
522 if (enable)
523 {
524 base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK | DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
525 base->CTRL0 |= DCDC_CTRL0_LP_MODE_EN_MASK;
526 }
527 else
528 {
529 base->CTRL0 &= ~DCDC_CTRL0_LP_MODE_EN_MASK;
530 }
531 }
532
533 /*!
534 * @brief Makes DCDC enter into standby mode or not.
535 *
536 * @param base DCDC peripheral base address.
537 * @param enable Used to control the behavior.
538 * - \b true Makes DCDC enter into standby mode.
539 */
DCDC_EnterStandbyMode(DCDC_Type * base,bool enable)540 static inline void DCDC_EnterStandbyMode(DCDC_Type *base, bool enable)
541 {
542 if (enable)
543 {
544 base->CTRL0 |= DCDC_CTRL0_STBY_EN_MASK;
545 }
546 else
547 {
548 base->CTRL0 &= ~DCDC_CTRL0_STBY_EN_MASK;
549 }
550 }
551
552 /*! @} */
553
554 /*!
555 * @name Outputs' Target Voltage Related Interfaces
556 * @{
557 */
558
559 /*!
560 * @brief Sets the target value(ranges from 0.625V to 1.4V) of VDD1P0 in standby mode, 25mV each step.
561 *
562 * @param base DCDC peripheral base address.
563 * @param targetVoltage The target value of VDD1P0 in standby mode, see @ref dcdc_standby_mode_1P0_target_vol_t.
564 */
DCDC_SetVDD1P0StandbyModeTargetVoltage(DCDC_Type * base,dcdc_standby_mode_1P0_target_vol_t targetVoltage)565 static inline void DCDC_SetVDD1P0StandbyModeTargetVoltage(DCDC_Type *base,
566 dcdc_standby_mode_1P0_target_vol_t targetVoltage)
567 {
568 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
569 base->CTRL1 =
570 ((base->CTRL1) & (~DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(targetVoltage);
571 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
572 {
573 }
574 }
575
576 /*!
577 * @brief Gets the target value of VDD1P0 in standby mode, the result takes "mV" as the unit.
578 *
579 * @param base DCDC peripheral base address.
580 *
581 * @return The VDD1P0's voltage value in standby mode and the unit is "mV".
582 */
DCDC_GetVDD1P0StandbyModeTargetVoltage(DCDC_Type * base)583 static inline uint16_t DCDC_GetVDD1P0StandbyModeTargetVoltage(DCDC_Type *base)
584 {
585 const uint16_t vdd1P0TargetVoltage[] = STANDBY_MODE_VDD1P0_TARGET_VOLTAGE;
586 uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT;
587
588 return vdd1P0TargetVoltage[voltageValue];
589 }
590
591 /*!
592 * @brief Sets the target value(ranges from 1.525V to 2.3V) of VDD1P8 in standby mode, 25mV each step.
593 *
594 * @param base DCDC peripheral base address.
595 * @param targetVoltage The target value of VDD1P8 in standby mode, see @ref dcdc_standby_mode_1P8_target_vol_t.
596 */
DCDC_SetVDD1P8StandbyModeTargetVoltage(DCDC_Type * base,dcdc_standby_mode_1P8_target_vol_t targetVoltage)597 static inline void DCDC_SetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base,
598 dcdc_standby_mode_1P8_target_vol_t targetVoltage)
599 {
600 base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
601 base->CTRL1 =
602 ((base->CTRL1) & (~DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(targetVoltage);
603 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
604 {
605 }
606 }
607
608 /*!
609 * @brief Gets the target value of VDD1P8 in standby mode, the result takes "mV" as the unit.
610 *
611 * @param base DCDC peripheral base address.
612 *
613 * @return The VDD1P8's voltage value in standby mode and the unit is "mV".
614 */
DCDC_GetVDD1P8StandbyModeTargetVoltage(DCDC_Type * base)615 static inline uint16_t DCDC_GetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base)
616 {
617 const uint16_t vdd1P8TargetVoltage[] = STANDBY_MODE_VDD1P8_TARGET_VOLTAGE;
618 uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT;
619
620 return vdd1P8TargetVoltage[voltageValue];
621 }
622
623 /*!
624 * @brief Sets the target value(ranges from 0.6V to 1.375V) of VDD1P0 in buck mode, 25mV each step.
625 *
626 * @param base DCDC peripheral base address.
627 * @param targetVoltage The target value of VDD1P0 in buck mode, see @ref dcdc_buck_mode_1P0_target_vol_t.
628 */
DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC_Type * base,dcdc_buck_mode_1P0_target_vol_t targetVoltage)629 static inline void DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC_Type *base, dcdc_buck_mode_1P0_target_vol_t targetVoltage)
630 {
631 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
632 base->CTRL1 = ((base->CTRL1 & (~DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_TRG(targetVoltage));
633 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
634 {
635 }
636 }
637
638 /*!
639 * @brief Gets the target value of VDD1P0 in buck mode, the result takes "mV" as the unit.
640 *
641 * @param base DCDC peripheral base address.
642 *
643 * @return The VDD1P0's voltage value in buck mode and the unit is "mV".
644 */
DCDC_GetVDD1P0BuckModeTargetVoltage(DCDC_Type * base)645 static inline uint16_t DCDC_GetVDD1P0BuckModeTargetVoltage(DCDC_Type *base)
646 {
647 const uint16_t vdd1P0TargetVoltage[] = BUCK_MODE_VDD1P0_TARGET_VOLTAGE;
648 uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT;
649
650 return vdd1P0TargetVoltage[voltageValue];
651 }
652
653 /*!
654 * @brief Sets the target value(ranges from 1.5V to 2.275V) of VDD1P8 in buck mode, 25mV each step.
655 *
656 * @param base DCDC peripheral base address.
657 * @param targetVoltage The target value of VDD1P8 in buck mode, see @ref dcdc_buck_mode_1P8_target_vol_t.
658 */
DCDC_SetVDD1P8BuckModeTargetVoltage(DCDC_Type * base,dcdc_buck_mode_1P8_target_vol_t targetVoltage)659 static inline void DCDC_SetVDD1P8BuckModeTargetVoltage(DCDC_Type *base, dcdc_buck_mode_1P8_target_vol_t targetVoltage)
660 {
661 base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
662 base->CTRL1 = ((base->CTRL1 & (~DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P8CTRL_TRG(targetVoltage));
663 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0))
664 {
665 }
666 }
667
668 /*!
669 * @brief Gets the target value of VDD1P8 in buck mode, the result takes "mV" as the unit.
670 *
671 * @param base DCDC peripheral base address.
672 *
673 * @return The VDD1P8's voltage value in buck mode and the unit is "mV".
674 */
DCDC_GetVDD1P8BuckModeTargetVoltage(DCDC_Type * base)675 static inline uint16_t DCDC_GetVDD1P8BuckModeTargetVoltage(DCDC_Type *base)
676 {
677 const uint16_t vdd1P8TargetVoltage[] = BUCK_MODE_VDD1P8_TARGET_VOLTAGE;
678 uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT;
679
680 return vdd1P8TargetVoltage[voltageValue];
681 }
682
683 /*!
684 * @brief Enables/Disables stepping for VDD1P0, before entering low power modes the stepping for VDD1P0 must be
685 * disabled.
686 *
687 * @param base DCDC peripheral base address.
688 * @param enable Used to control the behavior.
689 * - \b true Enables stepping for VDD1P0.
690 * - \b false Disables stepping for VDD1P0.
691 */
DCDC_EnableVDD1P0TargetVoltageStepping(DCDC_Type * base,bool enable)692 static inline void DCDC_EnableVDD1P0TargetVoltageStepping(DCDC_Type *base, bool enable)
693 {
694 if (enable)
695 {
696 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
697 }
698 else
699 {
700 base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK;
701 }
702 }
703
704 /*!
705 * @brief Enables/Disables stepping for VDD1P8, before entering low power modes the stepping for VDD1P8 must be
706 * disabled.
707 *
708 * @param base DCDC peripheral base address.
709 * @param enable Used to control the behavior.
710 * - \b true Enables stepping for VDD1P8.
711 * - \b false Disables stepping for VDD1P8.
712 */
DCDC_EnableVDD1P8TargetVoltageStepping(DCDC_Type * base,bool enable)713 static inline void DCDC_EnableVDD1P8TargetVoltageStepping(DCDC_Type *base, bool enable)
714 {
715 if (enable)
716 {
717 base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
718 }
719 else
720 {
721 base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK;
722 }
723 }
724
725 /*! @} */
726
727 /*!
728 * @name Detection Related Inferfaces
729 * @{
730 */
731
732 /*!
733 * @brief Gets the default setting for detection configuration.
734 *
735 * The default configuration are set according to responding registers' setting when powered on.
736 * They are:
737 * @code
738 * config->enableXtalokDetection = false;
739 * config->powerDownOverVoltageVdd1P8Detection = true;
740 * config->powerDownOverVoltageVdd1P0Detection = true;
741 * config->powerDownLowVoltageDetection = false;
742 * config->powerDownOverCurrentDetection = true;
743 * config->powerDownPeakCurrentDetection = true;
744 * config->powerDownZeroCrossDetection = true;
745 * config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
746 * config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
747 * @endcode
748 *
749 * @param config Pointer to configuration structure. See to @ref dcdc_detection_config_t.
750 */
751 void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config);
752
753 /*!
754 * @brief Configures the DCDC detection.
755 *
756 * @param base DCDC peripheral base address.
757 * @param config Pointer to configuration structure. See to @ref dcdc_detection_config_t.
758 */
759 void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config);
760
761 /*! @} */
762
763 /*!
764 * @name DCDC Miscellaneous Inferfaces
765 * @{
766 */
767
768 /*!
769 * @brief Enables/Disables the output range comparator.
770 *
771 * The output range comparator is disabled by default.
772 *
773 * @param base DCDC peripheral base address.
774 * @param enable Enable the feature or not.
775 * - \b true Enable the output range comparator.
776 * - \b false Disable the output range comparator.
777 */
DCDC_EnableOutputRangeComparator(DCDC_Type * base,bool enable)778 static inline void DCDC_EnableOutputRangeComparator(DCDC_Type *base, bool enable)
779 {
780 if (enable)
781 {
782 base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK;
783 }
784 else
785 {
786 base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK;
787 }
788 }
789
790 /*!
791 * @brief Configures the DCDC clock source.
792 *
793 * @param base DCDC peripheral base address.
794 * @param clockSource Clock source for DCDC. See to @ref dcdc_clock_source_t.
795 */
796 void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource);
797
798 /*!
799 * @brief Gets the default setting for low power configuration.
800 *
801 * The default configuration are set according to responding registers' setting when powered on.
802 * They are:
803 * @code
804 * config->enableAdjustHystereticValue = false;
805 * @endcode
806 *
807 * @param config Pointer to configuration structure. See to @ref dcdc_low_power_config_t.
808 */
809 void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config);
810
811 /*!
812 * @brief Configures the DCDC low power.
813 *
814 * @param base DCDC peripheral base address.
815 * @param config Pointer to configuration structure. See to @ref dcdc_low_power_config_t.
816 */
817 void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config);
818
819 /*!
820 * @brief Sets the bangap trim value(0~31) to trim bandgap voltage.
821 *
822 * @param base DCDC peripheral base address.
823 * @param trimValue The bangap trim value. Available range is 0U-31U.
824 */
DCDC_SetBandgapVoltageTrimValue(DCDC_Type * base,uint32_t trimValue)825 static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue)
826 {
827 base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK;
828 base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue);
829 }
830
831 /*!
832 * @brief Gets the default setting for loop control configuration.
833 *
834 * The default configuration are set according to responding registers' setting when powered on.
835 * They are:
836 * @code
837 * config->enableCommonHysteresis = false;
838 * config->enableCommonThresholdDetection = false;
839 * config->enableInvertHysteresisSign = false;
840 * config->enableRCThresholdDetection = false;
841 * config->enableRCScaleCircuit = 0U;
842 * config->complementFeedForwardStep = 0U;
843 * config->controlParameterMagnitude = 2U;
844 * config->integralProportionalRatio = 2U;
845 * @endcode
846 *
847 * @param config Pointer to configuration structure. See to @ref dcdc_loop_control_config_t.
848 */
849 void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config);
850
851 /*!
852 * @brief Configures the DCDC loop control.
853 *
854 * @param base DCDC peripheral base address.
855 * @param config Pointer to configuration structure. See to @ref dcdc_loop_control_config_t.
856 */
857 void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config);
858
859 /*!
860 * @brief Configures for the min power.
861 *
862 * @param base DCDC peripheral base address.
863 * @param config Pointer to configuration structure. See to @ref dcdc_min_power_config_t.
864 */
865 void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config);
866
867 /*!
868 * @brief Sets the current bias of low power comparator.
869 *
870 * @param base DCDC peripheral base address.
871 * @param biasValue The current bias of low power comparator. Refer to @ref dcdc_comparator_current_bias_t.
872 */
DCDC_SetLPComparatorBiasValue(DCDC_Type * base,dcdc_comparator_current_bias_t biasValue)873 static inline void DCDC_SetLPComparatorBiasValue(DCDC_Type *base, dcdc_comparator_current_bias_t biasValue)
874 {
875 base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK;
876 base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasValue);
877 }
878
879 /*!
880 * @brief Configures the DCDC internal regulator.
881 *
882 * @param base DCDC peripheral base address.
883 * @param config Pointer to configuration structure. See to @ref dcdc_internal_regulator_config_t.
884 */
885 void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config);
886
887 /*!
888 * @brief Adjusts delay to reduce ground noise.
889 *
890 * @param base DCDC peripheral base address.
891 * @param enable Enable the feature or not.
892 */
DCDC_EnableAdjustDelay(DCDC_Type * base,bool enable)893 static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable)
894 {
895 if (enable)
896 {
897 base->REG3 |= DCDC_REG3_MISC_DELAY_TIMING_MASK;
898 }
899 else
900 {
901 base->REG3 &= ~DCDC_REG3_MISC_DELAY_TIMING_MASK;
902 }
903 }
904
905 /*!
906 * @brief Enables/Disables to improve the transition from heavy load to light load.
907 *
908 * @note It is valid while zero cross detection is enabled. If ouput exceeds the threshold, DCDC would return CCM from
909 * DCM.
910 *
911 * @param base DCDC peripheral base address.
912 * @param enable Enable the feature or not.
913 */
DCDC_EnableImproveTransition(DCDC_Type * base,bool enable)914 static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable)
915 {
916 if (enable)
917 {
918 base->REG2 |= DCDC_REG2_DCM_SET_CTRL_MASK;
919 }
920 else
921 {
922 base->REG2 &= ~DCDC_REG2_DCM_SET_CTRL_MASK;
923 }
924 }
925 /*! @} */
926
927 /*!
928 * @name Setpoint Control Related Interfaces
929 */
930
931 /*!
932 * @brief Initializes DCDC module when the control mode selected as setpoint mode.
933 *
934 * @note The function should be invoked in the initial step to config the
935 * DCDC via setpoint control mode.
936 *
937 * @param base DCDC peripheral base address.
938 * @param config The pointer to the structure @ref dcdc_setpoint_config_t.
939 */
940 void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config);
941
942 /*!
943 * @brief Disable DCDC module when the control mode selected as setpoint mode.
944 *
945 * @param base DCDC peripheral base address.
946 * @param setpointMap The map of the setpoint to disable the DCDC module,
947 * Should be the OR'ed value of _dcdc_setpoint_map.
948 */
DCDC_SetPointDeinit(DCDC_Type * base,uint32_t setpointMap)949 static inline void DCDC_SetPointDeinit(DCDC_Type *base, uint32_t setpointMap)
950 {
951 base->REG4 &= ~setpointMap;
952 }
953
954 /*! @} */
955
956 /*!
957 * @name DCDC Status Related Interfaces
958 * @{
959 */
960
961 /*!
962 * @brief Get DCDC status flags.
963 *
964 * @param base peripheral base address.
965 * @return Mask of asserted status flags. See to @ref _dcdc_status_flags.
966 */
DCDC_GetStatusFlags(DCDC_Type * base)967 static inline uint32_t DCDC_GetStatusFlags(DCDC_Type *base)
968 {
969 return (base->REG0 & DCDC_REG0_STS_DC_OK_MASK);
970 }
971
972 /* @} */
973
974 /*!
975 * @name Application Guideline Interfaces
976 * @{
977 */
978
979 /*!
980 * @brief Boots DCDC into DCM(discontinous conduction mode).
981 *
982 * @code
983 * pwd_zcd=0x0;
984 * DM_CTRL = 1'b1;
985 * pwd_cmp_offset=0x0;
986 * dcdc_loopctrl_en_rcscale=0x3 or 0x5;
987 * DCM_set_ctrl=1'b1;
988 * @endcode
989 *
990 * @param base DCDC peripheral base address.
991 */
992 void DCDC_BootIntoDCM(DCDC_Type *base);
993
994 /*!
995 * @brief Boots DCDC into CCM(continous conduction mode).
996 *
997 * @code
998 * pwd_zcd=0x1;
999 * pwd_cmp_offset=0x0;
1000 * dcdc_loopctrl_en_rcscale=0x3;
1001 * @endcode
1002 *
1003 * @param base DCDC peripheral base address.
1004 */
1005 void DCDC_BootIntoCCM(DCDC_Type *base);
1006
1007 /*! @} */
1008
1009 /*!
1010 * @}
1011 */
1012
1013 #endif /* __FSL_DCDC_H__ */
1014
