1 /*
2  * Copyright 2019-2023 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10 
11 #include "fsl_common.h"
12 
13 /*! @addtogroup clock */
14 /*! @{ */
15 
16 /*! @file */
17 
18 /*******************************************************************************
19  * Configurations
20  ******************************************************************************/
21 
22 /*! @brief Configure whether driver controls clock
23  *
24  * When set to 0, peripheral drivers will enable clock in initialize function
25  * and disable clock in de-initialize function. When set to 1, peripheral
26  * driver will not control the clock, application could control the clock out of
27  * the driver.
28  *
29  * @note All drivers share this feature switcher. If it is set to 1, application
30  * should handle clock enable and disable for all drivers.
31  */
32 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
33 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
34 #endif
35 
36 /*******************************************************************************
37  * Definitions
38  ******************************************************************************/
39 
40 /*! @name Driver version */
41 /*@{*/
42 /*! @brief CLOCK driver version. */
43 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
44 
45 /* Definition for delay API in clock driver, users can redefine it to the real application. */
46 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
47 #if __CORTEX_M == 7
48 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
49 #else
50 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (240000000UL)
51 #endif
52 #endif
53 
54 /*@}*/
55 
56 /*!
57  * @brief CCM registers offset.
58  */
59 #define CCSR_OFFSET   0x0C
60 #define CBCDR_OFFSET  0x14
61 #define CBCMR_OFFSET  0x18
62 #define CSCMR1_OFFSET 0x1C
63 #define CSCMR2_OFFSET 0x20
64 #define CSCDR1_OFFSET 0x24
65 #define CDCDR_OFFSET  0x30
66 #define CSCDR2_OFFSET 0x38
67 #define CSCDR3_OFFSET 0x3C
68 #define CACRR_OFFSET  0x10
69 #define CS1CDR_OFFSET 0x28
70 #define CS2CDR_OFFSET 0x2C
71 
72 /*!
73  * @brief CCM Analog registers offset.
74  */
75 #define ARM_PLL_OFFSET   0x00
76 #define PLL_SYS_OFFSET   0x30
77 #define PLL_USB1_OFFSET  0x10
78 #define PLL_AUDIO_OFFSET 0x70
79 #define PLL_VIDEO_OFFSET 0xA0
80 #define PLL_ENET_OFFSET  0xE0
81 #define PLL_USB2_OFFSET  0x20
82 
83 #define CCM_TUPLE(reg, shift, mask, busyShift) \
84     (int)((reg & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
85 #define CCM_TUPLE_REG(base, tuple)  (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU))))
86 #define CCM_TUPLE_SHIFT(tuple)      (((tuple) >> 8U) & 0x1FU)
87 #define CCM_TUPLE_MASK(tuple)       ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))
88 #define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU)
89 
90 #define CCM_BUSY_WAIT (0x20U)
91 
92 /*!
93  * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
94  */
95 #define CCM_ANALOG_TUPLE(reg, shift)  (((reg & 0xFFFU) << 16U) | (shift))
96 #define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)
97 #define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
98     (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off)))
99 #define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
100 
101 /*!
102  * @brief SYS_PLL_FREQ frequency in Hz.
103  */
104 #define SYS_PLL1_FREQ (1000000000UL)
105 #define SYS_PLL2_MFI  (22UL)
106 #define SYS_PLL2_FREQ (XTAL_FREQ * SYS_PLL2_MFI)
107 #define SYS_PLL3_MFI  (20UL)
108 #define SYS_PLL3_FREQ (XTAL_FREQ * SYS_PLL3_MFI)
109 #define XTAL_FREQ     (24000000UL)
110 
111 /*! @brief Clock gate name array for ADC. */
112 #define LPADC_CLOCKS                                   \
113     {                                                  \
114         kCLOCK_IpInvalid, kCLOCK_Lpadc1, kCLOCK_Lpadc2 \
115     }
116 
117 /*! @brief Clock gate name array for ADC. */
118 #define ADC_ETC_CLOCKS \
119     {                  \
120         kCLOCK_Adc_Etc \
121     }
122 
123 /*! @brief Clock gate name array for AOI. */
124 #define AOI_CLOCKS                                 \
125     {                                              \
126         kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
127     }
128 
129 /*! @brief Clock gate name array for DCDC. */
130 #define DCDC_CLOCKS \
131     {               \
132         kCLOCK_Dcdc \
133     }
134 
135 /*! @brief Clock gate name array for SRC. */
136 #define SRC_CLOCKS \
137     {              \
138         kCLOCK_Src \
139     }
140 
141 /*! @brief Clock gate name array for GPC. */
142 #define GPC_CLOCKS \
143     {              \
144         kCLOCK_Gpc \
145     }
146 
147 /*! @brief Clock gate name array for SSARC. */
148 #define SSARC_CLOCKS \
149     {                \
150         kCLOCK_Ssarc \
151     }
152 
153 /*! @brief Clock gate name array for WDOG. */
154 #define WDOG_CLOCKS                                                              \
155     {                                                                            \
156         kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3, kCLOCK_Wdog4 \
157     }
158 
159 /*! @brief Clock gate name array for EWM. */
160 #define EWM_CLOCKS  \
161     {               \
162         kCLOCK_Ewm0 \
163     }
164 
165 /*! @brief Clock gate name array for Sema. */
166 #define SEMA_CLOCKS \
167     {               \
168         kCLOCK_Sema \
169     }
170 
171 /*! @brief Clock gate name array for MU. */
172 #if (__CORTEX_M == 7)
173 #define MU_CLOCKS   \
174     {               \
175         kCLOCK_Mu_A \
176     }
177 #else
178 #define MU_CLOCKS   \
179     {               \
180         kCLOCK_Mu_B \
181     }
182 #endif
183 
184 /*! @brief Clock gate name array for EDMA. */
185 #define EDMA_CLOCKS                   \
186     {                                 \
187         kCLOCK_Edma, kCLOCK_Edma_Lpsr \
188     }
189 
190 /*! @brief Clock gate name array for FLEXRAM. */
191 #define FLEXRAM_CLOCKS \
192     {                  \
193         kCLOCK_Flexram \
194     }
195 
196 /*! @brief Clock gate name array for LMEM. */
197 #define LMEM_CLOCKS \
198     {               \
199         kCLOCK_Lmem \
200     }
201 
202 /*! @brief Clock gate name array for FLEXSPI. */
203 #define FLEXSPI_CLOCKS                                     \
204     {                                                      \
205         kCLOCK_IpInvalid, kCLOCK_Flexspi1, kCLOCK_Flexspi2 \
206     }
207 
208 /*! @brief Clock gate name array for RDC. */
209 #define RDC_CLOCKS                                 \
210     {                                              \
211         kCLOCK_Rdc, kCLOCK_M7_Xrdc, kCLOCK_M4_Xrdc \
212     }
213 
214 /*! @brief Clock ip name array for DCDC. */
215 #define DCDC_CLOCKS \
216     {               \
217         kCLOCK_Dcdc \
218     }
219 
220 /*! @brief Clock ip name array for SEMC. */
221 #define SEMC_CLOCKS \
222     {               \
223         kCLOCK_Semc \
224     }
225 
226 /*! @brief Clock ip name array for XECC. */
227 #define XECC_CLOCKS \
228     {               \
229         kCLOCK_Xecc \
230     }
231 
232 /*! @brief Clock ip name array for IEE. */
233 #define IEE_CLOCKS \
234     {              \
235         kCLOCK_Iee \
236     }
237 
238 /*! @brief Clock ip name array for KEY_MANAGER. */
239 #define KEYMANAGER_CLOCKS  \
240     {                      \
241         kCLOCK_Key_Manager \
242     }
243 
244 /*! @brief Clock ip name array for PUF. */
245 #define PUF_CLOCKS \
246     {              \
247         kCLOCK_Puf \
248     }
249 
250 /*! @brief Clock ip name array for OCOTP. */
251 #define OCOTP_CLOCKS \
252     {                \
253         kCLOCK_Ocotp \
254     }
255 
256 /*! @brief Clock ip name array for CAAM. */
257 #define CAAM_CLOCKS \
258     {               \
259         kCLOCK_Caam \
260     }
261 
262 /*! @brief Clock ip name array for XBAR. */
263 #define XBAR_CLOCKS                                                \
264     {                                                              \
265         kCLOCK_IpInvalid, kCLOCK_Xbar1, kCLOCK_Xbar2, kCLOCK_Xbar3 \
266     }
267 
268 /*! @brief Clock ip name array for IOMUXC. */
269 #define IOMUXC_CLOCKS                     \
270     {                                     \
271         kCLOCK_Iomuxc, kCLOCK_Iomuxc_Lpsr \
272     }
273 
274 /*! @brief Clock ip name array for GPIO. */
275 #define GPIO_CLOCKS                                                                                                  \
276     {                                                                                                                \
277         kCLOCK_IpInvalid, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, \
278             kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio,                            \
279     }
280 
281 /*! @brief Clock ip name array for KPP. */
282 #define KPP_CLOCKS \
283     {              \
284         kCLOCK_Kpp \
285     }
286 
287 /*! @brief Clock ip name array for FLEXIO. */
288 #define FLEXIO_CLOCKS                                    \
289     {                                                    \
290         kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \
291     }
292 
293 /*! @brief Clock ip name array for DAC. */
294 #define DAC_CLOCKS \
295     {              \
296         kCLOCK_Dac \
297     }
298 
299 /*! @brief Clock ip name array for CMP. */
300 #define CMP_CLOCKS                                                               \
301     {                                                                            \
302         kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
303     }
304 
305 /*! @brief Clock ip name array for PIT. */
306 #define PIT_CLOCKS                                 \
307     {                                              \
308         kCLOCK_IpInvalid, kCLOCK_Pit1, kCLOCK_Pit2 \
309     }
310 
311 /*! @brief Clock ip name array for GPT. */
312 #define GPT_CLOCKS                                                                                     \
313     {                                                                                                  \
314         kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6 \
315     }
316 
317 /*! @brief Clock ip name array for QTIMER. */
318 #define TMR_CLOCKS                                                                       \
319     {                                                                                    \
320         kCLOCK_IpInvalid, kCLOCK_Qtimer1, kCLOCK_Qtimer2, kCLOCK_Qtimer3, kCLOCK_Qtimer4 \
321     }
322 
323 /*! @brief Clock ip name array for ENC. */
324 #define ENC_CLOCKS                                                           \
325     {                                                                        \
326         kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
327     }
328 
329 /*! @brief Clock ip name array for PWM. */
330 #define PWM_CLOCKS                                                                \
331     {                                                                             \
332         {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
333             {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1},                 \
334             {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2},                 \
335             {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3},                 \
336         {                                                                         \
337             kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4                    \
338         }                                                                         \
339     }
340 
341 /*! @brief Clock ip name array for FLEXCAN. */
342 #define FLEXCAN_CLOCKS                                          \
343     {                                                           \
344         kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \
345     }
346 
347 /*! @brief Clock ip name array for LPUART. */
348 #define LPUART_CLOCKS                                                                                         \
349     {                                                                                                         \
350         kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5,     \
351             kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8, kCLOCK_Lpuart9, kCLOCK_Lpuart10, kCLOCK_Lpuart11, \
352             kCLOCK_Lpuart12                                                                                   \
353     }
354 
355 /*! @brief Clock ip name array for LPI2C. */
356 #define LPI2C_CLOCKS                                                                                               \
357     {                                                                                                              \
358         kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4, kCLOCK_Lpi2c5, kCLOCK_Lpi2c6 \
359     }
360 
361 /*! @brief Clock ip name array for LPSPI. */
362 #define LPSPI_CLOCKS                                                                                               \
363     {                                                                                                              \
364         kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4, kCLOCK_Lpspi5, kCLOCK_Lpspi6 \
365     }
366 
367 /*! @brief Clock ip name array for EMVSIM. */
368 #define EMVSIM_CLOCKS                              \
369     {                                              \
370         kCLOCK_IpInvalid, kCLOCK_Sim1, kCLOCK_Sim2 \
371     }
372 
373 /*! @brief Clock ip name array for ENET. */
374 #define ENET_CLOCKS                 \
375     {                               \
376         kCLOCK_Enet, kCLOCK_Enet_1g \
377     }
378 
379 /*! @brief Clock ip name array for USB. */
380 #define USB_CLOCKS \
381     {              \
382         kCLOCK_Usb \
383     }
384 
385 /*! @brief Clock ip name array for CDOG. */
386 #define CDOG_CLOCKS \
387     {               \
388         kCLOCK_Cdog \
389     }
390 
391 /*! @brief Clock ip name array for USDHC. */
392 #define USDHC_CLOCKS                                   \
393     {                                                  \
394         kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
395     }
396 
397 /*! @brief Clock ip name array for ASRC. */
398 #define ASRC_CLOCKS \
399     {               \
400         kCLOCK_Asrc \
401     }
402 
403 /*! @brief Clock ip name array for MQS. */
404 #define MQS_CLOCKS \
405     {              \
406         kCLOCK_Mqs \
407     }
408 
409 /*! @brief Clock ip name array for PDM. */
410 #define PDM_CLOCKS \
411     {              \
412         kCLOCK_Pdm \
413     }
414 
415 /*! @brief Clock ip name array for SPDIF. */
416 #define SPDIF_CLOCKS \
417     {                \
418         kCLOCK_Spdif \
419     }
420 
421 /*! @brief Clock ip name array for SAI. */
422 #define SAI_CLOCKS                                                           \
423     {                                                                        \
424         kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4 \
425     }
426 
427 /*! @brief Clock ip name array for PXP. */
428 #define PXP_CLOCKS \
429     {              \
430         kCLOCK_Pxp \
431     }
432 
433 /*! @brief Clock ip name array for GPU2d. */
434 #define GPU2D_CLOCKS \
435     {                \
436         kCLOCK_Gpu2d \
437     }
438 
439 /*! @brief Clock ip name array for LCDIF. */
440 #define LCDIF_CLOCKS \
441     {                \
442         kCLOCK_Lcdif \
443     }
444 
445 /*! @brief Clock ip name array for LCDIFV2. */
446 #define LCDIFV2_CLOCKS \
447     {                  \
448         kCLOCK_Lcdifv2 \
449     }
450 
451 /*! @brief Clock ip name array for MIPI_DSI. */
452 #define MIPI_DSI_HOST_CLOCKS \
453     {                        \
454         kCLOCK_Mipi_Dsi      \
455     }
456 
457 /*! @brief Clock ip name array for MIPI_CSI. */
458 #define MIPI_CSI2RX_CLOCKS \
459     {                      \
460         kCLOCK_Mipi_Csi    \
461     }
462 
463 /*! @brief Clock ip name array for CSI. */
464 #define CSI_CLOCKS \
465     {              \
466         kCLOCK_Csi \
467     }
468 
469 /*! @brief Clock ip name array for DCIC. */
470 #define DCIC_CLOCKS                                         \
471     {                                                       \
472         kCLOCK_IpInvalid, kCLOCK_Dcic_Mipi, kCLOCK_Dcic_Lcd \
473     }
474 
475 /*! @brief Clock ip name array for DMAMUX_CLOCKS. */
476 #define DMAMUX_CLOCKS                 \
477     {                                 \
478         kCLOCK_Edma, kCLOCK_Edma_Lpsr \
479     }
480 
481 /*! @brief Clock ip name array for XBARA. */
482 #define XBARA_CLOCKS                   \
483     {                                  \
484         kCLOCK_IpInvalid, kCLOCK_Xbar1 \
485     }
486 
487 /*! @brief Clock ip name array for XBARB. */
488 #define XBARB_CLOCKS                                                   \
489     {                                                                  \
490         kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
491     }
492 
493 /*!
494  * @brief Clock LPCG index
495  */
496 typedef enum _clock_lpcg
497 {
498     kCLOCK_M7          = 0,   /*!< Clock LPCG M7. */
499     kCLOCK_M4          = 1,   /*!< Clock LPCG M4. */
500     kCLOCK_Sim_M7      = 2,   /*!< Clock LPCG SIM M7. */
501     kCLOCK_Sim_M       = 3,   /*!< Clock LPCG SIM M4. */
502     kCLOCK_Sim_Disp    = 4,   /*!< Clock LPCG SIM DISP. */
503     kCLOCK_Sim_Per     = 5,   /*!< Clock LPCG SIM PER. */
504     kCLOCK_Sim_Lpsr    = 6,   /*!< Clock LPCG SIM LPSR. */
505     kCLOCK_Anadig      = 7,   /*!< Clock LPCG Anadig. */
506     kCLOCK_Dcdc        = 8,   /*!< Clock LPCG DCDC. */
507     kCLOCK_Src         = 9,   /*!< Clock LPCG SRC. */
508     kCLOCK_Ccm         = 10,  /*!< Clock LPCG CCM. */
509     kCLOCK_Gpc         = 11,  /*!< Clock LPCG GPC. */
510     kCLOCK_Ssarc       = 12,  /*!< Clock LPCG SSARC. */
511     kCLOCK_Sim_R       = 13,  /*!< Clock LPCG SIM_R. */
512     kCLOCK_Wdog1       = 14,  /*!< Clock LPCG WDOG1. */
513     kCLOCK_Wdog2       = 15,  /*!< Clock LPCG WDOG2. */
514     kCLOCK_Wdog3       = 16,  /*!< Clock LPCG WDOG3. */
515     kCLOCK_Wdog4       = 17,  /*!< Clock LPCG WDOG4. */
516     kCLOCK_Ewm0        = 18,  /*!< Clock LPCG EWM0. */
517     kCLOCK_Sema        = 19,  /*!< Clock LPCG SEMA. */
518     kCLOCK_Mu_A        = 20,  /*!< Clock LPCG MU_A. */
519     kCLOCK_Mu_B        = 21,  /*!< Clock LPCG MU_B. */
520     kCLOCK_Edma        = 22,  /*!< Clock LPCG EDMA. */
521     kCLOCK_Edma_Lpsr   = 23,  /*!< Clock LPCG EDMA_LPSR. */
522     kCLOCK_Romcp       = 24,  /*!< Clock LPCG ROMCP. */
523     kCLOCK_Ocram       = 25,  /*!< Clock LPCG OCRAM. */
524     kCLOCK_Flexram     = 26,  /*!< Clock LPCG FLEXRAM. */
525     kCLOCK_Lmem        = 27,  /*!< Clock LPCG Lmem. */
526     kCLOCK_Flexspi1    = 28,  /*!< Clock LPCG Flexspi1. */
527     kCLOCK_Flexspi2    = 29,  /*!< Clock LPCG Flexspi2. */
528     kCLOCK_Rdc         = 30,  /*!< Clock LPCG RDC. */
529     kCLOCK_M7_Xrdc     = 31,  /*!< Clock LPCG M7 XRDC. */
530     kCLOCK_M4_Xrdc     = 32,  /*!< Clock LPCG M4 XRDC. */
531     kCLOCK_Semc        = 33,  /*!< Clock LPCG SEMC. */
532     kCLOCK_Xecc        = 34,  /*!< Clock LPCG XECC. */
533     kCLOCK_Iee         = 35,  /*!< Clock LPCG IEE. */
534     kCLOCK_Key_Manager = 36,  /*!< Clock LPCG KEY_MANAGER. */
535     kCLOCK_Puf         = 36,  /*!< Clock LPCG PUF. */
536     kCLOCK_Ocotp       = 37,  /*!< Clock LPCG OSOTP. */
537     kCLOCK_Snvs_Hp     = 38,  /*!< Clock LPCG SNVS_HP. */
538     kCLOCK_Snvs        = 39,  /*!< Clock LPCG SNVS. */
539     kCLOCK_Caam        = 40,  /*!< Clock LPCG Caam. */
540     kCLOCK_Jtag_Mux    = 41,  /*!< Clock LPCG JTAG_MUX. */
541     kCLOCK_Cstrace     = 42,  /*!< Clock LPCG CSTRACE. */
542     kCLOCK_Xbar1       = 43,  /*!< Clock LPCG XBAR1. */
543     kCLOCK_Xbar2       = 44,  /*!< Clock LPCG XBAR2. */
544     kCLOCK_Xbar3       = 45,  /*!< Clock LPCG XBAR3. */
545     kCLOCK_Aoi1        = 46,  /*!< Clock LPCG AOI1. */
546     kCLOCK_Aoi2        = 47,  /*!< Clock LPCG AOI2. */
547     kCLOCK_Adc_Etc     = 48,  /*!< Clock LPCG ADC_ETC. */
548     kCLOCK_Iomuxc      = 49,  /*!< Clock LPCG IOMUXC. */
549     kCLOCK_Iomuxc_Lpsr = 50,  /*!< Clock LPCG IOMUXC_LPSR. */
550     kCLOCK_Gpio        = 51,  /*!< Clock LPCG GPIO. */
551     kCLOCK_Kpp         = 52,  /*!< Clock LPCG KPP. */
552     kCLOCK_Flexio1     = 53,  /*!< Clock LPCG FLEXIO1. */
553     kCLOCK_Flexio2     = 54,  /*!< Clock LPCG FLEXIO2. */
554     kCLOCK_Lpadc1      = 55,  /*!< Clock LPCG LPADC1. */
555     kCLOCK_Lpadc2      = 56,  /*!< Clock LPCG LPADC2. */
556     kCLOCK_Dac         = 57,  /*!< Clock LPCG DAC. */
557     kCLOCK_Acmp1       = 58,  /*!< Clock LPCG ACMP1. */
558     kCLOCK_Acmp2       = 59,  /*!< Clock LPCG ACMP2. */
559     kCLOCK_Acmp3       = 60,  /*!< Clock LPCG ACMP3. */
560     kCLOCK_Acmp4       = 61,  /*!< Clock LPCG ACMP4. */
561     kCLOCK_Pit1        = 62,  /*!< Clock LPCG PIT1. */
562     kCLOCK_Pit2        = 63,  /*!< Clock LPCG PIT2. */
563     kCLOCK_Gpt1        = 64,  /*!< Clock LPCG GPT1. */
564     kCLOCK_Gpt2        = 65,  /*!< Clock LPCG GPT2. */
565     kCLOCK_Gpt3        = 66,  /*!< Clock LPCG GPT3. */
566     kCLOCK_Gpt4        = 67,  /*!< Clock LPCG GPT4. */
567     kCLOCK_Gpt5        = 68,  /*!< Clock LPCG GPT5. */
568     kCLOCK_Gpt6        = 69,  /*!< Clock LPCG GPT6. */
569     kCLOCK_Qtimer1     = 70,  /*!< Clock LPCG QTIMER1. */
570     kCLOCK_Qtimer2     = 71,  /*!< Clock LPCG QTIMER2. */
571     kCLOCK_Qtimer3     = 72,  /*!< Clock LPCG QTIMER3. */
572     kCLOCK_Qtimer4     = 73,  /*!< Clock LPCG QTIMER4. */
573     kCLOCK_Enc1        = 74,  /*!< Clock LPCG Enc1. */
574     kCLOCK_Enc2        = 75,  /*!< Clock LPCG Enc2. */
575     kCLOCK_Enc3        = 76,  /*!< Clock LPCG Enc3. */
576     kCLOCK_Enc4        = 77,  /*!< Clock LPCG Enc4. */
577     kCLOCK_Hrtimer     = 78,  /*!< Clock LPCG Hrtimer. */
578     kCLOCK_Pwm1        = 79,  /*!< Clock LPCG PWM1. */
579     kCLOCK_Pwm2        = 80,  /*!< Clock LPCG PWM2. */
580     kCLOCK_Pwm3        = 81,  /*!< Clock LPCG PWM3. */
581     kCLOCK_Pwm4        = 82,  /*!< Clock LPCG PWM4. */
582     kCLOCK_Can1        = 83,  /*!< Clock LPCG CAN1. */
583     kCLOCK_Can2        = 84,  /*!< Clock LPCG CAN2. */
584     kCLOCK_Can3        = 85,  /*!< Clock LPCG CAN3. */
585     kCLOCK_Lpuart1     = 86,  /*!< Clock LPCG LPUART1. */
586     kCLOCK_Lpuart2     = 87,  /*!< Clock LPCG LPUART2. */
587     kCLOCK_Lpuart3     = 88,  /*!< Clock LPCG LPUART3. */
588     kCLOCK_Lpuart4     = 89,  /*!< Clock LPCG LPUART4. */
589     kCLOCK_Lpuart5     = 90,  /*!< Clock LPCG LPUART5. */
590     kCLOCK_Lpuart6     = 91,  /*!< Clock LPCG LPUART6. */
591     kCLOCK_Lpuart7     = 92,  /*!< Clock LPCG LPUART7. */
592     kCLOCK_Lpuart8     = 93,  /*!< Clock LPCG LPUART8. */
593     kCLOCK_Lpuart9     = 94,  /*!< Clock LPCG LPUART9. */
594     kCLOCK_Lpuart10    = 95,  /*!< Clock LPCG LPUART10. */
595     kCLOCK_Lpuart11    = 96,  /*!< Clock LPCG LPUART11. */
596     kCLOCK_Lpuart12    = 97,  /*!< Clock LPCG LPUART12. */
597     kCLOCK_Lpi2c1      = 98,  /*!< Clock LPCG LPI2C1. */
598     kCLOCK_Lpi2c2      = 99,  /*!< Clock LPCG LPI2C2. */
599     kCLOCK_Lpi2c3      = 100, /*!< Clock LPCG LPI2C3. */
600     kCLOCK_Lpi2c4      = 101, /*!< Clock LPCG LPI2C4. */
601     kCLOCK_Lpi2c5      = 102, /*!< Clock LPCG LPI2C5. */
602     kCLOCK_Lpi2c6      = 103, /*!< Clock LPCG LPI2C6. */
603     kCLOCK_Lpspi1      = 104, /*!< Clock LPCG LPSPI1. */
604     kCLOCK_Lpspi2      = 105, /*!< Clock LPCG LPSPI2. */
605     kCLOCK_Lpspi3      = 106, /*!< Clock LPCG LPSPI3. */
606     kCLOCK_Lpspi4      = 107, /*!< Clock LPCG LPSPI4. */
607     kCLOCK_Lpspi5      = 108, /*!< Clock LPCG LPSPI5. */
608     kCLOCK_Lpspi6      = 109, /*!< Clock LPCG LPSPI6. */
609     kCLOCK_Sim1        = 110, /*!< Clock LPCG SIM1. */
610     kCLOCK_Sim2        = 111, /*!< Clock LPCG SIM2. */
611     kCLOCK_Enet        = 112, /*!< Clock LPCG ENET. */
612     kCLOCK_Enet_1g     = 113, /*!< Clock LPCG ENET 1G. */
613     kCLOCK_Usb         = 115, /*!< Clock LPCG USB. */
614     kCLOCK_Cdog        = 116, /*!< Clock LPCG CDOG. */
615     kCLOCK_Usdhc1      = 117, /*!< Clock LPCG USDHC1. */
616     kCLOCK_Usdhc2      = 118, /*!< Clock LPCG USDHC2. */
617     kCLOCK_Asrc        = 119, /*!< Clock LPCG ASRC. */
618     kCLOCK_Mqs         = 120, /*!< Clock LPCG MQS. */
619     kCLOCK_Pdm         = 121, /*!< Clock LPCG PDM. */
620     kCLOCK_Spdif       = 122, /*!< Clock LPCG SPDIF. */
621     kCLOCK_Sai1        = 123, /*!< Clock LPCG SAI1. */
622     kCLOCK_Sai2        = 124, /*!< Clock LPCG SAI2. */
623     kCLOCK_Sai3        = 125, /*!< Clock LPCG SAI3. */
624     kCLOCK_Sai4        = 126, /*!< Clock LPCG SAI4. */
625     kCLOCK_Pxp         = 127, /*!< Clock LPCG PXP. */
626     kCLOCK_Gpu2d       = 128, /*!< Clock LPCG GPU2D. */
627     kCLOCK_Lcdif       = 129, /*!< Clock LPCG LCDIF. */
628     kCLOCK_Lcdifv2     = 130, /*!< Clock LPCG LCDIFV2. */
629     kCLOCK_Mipi_Dsi    = 131, /*!< Clock LPCG MIPI DSI. */
630     kCLOCK_Mipi_Csi    = 132, /*!< Clock LPCG MIPI CSI. */
631     kCLOCK_Csi         = 133, /*!< Clock LPCG CSI. */
632     kCLOCK_Dcic_Mipi   = 134, /*!< Clock LPCG DCIC MIPI. */
633     kCLOCK_Dcic_Lcd    = 135, /*!< Clock LPCG DCIC LCD. */
634     kCLOCK_Video_Mux   = 136, /*!< Clock LPCG VIDEO MUX. */
635     kCLOCK_Uniq_Edt_I  = 137, /*!< Clock LPCG Uniq_Edt_I. */
636 
637     kCLOCK_IpInvalid, /*!< Invalid value. */
638 } clock_lpcg_t;
639 
640 /*!
641  * @brief Clock name.
642  */
643 typedef enum _clock_name
644 {
645     kCLOCK_OscRc16M     = 0,  /*!< 16MHz RC Oscillator. */
646     kCLOCK_OscRc48M     = 1,  /*!< 48MHz RC Oscillator. */
647     kCLOCK_OscRc48MDiv2 = 2,  /*!< 48MHz RC Oscillator Div2. */
648     kCLOCK_OscRc400M    = 3,  /*!< 400MHz RC Oscillator. */
649     kCLOCK_Osc24M       = 4,  /*!< 24MHz Oscillator. */
650     kCLOCK_Osc24MOut    = 5,  /*!< 48MHz Oscillator Out. */
651     kCLOCK_ArmPll       = 6,  /*!< ARM PLL. */
652     kCLOCK_ArmPllOut    = 7,  /*!< ARM PLL Out. */
653     kCLOCK_SysPll2      = 8,  /*!< SYS PLL2. */
654     kCLOCK_SysPll2Out   = 9,  /*!< SYS PLL2 OUT. */
655     kCLOCK_SysPll2Pfd0  = 10, /*!< SYS PLL2 PFD0. */
656     kCLOCK_SysPll2Pfd1  = 11, /*!< SYS PLL2 PFD1. */
657     kCLOCK_SysPll2Pfd2  = 12, /*!< SYS PLL2 PFD2. */
658     kCLOCK_SysPll2Pfd3  = 13, /*!< SYS PLL2 PFD3. */
659     kCLOCK_SysPll3      = 14, /*!< SYS PLL3. */
660     kCLOCK_SysPll3Out   = 15, /*!< SYS PLL3 OUT. */
661     kCLOCK_SysPll3Div2  = 16, /*!< SYS PLL3 DIV2 */
662     kCLOCK_SysPll3Pfd0  = 17, /*!< SYS PLL3 PFD0. */
663     kCLOCK_SysPll3Pfd1  = 18, /*!< SYS PLL3 PFD1 */
664     kCLOCK_SysPll3Pfd2  = 19, /*!< SYS PLL3 PFD2 */
665     kCLOCK_SysPll3Pfd3  = 20, /*!< SYS PLL3 PFD3 */
666     kCLOCK_SysPll1      = 21, /*!< SYS PLL1. */
667     kCLOCK_SysPll1Out   = 22, /*!< SYS PLL1 OUT. */
668     kCLOCK_SysPll1Div2  = 23, /*!< SYS PLL1 DIV2. */
669     kCLOCK_SysPll1Div5  = 24, /*!< SYS PLL1 DIV5. */
670     kCLOCK_AudioPll     = 25, /*!< SYS AUDIO PLL. */
671     kCLOCK_AudioPllOut  = 26, /*!< SYS AUDIO PLL OUT. */
672     kCLOCK_VideoPll     = 27, /*!< SYS VIDEO PLL. */
673     kCLOCK_VideoPllOut  = 28, /*!< SYS VIDEO PLL OUT. */
674     kCLOCK_CpuClk,            /*!< SYS CPU CLK. */
675     kCLOCK_CoreSysClk,        /*!< SYS CORE SYS CLK. */
676     kCLOCK_Reserved = 0xFFU,  /*!< Reserved. */
677 } clock_name_t;
678 
679 /* Clock OBSERVE SIGNALS */
680 #define CCM_OBS_M7_CLK_ROOT          128, 4
681 #define CCM_OBS_M4_CLK_ROOT          129, 0
682 #define CCM_OBS_BUS_CLK_ROOT         130, 2
683 #define CCM_OBS_BUS_LPSR_CLK_ROOT    131, 0
684 #define CCM_OBS_SEMC_CLK_ROOT        132, 2
685 #define CCM_OBS_CSSYS_CLK_ROOT       133, 2
686 #define CCM_OBS_CSTRACE_CLK_ROOT     134, 2
687 #define CCM_OBS_M4_SYSTICK_CLK_ROOT  135, 0
688 #define CCM_OBS_M7_SYSTICK_CLK_ROOT  136, 2
689 #define CCM_OBS_ADC1_CLK_ROOT        137, 2
690 #define CCM_OBS_ADC2_CLK_ROOT        138, 2
691 #define CCM_OBS_ACMP_CLK_ROOT        139, 2
692 #define CCM_OBS_FLEXIO1_CLK_ROOT     140, 2
693 #define CCM_OBS_FLEXIO2_CLK_ROOT     141, 2
694 #define CCM_OBS_GPT1_CLK_ROOT        142, 2
695 #define CCM_OBS_GPT2_CLK_ROOT        143, 2
696 #define CCM_OBS_GPT3_CLK_ROOT        144, 2
697 #define CCM_OBS_GPT4_CLK_ROOT        145, 2
698 #define CCM_OBS_GPT5_CLK_ROOT        146, 2
699 #define CCM_OBS_GPT6_CLK_ROOT        147, 2
700 #define CCM_OBS_FLEXSPI1_CLK_ROOT    148, 2
701 #define CCM_OBS_FLEXSPI2_CLK_ROOT    149, 2
702 #define CCM_OBS_CAN1_CLK_ROOT        150, 2
703 #define CCM_OBS_CAN2_CLK_ROOT        151, 2
704 #define CCM_OBS_CAN3_CLK_ROOT        152, 0
705 #define CCM_OBS_LPUART1_CLK_ROOT     153, 2
706 #define CCM_OBS_LPUART2_CLK_ROOT     154, 2
707 #define CCM_OBS_LPUART3_CLK_ROOT     155, 2
708 #define CCM_OBS_LPUART4_CLK_ROOT     156, 2
709 #define CCM_OBS_LPUART5_CLK_ROOT     157, 2
710 #define CCM_OBS_LPUART6_CLK_ROOT     158, 2
711 #define CCM_OBS_LPUART7_CLK_ROOT     159, 2
712 #define CCM_OBS_LPUART8_CLK_ROOT     160, 2
713 #define CCM_OBS_LPUART9_CLK_ROOT     161, 2
714 #define CCM_OBS_LPUART10_CLK_ROOT    162, 2
715 #define CCM_OBS_LPUART11_CLK_ROOT    163, 0
716 #define CCM_OBS_LPUART12_CLK_ROOT    164, 0
717 #define CCM_OBS_LPI2C1_CLK_ROOT      165, 2
718 #define CCM_OBS_LPI2C2_CLK_ROOT      166, 2
719 #define CCM_OBS_LPI2C3_CLK_ROOT      167, 2
720 #define CCM_OBS_LPI2C4_CLK_ROOT      168, 2
721 #define CCM_OBS_LPI2C5_CLK_ROOT      169, 0
722 #define CCM_OBS_LPI2C6_CLK_ROOT      170, 0
723 #define CCM_OBS_LPSPI1_CLK_ROOT      171, 2
724 #define CCM_OBS_LPSPI2_CLK_ROOT      172, 2
725 #define CCM_OBS_LPSPI3_CLK_ROOT      173, 2
726 #define CCM_OBS_LPSPI4_CLK_ROOT      174, 2
727 #define CCM_OBS_LPSPI5_CLK_ROOT      175, 0
728 #define CCM_OBS_LPSPI6_CLK_ROOT      176, 0
729 #define CCM_OBS_EMV1_CLK_ROOT        177, 2
730 #define CCM_OBS_EMV2_CLK_ROOT        178, 2
731 #define CCM_OBS_ENET1_CLK_ROOT       179, 2
732 #define CCM_OBS_ENET2_CLK_ROOT       180, 2
733 #define CCM_OBS_ENET_25M_CLK_ROOT    182, 2
734 #define CCM_OBS_ENET_TIMER1_CLK_ROOT 183, 2
735 #define CCM_OBS_ENET_TIMER2_CLK_ROOT 184, 2
736 #define CCM_OBS_USDHC1_CLK_ROOT      186, 2
737 #define CCM_OBS_USDHC2_CLK_ROOT      187, 2
738 #define CCM_OBS_ASRC_CLK_ROOT        188, 2
739 #define CCM_OBS_MQS_CLK_ROOT         189, 2
740 #define CCM_OBS_MIC_CLK_ROOT         190, 0
741 #define CCM_OBS_SPDIF_CLK_ROOT       191, 2
742 #define CCM_OBS_SAI1_CLK_ROOT        192, 2
743 #define CCM_OBS_SAI2_CLK_ROOT        193, 2
744 #define CCM_OBS_SAI3_CLK_ROOT        194, 2
745 #define CCM_OBS_SAI4_CLK_ROOT        195, 0
746 #define CCM_OBS_GC355_CLK_ROOT       196, 2
747 #define CCM_OBS_LCDIF_CLK_ROOT       197, 2
748 #define CCM_OBS_LCDIFV2_CLK_ROOT     198, 2
749 #define CCM_OBS_MIPI_REF_CLK_ROOT    199, 2
750 #define CCM_OBS_MIPI_ESC_CLK_ROOT    200, 2
751 #define CCM_OBS_CSI2_CLK_ROOT        201, 2
752 #define CCM_OBS_CSI2_ESC_CLK_ROOT    202, 2
753 #define CCM_OBS_CSI2_UI_CLK_ROOT     203, 2
754 #define CCM_OBS_CSI_CLK_ROOT         204, 2
755 #define CCM_OBS_CCM_CKO1_CLK_ROOT    205, 0
756 #define CCM_OBS_CCM_CKO2_CLK_ROOT    206, 2
757 #define CCM_OBS_CM7_CORE_STCLKEN     207, 4
758 #define CCM_OBS_CCM_FLEXRAM_CLK_ROOT 208, 4
759 #define CCM_OBS_MIPI_DSI_TXESC       209, 2
760 #define CCM_OBS_MIPI_DSI_RXESC       210, 2
761 #define CCM_OBS_OSC_RC_16M           224, 0
762 #define CCM_OBS_OSC_RC_48M           225, 0
763 #define CCM_OBS_OSC_RC_48M_DIV2      226, 0
764 #define CCM_OBS_OSC_RC_400M          227, 0
765 #define CCM_OBS_OSC_24M_OUT          229, 0
766 #define CCM_OBS_ARM_PLL_OUT          231, 2
767 #define CCM_OBS_SYS_PLL2_OUT         233, 2
768 #define CCM_OBS_SYS_PLL2_PFD0        234, 2
769 #define CCM_OBS_SYS_PLL2_PFD1        235, 2
770 #define CCM_OBS_SYS_PLL2_PFD2        236, 2
771 #define CCM_OBS_SYS_PLL2_PFD3        237, 2
772 #define CCM_OBS_SYS_PLL3_OUT         239, 2
773 #define CCM_OBS_SYS_PLL3_DIV2        240, 2
774 #define CCM_OBS_SYS_PLL3_PFD0        241, 2
775 #define CCM_OBS_SYS_PLL3_PFD1        242, 2
776 #define CCM_OBS_SYS_PLL3_PFD2        243, 2
777 #define CCM_OBS_SYS_PLL3_PFD3        244, 2
778 #define CCM_OBS_SYS_PLL1_OUT         246, 2
779 #define CCM_OBS_SYS_PLL1_DIV2        247, 2
780 #define CCM_OBS_SYS_PLL1_DIV5        248, 2
781 #define CCM_OBS_PLL_AUDIO_OUT        250, 2
782 #define CCM_OBS_PLL_VIDEO_OUT        252, 2
783 
784 #define CCM_OBS_DIV 3
785 
786 /* Clock Source Definitions */
787 /* clang-format off */
788 static const clock_name_t s_clockSourceName[][8] = {
789         /*SRC0,               SRC1,             SRC2,             SRC3,            SRC4,             SRC5,              SRC6,              SRC7,                      name             index */ \
790         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_ArmPllOut,   kCLOCK_Reserved,   kCLOCK_SysPll3Out, kCLOCK_Reserved},      /* M7               0    */ \
791         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Out, kCLOCK_SysPll1Div5},   /* M4               1    */ \
792         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Out, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},   /* BUS              2    */ \
793         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Out, kCLOCK_SysPll1Div5},   /* BUS_LPSR         3    */ \
794         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd1, kCLOCK_SysPll3Pfd0},  /* SEMC             4    */ \
795         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* CSSYS            5    */ \
796         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1, kCLOCK_SysPll2Out},  /* CSTRACE          6    */ \
797         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd0, kCLOCK_SysPll1Div5},  /* M4_SYSTICK       7    */ \
798         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd0},  /* M7_SYSTICK       8    */ \
799         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* ADC1             9    */ \
800         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* ADC2            10    */ \
801         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Out, kCLOCK_SysPll1Div5, kCLOCK_AudioPllOut, kCLOCK_SysPll2Pfd3},  /* ACMP            11    */ \
802         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* FLEXIO1         12    */ \
803         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* FLEXIO2         13    */ \
804         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll3Pfd3}, /* GPT1            14    */ \
805         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_AudioPllOut, kCLOCK_VideoPllOut}, /* GPT2            15    */ \
806         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_AudioPllOut, kCLOCK_VideoPllOut}, /* GPT3            16    */ \
807         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll3Pfd3}, /* GPT4            17    */ \
808         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll3Pfd3}, /* GPT5            18    */ \
809         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll3Pfd3}, /* GPT6            19    */ \
810         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd0, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out},   /* FLEXSPI1        20    */ \
811         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd0, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out},   /* FLEXSPI2        21    */ \
812         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* CAN1            22    */ \
813         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* CAN2            23    */ \
814         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd3, kCLOCK_SysPll1Div5},  /* CAN3            24    */ \
815         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART1         25    */ \
816         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART2         26    */ \
817         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART3         27    */ \
818         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART4         28    */ \
819         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART5         29    */ \
820         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART6         30    */ \
821         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART7         31    */ \
822         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART8         32    */ \
823         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART9         33    */ \
824         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPUART10        34    */ \
825         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd3, kCLOCK_SysPll1Div5},  /* LPUART11        35    */ \
826         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd3, kCLOCK_SysPll1Div5},  /* LPUART12        36    */ \
827         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPI2C1          37    */ \
828         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPI2C2          38    */ \
829         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPI2C3          39    */ \
830         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPI2C4          40    */ \
831         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd3, kCLOCK_SysPll1Div5},  /* LPI2C5          41    */ \
832         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd3, kCLOCK_SysPll1Div5},  /* LPI2C6          42    */ \
833         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPSPI1          43    */ \
834         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPSPI2          44    */ \
835         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPSPI3          45    */ \
836         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* LPSPI4          46    */ \
837         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5},  /* LPSPI5          47    */ \
838         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5},  /* LPSPI6          48    */ \
839         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* EMV1            49    */ \
840         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3},  /* EMV2            50    */ \
841         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET1           51    */ \
842         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET2           52    */ \
843         {kCLOCK_Reserved,     kCLOCK_Reserved,  kCLOCK_Reserved,  kCLOCK_Reserved, kCLOCK_Reserved,    kCLOCK_Reserved,    kCLOCK_Reserved,    kCLOCK_Reserved},    /* RESERVED        53    */ \
844         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET_25M        54    */ \
845         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET_TIMER1     55    */ \
846         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET_TIMER2     56    */ \
847         {kCLOCK_Reserved,     kCLOCK_Reserved,  kCLOCK_Reserved,  kCLOCK_Reserved, kCLOCK_Reserved,    kCLOCK_Reserved,    kCLOCK_Reserved,    kCLOCK_Reserved},    /* RESERVED        57    */ \
848         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll2Pfd0, kCLOCK_SysPll1Div5, kCLOCK_ArmPllOut},   /* USDHC1          58    */ \
849         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll2Pfd0, kCLOCK_SysPll1Div5, kCLOCK_ArmPllOut},   /* USDHC2          59    */ \
850         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll2Pfd3}, /* ASRC            60    */ \
851         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll2Pfd3}, /* MQS             61    */ \
852         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5},  /* MIC             62    */ \
853         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_AudioPllOut, kCLOCK_SysPll3Out, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll2Pfd3},  /* SPDIF           63    */ \
854         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_AudioPllOut, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd3}, /* SAI1            64    */ \
855         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_AudioPllOut, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd3}, /* SAI2            65    */ \
856         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_AudioPllOut, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd3}, /* SAI3            66    */ \
857         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5},  /* SAI4            67    */ \
858         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd1, kCLOCK_SysPll3Out, kCLOCK_VideoPllOut},   /* GC355           68    */ \
859         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Pfd0, kCLOCK_VideoPllOut},  /* LCDIF           69    */ \
860         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Pfd0, kCLOCK_VideoPllOut},  /* LCDIFV2         70    */ \
861         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd0, kCLOCK_SysPll3Pfd0, kCLOCK_VideoPllOut},  /* MIPI_REF        71    */ \
862         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd0, kCLOCK_SysPll3Pfd0, kCLOCK_VideoPllOut},  /* MIPI_ESC        72    */ \
863         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd0, kCLOCK_VideoPllOut},  /* CSI2            73    */ \
864         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd0, kCLOCK_VideoPllOut},  /* CSI2_ESC        74    */ \
865         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd0, kCLOCK_VideoPllOut},  /* CSI2_UI         75    */ \
866         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out, kCLOCK_SysPll3Pfd1, kCLOCK_VideoPllOut},  /* CSI             76    */ \
867         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll2Out, kCLOCK_SysPll3Pfd1, kCLOCK_SysPll1Div5},  /* CKO1            77    */ \
868         {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd3, kCLOCK_OscRc48M, kCLOCK_SysPll3Pfd1, kCLOCK_AudioPllOut}     /* CKO2            78    */ \
869 };
870 /* clang-format on */
871 
872 /*!
873  * @brief Root clock index
874  *
875  */
876 typedef enum _clock_root
877 {
878     kCLOCK_Root_M7          = 0,  /*!< CLOCK Root M7. */
879     kCLOCK_Root_M4          = 1,  /*!< CLOCK Root M4. */
880     kCLOCK_Root_Bus         = 2,  /*!< CLOCK Root Bus. */
881     kCLOCK_Root_Bus_Lpsr    = 3,  /*!< CLOCK Root Bus Lpsr. */
882     kCLOCK_Root_Semc        = 4,  /*!< CLOCK Root Semc. */
883     kCLOCK_Root_Cssys       = 5,  /*!< CLOCK Root Cssys. */
884     kCLOCK_Root_Cstrace     = 6,  /*!< CLOCK Root Cstrace. */
885     kCLOCK_Root_M4_Systick  = 7,  /*!< CLOCK Root M4 Systick. */
886     kCLOCK_Root_M7_Systick  = 8,  /*!< CLOCK Root M7 Systick. */
887     kCLOCK_Root_Adc1        = 9,  /*!< CLOCK Root Adc1. */
888     kCLOCK_Root_Adc2        = 10, /*!< CLOCK Root Adc2. */
889     kCLOCK_Root_Acmp        = 11, /*!< CLOCK Root Acmp. */
890     kCLOCK_Root_Flexio1     = 12, /*!< CLOCK Root Flexio1. */
891     kCLOCK_Root_Flexio2     = 13, /*!< CLOCK Root Flexio2. */
892     kCLOCK_Root_Gpt1        = 14, /*!< CLOCK Root Gpt1. */
893     kCLOCK_Root_Gpt2        = 15, /*!< CLOCK Root Gpt2. */
894     kCLOCK_Root_Gpt3        = 16, /*!< CLOCK Root Gpt3. */
895     kCLOCK_Root_Gpt4        = 17, /*!< CLOCK Root Gpt4. */
896     kCLOCK_Root_Gpt5        = 18, /*!< CLOCK Root Gpt5. */
897     kCLOCK_Root_Gpt6        = 19, /*!< CLOCK Root Gpt6. */
898     kCLOCK_Root_Flexspi1    = 20, /*!< CLOCK Root Flexspi1. */
899     kCLOCK_Root_Flexspi2    = 21, /*!< CLOCK Root Flexspi2. */
900     kCLOCK_Root_Can1        = 22, /*!< CLOCK Root Can1. */
901     kCLOCK_Root_Can2        = 23, /*!< CLOCK Root Can2. */
902     kCLOCK_Root_Can3        = 24, /*!< CLOCK Root Can3. */
903     kCLOCK_Root_Lpuart1     = 25, /*!< CLOCK Root Lpuart1. */
904     kCLOCK_Root_Lpuart2     = 26, /*!< CLOCK Root Lpuart2. */
905     kCLOCK_Root_Lpuart3     = 27, /*!< CLOCK Root Lpuart3. */
906     kCLOCK_Root_Lpuart4     = 28, /*!< CLOCK Root Lpuart4. */
907     kCLOCK_Root_Lpuart5     = 29, /*!< CLOCK Root Lpuart5. */
908     kCLOCK_Root_Lpuart6     = 30, /*!< CLOCK Root Lpuart6. */
909     kCLOCK_Root_Lpuart7     = 31, /*!< CLOCK Root Lpuart7. */
910     kCLOCK_Root_Lpuart8     = 32, /*!< CLOCK Root Lpuart8. */
911     kCLOCK_Root_Lpuart9     = 33, /*!< CLOCK Root Lpuart9. */
912     kCLOCK_Root_Lpuart10    = 34, /*!< CLOCK Root Lpuart10. */
913     kCLOCK_Root_Lpuart11    = 35, /*!< CLOCK Root Lpuart11. */
914     kCLOCK_Root_Lpuart12    = 36, /*!< CLOCK Root Lpuart12. */
915     kCLOCK_Root_Lpi2c1      = 37, /*!< CLOCK Root Lpi2c1. */
916     kCLOCK_Root_Lpi2c2      = 38, /*!< CLOCK Root Lpi2c2. */
917     kCLOCK_Root_Lpi2c3      = 39, /*!< CLOCK Root Lpi2c3. */
918     kCLOCK_Root_Lpi2c4      = 40, /*!< CLOCK Root Lpi2c4. */
919     kCLOCK_Root_Lpi2c5      = 41, /*!< CLOCK Root Lpi2c5. */
920     kCLOCK_Root_Lpi2c6      = 42, /*!< CLOCK Root Lpi2c6. */
921     kCLOCK_Root_Lpspi1      = 43, /*!< CLOCK Root Lpspi1. */
922     kCLOCK_Root_Lpspi2      = 44, /*!< CLOCK Root Lpspi2. */
923     kCLOCK_Root_Lpspi3      = 45, /*!< CLOCK Root Lpspi3. */
924     kCLOCK_Root_Lpspi4      = 46, /*!< CLOCK Root Lpspi4. */
925     kCLOCK_Root_Lpspi5      = 47, /*!< CLOCK Root Lpspi5. */
926     kCLOCK_Root_Lpspi6      = 48, /*!< CLOCK Root Lpspi6. */
927     kCLOCK_Root_Emv1        = 49, /*!< CLOCK Root Emv1. */
928     kCLOCK_Root_Emv2        = 50, /*!< CLOCK Root Emv2. */
929     kCLOCK_Root_Enet1       = 51, /*!< CLOCK Root Enet1. */
930     kCLOCK_Root_Enet2       = 52, /*!< CLOCK Root Enet2. */
931     kCLOCK_Root_Enet_25m    = 54, /*!< CLOCK Root Enet 25M. */
932     kCLOCK_Root_Enet_Timer1 = 55, /*!< CLOCK Root Enet Timer1. */
933     kCLOCK_Root_Enet_Timer2 = 56, /*!< CLOCK Root Enet Timer2. */
934     kCLOCK_Root_Usdhc1      = 58, /*!< CLOCK Root Usdhc1. */
935     kCLOCK_Root_Usdhc2      = 59, /*!< CLOCK Root Usdhc2. */
936     kCLOCK_Root_Asrc        = 60, /*!< CLOCK Root Asrc. */
937     kCLOCK_Root_Mqs         = 61, /*!< CLOCK Root Mqs. */
938     kCLOCK_Root_Mic         = 62, /*!< CLOCK Root MIC. */
939     kCLOCK_Root_Spdif       = 63, /*!< CLOCK Root Spdif */
940     kCLOCK_Root_Sai1        = 64, /*!< CLOCK Root Sai1. */
941     kCLOCK_Root_Sai2        = 65, /*!< CLOCK Root Sai2. */
942     kCLOCK_Root_Sai3        = 66, /*!< CLOCK Root Sai3. */
943     kCLOCK_Root_Sai4        = 67, /*!< CLOCK Root Sai4. */
944     kCLOCK_Root_Gc355       = 68, /*!< CLOCK Root Gc355. */
945     kCLOCK_Root_Lcdif       = 69, /*!< CLOCK Root Lcdif. */
946     kCLOCK_Root_Lcdifv2     = 70, /*!< CLOCK Root Lcdifv2. */
947     kCLOCK_Root_Mipi_Ref    = 71, /*!< CLOCK Root Mipi Ref. */
948     kCLOCK_Root_Mipi_Esc    = 72, /*!< CLOCK Root Mipi Esc. */
949     kCLOCK_Root_Csi2        = 73, /*!< CLOCK Root Csi2. */
950     kCLOCK_Root_Csi2_Esc    = 74, /*!< CLOCK Root Csi2 Esc. */
951     kCLOCK_Root_Csi2_Ui     = 75, /*!< CLOCK Root Csi2 Ui. */
952     kCLOCK_Root_Csi         = 76, /*!< CLOCK Root Csi. */
953     kCLOCK_Root_Cko1        = 77, /*!< CLOCK Root CKo1. */
954     kCLOCK_Root_Cko2        = 78, /*!< CLOCK Root CKo2. */
955 } clock_root_t;
956 
957 /*!
958  * @brief The enumerator of clock roots' clock source mux value.
959  */
960 typedef enum _clock_root_mux_source
961 {
962     /* M7 */
963     kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< M7 mux from MuxOscRc48MDiv2. */
964     kCLOCK_M7_ClockRoot_MuxOsc24MOut    = 1U, /*!< M7 mux from MuxOsc24MOut. */
965     kCLOCK_M7_ClockRoot_MuxOscRc400M    = 2U, /*!< M7 mux from MuxOscRc400M. */
966     kCLOCK_M7_ClockRoot_MuxOscRc16M     = 3U, /*!< M7 mux from MuxOscRc16M. */
967     kCLOCK_M7_ClockRoot_MuxArmPllOut    = 4U, /*!< M7 mux from MuxArmPllOut. */
968     kCLOCK_M7_ClockRoot_MuxSysPll3Out   = 6U, /*!< M7 mux from MuxSysPll3Out. */
969 
970     /* M4 */
971     kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< M4 mux from MuxOscRc48MDiv2. */
972     kCLOCK_M4_ClockRoot_MuxOsc24MOut    = 1U, /*!< M4 mux from MuxOsc24MOut. */
973     kCLOCK_M4_ClockRoot_MuxOscRc400M    = 2U, /*!< M4 mux from MuxOscRc400M. */
974     kCLOCK_M4_ClockRoot_MuxOscRc16M     = 3U, /*!< M4 mux from MuxOscRc16M. */
975     kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< M4 mux from MuxSysPll3Pfd3. */
976     kCLOCK_M4_ClockRoot_MuxSysPll3Out   = 5U, /*!< M4 mux from MuxSysPll3Out. */
977     kCLOCK_M4_ClockRoot_MuxSysPll2Out   = 6U, /*!< M4 mux from MuxSysPll2Out. */
978     kCLOCK_M4_ClockRoot_MuxSysPll1Div5  = 7U, /*!< M4 mux from MuxSysPll1Div5. */
979 
980     /* BUS */
981     kCLOCK_BUS_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< BUS mux from MuxOscRc48MDiv2. */
982     kCLOCK_BUS_ClockRoot_MuxOsc24MOut    = 1U, /*!< BUS mux from MuxOsc24MOut. */
983     kCLOCK_BUS_ClockRoot_MuxOscRc400M    = 2U, /*!< BUS mux from MuxOscRc400M. */
984     kCLOCK_BUS_ClockRoot_MuxOscRc16M     = 3U, /*!< BUS mux from MuxOscRc16M. */
985     kCLOCK_BUS_ClockRoot_MuxSysPll3Out   = 4U, /*!< BUS mux from MuxSysPll3Out. */
986     kCLOCK_BUS_ClockRoot_MuxSysPll1Div5  = 5U, /*!< BUS mux from MuxSysPll1Div5. */
987     kCLOCK_BUS_ClockRoot_MuxSysPll2Out   = 6U, /*!< BUS mux from MuxSysPll2Out. */
988     kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< BUS mux from MuxSysPll2Pfd3. */
989 
990     /* BUS_LPSR */
991     kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< BUS_LPSR mux from MuxOscRc48MDiv2. */
992     kCLOCK_BUS_LPSR_ClockRoot_MuxOsc24MOut    = 1U, /*!< BUS_LPSR mux from MuxOsc24MOut. */
993     kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc400M    = 2U, /*!< BUS_LPSR mux from MuxOscRc400M. */
994     kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc16M     = 3U, /*!< BUS_LPSR mux from MuxOscRc16M. */
995     kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< BUS_LPSR mux from MuxSysPll3Pfd3. */
996     kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out   = 5U, /*!< BUS_LPSR mux from MuxSysPll3Out. */
997     kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll2Out   = 6U, /*!< BUS_LPSR mux from MuxSysPll2Out. */
998     kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll1Div5  = 7U, /*!< BUS_LPSR mux from MuxSysPll1Div5. */
999 
1000     /* SEMC */
1001     kCLOCK_SEMC_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SEMC mux from MuxOscRc48MDiv2. */
1002     kCLOCK_SEMC_ClockRoot_MuxOsc24MOut    = 1U, /*!< SEMC mux from MuxOsc24MOut. */
1003     kCLOCK_SEMC_ClockRoot_MuxOscRc400M    = 2U, /*!< SEMC mux from MuxOscRc400M. */
1004     kCLOCK_SEMC_ClockRoot_MuxOscRc16M     = 3U, /*!< SEMC mux from MuxOscRc16M. */
1005     kCLOCK_SEMC_ClockRoot_MuxSysPll1Div5  = 4U, /*!< SEMC mux from MuxSysPll1Div5. */
1006     kCLOCK_SEMC_ClockRoot_MuxSysPll2Out   = 5U, /*!< SEMC mux from MuxSysPll2Out. */
1007     kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1  = 6U, /*!< SEMC mux from MuxSysPll2Pfd1. */
1008     kCLOCK_SEMC_ClockRoot_MuxSysPll3Pfd0  = 7U, /*!< SEMC mux from MuxSysPll3Pfd0. */
1009 
1010     /* CSSYS */
1011     kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSSYS mux from MuxOscRc48MDiv2. */
1012     kCLOCK_CSSYS_ClockRoot_MuxOsc24MOut    = 1U, /*!< CSSYS mux from MuxOsc24MOut. */
1013     kCLOCK_CSSYS_ClockRoot_MuxOscRc400M    = 2U, /*!< CSSYS mux from MuxOscRc400M. */
1014     kCLOCK_CSSYS_ClockRoot_MuxOscRc16M     = 3U, /*!< CSSYS mux from MuxOscRc16M. */
1015     kCLOCK_CSSYS_ClockRoot_MuxSysPll3Div2  = 4U, /*!< CSSYS mux from MuxSysPll3Div2. */
1016     kCLOCK_CSSYS_ClockRoot_MuxSysPll1Div5  = 5U, /*!< CSSYS mux from MuxSysPll1Div5. */
1017     kCLOCK_CSSYS_ClockRoot_MuxSysPll2Out   = 6U, /*!< CSSYS mux from MuxSysPll2Out. */
1018     kCLOCK_CSSYS_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< CSSYS mux from MuxSysPll2Pfd3. */
1019 
1020     /* CSTRACE */
1021     kCLOCK_CSTRACE_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSTRACE mux from MuxOscRc48MDiv2. */
1022     kCLOCK_CSTRACE_ClockRoot_MuxOsc24MOut    = 1U, /*!< CSTRACE mux from MuxOsc24MOut. */
1023     kCLOCK_CSTRACE_ClockRoot_MuxOscRc400M    = 2U, /*!< CSTRACE mux from MuxOscRc400M. */
1024     kCLOCK_CSTRACE_ClockRoot_MuxOscRc16M     = 3U, /*!< CSTRACE mux from MuxOscRc16M. */
1025     kCLOCK_CSTRACE_ClockRoot_MuxSysPll3Div2  = 4U, /*!< CSTRACE mux from MuxSysPll3Div2. */
1026     kCLOCK_CSTRACE_ClockRoot_MuxSysPll1Div5  = 5U, /*!< CSTRACE mux from MuxSysPll1Div5. */
1027     kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Pfd1  = 6U, /*!< CSTRACE mux from MuxSysPll2Pfd1. */
1028     kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out   = 7U, /*!< CSTRACE mux from MuxSysPll2Out. */
1029 
1030     /* M4_SYSTICK */
1031     kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< M4_SYSTICK mux from MuxOscRc48MDiv2. */
1032     kCLOCK_M4_SYSTICK_ClockRoot_MuxOsc24MOut    = 1U, /*!< M4_SYSTICK mux from MuxOsc24MOut. */
1033     kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc400M    = 2U, /*!< M4_SYSTICK mux from MuxOscRc400M. */
1034     kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc16M     = 3U, /*!< M4_SYSTICK mux from MuxOscRc16M. */
1035     kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< M4_SYSTICK mux from MuxSysPll3Pfd3. */
1036     kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Out   = 5U, /*!< M4_SYSTICK mux from MuxSysPll3Out. */
1037     kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll2Pfd0  = 6U, /*!< M4_SYSTICK mux from MuxSysPll2Pfd0. */
1038     kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll1Div5  = 7U, /*!< M4_SYSTICK mux from MuxSysPll1Div5. */
1039 
1040     /* M7_SYSTICK */
1041     kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< M7_SYSTICK mux from MuxOscRc48MDiv2. */
1042     kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut    = 1U, /*!< M7_SYSTICK mux from MuxOsc24MOut. */
1043     kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M    = 2U, /*!< M7_SYSTICK mux from MuxOscRc400M. */
1044     kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc16M     = 3U, /*!< M7_SYSTICK mux from MuxOscRc16M. */
1045     kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Out   = 4U, /*!< M7_SYSTICK mux from MuxSysPll2Out. */
1046     kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2  = 5U, /*!< M7_SYSTICK mux from MuxSysPll3Div2. */
1047     kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll1Div5  = 6U, /*!< M7_SYSTICK mux from MuxSysPll1Div5. */
1048     kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Pfd0  = 7U, /*!< M7_SYSTICK mux from MuxSysPll2Pfd0. */
1049 
1050     /* ADC1 */
1051     kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ADC1 mux from MuxOscRc48MDiv2. */
1052     kCLOCK_ADC1_ClockRoot_MuxOsc24MOut    = 1U, /*!< ADC1 mux from MuxOsc24MOut. */
1053     kCLOCK_ADC1_ClockRoot_MuxOscRc400M    = 2U, /*!< ADC1 mux from MuxOscRc400M. */
1054     kCLOCK_ADC1_ClockRoot_MuxOscRc16M     = 3U, /*!< ADC1 mux from MuxOscRc16M. */
1055     kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2  = 4U, /*!< ADC1 mux from MuxSysPll3Div2. */
1056     kCLOCK_ADC1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< ADC1 mux from MuxSysPll1Div5. */
1057     kCLOCK_ADC1_ClockRoot_MuxSysPll2Out   = 6U, /*!< ADC1 mux from MuxSysPll2Out. */
1058     kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< ADC1 mux from MuxSysPll2Pfd3. */
1059 
1060     /* ADC2 */
1061     kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ADC2 mux from MuxOscRc48MDiv2. */
1062     kCLOCK_ADC2_ClockRoot_MuxOsc24MOut    = 1U, /*!< ADC2 mux from MuxOsc24MOut. */
1063     kCLOCK_ADC2_ClockRoot_MuxOscRc400M    = 2U, /*!< ADC2 mux from MuxOscRc400M. */
1064     kCLOCK_ADC2_ClockRoot_MuxOscRc16M     = 3U, /*!< ADC2 mux from MuxOscRc16M. */
1065     kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2  = 4U, /*!< ADC2 mux from MuxSysPll3Div2. */
1066     kCLOCK_ADC2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< ADC2 mux from MuxSysPll1Div5. */
1067     kCLOCK_ADC2_ClockRoot_MuxSysPll2Out   = 6U, /*!< ADC2 mux from MuxSysPll2Out. */
1068     kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< ADC2 mux from MuxSysPll2Pfd3. */
1069 
1070     /* ACMP */
1071     kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ACMP mux from MuxOscRc48MDiv2. */
1072     kCLOCK_ACMP_ClockRoot_MuxOsc24MOut    = 1U, /*!< ACMP mux from MuxOsc24MOut. */
1073     kCLOCK_ACMP_ClockRoot_MuxOscRc400M    = 2U, /*!< ACMP mux from MuxOscRc400M. */
1074     kCLOCK_ACMP_ClockRoot_MuxOscRc16M     = 3U, /*!< ACMP mux from MuxOscRc16M. */
1075     kCLOCK_ACMP_ClockRoot_MuxSysPll3Out   = 4U, /*!< ACMP mux from MuxSysPll3Out. */
1076     kCLOCK_ACMP_ClockRoot_MuxSysPll1Div5  = 5U, /*!< ACMP mux from MuxSysPll1Div5. */
1077     kCLOCK_ACMP_ClockRoot_MuxAudioPllOut  = 6U, /*!< ACMP mux from MuxAudioPllOut. */
1078     kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< ACMP mux from MuxSysPll2Pfd3. */
1079 
1080     /* FLEXIO1 */
1081     kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< FLEXIO1 mux from MuxOscRc48MDiv2. */
1082     kCLOCK_FLEXIO1_ClockRoot_MuxOsc24MOut    = 1U, /*!< FLEXIO1 mux from MuxOsc24MOut. */
1083     kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M    = 2U, /*!< FLEXIO1 mux from MuxOscRc400M. */
1084     kCLOCK_FLEXIO1_ClockRoot_MuxOscRc16M     = 3U, /*!< FLEXIO1 mux from MuxOscRc16M. */
1085     kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2  = 4U, /*!< FLEXIO1 mux from MuxSysPll3Div2. */
1086     kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< FLEXIO1 mux from MuxSysPll1Div5. */
1087     kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Out   = 6U, /*!< FLEXIO1 mux from MuxSysPll2Out. */
1088     kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< FLEXIO1 mux from MuxSysPll2Pfd3. */
1089 
1090     /* FLEXIO2 */
1091     kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< FLEXIO2 mux from MuxOscRc48MDiv2. */
1092     kCLOCK_FLEXIO2_ClockRoot_MuxOsc24MOut    = 1U, /*!< FLEXIO2 mux from MuxOsc24MOut. */
1093     kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M    = 2U, /*!< FLEXIO2 mux from MuxOscRc400M. */
1094     kCLOCK_FLEXIO2_ClockRoot_MuxOscRc16M     = 3U, /*!< FLEXIO2 mux from MuxOscRc16M. */
1095     kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2  = 4U, /*!< FLEXIO2 mux from MuxSysPll3Div2. */
1096     kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< FLEXIO2 mux from MuxSysPll1Div5. */
1097     kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Out   = 6U, /*!< FLEXIO2 mux from MuxSysPll2Out. */
1098     kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< FLEXIO2 mux from MuxSysPll2Pfd3. */
1099 
1100     /* GPT1 */
1101     kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT1 mux from MuxOscRc48MDiv2. */
1102     kCLOCK_GPT1_ClockRoot_MuxOsc24MOut    = 1U, /*!< GPT1 mux from MuxOsc24MOut. */
1103     kCLOCK_GPT1_ClockRoot_MuxOscRc400M    = 2U, /*!< GPT1 mux from MuxOscRc400M. */
1104     kCLOCK_GPT1_ClockRoot_MuxOscRc16M     = 3U, /*!< GPT1 mux from MuxOscRc16M. */
1105     kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2  = 4U, /*!< GPT1 mux from MuxSysPll3Div2. */
1106     kCLOCK_GPT1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< GPT1 mux from MuxSysPll1Div5. */
1107     kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd2  = 6U, /*!< GPT1 mux from MuxSysPll3Pfd2. */
1108     kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd3  = 7U, /*!< GPT1 mux from MuxSysPll3Pfd3. */
1109 
1110     /* GPT2 */
1111     kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT2 mux from MuxOscRc48MDiv2. */
1112     kCLOCK_GPT2_ClockRoot_MuxOsc24MOut    = 1U, /*!< GPT2 mux from MuxOsc24MOut. */
1113     kCLOCK_GPT2_ClockRoot_MuxOscRc400M    = 2U, /*!< GPT2 mux from MuxOscRc400M. */
1114     kCLOCK_GPT2_ClockRoot_MuxOscRc16M     = 3U, /*!< GPT2 mux from MuxOscRc16M. */
1115     kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2  = 4U, /*!< GPT2 mux from MuxSysPll3Div2. */
1116     kCLOCK_GPT2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< GPT2 mux from MuxSysPll1Div5. */
1117     kCLOCK_GPT2_ClockRoot_MuxAudioPllOut  = 6U, /*!< GPT2 mux from MuxAudioPllOut. */
1118     kCLOCK_GPT2_ClockRoot_MuxVideoPllOut  = 7U, /*!< GPT2 mux from MuxVideoPllOut. */
1119 
1120     /* GPT3 */
1121     kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT3 mux from MuxOscRc48MDiv2. */
1122     kCLOCK_GPT3_ClockRoot_MuxOsc24MOut    = 1U, /*!< GPT3 mux from MuxOsc24MOut. */
1123     kCLOCK_GPT3_ClockRoot_MuxOscRc400M    = 2U, /*!< GPT3 mux from MuxOscRc400M. */
1124     kCLOCK_GPT3_ClockRoot_MuxOscRc16M     = 3U, /*!< GPT3 mux from MuxOscRc16M. */
1125     kCLOCK_GPT3_ClockRoot_MuxSysPll3Div2  = 4U, /*!< GPT3 mux from MuxSysPll3Div2. */
1126     kCLOCK_GPT3_ClockRoot_MuxSysPll1Div5  = 5U, /*!< GPT3 mux from MuxSysPll1Div5. */
1127     kCLOCK_GPT3_ClockRoot_MuxAudioPllOut  = 6U, /*!< GPT3 mux from MuxAudioPllOut. */
1128     kCLOCK_GPT3_ClockRoot_MuxVideoPllOut  = 7U, /*!< GPT3 mux from MuxVideoPllOut. */
1129 
1130     /* GPT4 */
1131     kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT4 mux from MuxOscRc48MDiv2. */
1132     kCLOCK_GPT4_ClockRoot_MuxOsc24MOut    = 1U, /*!< GPT4 mux from MuxOsc24MOut. */
1133     kCLOCK_GPT4_ClockRoot_MuxOscRc400M    = 2U, /*!< GPT4 mux from MuxOscRc400M. */
1134     kCLOCK_GPT4_ClockRoot_MuxOscRc16M     = 3U, /*!< GPT4 mux from MuxOscRc16M. */
1135     kCLOCK_GPT4_ClockRoot_MuxSysPll3Div2  = 4U, /*!< GPT4 mux from MuxSysPll3Div2. */
1136     kCLOCK_GPT4_ClockRoot_MuxSysPll1Div5  = 5U, /*!< GPT4 mux from MuxSysPll1Div5. */
1137     kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd2  = 6U, /*!< GPT4 mux from MuxSysPll3Pfd2. */
1138     kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd3  = 7U, /*!< GPT4 mux from MuxSysPll3Pfd3. */
1139 
1140     /* GPT5 */
1141     kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT5 mux from MuxOscRc48MDiv2. */
1142     kCLOCK_GPT5_ClockRoot_MuxOsc24MOut    = 1U, /*!< GPT5 mux from MuxOsc24MOut. */
1143     kCLOCK_GPT5_ClockRoot_MuxOscRc400M    = 2U, /*!< GPT5 mux from MuxOscRc400M. */
1144     kCLOCK_GPT5_ClockRoot_MuxOscRc16M     = 3U, /*!< GPT5 mux from MuxOscRc16M. */
1145     kCLOCK_GPT5_ClockRoot_MuxSysPll3Div2  = 4U, /*!< GPT5 mux from MuxSysPll3Div2. */
1146     kCLOCK_GPT5_ClockRoot_MuxSysPll1Div5  = 5U, /*!< GPT5 mux from MuxSysPll1Div5. */
1147     kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd2  = 6U, /*!< GPT5 mux from MuxSysPll3Pfd2. */
1148     kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd3  = 7U, /*!< GPT5 mux from MuxSysPll3Pfd3. */
1149 
1150     /* GPT6 */
1151     kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT6 mux from MuxOscRc48MDiv2. */
1152     kCLOCK_GPT6_ClockRoot_MuxOsc24MOut    = 1U, /*!< GPT6 mux from MuxOsc24MOut. */
1153     kCLOCK_GPT6_ClockRoot_MuxOscRc400M    = 2U, /*!< GPT6 mux from MuxOscRc400M. */
1154     kCLOCK_GPT6_ClockRoot_MuxOscRc16M     = 3U, /*!< GPT6 mux from MuxOscRc16M. */
1155     kCLOCK_GPT6_ClockRoot_MuxSysPll3Div2  = 4U, /*!< GPT6 mux from MuxSysPll3Div2. */
1156     kCLOCK_GPT6_ClockRoot_MuxSysPll1Div5  = 5U, /*!< GPT6 mux from MuxSysPll1Div5. */
1157     kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd2  = 6U, /*!< GPT6 mux from MuxSysPll3Pfd2. */
1158     kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd3  = 7U, /*!< GPT6 mux from MuxSysPll3Pfd3. */
1159 
1160     /* FLEXSPI1 */
1161     kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< FLEXSPI1 mux from MuxOscRc48MDiv2. */
1162     kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24MOut    = 1U, /*!< FLEXSPI1 mux from MuxOsc24MOut. */
1163     kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M    = 2U, /*!< FLEXSPI1 mux from MuxOscRc400M. */
1164     kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc16M     = 3U, /*!< FLEXSPI1 mux from MuxOscRc16M. */
1165     kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0  = 4U, /*!< FLEXSPI1 mux from MuxSysPll3Pfd0. */
1166     kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Out   = 5U, /*!< FLEXSPI1 mux from MuxSysPll2Out. */
1167     kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd2  = 6U, /*!< FLEXSPI1 mux from MuxSysPll2Pfd2. */
1168     kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Out   = 7U, /*!< FLEXSPI1 mux from MuxSysPll3Out. */
1169 
1170     /* FLEXSPI2 */
1171     kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< FLEXSPI2 mux from MuxOscRc48MDiv2. */
1172     kCLOCK_FLEXSPI2_ClockRoot_MuxOsc24MOut    = 1U, /*!< FLEXSPI2 mux from MuxOsc24MOut. */
1173     kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M    = 2U, /*!< FLEXSPI2 mux from MuxOscRc400M. */
1174     kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc16M     = 3U, /*!< FLEXSPI2 mux from MuxOscRc16M. */
1175     kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd0  = 4U, /*!< FLEXSPI2 mux from MuxSysPll3Pfd0. */
1176     kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Out   = 5U, /*!< FLEXSPI2 mux from MuxSysPll2Out. */
1177     kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd2  = 6U, /*!< FLEXSPI2 mux from MuxSysPll2Pfd2. */
1178     kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Out   = 7U, /*!< FLEXSPI2 mux from MuxSysPll3Out. */
1179 
1180     /* CAN1 */
1181     kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CAN1 mux from MuxOscRc48MDiv2. */
1182     kCLOCK_CAN1_ClockRoot_MuxOsc24MOut    = 1U, /*!< CAN1 mux from MuxOsc24MOut. */
1183     kCLOCK_CAN1_ClockRoot_MuxOscRc400M    = 2U, /*!< CAN1 mux from MuxOscRc400M. */
1184     kCLOCK_CAN1_ClockRoot_MuxOscRc16M     = 3U, /*!< CAN1 mux from MuxOscRc16M. */
1185     kCLOCK_CAN1_ClockRoot_MuxSysPll3Div2  = 4U, /*!< CAN1 mux from MuxSysPll3Div2. */
1186     kCLOCK_CAN1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< CAN1 mux from MuxSysPll1Div5. */
1187     kCLOCK_CAN1_ClockRoot_MuxSysPll2Out   = 6U, /*!< CAN1 mux from MuxSysPll2Out. */
1188     kCLOCK_CAN1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< CAN1 mux from MuxSysPll2Pfd3. */
1189 
1190     /* CAN2 */
1191     kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CAN2 mux from MuxOscRc48MDiv2. */
1192     kCLOCK_CAN2_ClockRoot_MuxOsc24MOut    = 1U, /*!< CAN2 mux from MuxOsc24MOut. */
1193     kCLOCK_CAN2_ClockRoot_MuxOscRc400M    = 2U, /*!< CAN2 mux from MuxOscRc400M. */
1194     kCLOCK_CAN2_ClockRoot_MuxOscRc16M     = 3U, /*!< CAN2 mux from MuxOscRc16M. */
1195     kCLOCK_CAN2_ClockRoot_MuxSysPll3Div2  = 4U, /*!< CAN2 mux from MuxSysPll3Div2. */
1196     kCLOCK_CAN2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< CAN2 mux from MuxSysPll1Div5. */
1197     kCLOCK_CAN2_ClockRoot_MuxSysPll2Out   = 6U, /*!< CAN2 mux from MuxSysPll2Out. */
1198     kCLOCK_CAN2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< CAN2 mux from MuxSysPll2Pfd3. */
1199 
1200     /* CAN3 */
1201     kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CAN3 mux from MuxOscRc48MDiv2. */
1202     kCLOCK_CAN3_ClockRoot_MuxOsc24MOut    = 1U, /*!< CAN3 mux from MuxOsc24MOut. */
1203     kCLOCK_CAN3_ClockRoot_MuxOscRc400M    = 2U, /*!< CAN3 mux from MuxOscRc400M. */
1204     kCLOCK_CAN3_ClockRoot_MuxOscRc16M     = 3U, /*!< CAN3 mux from MuxOscRc16M. */
1205     kCLOCK_CAN3_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< CAN3 mux from MuxSysPll3Pfd3. */
1206     kCLOCK_CAN3_ClockRoot_MuxSysPll3Out   = 5U, /*!< CAN3 mux from MuxSysPll3Out. */
1207     kCLOCK_CAN3_ClockRoot_MuxSysPll2Pfd3  = 6U, /*!< CAN3 mux from MuxSysPll2Pfd3. */
1208     kCLOCK_CAN3_ClockRoot_MuxSysPll1Div5  = 7U, /*!< CAN3 mux from MuxSysPll1Div5. */
1209 
1210     /* LPUART1 */
1211     kCLOCK_LPUART1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART1 mux from MuxOscRc48MDiv2. */
1212     kCLOCK_LPUART1_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART1 mux from MuxOsc24MOut. */
1213     kCLOCK_LPUART1_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART1 mux from MuxOscRc400M. */
1214     kCLOCK_LPUART1_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART1 mux from MuxOscRc16M. */
1215     kCLOCK_LPUART1_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART1 mux from MuxSysPll3Div2. */
1216     kCLOCK_LPUART1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART1 mux from MuxSysPll1Div5. */
1217     kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART1 mux from MuxSysPll2Out. */
1218     kCLOCK_LPUART1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART1 mux from MuxSysPll2Pfd3. */
1219 
1220     /* LPUART2 */
1221     kCLOCK_LPUART2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART2 mux from MuxOscRc48MDiv2. */
1222     kCLOCK_LPUART2_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART2 mux from MuxOsc24MOut. */
1223     kCLOCK_LPUART2_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART2 mux from MuxOscRc400M. */
1224     kCLOCK_LPUART2_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART2 mux from MuxOscRc16M. */
1225     kCLOCK_LPUART2_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART2 mux from MuxSysPll3Div2. */
1226     kCLOCK_LPUART2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART2 mux from MuxSysPll1Div5. */
1227     kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART2 mux from MuxSysPll2Out. */
1228     kCLOCK_LPUART2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART2 mux from MuxSysPll2Pfd3. */
1229 
1230     /* LPUART3 */
1231     kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART3 mux from MuxOscRc48MDiv2. */
1232     kCLOCK_LPUART3_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART3 mux from MuxOsc24MOut. */
1233     kCLOCK_LPUART3_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART3 mux from MuxOscRc400M. */
1234     kCLOCK_LPUART3_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART3 mux from MuxOscRc16M. */
1235     kCLOCK_LPUART3_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART3 mux from MuxSysPll3Div2. */
1236     kCLOCK_LPUART3_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART3 mux from MuxSysPll1Div5. */
1237     kCLOCK_LPUART3_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART3 mux from MuxSysPll2Out. */
1238     kCLOCK_LPUART3_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART3 mux from MuxSysPll2Pfd3. */
1239 
1240     /* LPUART4 */
1241     kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART4 mux from MuxOscRc48MDiv2. */
1242     kCLOCK_LPUART4_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART4 mux from MuxOsc24MOut. */
1243     kCLOCK_LPUART4_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART4 mux from MuxOscRc400M. */
1244     kCLOCK_LPUART4_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART4 mux from MuxOscRc16M. */
1245     kCLOCK_LPUART4_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART4 mux from MuxSysPll3Div2. */
1246     kCLOCK_LPUART4_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART4 mux from MuxSysPll1Div5. */
1247     kCLOCK_LPUART4_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART4 mux from MuxSysPll2Out. */
1248     kCLOCK_LPUART4_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART4 mux from MuxSysPll2Pfd3. */
1249 
1250     /* LPUART5 */
1251     kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART5 mux from MuxOscRc48MDiv2. */
1252     kCLOCK_LPUART5_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART5 mux from MuxOsc24MOut. */
1253     kCLOCK_LPUART5_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART5 mux from MuxOscRc400M. */
1254     kCLOCK_LPUART5_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART5 mux from MuxOscRc16M. */
1255     kCLOCK_LPUART5_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART5 mux from MuxSysPll3Div2. */
1256     kCLOCK_LPUART5_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART5 mux from MuxSysPll1Div5. */
1257     kCLOCK_LPUART5_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART5 mux from MuxSysPll2Out. */
1258     kCLOCK_LPUART5_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART5 mux from MuxSysPll2Pfd3. */
1259 
1260     /* LPUART6 */
1261     kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART6 mux from MuxOscRc48MDiv2. */
1262     kCLOCK_LPUART6_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART6 mux from MuxOsc24MOut. */
1263     kCLOCK_LPUART6_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART6 mux from MuxOscRc400M. */
1264     kCLOCK_LPUART6_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART6 mux from MuxOscRc16M. */
1265     kCLOCK_LPUART6_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART6 mux from MuxSysPll3Div2. */
1266     kCLOCK_LPUART6_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART6 mux from MuxSysPll1Div5. */
1267     kCLOCK_LPUART6_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART6 mux from MuxSysPll2Out. */
1268     kCLOCK_LPUART6_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART6 mux from MuxSysPll2Pfd3. */
1269 
1270     /* LPUART7 */
1271     kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART7 mux from MuxOscRc48MDiv2. */
1272     kCLOCK_LPUART7_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART7 mux from MuxOsc24MOut. */
1273     kCLOCK_LPUART7_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART7 mux from MuxOscRc400M. */
1274     kCLOCK_LPUART7_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART7 mux from MuxOscRc16M. */
1275     kCLOCK_LPUART7_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART7 mux from MuxSysPll3Div2. */
1276     kCLOCK_LPUART7_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART7 mux from MuxSysPll1Div5. */
1277     kCLOCK_LPUART7_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART7 mux from MuxSysPll2Out. */
1278     kCLOCK_LPUART7_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART7 mux from MuxSysPll2Pfd3. */
1279 
1280     /* LPUART8 */
1281     kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART8 mux from MuxOscRc48MDiv2. */
1282     kCLOCK_LPUART8_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART8 mux from MuxOsc24MOut. */
1283     kCLOCK_LPUART8_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART8 mux from MuxOscRc400M. */
1284     kCLOCK_LPUART8_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART8 mux from MuxOscRc16M. */
1285     kCLOCK_LPUART8_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART8 mux from MuxSysPll3Div2. */
1286     kCLOCK_LPUART8_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART8 mux from MuxSysPll1Div5. */
1287     kCLOCK_LPUART8_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART8 mux from MuxSysPll2Out. */
1288     kCLOCK_LPUART8_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART8 mux from MuxSysPll2Pfd3. */
1289 
1290     /* LPUART9 */
1291     kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART9 mux from MuxOscRc48MDiv2. */
1292     kCLOCK_LPUART9_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART9 mux from MuxOsc24MOut. */
1293     kCLOCK_LPUART9_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART9 mux from MuxOscRc400M. */
1294     kCLOCK_LPUART9_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART9 mux from MuxOscRc16M. */
1295     kCLOCK_LPUART9_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART9 mux from MuxSysPll3Div2. */
1296     kCLOCK_LPUART9_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART9 mux from MuxSysPll1Div5. */
1297     kCLOCK_LPUART9_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART9 mux from MuxSysPll2Out. */
1298     kCLOCK_LPUART9_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART9 mux from MuxSysPll2Pfd3. */
1299 
1300     /* LPUART10 */
1301     kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART10 mux from MuxOscRc48MDiv2. */
1302     kCLOCK_LPUART10_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART10 mux from MuxOsc24MOut. */
1303     kCLOCK_LPUART10_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART10 mux from MuxOscRc400M. */
1304     kCLOCK_LPUART10_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART10 mux from MuxOscRc16M. */
1305     kCLOCK_LPUART10_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPUART10 mux from MuxSysPll3Div2. */
1306     kCLOCK_LPUART10_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPUART10 mux from MuxSysPll1Div5. */
1307     kCLOCK_LPUART10_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPUART10 mux from MuxSysPll2Out. */
1308     kCLOCK_LPUART10_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPUART10 mux from MuxSysPll2Pfd3. */
1309 
1310     /* LPUART11 */
1311     kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART11 mux from MuxOscRc48MDiv2. */
1312     kCLOCK_LPUART11_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART11 mux from MuxOsc24MOut. */
1313     kCLOCK_LPUART11_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART11 mux from MuxOscRc400M. */
1314     kCLOCK_LPUART11_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART11 mux from MuxOscRc16M. */
1315     kCLOCK_LPUART11_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< LPUART11 mux from MuxSysPll3Pfd3. */
1316     kCLOCK_LPUART11_ClockRoot_MuxSysPll3Out   = 5U, /*!< LPUART11 mux from MuxSysPll3Out. */
1317     kCLOCK_LPUART11_ClockRoot_MuxSysPll2Pfd3  = 6U, /*!< LPUART11 mux from MuxSysPll2Pfd3. */
1318     kCLOCK_LPUART11_ClockRoot_MuxSysPll1Div5  = 7U, /*!< LPUART11 mux from MuxSysPll1Div5. */
1319 
1320     /* LPUART12 */
1321     kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART12 mux from MuxOscRc48MDiv2. */
1322     kCLOCK_LPUART12_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPUART12 mux from MuxOsc24MOut. */
1323     kCLOCK_LPUART12_ClockRoot_MuxOscRc400M    = 2U, /*!< LPUART12 mux from MuxOscRc400M. */
1324     kCLOCK_LPUART12_ClockRoot_MuxOscRc16M     = 3U, /*!< LPUART12 mux from MuxOscRc16M. */
1325     kCLOCK_LPUART12_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< LPUART12 mux from MuxSysPll3Pfd3. */
1326     kCLOCK_LPUART12_ClockRoot_MuxSysPll3Out   = 5U, /*!< LPUART12 mux from MuxSysPll3Out. */
1327     kCLOCK_LPUART12_ClockRoot_MuxSysPll2Pfd3  = 6U, /*!< LPUART12 mux from MuxSysPll2Pfd3. */
1328     kCLOCK_LPUART12_ClockRoot_MuxSysPll1Div5  = 7U, /*!< LPUART12 mux from MuxSysPll1Div5. */
1329 
1330     /* LPI2C1 */
1331     kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C1 mux from MuxOscRc48MDiv2. */
1332     kCLOCK_LPI2C1_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPI2C1 mux from MuxOsc24MOut. */
1333     kCLOCK_LPI2C1_ClockRoot_MuxOscRc400M    = 2U, /*!< LPI2C1 mux from MuxOscRc400M. */
1334     kCLOCK_LPI2C1_ClockRoot_MuxOscRc16M     = 3U, /*!< LPI2C1 mux from MuxOscRc16M. */
1335     kCLOCK_LPI2C1_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPI2C1 mux from MuxSysPll3Div2. */
1336     kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPI2C1 mux from MuxSysPll1Div5. */
1337     kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPI2C1 mux from MuxSysPll2Out. */
1338     kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPI2C1 mux from MuxSysPll2Pfd3. */
1339 
1340     /* LPI2C2 */
1341     kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C2 mux from MuxOscRc48MDiv2. */
1342     kCLOCK_LPI2C2_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPI2C2 mux from MuxOsc24MOut. */
1343     kCLOCK_LPI2C2_ClockRoot_MuxOscRc400M    = 2U, /*!< LPI2C2 mux from MuxOscRc400M. */
1344     kCLOCK_LPI2C2_ClockRoot_MuxOscRc16M     = 3U, /*!< LPI2C2 mux from MuxOscRc16M. */
1345     kCLOCK_LPI2C2_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPI2C2 mux from MuxSysPll3Div2. */
1346     kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPI2C2 mux from MuxSysPll1Div5. */
1347     kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPI2C2 mux from MuxSysPll2Out. */
1348     kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPI2C2 mux from MuxSysPll2Pfd3. */
1349 
1350     /* LPI2C3 */
1351     kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C3 mux from MuxOscRc48MDiv2. */
1352     kCLOCK_LPI2C3_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPI2C3 mux from MuxOsc24MOut. */
1353     kCLOCK_LPI2C3_ClockRoot_MuxOscRc400M    = 2U, /*!< LPI2C3 mux from MuxOscRc400M. */
1354     kCLOCK_LPI2C3_ClockRoot_MuxOscRc16M     = 3U, /*!< LPI2C3 mux from MuxOscRc16M. */
1355     kCLOCK_LPI2C3_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPI2C3 mux from MuxSysPll3Div2. */
1356     kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPI2C3 mux from MuxSysPll1Div5. */
1357     kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPI2C3 mux from MuxSysPll2Out. */
1358     kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPI2C3 mux from MuxSysPll2Pfd3. */
1359 
1360     /* LPI2C4 */
1361     kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C4 mux from MuxOscRc48MDiv2. */
1362     kCLOCK_LPI2C4_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPI2C4 mux from MuxOsc24MOut. */
1363     kCLOCK_LPI2C4_ClockRoot_MuxOscRc400M    = 2U, /*!< LPI2C4 mux from MuxOscRc400M. */
1364     kCLOCK_LPI2C4_ClockRoot_MuxOscRc16M     = 3U, /*!< LPI2C4 mux from MuxOscRc16M. */
1365     kCLOCK_LPI2C4_ClockRoot_MuxSysPll3Div2  = 4U, /*!< LPI2C4 mux from MuxSysPll3Div2. */
1366     kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPI2C4 mux from MuxSysPll1Div5. */
1367     kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPI2C4 mux from MuxSysPll2Out. */
1368     kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPI2C4 mux from MuxSysPll2Pfd3. */
1369 
1370     /* LPI2C5 */
1371     kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C5 mux from MuxOscRc48MDiv2. */
1372     kCLOCK_LPI2C5_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPI2C5 mux from MuxOsc24MOut. */
1373     kCLOCK_LPI2C5_ClockRoot_MuxOscRc400M    = 2U, /*!< LPI2C5 mux from MuxOscRc400M. */
1374     kCLOCK_LPI2C5_ClockRoot_MuxOscRc16M     = 3U, /*!< LPI2C5 mux from MuxOscRc16M. */
1375     kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< LPI2C5 mux from MuxSysPll3Pfd3. */
1376     kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Out   = 5U, /*!< LPI2C5 mux from MuxSysPll3Out. */
1377     kCLOCK_LPI2C5_ClockRoot_MuxSysPll2Pfd3  = 6U, /*!< LPI2C5 mux from MuxSysPll2Pfd3. */
1378     kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Div5  = 7U, /*!< LPI2C5 mux from MuxSysPll1Div5. */
1379 
1380     /* LPI2C6 */
1381     kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C6 mux from MuxOscRc48MDiv2. */
1382     kCLOCK_LPI2C6_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPI2C6 mux from MuxOsc24MOut. */
1383     kCLOCK_LPI2C6_ClockRoot_MuxOscRc400M    = 2U, /*!< LPI2C6 mux from MuxOscRc400M. */
1384     kCLOCK_LPI2C6_ClockRoot_MuxOscRc16M     = 3U, /*!< LPI2C6 mux from MuxOscRc16M. */
1385     kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< LPI2C6 mux from MuxSysPll3Pfd3. */
1386     kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Out   = 5U, /*!< LPI2C6 mux from MuxSysPll3Out. */
1387     kCLOCK_LPI2C6_ClockRoot_MuxSysPll2Pfd3  = 6U, /*!< LPI2C6 mux from MuxSysPll2Pfd3. */
1388     kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Div5  = 7U, /*!< LPI2C6 mux from MuxSysPll1Div5. */
1389 
1390     /* LPSPI1 */
1391     kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI1 mux from MuxOscRc48MDiv2. */
1392     kCLOCK_LPSPI1_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPSPI1 mux from MuxOsc24MOut. */
1393     kCLOCK_LPSPI1_ClockRoot_MuxOscRc400M    = 2U, /*!< LPSPI1 mux from MuxOscRc400M. */
1394     kCLOCK_LPSPI1_ClockRoot_MuxOscRc16M     = 3U, /*!< LPSPI1 mux from MuxOscRc16M. */
1395     kCLOCK_LPSPI1_ClockRoot_MuxSysPll3Pfd2  = 4U, /*!< LPSPI1 mux from MuxSysPll3Pfd2. */
1396     kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPSPI1 mux from MuxSysPll1Div5. */
1397     kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPSPI1 mux from MuxSysPll2Out. */
1398     kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPSPI1 mux from MuxSysPll2Pfd3. */
1399 
1400     /* LPSPI2 */
1401     kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI2 mux from MuxOscRc48MDiv2. */
1402     kCLOCK_LPSPI2_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPSPI2 mux from MuxOsc24MOut. */
1403     kCLOCK_LPSPI2_ClockRoot_MuxOscRc400M    = 2U, /*!< LPSPI2 mux from MuxOscRc400M. */
1404     kCLOCK_LPSPI2_ClockRoot_MuxOscRc16M     = 3U, /*!< LPSPI2 mux from MuxOscRc16M. */
1405     kCLOCK_LPSPI2_ClockRoot_MuxSysPll3Pfd2  = 4U, /*!< LPSPI2 mux from MuxSysPll3Pfd2. */
1406     kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPSPI2 mux from MuxSysPll1Div5. */
1407     kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPSPI2 mux from MuxSysPll2Out. */
1408     kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPSPI2 mux from MuxSysPll2Pfd3. */
1409 
1410     /* LPSPI3 */
1411     kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI3 mux from MuxOscRc48MDiv2. */
1412     kCLOCK_LPSPI3_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPSPI3 mux from MuxOsc24MOut. */
1413     kCLOCK_LPSPI3_ClockRoot_MuxOscRc400M    = 2U, /*!< LPSPI3 mux from MuxOscRc400M. */
1414     kCLOCK_LPSPI3_ClockRoot_MuxOscRc16M     = 3U, /*!< LPSPI3 mux from MuxOscRc16M. */
1415     kCLOCK_LPSPI3_ClockRoot_MuxSysPll3Pfd2  = 4U, /*!< LPSPI3 mux from MuxSysPll3Pfd2. */
1416     kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPSPI3 mux from MuxSysPll1Div5. */
1417     kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPSPI3 mux from MuxSysPll2Out. */
1418     kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPSPI3 mux from MuxSysPll2Pfd3. */
1419 
1420     /* LPSPI4 */
1421     kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI4 mux from MuxOscRc48MDiv2. */
1422     kCLOCK_LPSPI4_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPSPI4 mux from MuxOsc24MOut. */
1423     kCLOCK_LPSPI4_ClockRoot_MuxOscRc400M    = 2U, /*!< LPSPI4 mux from MuxOscRc400M. */
1424     kCLOCK_LPSPI4_ClockRoot_MuxOscRc16M     = 3U, /*!< LPSPI4 mux from MuxOscRc16M. */
1425     kCLOCK_LPSPI4_ClockRoot_MuxSysPll3Pfd2  = 4U, /*!< LPSPI4 mux from MuxSysPll3Pfd2. */
1426     kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Div5  = 5U, /*!< LPSPI4 mux from MuxSysPll1Div5. */
1427     kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Out   = 6U, /*!< LPSPI4 mux from MuxSysPll2Out. */
1428     kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< LPSPI4 mux from MuxSysPll2Pfd3. */
1429 
1430     /* LPSPI5 */
1431     kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI5 mux from MuxOscRc48MDiv2. */
1432     kCLOCK_LPSPI5_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPSPI5 mux from MuxOsc24MOut. */
1433     kCLOCK_LPSPI5_ClockRoot_MuxOscRc400M    = 2U, /*!< LPSPI5 mux from MuxOscRc400M. */
1434     kCLOCK_LPSPI5_ClockRoot_MuxOscRc16M     = 3U, /*!< LPSPI5 mux from MuxOscRc16M. */
1435     kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< LPSPI5 mux from MuxSysPll3Pfd3. */
1436     kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Out   = 5U, /*!< LPSPI5 mux from MuxSysPll3Out. */
1437     kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd2  = 6U, /*!< LPSPI5 mux from MuxSysPll3Pfd2. */
1438     kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Div5  = 7U, /*!< LPSPI5 mux from MuxSysPll1Div5. */
1439 
1440     /* LPSPI6 */
1441     kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI6 mux from MuxOscRc48MDiv2. */
1442     kCLOCK_LPSPI6_ClockRoot_MuxOsc24MOut    = 1U, /*!< LPSPI6 mux from MuxOsc24MOut. */
1443     kCLOCK_LPSPI6_ClockRoot_MuxOscRc400M    = 2U, /*!< LPSPI6 mux from MuxOscRc400M. */
1444     kCLOCK_LPSPI6_ClockRoot_MuxOscRc16M     = 3U, /*!< LPSPI6 mux from MuxOscRc16M. */
1445     kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< LPSPI6 mux from MuxSysPll3Pfd3. */
1446     kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Out   = 5U, /*!< LPSPI6 mux from MuxSysPll3Out. */
1447     kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd2  = 6U, /*!< LPSPI6 mux from MuxSysPll3Pfd2. */
1448     kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Div5  = 7U, /*!< LPSPI6 mux from MuxSysPll1Div5. */
1449 
1450     /* EMV1 */
1451     kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< EMV1 mux from MuxOscRc48MDiv2. */
1452     kCLOCK_EMV1_ClockRoot_MuxOsc24MOut    = 1U, /*!< EMV1 mux from MuxOsc24MOut. */
1453     kCLOCK_EMV1_ClockRoot_MuxOscRc400M    = 2U, /*!< EMV1 mux from MuxOscRc400M. */
1454     kCLOCK_EMV1_ClockRoot_MuxOscRc16M     = 3U, /*!< EMV1 mux from MuxOscRc16M. */
1455     kCLOCK_EMV1_ClockRoot_MuxSysPll3Div2  = 4U, /*!< EMV1 mux from MuxSysPll3Div2. */
1456     kCLOCK_EMV1_ClockRoot_MuxSysPll1Div5  = 5U, /*!< EMV1 mux from MuxSysPll1Div5. */
1457     kCLOCK_EMV1_ClockRoot_MuxSysPll2Out   = 6U, /*!< EMV1 mux from MuxSysPll2Out. */
1458     kCLOCK_EMV1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< EMV1 mux from MuxSysPll2Pfd3. */
1459 
1460     /* EMV2 */
1461     kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< EMV2 mux from MuxOscRc48MDiv2. */
1462     kCLOCK_EMV2_ClockRoot_MuxOsc24MOut    = 1U, /*!< EMV2 mux from MuxOsc24MOut. */
1463     kCLOCK_EMV2_ClockRoot_MuxOscRc400M    = 2U, /*!< EMV2 mux from MuxOscRc400M. */
1464     kCLOCK_EMV2_ClockRoot_MuxOscRc16M     = 3U, /*!< EMV2 mux from MuxOscRc16M. */
1465     kCLOCK_EMV2_ClockRoot_MuxSysPll3Div2  = 4U, /*!< EMV2 mux from MuxSysPll3Div2. */
1466     kCLOCK_EMV2_ClockRoot_MuxSysPll1Div5  = 5U, /*!< EMV2 mux from MuxSysPll1Div5. */
1467     kCLOCK_EMV2_ClockRoot_MuxSysPll2Out   = 6U, /*!< EMV2 mux from MuxSysPll2Out. */
1468     kCLOCK_EMV2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< EMV2 mux from MuxSysPll2Pfd3. */
1469 
1470     /* ENET1 */
1471     kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET1 mux from MuxOscRc48MDiv2. */
1472     kCLOCK_ENET1_ClockRoot_MuxOsc24MOut    = 1U, /*!< ENET1 mux from MuxOsc24MOut. */
1473     kCLOCK_ENET1_ClockRoot_MuxOscRc400M    = 2U, /*!< ENET1 mux from MuxOscRc400M. */
1474     kCLOCK_ENET1_ClockRoot_MuxOscRc16M     = 3U, /*!< ENET1 mux from MuxOscRc16M. */
1475     kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2  = 4U, /*!< ENET1 mux from MuxSysPll1Div2. */
1476     kCLOCK_ENET1_ClockRoot_MuxAudioPllOut  = 5U, /*!< ENET1 mux from MuxAudioPllOut. */
1477     kCLOCK_ENET1_ClockRoot_MuxSysPll1Div5  = 6U, /*!< ENET1 mux from MuxSysPll1Div5. */
1478     kCLOCK_ENET1_ClockRoot_MuxSysPll2Pfd1  = 7U, /*!< ENET1 mux from MuxSysPll2Pfd1. */
1479 
1480     /* ENET2 */
1481     kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET2 mux from MuxOscRc48MDiv2. */
1482     kCLOCK_ENET2_ClockRoot_MuxOsc24MOut    = 1U, /*!< ENET2 mux from MuxOsc24MOut. */
1483     kCLOCK_ENET2_ClockRoot_MuxOscRc400M    = 2U, /*!< ENET2 mux from MuxOscRc400M. */
1484     kCLOCK_ENET2_ClockRoot_MuxOscRc16M     = 3U, /*!< ENET2 mux from MuxOscRc16M. */
1485     kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2  = 4U, /*!< ENET2 mux from MuxSysPll1Div2. */
1486     kCLOCK_ENET2_ClockRoot_MuxAudioPllOut  = 5U, /*!< ENET2 mux from MuxAudioPllOut. */
1487     kCLOCK_ENET2_ClockRoot_MuxSysPll1Div5  = 6U, /*!< ENET2 mux from MuxSysPll1Div5. */
1488     kCLOCK_ENET2_ClockRoot_MuxSysPll2Pfd1  = 7U, /*!< ENET2 mux from MuxSysPll2Pfd1. */
1489 
1490     /* ENET_25M */
1491     kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET_25M mux from MuxOscRc48MDiv2. */
1492     kCLOCK_ENET_25M_ClockRoot_MuxOsc24MOut    = 1U, /*!< ENET_25M mux from MuxOsc24MOut. */
1493     kCLOCK_ENET_25M_ClockRoot_MuxOscRc400M    = 2U, /*!< ENET_25M mux from MuxOscRc400M. */
1494     kCLOCK_ENET_25M_ClockRoot_MuxOscRc16M     = 3U, /*!< ENET_25M mux from MuxOscRc16M. */
1495     kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div2  = 4U, /*!< ENET_25M mux from MuxSysPll1Div2. */
1496     kCLOCK_ENET_25M_ClockRoot_MuxAudioPllOut  = 5U, /*!< ENET_25M mux from MuxAudioPllOut. */
1497     kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div5  = 6U, /*!< ENET_25M mux from MuxSysPll1Div5. */
1498     kCLOCK_ENET_25M_ClockRoot_MuxSysPll2Pfd1  = 7U, /*!< ENET_25M mux from MuxSysPll2Pfd1. */
1499 
1500     /* ENET_TIMER1 */
1501     kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET_TIMER1 mux from MuxOscRc48MDiv2. */
1502     kCLOCK_ENET_TIMER1_ClockRoot_MuxOsc24MOut    = 1U, /*!< ENET_TIMER1 mux from MuxOsc24MOut. */
1503     kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc400M    = 2U, /*!< ENET_TIMER1 mux from MuxOscRc400M. */
1504     kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc16M     = 3U, /*!< ENET_TIMER1 mux from MuxOscRc16M. */
1505     kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div2  = 4U, /*!< ENET_TIMER1 mux from MuxSysPll1Div2. */
1506     kCLOCK_ENET_TIMER1_ClockRoot_MuxAudioPllOut  = 5U, /*!< ENET_TIMER1 mux from MuxAudioPllOut. */
1507     kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div5  = 6U, /*!< ENET_TIMER1 mux from MuxSysPll1Div5. */
1508     kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll2Pfd1  = 7U, /*!< ENET_TIMER1 mux from MuxSysPll2Pfd1. */
1509 
1510     /* ENET_TIMER2 */
1511     kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET_TIMER2 mux from MuxOscRc48MDiv2. */
1512     kCLOCK_ENET_TIMER2_ClockRoot_MuxOsc24MOut    = 1U, /*!< ENET_TIMER2 mux from MuxOsc24MOut. */
1513     kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc400M    = 2U, /*!< ENET_TIMER2 mux from MuxOscRc400M. */
1514     kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc16M     = 3U, /*!< ENET_TIMER2 mux from MuxOscRc16M. */
1515     kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div2  = 4U, /*!< ENET_TIMER2 mux from MuxSysPll1Div2. */
1516     kCLOCK_ENET_TIMER2_ClockRoot_MuxAudioPllOut  = 5U, /*!< ENET_TIMER2 mux from MuxAudioPllOut. */
1517     kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div5  = 6U, /*!< ENET_TIMER2 mux from MuxSysPll1Div5. */
1518     kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll2Pfd1  = 7U, /*!< ENET_TIMER2 mux from MuxSysPll2Pfd1. */
1519 
1520     /* USDHC1 */
1521     kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< USDHC1 mux from MuxOscRc48MDiv2. */
1522     kCLOCK_USDHC1_ClockRoot_MuxOsc24MOut    = 1U, /*!< USDHC1 mux from MuxOsc24MOut. */
1523     kCLOCK_USDHC1_ClockRoot_MuxOscRc400M    = 2U, /*!< USDHC1 mux from MuxOscRc400M. */
1524     kCLOCK_USDHC1_ClockRoot_MuxOscRc16M     = 3U, /*!< USDHC1 mux from MuxOscRc16M. */
1525     kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2  = 4U, /*!< USDHC1 mux from MuxSysPll2Pfd2. */
1526     kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd0  = 5U, /*!< USDHC1 mux from MuxSysPll2Pfd0. */
1527     kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5  = 6U, /*!< USDHC1 mux from MuxSysPll1Div5. */
1528     kCLOCK_USDHC1_ClockRoot_MuxArmPllOut    = 7U, /*!< USDHC1 mux from MuxArmPllOut. */
1529 
1530     /* USDHC2 */
1531     kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< USDHC2 mux from MuxOscRc48MDiv2. */
1532     kCLOCK_USDHC2_ClockRoot_MuxOsc24MOut    = 1U, /*!< USDHC2 mux from MuxOsc24MOut. */
1533     kCLOCK_USDHC2_ClockRoot_MuxOscRc400M    = 2U, /*!< USDHC2 mux from MuxOscRc400M. */
1534     kCLOCK_USDHC2_ClockRoot_MuxOscRc16M     = 3U, /*!< USDHC2 mux from MuxOscRc16M. */
1535     kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2  = 4U, /*!< USDHC2 mux from MuxSysPll2Pfd2. */
1536     kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd0  = 5U, /*!< USDHC2 mux from MuxSysPll2Pfd0. */
1537     kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5  = 6U, /*!< USDHC2 mux from MuxSysPll1Div5. */
1538     kCLOCK_USDHC2_ClockRoot_MuxArmPllOut    = 7U, /*!< USDHC2 mux from MuxArmPllOut. */
1539 
1540     /* ASRC */
1541     kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ASRC mux from MuxOscRc48MDiv2. */
1542     kCLOCK_ASRC_ClockRoot_MuxOsc24MOut    = 1U, /*!< ASRC mux from MuxOsc24MOut. */
1543     kCLOCK_ASRC_ClockRoot_MuxOscRc400M    = 2U, /*!< ASRC mux from MuxOscRc400M. */
1544     kCLOCK_ASRC_ClockRoot_MuxOscRc16M     = 3U, /*!< ASRC mux from MuxOscRc16M. */
1545     kCLOCK_ASRC_ClockRoot_MuxSysPll1Div5  = 4U, /*!< ASRC mux from MuxSysPll1Div5. */
1546     kCLOCK_ASRC_ClockRoot_MuxSysPll3Div2  = 5U, /*!< ASRC mux from MuxSysPll3Div2. */
1547     kCLOCK_ASRC_ClockRoot_MuxAudioPllOut  = 6U, /*!< ASRC mux from MuxAudioPllOut. */
1548     kCLOCK_ASRC_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< ASRC mux from MuxSysPll2Pfd3. */
1549 
1550     /* MQS */
1551     kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< MQS mux from MuxOscRc48MDiv2. */
1552     kCLOCK_MQS_ClockRoot_MuxOsc24MOut    = 1U, /*!< MQS mux from MuxOsc24MOut. */
1553     kCLOCK_MQS_ClockRoot_MuxOscRc400M    = 2U, /*!< MQS mux from MuxOscRc400M. */
1554     kCLOCK_MQS_ClockRoot_MuxOscRc16M     = 3U, /*!< MQS mux from MuxOscRc16M. */
1555     kCLOCK_MQS_ClockRoot_MuxSysPll1Div5  = 4U, /*!< MQS mux from MuxSysPll1Div5. */
1556     kCLOCK_MQS_ClockRoot_MuxSysPll3Div2  = 5U, /*!< MQS mux from MuxSysPll3Div2. */
1557     kCLOCK_MQS_ClockRoot_MuxAudioPllOut  = 6U, /*!< MQS mux from MuxAudioPllOut. */
1558     kCLOCK_MQS_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< MQS mux from MuxSysPll2Pfd3. */
1559 
1560     /* MIC */
1561     kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< MIC mux from MuxOscRc48MDiv2. */
1562     kCLOCK_MIC_ClockRoot_MuxOsc24MOut    = 1U, /*!< MIC mux from MuxOsc24MOut. */
1563     kCLOCK_MIC_ClockRoot_MuxOscRc400M    = 2U, /*!< MIC mux from MuxOscRc400M. */
1564     kCLOCK_MIC_ClockRoot_MuxOscRc16M     = 3U, /*!< MIC mux from MuxOscRc16M. */
1565     kCLOCK_MIC_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< MIC mux from MuxSysPll3Pfd3. */
1566     kCLOCK_MIC_ClockRoot_MuxSysPll3Out   = 5U, /*!< MIC mux from MuxSysPll3Out. */
1567     kCLOCK_MIC_ClockRoot_MuxAudioPllOut  = 6U, /*!< MIC mux from MuxAudioPllOut. */
1568     kCLOCK_MIC_ClockRoot_MuxSysPll1Div5  = 7U, /*!< MIC mux from MuxSysPll1Div5. */
1569 
1570     /* SPDIF */
1571     kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SPDIF mux from MuxOscRc48MDiv2. */
1572     kCLOCK_SPDIF_ClockRoot_MuxOsc24MOut    = 1U, /*!< SPDIF mux from MuxOsc24MOut. */
1573     kCLOCK_SPDIF_ClockRoot_MuxOscRc400M    = 2U, /*!< SPDIF mux from MuxOscRc400M. */
1574     kCLOCK_SPDIF_ClockRoot_MuxOscRc16M     = 3U, /*!< SPDIF mux from MuxOscRc16M. */
1575     kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut  = 4U, /*!< SPDIF mux from MuxAudioPllOut. */
1576     kCLOCK_SPDIF_ClockRoot_MuxSysPll3Out   = 5U, /*!< SPDIF mux from MuxSysPll3Out. */
1577     kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2  = 6U, /*!< SPDIF mux from MuxSysPll3Pfd2. */
1578     kCLOCK_SPDIF_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< SPDIF mux from MuxSysPll2Pfd3. */
1579 
1580     /* SAI1 */
1581     kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SAI1 mux from MuxOscRc48MDiv2. */
1582     kCLOCK_SAI1_ClockRoot_MuxOsc24MOut    = 1U, /*!< SAI1 mux from MuxOsc24MOut. */
1583     kCLOCK_SAI1_ClockRoot_MuxOscRc400M    = 2U, /*!< SAI1 mux from MuxOscRc400M. */
1584     kCLOCK_SAI1_ClockRoot_MuxOscRc16M     = 3U, /*!< SAI1 mux from MuxOscRc16M. */
1585     kCLOCK_SAI1_ClockRoot_MuxAudioPllOut  = 4U, /*!< SAI1 mux from MuxAudioPllOut. */
1586     kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2  = 5U, /*!< SAI1 mux from MuxSysPll3Pfd2. */
1587     kCLOCK_SAI1_ClockRoot_MuxSysPll1Div5  = 6U, /*!< SAI1 mux from MuxSysPll1Div5. */
1588     kCLOCK_SAI1_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< SAI1 mux from MuxSysPll2Pfd3. */
1589 
1590     /* SAI2 */
1591     kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SAI2 mux from MuxOscRc48MDiv2. */
1592     kCLOCK_SAI2_ClockRoot_MuxOsc24MOut    = 1U, /*!< SAI2 mux from MuxOsc24MOut. */
1593     kCLOCK_SAI2_ClockRoot_MuxOscRc400M    = 2U, /*!< SAI2 mux from MuxOscRc400M. */
1594     kCLOCK_SAI2_ClockRoot_MuxOscRc16M     = 3U, /*!< SAI2 mux from MuxOscRc16M. */
1595     kCLOCK_SAI2_ClockRoot_MuxAudioPllOut  = 4U, /*!< SAI2 mux from MuxAudioPllOut. */
1596     kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2  = 5U, /*!< SAI2 mux from MuxSysPll3Pfd2. */
1597     kCLOCK_SAI2_ClockRoot_MuxSysPll1Div5  = 6U, /*!< SAI2 mux from MuxSysPll1Div5. */
1598     kCLOCK_SAI2_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< SAI2 mux from MuxSysPll2Pfd3. */
1599 
1600     /* SAI3 */
1601     kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SAI3 mux from MuxOscRc48MDiv2. */
1602     kCLOCK_SAI3_ClockRoot_MuxOsc24MOut    = 1U, /*!< SAI3 mux from MuxOsc24MOut. */
1603     kCLOCK_SAI3_ClockRoot_MuxOscRc400M    = 2U, /*!< SAI3 mux from MuxOscRc400M. */
1604     kCLOCK_SAI3_ClockRoot_MuxOscRc16M     = 3U, /*!< SAI3 mux from MuxOscRc16M. */
1605     kCLOCK_SAI3_ClockRoot_MuxAudioPllOut  = 4U, /*!< SAI3 mux from MuxAudioPllOut. */
1606     kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2  = 5U, /*!< SAI3 mux from MuxSysPll3Pfd2. */
1607     kCLOCK_SAI3_ClockRoot_MuxSysPll1Div5  = 6U, /*!< SAI3 mux from MuxSysPll1Div5. */
1608     kCLOCK_SAI3_ClockRoot_MuxSysPll2Pfd3  = 7U, /*!< SAI3 mux from MuxSysPll2Pfd3. */
1609 
1610     /* SAI4 */
1611     kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SAI4 mux from MuxOscRc48MDiv2. */
1612     kCLOCK_SAI4_ClockRoot_MuxOsc24MOut    = 1U, /*!< SAI4 mux from MuxOsc24MOut. */
1613     kCLOCK_SAI4_ClockRoot_MuxOscRc400M    = 2U, /*!< SAI4 mux from MuxOscRc400M. */
1614     kCLOCK_SAI4_ClockRoot_MuxOscRc16M     = 3U, /*!< SAI4 mux from MuxOscRc16M. */
1615     kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd3  = 4U, /*!< SAI4 mux from MuxSysPll3Pfd3. */
1616     kCLOCK_SAI4_ClockRoot_MuxSysPll3Out   = 5U, /*!< SAI4 mux from MuxSysPll3Out. */
1617     kCLOCK_SAI4_ClockRoot_MuxAudioPllOut  = 6U, /*!< SAI4 mux from MuxAudioPllOut. */
1618     kCLOCK_SAI4_ClockRoot_MuxSysPll1Div5  = 7U, /*!< SAI4 mux from MuxSysPll1Div5. */
1619 
1620     /* GC355 */
1621     kCLOCK_GC355_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GC355 mux from MuxOscRc48MDiv2. */
1622     kCLOCK_GC355_ClockRoot_MuxOsc24MOut    = 1U, /*!< GC355 mux from MuxOsc24MOut. */
1623     kCLOCK_GC355_ClockRoot_MuxOscRc400M    = 2U, /*!< GC355 mux from MuxOscRc400M. */
1624     kCLOCK_GC355_ClockRoot_MuxOscRc16M     = 3U, /*!< GC355 mux from MuxOscRc16M. */
1625     kCLOCK_GC355_ClockRoot_MuxSysPll2Out   = 4U, /*!< GC355 mux from MuxSysPll2Out. */
1626     kCLOCK_GC355_ClockRoot_MuxSysPll2Pfd1  = 5U, /*!< GC355 mux from MuxSysPll2Pfd1. */
1627     kCLOCK_GC355_ClockRoot_MuxSysPll3Out   = 6U, /*!< GC355 mux from MuxSysPll3Out. */
1628     kCLOCK_GC355_ClockRoot_MuxVideoPllOut  = 7U, /*!< GC355 mux from MuxVideoPllOut. */
1629 
1630     /* LCDIF */
1631     kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LCDIF mux from MuxOscRc48MDiv2. */
1632     kCLOCK_LCDIF_ClockRoot_MuxOsc24MOut    = 1U, /*!< LCDIF mux from MuxOsc24MOut. */
1633     kCLOCK_LCDIF_ClockRoot_MuxOscRc400M    = 2U, /*!< LCDIF mux from MuxOscRc400M. */
1634     kCLOCK_LCDIF_ClockRoot_MuxOscRc16M     = 3U, /*!< LCDIF mux from MuxOscRc16M. */
1635     kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out   = 4U, /*!< LCDIF mux from MuxSysPll2Out. */
1636     kCLOCK_LCDIF_ClockRoot_MuxSysPll2Pfd2  = 5U, /*!< LCDIF mux from MuxSysPll2Pfd2. */
1637     kCLOCK_LCDIF_ClockRoot_MuxSysPll3Pfd0  = 6U, /*!< LCDIF mux from MuxSysPll3Pfd0. */
1638     kCLOCK_LCDIF_ClockRoot_MuxVideoPllOut  = 7U, /*!< LCDIF mux from MuxVideoPllOut. */
1639 
1640     /* LCDIFV2 */
1641     kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LCDIFV2 mux from MuxOscRc48MDiv2. */
1642     kCLOCK_LCDIFV2_ClockRoot_MuxOsc24MOut    = 1U, /*!< LCDIFV2 mux from MuxOsc24MOut. */
1643     kCLOCK_LCDIFV2_ClockRoot_MuxOscRc400M    = 2U, /*!< LCDIFV2 mux from MuxOscRc400M. */
1644     kCLOCK_LCDIFV2_ClockRoot_MuxOscRc16M     = 3U, /*!< LCDIFV2 mux from MuxOscRc16M. */
1645     kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Out   = 4U, /*!< LCDIFV2 mux from MuxSysPll2Out. */
1646     kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Pfd2  = 5U, /*!< LCDIFV2 mux from MuxSysPll2Pfd2. */
1647     kCLOCK_LCDIFV2_ClockRoot_MuxSysPll3Pfd0  = 6U, /*!< LCDIFV2 mux from MuxSysPll3Pfd0. */
1648     kCLOCK_LCDIFV2_ClockRoot_MuxVideoPllOut  = 7U, /*!< LCDIFV2 mux from MuxVideoPllOut. */
1649 
1650     /* MIPI_REF */
1651     kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< MIPI_REF mux from MuxOscRc48MDiv2. */
1652     kCLOCK_MIPI_REF_ClockRoot_MuxOsc24MOut    = 1U, /*!< MIPI_REF mux from MuxOsc24MOut. */
1653     kCLOCK_MIPI_REF_ClockRoot_MuxOscRc400M    = 2U, /*!< MIPI_REF mux from MuxOscRc400M. */
1654     kCLOCK_MIPI_REF_ClockRoot_MuxOscRc16M     = 3U, /*!< MIPI_REF mux from MuxOscRc16M. */
1655     kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Out   = 4U, /*!< MIPI_REF mux from MuxSysPll2Out. */
1656     kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Pfd0  = 5U, /*!< MIPI_REF mux from MuxSysPll2Pfd0. */
1657     kCLOCK_MIPI_REF_ClockRoot_MuxSysPll3Pfd0  = 6U, /*!< MIPI_REF mux from MuxSysPll3Pfd0. */
1658     kCLOCK_MIPI_REF_ClockRoot_MuxVideoPllOut  = 7U, /*!< MIPI_REF mux from MuxVideoPllOut. */
1659 
1660     /* MIPI_ESC */
1661     kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< MIPI_ESC mux from MuxOscRc48MDiv2. */
1662     kCLOCK_MIPI_ESC_ClockRoot_MuxOsc24MOut    = 1U, /*!< MIPI_ESC mux from MuxOsc24MOut. */
1663     kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc400M    = 2U, /*!< MIPI_ESC mux from MuxOscRc400M. */
1664     kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc16M     = 3U, /*!< MIPI_ESC mux from MuxOscRc16M. */
1665     kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Out   = 4U, /*!< MIPI_ESC mux from MuxSysPll2Out. */
1666     kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Pfd0  = 5U, /*!< MIPI_ESC mux from MuxSysPll2Pfd0. */
1667     kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll3Pfd0  = 6U, /*!< MIPI_ESC mux from MuxSysPll3Pfd0. */
1668     kCLOCK_MIPI_ESC_ClockRoot_MuxVideoPllOut  = 7U, /*!< MIPI_ESC mux from MuxVideoPllOut. */
1669 
1670     /* CSI2 */
1671     kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSI2 mux from MuxOscRc48MDiv2. */
1672     kCLOCK_CSI2_ClockRoot_MuxOsc24MOut    = 1U, /*!< CSI2 mux from MuxOsc24MOut. */
1673     kCLOCK_CSI2_ClockRoot_MuxOscRc400M    = 2U, /*!< CSI2 mux from MuxOscRc400M. */
1674     kCLOCK_CSI2_ClockRoot_MuxOscRc16M     = 3U, /*!< CSI2 mux from MuxOscRc16M. */
1675     kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd2  = 4U, /*!< CSI2 mux from MuxSysPll2Pfd2. */
1676     kCLOCK_CSI2_ClockRoot_MuxSysPll3Out   = 5U, /*!< CSI2 mux from MuxSysPll3Out. */
1677     kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd0  = 6U, /*!< CSI2 mux from MuxSysPll2Pfd0. */
1678     kCLOCK_CSI2_ClockRoot_MuxVideoPllOut  = 7U, /*!< CSI2 mux from MuxVideoPllOut. */
1679 
1680     /* CSI2_ESC */
1681     kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSI2_ESC mux from MuxOscRc48MDiv2. */
1682     kCLOCK_CSI2_ESC_ClockRoot_MuxOsc24MOut    = 1U, /*!< CSI2_ESC mux from MuxOsc24MOut. */
1683     kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc400M    = 2U, /*!< CSI2_ESC mux from MuxOscRc400M. */
1684     kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc16M     = 3U, /*!< CSI2_ESC mux from MuxOscRc16M. */
1685     kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd2  = 4U, /*!< CSI2_ESC mux from MuxSysPll2Pfd2. */
1686     kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll3Out   = 5U, /*!< CSI2_ESC mux from MuxSysPll3Out. */
1687     kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd0  = 6U, /*!< CSI2_ESC mux from MuxSysPll2Pfd0. */
1688     kCLOCK_CSI2_ESC_ClockRoot_MuxVideoPllOut  = 7U, /*!< CSI2_ESC mux from MuxVideoPllOut. */
1689 
1690     /* CSI2_UI */
1691     kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSI2_UI mux from MuxOscRc48MDiv2. */
1692     kCLOCK_CSI2_UI_ClockRoot_MuxOsc24MOut    = 1U, /*!< CSI2_UI mux from MuxOsc24MOut. */
1693     kCLOCK_CSI2_UI_ClockRoot_MuxOscRc400M    = 2U, /*!< CSI2_UI mux from MuxOscRc400M. */
1694     kCLOCK_CSI2_UI_ClockRoot_MuxOscRc16M     = 3U, /*!< CSI2_UI mux from MuxOscRc16M. */
1695     kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd2  = 4U, /*!< CSI2_UI mux from MuxSysPll2Pfd2. */
1696     kCLOCK_CSI2_UI_ClockRoot_MuxSysPll3Out   = 5U, /*!< CSI2_UI mux from MuxSysPll3Out. */
1697     kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd0  = 6U, /*!< CSI2_UI mux from MuxSysPll2Pfd0. */
1698     kCLOCK_CSI2_UI_ClockRoot_MuxVideoPllOut  = 7U, /*!< CSI2_UI mux from MuxVideoPllOut. */
1699 
1700     /* CSI */
1701     kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSI mux from MuxOscRc48MDiv2. */
1702     kCLOCK_CSI_ClockRoot_MuxOsc24MOut    = 1U, /*!< CSI mux from MuxOsc24MOut. */
1703     kCLOCK_CSI_ClockRoot_MuxOscRc400M    = 2U, /*!< CSI mux from MuxOscRc400M. */
1704     kCLOCK_CSI_ClockRoot_MuxOscRc16M     = 3U, /*!< CSI mux from MuxOscRc16M. */
1705     kCLOCK_CSI_ClockRoot_MuxSysPll2Pfd2  = 4U, /*!< CSI mux from MuxSysPll2Pfd2. */
1706     kCLOCK_CSI_ClockRoot_MuxSysPll3Out   = 5U, /*!< CSI mux from MuxSysPll3Out. */
1707     kCLOCK_CSI_ClockRoot_MuxSysPll3Pfd1  = 6U, /*!< CSI mux from MuxSysPll3Pfd1. */
1708     kCLOCK_CSI_ClockRoot_MuxVideoPllOut  = 7U, /*!< CSI mux from MuxVideoPllOut. */
1709 
1710     /* CKO1 */
1711     kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CKO1 mux from MuxOscRc48MDiv2. */
1712     kCLOCK_CKO1_ClockRoot_MuxOsc24MOut    = 1U, /*!< CKO1 mux from MuxOsc24MOut. */
1713     kCLOCK_CKO1_ClockRoot_MuxOscRc400M    = 2U, /*!< CKO1 mux from MuxOscRc400M. */
1714     kCLOCK_CKO1_ClockRoot_MuxOscRc16M     = 3U, /*!< CKO1 mux from MuxOscRc16M. */
1715     kCLOCK_CKO1_ClockRoot_MuxSysPll2Pfd2  = 4U, /*!< CKO1 mux from MuxSysPll2Pfd2. */
1716     kCLOCK_CKO1_ClockRoot_MuxSysPll2Out   = 5U, /*!< CKO1 mux from MuxSysPll2Out. */
1717     kCLOCK_CKO1_ClockRoot_MuxSysPll3Pfd1  = 6U, /*!< CKO1 mux from MuxSysPll3Pfd1. */
1718     kCLOCK_CKO1_ClockRoot_MuxSysPll1Div5  = 7U, /*!< CKO1 mux from MuxSysPll1Div5. */
1719 
1720     /* CKO2 */
1721     kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CKO2 mux from MuxOscRc48MDiv2. */
1722     kCLOCK_CKO2_ClockRoot_MuxOsc24MOut    = 1U, /*!< CKO2 mux from MuxOsc24MOut. */
1723     kCLOCK_CKO2_ClockRoot_MuxOscRc400M    = 2U, /*!< CKO2 mux from MuxOscRc400M. */
1724     kCLOCK_CKO2_ClockRoot_MuxOscRc16M     = 3U, /*!< CKO2 mux from MuxOscRc16M. */
1725     kCLOCK_CKO2_ClockRoot_MuxSysPll2Pfd3  = 4U, /*!< CKO2 mux from MuxSysPll2Pfd3. */
1726     kCLOCK_CKO2_ClockRoot_MuxOscRc48M     = 5U, /*!< CKO2 mux from MuxOscRc48M. */
1727     kCLOCK_CKO2_ClockRoot_MuxSysPll3Pfd1  = 6U, /*!< CKO2 mux from MuxSysPll3Pfd1. */
1728     kCLOCK_CKO2_ClockRoot_MuxAudioPllOut  = 7U, /*!< CKO2 mux from MuxAudioPllOut. */
1729 } clock_root_mux_source_t;
1730 
1731 /*!
1732  * @brief Clock group enumeration.
1733  */
1734 typedef enum _clock_group
1735 {
1736     kCLOCK_Group_FlexRAM = 0, /*!< FlexRAM clock group. */
1737     kCLOCK_Group_MipiDsi = 1, /*!< Mipi Dsi clock group. */
1738     kCLOCK_Group_Last,        /*!< Last clock group. */
1739 } clock_group_t;
1740 
1741 /*!
1742  * @brief The structure used to configure clock group.
1743  */
1744 typedef struct _clock_group_config
1745 {
1746     bool clockOff;     /*!< Turn off the clock. */
1747     uint16_t resetDiv; /*!< resetDiv + 1 should be common multiple of all dividers, valid range 0 ~ 255. */
1748     uint8_t div0;      /*!< Divide root clock by div0 + 1, valid range: 0 ~ 15. */
1749 } clock_group_config_t;
1750 
1751 #define clock_ip_name_t clock_lpcg_t
1752 
1753 #if (__CORTEX_M == 7)
1754 #define CLOCK_GetCpuClkFreq CLOCK_GetM7Freq
1755 #else
1756 #define CLOCK_GetCpuClkFreq CLOCK_GetM4Freq
1757 #endif
1758 
1759 #define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */
1760 
1761 /* uncomment the following line if want to use OBS to retrieve frequency */
1762 /* #define GET_FREQ_FROM_OBS */
1763 
1764 /*! @brief OSC 24M sorce select */
1765 typedef enum _clock_osc
1766 {
1767     kCLOCK_RcOsc   = 0U, /*!< On chip OSC. */
1768     kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */
1769 } clock_osc_t;
1770 
1771 /*! @brief Clock gate value */
1772 typedef enum _clock_gate_value
1773 {
1774     kCLOCK_Off = (int)~CCM_LPCG_DIRECT_ON_MASK, /*!< Clock is off. */
1775     kCLOCK_On  = CCM_LPCG_DIRECT_ON_MASK,       /*!< Clock is on*/
1776 } clock_gate_value_t;
1777 
1778 /*! @brief System clock mode */
1779 typedef enum _clock_mode_t
1780 {
1781     kCLOCK_ModeRun  = 0U, /*!< Remain in run mode. */
1782     kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */
1783     kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */
1784 } clock_mode_t;
1785 
1786 /*! @brief USB clock source definition. */
1787 typedef enum _clock_usb_src
1788 {
1789     kCLOCK_Usb480M      = 0,                /*!< Use 480M.      */
1790     kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
1791                                             care the clock source. */
1792 } clock_usb_src_t;
1793 
1794 /*! @brief Source of the USB HS PHY. */
1795 typedef enum _clock_usb_phy_src
1796 {
1797     kCLOCK_Usbphy480M = 0, /*!< Use 480M.      */
1798 } clock_usb_phy_src_t;
1799 
1800 /*! @brief PLL clock source, bypass cloco source also */
1801 enum _clock_pll_clk_src
1802 {
1803     kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */
1804     kCLOCK_PllSrcClkPN  = 1U, /*!< Pll clock source CLK1_P and CLK1_N */
1805 };
1806 
1807 /*!
1808  * @brief PLL post divider enumeration.
1809  */
1810 typedef enum _clock_pll_post_div
1811 {
1812     kCLOCK_PllPostDiv8 = 0U, /*!< Divide by 8. */
1813     kCLOCK_PllPostDiv4 = 1U, /*!< Divide by 4. */
1814 } clock_pll_post_div_t;
1815 
1816 /*!
1817  * @brief PLL configuration for ARM.
1818  *
1819  * The output clock frequency is:
1820  *
1821  *  Fout=Fin*loopDivider /(2 * postDivider).
1822  *
1823  * Fin is always 24MHz.
1824  */
1825 typedef struct _clock_arm_pll_config
1826 {
1827     clock_pll_post_div_t postDivider; /*!< Post divider. */
1828     uint32_t loopDivider;             /*!< PLL loop divider. Valid range: 104-208. */
1829 } clock_arm_pll_config_t;
1830 
1831 /*! @brief PLL configuration for USB */
1832 typedef struct _clock_usb_pll_config
1833 {
1834     uint8_t loopDivider; /*!< PLL loop divider.
1835                               0 - Fout=Fref*20;
1836                               1 - Fout=Fref*22 */
1837     uint8_t src;         /*!< Pll clock source, reference _clock_pll_clk_src */
1838 
1839 } clock_usb_pll_config_t;
1840 
1841 /*! @brief Spread specturm configure Pll */
1842 typedef struct _clock_pll_ss_config
1843 {
1844     uint16_t stop; /*!< Spread spectrum stop value to get frequency change. */
1845     uint16_t step; /*!< Spread spectrum step value to get frequency change step. */
1846 } clock_pll_ss_config_t;
1847 
1848 /*! @brief PLL configure for Sys Pll2 */
1849 typedef struct _clock_sys_pll2_config
1850 {
1851     uint32_t mfd;              /*!< Denominator of spread spectrum */
1852     clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter,
1853                                  it can be NULL, if ssEnable is set to false */
1854     bool ssEnable;             /*!< Enable spread spectrum flag */
1855 } clock_sys_pll2_config_t;
1856 
1857 /*! @brief PLL configure for Sys Pll1 */
1858 typedef struct _clock_sys_pll1_config
1859 {
1860     bool pllDiv2En;            /*!< Enable Sys Pll1 divide-by-2 clock or not. */
1861     bool pllDiv5En;            /*!< Enable Sys Pll1 divide-by-5 clock or not. */
1862     clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter,
1863                                  it can be NULL, if ssEnable is set to false */
1864     bool ssEnable;             /*!< Enable spread spectrum flag */
1865 } clock_sys_pll1_config_t;
1866 
1867 /*! @brief PLL configuration for AUDIO and VIDEO */
1868 typedef struct _clock_audio_pll_config
1869 {
1870     uint8_t loopDivider;       /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
1871     uint8_t postDivider;       /*!< Divider after the PLL, 0x0=divided by 1, 0x1=divided by 2, 0x2=divided by 4,
1872                                     0x3=divided by 8, 0x4=divided by 16, 0x5=divided by 32.*/
1873     uint32_t numerator;        /*!< 30 bit numerator of fractional loop divider.*/
1874     uint32_t denominator;      /*!< 30 bit denominator of fractional loop divider */
1875     clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter,
1876                                  it can be NULL, if ssEnable is set to false */
1877     bool ssEnable;             /*!< Enable spread spectrum flag */
1878 } clock_av_pll_config_t, clock_audio_pll_config_t, clock_video_pll_config_t;
1879 
1880 /*!
1881  * @brief PLL configuration fro AUDIO PLL, SYSTEM PLL1 and VIDEO PLL.
1882  */
1883 typedef struct _clock_audio_pll_gpc_config
1884 {
1885     uint8_t loopDivider;       /*!< PLL loop divider.  */
1886     uint32_t numerator;        /*!< 30 bit numerator of fractional loop divider.*/
1887     uint32_t denominator;      /*!< 30 bit denominator of fractional loop divider */
1888     clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter,
1889                                  it can be NULL, if ssEnable is set to false */
1890     bool ssEnable;             /*!< Enable spread spectrum flag */
1891 } clock_audio_pll_gpc_config_t, clock_video_pll_gpc_config_t, clock_sys_pll1_gpc_config_t;
1892 
1893 /*! @brief PLL configuration for ENET */
1894 typedef struct _clock_enet_pll_config
1895 {
1896     bool enableClkOutput;    /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */
1897     bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET2 (ref_enetpll2). */
1898     uint8_t loopDivider;     /*!< Controls the frequency of the ENET0 reference clock.
1899                                   b00 25MHz
1900                                   b01 50MHz
1901                                   b10 100MHz (not 50% duty cycle)
1902                                   b11 125MHz */
1903     uint8_t src;             /*!< Pll clock source, reference _clock_pll_clk_src */
1904     bool enableClkOutput1;   /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
1905     uint8_t loopDivider1;    /*!< Controls the frequency of the ENET1 reference clock.
1906                                   b00 25MHz
1907                                   b01 50MHz
1908                                   b10 100MHz (not 50% duty cycle)
1909                                   b11 125MHz */
1910 } clock_enet_pll_config_t;
1911 
1912 /*! @brief Clock root configuration */
1913 typedef struct _clock_root_config_t
1914 {
1915     bool clockOff;
1916     uint8_t mux; /*!< See #clock_root_mux_source_t for details. */
1917     uint8_t div; /*!< it's the actual divider */
1918 } clock_root_config_t;
1919 
1920 /*! @brief Clock root configuration in SetPoint Mode */
1921 typedef struct _clock_root_setpoint_config_t
1922 {
1923     uint8_t grade; /*!< Indicate speed grade for each SetPoint */
1924     bool clockOff;
1925     uint8_t mux; /*!< See #clock_root_mux_source_t for details. */
1926     uint8_t div; /*!< it's the actual divider */
1927 } clock_root_setpoint_config_t;
1928 
1929 /*! @brief PLL name */
1930 typedef enum _clock_pll
1931 {
1932     kCLOCK_PllArm,          /*!< ARM PLL. */
1933     kCLOCK_PllSys1,         /*!< SYS1 PLL, it has a dedicated frequency of 1GHz. */
1934     kCLOCK_PllSys2,         /*!< SYS2 PLL, it has a dedicated frequency of 528MHz. */
1935     kCLOCK_PllSys3,         /*!< SYS3 PLL, it has a dedicated frequency of 480MHz. */
1936     kCLOCK_PllAudio,        /*!< Audio PLL. */
1937     kCLOCK_PllVideo,        /*!< Video PLL. */
1938     kCLOCK_PllInvalid = -1, /*!< Invalid value. */
1939 } clock_pll_t;
1940 
1941 #define PLL_PFD_COUNT 4
1942 /*! @brief PLL PFD name */
1943 typedef enum _clock_pfd
1944 {
1945     kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
1946     kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
1947     kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
1948     kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
1949 } clock_pfd_t;
1950 
1951 /*!
1952  * @brief The enumeration of control mode.
1953  *
1954  */
1955 typedef enum _clock_control_mode
1956 {
1957     kCLOCK_SoftwareMode = 0U, /*!< Software control mode. */
1958     kCLOCK_GpcMode,           /*!< GPC control mode. */
1959 } clock_control_mode_t;
1960 
1961 /*!
1962  * @brief The enumeration of 24MHz crystal oscillator mode.
1963  */
1964 typedef enum _clock_24MOsc_mode
1965 {
1966     kCLOCK_24MOscHighGainMode = 0U, /*!< 24MHz crystal oscillator work as high gain mode. */
1967     kCLOCK_24MOscBypassMode   = 1U, /*!< 24MHz crystal oscillator work as bypass mode. */
1968     kCLOCK_24MOscLowPowerMode = 2U, /*!< 24MHz crystal oscillator work as low power mode. */
1969 } clock_24MOsc_mode_t;
1970 
1971 /*!
1972  * @brief The enumeration of 16MHz RC oscillator clock source.
1973  */
1974 typedef enum _clock_16MOsc_source
1975 {
1976     kCLOCK_16MOscSourceFrom16MOsc = 0U, /*!< Source from 16MHz RC oscialltor. */
1977     kCLOCK_16MOscSourceFrom24MOsc = 1U, /*!< Source from 24MHz crystal oscillator. */
1978 } clock_16MOsc_source_t;
1979 
1980 /*!
1981  * @brief The enumeration of 1MHz output clock behavior, including disabling 1MHz output,
1982  * enabling locked 1MHz clock output, and enabling free-running 1MHz clock output.
1983  */
1984 typedef enum _clock_1MHzOut_behavior
1985 {
1986     kCLOCK_1MHzOutDisable               = 0U, /*!< Disable 1MHz output clock. */
1987     kCLOCK_1MHzOutEnableLocked1Mhz      = 1U, /*!< Enable 1MHz output clock, and select locked 1MHz to output. */
1988     kCLOCK_1MHzOutEnableFreeRunning1Mhz = 2U, /*!< Enable 1MHZ output clock,
1989                                                    and select free-running 1MHz to output. */
1990 } clock_1MHzOut_behavior_t;
1991 
1992 /*!
1993  * @brief The clock dependence level.
1994  */
1995 typedef enum _clock_level
1996 {
1997     kCLOCK_Level0 = 0x0UL, /*!< Not needed in any mode. */
1998     kCLOCK_Level1 = 0x1UL, /*!< Needed in RUN mode. */
1999     kCLOCK_Level2 = 0x2UL, /*!< Needed in RUN and WAIT mode. */
2000     kCLOCK_Level3 = 0x3UL, /*!< Needed in RUN, WAIT and STOP mode. */
2001     kCLOCK_Level4 = 0x4UL, /*!< Always on in any mode. */
2002 } clock_level_t;
2003 
2004 /*******************************************************************************
2005  * API
2006  ******************************************************************************/
2007 
2008 #if defined(__cplusplus)
2009 extern "C" {
2010 #endif /* __cplusplus */
2011 
2012 /*!
2013  * @brief Set CCM Root Clock MUX node to certain value.
2014  *
2015  * @param root Which root clock node to set, see \ref clock_root_t.
2016  * @param src Clock mux value to set, different mux has different value range. See \ref clock_root_mux_source_t.
2017  */
CLOCK_SetRootClockMux(clock_root_t root,uint8_t src)2018 static inline void CLOCK_SetRootClockMux(clock_root_t root, uint8_t src)
2019 {
2020     assert(src < 8U);
2021     CCM->CLOCK_ROOT[root].CONTROL =
2022         (CCM->CLOCK_ROOT[root].CONTROL & ~(CCM_CLOCK_ROOT_CONTROL_MUX_MASK)) | CCM_CLOCK_ROOT_CONTROL_MUX(src);
2023     __DSB();
2024     __ISB();
2025 #if __CORTEX_M == 4
2026     (void)CCM->CLOCK_ROOT[root].CONTROL;
2027 #endif
2028 }
2029 
2030 /*!
2031  * @brief Get CCM Root Clock MUX value.
2032  *
2033  * @param root Which root clock node to get, see \ref clock_root_t.
2034  * @return Clock mux value.
2035  */
CLOCK_GetRootClockMux(clock_root_t root)2036 static inline uint32_t CLOCK_GetRootClockMux(clock_root_t root)
2037 {
2038     return (CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_MUX_MASK) >> CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT;
2039 }
2040 
2041 /*!
2042  * @brief Get CCM Root Clock Source.
2043  *
2044  * @param root Which root clock node to get, see \ref clock_root_t.
2045  * @param src Clock mux value to get, see \ref clock_root_mux_source_t.
2046  * @return Clock source
2047  */
CLOCK_GetRootClockSource(clock_root_t root,uint32_t src)2048 static inline clock_name_t CLOCK_GetRootClockSource(clock_root_t root, uint32_t src)
2049 {
2050     return s_clockSourceName[root][src];
2051 }
2052 
2053 /*!
2054  * @brief Set CCM Root Clock DIV certain value.
2055  *
2056  * @param root Which root clock to set, see \ref clock_root_t.
2057  * @param div Clock div value to set range is 1-256, different divider has different value range.
2058  */
CLOCK_SetRootClockDiv(clock_root_t root,uint32_t div)2059 static inline void CLOCK_SetRootClockDiv(clock_root_t root, uint32_t div)
2060 {
2061     assert(div);
2062     CCM->CLOCK_ROOT[root].CONTROL = (CCM->CLOCK_ROOT[root].CONTROL & ~CCM_CLOCK_ROOT_CONTROL_DIV_MASK) |
2063                                     CCM_CLOCK_ROOT_CONTROL_DIV((uint32_t)div - 1UL);
2064     __DSB();
2065     __ISB();
2066 #if __CORTEX_M == 4
2067     (void)CCM->CLOCK_ROOT[root].CONTROL;
2068 #endif
2069 }
2070 
2071 /*!
2072  * @brief Get CCM DIV node value.
2073  *
2074  * @param root Which root clock node to get, see \ref clock_root_t.
2075  * @return divider set for this root
2076  */
CLOCK_GetRootClockDiv(clock_root_t root)2077 static inline uint32_t CLOCK_GetRootClockDiv(clock_root_t root)
2078 {
2079     return ((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) >> CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT) +
2080            1UL;
2081 }
2082 
2083 /*!
2084  * @brief Power Off Root Clock
2085  *
2086  * @param root Which root clock node to set, see \ref clock_root_t.
2087  */
CLOCK_PowerOffRootClock(clock_root_t root)2088 static inline void CLOCK_PowerOffRootClock(clock_root_t root)
2089 {
2090     if (0UL == (CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_OFF_MASK))
2091     {
2092         CCM->CLOCK_ROOT[root].CONTROL_SET = CCM_CLOCK_ROOT_CONTROL_OFF_MASK;
2093         __DSB();
2094         __ISB();
2095 #if __CORTEX_M == 4
2096         (void)CCM->CLOCK_ROOT[root].CONTROL;
2097 #endif
2098     }
2099 }
2100 
2101 /*!
2102  * @brief Power On Root Clock
2103  *
2104  * @param root Which root clock node to set, see \ref clock_root_t.
2105  */
CLOCK_PowerOnRootClock(clock_root_t root)2106 static inline void CLOCK_PowerOnRootClock(clock_root_t root)
2107 {
2108     CCM->CLOCK_ROOT[root].CONTROL_CLR = CCM_CLOCK_ROOT_CONTROL_OFF_MASK;
2109     __DSB();
2110     __ISB();
2111 #if __CORTEX_M == 4
2112     (void)CCM->CLOCK_ROOT[root].CONTROL;
2113 #endif
2114 }
2115 
2116 /*!
2117  * @brief Configure Root Clock
2118  *
2119  * @param root Which root clock node to set, see \ref clock_root_t.
2120  * @param config root clock config, see \ref clock_root_config_t
2121  */
CLOCK_SetRootClock(clock_root_t root,const clock_root_config_t * config)2122 static inline void CLOCK_SetRootClock(clock_root_t root, const clock_root_config_t *config)
2123 {
2124     assert(config);
2125     CCM->CLOCK_ROOT[root].CONTROL = CCM_CLOCK_ROOT_CONTROL_MUX(config->mux) |
2126                                     CCM_CLOCK_ROOT_CONTROL_DIV((uint32_t)config->div - 1UL) |
2127                                     (config->clockOff ? CCM_CLOCK_ROOT_CONTROL_OFF(config->clockOff) : 0UL);
2128     __DSB();
2129     __ISB();
2130 #if __CORTEX_M == 4
2131     (void)CCM->CLOCK_ROOT[root].CONTROL;
2132 #endif
2133 }
2134 
2135 /*!
2136  * @brief Control the clock gate for specific IP.
2137  *
2138  * @note This API will not have any effect when this clock is in CPULPM or SetPoint Mode
2139  *
2140  * @param name  Which clock to enable, see \ref clock_lpcg_t.
2141  * @param value Clock gate value to set, see \ref clock_gate_value_t.
2142  */
CLOCK_ControlGate(clock_ip_name_t name,clock_gate_value_t value)2143 static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
2144 {
2145     if (((uint32_t)value & CCM_LPCG_DIRECT_ON_MASK) != (CCM->LPCG[name].DIRECT & CCM_LPCG_DIRECT_ON_MASK))
2146     {
2147         CCM->LPCG[name].DIRECT = ((uint32_t)value & CCM_LPCG_DIRECT_ON_MASK);
2148         __DSB();
2149         __ISB();
2150 
2151         while ((CCM->LPCG[name].STATUS0 & CCM_LPCG_STATUS0_ON_MASK) != ((uint32_t)value & CCM_LPCG_STATUS0_ON_MASK))
2152         {
2153         }
2154     }
2155 }
2156 
2157 /*!
2158  * @brief Enable the clock for specific IP.
2159  *
2160  * @param name  Which clock to enable, see \ref clock_lpcg_t.
2161  */
CLOCK_EnableClock(clock_ip_name_t name)2162 static inline void CLOCK_EnableClock(clock_ip_name_t name)
2163 {
2164     CLOCK_ControlGate(name, kCLOCK_On);
2165 }
2166 
2167 /*!
2168  * @brief Disable the clock for specific IP.
2169  *
2170  * @param name  Which clock to disable, see \ref clock_lpcg_t.
2171  */
CLOCK_DisableClock(clock_ip_name_t name)2172 static inline void CLOCK_DisableClock(clock_ip_name_t name)
2173 {
2174     CLOCK_ControlGate(name, kCLOCK_Off);
2175 }
2176 
2177 /*!
2178  * @brief Set the clock group configuration.
2179  *
2180  * @param group  Which group to configure, see \ref clock_group_t.
2181  * @param config Configuration to set.
2182  */
2183 void CLOCK_SetGroupConfig(clock_group_t group, const clock_group_config_t *config);
2184 
2185 /*!
2186  * @brief Gets the clock frequency for a specific clock name.
2187  *
2188  * This function checks the current clock configurations and then calculates
2189  * the clock frequency for a specific clock name defined in clock_name_t.
2190  *
2191  * @param name Clock names defined in clock_name_t
2192  * @return Clock frequency value in hertz
2193  */
2194 uint32_t CLOCK_GetFreq(clock_name_t name);
2195 
2196 /*!
2197  * @brief Gets the clock frequency for a specific root clock name.
2198  *
2199  * This function checks the current clock configurations and then calculates
2200  * the clock frequency for a specific clock name defined in clock_root_t.
2201  *
2202  * @param root Clock names defined in clock_root_t
2203  * @return Clock frequency value in hertz
2204  */
CLOCK_GetRootClockFreq(clock_root_t root)2205 static inline uint32_t CLOCK_GetRootClockFreq(clock_root_t root)
2206 {
2207     uint32_t freq, mux;
2208     mux  = CLOCK_GetRootClockMux(root);
2209     freq = CLOCK_GetFreq(s_clockSourceName[root][mux]) / (CLOCK_GetRootClockDiv(root));
2210     assert(freq);
2211     return freq;
2212 }
2213 
2214 /*!
2215  * @brief Get the CCM CPU/core/system frequency.
2216  *
2217  * @return  Clock frequency; If the clock is invalid, returns 0.
2218  */
CLOCK_GetM7Freq(void)2219 static inline uint32_t CLOCK_GetM7Freq(void)
2220 {
2221     return CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
2222 }
2223 
2224 /*!
2225  * @brief Get the CCM CPU/core/system frequency.
2226  *
2227  * @return  Clock frequency; If the clock is invalid, returns 0.
2228  */
CLOCK_GetM4Freq(void)2229 static inline uint32_t CLOCK_GetM4Freq(void)
2230 {
2231     return CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
2232 }
2233 
2234 /*!
2235  * @brief Check if PLL is bypassed
2236  *
2237  * @param pll PLL control name (see @ref clock_pll_t enumeration)
2238  * @return PLL bypass status.
2239  *         - true: The PLL is bypassed.
2240  *         - false: The PLL is not bypassed.
2241  */
CLOCK_IsPllBypassed(clock_pll_t pll)2242 static inline bool CLOCK_IsPllBypassed(clock_pll_t pll)
2243 {
2244     if (pll == kCLOCK_PllArm)
2245     {
2246         return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) >>
2247                       ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT);
2248     }
2249     else if (pll == kCLOCK_PllSys2)
2250     {
2251         return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >>
2252                       ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT);
2253     }
2254     else if (pll == kCLOCK_PllSys3)
2255     {
2256         return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) >>
2257                       ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT);
2258     }
2259     else
2260     {
2261         return false;
2262     }
2263 }
2264 
2265 /*!
2266  * @brief Check if PLL is enabled
2267  *
2268  * @param pll PLL control name (see @ref clock_pll_t enumeration)
2269  * @return PLL bypass status.
2270  *         - true: The PLL is enabled.
2271  *         - false: The PLL is not enabled.
2272  */
CLOCK_IsPllEnabled(clock_pll_t pll)2273 static inline bool CLOCK_IsPllEnabled(clock_pll_t pll)
2274 {
2275     if (pll == kCLOCK_PllArm)
2276     {
2277         return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) >>
2278                       ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT);
2279     }
2280     else if (pll == kCLOCK_PllSys2)
2281     {
2282         return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >>
2283                       ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT);
2284     }
2285     else if (pll == kCLOCK_PllSys3)
2286     {
2287         return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) >>
2288                       ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT);
2289     }
2290     else if (pll == kCLOCK_PllSys1)
2291     {
2292         return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >>
2293                       ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT);
2294     }
2295     else if (pll == kCLOCK_PllAudio)
2296     {
2297         return (bool)((ANADIG_PLL->PLL_AUDIO_CTRL & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) >>
2298                       ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT);
2299     }
2300     else if (pll == kCLOCK_PllVideo)
2301     {
2302         return (bool)((ANADIG_PLL->PLL_VIDEO_CTRL & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK) >>
2303                       ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT);
2304     }
2305     else
2306     {
2307         return false;
2308     }
2309 }
2310 
2311 /*!
2312  * @name OSC operations
2313  * @{
2314  */
2315 
2316 /*!
2317  * @brief Gets the RTC clock frequency.
2318  *
2319  * @return  Clock frequency; If the clock is invalid, returns 0.
2320  */
CLOCK_GetRtcFreq(void)2321 static inline uint32_t CLOCK_GetRtcFreq(void)
2322 {
2323     return 32768U;
2324 }
2325 
2326 /*!
2327  * @brief Set the control mode of 48MHz RC oscillator.
2328  *
2329  * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t.
2330  */
CLOCK_OSC_SetOsc48MControlMode(clock_control_mode_t controlMode)2331 static inline void CLOCK_OSC_SetOsc48MControlMode(clock_control_mode_t controlMode)
2332 {
2333     ANADIG_OSC->OSC_48M_CTRL = (ANADIG_OSC->OSC_48M_CTRL & ~(ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK)) |
2334                                ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE(controlMode);
2335 }
2336 
2337 /*!
2338  * @brief Enable/disable 48MHz RC oscillator.
2339  *
2340  * @param enable Used to enable or disable the 48MHz RC oscillator.
2341  *          - \b true Enable the 48MHz RC oscillator.
2342  *          - \b false Dissable the 48MHz RC oscillator.
2343  */
CLOCK_OSC_EnableOsc48M(bool enable)2344 static inline void CLOCK_OSC_EnableOsc48M(bool enable)
2345 {
2346     if (enable)
2347     {
2348         ANADIG_OSC->OSC_48M_CTRL |= ANADIG_OSC_OSC_48M_CTRL_TEN_MASK;
2349     }
2350     else
2351     {
2352         ANADIG_OSC->OSC_48M_CTRL &= ~ANADIG_OSC_OSC_48M_CTRL_TEN_MASK;
2353     }
2354 }
2355 
2356 /*!
2357  * @brief Set the control mode of the 24MHz clock sourced from 48MHz RC oscillator.
2358  *
2359  * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t.
2360  */
CLOCK_OSC_SetOsc48MDiv2ControlMode(clock_control_mode_t controlMode)2361 static inline void CLOCK_OSC_SetOsc48MDiv2ControlMode(clock_control_mode_t controlMode)
2362 {
2363     ANADIG_OSC->OSC_48M_CTRL = (ANADIG_OSC->OSC_48M_CTRL & ~(ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK)) |
2364                                ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE(controlMode);
2365 }
2366 
2367 /*!
2368  * @brief Enable/disable the 24MHz clock sourced from 48MHz RC oscillator.
2369  *
2370  * @note The 48MHz RC oscillator must be enabled before enabling this 24MHz clock.
2371  *
2372  * @param enable Used to enable/disable the 24MHz clock sourced from 48MHz RC oscillator.
2373  *          - \b true Enable the 24MHz clock sourced from 48MHz.
2374  *          - \b false Disable the 24MHz clock sourced from 48MHz.
2375  */
CLOCK_OSC_EnableOsc48MDiv2(bool enable)2376 static inline void CLOCK_OSC_EnableOsc48MDiv2(bool enable)
2377 {
2378     if (enable)
2379     {
2380         ANADIG_OSC->OSC_48M_CTRL |= ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK;
2381     }
2382     else
2383     {
2384         ANADIG_OSC->OSC_48M_CTRL &= ~ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK;
2385     }
2386 }
2387 
2388 /*!
2389  * @brief Set the control mode of 24MHz crystal oscillator.
2390  *
2391  * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t.
2392  */
CLOCK_OSC_SetOsc24MControlMode(clock_control_mode_t controlMode)2393 static inline void CLOCK_OSC_SetOsc24MControlMode(clock_control_mode_t controlMode)
2394 {
2395     ANADIG_OSC->OSC_24M_CTRL = (ANADIG_OSC->OSC_24M_CTRL & ~(ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK)) |
2396                                ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(controlMode);
2397 }
2398 
2399 /*! @brief Enable OSC 24Mhz
2400  *
2401  * This function enables OSC 24Mhz.
2402  */
2403 void CLOCK_OSC_EnableOsc24M(void);
2404 
2405 /*!
2406  * @brief Gate/ungate the 24MHz crystal oscillator output.
2407  *
2408  * @note Gating the 24MHz crystal oscillator can save power.
2409  *
2410  * @param enableGate Used to gate/ungate the 24MHz crystal oscillator.
2411  *          - \b true Gate the 24MHz crystal oscillator to save power.
2412  *          - \b false Ungate the 24MHz crystal oscillator.
2413  */
CLOCK_OSC_GateOsc24M(bool enableGate)2414 static inline void CLOCK_OSC_GateOsc24M(bool enableGate)
2415 {
2416     if (enableGate)
2417     {
2418         ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK;
2419     }
2420     else
2421     {
2422         ANADIG_OSC->OSC_24M_CTRL &= ~ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK;
2423     }
2424 }
2425 
2426 /*!
2427  * @brief Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and
2428  * bypass mode.
2429  *
2430  * @param workMode The work mode of 24MHz crystal oscillator, please refer to @ref clock_24MOsc_mode_t for details.
2431  */
2432 void CLOCK_OSC_SetOsc24MWorkMode(clock_24MOsc_mode_t workMode);
2433 
2434 /*!
2435  * @brief Set the control mode of 400MHz RC oscillator.
2436  *
2437  * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t.
2438  */
CLOCK_OSC_SetOscRc400MControlMode(clock_control_mode_t controlMode)2439 static inline void CLOCK_OSC_SetOscRc400MControlMode(clock_control_mode_t controlMode)
2440 {
2441     ANADIG_OSC->OSC_400M_CTRL1 = (ANADIG_OSC->OSC_400M_CTRL1 & (~ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK)) |
2442                                  ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(controlMode);
2443 }
2444 
2445 /*! @brief Enable OSC RC 400Mhz
2446  *
2447  * This function enables OSC RC 400Mhz.
2448  */
2449 void CLOCK_OSC_EnableOscRc400M(void);
2450 
2451 /*!
2452  * @brief Gate/ungate 400MHz RC oscillator.
2453  *
2454  * @param enableGate Used to gate/ungate 400MHz RC oscillator.
2455  *          - \b true Gate the 400MHz RC oscillator.
2456  *          - \b false Ungate the 400MHz RC oscillator.
2457  */
CLOCK_OSC_GateOscRc400M(bool enableGate)2458 static inline void CLOCK_OSC_GateOscRc400M(bool enableGate)
2459 {
2460     if (enableGate)
2461     {
2462         ANADIG_OSC->OSC_400M_CTRL1 |= ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK;
2463     }
2464     else
2465     {
2466         ANADIG_OSC->OSC_400M_CTRL1 &= ~ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK;
2467     }
2468 }
2469 
2470 /*!
2471  * @brief Trims OSC RC 400MHz.
2472  *
2473  * @param enable Used to enable trim function.
2474  * @param bypass Bypass the trim function.
2475  * @param trim Trim value.
2476  */
2477 void CLOCK_OSC_TrimOscRc400M(bool enable, bool bypass, uint16_t trim);
2478 
2479 /*!
2480  * @brief Set the divide value for ref_clk to generate slow clock.
2481  *
2482  * @note slow_clk = ref_clk / (divValue + 1), and the recommand divide value is 24.
2483  *
2484  * @param divValue The divide value to be set, the available range is 0~63.
2485  */
2486 void CLOCK_OSC_SetOscRc400MRefClkDiv(uint8_t divValue);
2487 
2488 /*!
2489  * @brief Set the target count for the fast clock.
2490  *
2491  * @param targetCount The desired target for the fast clock, should be the number of clock cycles of the fast_clk per
2492  * divided ref_clk.
2493  */
2494 void CLOCK_OSC_SetOscRc400MFastClkCount(uint16_t targetCount);
2495 
2496 /*!
2497  * @brief Set the negative and positive hysteresis value for the tuned clock.
2498  *
2499  * @note The hysteresis value should be set after the clock is tuned.
2500  *
2501  * @param negHysteresis The negative hysteresis value for the turned clock, this value in number of clock cycles of the
2502  * fast clock
2503  * @param posHysteresis The positive hysteresis value for the turned clock, this value in number of clock cycles of the
2504  * fast clock
2505  */
2506 void CLOCK_OSC_SetOscRc400MHysteresisValue(uint8_t negHysteresis, uint8_t posHysteresis);
2507 
2508 /*!
2509  * @brief Bypass/un-bypass the tune logic
2510  *
2511  * @param enableBypass Used to control whether to bypass the turn logic.
2512  *        - \b true Bypass the tune logic and use the programmed oscillator frequency to run the oscillator.
2513  *                  Function CLOCK_OSC_SetOscRc400MTuneValue() can be used to set oscillator frequency.
2514  *        - \b false Use the output of tune logic to run the oscillator.
2515  */
2516 void CLOCK_OSC_BypassOscRc400MTuneLogic(bool enableBypass);
2517 
2518 /*!
2519  * @brief Start/Stop the tune logic.
2520  *
2521  * @param enable Used to start or stop the tune logic.
2522  *          - \b true Start tuning
2523  *          - \b false Stop tuning and reset the tuning logic.
2524  */
2525 void CLOCK_OSC_EnableOscRc400MTuneLogic(bool enable);
2526 
2527 /*!
2528  * @brief Freeze/Unfreeze the tuning value.
2529  *
2530  * @param enableFreeze Used to control whether to freeze the tune value.
2531  *          - \b true Freeze the tune at the current tuned value and the oscillator runs at tje frozen tune value.
2532  *          - \b false Unfreezes and continues the tune operation.
2533  */
2534 void CLOCK_OSC_FreezeOscRc400MTuneValue(bool enableFreeze);
2535 
2536 /*!
2537  * @brief Set the 400MHz RC oscillator tune value when the tune logic is disabled.
2538  *
2539  * @param tuneValue The tune value to determine the frequency of Oscillator.
2540  */
2541 void CLOCK_OSC_SetOscRc400MTuneValue(uint8_t tuneValue);
2542 
2543 /*!
2544  * @brief Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output,
2545  * enable the free-running 1MHz clock output, enable the locked 1MHz clock output.
2546  *
2547  * @note The 1MHz clock is divided from 400M RC Oscillator.
2548  *
2549  * @param behavior The behavior of 1MHz output clock, please refer to @ref clock_1MHzOut_behavior_t for details.
2550  */
2551 void CLOCK_OSC_Set1MHzOutputBehavior(clock_1MHzOut_behavior_t behavior);
2552 
2553 /*!
2554  * @brief Set the count for the locked 1MHz clock out.
2555  *
2556  * @param count Used to set the desired target for the locked 1MHz clock out, the value in number of clock cycles of the
2557  * fast clock per divided ref_clk.
2558  */
2559 void CLOCK_OSC_SetLocked1MHzCount(uint16_t count);
2560 
2561 /*!
2562  * @brief Check the error flag for locked 1MHz clock out.
2563  *
2564  * @return The error flag for locked 1MHz clock out.
2565  *      - \b true The count value has been reached within one diviced ref clock period
2566  *      - \b false No effect.
2567  */
2568 bool CLOCK_OSC_CheckLocked1MHzErrorFlag(void);
2569 
2570 /*!
2571  * @brief Clear the error flag for locked 1MHz clock out.
2572  */
2573 void CLOCK_OSC_ClearLocked1MHzErrorFlag(void);
2574 
2575 /*!
2576  * @brief Get current count for the fast clock during the tune process.
2577  *
2578  * @return The current count for the fast clock.
2579  */
2580 uint16_t CLOCK_OSC_GetCurrentOscRc400MFastClockCount(void);
2581 
2582 /*!
2583  * @brief Get current tune value used by oscillator during tune process.
2584  *
2585  * @return The current tune value.
2586  */
2587 uint8_t CLOCK_OSC_GetCurrentOscRc400MTuneValue(void);
2588 
2589 /*!
2590  * @brief Set the control mode of 16MHz crystal oscillator.
2591  *
2592  * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t.
2593  */
CLOCK_OSC_SetOsc16MControlMode(clock_control_mode_t controlMode)2594 static inline void CLOCK_OSC_SetOsc16MControlMode(clock_control_mode_t controlMode)
2595 {
2596     ANADIG_OSC->OSC_16M_CTRL = (ANADIG_OSC->OSC_16M_CTRL & (~ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK)) |
2597                                ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE(controlMode);
2598 }
2599 
2600 /*!
2601  * @brief Configure the 16MHz oscillator.
2602  *
2603  * @param source Used to select the source for 16MHz RC oscillator, please refer to @ref clock_16MOsc_source_t.
2604  * @param enablePowerSave Enable/disable power save mode function at 16MHz OSC.
2605  *          - \b true Enable power save mode function at 16MHz osc.
2606  *          - \b false Disable power save mode function at 16MHz osc.
2607  * @param enableClockOut Enable/Disable clock output for 16MHz RCOSC.
2608  *          - \b true Enable clock output for 16MHz RCOSC.
2609  *          - \b false Disable clock output for 16MHz RCOSC.
2610  */
2611 void CLOCK_OSC_SetOsc16MConfig(clock_16MOsc_source_t source, bool enablePowerSave, bool enableClockOut);
2612 
2613 /* @} */
2614 
2615 /*!
2616  * @brief Initialize the ARM PLL.
2617  *
2618  * This function initialize the ARM PLL with specific settings
2619  *
2620  * @param config   configuration to set to PLL.
2621  */
2622 void CLOCK_InitArmPll(const clock_arm_pll_config_t *config);
2623 
2624 /*!
2625  * @brief Calculate corresponding config values per given frequency
2626  *
2627  * This function calculates config valudes per given frequency for Arm PLL
2628  *
2629  * @param config pll config structure
2630  * @param freqInMhz target frequency
2631  */
2632 status_t CLOCK_CalcArmPllFreq(clock_arm_pll_config_t *config, uint32_t freqInMhz);
2633 
2634 /*!
2635  * @brief Initializes the Arm PLL with Specific Frequency (in Mhz).
2636  *
2637  * This function initializes the Arm PLL with specific frequency
2638  *
2639  * @param freqInMhz target frequency
2640  */
2641 status_t CLOCK_InitArmPllWithFreq(uint32_t freqInMhz);
2642 
2643 /*!
2644  * @brief De-initialize the ARM PLL.
2645  */
2646 void CLOCK_DeinitArmPll(void);
2647 
2648 /*!
2649  * @brief Calculate spread spectrum step and stop.
2650  *
2651  * This function calculate spread spectrum step and stop according to given
2652  * parameters. For integer PLL (syspll2) the factor is mfd, while for other
2653  * fractional PLLs (audio/video/syspll1), the factor is denominator.
2654  *
2655  * @param factor factor to calculate step/stop
2656  * @param range spread spectrum range
2657  * @param mod spread spectrum modulation frequency
2658  * @param ss calculated spread spectrum values
2659  *
2660  */
2661 void CLOCK_CalcPllSpreadSpectrum(uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss);
2662 
2663 /*!
2664  * @brief Initialize the System PLL1.
2665  *
2666  * This function initializes the System PLL1 with specific settings
2667  *
2668  * @param config Configuration to set to PLL1.
2669  */
2670 void CLOCK_InitSysPll1(const clock_sys_pll1_config_t *config);
2671 
2672 /*!
2673  * @brief De-initialize the System PLL1.
2674  */
2675 void CLOCK_DeinitSysPll1(void);
2676 
2677 /*!
2678  * @brief Set System PLL1 output frequency in GPC mode.
2679  *
2680  * @param config Pointer to System PLL1 configure structure.
2681  */
2682 void CLOCK_GPC_SetSysPll1OutputFreq(const clock_sys_pll1_gpc_config_t *config);
2683 
2684 /*!
2685  * @brief Initialize the System PLL2.
2686  *
2687  * This function initializes the System PLL2 with specific settings
2688  *
2689  * @param config Configuration to configure spread spectrum. This parameter can
2690  *            be NULL, if no need to enabled spread spectrum
2691  */
2692 void CLOCK_InitSysPll2(const clock_sys_pll2_config_t *config);
2693 
2694 /*!
2695  * @brief De-initialize the System PLL2.
2696  */
2697 void CLOCK_DeinitSysPll2(void);
2698 
2699 /*!
2700  * @brief Check if Sys PLL2 PFD is enabled
2701  *
2702  * @param pfd PFD control name
2703  * @return PFD bypass status.
2704  *         - true: power on.
2705  *         - false: power off.
2706  * @note Only useful in software control mode.
2707  */
2708 bool CLOCK_IsSysPll2PfdEnabled(clock_pfd_t pfd);
2709 
2710 /*!
2711  * @brief Initialize the System PLL3.
2712  *
2713  * This function initializes the System PLL3 with specific settings
2714  *
2715  */
2716 void CLOCK_InitSysPll3(void);
2717 
2718 /*!
2719  * @brief De-initialize the System PLL3.
2720  */
2721 void CLOCK_DeinitSysPll3(void);
2722 
2723 /*!
2724  * @brief Check if Sys PLL3 PFD is enabled
2725  *
2726  * @param pfd PFD control name
2727  * @return PFD bypass status.
2728  *         - true: power on.
2729  *         - false: power off.
2730  * @note Only useful in software control mode.
2731  */
2732 bool CLOCK_IsSysPll3PfdEnabled(clock_pfd_t pfd);
2733 
2734 /*!
2735  * @name PLL/PFD operations
2736  * @{
2737  */
2738 /*!
2739  * @brief PLL bypass setting
2740  *
2741  * @param pll PLL control name (see @ref clock_pll_t enumeration)
2742  * @param bypass Bypass the PLL.
2743  *               - true: Bypass the PLL.
2744  *               - false:Not bypass the PLL.
2745  */
2746 void CLOCK_SetPllBypass(clock_pll_t pll, bool bypass);
2747 
2748 /*!
2749  * @brief Calculate corresponding config values per given frequency
2750  *
2751  * This function calculates config valudes per given frequency for Audio/Video
2752  * PLL.
2753  *
2754  * @param config pll config structure
2755  * @param freqInMhz target frequency
2756  */
2757 status_t CLOCK_CalcAvPllFreq(clock_av_pll_config_t *config, uint32_t freqInMhz);
2758 
2759 /*!
2760  * @brief Initializes the Audio PLL with Specific Frequency (in Mhz).
2761  *
2762  * This function initializes the Audio PLL with specific frequency
2763  *
2764  * @param freqInMhz target frequency
2765  * @param ssEnable  enable spread spectrum or not
2766  * @param ssRange   range spread spectrum range
2767  * @param ssMod spread spectrum modulation frequency
2768  */
2769 status_t CLOCK_InitAudioPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod);
2770 
2771 /*!
2772  * @brief Initializes the Audio PLL.
2773  *
2774  * This function initializes the Audio PLL with specific settings
2775  *
2776  * @param config Configuration to set to PLL.
2777  */
2778 void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
2779 
2780 /*!
2781  * @brief De-initialize the Audio PLL.
2782  */
2783 void CLOCK_DeinitAudioPll(void);
2784 
2785 /*!
2786  * @brief Set Audio PLL output frequency in GPC mode.
2787  *
2788  * @param config Pointer to clock_audio_pll_gpc_config_t structure.
2789  */
2790 void CLOCK_GPC_SetAudioPllOutputFreq(const clock_audio_pll_gpc_config_t *config);
2791 
2792 /*!
2793  * @brief Initializes the Video PLL with Specific Frequency (in Mhz).
2794  *
2795  * This function initializes the Video PLL with specific frequency
2796  *
2797  * @param freqInMhz target frequency
2798  * @param ssEnable  enable spread spectrum or not
2799  * @param ssRange   range spread spectrum range
2800  * @param ssMod spread spectrum modulation frequency
2801  */
2802 status_t CLOCK_InitVideoPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod);
2803 
2804 /*!
2805  * @brief Initialize the video PLL.
2806  *
2807  * This function configures the Video PLL with specific settings
2808  *
2809  * @param config   configuration to set to PLL.
2810  */
2811 void CLOCK_InitVideoPll(const clock_video_pll_config_t *config);
2812 
2813 /*!
2814  * @brief De-initialize the Video PLL.
2815  */
2816 void CLOCK_DeinitVideoPll(void);
2817 
2818 /*!
2819  * @brief Set Video PLL output frequency in GPC mode.
2820  *
2821  * @param config Pointer to Vidoe PLL configure structure.
2822  */
2823 void CLOCK_GPC_SetVideoPllOutputFreq(const clock_video_pll_gpc_config_t *config);
2824 /*!
2825  * @brief Get current PLL output frequency.
2826  *
2827  * This function get current output frequency of specific PLL
2828  *
2829  * @param pll   pll name to get frequency.
2830  * @return The PLL output frequency in hertz.
2831  */
2832 uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
2833 
2834 /*!
2835  * @brief Initialize PLL PFD.
2836  *
2837  * This function initializes the System PLL PFD. During new value setting,
2838  * the clock output is disabled to prevent glitch.
2839  *
2840  * @param pll Which PLL of targeting PFD to be operated.
2841  * @param pfd Which PFD clock to enable.
2842  * @param frac The PFD FRAC value.
2843  * @note It is recommended that PFD settings are kept between 12-35.
2844  */
2845 void CLOCK_InitPfd(clock_pll_t pll, clock_pfd_t pfd, uint8_t frac);
2846 
2847 /*!
2848  * @brief De-initialize selected PLL PFD.
2849  *
2850  * @param pll Which PLL of targeting PFD to be operated.
2851  * @param pfd Which PFD clock to enable.
2852  */
2853 void CLOCK_DeinitPfd(clock_pll_t pll, clock_pfd_t pfd);
2854 
2855 /*!
2856  * @brief Get current PFD output frequency.
2857  *
2858  * This function get current output frequency of specific System PLL PFD
2859  *
2860  * @param pll Which PLL of targeting PFD to be operated.
2861  * @param pfd pfd name to get frequency.
2862  * @return The PFD output frequency in hertz.
2863  */
2864 uint32_t CLOCK_GetPfdFreq(clock_pll_t pll, clock_pfd_t pfd);
2865 
2866 uint32_t CLOCK_GetFreqFromObs(uint32_t obsSigIndex, uint32_t obsIndex);
2867 
2868 /*! @brief Enable USB HS clock.
2869  *
2870  * This function only enables the access to USB HS prepheral, upper layer
2871  * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
2872  * clock to use USB HS.
2873  *
2874  * @param src  USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
2875  * @param freq USB HS does not care about the clock source, so this parameter is ignored.
2876  * @retval true The clock is set successfully.
2877  * @retval false The clock source is invalid to get proper USB HS clock.
2878  */
2879 bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
2880 
2881 /*! @brief Enable USB HS clock.
2882  *
2883  * This function only enables the access to USB HS prepheral, upper layer
2884  * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
2885  * clock to use USB HS.
2886  *
2887  * @param src  USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
2888  * @param freq USB HS does not care about the clock source, so this parameter is ignored.
2889  * @retval true The clock is set successfully.
2890  * @retval false The clock source is invalid to get proper USB HS clock.
2891  */
2892 bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq);
2893 
2894 /*! @brief Enable USB HS PHY PLL clock.
2895  *
2896  * This function enables the internal 480MHz USB PHY PLL clock.
2897  *
2898  * @param src  USB HS PHY PLL clock source.
2899  * @param freq The frequency specified by src.
2900  * @retval true The clock is set successfully.
2901  * @retval false The clock source is invalid to get proper USB HS clock.
2902  */
2903 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
2904 
2905 /*! @brief Disable USB HS PHY PLL clock.
2906  *
2907  * This function disables USB HS PHY PLL clock.
2908  */
2909 void CLOCK_DisableUsbhs0PhyPllClock(void);
2910 
2911 /*! @brief Enable USB HS PHY PLL clock.
2912  *
2913  * This function enables the internal 480MHz USB PHY PLL clock.
2914  *
2915  * @param src  USB HS PHY PLL clock source.
2916  * @param freq The frequency specified by src.
2917  * @retval true The clock is set successfully.
2918  * @retval false The clock source is invalid to get proper USB HS clock.
2919  */
2920 bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
2921 
2922 /*! @brief Disable USB HS PHY PLL clock.
2923  *
2924  * This function disables USB HS PHY PLL clock.
2925  */
2926 void CLOCK_DisableUsbhs1PhyPllClock(void);
2927 
2928 /*!
2929  * @brief Lock low power and access control mode for this clock.
2930  *
2931  * @note When this bit is set, bits 16-20 can not be changed until next system reset.
2932  *
2933  * @param name Clock source name, see \ref clock_name_t.
2934  */
CLOCK_OSCPLL_LockControlMode(clock_name_t name)2935 static inline void CLOCK_OSCPLL_LockControlMode(clock_name_t name)
2936 {
2937     CCM->OSCPLL[name].AUTHEN |= CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK;
2938 }
2939 
2940 /*!
2941  * @brief Lock the value of Domain ID white list for this clock.
2942  *
2943  * @note Once locked, this bit and domain ID white list can not be changed until next system reset.
2944  *
2945  * @param name Clock source name, see \ref clock_name_t.
2946  */
CLOCK_OSCPLL_LockWhiteList(clock_name_t name)2947 static inline void CLOCK_OSCPLL_LockWhiteList(clock_name_t name)
2948 {
2949     CCM->OSCPLL[name].AUTHEN |= CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK;
2950 }
2951 
2952 /*!
2953  * @brief Set domain ID that can change this clock.
2954  *
2955  * @note If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.
2956  *
2957  * @param name Clock source name, see \ref clock_name_t.
2958  * @param domainId Domains that on the whitelist can change this clock.
2959  */
CLOCK_OSCPLL_SetWhiteList(clock_name_t name,uint8_t domainId)2960 static inline void CLOCK_OSCPLL_SetWhiteList(clock_name_t name, uint8_t domainId)
2961 {
2962     CCM->OSCPLL[name].AUTHEN =
2963         (CCM->OSCPLL[name].AUTHEN & ~CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK) | CCM_OSCPLL_AUTHEN_WHITE_LIST(domainId);
2964 }
2965 
2966 /*!
2967  * @brief Check whether this clock implement SetPoint control scheme.
2968  *
2969  * @param name Clock source name, see \ref clock_name_t.
2970  * @return  Clock source SetPoint implement status.
2971  *         - true: SetPoint is implemented.
2972  *         - false: SetPoint is not implemented.
2973  */
CLOCK_OSCPLL_IsSetPointImplemented(clock_name_t name)2974 static inline bool CLOCK_OSCPLL_IsSetPointImplemented(clock_name_t name)
2975 {
2976     return (((CCM->OSCPLL[name].CONFIG & CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK) >>
2977              CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT) != 0UL);
2978 }
2979 
2980 /*!
2981  * @brief Set this clock works in Unassigned Mode.
2982  *
2983  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
2984  *
2985  * @param name Clock source name, see \ref clock_name_t.
2986  */
CLOCK_OSCPLL_ControlByUnassignedMode(clock_name_t name)2987 static inline void CLOCK_OSCPLL_ControlByUnassignedMode(clock_name_t name)
2988 {
2989     CCM->OSCPLL[name].AUTHEN &=
2990         ~(CCM_OSCPLL_AUTHEN_CPULPM_MASK | CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK | CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK);
2991 }
2992 
2993 /*!
2994  * @brief Set this clock works in SetPoint control Mode.
2995  *
2996  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
2997  *
2998  * @param name Clock source name, see \ref clock_name_t.
2999  * @param spValue Bit0~Bit15 hold value for Setpoint 0~16 respectively.
3000  *                A bitfield value of 0 implies clock will be shutdown in this Setpoint.
3001  *                A bitfield value of 1 implies clock will be turn on in this Setpoint.
3002  * @param stbyValue Bit0~Bit15 hold value for Setpoint 0~16 standby.
3003  *                A bitfield value of 0 implies clock will be shutdown during standby.
3004  *                A bitfield value of 1 represent clock will keep Setpoint setting during standby.
3005  */
3006 void CLOCK_OSCPLL_ControlBySetPointMode(clock_name_t name, uint16_t spValue, uint16_t stbyValue);
3007 
3008 /*!
3009  * @brief Set this clock works in CPU Low Power Mode.
3010  *
3011  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3012  *
3013  * @param name Clock source name, see \ref clock_name_t.
3014  * @param domainId Domains that on the whitelist can change this clock.
3015  * @param level0,level1 Depend level of this clock.
3016  */
3017 void CLOCK_OSCPLL_ControlByCpuLowPowerMode(clock_name_t name,
3018                                            uint8_t domainId,
3019                                            clock_level_t level0,
3020                                            clock_level_t level1);
3021 
3022 /*!
3023  * @brief Set clock depend level for current accessing domain.
3024  *
3025  * @note This setting only take effects in CPU Low Power Mode.
3026  *
3027  * @param name Clock source name, see \ref clock_name_t.
3028  * @param level Depend level of this clock.
3029  */
CLOCK_OSCPLL_SetCurrentClockLevel(clock_name_t name,clock_level_t level)3030 static inline void CLOCK_OSCPLL_SetCurrentClockLevel(clock_name_t name, clock_level_t level)
3031 {
3032     CCM->OSCPLL[name].DOMAINr =
3033         (CCM->OSCPLL[name].DOMAINr & ~CCM_OSCPLL_DOMAIN_LEVEL_MASK) | CCM_OSCPLL_DOMAIN_LEVEL(level);
3034 }
3035 
3036 /*!
3037  * @brief Set this clock works in Domain Mode.
3038  *
3039  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3040  *
3041  * @param name Clock source name, see \ref clock_name_t.
3042  * @param domainId Domains that on the whitelist can change this clock.
3043  */
CLOCK_OSCPLL_ControlByDomainMode(clock_name_t name,uint8_t domainId)3044 static inline void CLOCK_OSCPLL_ControlByDomainMode(clock_name_t name, uint8_t domainId)
3045 {
3046     CCM->OSCPLL[name].AUTHEN =
3047         (CCM->OSCPLL[name].AUTHEN &
3048          ~(CCM_OSCPLL_AUTHEN_CPULPM_MASK | CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK | CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK)) |
3049         CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK | CCM_OSCPLL_AUTHEN_WHITE_LIST(domainId);
3050 }
3051 
3052 /*!
3053  * @brief Lock low power and access control mode for this clock.
3054  *
3055  * @note When this bit is set, bits 16-20 can not be changed until next system reset.
3056  *
3057  * @param name Clock root name, see \ref clock_root_t.
3058  */
CLOCK_ROOT_LockControlMode(clock_root_t name)3059 static inline void CLOCK_ROOT_LockControlMode(clock_root_t name)
3060 {
3061     CCM->CLOCK_ROOT[name].AUTHEN |= CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK;
3062 }
3063 
3064 /*!
3065  * @brief Lock the value of Domain ID white list for this clock.
3066  *
3067  * @note Once locked, this bit and domain ID white list can not be changed until next system reset.
3068  *
3069  * @param name Clock root name, see \ref clock_root_t.
3070  */
CLOCK_ROOT_LockWhiteList(clock_root_t name)3071 static inline void CLOCK_ROOT_LockWhiteList(clock_root_t name)
3072 {
3073     CCM->CLOCK_ROOT[name].AUTHEN |= CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK;
3074 }
3075 
3076 /*!
3077  * @brief Set domain ID that can change this clock.
3078  *
3079  * @note If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.
3080  *
3081  * @param name Clock root name, see \ref clock_root_t.
3082  * @param domainId Domains that on the whitelist can change this clock.
3083  */
CLOCK_ROOT_SetWhiteList(clock_root_t name,uint8_t domainId)3084 static inline void CLOCK_ROOT_SetWhiteList(clock_root_t name, uint8_t domainId)
3085 {
3086     CCM->CLOCK_ROOT[name].AUTHEN = (CCM->CLOCK_ROOT[name].AUTHEN & ~CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK) |
3087                                    CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(domainId);
3088 }
3089 
3090 /*!
3091  * @brief Check whether this clock implement SetPoint control scheme.
3092  *
3093  * @param name Clock root name, see \ref clock_root_t.
3094  * @return  Clock root SetPoint implement status.
3095  *         - true: SetPoint is implemented.
3096  *         - false: SetPoint is not implemented.
3097  */
CLOCK_ROOT_IsSetPointImplemented(clock_root_t name)3098 static inline bool CLOCK_ROOT_IsSetPointImplemented(clock_root_t name)
3099 {
3100     return (((CCM->CLOCK_ROOT[name].CONFIG & CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK) >>
3101              CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT) != 0UL);
3102 }
3103 
3104 /*!
3105  * @brief Set this clock works in Unassigned Mode.
3106  *
3107  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3108  *
3109  * @param name Clock root name, see \ref clock_root_t.
3110  */
CLOCK_ROOT_ControlByUnassignedMode(clock_root_t name)3111 static inline void CLOCK_ROOT_ControlByUnassignedMode(clock_root_t name)
3112 {
3113     CCM->CLOCK_ROOT[name].AUTHEN &=
3114         ~(CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK | CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK);
3115 }
3116 
3117 /*!
3118  * @brief Configure one SetPoint for this clock.
3119  *
3120  * @note SetPoint value could only be changed in Unassigend Mode.
3121  *
3122  * @param name Which clock root to set, see \ref clock_root_t.
3123  * @param spIndex Which SetPoint of this clock root to set.
3124  * @param config SetPoint config, see \ref clock_root_setpoint_config_t
3125  */
CLOCK_ROOT_ConfigSetPoint(clock_root_t name,uint16_t spIndex,const clock_root_setpoint_config_t * config)3126 static inline void CLOCK_ROOT_ConfigSetPoint(clock_root_t name,
3127                                              uint16_t spIndex,
3128                                              const clock_root_setpoint_config_t *config)
3129 {
3130     assert(config != NULL);
3131     CCM->CLOCK_ROOT[name].SETPOINT[spIndex] =
3132         CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE(config->grade) |
3133         CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX(config->mux) |
3134         CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV((uint32_t)config->div - 1UL) |
3135         CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF(config->clockOff);
3136 }
3137 
3138 /*!
3139  * @brief Enable SetPoint control for this clock root.
3140  *
3141  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3142  *
3143  * @param name Clock root name, see \ref clock_root_t.
3144  */
CLOCK_ROOT_EnableSetPointControl(clock_root_t name)3145 static inline void CLOCK_ROOT_EnableSetPointControl(clock_root_t name)
3146 {
3147     CCM->CLOCK_ROOT[name].AUTHEN = (CCM->CLOCK_ROOT[name].AUTHEN & ~CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK) |
3148                                    CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK;
3149 }
3150 
3151 /*!
3152  * @brief Set this clock works in SetPoint controlled Mode.
3153  *
3154  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3155  *
3156  * @param name Clock root name, see \ref clock_root_t.
3157  * @param spTable Point to the array that stores clock root settings for each setpoint. Note that the pointed array must
3158  * have 16 elements.
3159  */
3160 void CLOCK_ROOT_ControlBySetPointMode(clock_root_t name, const clock_root_setpoint_config_t *spTable);
3161 
3162 /*!
3163  * @brief Set this clock works in CPU Low Power Mode.
3164  *
3165  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3166  *
3167  * @param name Clock root name, see \ref clock_root_t.
3168  * @param domainId Domains that on the whitelist can change this clock.
3169  */
CLOCK_ROOT_ControlByDomainMode(clock_root_t name,uint8_t domainId)3170 static inline void CLOCK_ROOT_ControlByDomainMode(clock_root_t name, uint8_t domainId)
3171 {
3172     CCM->CLOCK_ROOT[name].AUTHEN = (CCM->CLOCK_ROOT[name].AUTHEN & ~(CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK |
3173                                                                      CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK)) |
3174                                    CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK | CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(domainId);
3175 }
3176 
3177 /*!
3178  * @brief Lock low power and access control mode for this clock.
3179  *
3180  * @note When this bit is set, bits 16-20 can not be changed until next system reset.
3181  *
3182  * @param name Clock gate name, see \ref clock_lpcg_t.
3183  */
CLOCK_LPCG_LockControlMode(clock_lpcg_t name)3184 static inline void CLOCK_LPCG_LockControlMode(clock_lpcg_t name)
3185 {
3186     CCM->LPCG[name].AUTHEN |= CCM_LPCG_AUTHEN_LOCK_MODE_MASK;
3187 }
3188 
3189 /*!
3190  * @brief Lock the value of Domain ID white list for this clock.
3191  *
3192  * @note Once locked, this bit and domain ID white list can not be changed until next system reset.
3193  *
3194  * @param name Clock gate name, see \ref clock_lpcg_t.
3195  */
CLOCK_LPCG_LockWhiteList(clock_lpcg_t name)3196 static inline void CLOCK_LPCG_LockWhiteList(clock_lpcg_t name)
3197 {
3198     CCM->LPCG[name].AUTHEN |= CCM_LPCG_AUTHEN_LOCK_LIST_MASK;
3199 }
3200 
3201 /*!
3202  * @brief Set domain ID that can change this clock.
3203  *
3204  * @note If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset.
3205  *
3206  * @param name Clock gate name, see \ref clock_lpcg_t.
3207  * @param domainId Domains that on the whitelist can change this clock.
3208  */
CLOCK_LPCG_SetWhiteList(clock_lpcg_t name,uint8_t domainId)3209 static inline void CLOCK_LPCG_SetWhiteList(clock_lpcg_t name, uint8_t domainId)
3210 {
3211     CCM->LPCG[name].AUTHEN =
3212         (CCM->LPCG[name].AUTHEN & ~CCM_LPCG_AUTHEN_WHITE_LIST_MASK) | CCM_LPCG_AUTHEN_WHITE_LIST(domainId);
3213 }
3214 
3215 /*!
3216  * @brief Check whether this clock implement SetPoint control scheme.
3217  *
3218  * @param name Clock gate name, see \ref clock_lpcg_t.
3219  * @return  Clock gate SetPoint implement status.
3220  *         - true: SetPoint is implemented.
3221  *         - false: SetPoint is not implemented.
3222  */
CLOCK_LPCG_IsSetPointImplemented(clock_lpcg_t name)3223 static inline bool CLOCK_LPCG_IsSetPointImplemented(clock_lpcg_t name)
3224 {
3225     return (((CCM->LPCG[name].CONFIG & CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK) >>
3226              CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT) != 0UL);
3227 }
3228 
3229 /*!
3230  * @brief Set this clock works in Unassigned Mode.
3231  *
3232  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3233  *
3234  * @param name Clock gate name, see \ref clock_lpcg_t.
3235  */
CLOCK_LPCG_ControlByUnassignedMode(clock_lpcg_t name)3236 static inline void CLOCK_LPCG_ControlByUnassignedMode(clock_lpcg_t name)
3237 {
3238     CCM->LPCG[name].AUTHEN &=
3239         ~(CCM_LPCG_AUTHEN_CPULPM_MASK | CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK);
3240 }
3241 
3242 /*!
3243  * @brief Set this clock works in SetPoint control Mode.
3244  *
3245  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3246  *
3247  * @param name Clock gate name, see \ref clock_lpcg_t.
3248  * @param spValue Bit0~Bit15 hold value for Setpoint 0~16 respectively.
3249  *                A bitfield value of 0 implies clock will be shutdown in this Setpoint.
3250  *                A bitfield value of 1 implies clock will be turn on in this Setpoint.
3251  * @param stbyValue Bit0~Bit15 hold value for Setpoint 0~16 standby.
3252  *                A bitfield value of 0 implies clock will be shutdown during standby.
3253  *                A bitfield value of 1 represent clock will keep Setpoint setting during standby.
3254  */
3255 void CLOCK_LPCG_ControlBySetPointMode(clock_lpcg_t name, uint16_t spValue, uint16_t stbyValue);
3256 
3257 /*!
3258  * @brief Set this clock works in CPU Low Power Mode.
3259  *
3260  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3261  *
3262  * @param name Clock gate name, see \ref clock_lpcg_t.
3263  * @param domainId Domains that on the whitelist can change this clock.
3264  * @param level0,level1 Depend level of this clock.
3265  */
3266 void CLOCK_LPCG_ControlByCpuLowPowerMode(clock_lpcg_t name,
3267                                          uint8_t domainId,
3268                                          clock_level_t level0,
3269                                          clock_level_t level1);
3270 
3271 /*!
3272  * @brief Set clock depend level for current accessing domain.
3273  *
3274  * @note This setting only take effects in CPU Low Power Mode.
3275  *
3276  * @param name Clock gate name, see \ref clock_lpcg_t.
3277  * @param level Depend level of this clock.
3278  */
CLOCK_LPCG_SetCurrentClockLevel(clock_lpcg_t name,clock_level_t level)3279 static inline void CLOCK_LPCG_SetCurrentClockLevel(clock_lpcg_t name, clock_level_t level)
3280 {
3281     CCM->LPCG[name].DOMAINr = (CCM->LPCG[name].DOMAINr & ~CCM_LPCG_DOMAIN_LEVEL_MASK) | CCM_LPCG_DOMAIN_LEVEL(level);
3282 }
3283 
3284 /*!
3285  * @brief Set this clock works in Domain Mode.
3286  *
3287  * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset.
3288  *
3289  * @param name Clock gate name, see \ref clock_lpcg_t.
3290  * @param domainId Domains that on the whitelist can change this clock.
3291  */
CLOCK_LPCG_ControlByDomainMode(clock_lpcg_t name,uint8_t domainId)3292 static inline void CLOCK_LPCG_ControlByDomainMode(clock_lpcg_t name, uint8_t domainId)
3293 {
3294     CCM->LPCG[name].AUTHEN =
3295         (CCM->LPCG[name].AUTHEN &
3296          ~(CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK | CCM_LPCG_AUTHEN_CPULPM_MASK | CCM_LPCG_AUTHEN_WHITE_LIST_MASK)) |
3297         CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_WHITE_LIST(domainId);
3298 }
3299 
3300 /* @} */
3301 
3302 #if defined(__cplusplus)
3303 }
3304 #endif /* __cplusplus */
3305 
3306 /*! @} */
3307 
3308 #endif /* _FSL_CLOCK_H_ */
3309