1 /*
2 * Copyright 2020-2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_NIC301_H_
9 #define _FSL_NIC301_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup nic301
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /* Component ID definition, used by tools. */
23 #ifndef FSL_COMPONENT_ID
24 #define FSL_COMPONENT_ID "platform.drivers.nic301"
25 #endif
26
27 /*! @name Driver version */
28 /*@{*/
29 /*! @brief NIC301 driver version 2.0.1. */
30 #define FSL_NIC301_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
31 /*@}*/
32
33 #define GPV0_BASE (0x41000000UL)
34 #define GPV1_BASE (0x41100000UL)
35 #define GPV4_BASE (0x41400000UL)
36
37 #define NIC_FN_MOD2_OFFSET (0x024UL)
38 #define NIC_FN_MOD_AHB_OFFSET (0x028UL)
39 #define NIC_WR_TIDEMARK_OFFSET (0x040UL)
40 #define NIC_READ_QOS_OFFSET (0x100UL)
41 #define NIC_WRITE_QOS_OFFSET (0x104UL)
42 #define NIC_FN_MOD_OFFSET (0x108UL)
43
44 #define NIC_LCD_BASE (GPV0_BASE + 0x44000)
45 #define NIC_CSI_BASE (GPV0_BASE + 0x45000)
46 #define NIC_PXP_BASE (GPV0_BASE + 0x46000)
47
48 #define NIC_DCP_BASE (GPV1_BASE + 0x42000)
49 #define NIC_ENET_BASE (GPV1_BASE + 0x43000)
50 #define NIC_USBO2_BASE (GPV1_BASE + 0x44000)
51 #define NIC_USDHC1_BASE (GPV1_BASE + 0x45000)
52 #define NIC_USDHC2_BASE (GPV1_BASE + 0x46000)
53 #define NIC_TestPort_BASE (GPV1_BASE + 0x47000)
54 #define NIC_ENET2_BASE (GPV1_BASE + 0x48000)
55
56 #define NIC_CM7_BASE (GPV4_BASE + 0x42000)
57 #define NIC_DMA_BASE (GPV4_BASE + 0x43000)
58
59 #define NIC_QOS_MASK (0xF)
60 #define NIC_WR_TIDEMARK_MASK (0x7)
61 #define NIC_FN_MOD_AHB_MASK (0x7)
62 #define NIC_FN_MOD_MASK (0x1)
63 #define NIC_FN_MOD2_MASK (0x1)
64
65 typedef enum _nic_reg
66 {
67 /* read_qos */
68 kNIC_REG_READ_QOS_LCD = NIC_LCD_BASE + NIC_READ_QOS_OFFSET,
69 kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET,
70 kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET,
71 kNIC_REG_READ_QOS_DCP = NIC_DCP_BASE + NIC_READ_QOS_OFFSET,
72 kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET,
73 kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET,
74 kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET,
75 kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET,
76 kNIC_REG_READ_QOS_TestPort = NIC_TestPort_BASE + NIC_READ_QOS_OFFSET,
77 kNIC_REG_READ_QOS_ENET2 = NIC_ENET2_BASE + NIC_READ_QOS_OFFSET,
78 kNIC_REG_READ_QOS_CM7 = NIC_CM7_BASE + NIC_READ_QOS_OFFSET,
79 kNIC_REG_READ_QOS_DMA = NIC_DMA_BASE + NIC_READ_QOS_OFFSET,
80
81 /* write_qos */
82 kNIC_REG_WRITE_QOS_LCD = NIC_LCD_BASE + NIC_WRITE_QOS_OFFSET,
83 kNIC_REG_WRITE_QOS_CSI = NIC_CSI_BASE + NIC_WRITE_QOS_OFFSET,
84 kNIC_REG_WRITE_QOS_PXP = NIC_PXP_BASE + NIC_WRITE_QOS_OFFSET,
85 kNIC_REG_WRITE_QOS_DCP = NIC_DCP_BASE + NIC_WRITE_QOS_OFFSET,
86 kNIC_REG_WRITE_QOS_ENET = NIC_ENET_BASE + NIC_WRITE_QOS_OFFSET,
87 kNIC_REG_WRITE_QOS_USBO2 = NIC_USBO2_BASE + NIC_WRITE_QOS_OFFSET,
88 kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET,
89 kNIC_REG_WRITE_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_WRITE_QOS_OFFSET,
90 kNIC_REG_WRITE_QOS_TestPort = NIC_TestPort_BASE + NIC_WRITE_QOS_OFFSET,
91 kNIC_REG_WRITE_QOS_ENET2 = NIC_ENET2_BASE + NIC_WRITE_QOS_OFFSET,
92 kNIC_REG_WRITE_QOS_CM7 = NIC_CM7_BASE + NIC_WRITE_QOS_OFFSET,
93 kNIC_REG_WRITE_QOS_DMA = NIC_DMA_BASE + NIC_WRITE_QOS_OFFSET,
94
95 /* fn_mod */
96 kNIC_REG_FN_MOD_LCD = NIC_LCD_BASE + NIC_FN_MOD_OFFSET,
97 kNIC_REG_FN_MOD_CSI = NIC_CSI_BASE + NIC_FN_MOD_OFFSET,
98 kNIC_REG_FN_MOD_PXP = NIC_PXP_BASE + NIC_FN_MOD_OFFSET,
99 kNIC_REG_FN_MOD_DCP = NIC_DCP_BASE + NIC_FN_MOD_OFFSET,
100 kNIC_REG_FN_MOD_ENET = NIC_ENET_BASE + NIC_FN_MOD_OFFSET,
101 kNIC_REG_FN_MOD_USBO2 = NIC_USBO2_BASE + NIC_FN_MOD_OFFSET,
102 kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET,
103 kNIC_REG_FN_MOD_USDHC2 = NIC_USDHC2_BASE + NIC_FN_MOD_OFFSET,
104 kNIC_REG_FN_MOD_TestPort = NIC_TestPort_BASE + NIC_FN_MOD_OFFSET,
105 kNIC_REG_FN_MOD_ENET2 = NIC_ENET2_BASE + NIC_FN_MOD_OFFSET,
106 kNIC_REG_FN_MOD_CM7 = NIC_CM7_BASE + NIC_FN_MOD_OFFSET,
107 kNIC_REG_FN_MOD_DMA = NIC_DMA_BASE + NIC_FN_MOD_OFFSET,
108
109 /* fn_mod2 */
110 kNIC_REG_FN_MOD2_DCP = NIC_DCP_BASE + NIC_FN_MOD2_OFFSET,
111
112 /* fn_mod_ahb */
113 kNIC_REG_FN_MOD_AHB_ENET = NIC_ENET_BASE + NIC_FN_MOD_AHB_OFFSET,
114 kNIC_REG_FN_MOD_AHB_TestPort = NIC_TestPort_BASE + NIC_FN_MOD_AHB_OFFSET,
115 kNIC_REG_FN_MOD_AHB_ENET2 = NIC_ENET2_BASE + NIC_FN_MOD_AHB_OFFSET,
116 kNIC_REG_FN_MOD_AHB_DMA = NIC_DMA_BASE + NIC_FN_MOD_AHB_OFFSET,
117
118 /* wr_tidemark */
119 kNIC_REG_WR_TIDEMARK_CM7 = NIC_CM7_BASE + NIC_WR_TIDEMARK_OFFSET,
120 } nic_reg_t;
121
122 /* fn_mod2 */
123 typedef enum _nic_fn_mod2
124 {
125 kNIC_FN_MOD2_ENABLE = 0,
126 kNIC_FN_MOD2_BYPASS,
127 } nic_fn_mod2_t;
128
129 /* fn_mod_ahb */
130 typedef enum _nic_fn_mod_ahb
131 {
132 kNIC_FN_MOD_AHB_RD_INCR_OVERRIDE = 0,
133 kNIC_FN_MOD_AHB_WR_INCR_OVERRIDE,
134 kNIC_FN_MOD_AHB_LOCK_OVERRIDE,
135 } nic_fn_mod_ahb_t;
136
137 /* fn_mod */
138 typedef enum _nic_fn_mod
139 {
140 kNIC_FN_MOD_ReadIssue = 0,
141 kNIC_FN_MOD_WriteIssue,
142 } nic_fn_mod_t;
143
144 /* read_qos/write_qos */
145 typedef enum _nic_qos
146 {
147 kNIC_QOS_0 = 0,
148 kNIC_QOS_1,
149 kNIC_QOS_2,
150 kNIC_QOS_3,
151 kNIC_QOS_4,
152 kNIC_QOS_5,
153 kNIC_QOS_6,
154 kNIC_QOS_7,
155 kNIC_QOS_8,
156 kNIC_QOS_9,
157 kNIC_QOS_10,
158 kNIC_QOS_11,
159 kNIC_QOS_12,
160 kNIC_QOS_13,
161 kNIC_QOS_14,
162 kNIC_QOS_15,
163 } nic_qos_t;
164
165 /*******************************************************************************
166 * API
167 ******************************************************************************/
168 #if defined(__cplusplus)
169 extern "C" {
170 #endif /* __cplusplus */
171
172 /*!
173 * @brief Set read_qos Value
174 *
175 * @param base Base address of GPV address
176 * @param value Target value (0 - 15)
177 */
NIC_SetReadQos(nic_reg_t base,nic_qos_t value)178 static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value)
179 {
180 *(volatile uint32_t *)(base) = (value & NIC_QOS_MASK);
181 __DSB();
182 }
183
184 /*!
185 * @brief Get read_qos Value
186 *
187 * @param base Base address of GPV address
188 * @return Current value configured
189 */
NIC_GetReadQos(nic_reg_t base)190 static inline nic_qos_t NIC_GetReadQos(nic_reg_t base)
191 {
192 return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK);
193 }
194
195 /*!
196 * @brief Set write_qos Value
197 *
198 * @param base Base address of GPV address
199 * @param value Target value (0 - 15)
200 */
NIC_SetWriteQos(nic_reg_t base,nic_qos_t value)201 static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value)
202 {
203 *(volatile uint32_t *)(base) = (value & NIC_QOS_MASK);
204 __DSB();
205 }
206
207 /*!
208 * @brief Get write_qos Value
209 *
210 * @param base Base address of GPV address
211 * @return Current value configured
212 */
NIC_GetWriteQos(nic_reg_t base)213 static inline nic_qos_t NIC_GetWriteQos(nic_reg_t base)
214 {
215 return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK);
216 }
217
218 /*!
219 * @brief Set fn_mod_ahb Value
220 *
221 * @param base Base address of GPV address
222 * @param value Target value
223 */
NIC_SetFnModAhb(nic_reg_t base,nic_fn_mod_ahb_t value)224 static inline void NIC_SetFnModAhb(nic_reg_t base, nic_fn_mod_ahb_t value)
225 {
226 *(volatile uint32_t *)(base) = value;
227 __DSB();
228 }
229
230 /*!
231 * @brief Get fn_mod_ahb Value
232 *
233 * @param base Base address of GPV address
234 * @return Current value configured
235 */
NIC_GetFnModAhb(nic_reg_t base)236 static inline nic_fn_mod_ahb_t NIC_GetFnModAhb(nic_reg_t base)
237 {
238 return (nic_fn_mod_ahb_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_AHB_MASK);
239 }
240
241 /*!
242 * @brief Set wr_tidemark Value
243 *
244 * @param base Base address of GPV address
245 * @param value Target value (0 - 7)
246 */
NIC_SetWrTideMark(nic_reg_t base,uint8_t value)247 static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value)
248 {
249 *(volatile uint32_t *)(base) = (value & NIC_WR_TIDEMARK_MASK);
250 __DSB();
251 }
252
253 /*!
254 * @brief Get wr_tidemark Value
255 *
256 * @param base Base address of GPV address
257 * @return Current value configured
258 */
NIC_GetWrTideMark(nic_reg_t base)259 static inline uint8_t NIC_GetWrTideMark(nic_reg_t base)
260 {
261 return (uint8_t)((*(volatile uint32_t *)(base)) & NIC_WR_TIDEMARK_MASK);
262 }
263
264 /*!
265 * @brief Set fn_mod Value
266 *
267 * @param base Base address of GPV address
268 * @param value Target value
269 */
NIC_SetFnMod(nic_reg_t base,nic_fn_mod_t value)270 static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value)
271 {
272 *(volatile uint32_t *)(base) = value;
273 __DSB();
274 }
275
276 /*!
277 * @brief Get fn_mod Value
278 *
279 * @param base Base address of GPV address
280 * @return Current value configured
281 */
NIC_GetFnMod(nic_reg_t base)282 static inline nic_fn_mod_t NIC_GetFnMod(nic_reg_t base)
283 {
284 return (nic_fn_mod_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_MASK);
285 }
286
287 /*!
288 * @brief Set fn_mod2 Value
289 *
290 * @param base Base address of GPV address
291 * @param value Target value
292 */
NIC_SetFnMod2(nic_reg_t base,nic_fn_mod_t value)293 static inline void NIC_SetFnMod2(nic_reg_t base, nic_fn_mod_t value)
294 {
295 *(volatile uint32_t *)(base) = value;
296 __DSB();
297 }
298
299 /*!
300 * @brief Get fn_mod2 Value
301 *
302 * @param base Base address of GPV address
303 * @return Current value configured
304 */
NIC_GetFnMod2(nic_reg_t base)305 static inline nic_fn_mod2_t NIC_GetFnMod2(nic_reg_t base)
306 {
307 return (nic_fn_mod2_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD2_MASK);
308 }
309
310 #if defined(__cplusplus)
311 }
312 #endif /* __cplusplus */
313 /*!
314 * @}
315 */
316 #endif /* _FSL_NIC301_H_ */
317
