1 /*
2 * Copyright 2018 - 2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Configurations
20 ******************************************************************************/
21
22 /*! @brief Configure whether driver controls clock
23 *
24 * When set to 0, peripheral drivers will enable clock in initialize function
25 * and disable clock in de-initialize function. When set to 1, peripheral
26 * driver will not control the clock, application could control the clock out of
27 * the driver.
28 *
29 * @note All drivers share this feature switcher. If it is set to 1, application
30 * should handle clock enable and disable for all drivers.
31 */
32 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
33 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
34 #endif
35
36 /*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40 /*! @name Driver version */
41 /*@{*/
42 /*! @brief CLOCK driver version 2.0.0. */
43 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
44
45 /* Definition for delay API in clock driver, users can redefine it to the real application. */
46 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
47 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
48 #endif
49
50 /* analog pll definition */
51 #define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
52 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
53 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
54
55 /*@}*/
56
57 /*!
58 * @brief CCM registers offset.
59 */
60 #define CCSR_OFFSET 0x0C
61 #define CBCDR_OFFSET 0x14
62 #define CBCMR_OFFSET 0x18
63 #define CSCMR1_OFFSET 0x1C
64 #define CSCMR2_OFFSET 0x20
65 #define CSCDR1_OFFSET 0x24
66 #define CDCDR_OFFSET 0x30
67 #define CSCDR2_OFFSET 0x38
68 #define CSCDR3_OFFSET 0x3C
69 #define CACRR_OFFSET 0x10
70 #define CS1CDR_OFFSET 0x28
71 #define CS2CDR_OFFSET 0x2C
72
73 /*!
74 * @brief CCM Analog registers offset.
75 */
76 #define PLL_ARM_OFFSET 0x00
77 #define PLL_SYS_OFFSET 0x30
78 #define PLL_USB1_OFFSET 0x10
79 #define PLL_AUDIO_OFFSET 0x70
80 #define PLL_VIDEO_OFFSET 0xA0
81 #define PLL_ENET_OFFSET 0xE0
82 #define PLL_USB2_OFFSET 0x20
83
84 #define CCM_TUPLE(reg, shift, mask, busyShift) \
85 (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
86 #define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFU))))
87 #define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU)
88 #define CCM_TUPLE_MASK(tuple) \
89 ((uint32_t)((((uint32_t)(tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
90 #define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU)
91
92 #define CCM_NO_BUSY_WAIT (0x20U)
93
94 /*!
95 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
96 */
97 #define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift))
98 #define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)
99 #define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
100 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
101 #define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
102
103 /* Definition for ERRATA 50235 check */
104 #if (defined(FSL_FEATURE_CCM_HAS_ERRATA_50235) && FSL_FEATURE_CCM_HAS_ERRATA_50235)
105 #define CAN_CLOCK_CHECK_NO_AFFECTS \
106 ((CCM_CSCMR2_CAN_CLK_SEL(2U) != (CCM->CSCMR2 & CCM_CSCMR2_CAN_CLK_SEL_MASK)) || \
107 (CCM_CCGR5_CG12(0) != (CCM->CCGR5 & CCM_CCGR5_CG12_MASK)))
108 #endif /* FSL_FEATURE_CCM_HAS_ERRATA_50235 */
109
110 /*!
111 * @brief clock1PN frequency.
112 */
113 #define CLKPN_FREQ 0U
114
115 /*! @brief External XTAL (24M OSC/SYSOSC) clock frequency.
116 *
117 * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the
118 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
119 * if XTAL is 24MHz,
120 * @code
121 * CLOCK_InitExternalClk(false);
122 * CLOCK_SetXtalFreq(240000000);
123 * @endcode
124 */
125 extern volatile uint32_t g_xtalFreq;
126
127 /*! @brief External RTC XTAL (32K OSC) clock frequency.
128 *
129 * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the
130 * function CLOCK_SetRtcXtalFreq to set the value in to clock driver.
131 */
132 extern volatile uint32_t g_rtcXtalFreq;
133
134 /* For compatible with other platforms */
135 #define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
136 #define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq
137
138 /*! @brief Clock ip name array for ADC. */
139 #define ADC_CLOCKS \
140 { \
141 kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \
142 }
143
144 /*! @brief Clock ip name array for AOI. */
145 #define AOI_CLOCKS \
146 { \
147 kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
148 }
149
150 /*! @brief Clock ip name array for BEE. */
151 #define BEE_CLOCKS \
152 { \
153 kCLOCK_Bee \
154 }
155
156 /*! @brief Clock ip name array for CMP. */
157 #define CMP_CLOCKS \
158 { \
159 kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
160 }
161
162 /*! @brief Clock ip name array for DCDC. */
163 #define DCDC_CLOCKS \
164 { \
165 kCLOCK_Dcdc \
166 }
167
168 /*! @brief Clock ip name array for DCP. */
169 #define DCP_CLOCKS \
170 { \
171 kCLOCK_Dcp \
172 }
173
174 /*! @brief Clock ip name array for DMAMUX_CLOCKS. */
175 #define DMAMUX_CLOCKS \
176 { \
177 kCLOCK_Dma \
178 }
179
180 /*! @brief Clock ip name array for DMA. */
181 #define EDMA_CLOCKS \
182 { \
183 kCLOCK_Dma \
184 }
185
186 /*! @brief Clock ip name array for ENC. */
187 #define ENC_CLOCKS \
188 { \
189 kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
190 }
191
192 /*! @brief Clock ip name array for ENET. */
193 #define ENET_CLOCKS \
194 { \
195 kCLOCK_Enet \
196 }
197
198 /*! @brief Clock ip name array for EWM. */
199 #define EWM_CLOCKS \
200 { \
201 kCLOCK_Ewm0 \
202 }
203
204 /*! @brief Clock ip name array for FLEXCAN. */
205 #define FLEXCAN_CLOCKS \
206 { \
207 kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \
208 }
209
210 /*! @brief Clock ip name array for FLEXCAN Peripheral clock. */
211 #define FLEXCAN_PERIPH_CLOCKS \
212 { \
213 kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S, kCLOCK_Can3S \
214 }
215
216 /*! @brief Clock ip name array for FLEXIO. */
217 #define FLEXIO_CLOCKS \
218 { \
219 kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2, kCLOCK_Flexio3 \
220 }
221
222 /*! @brief Clock ip name array for FLEXRAM. */
223 #define FLEXRAM_CLOCKS \
224 { \
225 kCLOCK_FlexRam \
226 }
227
228 /*! @brief Clock ip name array for FLEXSPI. */
229 #define FLEXSPI_CLOCKS \
230 { \
231 kCLOCK_FlexSpi, kCLOCK_IpInvalid, kCLOCK_FlexSpi2 \
232 }
233
234 /*! @brief Clock ip name array for FLEXSPI EXSC. */
235 #define FLEXSPI_EXSC_CLOCKS \
236 { \
237 kCLOCK_FlexSpiExsc \
238 }
239
240 /*! @brief Clock ip name array for GPIO. */
241 #define GPIO_CLOCKS \
242 { \
243 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
244 }
245
246 /*! @brief Clock ip name array for GPT. */
247 #define GPT_CLOCKS \
248 { \
249 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
250 }
251
252 /*! @brief Clock ip name array for LCDIF. */
253 #define LCDIF_CLOCKS \
254 { \
255 kCLOCK_Lcd \
256 }
257
258 /*! @brief Clock ip name array for LCDIF PIXEL. */
259 #define LCDIF_PERIPH_CLOCKS \
260 { \
261 kCLOCK_LcdPixel \
262 }
263
264 /*! @brief Clock ip name array for LPI2C. */
265 #define LPI2C_CLOCKS \
266 { \
267 kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \
268 }
269
270 /*! @brief Clock ip name array for LPSPI. */
271 #define LPSPI_CLOCKS \
272 { \
273 kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3 \
274 }
275
276 /*! @brief Clock ip name array for LPUART. */
277 #define LPUART_CLOCKS \
278 { \
279 kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
280 kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \
281 }
282
283 /*! @brief Clock ip name array for MQS. */
284 #define MQS_CLOCKS \
285 { \
286 kCLOCK_Mqs \
287 }
288
289 /*! @brief Clock ip name array for OCRAM EXSC. */
290 #define OCRAM_EXSC_CLOCKS \
291 { \
292 kCLOCK_OcramExsc \
293 }
294
295 /*! @brief Clock ip name array for PIT. */
296 #define PIT_CLOCKS \
297 { \
298 kCLOCK_Pit \
299 }
300
301 /*! @brief Clock ip name array for PWM. */
302 #define PWM_CLOCKS \
303 { \
304 {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
305 {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, \
306 {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \
307 {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \
308 { \
309 kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \
310 } \
311 }
312
313 /*! @brief Clock ip name array for PXP. */
314 #define PXP_CLOCKS \
315 { \
316 kCLOCK_Pxp \
317 }
318
319 /*! @brief Clock ip name array for RTWDOG. */
320 #define RTWDOG_CLOCKS \
321 { \
322 kCLOCK_Wdog3 \
323 }
324
325 /*! @brief Clock ip name array for SAI. */
326 #define SAI_CLOCKS \
327 { \
328 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
329 }
330
331 /*! @brief Clock ip name array for SEMC. */
332 #define SEMC_CLOCKS \
333 { \
334 kCLOCK_Semc \
335 }
336
337 /*! @brief Clock ip name array for SEMC EXSC. */
338 #define SEMC_EXSC_CLOCKS \
339 { \
340 kCLOCK_SemcExsc \
341 }
342
343 /*! @brief Clock ip name array for QTIMER. */
344 #define TMR_CLOCKS \
345 { \
346 kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
347 }
348
349 /*! @brief Clock ip name array for TRNG. */
350 #define TRNG_CLOCKS \
351 { \
352 kCLOCK_Trng \
353 }
354
355 /*! @brief Clock ip name array for TSC. */
356 #define TSC_CLOCKS \
357 { \
358 kCLOCK_Tsc \
359 }
360
361 /*! @brief Clock ip name array for WDOG. */
362 #define WDOG_CLOCKS \
363 { \
364 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
365 }
366
367 /*! @brief Clock ip name array for USDHC. */
368 #define USDHC_CLOCKS \
369 { \
370 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
371 }
372
373 /*! @brief Clock ip name array for SPDIF. */
374 #define SPDIF_CLOCKS \
375 { \
376 kCLOCK_Spdif \
377 }
378
379 /*! @brief Clock ip name array for XBARA. */
380 #define XBARA_CLOCKS \
381 { \
382 kCLOCK_IpInvalid, kCLOCK_Xbar1 \
383 }
384
385 /*! @brief Clock ip name array for XBARB. */
386 #define XBARB_CLOCKS \
387 { \
388 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
389 }
390
391 #define CLOCK_SOURCE_NONE (0xFFU)
392
393 #define CLOCK_ROOT_SOUCE \
394 { \
395 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \
396 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC1 Clock Root. */ \
397 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \
398 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC2 Clock Root. */ \
399 {kCLOCK_SemcClk, kCLOCK_Usb1SwClk, kCLOCK_SysPllPfd2Clk, \
400 kCLOCK_Usb1PllPfd0Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXSPI Clock Root. */ \
401 {kCLOCK_SysPllPfd2Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_Usb1PllPfd1Clk, \
402 kCLOCK_SysPllClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXSPI2 Clock Root. */ \
403 {kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_SysPllClk, \
404 kCLOCK_SysPllPfd2Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPSPI Clock Root. */ \
405 {kCLOCK_SysPllClk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, \
406 kCLOCK_SysPllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* TRACE Clock Root */ \
407 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
408 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI1 Clock Root */ \
409 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
410 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI2 Clock Root */ \
411 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
412 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI3 Clock Root */ \
413 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_NoneName, \
414 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPI2C Clock Root */ \
415 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_Usb1Sw80MClk, \
416 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* CAN Clock Root. */ \
417 {kCLOCK_Usb1Sw80MClk, kCLOCK_OscClk, kCLOCK_NoneName, \
418 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* UART Clock Root */ \
419 {kCLOCK_SysPllClk, kCLOCK_Usb1PllPfd3Clk, kCLOCK_VideoPllClk, \
420 kCLOCK_SysPllPfd0Clk, kCLOCK_SysPllPfd1Clk, kCLOCK_Usb1PllPfd1Clk}, /* LCDIF Clock Root */ \
421 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
422 kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* SPDIF0 Clock Root */ \
423 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
424 kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO1 Clock Root */ \
425 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
426 kCLOCK_Usb1PllClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO2 Clock ROOT */ \
427 }
428
429 #define CLOCK_ROOT_MUX_TUPLE \
430 { \
431 kCLOCK_Usdhc1Mux, kCLOCK_Usdhc2Mux, kCLOCK_FlexspiMux, kCLOCK_Flexspi2Mux, kCLOCK_LpspiMux, kCLOCK_TraceMux, \
432 kCLOCK_Sai1Mux, kCLOCK_Sai2Mux, kCLOCK_Sai3Mux, kCLOCK_Lpi2cMux, kCLOCK_CanMux, kCLOCK_UartMux, \
433 kCLOCK_LcdifPreMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux, kCLOCK_Flexio2Mux, \
434 }
435
436 #define CLOCK_ROOT_NONE_PRE_DIV 0UL
437
438 #define CLOCK_ROOT_DIV_TUPLE \
439 { \
440 {kCLOCK_NonePreDiv, kCLOCK_Usdhc1Div}, {kCLOCK_NonePreDiv, kCLOCK_Usdhc2Div}, \
441 {kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_Flexspi2Div}, \
442 {kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_TraceDiv}, \
443 {kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, {kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div}, \
444 {kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv}, \
445 {kCLOCK_NonePreDiv, kCLOCK_CanDiv}, {kCLOCK_NonePreDiv, kCLOCK_UartDiv}, \
446 {kCLOCK_LcdifPreDiv, kCLOCK_LcdifDiv}, {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div}, \
447 {kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, {kCLOCK_Flexio2PreDiv, kCLOCK_Flexio2Div}, \
448 }
449
450 /*! @brief Clock name used to get clock frequency. */
451 typedef enum _clock_name
452 {
453 kCLOCK_CpuClk = 0x0U, /*!< CPU clock */
454 kCLOCK_AhbClk = 0x1U, /*!< AHB clock */
455 kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */
456 kCLOCK_IpgClk = 0x3U, /*!< IPG clock */
457 kCLOCK_PerClk = 0x4U, /*!< PER clock */
458
459 kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
460 kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */
461
462 kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */
463
464 kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */
465 kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */
466 kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */
467 kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */
468 kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */
469 kCLOCK_Usb1SwClk = 0x18U, /*!< USB1PLLSWCLK */
470 kCLOCK_Usb1Sw120MClk = 0x19U, /*!< USB1PLLSw120MCLK */
471 kCLOCK_Usb1Sw60MClk = 0x1AU, /*!< USB1PLLSw60MCLK */
472 kCLOCK_Usb1Sw80MClk = 0x1BU, /*!< USB1PLLSw80MCLK */
473
474 kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */
475
476 kCLOCK_SysPllClk = 0xEU, /*!< SYSPLLCLK. */
477 kCLOCK_SysPllPfd0Clk = 0xFU, /*!< SYSPLLPDF0CLK. */
478 kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */
479 kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */
480 kCLOCK_SysPllPfd3Clk = 0x12U, /*!< SYSPLLPFD3CLK. */
481
482 kCLOCK_EnetPll0Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll0. */
483 kCLOCK_EnetPll1Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll1. */
484
485 kCLOCK_AudioPllClk = 0x15U, /*!< Audio PLLCLK. */
486 kCLOCK_VideoPllClk = 0x16U, /*!< Video PLLCLK. */
487
488 kCLOCK_NoneName = CLOCK_SOURCE_NONE, /*!< None Clock Name. */
489 } clock_name_t;
490
491 #define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */
492 #define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */
493
494 /*!
495 * @brief CCM CCGR gate control for each module independently.
496 */
497 typedef enum _clock_ip_name
498 {
499 kCLOCK_IpInvalid = -1,
500
501 /* CCM CCGR0 */
502 kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */
503 kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */
504 kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */
505 kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */
506 kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */
507 kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */
508 kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */
509 kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */
510 kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */
511 kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */
512 kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */
513 kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */
514 kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */
515 kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */
516 kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */
517 kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */
518
519 /* CCM CCGR1 */
520 kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */
521 kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */
522 kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */
523 kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */
524 kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */
525 kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */
526 kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */
527 kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */
528 kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */
529 kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */
530 kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */
531 kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */
532 kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */
533 kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */
534 kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */
535
536 /* CCM CCGR2 */
537 kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */
538 kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */
539 kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */
540 kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */
541 kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */
542 kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */
543 kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */
544 kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */
545 kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */
546 kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */
547 kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */
548 kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */
549 kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */
550 kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */
551 kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */
552
553 /* CCM CCGR3 */
554 kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */
555 kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */
556 kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */
557 kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */
558 kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */
559 kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */
560 kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */
561 kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */
562 kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */
563 kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */
564 kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */
565 kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */
566 kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */
567 kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */
568 kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */
569 kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */
570
571 /* CCM CCGR4 */
572 kCLOCK_Sim_m7_clk_r = (4U << 8U) | CCM_CCGR4_CG0_SHIFT, /*!< CCGR4, CG0 */
573 kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */
574 kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */
575 kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */
576 kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */
577 kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */
578 kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */
579 kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */
580 kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */
581 kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */
582 kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */
583 kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */
584 kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */
585 kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */
586 kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */
587 kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */
588
589 /* CCM CCGR5 */
590 kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */
591 kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */
592 kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */
593 kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */
594 kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */
595 kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */
596 kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */
597 kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */
598 kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */
599 kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */
600 kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */
601 kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */
602 kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */
603 kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */
604 kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */
605
606 /* CCM CCGR6 */
607 kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */
608 kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */
609 kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */
610 kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */
611 kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */
612 kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */
613 kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */
614 kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */
615 kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */
616 kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */
617 kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */
618 kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */
619 kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */
620 kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */
621 kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */
622 kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */
623
624 /* CCM CCGR7 */
625 kCLOCK_FlexSpi2 = (7U << 8U) | CCM_CCGR7_CG1_SHIFT, /*!< CCGR7, CG1 */
626 kCLOCK_Axbs_l = (7U << 8U) | CCM_CCGR7_CG2_SHIFT, /*!< CCGR7, CG2 */
627 kCLOCK_Can3 = (7U << 8U) | CCM_CCGR7_CG3_SHIFT, /*!< CCGR7, CG3 */
628 kCLOCK_Can3S = (7U << 8U) | CCM_CCGR7_CG4_SHIFT, /*!< CCGR7, CG4 */
629 kCLOCK_Aips_lite = (7U << 8U) | CCM_CCGR7_CG5_SHIFT, /*!< CCGR7, CG5 */
630 kCLOCK_Flexio3 = (7U << 8U) | CCM_CCGR7_CG6_SHIFT, /*!< CCGR7, CG6 */
631
632 } clock_ip_name_t;
633
634 /*! @brief OSC 24M sorce select */
635 typedef enum _clock_osc
636 {
637 kCLOCK_RcOsc = 0U, /*!< On chip OSC. */
638 kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */
639 } clock_osc_t;
640
641 /*! @brief Clock gate value */
642 typedef enum _clock_gate_value
643 {
644 kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */
645 kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */
646 kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */
647 } clock_gate_value_t;
648
649 /*! @brief System clock mode */
650 typedef enum _clock_mode_t
651 {
652 kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */
653 kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */
654 kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */
655 } clock_mode_t;
656
657 /*!
658 * @brief MUX control names for clock mux setting.
659 *
660 * These constants define the mux control names for clock mux setting.\n
661 * - 0:7: REG offset to CCM_BASE in bytes.
662 * - 8:15: Root clock setting bit field shift.
663 * - 16:31: Root clock setting bit field width.
664 */
665 typedef enum _clock_mux
666 {
667 kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
668 CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT,
669 CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
670 CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */
671
672 kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
673 CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
674 CCM_CBCDR_PERIPH_CLK_SEL_MASK,
675 CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */
676 kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
677 CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT,
678 CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK,
679 CCM_NO_BUSY_WAIT), /*!< semc mux name */
680 kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET,
681 CCM_CBCDR_SEMC_CLK_SEL_SHIFT,
682 CCM_CBCDR_SEMC_CLK_SEL_MASK,
683 CCM_NO_BUSY_WAIT), /*!< semc mux name */
684
685 kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
686 CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
687 CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
688 CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */
689 kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
690 CCM_CBCMR_TRACE_CLK_SEL_SHIFT,
691 CCM_CBCMR_TRACE_CLK_SEL_MASK,
692 CCM_NO_BUSY_WAIT), /*!< trace mux name */
693 kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
694 CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
695 CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
696 CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */
697 kCLOCK_Flexspi2Mux = CCM_TUPLE(CBCMR_OFFSET,
698 CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT,
699 CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK,
700 CCM_NO_BUSY_WAIT), /*!< flexspi2 mux name */
701 kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
702 CCM_CBCMR_LPSPI_CLK_SEL_SHIFT,
703 CCM_CBCMR_LPSPI_CLK_SEL_MASK,
704 CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
705
706 kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
707 CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
708 CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
709 CCM_NO_BUSY_WAIT), /*!< flexspi mux name */
710 kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET,
711 CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT,
712 CCM_CSCMR1_USDHC2_CLK_SEL_MASK,
713 CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */
714 kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET,
715 CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT,
716 CCM_CSCMR1_USDHC1_CLK_SEL_MASK,
717 CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */
718 kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET,
719 CCM_CSCMR1_SAI3_CLK_SEL_SHIFT,
720 CCM_CSCMR1_SAI3_CLK_SEL_MASK,
721 CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
722 kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET,
723 CCM_CSCMR1_SAI2_CLK_SEL_SHIFT,
724 CCM_CSCMR1_SAI2_CLK_SEL_MASK,
725 CCM_NO_BUSY_WAIT), /*!< sai2 mux name */
726 kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET,
727 CCM_CSCMR1_SAI1_CLK_SEL_SHIFT,
728 CCM_CSCMR1_SAI1_CLK_SEL_MASK,
729 CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
730 kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
731 CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
732 CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
733 CCM_NO_BUSY_WAIT), /*!< perclk mux name */
734
735 kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2_OFFSET,
736 CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT,
737 CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK,
738 CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */
739 kCLOCK_CanMux = CCM_TUPLE(CSCMR2_OFFSET,
740 CCM_CSCMR2_CAN_CLK_SEL_SHIFT,
741 CCM_CSCMR2_CAN_CLK_SEL_MASK,
742 CCM_NO_BUSY_WAIT), /*!< can mux name */
743
744 kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET,
745 CCM_CSCDR1_UART_CLK_SEL_SHIFT,
746 CCM_CSCDR1_UART_CLK_SEL_MASK,
747 CCM_NO_BUSY_WAIT), /*!< uart mux name */
748
749 kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET,
750 CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT,
751 CCM_CDCDR_SPDIF0_CLK_SEL_MASK,
752 CCM_NO_BUSY_WAIT), /*!< spdif mux name */
753 kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR_OFFSET,
754 CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT,
755 CCM_CDCDR_FLEXIO1_CLK_SEL_MASK,
756 CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */
757
758 kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET,
759 CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT,
760 CCM_CSCDR2_LPI2C_CLK_SEL_MASK,
761 CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
762 kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2_OFFSET,
763 CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT,
764 CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK,
765 CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */
766 } clock_mux_t;
767
768 /*!
769 * @brief Clock divider value.
770 */
771 typedef enum _clock_div_value
772 {
773 kCLOCK_ArmDivBy1 = 0, /*!< ARM clock divider set to divided by 1. */
774 kCLOCK_ArmDivBy2 = 1, /*!< ARM clock divider set to divided by 2. */
775 kCLOCK_ArmDivBy3 = 2, /*!< ARM clock divider set to divided by 3. */
776 kCLOCK_ArmDivBy4 = 3, /*!< ARM clock divider set to divided by 4. */
777 kCLOCK_ArmDivBy5 = 4, /*!< ARM clock divider set to divided by 5. */
778 kCLOCK_ArmDivBy6 = 5, /*!< ARM clock divider set to divided by 6. */
779 kCLOCK_ArmDivBy7 = 6, /*!< ARM clock divider set to divided by 7. */
780 kCLOCK_ArmDivBy8 = 7, /*!< ARM clock divider set to divided by 8. */
781
782 kCLOCK_PeriphClk2DivBy1 = 0, /*!< PeriphClk2 divider set to divided by 1. */
783 kCLOCK_PeriphClk2DivBy2 = 1, /*!< PeriphClk2 divider set to divided by 2. */
784 kCLOCK_PeriphClk2DivBy3 = 2, /*!< PeriphClk2 divider set to divided by 3. */
785 kCLOCK_PeriphClk2DivBy4 = 3, /*!< PeriphClk2 divider set to divided by 4. */
786 kCLOCK_PeriphClk2DivBy5 = 4, /*!< PeriphClk2 divider set to divided by 5. */
787 kCLOCK_PeriphClk2DivBy6 = 5, /*!< PeriphClk2 divider set to divided by 6. */
788 kCLOCK_PeriphClk2DivBy7 = 6, /*!< PeriphClk2 divider set to divided by 7. */
789 kCLOCK_PeriphClk2DivBy8 = 7, /*!< PeriphClk2 divider set to divided by 8. */
790
791 kCLOCK_SemcDivBy1 = 0, /*!< SEMC clock divider set to divided by 1. */
792 kCLOCK_SemcDivBy2 = 1, /*!< SEMC clock divider set to divided by 2. */
793 kCLOCK_SemcDivBy3 = 2, /*!< SEMC clock divider set to divided by 3. */
794 kCLOCK_SemcDivBy4 = 3, /*!< SEMC clock divider set to divided by 4. */
795 kCLOCK_SemcDivBy5 = 4, /*!< SEMC clock divider set to divided by 5. */
796 kCLOCK_SemcDivBy6 = 5, /*!< SEMC clock divider set to divided by 6. */
797 kCLOCK_SemcDivBy7 = 6, /*!< SEMC clock divider set to divided by 7. */
798 kCLOCK_SemcDivBy8 = 7, /*!< SEMC clock divider set to divided by 8. */
799
800 kCLOCK_AhbDivBy1 = 0, /*!< AHB clock divider set to divided by 1. */
801 kCLOCK_AhbDivBy2 = 1, /*!< AHB clock divider set to divided by 2. */
802 kCLOCK_AhbDivBy3 = 2, /*!< AHB clock divider set to divided by 3. */
803 kCLOCK_AhbDivBy4 = 3, /*!< AHB clock divider set to divided by 4. */
804 kCLOCK_AhbDivBy5 = 4, /*!< AHB clock divider set to divided by 5. */
805 kCLOCK_AhbDivBy6 = 5, /*!< AHB clock divider set to divided by 6. */
806 kCLOCK_AhbDivBy7 = 6, /*!< AHB clock divider set to divided by 7. */
807 kCLOCK_AhbDivBy8 = 7, /*!< AHB clock divider set to divided by 8. */
808
809 kCLOCK_IpgDivBy1 = 0, /*!< IPG clock divider set to divided by 1. */
810 kCLOCK_IpgDivBy2 = 1, /*!< IPG clock divider set to divided by 2. */
811 kCLOCK_IpgDivBy3 = 2, /*!< IPG clock divider set to divided by 3. */
812 kCLOCK_IpgDivBy4 = 3, /*!< IPG clock divider set to divided by 4. */
813
814 kCLOCK_Flexspi2DivBy1 = 0, /*!< Flexspi2 divider set to divided by 1. */
815 kCLOCK_Flexspi2DivBy2 = 1, /*!< Flexspi2 divider set to divided by 2. */
816 kCLOCK_Flexspi2DivBy3 = 2, /*!< Flexspi2 divider set to divided by 3. */
817 kCLOCK_Flexspi2DivBy4 = 3, /*!< Flexspi2 divider set to divided by 4. */
818 kCLOCK_Flexspi2DivBy5 = 4, /*!< Flexspi2 divider set to divided by 5. */
819 kCLOCK_Flexspi2DivBy6 = 5, /*!< Flexspi2 divider set to divided by 6. */
820 kCLOCK_Flexspi2DivBy7 = 6, /*!< Flexspi2 divider set to divided by 7. */
821 kCLOCK_Flexspi2DivBy8 = 7, /*!< Flexspi2 divider set to divided by 8. */
822
823 kCLOCK_LpspiDivBy1 = 0, /*!< Lpspi divider set to divided by 1. */
824 kCLOCK_LpspiDivBy2 = 1, /*!< Lpspi divider set to divided by 2. */
825 kCLOCK_LpspiDivBy3 = 2, /*!< Lpspi divider set to divided by 3. */
826 kCLOCK_LpspiDivBy4 = 3, /*!< Lpspi divider set to divided by 4. */
827 kCLOCK_LpspiDivBy5 = 4, /*!< Lpspi divider set to divided by 5. */
828 kCLOCK_LpspiDivBy6 = 5, /*!< Lpspi divider set to divided by 6. */
829 kCLOCK_LpspiDivBy7 = 6, /*!< Lpspi divider set to divided by 7. */
830 kCLOCK_LpspiDivBy8 = 7, /*!< Lpspi divider set to divided by 8. */
831
832 kCLOCK_LcdifDivBy1 = 0, /*!< Lcdif divider set to divided by 1. */
833 kCLOCK_LcdifDivBy2 = 1, /*!< Lcdif divider set to divided by 2. */
834 kCLOCK_LcdifDivBy3 = 2, /*!< Lcdif divider set to divided by 3. */
835 kCLOCK_LcdifDivBy4 = 3, /*!< Lcdif divider set to divided by 4. */
836 kCLOCK_LcdifDivBy5 = 4, /*!< Lcdif divider set to divided by 5. */
837 kCLOCK_LcdifDivBy6 = 5, /*!< Lcdif divider set to divided by 6. */
838 kCLOCK_LcdifDivBy7 = 6, /*!< Lcdif divider set to divided by 7. */
839 kCLOCK_LcdifDivBy8 = 7, /*!< Lcdif divider set to divided by 8. */
840
841 kCLOCK_FlexspiDivBy1 = 0, /*!< Flexspi divider set to divided by 1. */
842 kCLOCK_FlexspiDivBy2 = 1, /*!< Flexspi divider set to divided by 2. */
843 kCLOCK_FlexspiDivBy3 = 2, /*!< Flexspi divider set to divided by 3. */
844 kCLOCK_FlexspiDivBy4 = 3, /*!< Flexspi divider set to divided by 4. */
845 kCLOCK_FlexspiDivBy5 = 4, /*!< Flexspi divider set to divided by 5. */
846 kCLOCK_FlexspiDivBy6 = 5, /*!< Flexspi divider set to divided by 6. */
847 kCLOCK_FlexspiDivBy7 = 6, /*!< Flexspi divider set to divided by 7. */
848 kCLOCK_FlexspiDivBy8 = 7, /*!< Flexspi divider set to divided by 8. */
849
850 kCLOCK_TraceDivBy1 = 0, /*!< Trace divider set to divided by 1. */
851 kCLOCK_TraceDivBy2 = 1, /*!< Trace divider set to divided by 2. */
852 kCLOCK_TraceDivBy3 = 2, /*!< Trace divider set to divided by 3. */
853 kCLOCK_TraceDivBy4 = 3, /*!< Trace divider set to divided by 4. */
854
855 kCLOCK_Usdhc2DivBy1 = 0, /*!< Usdhc2 divider set to divided by 1. */
856 kCLOCK_Usdhc2DivBy2 = 1, /*!< Usdhc2 divider set to divided by 2. */
857 kCLOCK_Usdhc2DivBy3 = 2, /*!< Usdhc2 divider set to divided by 3. */
858 kCLOCK_Usdhc2DivBy4 = 3, /*!< Usdhc2 divider set to divided by 4. */
859 kCLOCK_Usdhc2DivBy5 = 4, /*!< Usdhc2 divider set to divided by 5. */
860 kCLOCK_Usdhc2DivBy6 = 5, /*!< Usdhc2 divider set to divided by 6. */
861 kCLOCK_Usdhc2DivBy7 = 6, /*!< Usdhc2 divider set to divided by 7. */
862 kCLOCK_Usdhc2DivBy8 = 7, /*!< Usdhc2 divider set to divided by 8. */
863
864 kCLOCK_Usdhc1DivBy1 = 0, /*!< Usdhc1 divider set to divided by 1. */
865 kCLOCK_Usdhc1DivBy2 = 1, /*!< Usdhc1 divider set to divided by 2. */
866 kCLOCK_Usdhc1DivBy3 = 2, /*!< Usdhc1 divider set to divided by 3. */
867 kCLOCK_Usdhc1DivBy4 = 3, /*!< Usdhc1 divider set to divided by 4. */
868 kCLOCK_Usdhc1DivBy5 = 4, /*!< Usdhc1 divider set to divided by 5. */
869 kCLOCK_Usdhc1DivBy6 = 5, /*!< Usdhc1 divider set to divided by 6. */
870 kCLOCK_Usdhc1DivBy7 = 6, /*!< Usdhc1 divider set to divided by 7. */
871 kCLOCK_Usdhc1DivBy8 = 7, /*!< Usdhc1 divider set to divided by 8. */
872
873 kCLOCK_Flexio2DivBy1 = 0, /*!< Flexio2 divider set to divided by 1. */
874 kCLOCK_Flexio2DivBy2 = 1, /*!< Flexio2 divider set to divided by 2. */
875 kCLOCK_Flexio2DivBy3 = 2, /*!< Flexio2 divider set to divided by 3. */
876 kCLOCK_Flexio2DivBy4 = 3, /*!< Flexio2 divider set to divided by 4. */
877 kCLOCK_Flexio2DivBy5 = 4, /*!< Flexio2 divider set to divided by 5. */
878 kCLOCK_Flexio2DivBy6 = 5, /*!< Flexio2 divider set to divided by 6. */
879 kCLOCK_Flexio2DivBy7 = 6, /*!< Flexio2 divider set to divided by 7. */
880 kCLOCK_Flexio2DivBy8 = 7, /*!< Flexio2 divider set to divided by 8. */
881
882 kCLOCK_Sai3PreDivBy1 = 0, /*!< Sai3Pre divider set to divided by 1. */
883 kCLOCK_Sai3PreDivBy2 = 1, /*!< Sai3Pre divider set to divided by 2. */
884 kCLOCK_Sai3PreDivBy3 = 2, /*!< Sai3Pre divider set to divided by 3. */
885 kCLOCK_Sai3PreDivBy4 = 3, /*!< Sai3Pre divider set to divided by 4. */
886 kCLOCK_Sai3PreDivBy5 = 4, /*!< Sai3Pre divider set to divided by 5. */
887 kCLOCK_Sai3PreDivBy6 = 5, /*!< Sai3Pre divider set to divided by 6. */
888 kCLOCK_Sai3PreDivBy7 = 6, /*!< Sai3Pre divider set to divided by 7. */
889 kCLOCK_Sai3PreDivBy8 = 7, /*!< Sai3Pre divider set to divided by 8. */
890
891 kCLOCK_Flexio2PreDivBy1 = 0, /*!< Flexio2Pre divider set to divided by 1. */
892 kCLOCK_Flexio2PreDivBy2 = 1, /*!< Flexio2Pre divider set to divided by 2. */
893 kCLOCK_Flexio2PreDivBy3 = 2, /*!< Flexio2Pre divider set to divided by 3. */
894 kCLOCK_Flexio2PreDivBy4 = 3, /*!< Flexio2Pre divider set to divided by 4. */
895 kCLOCK_Flexio2PreDivBy5 = 4, /*!< Flexio2Pre divider set to divided by 5. */
896 kCLOCK_Flexio2PreDivBy6 = 5, /*!< Flexio2Pre divider set to divided by 6. */
897 kCLOCK_Flexio2PreDivBy7 = 6, /*!< Flexio2Pre divider set to divided by 7. */
898 kCLOCK_Flexio2PreDivBy8 = 7, /*!< Flexio2Pre divider set to divided by 8. */
899
900 kCLOCK_Sai1PreDivBy1 = 0, /*!< Sai1Pre divider set to divided by 1. */
901 kCLOCK_Sai1PreDivBy2 = 1, /*!< Sai1Pre divider set to divided by 2. */
902 kCLOCK_Sai1PreDivBy3 = 2, /*!< Sai1Pre divider set to divided by 3. */
903 kCLOCK_Sai1PreDivBy4 = 3, /*!< Sai1Pre divider set to divided by 4. */
904 kCLOCK_Sai1PreDivBy5 = 4, /*!< Sai1Pre divider set to divided by 5. */
905 kCLOCK_Sai1PreDivBy6 = 5, /*!< Sai1Pre divider set to divided by 6. */
906 kCLOCK_Sai1PreDivBy7 = 6, /*!< Sai1Pre divider set to divided by 7. */
907 kCLOCK_Sai1PreDivBy8 = 7, /*!< Sai1Pre divider set to divided by 8. */
908
909 kCLOCK_Sai2PreDivBy1 = 0, /*!< Sai2Pre divider set to divided by 1. */
910 kCLOCK_Sai2PreDivBy2 = 1, /*!< Sai2Pre divider set to divided by 2. */
911 kCLOCK_Sai2PreDivBy3 = 2, /*!< Sai2Pre divider set to divided by 3. */
912 kCLOCK_Sai2PreDivBy4 = 3, /*!< Sai2Pre divider set to divided by 4. */
913 kCLOCK_Sai2PreDivBy5 = 4, /*!< Sai2Pre divider set to divided by 5. */
914 kCLOCK_Sai2PreDivBy6 = 5, /*!< Sai2Pre divider set to divided by 6. */
915 kCLOCK_Sai2PreDivBy7 = 6, /*!< Sai2Pre divider set to divided by 7. */
916 kCLOCK_Sai2PreDivBy8 = 7, /*!< Sai2Pre divider set to divided by 8. */
917
918 kCLOCK_Spdif0PreDivBy1 = 0, /*!< Spdif0Pre divider set to divided by 1. */
919 kCLOCK_Spdif0PreDivBy2 = 1, /*!< Spdif0Pre divider set to divided by 2. */
920 kCLOCK_Spdif0PreDivBy3 = 2, /*!< Spdif0Pre divider set to divided by 3. */
921 kCLOCK_Spdif0PreDivBy4 = 3, /*!< Spdif0Pre divider set to divided by 4. */
922 kCLOCK_Spdif0PreDivBy5 = 4, /*!< Spdif0Pre divider set to divided by 5. */
923 kCLOCK_Spdif0PreDivBy6 = 5, /*!< Spdif0Pre divider set to divided by 6. */
924 kCLOCK_Spdif0PreDivBy7 = 6, /*!< Spdif0Pre divider set to divided by 7. */
925 kCLOCK_Spdif0PreDivBy8 = 7, /*!< Spdif0Pre divider set to divided by 8. */
926
927 kCLOCK_Spdif0DivBy1 = 0, /*!< Spdif0 divider set to divided by 1. */
928 kCLOCK_Spdif0DivBy2 = 1, /*!< Spdif0 divider set to divided by 2. */
929 kCLOCK_Spdif0DivBy3 = 2, /*!< Spdif0 divider set to divided by 3. */
930 kCLOCK_Spdif0DivBy4 = 3, /*!< Spdif0 divider set to divided by 4. */
931 kCLOCK_Spdif0DivBy5 = 4, /*!< Spdif0 divider set to divided by 5. */
932 kCLOCK_Spdif0DivBy6 = 5, /*!< Spdif0 divider set to divided by 6. */
933 kCLOCK_Spdif0DivBy7 = 6, /*!< Spdif0 divider set to divided by 7. */
934 kCLOCK_Spdif0DivBy8 = 7, /*!< Spdif0 divider set to divided by 8. */
935
936 kCLOCK_Flexio1PreDivBy1 = 0, /*!< Flexio1Pre divider set to divided by 1. */
937 kCLOCK_Flexio1PreDivBy2 = 1, /*!< Flexio1Pre divider set to divided by 2. */
938 kCLOCK_Flexio1PreDivBy3 = 2, /*!< Flexio1Pre divider set to divided by 3. */
939 kCLOCK_Flexio1PreDivBy8 = 7, /*!< Flexio1Pre divider set to divided by 8. */
940
941 kCLOCK_Flexio1DivBy1 = 0, /*!< Flexio1 divider set to divided by 1. */
942 kCLOCK_Flexio1DivBy2 = 1, /*!< Flexio1 divider set to divided by 2. */
943 kCLOCK_Flexio1DivBy3 = 2, /*!< Flexio1 divider set to divided by 3. */
944 kCLOCK_Flexio1DivBy4 = 3, /*!< Flexio1 divider set to divided by 4. */
945 kCLOCK_Flexio1DivBy5 = 4, /*!< Flexio1 divider set to divided by 5. */
946 kCLOCK_Flexio1DivBy6 = 5, /*!< Flexio1 divider set to divided by 6. */
947 kCLOCK_Flexio1DivBy7 = 6, /*!< Flexio1 divider set to divided by 7. */
948 kCLOCK_Flexio1DivBy8 = 7, /*!< Flexio1 divider set to divided by 8. */
949
950 kCLOCK_LcdifPreDivBy1 = 0, /*!< LcdifPre divider set to divided by 1. */
951 kCLOCK_LcdifPreDivBy2 = 1, /*!< LcdifPre divider set to divided by 2. */
952 kCLOCK_LcdifPreDivBy3 = 2, /*!< LcdifPre divider set to divided by 3. */
953 kCLOCK_LcdifPreDivBy4 = 3, /*!< LcdifPre divider set to divided by 4. */
954 kCLOCK_LcdifPreDivBy5 = 4, /*!< LcdifPre divider set to divided by 5. */
955 kCLOCK_LcdifPreDivBy6 = 5, /*!< LcdifPre divider set to divided by 6. */
956 kCLOCK_LcdifPreDivBy7 = 6, /*!< LcdifPre divider set to divided by 7. */
957 kCLOCK_LcdifPreDivBy8 = 7, /*!< LcdifPre divider set to divided by 8. */
958
959 /* Only kCLOCK_PerClk, kCLOCK_Lpi2cDiv, kCLOCK_CanDiv, kCLOCK_UartDiv, kCLOCK_Sai1Div,
960 * kCLOCK_Sai2Div, kCLOCK_Sai3Div can use these.
961 */
962 kCLOCK_MiscDivBy1 = 0, /*!< Misc divider like LPI2C set to divided by 1 . */
963 kCLOCK_MiscDivBy2 = 1, /*!< Misc divider like LPI2C set to divided by 2 . */
964 kCLOCK_MiscDivBy3 = 2, /*!< Misc divider like LPI2C set to divided by 3 . */
965 kCLOCK_MiscDivBy4 = 3, /*!< Misc divider like LPI2C set to divided by 4 . */
966 kCLOCK_MiscDivBy5 = 4, /*!< Misc divider like LPI2C set to divided by 5 . */
967 kCLOCK_MiscDivBy6 = 5, /*!< Misc divider like LPI2C set to divided by 6 . */
968 kCLOCK_MiscDivBy7 = 6, /*!< Misc divider like LPI2C set to divided by 7 . */
969 kCLOCK_MiscDivBy8 = 7, /*!< Misc divider like LPI2C set to divided by 8 . */
970 kCLOCK_MiscDivBy9 = 8, /*!< Misc divider like LPI2C set to divided by 9 . */
971 kCLOCK_MiscDivBy10 = 9, /*!< Misc divider like LPI2C set to divided by 10. */
972 kCLOCK_MiscDivBy11 = 10, /*!< Misc divider like LPI2C set to divided by 11. */
973 kCLOCK_MiscDivBy12 = 11, /*!< Misc divider like LPI2C set to divided by 12. */
974 kCLOCK_MiscDivBy13 = 12, /*!< Misc divider like LPI2C set to divided by 13. */
975 kCLOCK_MiscDivBy14 = 13, /*!< Misc divider like LPI2C set to divided by 14. */
976 kCLOCK_MiscDivBy15 = 14, /*!< Misc divider like LPI2C set to divided by 15. */
977 kCLOCK_MiscDivBy16 = 15, /*!< Misc divider like LPI2C set to divided by 16. */
978 kCLOCK_MiscDivBy17 = 16, /*!< Misc divider like LPI2C set to divided by 17. */
979 kCLOCK_MiscDivBy18 = 17, /*!< Misc divider like LPI2C set to divided by 18. */
980 kCLOCK_MiscDivBy19 = 18, /*!< Misc divider like LPI2C set to divided by 19. */
981 kCLOCK_MiscDivBy20 = 19, /*!< Misc divider like LPI2C set to divided by 20. */
982 kCLOCK_MiscDivBy21 = 20, /*!< Misc divider like LPI2C set to divided by 21. */
983 kCLOCK_MiscDivBy22 = 21, /*!< Misc divider like LPI2C set to divided by 22. */
984 kCLOCK_MiscDivBy23 = 22, /*!< Misc divider like LPI2C set to divided by 23. */
985 kCLOCK_MiscDivBy24 = 23, /*!< Misc divider like LPI2C set to divided by 24. */
986 kCLOCK_MiscDivBy25 = 24, /*!< Misc divider like LPI2C set to divided by 25. */
987 kCLOCK_MiscDivBy26 = 25, /*!< Misc divider like LPI2C set to divided by 26. */
988 kCLOCK_MiscDivBy27 = 26, /*!< Misc divider like LPI2C set to divided by 27. */
989 kCLOCK_MiscDivBy28 = 27, /*!< Misc divider like LPI2C set to divided by 28. */
990 kCLOCK_MiscDivBy29 = 28, /*!< Misc divider like LPI2C set to divided by 29. */
991 kCLOCK_MiscDivBy30 = 29, /*!< Misc divider like LPI2C set to divided by 30. */
992 kCLOCK_MiscDivBy31 = 30, /*!< Misc divider like LPI2C set to divided by 31. */
993 kCLOCK_MiscDivBy32 = 31, /*!< Misc divider like LPI2C set to divided by 32. */
994 kCLOCK_MiscDivBy33 = 32, /*!< Misc divider like LPI2C set to divided by 33. */
995 kCLOCK_MiscDivBy34 = 33, /*!< Misc divider like LPI2C set to divided by 34. */
996 kCLOCK_MiscDivBy35 = 34, /*!< Misc divider like LPI2C set to divided by 35. */
997 kCLOCK_MiscDivBy36 = 35, /*!< Misc divider like LPI2C set to divided by 36. */
998 kCLOCK_MiscDivBy37 = 36, /*!< Misc divider like LPI2C set to divided by 37. */
999 kCLOCK_MiscDivBy38 = 37, /*!< Misc divider like LPI2C set to divided by 38. */
1000 kCLOCK_MiscDivBy39 = 38, /*!< Misc divider like LPI2C set to divided by 39. */
1001 kCLOCK_MiscDivBy40 = 39, /*!< Misc divider like LPI2C set to divided by 40. */
1002 kCLOCK_MiscDivBy41 = 40, /*!< Misc divider like LPI2C set to divided by 41. */
1003 kCLOCK_MiscDivBy42 = 41, /*!< Misc divider like LPI2C set to divided by 42. */
1004 kCLOCK_MiscDivBy43 = 42, /*!< Misc divider like LPI2C set to divided by 43. */
1005 kCLOCK_MiscDivBy44 = 43, /*!< Misc divider like LPI2C set to divided by 44. */
1006 kCLOCK_MiscDivBy45 = 44, /*!< Misc divider like LPI2C set to divided by 45. */
1007 kCLOCK_MiscDivBy46 = 45, /*!< Misc divider like LPI2C set to divided by 46. */
1008 kCLOCK_MiscDivBy47 = 46, /*!< Misc divider like LPI2C set to divided by 47. */
1009 kCLOCK_MiscDivBy48 = 47, /*!< Misc divider like LPI2C set to divided by 48. */
1010 kCLOCK_MiscDivBy49 = 48, /*!< Misc divider like LPI2C set to divided by 49. */
1011 kCLOCK_MiscDivBy50 = 49, /*!< Misc divider like LPI2C set to divided by 50. */
1012 kCLOCK_MiscDivBy51 = 50, /*!< Misc divider like LPI2C set to divided by 51. */
1013 kCLOCK_MiscDivBy52 = 51, /*!< Misc divider like LPI2C set to divided by 52. */
1014 kCLOCK_MiscDivBy53 = 52, /*!< Misc divider like LPI2C set to divided by 53. */
1015 kCLOCK_MiscDivBy54 = 53, /*!< Misc divider like LPI2C set to divided by 54. */
1016 kCLOCK_MiscDivBy55 = 54, /*!< Misc divider like LPI2C set to divided by 55. */
1017 kCLOCK_MiscDivBy56 = 55, /*!< Misc divider like LPI2C set to divided by 56. */
1018 kCLOCK_MiscDivBy57 = 56, /*!< Misc divider like LPI2C set to divided by 57. */
1019 kCLOCK_MiscDivBy58 = 57, /*!< Misc divider like LPI2C set to divided by 58. */
1020 kCLOCK_MiscDivBy59 = 58, /*!< Misc divider like LPI2C set to divided by 59. */
1021 kCLOCK_MiscDivBy60 = 59, /*!< Misc divider like LPI2C set to divided by 60. */
1022 kCLOCK_MiscDivBy61 = 60, /*!< Misc divider like LPI2C set to divided by 61. */
1023 kCLOCK_MiscDivBy62 = 61, /*!< Misc divider like LPI2C set to divided by 62. */
1024 kCLOCK_MiscDivBy63 = 62, /*!< Misc divider like LPI2C set to divided by 63. */
1025 kCLOCK_MiscDivBy64 = 63, /*!< Misc divider like LPI2C set to divided by 64. */
1026 } clock_div_value_t;
1027
1028 /*!
1029 * @brief DIV control names for clock div setting.
1030 *
1031 * These constants define div control names for clock div setting.\n
1032 * - 0:7: REG offset to CCM_BASE in bytes.
1033 * - 8:15: Root clock setting bit field shift.
1034 * - 16:31: Root clock setting bit field width.
1035 */
1036 typedef enum _clock_div
1037 {
1038 kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET,
1039 CCM_CACRR_ARM_PODF_SHIFT,
1040 CCM_CACRR_ARM_PODF_MASK,
1041 CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */
1042
1043 kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET,
1044 CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT,
1045 CCM_CBCDR_PERIPH_CLK2_PODF_MASK,
1046 CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */
1047 kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET,
1048 CCM_CBCDR_SEMC_PODF_SHIFT,
1049 CCM_CBCDR_SEMC_PODF_MASK,
1050 CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */
1051 kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET,
1052 CCM_CBCDR_AHB_PODF_SHIFT,
1053 CCM_CBCDR_AHB_PODF_MASK,
1054 CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
1055 kCLOCK_IpgDiv = CCM_TUPLE(
1056 CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
1057
1058 kCLOCK_Flexspi2Div = CCM_TUPLE(CBCMR_OFFSET,
1059 CCM_CBCMR_FLEXSPI2_PODF_SHIFT,
1060 CCM_CBCMR_FLEXSPI2_PODF_MASK,
1061 CCM_NO_BUSY_WAIT), /*!< flexspi2 div name */
1062 kCLOCK_LpspiDiv = CCM_TUPLE(
1063 CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */
1064 kCLOCK_LcdifDiv = CCM_TUPLE(
1065 CBCMR_OFFSET, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */
1066
1067 kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET,
1068 CCM_CSCMR1_FLEXSPI_PODF_SHIFT,
1069 CCM_CSCMR1_FLEXSPI_PODF_MASK,
1070 CCM_NO_BUSY_WAIT), /*!< flexspi div name */
1071 kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET,
1072 CCM_CSCMR1_PERCLK_PODF_SHIFT,
1073 CCM_CSCMR1_PERCLK_PODF_MASK,
1074 CCM_NO_BUSY_WAIT), /*!< perclk div name */
1075
1076 kCLOCK_CanDiv = CCM_TUPLE(CSCMR2_OFFSET,
1077 CCM_CSCMR2_CAN_CLK_PODF_SHIFT,
1078 CCM_CSCMR2_CAN_CLK_PODF_MASK,
1079 CCM_NO_BUSY_WAIT), /*!< can div name */
1080
1081 kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET,
1082 CCM_CSCDR1_TRACE_PODF_SHIFT,
1083 CCM_CSCDR1_TRACE_PODF_MASK,
1084 CCM_NO_BUSY_WAIT), /*!< trace div name */
1085 kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1_OFFSET,
1086 CCM_CSCDR1_USDHC2_PODF_SHIFT,
1087 CCM_CSCDR1_USDHC2_PODF_MASK,
1088 CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */
1089 kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1_OFFSET,
1090 CCM_CSCDR1_USDHC1_PODF_SHIFT,
1091 CCM_CSCDR1_USDHC1_PODF_MASK,
1092 CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */
1093 kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET,
1094 CCM_CSCDR1_UART_CLK_PODF_SHIFT,
1095 CCM_CSCDR1_UART_CLK_PODF_MASK,
1096 CCM_NO_BUSY_WAIT), /*!< uart div name */
1097
1098 kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR_OFFSET,
1099 CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT,
1100 CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK,
1101 CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */
1102 kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
1103 CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
1104 CCM_CS1CDR_SAI3_CLK_PRED_MASK,
1105 CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
1106 kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET,
1107 CCM_CS1CDR_SAI3_CLK_PODF_SHIFT,
1108 CCM_CS1CDR_SAI3_CLK_PODF_MASK,
1109 CCM_NO_BUSY_WAIT), /*!< sai3 div name */
1110 kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
1111 CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT,
1112 CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK,
1113 CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
1114 kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
1115 CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
1116 CCM_CS1CDR_SAI1_CLK_PRED_MASK,
1117 CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */
1118 kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET,
1119 CCM_CS1CDR_SAI1_CLK_PODF_SHIFT,
1120 CCM_CS1CDR_SAI1_CLK_PODF_MASK,
1121 CCM_NO_BUSY_WAIT), /*!< sai1 div name */
1122
1123 kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET,
1124 CCM_CS2CDR_SAI2_CLK_PRED_SHIFT,
1125 CCM_CS2CDR_SAI2_CLK_PRED_MASK,
1126 CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */
1127 kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET,
1128 CCM_CS2CDR_SAI2_CLK_PODF_SHIFT,
1129 CCM_CS2CDR_SAI2_CLK_PODF_MASK,
1130 CCM_NO_BUSY_WAIT), /*!< sai2 div name */
1131
1132 kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
1133 CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
1134 CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
1135 CCM_NO_BUSY_WAIT), /*!< spdif pre div name */
1136 kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
1137 CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
1138 CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
1139 CCM_NO_BUSY_WAIT), /*!< spdif div name */
1140 kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR_OFFSET,
1141 CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT,
1142 CCM_CDCDR_FLEXIO1_CLK_PRED_MASK,
1143 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
1144 kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR_OFFSET,
1145 CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT,
1146 CCM_CDCDR_FLEXIO1_CLK_PODF_MASK,
1147 CCM_NO_BUSY_WAIT), /*!< flexio1 div name */
1148
1149 kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
1150 CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
1151 CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
1152 CCM_NO_BUSY_WAIT), /*!< lpi2c div name */
1153 kCLOCK_LcdifPreDiv = CCM_TUPLE(CSCDR2_OFFSET,
1154 CCM_CSCDR2_LCDIF_PRED_SHIFT,
1155 CCM_CSCDR2_LCDIF_PRED_MASK,
1156 CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */
1157
1158 kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV, /*!< None Pre div. */
1159 } clock_div_t;
1160
1161 /*! @brief USB clock source definition. */
1162 typedef enum _clock_usb_src
1163 {
1164 kCLOCK_Usb480M = 0, /*!< Use 480M. */
1165 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
1166 care the clock source. */
1167 } clock_usb_src_t;
1168
1169 /*! @brief Source of the USB HS PHY. */
1170 typedef enum _clock_usb_phy_src
1171 {
1172 kCLOCK_Usbphy480M = 0, /*!< Use 480M. */
1173 } clock_usb_phy_src_t;
1174
1175 /*!@brief PLL clock source, bypass cloco source also */
1176 enum _clock_pll_clk_src
1177 {
1178 kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */
1179 kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */
1180 };
1181
1182 /*! @brief PLL configuration for ARM */
1183 typedef struct _clock_arm_pll_config
1184 {
1185 uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */
1186 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1187 } clock_arm_pll_config_t;
1188
1189 /*! @brief PLL configuration for USB */
1190 typedef struct _clock_usb_pll_config
1191 {
1192 uint8_t loopDivider; /*!< PLL loop divider.
1193 0 - Fout=Fref*20;
1194 1 - Fout=Fref*22 */
1195 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1196
1197 } clock_usb_pll_config_t;
1198
1199 /*! @brief PLL configuration for System */
1200 typedef struct _clock_sys_pll_config
1201 {
1202 uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M).
1203 0 - Fout=Fref*20;
1204 1 - Fout=Fref*22 */
1205 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
1206 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
1207 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1208 uint16_t ss_stop; /*!< Stop value to get frequency change. */
1209 uint8_t ss_enable; /*!< Enable spread spectrum modulation */
1210 uint16_t ss_step; /*!< Step value to get frequency change step. */
1211 } clock_sys_pll_config_t;
1212
1213 /*! @brief PLL configuration for AUDIO and VIDEO */
1214 typedef struct _clock_audio_pll_config
1215 {
1216 uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
1217 uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
1218 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
1219 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
1220 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1221 } clock_audio_pll_config_t;
1222
1223 /*! @brief PLL configuration for AUDIO and VIDEO */
1224 typedef struct _clock_video_pll_config
1225 {
1226 uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
1227 uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
1228 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
1229 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
1230 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1231
1232 } clock_video_pll_config_t;
1233
1234 /*! @brief PLL configuration for ENET */
1235 typedef struct _clock_enet_pll_config
1236 {
1237 bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */
1238
1239 bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
1240 uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock.
1241 b00 25MHz
1242 b01 50MHz
1243 b10 100MHz (not 50% duty cycle)
1244 b11 125MHz */
1245 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1246 } clock_enet_pll_config_t;
1247
1248 /*! @brief PLL name */
1249 typedef enum _clock_pll
1250 {
1251 kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */
1252 kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */
1253 kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */
1254 kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */
1255 kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */
1256
1257 kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */
1258 kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet1 */
1259 } clock_pll_t;
1260
1261 /*! @brief PLL PFD name */
1262 typedef enum _clock_pfd
1263 {
1264 kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
1265 kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
1266 kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
1267 kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
1268 } clock_pfd_t;
1269
1270 /*!
1271 * @brief The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
1272 */
1273 typedef enum _clock_output1_selection
1274 {
1275 kCLOCK_OutputPllUsb1 = 0U, /*!< Selects USB1 PLL clock(Divided by 2) output. */
1276 kCLOCK_OutputPllSys = 1U, /*!< Selects SYS PLL clock(Divided by 2) output. */
1277 kCLOCK_OutputPllVideo = 3U, /*!< Selects Video PLL clock(Divided by 2) output. */
1278 kCLOCK_OutputSemcClk = 5U, /*!< Selects semc clock root output. */
1279 kCLOCK_OutputLcdifPixClk = 0xAU, /*!< Selects Lcdif pix clock root output. */
1280 kCLOCK_OutputAhbClk = 0xBU, /*!< Selects AHB clock root output. */
1281 kCLOCK_OutputIpgClk = 0xCU, /*!< Selects IPG clock root output. */
1282 kCLOCK_OutputPerClk = 0xDU, /*!< Selects PERCLK clock root output. */
1283 kCLOCK_OutputCkilSyncClk = 0xEU, /*!< Selects Ckil clock root output. */
1284 kCLOCK_OutputPll4MainClk = 0xFU, /*!< Selects PLL4 main clock output. */
1285 kCLOCK_DisableClockOutput1 = 0x10U, /*!< Disables CLKO1. */
1286 } clock_output1_selection_t;
1287
1288 /*!
1289 * @brief The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.
1290 *
1291 */
1292 typedef enum _clock_output2_selection
1293 {
1294 kCLOCK_OutputUsdhc1Clk = 3U, /*!< Selects USDHC1 clock root output. */
1295 kCLOCK_OutputLpi2cClk = 6U, /*!< Selects LPI2C clock root output. */
1296 kCLOCK_OutputOscClk = 0xEU, /*!< Selects OSC output. */
1297 kCLOCK_OutputUsdhc2Clk = 0x11U, /*!< Selects USDHC2 clock root output. */
1298 kCLOCK_OutputSai1Clk = 0x12U, /*!< Selects SAI1 clock root output. */
1299 kCLOCK_OutputSai2Clk = 0x13U, /*!< Selects SAI2 clock root output. */
1300 kCLOCK_OutputSai3Clk = 0x14U, /*!< Selects SAI3 clock root output. */
1301 kCLOCK_OutputCanClk = 0x17U, /*!< Selects CAN clock root output. */
1302 kCLOCK_OutputFlexspiClk = 0x1BU, /*!< Selects FLEXSPI clock root output. */
1303 kCLOCK_OutputUartClk = 0x1CU, /*!< Selects UART clock root output. */
1304 kCLOCK_OutputSpdif0Clk = 0x1DU, /*!< Selects SPDIF0 clock root output. */
1305 kCLOCK_DisableClockOutput2 = 0x1FU, /*!< Disables CLKO2. */
1306 } clock_output2_selection_t;
1307
1308 /*!
1309 * @brief The enumerator of clock output's divider.
1310 */
1311 typedef enum _clock_output_divider
1312 {
1313 kCLOCK_DivideBy1 = 0U, /*!< Output clock divided by 1. */
1314 kCLOCK_DivideBy2, /*!< Output clock divided by 2. */
1315 kCLOCK_DivideBy3, /*!< Output clock divided by 3. */
1316 kCLOCK_DivideBy4, /*!< Output clock divided by 4. */
1317 kCLOCK_DivideBy5, /*!< Output clock divided by 5. */
1318 kCLOCK_DivideBy6, /*!< Output clock divided by 6. */
1319 kCLOCK_DivideBy7, /*!< Output clock divided by 7. */
1320 kCLOCK_DivideBy8, /*!< Output clock divided by 8. */
1321 } clock_output_divider_t;
1322
1323 /*!
1324 * @brief The enumerator of clock root.
1325 */
1326 typedef enum _clock_root
1327 {
1328 kCLOCK_Usdhc1ClkRoot = 0U, /*!< USDHC1 clock root. */
1329 kCLOCK_Usdhc2ClkRoot, /*!< USDHC2 clock root. */
1330 kCLOCK_FlexspiClkRoot, /*!< FLEXSPI clock root. */
1331 kCLOCK_Flexspi2ClkRoot, /*!< FLEXSPI2 clock root. */
1332 kCLOCK_LpspiClkRoot, /*!< LPSPI clock root. */
1333 kCLOCK_TraceClkRoot, /*!< Trace clock root. */
1334 kCLOCK_Sai1ClkRoot, /*!< SAI1 clock root. */
1335 kCLOCK_Sai2ClkRoot, /*!< SAI2 clock root. */
1336 kCLOCK_Sai3ClkRoot, /*!< SAI3 clock root. */
1337 kCLOCK_Lpi2cClkRoot, /*!< LPI2C clock root. */
1338 kCLOCK_CanClkRoot, /*!< CAN clock root. */
1339 kCLOCK_UartClkRoot, /*!< UART clock root. */
1340 kCLOCK_LcdifClkRoot, /*!< LCD clock root. */
1341 kCLOCK_SpdifClkRoot, /*!< SPDIF clock root. */
1342 kCLOCK_Flexio1ClkRoot, /*!< FLEXIO1 clock root. */
1343 kCLOCK_Flexio2ClkRoot, /*!< FLEXIO2 clock root. */
1344 } clock_root_t;
1345
1346 /*******************************************************************************
1347 * API
1348 ******************************************************************************/
1349
1350 #if defined(__cplusplus)
1351 extern "C" {
1352 #endif /* __cplusplus */
1353
1354 /*!
1355 * @brief Set CCM MUX node to certain value.
1356 *
1357 * @param mux Which mux node to set, see \ref clock_mux_t.
1358 * @param value Clock mux value to set, different mux has different value range.
1359 */
CLOCK_SetMux(clock_mux_t mux,uint32_t value)1360 static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
1361 {
1362 uint32_t busyShift;
1363
1364 busyShift = (uint32_t)CCM_TUPLE_BUSY_SHIFT(mux);
1365 CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
1366 (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
1367
1368 assert(busyShift <= CCM_NO_BUSY_WAIT);
1369
1370 /* Clock switch need Handshake? */
1371 if (CCM_NO_BUSY_WAIT != busyShift)
1372 {
1373 /* Wait until CCM internal handshake finish. */
1374 while ((CCM->CDHIPR & ((1UL << busyShift))) != 0UL)
1375 {
1376 }
1377 }
1378 }
1379
1380 /*!
1381 * @brief Get CCM MUX value.
1382 *
1383 * @param mux Which mux node to get, see \ref clock_mux_t.
1384 * @return Clock mux value.
1385 */
CLOCK_GetMux(clock_mux_t mux)1386 static inline uint32_t CLOCK_GetMux(clock_mux_t mux)
1387 {
1388 return (((uint32_t)(CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux))) >> CCM_TUPLE_SHIFT(mux));
1389 }
1390
1391 /*!
1392 * @brief Set clock divider value.
1393 *
1394 * Example, set the ARM clock divider to divide by 2:
1395 * @code
1396 CLOCK_SetDiv(kCLOCK_ArmDiv, kCLOCK_ArmDivBy2);
1397 @endcode
1398 *
1399 * Example, set the LPI2C clock divider to divide by 5.
1400 * @code
1401 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, kCLOCK_MiscDivBy5);
1402 @endcode
1403 *
1404 * Only @ref kCLOCK_PerClk, @ref kCLOCK_Lpi2cDiv, @ref kCLOCK_CanDiv, @ref kCLOCK_UartDiv, @ref kCLOCK_Sai1Div,
1405 * @ref kCLOCK_Sai2Div, @ref kCLOCK_Sai3Div can use the divider kCLOCK_MiscDivByxxx.
1406 *
1407 * @param divider Which divider node to set.
1408 * @param value Clock div value to set, different divider has different value range. See @ref clock_div_value_t
1409 * for details.
1410 * Divided clock frequency = Undivided clock frequency / (value + 1)
1411 */
CLOCK_SetDiv(clock_div_t divider,uint32_t value)1412 static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
1413 {
1414 uint32_t busyShift;
1415
1416 busyShift = CCM_TUPLE_BUSY_SHIFT(divider);
1417 CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
1418 (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
1419
1420 assert(busyShift <= CCM_NO_BUSY_WAIT);
1421
1422 /* Clock switch need Handshake? */
1423 if (CCM_NO_BUSY_WAIT != busyShift)
1424 {
1425 /* Wait until CCM internal handshake finish. */
1426 while ((CCM->CDHIPR & ((uint32_t)(1UL << busyShift))) != 0UL)
1427 {
1428 }
1429 }
1430 }
1431
1432 /*!
1433 * @brief Get CCM DIV node value.
1434 *
1435 * @param divider Which div node to get, see \ref clock_div_t.
1436 */
CLOCK_GetDiv(clock_div_t divider)1437 static inline uint32_t CLOCK_GetDiv(clock_div_t divider)
1438 {
1439 return ((uint32_t)(CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
1440 }
1441
1442 /*!
1443 * @brief Control the clock gate for specific IP.
1444 *
1445 * @param name Which clock to enable, see \ref clock_ip_name_t.
1446 * @param value Clock gate value to set, see \ref clock_gate_value_t.
1447 */
CLOCK_ControlGate(clock_ip_name_t name,clock_gate_value_t value)1448 static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
1449 {
1450 uint32_t index = ((uint32_t)name) >> 8UL;
1451 uint32_t shift = ((uint32_t)name) & 0x1FUL;
1452 volatile uint32_t *reg;
1453
1454 assert(index <= 7UL);
1455
1456 reg = (volatile uint32_t *)(&(((volatile uint32_t *)&CCM->CCGR0)[index]));
1457 SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, (3UL << shift), (((uint32_t)value) << (uint32_t)shift));
1458 }
1459
1460 /*!
1461 * @brief Enable the clock for specific IP.
1462 *
1463 * @param name Which clock to enable, see \ref clock_ip_name_t.
1464 */
CLOCK_EnableClock(clock_ip_name_t name)1465 static inline void CLOCK_EnableClock(clock_ip_name_t name)
1466 {
1467 CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait);
1468 }
1469
1470 /*!
1471 * @brief Disable the clock for specific IP.
1472 *
1473 * @param name Which clock to disable, see \ref clock_ip_name_t.
1474 */
CLOCK_DisableClock(clock_ip_name_t name)1475 static inline void CLOCK_DisableClock(clock_ip_name_t name)
1476 {
1477 CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded);
1478 }
1479
1480 /*!
1481 * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal.
1482 *
1483 * @param mode Which mode to enter, see \ref clock_mode_t.
1484 */
CLOCK_SetMode(clock_mode_t mode)1485 static inline void CLOCK_SetMode(clock_mode_t mode)
1486 {
1487 CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode);
1488 }
1489
1490 /*!
1491 * @brief Gets the OSC clock frequency.
1492 *
1493 * This function will return the external XTAL OSC frequency if it is selected as the source of OSC,
1494 * otherwise internal 24MHz RC OSC frequency will be returned.
1495 *
1496 * @return Clock frequency; If the clock is invalid, returns 0.
1497 */
CLOCK_GetOscFreq(void)1498 static inline uint32_t CLOCK_GetOscFreq(void)
1499 {
1500 return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq;
1501 }
1502
1503 /*!
1504 * @brief Gets the AHB clock frequency.
1505 *
1506 * @return The AHB clock frequency value in hertz.
1507 */
1508 uint32_t CLOCK_GetAhbFreq(void);
1509
1510 /*!
1511 * @brief Gets the SEMC clock frequency.
1512 *
1513 * @return The SEMC clock frequency value in hertz.
1514 */
1515 uint32_t CLOCK_GetSemcFreq(void);
1516
1517 /*!
1518 * @brief Gets the IPG clock frequency.
1519 *
1520 * @return The IPG clock frequency value in hertz.
1521 */
1522 uint32_t CLOCK_GetIpgFreq(void);
1523
1524 /*!
1525 * @brief Gets the PER clock frequency.
1526 *
1527 * @return The PER clock frequency value in hertz.
1528 */
1529 uint32_t CLOCK_GetPerClkFreq(void);
1530
1531 /*!
1532 * @brief Gets the clock frequency for a specific clock name.
1533 *
1534 * This function checks the current clock configurations and then calculates
1535 * the clock frequency for a specific clock name defined in clock_name_t.
1536 *
1537 * @param name Clock names defined in clock_name_t
1538 * @return Clock frequency value in hertz
1539 */
1540 uint32_t CLOCK_GetFreq(clock_name_t name);
1541
1542 /*!
1543 * @brief Get the CCM CPU/core/system frequency.
1544 *
1545 * @return Clock frequency; If the clock is invalid, returns 0.
1546 */
CLOCK_GetCpuClkFreq(void)1547 static inline uint32_t CLOCK_GetCpuClkFreq(void)
1548 {
1549 return CLOCK_GetFreq(kCLOCK_CpuClk);
1550 }
1551
1552 /*!
1553 * @brief Gets the frequency of selected clock root.
1554 *
1555 * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
1556 * @return The frequency of selected clock root.
1557 */
1558 uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
1559
1560 /*!
1561 * @name OSC operations
1562 * @{
1563 */
1564
1565 /*!
1566 * @brief Initialize the external 24MHz clock.
1567 *
1568 * This function supports two modes:
1569 * 1. Use external crystal oscillator.
1570 * 2. Bypass the external crystal oscillator, using input source clock directly.
1571 *
1572 * After this function, please call CLOCK_SetXtal0Freq to inform clock driver
1573 * the external clock frequency.
1574 *
1575 * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
1576 * @note This device does not support bypass external crystal oscillator, so
1577 * the input parameter should always be false.
1578 */
1579 void CLOCK_InitExternalClk(bool bypassXtalOsc);
1580
1581 /*!
1582 * @brief Deinitialize the external 24MHz clock.
1583 *
1584 * This function disables the external 24MHz clock.
1585 *
1586 * After this function, please call CLOCK_SetXtal0Freq to set external clock
1587 * frequency to 0.
1588 */
1589 void CLOCK_DeinitExternalClk(void);
1590
1591 /*!
1592 * @brief Switch the OSC.
1593 *
1594 * This function switches the OSC source for SoC.
1595 *
1596 * @param osc OSC source to switch to.
1597 */
1598 void CLOCK_SwitchOsc(clock_osc_t osc);
1599
1600 /*!
1601 * @brief Gets the RTC clock frequency.
1602 *
1603 * @return Clock frequency; If the clock is invalid, returns 0.
1604 */
CLOCK_GetRtcFreq(void)1605 static inline uint32_t CLOCK_GetRtcFreq(void)
1606 {
1607 return 32768U;
1608 }
1609
1610 /*!
1611 * @brief Set the XTAL (24M OSC) frequency based on board setting.
1612 *
1613 * @param freq The XTAL input clock frequency in Hz.
1614 */
CLOCK_SetXtalFreq(uint32_t freq)1615 static inline void CLOCK_SetXtalFreq(uint32_t freq)
1616 {
1617 g_xtalFreq = freq;
1618 }
1619
1620 /*!
1621 * @brief Set the RTC XTAL (32K OSC) frequency based on board setting.
1622 *
1623 * @param freq The RTC XTAL input clock frequency in Hz.
1624 */
CLOCK_SetRtcXtalFreq(uint32_t freq)1625 static inline void CLOCK_SetRtcXtalFreq(uint32_t freq)
1626 {
1627 g_rtcXtalFreq = freq;
1628 }
1629
1630 /*!
1631 * @brief Initialize the RC oscillator 24MHz clock.
1632 */
1633 void CLOCK_InitRcOsc24M(void);
1634
1635 /*!
1636 * @brief Power down the RCOSC 24M clock.
1637 */
1638 void CLOCK_DeinitRcOsc24M(void);
1639 /* @} */
1640
1641 /*! @brief Enable USB HS clock.
1642 *
1643 * This function only enables the access to USB HS prepheral, upper layer
1644 * should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
1645 * clock to use USB HS.
1646 *
1647 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
1648 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
1649 * @retval true The clock is set successfully.
1650 * @retval false The clock source is invalid to get proper USB HS clock.
1651 */
1652 bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
1653
1654 /* @} */
1655
1656 /*!
1657 * @name PLL/PFD operations
1658 * @{
1659 */
1660 /*!
1661 * @brief PLL bypass setting
1662 *
1663 * @param base CCM_ANALOG base pointer.
1664 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1665 * @param bypass Bypass the PLL.
1666 * - true: Bypass the PLL.
1667 * - false:Not bypass the PLL.
1668 */
CLOCK_SetPllBypass(CCM_ANALOG_Type * base,clock_pll_t pll,bool bypass)1669 static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
1670 {
1671 if (bypass)
1672 {
1673 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1674 }
1675 else
1676 {
1677 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1678 }
1679 }
1680
1681 /*!
1682 * @brief Check if PLL is bypassed
1683 *
1684 * @param base CCM_ANALOG base pointer.
1685 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1686 * @return PLL bypass status.
1687 * - true: The PLL is bypassed.
1688 * - false: The PLL is not bypassed.
1689 */
CLOCK_IsPllBypassed(CCM_ANALOG_Type * base,clock_pll_t pll)1690 static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
1691 {
1692 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT));
1693 }
1694
1695 /*!
1696 * @brief Check if PLL is enabled
1697 *
1698 * @param base CCM_ANALOG base pointer.
1699 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1700 * @return PLL bypass status.
1701 * - true: The PLL is enabled.
1702 * - false: The PLL is not enabled.
1703 */
CLOCK_IsPllEnabled(CCM_ANALOG_Type * base,clock_pll_t pll)1704 static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll)
1705 {
1706 return ((CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll))) != 0U);
1707 }
1708
1709 /*!
1710 * @brief PLL bypass clock source setting.
1711 * Note: change the bypass clock source also change the pll reference clock source.
1712 *
1713 * @param base CCM_ANALOG base pointer.
1714 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1715 * @param src Bypass clock source, reference _clock_pll_bypass_clk_src.
1716 */
CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type * base,clock_pll_t pll,uint32_t src)1717 static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
1718 {
1719 CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src;
1720 }
1721
1722 /*!
1723 * @brief Get PLL bypass clock value, it is PLL reference clock actually.
1724 * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0
1725 * will be returned.
1726 * @param base CCM_ANALOG base pointer.
1727 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1728 * @retval bypass reference clock frequency value.
1729 */
CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type * base,clock_pll_t pll)1730 static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll)
1731 {
1732 return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >>
1733 CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ?
1734 CLOCK_GetOscFreq() :
1735 CLKPN_FREQ;
1736 }
1737
1738 /*!
1739 * @brief Initialize the ARM PLL.
1740 *
1741 * This function initialize the ARM PLL with specific settings
1742 *
1743 * @param config configuration to set to PLL.
1744 */
1745 void CLOCK_InitArmPll(const clock_arm_pll_config_t *config);
1746
1747 /*!
1748 * @brief De-initialize the ARM PLL.
1749 */
1750 void CLOCK_DeinitArmPll(void);
1751
1752 /*!
1753 * @brief Initialize the System PLL.
1754 *
1755 * This function initializes the System PLL with specific settings
1756 *
1757 * @param config Configuration to set to PLL.
1758 */
1759 void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
1760
1761 /*!
1762 * @brief De-initialize the System PLL.
1763 */
1764 void CLOCK_DeinitSysPll(void);
1765
1766 /*!
1767 * @brief Initialize the USB1 PLL.
1768 *
1769 * This function initializes the USB1 PLL with specific settings
1770 *
1771 * @param config Configuration to set to PLL.
1772 */
1773 void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config);
1774
1775 /*!
1776 * @brief Deinitialize the USB1 PLL.
1777 */
1778 void CLOCK_DeinitUsb1Pll(void);
1779
1780 /*!
1781 * @brief Initialize the USB2 PLL.
1782 *
1783 * This function initializes the USB2 PLL with specific settings
1784 *
1785 * @param config Configuration to set to PLL.
1786 */
1787
1788 /*!
1789 * @brief Initializes the Audio PLL.
1790 *
1791 * This function initializes the Audio PLL with specific settings
1792 *
1793 * @param config Configuration to set to PLL.
1794 */
1795 void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
1796
1797 /*!
1798 * @brief De-initialize the Audio PLL.
1799 */
1800 void CLOCK_DeinitAudioPll(void);
1801
1802 /*!
1803 * @brief Initialize the video PLL.
1804 *
1805 * This function configures the Video PLL with specific settings
1806 *
1807 * @param config configuration to set to PLL.
1808 */
1809 void CLOCK_InitVideoPll(const clock_video_pll_config_t *config);
1810
1811 /*!
1812 * @brief De-initialize the Video PLL.
1813 */
1814 void CLOCK_DeinitVideoPll(void);
1815 /*!
1816 * @brief Initialize the ENET PLL.
1817 *
1818 * This function initializes the ENET PLL with specific settings.
1819 *
1820 * @param config Configuration to set to PLL.
1821 */
1822 void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config);
1823
1824 /*!
1825 * @brief Deinitialize the ENET PLL.
1826 *
1827 * This function disables the ENET PLL.
1828 */
1829 void CLOCK_DeinitEnetPll(void);
1830
1831 /*!
1832 * @brief Get current PLL output frequency.
1833 *
1834 * This function get current output frequency of specific PLL
1835 *
1836 * @param pll pll name to get frequency.
1837 * @return The PLL output frequency in hertz.
1838 */
1839 uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
1840
1841 /*!
1842 * @brief Initialize the System PLL PFD.
1843 *
1844 * This function initializes the System PLL PFD. During new value setting,
1845 * the clock output is disabled to prevent glitch.
1846 *
1847 * @param pfd Which PFD clock to enable.
1848 * @param pfdFrac The PFD FRAC value.
1849 * @note It is recommended that PFD settings are kept between 12-35.
1850 */
1851 void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac);
1852
1853 /*!
1854 * @brief De-initialize the System PLL PFD.
1855 *
1856 * This function disables the System PLL PFD.
1857 *
1858 * @param pfd Which PFD clock to disable.
1859 */
1860 void CLOCK_DeinitSysPfd(clock_pfd_t pfd);
1861
1862 /*!
1863 * @brief Check if Sys PFD is enabled
1864 *
1865 * @param pfd PFD control name
1866 * @return PFD bypass status.
1867 * - true: power on.
1868 * - false: power off.
1869 */
1870 bool CLOCK_IsSysPfdEnabled(clock_pfd_t pfd);
1871
1872 /*!
1873 * @brief Initialize the USB1 PLL PFD.
1874 *
1875 * This function initializes the USB1 PLL PFD. During new value setting,
1876 * the clock output is disabled to prevent glitch.
1877 *
1878 * @param pfd Which PFD clock to enable.
1879 * @param pfdFrac The PFD FRAC value.
1880 * @note It is recommended that PFD settings are kept between 12-35.
1881 */
1882 void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac);
1883
1884 /*!
1885 * @brief De-initialize the USB1 PLL PFD.
1886 *
1887 * This function disables the USB1 PLL PFD.
1888 *
1889 * @param pfd Which PFD clock to disable.
1890 */
1891 void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd);
1892
1893 /*!
1894 * @brief Check if Usb1 PFD is enabled
1895 *
1896 * @param pfd PFD control name.
1897 * @return PFD bypass status.
1898 * - true: power on.
1899 * - false: power off.
1900 */
1901 bool CLOCK_IsUsb1PfdEnabled(clock_pfd_t pfd);
1902
1903 /*!
1904 * @brief Get current System PLL PFD output frequency.
1905 *
1906 * This function get current output frequency of specific System PLL PFD
1907 *
1908 * @param pfd pfd name to get frequency.
1909 * @return The PFD output frequency in hertz.
1910 */
1911 uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
1912
1913 /*!
1914 * @brief Get current USB1 PLL PFD output frequency.
1915 *
1916 * This function get current output frequency of specific USB1 PLL PFD
1917 *
1918 * @param pfd pfd name to get frequency.
1919 * @return The PFD output frequency in hertz.
1920 */
1921 uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd);
1922
1923 /*! @brief Enable USB HS PHY PLL clock.
1924 *
1925 * This function enables the internal 480MHz USB PHY PLL clock.
1926 *
1927 * @param src USB HS PHY PLL clock source.
1928 * @param freq The frequency specified by src.
1929 * @retval true The clock is set successfully.
1930 * @retval false The clock source is invalid to get proper USB HS clock.
1931 */
1932 bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1933
1934 /*! @brief Disable USB HS PHY PLL clock.
1935 *
1936 * This function disables USB HS PHY PLL clock.
1937 */
1938 void CLOCK_DisableUsbhs0PhyPllClock(void);
1939
1940 /* @} */
1941
1942 /*!
1943 * @name Clock Output Inferfaces
1944 * @{
1945 */
1946
1947 /*!
1948 * @brief Set the clock source and the divider of the clock output1.
1949 *
1950 * @param selection The clock source to be output, please refer to @ref clock_output1_selection_t.
1951 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1952 */
1953 void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider);
1954
1955 /*!
1956 * @brief Set the clock source and the divider of the clock output2.
1957 *
1958 * @param selection The clock source to be output, please refer to @ref clock_output2_selection_t.
1959 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1960 */
1961 void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider);
1962
1963 /*!
1964 * @brief Get the frequency of clock output1 clock signal.
1965 *
1966 * @return The frequency of clock output1 clock signal.
1967 */
1968 uint32_t CLOCK_GetClockOutCLKO1Freq(void);
1969
1970 /*!
1971 * @brief Get the frequency of clock output2 clock signal.
1972 *
1973 * @return The frequency of clock output2 clock signal.
1974 */
1975 uint32_t CLOCK_GetClockOutClkO2Freq(void);
1976
1977 /*! @} */
1978
1979 #if defined(__cplusplus)
1980 }
1981 #endif /* __cplusplus */
1982
1983 /*! @} */
1984
1985 #endif /* _FSL_CLOCK_H_ */
1986
