1 /* 2 ** ################################################################### 3 ** Version: rev. 1.1, 2019-02-20 4 ** Build: b231018 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2023 NXP 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** http: www.nxp.com 14 ** mail: support@nxp.com 15 ** 16 ** Revisions: 17 ** - rev. 0.1 (2018-11-05) 18 ** Initial version. 19 ** - rev. 1.0 (2019-01-18) 20 ** Rev.0 Header GA 21 ** - rev. 1.1 (2019-02-20) 22 ** Update register SRC_SRSR's bitfield LOCKUP_SYSRESETREQ to LOCKUP. 23 ** 24 ** ################################################################### 25 */ 26 27 #ifndef _MIMXRT1015_FEATURES_H_ 28 #define _MIMXRT1015_FEATURES_H_ 29 30 /* SOC module features */ 31 32 /* @brief ADC availability on the SoC. */ 33 #define FSL_FEATURE_SOC_ADC_COUNT (1) 34 /* @brief AIPSTZ availability on the SoC. */ 35 #define FSL_FEATURE_SOC_AIPSTZ_COUNT (4) 36 /* @brief AOI availability on the SoC. */ 37 #define FSL_FEATURE_SOC_AOI_COUNT (1) 38 /* @brief CCM availability on the SoC. */ 39 #define FSL_FEATURE_SOC_CCM_COUNT (1) 40 /* @brief CCM_ANALOG availability on the SoC. */ 41 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) 42 /* @brief DCDC availability on the SoC. */ 43 #define FSL_FEATURE_SOC_DCDC_COUNT (1) 44 /* @brief DCP availability on the SoC. */ 45 #define FSL_FEATURE_SOC_DCP_COUNT (1) 46 /* @brief DMAMUX availability on the SoC. */ 47 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 48 /* @brief EDMA availability on the SoC. */ 49 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 50 /* @brief ENC availability on the SoC. */ 51 #define FSL_FEATURE_SOC_ENC_COUNT (1) 52 /* @brief EWM availability on the SoC. */ 53 #define FSL_FEATURE_SOC_EWM_COUNT (1) 54 /* @brief FLEXIO availability on the SoC. */ 55 #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) 56 /* @brief FLEXRAM availability on the SoC. */ 57 #define FSL_FEATURE_SOC_FLEXRAM_COUNT (1) 58 /* @brief FLEXSPI availability on the SoC. */ 59 #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1) 60 /* @brief GPC availability on the SoC. */ 61 #define FSL_FEATURE_SOC_GPC_COUNT (1) 62 /* @brief GPT availability on the SoC. */ 63 #define FSL_FEATURE_SOC_GPT_COUNT (2) 64 /* @brief I2S availability on the SoC. */ 65 #define FSL_FEATURE_SOC_I2S_COUNT (3) 66 /* @brief IGPIO availability on the SoC. */ 67 #define FSL_FEATURE_SOC_IGPIO_COUNT (4) 68 /* @brief IOMUXC availability on the SoC. */ 69 #define FSL_FEATURE_SOC_IOMUXC_COUNT (1) 70 /* @brief IOMUXC_GPR availability on the SoC. */ 71 #define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) 72 /* @brief IOMUXC_SNVS availability on the SoC. */ 73 #define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1) 74 /* @brief KPP availability on the SoC. */ 75 #define FSL_FEATURE_SOC_KPP_COUNT (1) 76 /* @brief LPI2C availability on the SoC. */ 77 #define FSL_FEATURE_SOC_LPI2C_COUNT (2) 78 /* @brief LPSPI availability on the SoC. */ 79 #define FSL_FEATURE_SOC_LPSPI_COUNT (2) 80 /* @brief LPUART availability on the SoC. */ 81 #define FSL_FEATURE_SOC_LPUART_COUNT (4) 82 /* @brief MPU availability on the SoC. */ 83 #define FSL_FEATURE_SOC_MPU_COUNT (1) 84 /* @brief OCOTP availability on the SoC. */ 85 #define FSL_FEATURE_SOC_OCOTP_COUNT (1) 86 /* @brief PIT availability on the SoC. */ 87 #define FSL_FEATURE_SOC_PIT_COUNT (1) 88 /* @brief PMU availability on the SoC. */ 89 #define FSL_FEATURE_SOC_PMU_COUNT (1) 90 /* @brief PWM availability on the SoC. */ 91 #define FSL_FEATURE_SOC_PWM_COUNT (1) 92 /* @brief SNVS availability on the SoC. */ 93 #define FSL_FEATURE_SOC_SNVS_COUNT (1) 94 /* @brief SPDIF availability on the SoC. */ 95 #define FSL_FEATURE_SOC_SPDIF_COUNT (1) 96 /* @brief SRC availability on the SoC. */ 97 #define FSL_FEATURE_SOC_SRC_COUNT (1) 98 /* @brief TEMPMON availability on the SoC. */ 99 #define FSL_FEATURE_SOC_TEMPMON_COUNT (1) 100 /* @brief TMR availability on the SoC. */ 101 #define FSL_FEATURE_SOC_TMR_COUNT (1) 102 /* @brief TRNG availability on the SoC. */ 103 #define FSL_FEATURE_SOC_TRNG_COUNT (1) 104 /* @brief USBHS availability on the SoC. */ 105 #define FSL_FEATURE_SOC_USBHS_COUNT (1) 106 /* @brief USBNC availability on the SoC. */ 107 #define FSL_FEATURE_SOC_USBNC_COUNT (1) 108 /* @brief USBPHY availability on the SoC. */ 109 #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 110 /* @brief USB_ANALOG availability on the SoC. */ 111 #define FSL_FEATURE_SOC_USB_ANALOG_COUNT (1) 112 /* @brief WDOG availability on the SoC. */ 113 #define FSL_FEATURE_SOC_WDOG_COUNT (2) 114 /* @brief XBARA availability on the SoC. */ 115 #define FSL_FEATURE_SOC_XBARA_COUNT (1) 116 /* @brief XBARB availability on the SoC. */ 117 #define FSL_FEATURE_SOC_XBARB_COUNT (1) 118 /* @brief XTALOSC24M availability on the SoC. */ 119 #define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1) 120 /* @brief ROM API Availability */ 121 #define FSL_FEATURE_BOOT_ROM_HAS_ROMAPI (1) 122 123 /* ADC module features */ 124 125 /* @brief Remove Hardware Trigger feature. */ 126 #define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0) 127 /* @brief Remove ALT Clock selection feature. */ 128 #define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1) 129 /* @brief Conversion control count (related to number of registers HCn and Rn). */ 130 #define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (8) 131 132 /* ADC_ETC module features */ 133 134 /* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */ 135 #define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1) 136 /* @brief Has TRIGm_CHAIN_a_b IEn_EN. */ 137 #define FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN (0) 138 /* @brief Has no TSC0 trigger related bitfields (bit field CTRL[EXT0_TRIG_ENABLE], CTRL[EXT0_TRIG_PRIORITY]). */ 139 #define FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG (1) 140 /* @brief Has no TSC1 trigger related bitfields (bit field CTRL[EXT1_TRIG_ENABLE], CTRL[EXT1_TRIG_PRIORITY]). */ 141 #define FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG (1) 142 143 /* AOI module features */ 144 145 /* @brief Maximum value of input mux. */ 146 #define FSL_FEATURE_AOI_MODULE_INPUTS (4) 147 /* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ 148 #define FSL_FEATURE_AOI_EVENT_COUNT (4) 149 150 /* CCM module features */ 151 152 /* @brief Is affected by errata with ID 50235 (Incorrect clock setting for CAN affects by LPUART clock gate). */ 153 #define FSL_FEATURE_CCM_HAS_ERRATA_50235 (0) 154 155 /* DCDC module features */ 156 157 /* @brief Has CTRL register (register CTRL0/1). */ 158 #define FSL_FEATURE_DCDC_HAS_CTRL_REG (0) 159 /* @brief DCDC VDD output count. */ 160 #define FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT (1) 161 /* @brief Has no current alert function (register bit field REG0[CURRENT_ALERT_RESET]). */ 162 #define FSL_FEATURE_DCDC_HAS_NO_CURRENT_ALERT_FUNC (0) 163 /* @brief Has switching converter differential mode (register bit field REG1[LOOPCTRL_EN_DF_HYST]). */ 164 #define FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE (0) 165 /* @brief Has register bit field REG0[REG_DCDC_IN_DET]. */ 166 #define FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET (0) 167 /* @brief Has no register bit field REG0[EN_LP_OVERLOAD_SNS]. */ 168 #define FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS (0) 169 /* @brief Has register bit field REG3[REG_FBK_SEL]). */ 170 #define FSL_FEATURE_DCDC_HAS_REG3_FBK_SEL (0) 171 172 /* EDMA module features */ 173 174 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 175 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) 176 /* @brief Total number of DMA channels on all modules. */ 177 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32) 178 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 179 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 180 /* @brief Has DMA_Error interrupt vector. */ 181 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 182 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 183 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) 184 /* @brief Channel IRQ entry shared offset. */ 185 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16) 186 /* @brief If 8 bytes transfer supported. */ 187 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) 188 /* @brief If 16 bytes transfer supported. */ 189 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0) 190 /* @brief If 32 bytes transfer supported. */ 191 #define FSL_FEATURE_EDMA_SUPPORT_32_BYTES_TRANSFER (1) 192 193 /* DMAMUX module features */ 194 195 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 196 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) 197 /* @brief Total number of DMA channels on all modules. */ 198 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (32) 199 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 200 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 201 /* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */ 202 #define FSL_FEATURE_DMAMUX_HAS_A_ON (1) 203 /* @brief Register CHCFGn width. */ 204 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (32) 205 206 /* ENC module features */ 207 208 /* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */ 209 #define FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT (1) 210 /* @brief Has register CTRL3. */ 211 #define FSL_FEATURE_ENC_HAS_CTRL3 (0) 212 /* @brief Has register LASTEDGE or LASTEDGEH. */ 213 #define FSL_FEATURE_ENC_HAS_LASTEDGE (0) 214 /* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ 215 #define FSL_FEATURE_ENC_HAS_POSDPER (0) 216 /* @brief Has bitfiled FILT[FILT_PRSC]. */ 217 #define FSL_FEATURE_ENC_HAS_FILT_PRSC (1) 218 219 /* EWM module features */ 220 221 /* @brief Has clock select (register CLKCTRL). */ 222 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) 223 /* @brief Has clock prescaler (register CLKPRESCALER). */ 224 #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 225 226 /* FLEXIO module features */ 227 228 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ 229 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) 230 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ 231 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) 232 /* @brief Has pin input output related registers */ 233 #define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (0) 234 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ 235 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) 236 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ 237 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) 238 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ 239 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) 240 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 241 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) 242 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 243 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) 244 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ 245 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) 246 /* @brief Reset value of the FLEXIO_VERID register */ 247 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) 248 /* @brief Reset value of the FLEXIO_PARAM register */ 249 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200808) 250 /* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ 251 #define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (2) 252 /* @brief Flexio DMA request base channel */ 253 #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) 254 255 /* FLEXRAM module features */ 256 257 /* @brief Bank size */ 258 #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768) 259 /* @brief Total Bank numbers */ 260 #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (4) 261 /* @brief Has FLEXRAM_MAGIC_ADDR. */ 262 #define FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR (0) 263 /* @brief If FLEXRAM has ECC function. */ 264 #define FSL_FEATURE_FLEXRAM_HAS_ECC (0) 265 /* @brief If FLEXRAM has ECC Error Injection function. */ 266 #define FSL_FEATURE_FLEXRAM_HAS_ECC_ERROR_INJECTION (0) 267 268 /* FLEXSPI module features */ 269 270 /* @brief FlexSPI AHB buffer count */ 271 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4) 272 /* @brief FlexSPI has no data learn. */ 273 #define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1) 274 /* @brief There is AHBBUSERROREN bit in INTEN register. */ 275 #define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0) 276 /* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ 277 #define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (1) 278 /* @brief FLEXSPI has no IP parallel mode. */ 279 #define FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE (0) 280 /* @brief FLEXSPI has no AHB parallel mode. */ 281 #define FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE (0) 282 /* @brief FLEXSPI support address shift. */ 283 #define FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT (0) 284 /* @brief FlexSPI has no MCR0 ARDFEN bit */ 285 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN (0) 286 /* @brief FlexSPI has no MCR0 ATDFEN bit */ 287 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0) 288 /* @brief FlexSPI has no STS0 DATALEARNPHASEB bit */ 289 #define FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB (1) 290 291 /* GPC module features */ 292 293 /* @brief Has DVFS0 Change Request. */ 294 #define FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR (0) 295 /* @brief Has GPC interrupt/event masking. */ 296 #define FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM (0) 297 /* @brief Has L2 cache power control. */ 298 #define FSL_FEATURE_GPC_HAS_CNTR_L2PGE (0) 299 /* @brief Has FLEXRAM PDRAM0(bank1-7) power control. */ 300 #define FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE (1) 301 /* @brief Has VADC power control. */ 302 #define FSL_FEATURE_GPC_HAS_CNTR_VADC (0) 303 /* @brief Has Display power control. */ 304 #define FSL_FEATURE_GPC_HAS_CNTR_DISPLAY (0) 305 /* @brief Supports IRQ 0-31. */ 306 #define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1) 307 308 /* IGPIO module features */ 309 310 /* @brief Has data register set DR_SET. */ 311 #define FSL_FEATURE_IGPIO_HAS_DR_SET (1) 312 /* @brief Has data register clear DR_CLEAR. */ 313 #define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1) 314 /* @brief Has data register toggle DR_TOGGLE. */ 315 #define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1) 316 317 /* LPI2C module features */ 318 319 /* @brief Has separate DMA RX and TX requests. */ 320 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) 321 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 322 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) 323 324 /* LPSPI module features */ 325 326 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 327 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16) 328 /* @brief Has separate DMA RX and TX requests. */ 329 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 330 /* @brief Has CCR1 (related to existence of registers CCR1). */ 331 #define FSL_FEATURE_LPSPI_HAS_CCR1 (0) 332 /* @brief Has no PCSCFG bit in CFGR1 register */ 333 #define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) 334 /* @brief Has no WIDTH bits in TCR register */ 335 #define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) 336 337 /* LPUART module features */ 338 339 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 340 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 341 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 342 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 343 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 344 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 345 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 346 #define FSL_FEATURE_LPUART_HAS_FIFO (1) 347 /* @brief Has 32-bit register MODIR */ 348 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 349 /* @brief Hardware flow control (RTS, CTS) is supported. */ 350 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 351 /* @brief Infrared (modulation) is supported. */ 352 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 353 /* @brief 2 bits long stop bit is available. */ 354 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 355 /* @brief If 10-bit mode is supported. */ 356 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 357 /* @brief If 7-bit mode is supported. */ 358 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) 359 /* @brief Baud rate fine adjustment is available. */ 360 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 361 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 362 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 363 /* @brief Baud rate oversampling is available. */ 364 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 365 /* @brief Baud rate oversampling is available. */ 366 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 367 /* @brief Peripheral type. */ 368 #define FSL_FEATURE_LPUART_IS_SCI (1) 369 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 370 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) 371 /* @brief Supports two match addresses to filter incoming frames. */ 372 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 373 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 374 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 375 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 376 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 377 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 378 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 379 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 380 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 381 /* @brief Has improved smart card (ISO7816 protocol) support. */ 382 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 383 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 384 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 385 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 386 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 387 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 388 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 389 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 390 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 391 /* @brief Has separate DMA RX and TX requests. */ 392 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 393 /* @brief Has separate RX and TX interrupts. */ 394 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 395 /* @brief Has LPAURT_PARAM. */ 396 #define FSL_FEATURE_LPUART_HAS_PARAM (1) 397 /* @brief Has LPUART_VERID. */ 398 #define FSL_FEATURE_LPUART_HAS_VERID (1) 399 /* @brief Has LPUART_GLOBAL. */ 400 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) 401 /* @brief Has LPUART_PINCFG. */ 402 #define FSL_FEATURE_LPUART_HAS_PINCFG (1) 403 /* @brief Has register MODEM Control. */ 404 #define FSL_FEATURE_LPUART_HAS_MCR (0) 405 /* @brief Has register Half Duplex Control. */ 406 #define FSL_FEATURE_LPUART_HAS_HDCR (0) 407 /* @brief Has register Timeout. */ 408 #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) 409 410 /* interrupt module features */ 411 412 /* @brief Lowest interrupt request number. */ 413 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 414 /* @brief Highest interrupt request number. */ 415 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (133) 416 417 /* OCOTP module features */ 418 419 /* @brief Has timing control, (register TIMING). */ 420 #define FSL_FEATURE_OCOTP_HAS_TIMING_CTRL (1) 421 /* @brief Support lock eFuse word write lock, (CTRL[WORDLOCK]). */ 422 #define FSL_FEATURE_OCOTP_HAS_WORDLOCK (0) 423 424 /* PIT module features */ 425 426 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 427 #define FSL_FEATURE_PIT_TIMER_COUNT (4) 428 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 429 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) 430 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 431 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 432 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 433 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) 434 /* @brief Has timer enable control. */ 435 #define FSL_FEATURE_PIT_HAS_MDIS (1) 436 437 /* PWM module features */ 438 439 /* @brief If (e)FlexPWM has module A channels (outputs). */ 440 #define FSL_FEATURE_PWM_HAS_CHANNELA (1) 441 /* @brief If (e)FlexPWM has module B channels (outputs). */ 442 #define FSL_FEATURE_PWM_HAS_CHANNELB (1) 443 /* @brief If (e)FlexPWM has module X channels (outputs). */ 444 #define FSL_FEATURE_PWM_HAS_CHANNELX (1) 445 /* @brief If (e)FlexPWM has fractional feature. */ 446 #define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) 447 /* @brief If (e)FlexPWM has mux trigger source select bit field. */ 448 #define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) 449 /* @brief Number of submodules in each (e)FlexPWM module. */ 450 #define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) 451 /* @brief Number of fault channel in each (e)FlexPWM module. */ 452 #define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) 453 /* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ 454 #define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) 455 /* @brief If (e)FlexPWM has phase delay feature. */ 456 #define FSL_FEATURE_PWM_HAS_PHASE_DELAY (0) 457 /* @brief If (e)FlexPWM has input filter capture feature. */ 458 #define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (0) 459 /* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ 460 #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1) 461 /* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ 462 #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) 463 /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ 464 #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) 465 466 /* RTWDOG module features */ 467 468 /* @brief Watchdog is available. */ 469 #define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1) 470 /* @brief RTWDOG_CNT can be 32-bit written. */ 471 #define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1) 472 473 /* SAI module features */ 474 475 /* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ 476 #define FSL_FEATURE_SAI_HAS_FIFO (1) 477 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 478 #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (32) 479 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 480 #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ 481 (((x) == SAI1) ? (4) : \ 482 (((x) == SAI2) ? (1) : \ 483 (((x) == SAI3) ? (1) : (-1)))) 484 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 485 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) 486 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 487 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) 488 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 489 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) 490 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 491 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) 492 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 493 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) 494 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 495 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 496 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 497 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) 498 /* @brief Interrupt source number */ 499 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) 500 /* @brief Has register of MCR. */ 501 #define FSL_FEATURE_SAI_HAS_MCR (0) 502 /* @brief Has bit field MICS of the MCR register. */ 503 #define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) 504 /* @brief Has register of MDR */ 505 #define FSL_FEATURE_SAI_HAS_MDR (0) 506 /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ 507 #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) 508 /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ 509 #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) 510 /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ 511 #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) 512 /* @brief Support synchronous with another SAI. */ 513 #define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (0) 514 515 /* SNVS module features */ 516 517 /* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ 518 #define FSL_FEATURE_SNVS_HAS_SRTC (1) 519 /* @brief Has Passive Tamper Filter (regitser LPTGFCR). */ 520 #define FSL_FEATURE_SNVS_PASSIVE_TAMPER_FILTER (0) 521 /* @brief Has Active Tampers (regitser LPATCTLR, LPATCLKR, LPATRCnR). */ 522 #define FSL_FEATURE_SNVS_HAS_ACTIVE_TAMPERS (0) 523 /* @brief Number of TAMPER. */ 524 #define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (0) 525 526 /* SRC module features */ 527 528 /* @brief There is MASK_WDOG3_RST bit in SCR register. */ 529 #define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1) 530 /* @brief There is MIX_RST_STRCH bit in SCR register. */ 531 #define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (0) 532 /* @brief There is DBG_RST_MSK_PG bit in SCR register. */ 533 #define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1) 534 /* @brief There is WDOG3_RST_OPTN bit in SCR register. */ 535 #define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (0) 536 /* @brief There is CORES_DBG_RST bit in SCR register. */ 537 #define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (0) 538 /* @brief There is MTSR bit in SCR register. */ 539 #define FSL_FEATURE_SRC_HAS_SCR_MTSR (0) 540 /* @brief There is CORE0_DBG_RST bit in SCR register. */ 541 #define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1) 542 /* @brief There is CORE0_RST bit in SCR register. */ 543 #define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1) 544 /* @brief There is LOCKUP_RST bit in SCR register. */ 545 #define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (1) 546 /* @brief There is SWRC bit in SCR register. */ 547 #define FSL_FEATURE_SRC_HAS_SCR_SWRC (0) 548 /* @brief There is EIM_RST bit in SCR register. */ 549 #define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (0) 550 /* @brief There is LUEN bit in SCR register. */ 551 #define FSL_FEATURE_SRC_HAS_SCR_LUEN (0) 552 /* @brief There is no WRBC bit in SCR register. */ 553 #define FSL_FEATURE_SRC_HAS_NO_SCR_WRBC (1) 554 /* @brief There is no WRE bit in SCR register. */ 555 #define FSL_FEATURE_SRC_HAS_NO_SCR_WRE (1) 556 /* @brief There is SISR register. */ 557 #define FSL_FEATURE_SRC_HAS_SISR (0) 558 /* @brief There is RESET_OUT bit in SRSR register. */ 559 #define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0) 560 /* @brief There is WDOG3_RST_B bit in SRSR register. */ 561 #define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1) 562 /* @brief There is JTAG_SW_RST bit in SRSR register. */ 563 #define FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST (1) 564 /* @brief There is SW bit in SRSR register. */ 565 #define FSL_FEATURE_SRC_HAS_SRSR_SW (0) 566 /* @brief There is IPP_USER_RESET_B bit in SRSR register. */ 567 #define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1) 568 /* @brief There is SNVS bit in SRSR register. */ 569 #define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0) 570 /* @brief There is CSU_RESET_B bit in SRSR register. */ 571 #define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1) 572 /* @brief There is LOCKUP bit in SRSR register. */ 573 #define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (1) 574 /* @brief There is LOCKUP_SYSRESETREQ bit in SRSR register. */ 575 #define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ (0) 576 /* @brief There is POR bit in SRSR register. */ 577 #define FSL_FEATURE_SRC_HAS_SRSR_POR (0) 578 /* @brief There is IPP_RESET_B bit in SRSR register. */ 579 #define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1) 580 /* @brief There is no WBI bit in SCR register. */ 581 #define FSL_FEATURE_SRC_HAS_NO_SRSR_WBI (1) 582 583 /* SCB module features */ 584 585 /* @brief L1 ICACHE line size in byte. */ 586 #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) 587 /* @brief L1 DCACHE line size in byte. */ 588 #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) 589 590 /* TRNG module features */ 591 592 /* @brief TRNG has no TRNG_ACC bitfield. */ 593 #define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) 594 595 /* USBHS module features */ 596 597 /* @brief EHCI module instance count */ 598 #define FSL_FEATURE_USBHS_EHCI_COUNT (1) 599 /* @brief Number of endpoints supported */ 600 #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) 601 602 /* USBPHY module features */ 603 604 /* @brief USBPHY contain DCD analog module */ 605 #define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) 606 /* @brief USBPHY has register TRIM_OVERRIDE_EN */ 607 #define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (0) 608 /* @brief USBPHY is 28FDSOI */ 609 #define FSL_FEATURE_USBPHY_28FDSOI (0) 610 611 /* XBARA module features */ 612 613 /* @brief Number of interrupt requests. */ 614 #define FSL_FEATURE_XBARA_INTERRUPT_COUNT (4) 615 616 #endif /* _MIMXRT1015_FEATURES_H_ */ 617 618
