1 /*
2 * Copyright 2020, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup clock */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @brief Configure whether driver controls clock
23 *
24 * When set to 0, peripheral drivers will enable clock in initialize function
25 * and disable clock in de-initialize function. When set to 1, peripheral
26 * driver will not control the clock, application could control the clock out of
27 * the driver.
28 *
29 * @note All drivers share this feature switcher. If it is set to 1, application
30 * should handle clock enable and disable for all drivers.
31 */
32 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
33 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
34 #endif
35
36 /*! @name Driver version */
37 /*@{*/
38 /*! @brief CLOCK driver version 2.0.5. */
39 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
40 /*@}*/
41
42 /* Definition for delay API in clock driver, users can redefine it to the real application. */
43 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
44 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (160000000UL)
45 #endif
46
47 /*!
48 * @brief CGC (A/S)PLLPFD[PFDx] value.
49 */
50 #define CGC_PLLPFD_PFD_VAL(pfdClkout, fracValue) ((uint32_t)((uint32_t)(fracValue) << (uint32_t)(pfdClkout)))
51 /*!
52 * @brief CGC (A/S)PLLPFD[PFD] mask.
53 */
54 #define CGC_PLLPFD_PFD_MASK(pfdClkout) ((uint32_t)((uint32_t)(CGC_PLL0PFDCFG_PFD0_MASK) << (uint32_t)(pfdClkout)))
55 /*!
56 * @brief CGC (A/S)PLLPFD[PFDx_VALID] mask.
57 */
58 #define CGC_PLLPFD_PFD_VALID_MASK(pfdClkout) \
59 ((uint32_t)((uint32_t)CGC_PLL0PFDCFG_PFD0_VALID_MASK << (uint32_t)(pfdClkout)))
60 /*!
61 * @brief CGC (A/S)PLLPFD[PFDx_CLKGATE] mask.
62 */
63 #define CGC_PLLPFD_PFD_CLKGATE_MASK(pfdClkout) \
64 ((uint32_t)((uint32_t)CGC_PLL0PFDCFG_PFD0_CLKGATE_MASK << (uint32_t)(pfdClkout)))
65
66 /*! @brief External XTAL (SYSOSC) clock frequency.
67 *
68 * The XTAL (SYSOSC) clock frequency in Hz. When the clock is set up, use the
69 * function CLOCK_SetXtalFreq to set the value in the clock driver. For example,
70 * if XTAL is 24 MHz:
71 * @code
72 * CLOCK_InitSysOsc(...);
73 * CLOCK_SetXtalFreq(24000000);
74 * @endcode
75 *
76 * This is important for the multicore platforms where only one core needs to set up the
77 * OSC/SYSOSC using CLOCK_InitSysOsc. All other cores need to call the CLOCK_SetXtalFreq
78 * to get a valid clock frequency.
79 */
80 extern volatile uint32_t g_xtal0Freq;
81
82 /*! @brief External XTAL32/EXTAL32 clock frequency.
83 *
84 * The XTAL32/EXTAL32 clock frequency in Hz. When the clock is set up, use the
85 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
86 *
87 * This is important for the multicore platforms where only one core needs to set up
88 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
89 * to get a valid clock frequency.
90 */
91 extern volatile uint32_t g_xtal32Freq;
92
93 /*! @brief External LVDS pad clock frequency.
94 *
95 * The LVDS pad clock frequency in Hz. When the clock is set up, use the
96 * function CLOCK_SetLvdsFreq to set the value in the clock driver.
97 *
98 */
99 extern volatile uint32_t g_lvdsFreq;
100
101 /*! @brief External MCLK pad clock frequency.
102 *
103 * The MCLK pad clock frequency in Hz. When the clock is set up, use the
104 * function CLOCK_SetMclkFreq to set the value in the clock driver.
105 *
106 */
107 extern volatile uint32_t g_mclkFreq[4];
108
109 /*! @brief External RX_BCLK pad clock frequency.
110 *
111 * The RX_BCLK pad clock frequency in Hz. When the clock is set up, use the
112 * function CLOCK_SetRxBclkFreq to set the value in the clock driver.
113 *
114 */
115 extern volatile uint32_t g_rxBclkFreq[8];
116
117 /*! @brief External TX_BCLK pad clock frequency.
118 *
119 * The TX_BCLK pad clock frequency in Hz. When the clock is set up, use the
120 * function CLOCK_SetTxBclkFreq to set the value in the clock driver.
121 *
122 */
123 extern volatile uint32_t g_txBclkFreq[8];
124
125 /*! @brief Recovered SPDIF_RX clock frequency.
126 *
127 * The SPDIF_RX clock frequency in Hz. When the clock is sampled, use the
128 * function CLOCK_SetSpdifRxFreq to set the value in the clock driver.
129 *
130 */
131 extern volatile uint32_t g_spdifRxFreq;
132
133 /*!
134 * @brief Re-define PCC register masks and bitfield operations to unify
135 * the different namings in the soc header file.
136 */
137 #define PCC_CLKCFG_PCD_MASK (0x7U)
138 #define PCC_CLKCFG_PCD_SHIFT (0U)
139 #define PCC_CLKCFG_PCD(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCD_SHIFT)) & PCC_CLKCFG_PCD_MASK)
140 #define PCC_CLKCFG_FRAC_MASK (0x8U)
141 #define PCC_CLKCFG_FRAC_SHIFT (3U)
142 #define PCC_CLKCFG_FRAC(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_FRAC_SHIFT)) & PCC_CLKCFG_FRAC_MASK)
143 #define PCC_CLKCFG_PCS_MASK (0x7000000U)
144 #define PCC_CLKCFG_PCS_SHIFT (24U)
145 #define PCC_CLKCFG_PCS(x) (((uint32_t)(((uint32_t)(x)) << PCC_CLKCFG_PCS_SHIFT)) & PCC_CLKCFG_PCS_MASK)
146 #define PCC_CLKCFG_INUSE_MASK (0x20000000U)
147 #define PCC_CLKCFG_CGC_MASK (0x40000000U)
148 #define PCC_CLKCFG_PR_MASK (0x80000000U)
149
150 /*! @brief Bitfield values for general PCC registers. */
151 #define PCC_PCS_VAL(reg) (((reg)&PCC_CLKCFG_PCS_MASK) >> PCC_CLKCFG_PCS_SHIFT)
152 #define PCC_FRAC_VAL(reg) (((reg)&PCC_CLKCFG_FRAC_MASK) >> PCC_CLKCFG_FRAC_SHIFT)
153 #define PCC_PCD_VAL(reg) (((reg)&PCC_CLKCFG_PCD_MASK) >> PCC_CLKCFG_PCD_SHIFT)
154
155 /*!
156 * @brief Clock source index macros for clock_ip_src_t.
157 */
158 #define CLOCK_IP_SOURCE_PCC_INDEX(idx) ((idx) << 8U)
159 #define CLOCK_IP_SOURCE_NON_PCC_INDEX(idx) ((idx) << 16U)
160 #define CLOCK_IP_SOURCE_PCC_INDEX_VAL(src) ((uint32_t)(src) >> 8U)
161 #define CLOCK_IP_SOURCE_NON_PCC_INDEX_VAL(src) ((uint32_t)(src) >> 16U)
162
163 /*!
164 * @brief Define PCC bit available mask for clock_ip_name_t.
165 */
166 #define PCC_PCS_AVAIL_MASK (0x2U)
167 #define PCC_PCD_FRAC_AVAIL_MASK (0x1U)
168 /*!
169 * @brief Define Non-PCC register flag mask for clock_ip_name_t.
170 */
171 #define IP_NAME_NON_PCC_FLAG_MASK ((uint32_t)1U << 30)
172
173 /*!
174 * @brief Define PCC register content for clock_ip_name_t.
175 */
176 #define PCC_REG(name) (*(volatile uint32_t *)((uint32_t)(name) & ~(PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK)))
177
178 /*! @brief Clock ip name array for RGPIO2P. */
179 #define RGPIO_CLOCKS \
180 { \
181 kCLOCK_RgpioA, kCLOCK_RgpioB, kCLOCK_RgpioC, kCLOCK_RgpioD, kCLOCK_RgpioE, kCLOCK_RgpioF \
182 }
183
184 /*! @brief Clock ip name array for SAI. */
185 #define SAI_CLOCKS \
186 { \
187 kCLOCK_Sai0, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4, kCLOCK_Sai5, kCLOCK_Sai6, kCLOCK_Sai7 \
188 }
189
190 /*! @brief Clock ip name array for PCTL. */
191 #define PCTL_CLOCKS \
192 { \
193 kCLOCK_PctlA, kCLOCK_PctlB, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_PctlE, kCLOCK_PctlF \
194 }
195
196 /*! @brief Clock ip name array for LPI2C. */
197 #define LPI2C_CLOCKS \
198 { \
199 kCLOCK_Lpi2c0, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4, kCLOCK_Lpi2c5, kCLOCK_Lpi2c6, \
200 kCLOCK_Lpi2c7 \
201 }
202
203 /*! @brief Clock ip name array for I3C. */
204 #define I3C_CLOCKS \
205 { \
206 kCLOCK_I3c0, kCLOCK_I3c1, kCLOCK_I3c2 \
207 }
208
209 /*! @brief Clock ip name array for FLEXIO. */
210 #define FLEXIO_CLOCKS \
211 { \
212 kCLOCK_Flexio0, kCLOCK_Flexio1 \
213 }
214
215 /*! @brief Clock ip name array for FLEXCAN. */
216 #define FLEXCAN_CLOCKS \
217 { \
218 kCLOCK_Flexcan \
219 }
220
221 /*! @brief Clock ip name array for PDM. */
222 #define PDM_CLOCKS \
223 { \
224 kCLOCK_Micfil \
225 }
226
227 /*! @brief Clock ip name array for LCDIF/DCNANO. */
228 #define LCDIF_CLOCKS \
229 { \
230 kCLOCK_Dcnano \
231 }
232
233 /*! @brief Clock ip name array for MIPI DSI. */
234 #define MIPI_DSI_HOST_CLOCKS \
235 { \
236 kCLOCK_Dsi \
237 }
238
239 /*! @brief Clock ip name array for EDMA. */
240 #define EDMA_CLOCKS \
241 { \
242 kCLOCK_Dma0, kCLOCK_Dma1, kCLOCK_Dma2 \
243 }
244
245 /*! @brief Clock ip name array for EDMA Channels. */
246 #define EDMA_CHAN_CLOCKS \
247 { \
248 kCLOCK_Dma0Ch0, kCLOCK_Dma1Ch0, kCLOCK_Dma2Ch0 \
249 }
250
251 /*! @brief Clock ip name array for LPUART. */
252 #define LPUART_CLOCKS \
253 { \
254 kCLOCK_Lpuart0, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
255 kCLOCK_Lpuart6, kCLOCK_Lpuart7 \
256 }
257
258 /*! @brief Clock ip name array for DAC. */
259 #define DAC_CLOCKS \
260 { \
261 kCLOCK_Dac0, kCLOCK_Dac1 \
262 }
263
264 /*! @brief Clock ip name array for LPTMR. */
265 #define LPTMR_CLOCKS \
266 { \
267 kCLOCK_Lptmr0, kCLOCK_Lptmr1 \
268 }
269
270 /*! @brief Clock ip name array for LPADC. */
271 #define LPADC_CLOCKS \
272 { \
273 kCLOCK_Adc0, kCLOCK_Adc1 \
274 }
275
276 /*! @brief Clock ip name array for LPSPI. */
277 #define LPSPI_CLOCKS \
278 { \
279 kCLOCK_Lpspi0, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4, kCLOCK_Lpspi5 \
280 }
281
282 /*! @brief Clock ip name array for TPM. */
283 #define TPM_CLOCKS \
284 { \
285 kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2, kCLOCK_Tpm3, kCLOCK_Tpm4, kCLOCK_Tpm5, kCLOCK_Tpm6, kCLOCK_Tpm7, \
286 kCLOCK_Tpm8 \
287 }
288
289 /*! @brief Clock ip name array for LPIT. */
290 #define LPIT_CLOCKS \
291 { \
292 kCLOCK_Lpit0, kCLOCK_Lpit1 \
293 }
294
295 /*! @brief Clock ip name array for CMP. */
296 #define CMP_CLOCKS \
297 { \
298 kCLOCK_Cmp0, kCLOCK_Cmp1 \
299 }
300
301 /*! @brief Clock ip name array for MU. */
302 #if defined(MIMX8UD7_cm33_SERIES)
303 #define MU_CLOCKS \
304 { \
305 kCLOCK_Mu0A, kCLOCK_Mu1A, kCLOCK_Mu2A \
306 }
307 #elif defined(MIMX8UD7_dsp0_SERIES)
308 #define MU_CLOCKS \
309 { \
310 kCLOCK_Mu1B \
311 }
312 #elif defined(MIMX8UD7_dsp1_SERIES)
313 #define MU_CLOCKS \
314 { \
315 kCLOCK_Mu2B, kCLOCK_Mu3B \
316 }
317 #elif defined(MIMX8UD5_cm33_SERIES)
318 #define MU_CLOCKS \
319 { \
320 kCLOCK_Mu0A, kCLOCK_Mu1A, kCLOCK_Mu2A \
321 }
322 #elif defined(MIMX8UD5_dsp0_SERIES)
323 #define MU_CLOCKS \
324 { \
325 kCLOCK_Mu1B \
326 }
327 #elif defined(MIMX8UD5_dsp1_SERIES)
328 #define MU_CLOCKS \
329 { \
330 kCLOCK_Mu2B, kCLOCK_Mu3B \
331 }
332 #elif defined(MIMX8UD3_cm33_SERIES)
333 #define MU_CLOCKS \
334 { \
335 kCLOCK_Mu0A, kCLOCK_Mu1A, kCLOCK_Mu2A \
336 }
337 #elif defined(MIMX8UD3_dsp0_SERIES)
338 #define MU_CLOCKS \
339 { \
340 kCLOCK_Mu1B \
341 }
342 #elif defined(MIMX8UD3_dsp1_SERIES)
343 #define MU_CLOCKS \
344 { \
345 kCLOCK_Mu2B, kCLOCK_Mu3B \
346 }
347 #elif defined(MIMX8US5_cm33_SERIES)
348 #define MU_CLOCKS \
349 { \
350 kCLOCK_Mu0A, kCLOCK_Mu1A, kCLOCK_Mu2A \
351 }
352 #elif defined(MIMX8US5_dsp0_SERIES)
353 #define MU_CLOCKS \
354 { \
355 kCLOCK_Mu1B \
356 }
357 #elif defined(MIMX8US5_dsp1_SERIES)
358 #define MU_CLOCKS \
359 { \
360 kCLOCK_Mu2B, kCLOCK_Mu3B \
361 }
362 #elif defined(MIMX8US3_cm33_SERIES)
363 #define MU_CLOCKS \
364 { \
365 kCLOCK_Mu0A, kCLOCK_Mu1A, kCLOCK_Mu2A \
366 }
367 #elif defined(MIMX8US3_dsp0_SERIES)
368 #define MU_CLOCKS \
369 { \
370 kCLOCK_Mu1B \
371 }
372 #elif defined(MIMX8US3_dsp1_SERIES)
373 #define MU_CLOCKS \
374 { \
375 kCLOCK_Mu2B, kCLOCK_Mu3B \
376 }
377 #else
378 #error "Unsupport core by the driver."
379 #endif
380
381 /*! @brief Clock ip name array for WDOG. */
382 #define WDOG_CLOCKS \
383 { \
384 kCLOCK_Wdog0, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3, kCLOCK_Wdog4, kCLOCK_Wdog5 \
385 }
386
387 /*! @brief Clock ip name array for SEMA42. */
388 #define SEMA42_CLOCKS \
389 { \
390 kCLOCK_Sema420, kCLOCK_Sema421, kCLOCK_Sema422 \
391 }
392
393 /*! @brief Clock ip name array for TPIU. */
394 #define TPIU_CLOCKS \
395 { \
396 kCLOCK_Tpiu \
397 }
398
399 /*! @brief Clock ip name array for QSPI. */
400 #define FLEXSPI_CLOCKS \
401 { \
402 kCLOCK_Flexspi0, kCLOCK_Flexspi1, kCLOCK_Flexspi2 \
403 }
404
405 /*! @brief Clock ip name array for MRT. */
406 #define MRT_CLOCKS \
407 { \
408 kCLOCK_Mrt \
409 }
410
411 /*! @brief Clock ip name array for BBNSM. */
412 #define BBNSM_CLOCKS \
413 { \
414 kCLOCK_Bbnsm \
415 }
416
417 /*! @brief Clock ip name array for PXP. */
418 #define PXP_CLOCKS \
419 { \
420 kCLOCK_Pxp \
421 }
422
423 /*! @brief Clock ip name array for EPDC. */
424 #define EPDC_CLOCKS \
425 { \
426 kCLOCK_Epdc \
427 }
428
429 /*! @brief Clock name used to get clock frequency. */
430 typedef enum _clock_name
431 {
432
433 /* ---------------------------- System layer clock -----------------------*/
434 kCLOCK_Cm33CorePlatClk, /*!< RTD : CM33 Core/Platform clock */
435 kCLOCK_Cm33BusClk, /*!< RTD : CM33 Bus clock */
436 kCLOCK_Cm33SlowClk, /*!< RTD : CM33 Slow clock */
437 kCLOCK_FusionDspCorePlatClk, /*!< RTD : FusionF1 DSP Core/Platform clock */
438 kCLOCK_FusionDspBusClk, /*!< RTD : FusionF1 DSP Bus clock */
439 kCLOCK_FusionDspSlowClk, /*!< RTD : FusionF1 DSP Slow clock */
440 kCLOCK_XbarBusClk, /*!< AD : XBAR Bus clock */
441 kCLOCK_HifiDspClk, /*!< LPAV: HIFI4 clock */
442 kCLOCK_HifiNicPlatClk, /*!< LPAV: NIC HIFI clock */
443 kCLOCK_NicLpavAxiClk, /*!< LPAV: NIC LPAV AXI clock */
444 kCLOCK_NicLpavAhbClk, /*!< LPAV: NIC LPAV AHB clock */
445 kCLOCK_NicLpavBusClk, /*!< LPAV: LPAV Bus clock */
446 kCLOCK_DdrClk, /*!< LPAV: DDR clock */
447
448 /* ------------------------------------ CGC clock ------------------------*/
449 kCLOCK_SysOscClk, /*!< CGC system OSC clock. (SYSOSC) */
450 kCLOCK_FroClk, /*!< CGC FRO 192MHz clock. */
451 kCLOCK_LpOscClk, /*!< CGC LPOSC clock. (LPOSC) */
452 kCLOCK_RtcOscClk, /*!< CGC RTC OSC clock. (RTCOSC) */
453 kCLOCK_LvdsClk, /*!< LVDS pad input clock frequency. */
454
455 kCLOCK_RtdFroDiv1Clk, /*!< FRODIV1_CLK in RTD. */
456 kCLOCK_RtdFroDiv2Clk, /*!< FRODIV2_CLK in RTD. */
457 kCLOCK_RtdFroDiv3Clk, /*!< FRODIV3_CLK in RTD. */
458
459 kCLOCK_RtdSysOscDiv1Clk, /*!< SOSCDIV1_CLK in RTD. */
460 kCLOCK_RtdSysOscDiv2Clk, /*!< SOSCDIV2_CLK in RTD. */
461 kCLOCK_RtdSysOscDiv3Clk, /*!< SOSCDIV3_CLK in RTD. */
462
463 kCLOCK_AdFroDiv1Clk, /*!< FRODIV1_CLK in AD. */
464 kCLOCK_AdFroDiv2Clk, /*!< FRODIV2_CLK in AD. */
465 kCLOCK_AdFroDiv3Clk, /*!< FRODIV3_CLK in AD. */
466
467 kCLOCK_AdSysOscDiv1Clk, /*!< SOSCDIV1_CLK in AD. */
468 kCLOCK_AdSysOscDiv2Clk, /*!< SOSCDIV2_CLK in AD. */
469 kCLOCK_AdSysOscDiv3Clk, /*!< SOSCDIV3_CLK in AD. */
470
471 kCLOCK_LpavFroDiv1Clk, /*!< FRODIV1_CLK in LPAV. */
472 kCLOCK_LpavFroDiv2Clk, /*!< FRODIV2_CLK in LPAV. */
473 kCLOCK_LpavFroDiv3Clk, /*!< FRODIV3_CLK in LPAV. */
474
475 kCLOCK_LpavSysOscDiv1Clk, /*!< SOSCDIV1_CLK in LPAV. */
476 kCLOCK_LpavSysOscDiv2Clk, /*!< SOSCDIV2_CLK in LPAV. */
477 kCLOCK_LpavSysOscDiv3Clk, /*!< SOSCDIV3_CLK in LPAV. */
478
479 kCLOCK_Pll0Clk, /*!< CGC PLL0 clock. (PLL0CLK) */
480 kCLOCK_Pll1Clk, /*!< CGC PLL1 clock. (PLL1CLK) */
481 kCLOCK_Pll3Clk, /*!< CGC PLL3 clock. (PLL3CLK) */
482 kCLOCK_Pll4Clk, /*!< CGC PLL4 clock. (PLL4CLK) */
483
484 kCLOCK_Pll0Pfd0Clk, /*!< pll0 pfd0. */
485 kCLOCK_Pll0Pfd1Clk, /*!< pll0 pfd1. */
486 kCLOCK_Pll0Pfd2Clk, /*!< pll0 pfd2. */
487 kCLOCK_Pll0Pfd3Clk, /*!< pll0 pfd3. */
488
489 kCLOCK_Pll1Pfd0Clk, /*!< pll1 pfd0. */
490 kCLOCK_Pll1Pfd1Clk, /*!< pll1 pfd1. */
491 kCLOCK_Pll1Pfd2Clk, /*!< pll1 pfd2. */
492 kCLOCK_Pll1Pfd3Clk, /*!< pll1 pfd3. */
493
494 kCLOCK_Pll3Pfd0Clk, /*!< pll3 pfd0. */
495 kCLOCK_Pll3Pfd1Clk, /*!< pll3 pfd1. */
496 kCLOCK_Pll3Pfd2Clk, /*!< pll3 pfd2. */
497 kCLOCK_Pll3Pfd3Clk, /*!< pll3 pfd3. */
498
499 kCLOCK_Pll4Pfd0Clk, /*!< pll4 pfd0. */
500 kCLOCK_Pll4Pfd1Clk, /*!< pll4 pfd1. */
501 kCLOCK_Pll4Pfd2Clk, /*!< pll4 pfd2. */
502 kCLOCK_Pll4Pfd3Clk, /*!< pll4 pfd3. */
503
504 kCLOCK_Pll0VcoDivClk, /*!< PLL0VCODIV. */
505 kCLOCK_Pll0Pfd1DivClk, /*!< PLL0PFD1DIV. */
506 kCLOCK_Pll0Pfd2DivClk, /*!< PLL0PFD2DIV. */
507
508 kCLOCK_Pll1VcoDivClk, /*!< PLL1VCODIV. */
509 kCLOCK_Pll1Pfd1DivClk, /*!< PLL1PFD1DIV. */
510 kCLOCK_Pll1Pfd2DivClk, /*!< PLL1PFD2DIV. */
511
512 kCLOCK_Pll3VcoDivClk, /*!< PLL3VCODIV. */
513 kCLOCK_Pll3Pfd0Div1Clk, /*!< PLL3PFD0DIV1. */
514 kCLOCK_Pll3Pfd0Div2Clk, /*!< PLL3PFD0DIV2. */
515 kCLOCK_Pll3Pfd1Div1Clk, /*!< PLL3PFD1DIV1. */
516 kCLOCK_Pll3Pfd1Div2Clk, /*!< PLL3PFD1DIV2. */
517 kCLOCK_Pll3Pfd2Div1Clk, /*!< PLL3PFD2DIV1. */
518 kCLOCK_Pll3Pfd2Div2Clk, /*!< PLL3PFD2DIV2. */
519 kCLOCK_Pll3Pfd3Div1Clk, /*!< PLL3PFD3DIV1. */
520 kCLOCK_Pll3Pfd3Div2Clk, /*!< PLL3PFD3DIV2. */
521
522 kCLOCK_Pll4VcoDivClk, /*!< PLL4VCODIV. */
523 kCLOCK_Pll4Pfd0Div1Clk, /*!< PLL4PFD0DIV1. */
524 kCLOCK_Pll4Pfd0Div2Clk, /*!< PLL4PFD0DIV2. */
525 kCLOCK_Pll4Pfd1Div1Clk, /*!< PLL4PFD1DIV1. */
526 kCLOCK_Pll4Pfd1Div2Clk, /*!< PLL4PFD1DIV2. */
527 kCLOCK_Pll4Pfd2Div1Clk, /*!< PLL4PFD2DIV1. */
528 kCLOCK_Pll4Pfd2Div2Clk, /*!< PLL4PFD2DIV2. */
529 kCLOCK_Pll4Pfd3Div1Clk, /*!< PLL4PFD3DIV1. */
530 kCLOCK_Pll4Pfd3Div2Clk, /*!< PLL4PFD3DIV2. */
531 } clock_name_t;
532
533 /*!
534 * @brief Clock source for peripherals that support various clock selections.
535 */
536 typedef enum _clock_ip_src
537 {
538 kCLOCK_IpSrcNone = 0U, /*!< Clock is off. */
539
540 /* PCC0 platform PCS */
541 kCLOCK_Pcc0PlatIpSrcSysOscDiv1 =
542 CLOCK_IP_SOURCE_PCC_INDEX(0U) | 3U, /*!< PCC0, PCC1 Platform clock selection: kCLOCK_RtdSysOscDiv1Clk */
543 kCLOCK_Pcc0PlatIpSrcFroDiv1 =
544 CLOCK_IP_SOURCE_PCC_INDEX(0U) | 4U, /*!< PCC0, PCC1 Platform clock selection: kCLOCK_RtdFroDiv1Clk */
545 kCLOCK_Pcc0PlatIpSrcCm33Plat =
546 CLOCK_IP_SOURCE_PCC_INDEX(0U) | 5U, /*!< PCC0, PCC1 Platform clock selection: kCLOCK_Cm33CorePlatClk */
547 kCLOCK_Pcc0PlatIpSrcFro =
548 CLOCK_IP_SOURCE_PCC_INDEX(0U) | 6U, /*!< PCC0, PCC1 Platform clock selection: kCLOCK_FroClk */
549 kCLOCK_Pcc0PlatIpSrcPll0Pfd3 =
550 CLOCK_IP_SOURCE_PCC_INDEX(0U) | 7U, /*!< PCC0, PCC1 Platform clock selection: kCLOCK_Pll0Pfd3Clk */
551
552 /* PCC0 bus PCS */
553 kCLOCK_Pcc0BusIpSrcLpo = CLOCK_IP_SOURCE_PCC_INDEX(0U) | 1U, /*!< PCC0, PCC1 Bus clock selection: kCLOCK_LpOscClk */
554 kCLOCK_Pcc0BusIpSrcSysOscDiv2 =
555 CLOCK_IP_SOURCE_PCC_INDEX(0U) | 2U, /*!< PCC0, PCC1 Bus clock selection: kCLOCK_RtdSysOscDiv2Clk */
556 kCLOCK_Pcc0BusIpSrcFroDiv2 =
557 CLOCK_IP_SOURCE_PCC_INDEX(0U) | 3U, /*!< PCC0, PCC1 Bus clock selection: kCLOCK_RtdFroDiv2Clk */
558 kCLOCK_Pcc0BusIpSrcCm33Bus =
559 CLOCK_IP_SOURCE_PCC_INDEX(0U) | 4U, /*!< PCC0, PCC1 Bus clock selection: kCLOCK_Cm33BusClk */
560 kCLOCK_Pcc0BusIpSrcPll1Pfd1Div =
561 CLOCK_IP_SOURCE_PCC_INDEX(0U) | 5U, /*!< PCC0 Bus clock selection: kCLOCK_Pll1Pfd1DivClk */
562 kCLOCK_Pcc0BusIpSrcPll0Pfd2Div =
563 CLOCK_IP_SOURCE_PCC_INDEX(0U) | 6U, /*!< PCC0, PCC1 Bus clock selection: kCLOCK_Pll0Pfd2DivClk */
564 kCLOCK_Pcc0BusIpSrcPll0Pfd1Div =
565 CLOCK_IP_SOURCE_PCC_INDEX(0U) | 7U, /*!< PCC0, PCC1 Bus clock selection: kCLOCK_Pll0Pfd1DivClk */
566
567 /* PCC1 platform PCS */
568 kCLOCK_Pcc1PlatIpSrcSysOscDiv1 =
569 CLOCK_IP_SOURCE_PCC_INDEX(1U) | 3U, /*!< PCC0, PCC1 Platform clock selection: kCLOCK_RtdSysOscDiv1Clk */
570 kCLOCK_Pcc1PlatIpSrcFroDiv1 =
571 CLOCK_IP_SOURCE_PCC_INDEX(1U) | 4U, /*!< PCC0, PCC1 Platform clock selection: kCLOCK_RtdFroDiv1Clk */
572 kCLOCK_Pcc1PlatIpSrcCm33Plat =
573 CLOCK_IP_SOURCE_PCC_INDEX(1U) | 5U, /*!< PCC0, PCC1 Platform clock selection: kCLOCK_Cm33CorePlatClk */
574 kCLOCK_Pcc1PlatIpSrcFro =
575 CLOCK_IP_SOURCE_PCC_INDEX(1U) | 6U, /*!< PCC0, PCC1 Platform clock selection: kCLOCK_FroClk */
576 kCLOCK_Pcc1PlatIpSrcPll0Pfd3 =
577 CLOCK_IP_SOURCE_PCC_INDEX(1U) | 7U, /*!< PCC0, PCC1 Platform clock selection: kCLOCK_Pll0Pfd3Clk */
578
579 /* PCC1 bus PCS */
580 kCLOCK_Pcc1BusIpSrcLpo = CLOCK_IP_SOURCE_PCC_INDEX(1U) | 1U, /*!< PCC0, PCC1 Bus clock selection: kCLOCK_LpOscClk */
581 kCLOCK_Pcc1BusIpSrcSysOscDiv2 =
582 CLOCK_IP_SOURCE_PCC_INDEX(1U) | 2U, /*!< PCC0, PCC1 Bus clock selection: kCLOCK_RtdSysOscDiv2Clk */
583 kCLOCK_Pcc1BusIpSrcFroDiv2 =
584 CLOCK_IP_SOURCE_PCC_INDEX(1U) | 3U, /*!< PCC0, PCC1 Bus clock selection: kCLOCK_RtdFroDiv2Clk */
585 kCLOCK_Pcc1BusIpSrcCm33Bus =
586 CLOCK_IP_SOURCE_PCC_INDEX(1U) | 4U, /*!< PCC0, PCC1 Bus clock selection: kCLOCK_Cm33BusClk */
587 kCLOCK_Pcc1BusIpSrcPll1VcoDiv =
588 CLOCK_IP_SOURCE_PCC_INDEX(1U) | 5U, /*!< PCC1 Bus clock selection: kCLOCK_Pll1VcoDivClk */
589 kCLOCK_Pcc1BusIpSrcPll0Pfd2Div =
590 CLOCK_IP_SOURCE_PCC_INDEX(1U) | 6U, /*!< PCC0, PCC1 Bus clock selection: kCLOCK_Pll0Pfd2DivClk */
591 kCLOCK_Pcc1BusIpSrcPll0Pfd1Div =
592 CLOCK_IP_SOURCE_PCC_INDEX(1U) | 7U, /*!< PCC0, PCC1 Bus clock selection: kCLOCK_Pll0Pfd1DivClk */
593
594 /* PCC2 has no platform PCS, only bus PCS */
595 kCLOCK_Pcc2BusIpSrcLpo = CLOCK_IP_SOURCE_PCC_INDEX(2U) | 1U, /*!< PCC2 Bus clock selection: kCLOCK_LpOscClk */
596 kCLOCK_Pcc2BusIpSrcSysOscDiv3 =
597 CLOCK_IP_SOURCE_PCC_INDEX(2U) | 2U, /*!< PCC2 Bus clock selection: kCLOCK_RtdSysOscDiv3Clk */
598 kCLOCK_Pcc2BusIpSrcFroDiv3 =
599 CLOCK_IP_SOURCE_PCC_INDEX(2U) | 3U, /*!< PCC2 Bus clock selection: kCLOCK_RtdFroDiv3Clk */
600 kCLOCK_Pcc2BusIpSrcFusionDspBus =
601 CLOCK_IP_SOURCE_PCC_INDEX(2U) | 4U, /*!< PCC2 Bus clock selection: kCLOCK_FusionDspBusClk */
602 kCLOCK_Pcc2BusIpSrcPll1VcoDiv =
603 CLOCK_IP_SOURCE_PCC_INDEX(2U) | 5U, /*!< PCC2 Bus clock selection: kCLOCK_Pll1VcoDivClk */
604 kCLOCK_Pcc2BusIpSrcPll0Pfd2Div =
605 CLOCK_IP_SOURCE_PCC_INDEX(2U) | 6U, /*!< PCC2 Bus clock selection: kCLOCK_Pll0Pfd2DivClk */
606 kCLOCK_Pcc2BusIpSrcPll0Pfd1Div =
607 CLOCK_IP_SOURCE_PCC_INDEX(2U) | 7U, /*!< PCC2 Bus clock selection: kCLOCK_Pll0Pfd1DivClk */
608
609 /* PCC3 has no platform PCS, only bus PCS */
610 kCLOCK_Pcc3BusIpSrcLpo = CLOCK_IP_SOURCE_PCC_INDEX(3U) | 1U, /*!< PCC3 Bus clock selection: kCLOCK_LpOscClk */
611 kCLOCK_Pcc3BusIpSrcSysOscDiv2 =
612 CLOCK_IP_SOURCE_PCC_INDEX(3U) | 2U, /*!< PCC3 Bus clock selection: kCLOCK_AdSysOscDiv2Clk */
613 kCLOCK_Pcc3BusIpSrcFroDiv2 =
614 CLOCK_IP_SOURCE_PCC_INDEX(3U) | 3U, /*!< PCC3 Bus clock selection: kCLOCK_AdFroDiv2Clk */
615 kCLOCK_Pcc3BusIpSrcXbarBus = CLOCK_IP_SOURCE_PCC_INDEX(3U) | 4U, /*!< PCC3 Bus clock selection: kCLOCK_XbarBusClk */
616 kCLOCK_Pcc3BusIpSrcPll3Pfd1Div1 =
617 CLOCK_IP_SOURCE_PCC_INDEX(3U) | 5U, /*!< PCC3 Bus clock selection: kCLOCK_Pll3Pfd1Div1Clk */
618 kCLOCK_Pcc3BusIpSrcPll3Pfd0Div2 =
619 CLOCK_IP_SOURCE_PCC_INDEX(3U) | 6U, /*!< PCC3 Bus clock selection: kCLOCK_Pll3Pfd0Div2Clk */
620 kCLOCK_Pcc3BusIpSrcPll3Pfd0Div1 =
621 CLOCK_IP_SOURCE_PCC_INDEX(3U) | 7U, /*!< PCC3 Bus clock selection: kCLOCK_Pll3Pfd0Div1Clk */
622
623 /* PCC4 platform PCS */
624 kCLOCK_Pcc4PlatIpSrcSysOscDiv1 =
625 CLOCK_IP_SOURCE_PCC_INDEX(4U) | 1U, /*!< PCC4 Platform clock selection: kCLOCK_AdSysOscDiv1Clk */
626 kCLOCK_Pcc4PlatIpSrcFroDiv1 =
627 CLOCK_IP_SOURCE_PCC_INDEX(4U) | 2U, /*!< PCC4 Platform clock selection: kCLOCK_AdFroDiv1Clk */
628 kCLOCK_Pcc4PlatIpSrcPll3Pfd3Div2 =
629 CLOCK_IP_SOURCE_PCC_INDEX(4U) | 3U, /*!< PCC4 Platform clock selection: kCLOCK_Pll3Pfd3Div2Clk */
630 kCLOCK_Pcc4PlatIpSrcPll3Pfd3Div1 =
631 CLOCK_IP_SOURCE_PCC_INDEX(4U) | 4U, /*!< PCC4 Platform clock selection: kCLOCK_Pll3Pfd3Div1Clk */
632 kCLOCK_Pcc4PlatIpSrcPll3Pfd2Div2 =
633 CLOCK_IP_SOURCE_PCC_INDEX(4U) | 5U, /*!< PCC4 Platform clock selection: kCLOCK_Pll3Pfd2Div2Clk */
634 kCLOCK_Pcc4PlatIpSrcPll3Pfd2Div1 =
635 CLOCK_IP_SOURCE_PCC_INDEX(4U) | 6U, /*!< PCC4 Platform clock selection: kCLOCK_Pll3Pfd2Div1Clk */
636 kCLOCK_Pcc4PlatIpSrcPll3Pfd1Div2 =
637 CLOCK_IP_SOURCE_PCC_INDEX(4U) | 7U, /*!< PCC4 Platform clock selection: kCLOCK_Pll3Pfd1Div2Clk */
638
639 /* PCC4 bus PCS */
640 kCLOCK_Pcc4BusIpSrcLpo = CLOCK_IP_SOURCE_PCC_INDEX(4U) | 2U, /*!< PCC4 Bus clock selection: kCLOCK_LpOscClk */
641 kCLOCK_Pcc4BusIpSrcSysOscDiv2 =
642 CLOCK_IP_SOURCE_PCC_INDEX(4U) | 3U, /*!< PCC4 Bus clock selection: kCLOCK_AdSysOscDiv2Clk */
643 kCLOCK_Pcc4BusIpSrcFroDiv2 =
644 CLOCK_IP_SOURCE_PCC_INDEX(4U) | 4U, /*!< PCC4 Bus clock selection: kCLOCK_AdFroDiv2Clk */
645 kCLOCK_Pcc4BusIpSrcXbarBus = CLOCK_IP_SOURCE_PCC_INDEX(4U) | 5U, /*!< PCC4 Bus clock selection: kCLOCK_XbarBusClk */
646 kCLOCK_Pcc4BusIpSrcPll3VcoDiv =
647 CLOCK_IP_SOURCE_PCC_INDEX(4U) | 6U, /*!< PCC4 Bus clock selection: kCLOCK_Pll3VcoDivClk */
648 kCLOCK_Pcc4BusIpSrcPll3Pfd0Div1 =
649 CLOCK_IP_SOURCE_PCC_INDEX(4U) | 7U, /*!< PCC4 Bus clock selection: kCLOCK_Pll3Pfd0Div1Clk */
650
651 /* PCC5 platform PCS */
652 kCLOCK_Pcc5PlatIpSrcPll4Pfd3Div2 =
653 CLOCK_IP_SOURCE_PCC_INDEX(5U) | 1U, /*!< PCC5 Platform clock selection: kCLOCK_Pll4Pfd3Div2Clk */
654 kCLOCK_Pcc5PlatIpSrcPll4Pfd2Div2 =
655 CLOCK_IP_SOURCE_PCC_INDEX(5U) | 2U, /*!< PCC5 Platform clock selection: kCLOCK_Pll4Pfd2Div2Clk */
656 kCLOCK_Pcc5PlatIpSrcPll4Pfd2Div1 =
657 CLOCK_IP_SOURCE_PCC_INDEX(5U) | 3U, /*!< PCC5 Platform clock selection: kCLOCK_Pll4Pfd2Div1Clk */
658 kCLOCK_Pcc5PlatIpSrcPll4Pfd1Div2 =
659 CLOCK_IP_SOURCE_PCC_INDEX(5U) | 4U, /*!< PCC5 Platform clock selection: kCLOCK_Pll4Pfd1Div2Clk */
660 kCLOCK_Pcc5PlatIpSrcPll4Pfd1Div1 =
661 CLOCK_IP_SOURCE_PCC_INDEX(5U) | 5U, /*!< PCC5 Platform clock selection: kCLOCK_Pll4Pfd1Div1Clk */
662 kCLOCK_Pcc5PlatIpSrcPll4Pfd0Div2 =
663 CLOCK_IP_SOURCE_PCC_INDEX(5U) | 6U, /*!< PCC5 Platform clock selection: kCLOCK_Pll4Pfd0Div2Clk */
664 kCLOCK_Pcc5PlatIpSrcPll4Pfd0Div1 =
665 CLOCK_IP_SOURCE_PCC_INDEX(5U) | 7U, /*!< PCC5 Platform clock selection: kCLOCK_Pll4Pfd0Div1Clk */
666
667 /* PCC5 bus PCS */
668 kCLOCK_Pcc5BusIpSrcLpo = CLOCK_IP_SOURCE_PCC_INDEX(5U) | 2U, /*!< PCC5 Bus clock selection: kCLOCK_LpOscClk */
669 kCLOCK_Pcc5BusIpSrcSysOscDiv2 =
670 CLOCK_IP_SOURCE_PCC_INDEX(5U) | 3U, /*!< PCC5 Bus clock selection: kCLOCK_LpavSysOscDiv2Clk */
671 kCLOCK_Pcc5BusIpSrcFroDiv2 =
672 CLOCK_IP_SOURCE_PCC_INDEX(5U) | 4U, /*!< PCC5 Bus clock selection: kCLOCK_LpavFroDiv2Clk */
673 kCLOCK_Pcc5BusIpSrcLpavBus =
674 CLOCK_IP_SOURCE_PCC_INDEX(5U) | 5U, /*!< PCC5 Bus clock selection: kCLOCK_NicLpavBusClk */
675 kCLOCK_Pcc5BusIpSrcPll4VcoDiv =
676 CLOCK_IP_SOURCE_PCC_INDEX(5U) | 6U, /*!< PCC5 Bus clock selection: kCLOCK_Pll4VcoDivClk */
677 kCLOCK_Pcc5BusIpSrcPll4Pfd3Div1 =
678 CLOCK_IP_SOURCE_PCC_INDEX(5U) | 7U, /*!< PCC5 Bus clock selection: kCLOCK_Pll4Pfd3Div1Clk */
679
680 /* SAI0-1/MQS0 clock source */
681 kCLOCK_Cm33SaiClkSrcPll1Pfd2Div =
682 CLOCK_IP_SOURCE_NON_PCC_INDEX(1U) | 0U, /*!< PLL1 PFD2 DIV in RTD: kCLOCK_Pll1Pfd2DivClk. */
683 kCLOCK_Cm33SaiClkSrcRtdAudClk =
684 CLOCK_IP_SOURCE_NON_PCC_INDEX(1U) | 1U, /*!< Common audio clock in RTD, see cgc_rtd_audclk_src_t. */
685 kCLOCK_Cm33SaiClkSrcLpavAudClk =
686 CLOCK_IP_SOURCE_NON_PCC_INDEX(1U) | 2U, /*!< Common audio clock in LPAV, see cgc_lpav_audclk_src_t. */
687 kCLOCK_Cm33SaiClkSrcSysOsc =
688 CLOCK_IP_SOURCE_NON_PCC_INDEX(1U) | 3U, /*!< SYSOSC main reference clock to the chip: kCLOCK_SysOscClk. */
689
690 /* SAI2-3 clock source */
691 kCLOCK_FusionSaiClkSrcPll1Pfd2Div =
692 CLOCK_IP_SOURCE_NON_PCC_INDEX(2U) | 0U, /*!< PLL1 PFD2 DIV in RTD: kCLOCK_Pll1Pfd2DivClk. */
693 kCLOCK_FusionSaiClkSrcExtMclk1 =
694 CLOCK_IP_SOURCE_NON_PCC_INDEX(2U) | 1U, /*!< External audio master clock input 1. */
695 kCLOCK_FusionSaiClkSrcSai3Rx =
696 CLOCK_IP_SOURCE_NON_PCC_INDEX(2U) | 2U, /*!< SAI3 receiver serial bit clock. Only for SAI2. */
697 kCLOCK_FusionSaiClkSrcSai2Tx =
698 CLOCK_IP_SOURCE_NON_PCC_INDEX(2U) | 2U, /*!< SAI2 transmitter serial bit clock. Only for SAI3. */
699 kCLOCK_FusionSaiClkSrcSysOsc =
700 CLOCK_IP_SOURCE_NON_PCC_INDEX(2U) | 3U, /*!< SYSOSC main reference clock to the chip: kCLOCK_SysOscClk. */
701 /* MICFIL clock source */
702 kCLOCK_FusionMicfilClkSrcPll1Pfd2Div =
703 CLOCK_IP_SOURCE_NON_PCC_INDEX(3U) | 0U, /*!< PLL1 PFD2 DIV in RTD: kCLOCK_Pll1Pfd2DivClk */
704 kCLOCK_FusionMicfilClkSrcFro24 = CLOCK_IP_SOURCE_NON_PCC_INDEX(3U) | 1U, /*!< FRO24: kCLOCK_FroClk/8. */
705 kCLOCK_FusionMicfilClkSrcSysOsc =
706 CLOCK_IP_SOURCE_NON_PCC_INDEX(3U) | 2U, /*!< SYSOSC main reference clock to the chip: kCLOCK_SysOscClk. */
707 kCLOCK_FusionMicfilClkSrcExtMclk1 =
708 CLOCK_IP_SOURCE_NON_PCC_INDEX(3U) | 3U, /*!< External audio master clock input 1. */
709 kCLOCK_FusionMicfilClkSrcRtcOsc = CLOCK_IP_SOURCE_NON_PCC_INDEX(3U) | 4U, /*!< kCLOCK_RtcOscClk. */
710 kCLOCK_FusionMicfilClkSrcLpo = CLOCK_IP_SOURCE_NON_PCC_INDEX(3U) | 5U, /*!< kCLOCK_LpOscClk. */
711 /* TPM2 clock source */
712 kCLOCK_FusionTpm2ClkSrcPll1Pfd2Div =
713 CLOCK_IP_SOURCE_NON_PCC_INDEX(4U) | 0U, /*!< PLL1 PFD2 DIV in RTD: kCLOCK_Pll1Pfd2DivClk. */
714 kCLOCK_FusionTpm2ClkSrcExtMclk1 =
715 CLOCK_IP_SOURCE_NON_PCC_INDEX(4U) | 1U, /*!< External audio master clock input 1. */
716 kCLOCK_FusionTpm2ClkSrcLpo =
717 CLOCK_IP_SOURCE_NON_PCC_INDEX(4U) | 0x11U, /*!< PCC2 Bus clock selection: kCLOCK_LpOscClk */
718 kCLOCK_FusionTpm2ClkSrcSysOscDiv3 =
719 CLOCK_IP_SOURCE_NON_PCC_INDEX(4U) | 0x12U, /*!< PCC2 Bus clock selection: kCLOCK_RtdSysOscDiv3Clk */
720 kCLOCK_FusionTpm2ClkSrcFroDiv3 =
721 CLOCK_IP_SOURCE_NON_PCC_INDEX(4U) | 0x13U, /*!< PCC2 Bus clock selection: kCLOCK_RtdFroDiv3Clk */
722 kCLOCK_FusionTpm2ClkSrcFusionDspBus =
723 CLOCK_IP_SOURCE_NON_PCC_INDEX(4U) | 0x14U, /*!< PCC2 Bus clock selection: kCLOCK_FusionDspBusClk */
724 kCLOCK_FusionTpm2ClkSrcPll1VcoDiv =
725 CLOCK_IP_SOURCE_NON_PCC_INDEX(4U) | 0x15U, /*!< PCC2 Bus clock selection: kCLOCK_Pll1VcoDivClk */
726 kCLOCK_FusionTpm2ClkSrcPll0Pfd2Div =
727 CLOCK_IP_SOURCE_NON_PCC_INDEX(4U) | 0x16U, /*!< PCC2 Bus clock selection: kCLOCK_Pll0Pfd2DivClk */
728 kCLOCK_FusionTpm2ClkSrcPll0Pfd1Div =
729 CLOCK_IP_SOURCE_NON_PCC_INDEX(4U) | 0x17U, /*!< PCC2 Bus clock selection: kCLOCK_Pll0Pfd1DivClk */
730 /* TPM3 clock source */
731 kCLOCK_FusionTpm3ClkSrcPll1Pfd2Div =
732 CLOCK_IP_SOURCE_NON_PCC_INDEX(5U) | 0U, /*!< PLL1 PFD2 DIV in RTD: kCLOCK_Pll1Pfd2DivClk. */
733 kCLOCK_FusionTpm3ClkSrcRtdAudClk =
734 CLOCK_IP_SOURCE_NON_PCC_INDEX(5U) | 1U, /*!< Common audio clock in RTD, see cgc_rtd_audclk_src_t. */
735 kCLOCK_FusionTpm3ClkSrcLpavAudClk =
736 CLOCK_IP_SOURCE_NON_PCC_INDEX(5U) | 2U, /*!< Common audio clock in LPAV, see cgc_lpav_audclk_src_t. */
737 kCLOCK_FusionTpm3ClkSrcLpo =
738 CLOCK_IP_SOURCE_NON_PCC_INDEX(5U) | 0x11U, /*!< PCC2 Bus clock selection: kCLOCK_LpOscClk */
739 kCLOCK_FusionTpm3ClkSrcSysOscDiv3 =
740 CLOCK_IP_SOURCE_NON_PCC_INDEX(5U) | 0x12U, /*!< PCC2 Bus clock selection: kCLOCK_RtdSysOscDiv3Clk */
741 kCLOCK_FusionTpm3ClkSrcFroDiv3 =
742 CLOCK_IP_SOURCE_NON_PCC_INDEX(5U) | 0x13U, /*!< PCC2 Bus clock selection: kCLOCK_RtdFroDiv3Clk */
743 kCLOCK_FusionTpm3ClkSrcFusionDspBus =
744 CLOCK_IP_SOURCE_NON_PCC_INDEX(5U) | 0x14U, /*!< PCC2 Bus clock selection: kCLOCK_FusionDspBusClk */
745 kCLOCK_FusionTpm3ClkSrcPll1VcoDiv =
746 CLOCK_IP_SOURCE_NON_PCC_INDEX(5U) | 0x15U, /*!< PCC2 Bus clock selection: kCLOCK_Pll1VcoDivClk */
747 kCLOCK_FusionTpm3ClkSrcPll0Pfd2Div =
748 CLOCK_IP_SOURCE_NON_PCC_INDEX(5U) | 0x16U, /*!< PCC2 Bus clock selection: kCLOCK_Pll0Pfd2DivClk */
749 kCLOCK_FusionTpm3ClkSrcPll0Pfd1Div =
750 CLOCK_IP_SOURCE_NON_PCC_INDEX(5U) | 0x17U, /*!< PCC2 Bus clock selection: kCLOCK_Pll0Pfd1DivClk */
751
752 /* SAI4-5/MQS1 clock source */
753 kCLOCK_AdSaiClkSrcPll3Pfd1Div1 =
754 CLOCK_IP_SOURCE_NON_PCC_INDEX(6U) | 0U, /*!< PLL3 PFD1 DIV1 in AD: kCLOCK_Pll3Pfd1Div2Clk. */
755 kCLOCK_AdSaiClkSrcAdAudClk =
756 CLOCK_IP_SOURCE_NON_PCC_INDEX(6U) | 1U, /*!< Common audio clock in AD, see cgc_ad_audclk_src_t. */
757 kCLOCK_AdSaiClkSrcLpavAudClk =
758 CLOCK_IP_SOURCE_NON_PCC_INDEX(6U) | 2U, /*!< Common audio clock in LPAV, see cgc_lpav_audclk_src_t. */
759 kCLOCK_AdSaiClkSrcSysOsc =
760 CLOCK_IP_SOURCE_NON_PCC_INDEX(6U) | 3U, /*!< SYSOSC main reference clock to the chip: kCLOCK_SysOscClk. */
761 /* TPM6-7 clock source */
762 kCLOCK_AdTpm67ClkSrcPll3Pfd1Div1 =
763 CLOCK_IP_SOURCE_NON_PCC_INDEX(7U) | 0U, /*!< PLL3 PFD1 DIV1 in AD: kCLOCK_Pll3Pfd1Div2Clk. */
764 kCLOCK_AdTpm67ClkSrcAdAudClk =
765 CLOCK_IP_SOURCE_NON_PCC_INDEX(7U) | 1U, /*!< Common audio clock in AD, see cgc_ad_audclk_src_t. */
766 kCLOCK_AdTpm67ClkSrcLpavAudClk =
767 CLOCK_IP_SOURCE_NON_PCC_INDEX(7U) | 2U, /*!< Common audio clock in LPAV, see cgc_lpav_audclk_src_t. */
768 kCLOCK_AdTpm67ClkSrcLpo =
769 CLOCK_IP_SOURCE_NON_PCC_INDEX(7U) | 0x12U, /*!< PCC4 Bus clock selection: kCLOCK_LpOscClk */
770 kCLOCK_AdTpm67ClkSrcSysOscDiv2 =
771 CLOCK_IP_SOURCE_NON_PCC_INDEX(7U) | 0x13U, /*!< PCC4 Bus clock selection: kCLOCK_AdSysOscDiv2Clk */
772 kCLOCK_AdTpm67ClkSrcFroDiv2 =
773 CLOCK_IP_SOURCE_NON_PCC_INDEX(7U) | 0x14U, /*!< PCC4 Bus clock selection: kCLOCK_AdFroDiv2Clk */
774 kCLOCK_AdTpm67ClkSrcXbarBus =
775 CLOCK_IP_SOURCE_NON_PCC_INDEX(7U) | 0x15U, /*!< PCC4 Bus clock selection: kCLOCK_XbarBusClk */
776 kCLOCK_AdTpm67ClkSrcPll3VcoDiv =
777 CLOCK_IP_SOURCE_NON_PCC_INDEX(7U) | 0x16U, /*!< PCC4 Bus clock selection: kCLOCK_Pll3VcoDivClk */
778 kCLOCK_AdTpm67ClkSrcPll3Pfd0Div1 =
779 CLOCK_IP_SOURCE_NON_PCC_INDEX(7U) | 0x17U, /*!< PCC4 Bus clock selection: kCLOCK_Pll3Pfd0Div1Clk */
780
781 /* SAI6-7/SPDIF clock source */
782 kCLOCK_LpavSaiClkSrcPll1Pfd2Div =
783 CLOCK_IP_SOURCE_NON_PCC_INDEX(8U) | 0U, /*!< PLL1 PFD2 DIV in RTD: kCLOCK_Pll1Pfd2DivClk. */
784 kCLOCK_LpavSaiClkSrcPll3Pfd1Div1 =
785 CLOCK_IP_SOURCE_NON_PCC_INDEX(8U) | 1U, /*!< PLL3 PFD1 DIV1 in AD: kCLOCK_Pll3Pfd1Div1Clk. */
786 kCLOCK_LpavSaiClkSrcRtdAudClk =
787 CLOCK_IP_SOURCE_NON_PCC_INDEX(8U) | 2U, /*!< Common audio clock in RTD, see cgc_rtd_audclk_src_t. */
788 kCLOCK_LpavSaiClkSrcAdAudClk =
789 CLOCK_IP_SOURCE_NON_PCC_INDEX(8U) | 3U, /*!< Common audio clock in AD, see cgc_ad_audclk_src_t. */
790 kCLOCK_LpavSaiClkSrcLpavAudClk =
791 CLOCK_IP_SOURCE_NON_PCC_INDEX(8U) | 4U, /*!< Common audio clock in LPAV, see cgc_lpav_audclk_src_t. */
792 kCLOCK_LpavSaiClkSrcSysOsc =
793 CLOCK_IP_SOURCE_NON_PCC_INDEX(8U) | 5U, /*!< SYSOSC main reference clock to the chip. */
794 /* TPM8 clock source */
795 kCLOCK_LpavTpm8ClkSrcPll1Pfd2Div =
796 CLOCK_IP_SOURCE_NON_PCC_INDEX(9U) | 0U, /*!< PLL1 PFD2 DIV in RTD: kCLOCK_Pll1Pfd2DivClk. */
797 kCLOCK_LpavTpm8ClkSrcPll3Pfd1Div1 =
798 CLOCK_IP_SOURCE_NON_PCC_INDEX(9U) | 1U, /*!< PLL3 PFD1 DIV1 in AD: kCLOCK_Pll3Pfd1Div1Clk. */
799 kCLOCK_LpavTpm8ClkSrcRtdAudClk =
800 CLOCK_IP_SOURCE_NON_PCC_INDEX(9U) | 2U, /*!< Common audio clock in RTD, see cgc_rtd_audclk_src_t. */
801 kCLOCK_LpavTpm8ClkSrcAdAudClk =
802 CLOCK_IP_SOURCE_NON_PCC_INDEX(9U) | 3U, /*!< Common audio clock in AD, see cgc_ad_audclk_src_t. */
803 kCLOCK_LpavTpm8ClkSrcLpavAudClk =
804 CLOCK_IP_SOURCE_NON_PCC_INDEX(9U) | 4U, /*!< Common audio clock in LPAV, see cgc_lpav_audclk_src_t. */
805 kCLOCK_LpavTpm8ClkSrcLpo =
806 CLOCK_IP_SOURCE_NON_PCC_INDEX(9U) | 0x12U, /*!< PCC5 Bus clock selection: kCLOCK_LpOscClk */
807 kCLOCK_LpavTpm8ClkSrcSysOscDiv2 =
808 CLOCK_IP_SOURCE_NON_PCC_INDEX(9U) | 0x13U, /*!< PCC5 Bus clock selection: kCLOCK_LpavSysOscDiv2Clk */
809 kCLOCK_LpavTpm8ClkSrcFroDiv2 =
810 CLOCK_IP_SOURCE_NON_PCC_INDEX(9U) | 0x14U, /*!< PCC5 Bus clock selection: kCLOCK_LpavFroDiv2Clk */
811 kCLOCK_LpavTpm8ClkSrcLpavBus =
812 CLOCK_IP_SOURCE_NON_PCC_INDEX(9U) | 0x15U, /*!< PCC5 Bus clock selection: kCLOCK_NicLpavBusClk */
813 kCLOCK_LpavTpm8ClkSrcPll4VcoDiv =
814 CLOCK_IP_SOURCE_NON_PCC_INDEX(9U) | 0x16U, /*!< PCC5 Bus clock selection: kCLOCK_Pll4VcoDivClk */
815 kCLOCK_LpavTpm8ClkSrcPll4Pfd3Div1 =
816 CLOCK_IP_SOURCE_NON_PCC_INDEX(9U) | 0x17U, /*!< PCC5 Bus clock selection: kCLOCK_Pll4Pfd3Div1Clk */
817 } clock_ip_src_t;
818
819 /*!
820 * @brief Clock source for LPTMR.
821 */
822 typedef enum _clock_lptmr_src
823 {
824 kCLOCK_LptmrSrcLPO1M = 0U, /*!< LPO 1MHz clock. */
825 kCLOCK_LptmrSrcRtc1K = 1U, /*!< RTC 1KHz clock. */
826 kCLOCK_LptmrSrcRtc32K = 2U, /*!< RTC 32KHz clock. */
827 kCLOCK_LptmrSrcSysOsc = 3U, /*!< system OSC clock. */
828 } clock_lptmr_src_t;
829
830 /*!
831 * @brief Peripheral clock name difinition used for clock gate, clock source
832 * and clock divider setting.
833 * [31:2] is defined as the corresponding register address.
834 * [ 1:1] is used as indicator of existing of PCS.
835 * [ 0:0] is used as indicator of existing of PCD/FRAC.
836 */
837 typedef enum _clock_ip_name
838 {
839 kCLOCK_IpInvalid = 0U,
840 /* PCC 0 for CM33 */
841 kCLOCK_Dma0 = (uint32_t)(PCC0_BASE + 0x4),
842 kCLOCK_Dma0Ch0 = (uint32_t)(PCC0_BASE + 0x8),
843 kCLOCK_Dma0Ch1 = (uint32_t)(PCC0_BASE + 0xc),
844 kCLOCK_Dma0Ch2 = (uint32_t)(PCC0_BASE + 0x10),
845 kCLOCK_Dma0Ch3 = (uint32_t)(PCC0_BASE + 0x14),
846 kCLOCK_Dma0Ch4 = (uint32_t)(PCC0_BASE + 0x18),
847 kCLOCK_Dma0Ch5 = (uint32_t)(PCC0_BASE + 0x1c),
848 kCLOCK_Dma0Ch6 = (uint32_t)(PCC0_BASE + 0x20),
849 kCLOCK_Dma0Ch7 = (uint32_t)(PCC0_BASE + 0x24),
850 kCLOCK_Dma0Ch8 = (uint32_t)(PCC0_BASE + 0x28),
851 kCLOCK_Dma0Ch9 = (uint32_t)(PCC0_BASE + 0x2c),
852 kCLOCK_Dma0Ch10 = (uint32_t)(PCC0_BASE + 0x30),
853 kCLOCK_Dma0Ch11 = (uint32_t)(PCC0_BASE + 0x34),
854 kCLOCK_Dma0Ch12 = (uint32_t)(PCC0_BASE + 0x38),
855 kCLOCK_Dma0Ch13 = (uint32_t)(PCC0_BASE + 0x3c),
856 kCLOCK_Dma0Ch14 = (uint32_t)(PCC0_BASE + 0x40),
857 kCLOCK_Dma0Ch15 = (uint32_t)(PCC0_BASE + 0x44),
858 kCLOCK_Dma0Ch16 = (uint32_t)(PCC0_BASE + 0x48),
859 kCLOCK_Dma0Ch17 = (uint32_t)(PCC0_BASE + 0x4c),
860 kCLOCK_Dma0Ch18 = (uint32_t)(PCC0_BASE + 0x50),
861 kCLOCK_Dma0Ch19 = (uint32_t)(PCC0_BASE + 0x54),
862 kCLOCK_Dma0Ch20 = (uint32_t)(PCC0_BASE + 0x58),
863 kCLOCK_Dma0Ch21 = (uint32_t)(PCC0_BASE + 0x5c),
864 kCLOCK_Dma0Ch22 = (uint32_t)(PCC0_BASE + 0x60),
865 kCLOCK_Dma0Ch23 = (uint32_t)(PCC0_BASE + 0x64),
866 kCLOCK_Dma0Ch24 = (uint32_t)(PCC0_BASE + 0x68),
867 kCLOCK_Dma0Ch25 = (uint32_t)(PCC0_BASE + 0x6c),
868 kCLOCK_Dma0Ch26 = (uint32_t)(PCC0_BASE + 0x70),
869 kCLOCK_Dma0Ch27 = (uint32_t)(PCC0_BASE + 0x74),
870 kCLOCK_Dma0Ch28 = (uint32_t)(PCC0_BASE + 0x78),
871 kCLOCK_Dma0Ch29 = (uint32_t)(PCC0_BASE + 0x7c),
872 kCLOCK_Dma0Ch30 = (uint32_t)(PCC0_BASE + 0x80),
873 kCLOCK_Dma0Ch31 = (uint32_t)(PCC0_BASE + 0x84),
874 kCLOCK_Mu0A = (uint32_t)(PCC0_BASE + 0x88),
875 kCLOCK_Mu1A = (uint32_t)(PCC0_BASE + 0x8c),
876 kCLOCK_Mu2A = (uint32_t)(PCC0_BASE + 0x90),
877 kCLOCK_Syspm0 = (uint32_t)(PCC0_BASE + 0x98),
878 kCLOCK_Wuu0 = (uint32_t)(PCC0_BASE + 0xa0),
879 kCLOCK_UpowerMuARtd = (uint32_t)(PCC0_BASE + 0xa4),
880 kCLOCK_Wdog0 = (uint32_t)(PCC0_BASE + 0xb0) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
881 kCLOCK_Wdog1 = (uint32_t)(PCC0_BASE + 0xb4) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
882 kCLOCK_TrdcMgr = (uint32_t)(PCC0_BASE + 0xc4),
883 kCLOCK_TrdcMbc0 = (uint32_t)(PCC0_BASE + 0xc8),
884 kCLOCK_TrdcMbc1 = (uint32_t)(PCC0_BASE + 0xcc),
885 kCLOCK_TrdcMbc2 = (uint32_t)(PCC0_BASE + 0xd0),
886 kCLOCK_TrdcMbc3 = (uint32_t)(PCC0_BASE + 0xd4),
887 kCLOCK_TrdcMrc = (uint32_t)(PCC0_BASE + 0xd8),
888 kCLOCK_Sema420 = (uint32_t)(PCC0_BASE + 0xdc),
889 kCLOCK_Bbnsm = (uint32_t)(PCC0_BASE + 0xe0),
890 kCLOCK_Flexspi0 = (uint32_t)(PCC0_BASE + 0xe4) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
891 kCLOCK_Lpit0 = (uint32_t)(PCC0_BASE + 0xec) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
892 kCLOCK_Flexio0 = (uint32_t)(PCC0_BASE + 0xf0) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
893 kCLOCK_I3c0 = (uint32_t)(PCC0_BASE + 0xf4) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
894 kCLOCK_Lpspi0 = (uint32_t)(PCC0_BASE + 0xf8) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
895 kCLOCK_Lpspi1 = (uint32_t)(PCC0_BASE + 0xfc) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
896 kCLOCK_Adc0 = (uint32_t)(PCC0_BASE + 0x100) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
897 kCLOCK_Cmp0 = (uint32_t)(PCC0_BASE + 0x104),
898 kCLOCK_Cmp1 = (uint32_t)(PCC0_BASE + 0x108),
899 kCLOCK_Dac0 = (uint32_t)(PCC0_BASE + 0x10c) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
900 kCLOCK_Dac1 = (uint32_t)(PCC0_BASE + 0x110) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
901 kCLOCK_Cm33Cache = (uint32_t)(PCC0_BASE + 0x118),
902 kCLOCK_SentinelLpuart = (uint32_t)(PCC0_BASE + 0x130) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
903 kCLOCK_PowersysWdog = (uint32_t)(PCC0_BASE + 0x138) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
904 kCLOCK_Ocotp = (uint32_t)(PCC0_BASE + 0x13c),
905
906 /* PCC 1 for CM33 */
907 kCLOCK_Tpiu = (uint32_t)(PCC1_BASE + 0xc) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
908 kCLOCK_Swo = (uint32_t)(PCC1_BASE + 0x18) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
909 kCLOCK_Flexspi1 = (uint32_t)(PCC1_BASE + 0x48) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
910 kCLOCK_Lptmr0 = (uint32_t)(PCC1_BASE + 0x4c),
911 kCLOCK_Lptmr1 = (uint32_t)(PCC1_BASE + 0x50),
912 kCLOCK_Tpm0 = (uint32_t)(PCC1_BASE + 0x54) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
913 kCLOCK_Tpm1 = (uint32_t)(PCC1_BASE + 0x58) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
914 kCLOCK_Lpi2c0 = (uint32_t)(PCC1_BASE + 0x60) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
915 kCLOCK_Lpi2c1 = (uint32_t)(PCC1_BASE + 0x64) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
916 kCLOCK_Lpuart0 = (uint32_t)(PCC1_BASE + 0x68) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
917 kCLOCK_Lpuart1 = (uint32_t)(PCC1_BASE + 0x6c) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
918 kCLOCK_Sai0 = (uint32_t)(PCC1_BASE + 0x70),
919 kCLOCK_Sai1 = (uint32_t)(PCC1_BASE + 0x74),
920 kCLOCK_DigFiltA = (uint32_t)(PCC1_BASE + 0x78),
921 kCLOCK_DigFiltB = (uint32_t)(PCC1_BASE + 0x7c),
922 kCLOCK_Adc1 = (uint32_t)(PCC1_BASE + 0x88) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
923 kCLOCK_Flexcan = (uint32_t)(PCC1_BASE + 0xa0) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
924 kCLOCK_RgpioA = (uint32_t)(PCC1_BASE + 0xb4),
925 kCLOCK_RgpioB = (uint32_t)(PCC1_BASE + 0xb8),
926 kCLOCK_RgpioC = (uint32_t)(PCC1_BASE + 0xbc),
927
928 /* PCC 2 for FusionF1 */
929 kCLOCK_Mu1B = (uint32_t)(PCC2_BASE + 0x0),
930 kCLOCK_Wdog2 = (uint32_t)(PCC2_BASE + 0x4) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
931 kCLOCK_Tpm2 = (uint32_t)(PCC2_BASE + 0x14) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
932 kCLOCK_Tpm3 = (uint32_t)(PCC2_BASE + 0x18) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
933 kCLOCK_Mrt = (uint32_t)(PCC2_BASE + 0x1c),
934 kCLOCK_Lpi2c2 = (uint32_t)(PCC2_BASE + 0x20) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
935 kCLOCK_Lpi2c3 = (uint32_t)(PCC2_BASE + 0x24) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
936 kCLOCK_I3c1 = (uint32_t)(PCC2_BASE + 0x28) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
937 kCLOCK_Lpuart2 = (uint32_t)(PCC2_BASE + 0x2c) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
938 kCLOCK_Lpuart3 = (uint32_t)(PCC2_BASE + 0x30) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
939 kCLOCK_Lpspi2 = (uint32_t)(PCC2_BASE + 0x34) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
940 kCLOCK_Lpspi3 = (uint32_t)(PCC2_BASE + 0x38) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
941 kCLOCK_Sai2 = (uint32_t)(PCC2_BASE + 0x3c),
942 kCLOCK_Sai3 = (uint32_t)(PCC2_BASE + 0x40),
943 kCLOCK_Micfil = (uint32_t)(PCC2_BASE + 0x44),
944
945 /* PCC 3 for CA35 */
946 kCLOCK_Dma1 = (uint32_t)(PCC3_BASE + 0x4),
947 kCLOCK_Dma1Ch0 = (uint32_t)(PCC3_BASE + 0x8),
948 kCLOCK_Dma1Ch1 = (uint32_t)(PCC3_BASE + 0xc),
949 kCLOCK_Dma1Ch2 = (uint32_t)(PCC3_BASE + 0x10),
950 kCLOCK_Dma1Ch3 = (uint32_t)(PCC3_BASE + 0x14),
951 kCLOCK_Dma1Ch4 = (uint32_t)(PCC3_BASE + 0x18),
952 kCLOCK_Dma1Ch5 = (uint32_t)(PCC3_BASE + 0x1c),
953 kCLOCK_Dma1Ch6 = (uint32_t)(PCC3_BASE + 0x20),
954 kCLOCK_Dma1Ch7 = (uint32_t)(PCC3_BASE + 0x24),
955 kCLOCK_Dma1Ch8 = (uint32_t)(PCC3_BASE + 0x28),
956 kCLOCK_Dma1Ch9 = (uint32_t)(PCC3_BASE + 0x2c),
957 kCLOCK_Dma1Ch10 = (uint32_t)(PCC3_BASE + 0x30),
958 kCLOCK_Dma1Ch11 = (uint32_t)(PCC3_BASE + 0x34),
959 kCLOCK_Dma1Ch12 = (uint32_t)(PCC3_BASE + 0x38),
960 kCLOCK_Dma1Ch13 = (uint32_t)(PCC3_BASE + 0x3c),
961 kCLOCK_Dma1Ch14 = (uint32_t)(PCC3_BASE + 0x40),
962 kCLOCK_Dma1Ch15 = (uint32_t)(PCC3_BASE + 0x44),
963 kCLOCK_Dma1Ch16 = (uint32_t)(PCC3_BASE + 0x48),
964 kCLOCK_Dma1Ch17 = (uint32_t)(PCC3_BASE + 0x4c),
965 kCLOCK_Dma1Ch18 = (uint32_t)(PCC3_BASE + 0x50),
966 kCLOCK_Dma1Ch19 = (uint32_t)(PCC3_BASE + 0x54),
967 kCLOCK_Dma1Ch20 = (uint32_t)(PCC3_BASE + 0x58),
968 kCLOCK_Dma1Ch21 = (uint32_t)(PCC3_BASE + 0x5c),
969 kCLOCK_Dma1Ch22 = (uint32_t)(PCC3_BASE + 0x60),
970 kCLOCK_Dma1Ch23 = (uint32_t)(PCC3_BASE + 0x64),
971 kCLOCK_Dma1Ch24 = (uint32_t)(PCC3_BASE + 0x68),
972 kCLOCK_Dma1Ch25 = (uint32_t)(PCC3_BASE + 0x6c),
973 kCLOCK_Dma1Ch26 = (uint32_t)(PCC3_BASE + 0x70),
974 kCLOCK_Dma1Ch27 = (uint32_t)(PCC3_BASE + 0x74),
975 kCLOCK_Dma1Ch28 = (uint32_t)(PCC3_BASE + 0x78),
976 kCLOCK_Dma1Ch29 = (uint32_t)(PCC3_BASE + 0x7c),
977 kCLOCK_Dma1Ch30 = (uint32_t)(PCC3_BASE + 0x80),
978 kCLOCK_Dma1Ch31 = (uint32_t)(PCC3_BASE + 0x84),
979 kCLOCK_Mu0B = (uint32_t)(PCC3_BASE + 0x88),
980 kCLOCK_Mu3A = (uint32_t)(PCC3_BASE + 0x8c),
981 kCLOCK_Wuu1 = (uint32_t)(PCC3_BASE + 0x98),
982 kCLOCK_Syspm1 = (uint32_t)(PCC3_BASE + 0x9c),
983 kCLOCK_UpowerMuAApd = (uint32_t)(PCC3_BASE + 0xa0),
984 kCLOCK_Wdog3 = (uint32_t)(PCC3_BASE + 0xa8) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
985 kCLOCK_Wdog4 = (uint32_t)(PCC3_BASE + 0xac) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
986 kCLOCK_Caam = (uint32_t)(PCC3_BASE + 0xb8),
987 kCLOCK_XrdcMgr = (uint32_t)(PCC3_BASE + 0xbc),
988 kCLOCK_Sema421 = (uint32_t)(PCC3_BASE + 0xc0),
989 kCLOCK_Lpit1 = (uint32_t)(PCC3_BASE + 0xc8) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
990 kCLOCK_Tpm4 = (uint32_t)(PCC3_BASE + 0xcc) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
991 kCLOCK_Tpm5 = (uint32_t)(PCC3_BASE + 0xd0) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
992 kCLOCK_Flexio1 = (uint32_t)(PCC3_BASE + 0xd4) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
993 kCLOCK_I3c2 = (uint32_t)(PCC3_BASE + 0xd8) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
994 kCLOCK_Lpi2c4 = (uint32_t)(PCC3_BASE + 0xdc) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
995 kCLOCK_Lpi2c5 = (uint32_t)(PCC3_BASE + 0xe0) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
996 kCLOCK_Lpuart4 = (uint32_t)(PCC3_BASE + 0xe4) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
997 kCLOCK_Lpuart5 = (uint32_t)(PCC3_BASE + 0xe8) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
998 kCLOCK_Lpspi4 = (uint32_t)(PCC3_BASE + 0xec) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
999 kCLOCK_Lpspi5 = (uint32_t)(PCC3_BASE + 0xf0) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1000
1001 /* PCC 4 for CA35 */
1002 kCLOCK_Flexspi2 = (uint32_t)(PCC4_BASE + 0x4) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1003 kCLOCK_Tpm6 = (uint32_t)(PCC4_BASE + 0x8) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1004 kCLOCK_Tpm7 = (uint32_t)(PCC4_BASE + 0xc) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1005 kCLOCK_Lpi2c6 = (uint32_t)(PCC4_BASE + 0x10) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1006 kCLOCK_Lpi2c7 = (uint32_t)(PCC4_BASE + 0x14) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1007 kCLOCK_Lpuart6 = (uint32_t)(PCC4_BASE + 0x18) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1008 kCLOCK_Lpuart7 = (uint32_t)(PCC4_BASE + 0x1c) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1009 kCLOCK_Sai4 = (uint32_t)(PCC4_BASE + 0x20),
1010 kCLOCK_Sai5 = (uint32_t)(PCC4_BASE + 0x24),
1011 kCLOCK_DigFiltE = (uint32_t)(PCC4_BASE + 0x28),
1012 kCLOCK_DigFiltF = (uint32_t)(PCC4_BASE + 0x2c),
1013 kCLOCK_Usdhc0 = (uint32_t)(PCC4_BASE + 0x34) | PCC_PCS_AVAIL_MASK,
1014 kCLOCK_Usdhc1 = (uint32_t)(PCC4_BASE + 0x38) | PCC_PCS_AVAIL_MASK,
1015 kCLOCK_Usdhc2 = (uint32_t)(PCC4_BASE + 0x3c) | PCC_PCS_AVAIL_MASK,
1016 kCLOCK_Usb0 = (uint32_t)(PCC4_BASE + 0x40),
1017 kCLOCK_Usb0Phy = (uint32_t)(PCC4_BASE + 0x44),
1018 kCLOCK_Usb1 = (uint32_t)(PCC4_BASE + 0x48),
1019 kCLOCK_Usb1Phy = (uint32_t)(PCC4_BASE + 0x4c),
1020 kCLOCK_UsbXbar = (uint32_t)(PCC4_BASE + 0x50),
1021 kCLOCK_Enet = (uint32_t)(PCC4_BASE + 0x54),
1022 kCLOCK_RgpioE = (uint32_t)(PCC4_BASE + 0x78),
1023 kCLOCK_RgpioF = (uint32_t)(PCC4_BASE + 0x7c),
1024
1025 /* PCC 5 for HiFi4 */
1026 kCLOCK_Dma2 = (uint32_t)(PCC5_BASE + 0x0),
1027 kCLOCK_Dma2Ch0 = (uint32_t)(PCC5_BASE + 0x4),
1028 kCLOCK_Dma2Ch1 = (uint32_t)(PCC5_BASE + 0x8),
1029 kCLOCK_Dma2Ch2 = (uint32_t)(PCC5_BASE + 0xc),
1030 kCLOCK_Dma2Ch3 = (uint32_t)(PCC5_BASE + 0x10),
1031 kCLOCK_Dma2Ch4 = (uint32_t)(PCC5_BASE + 0x14),
1032 kCLOCK_Dma2Ch5 = (uint32_t)(PCC5_BASE + 0x18),
1033 kCLOCK_Dma2Ch6 = (uint32_t)(PCC5_BASE + 0x1c),
1034 kCLOCK_Dma2Ch7 = (uint32_t)(PCC5_BASE + 0x20),
1035 kCLOCK_Dma2Ch8 = (uint32_t)(PCC5_BASE + 0x24),
1036 kCLOCK_Dma2Ch9 = (uint32_t)(PCC5_BASE + 0x28),
1037 kCLOCK_Dma2Ch10 = (uint32_t)(PCC5_BASE + 0x2c),
1038 kCLOCK_Dma2Ch11 = (uint32_t)(PCC5_BASE + 0x30),
1039 kCLOCK_Dma2Ch12 = (uint32_t)(PCC5_BASE + 0x34),
1040 kCLOCK_Dma2Ch13 = (uint32_t)(PCC5_BASE + 0x38),
1041 kCLOCK_Dma2Ch14 = (uint32_t)(PCC5_BASE + 0x3c),
1042 kCLOCK_Dma2Ch15 = (uint32_t)(PCC5_BASE + 0x40),
1043 kCLOCK_Dma2Ch16 = (uint32_t)(PCC5_BASE + 0x44),
1044 kCLOCK_Dma2Ch17 = (uint32_t)(PCC5_BASE + 0x48),
1045 kCLOCK_Dma2Ch18 = (uint32_t)(PCC5_BASE + 0x4c),
1046 kCLOCK_Dma2Ch19 = (uint32_t)(PCC5_BASE + 0x50),
1047 kCLOCK_Dma2Ch20 = (uint32_t)(PCC5_BASE + 0x54),
1048 kCLOCK_Dma2Ch21 = (uint32_t)(PCC5_BASE + 0x58),
1049 kCLOCK_Dma2Ch22 = (uint32_t)(PCC5_BASE + 0x5c),
1050 kCLOCK_Dma2Ch23 = (uint32_t)(PCC5_BASE + 0x60),
1051 kCLOCK_Dma2Ch24 = (uint32_t)(PCC5_BASE + 0x64),
1052 kCLOCK_Dma2Ch25 = (uint32_t)(PCC5_BASE + 0x68),
1053 kCLOCK_Dma2Ch26 = (uint32_t)(PCC5_BASE + 0x6c),
1054 kCLOCK_Dma2Ch27 = (uint32_t)(PCC5_BASE + 0x70),
1055 kCLOCK_Dma2Ch28 = (uint32_t)(PCC5_BASE + 0x74),
1056 kCLOCK_Dma2Ch29 = (uint32_t)(PCC5_BASE + 0x78),
1057 kCLOCK_Dma2Ch30 = (uint32_t)(PCC5_BASE + 0x7c),
1058 kCLOCK_Dma2Ch31 = (uint32_t)(PCC5_BASE + 0x80),
1059 kCLOCK_Mu2B = (uint32_t)(PCC5_BASE + 0x84),
1060 kCLOCK_Mu3B = (uint32_t)(PCC5_BASE + 0x88),
1061 kCLOCK_Sema422 = (uint32_t)(PCC5_BASE + 0x8c),
1062 kCLOCK_Tpm8 = (uint32_t)(PCC5_BASE + 0xa0) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1063 kCLOCK_Sai6 = (uint32_t)(PCC5_BASE + 0xa4),
1064 kCLOCK_Sai7 = (uint32_t)(PCC5_BASE + 0xa8),
1065 kCLOCK_Spdif = (uint32_t)(PCC5_BASE + 0xac),
1066 kCLOCK_Isi = (uint32_t)(PCC5_BASE + 0xb0),
1067 kCLOCK_CsiRegs = (uint32_t)(PCC5_BASE + 0xb4),
1068 kCLOCK_Csi = (uint32_t)(PCC5_BASE + 0xbc) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1069 kCLOCK_Dsi = (uint32_t)(PCC5_BASE + 0xc0) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1070 kCLOCK_Wdog5 = (uint32_t)(PCC5_BASE + 0xc8) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1071 kCLOCK_Epdc = (uint32_t)(PCC5_BASE + 0xcc) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1072 kCLOCK_Pxp = (uint32_t)(PCC5_BASE + 0xd0),
1073 kCLOCK_Gpu2d = (uint32_t)(PCC5_BASE + 0xf0) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1074 kCLOCK_Gpu3d = (uint32_t)(PCC5_BASE + 0xf4) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1075 kCLOCK_Dcnano = (uint32_t)(PCC5_BASE + 0xf8) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1076 kCLOCK_Lpddr4 = (uint32_t)(PCC5_BASE + 0x108),
1077 kCLOCK_CsiClkUi = (uint32_t)(PCC5_BASE + 0x10c) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1078 kCLOCK_CsiClkEsc = (uint32_t)(PCC5_BASE + 0x110) | PCC_PCS_AVAIL_MASK | PCC_PCD_FRAC_AVAIL_MASK,
1079 kCLOCK_RgpioD = (uint32_t)(PCC5_BASE + 0x114),
1080
1081 /* Non-PCC IPs */
1082 kCLOCK_Mqs0 = (uint32_t)(CGC_RTD_BASE + 0x90c) | IP_NAME_NON_PCC_FLAG_MASK,
1083 kCLOCK_Mqs1 = (uint32_t)(CGC_AD_BASE + 0x90c) | IP_NAME_NON_PCC_FLAG_MASK,
1084 } clock_ip_name_t;
1085
1086 /*!
1087 * @brief CGC status return codes.
1088 */
1089 enum
1090 {
1091 kStatus_CGC_Busy = MAKE_STATUS(kStatusGroup_SCG, 1), /*!< Clock is busy. */
1092 kStatus_CGC_InvalidSrc = MAKE_STATUS(kStatusGroup_SCG, 2) /*!< Invalid source. */
1093 };
1094
1095 /*!
1096 * @brief CGC system clock type.
1097 */
1098 typedef enum _cgc_sys_clk
1099 {
1100 /* RTD */
1101 kCGC_SysClkSlow, /*!< System slow clock. */
1102 kCGC_SysClkBus, /*!< Bus clock. */
1103 kCGC_SysClkCorePlat, /*!< Core/Platform clock. */
1104
1105 /* LPAV HIFI */
1106 kCGC_SysClkHifi4, /*!< Hifi4 core clock. */
1107 kCGC_SysClkNicHifi, /*!< Hifi4 platform clock. */
1108 /* NIC LPAV */
1109 kCGC_SysClkLpavAxi, /*!< LPAV AXI clock. */
1110 kCGC_SysClkLpavAhb, /*!< LPAV AHB clock. */
1111 kCGC_SysClkLpavBus, /*!< LPAV Bus clock. */
1112 } cgc_sys_clk_t;
1113
1114 /*!
1115 * @brief CGC system clock source for RTD.
1116 */
1117 typedef enum _cgc_rtd_sys_clk_src
1118 {
1119 kCGC_RtdSysClkSrcFro = 0U, /*!< FRO192. */
1120 kCGC_RtdSysClkSrcPll0Pfd0 = 1U, /*!< PLL0 PFD0. */
1121 kCGC_RtdSysClkSrcPll1Pfd0 = 2U, /*!< PLL1 PFD0. */
1122 kCGC_RtdSysClkSrcSysOsc = 3U, /*!< System OSC. */
1123 kCGC_RtdSysClkSrcRtcOsc = 4U, /*!< RTC OSC. */
1124 kCGC_RtdSysClkSrcLvds = 5U, /*!< LVDS XCVR. */
1125 kCGC_RtdSysClkSrcPll0 = 6U, /*!< PLL0. */
1126 } cgc_rtd_sys_clk_src_t;
1127
1128 /*!
1129 * @brief CGC system clock source for NIC in AD.
1130 */
1131 typedef enum _cgc_nic_sys_clk_src
1132 {
1133 kCGC_NicSysClkSrcFro = 0U, /*!< FRO192. */
1134 kCGC_NicSysClkSrcPll3Pfd0 = 1U, /*!< PLL0 PFD0. */
1135 kCGC_NicSysClkSrcSysOsc = 2U, /*!< System OSC. */
1136 kCGC_NicSysClkSrcLvds = 3U, /*!< LVDS XCVR. */
1137 } cgc_nic_sys_clk_src_t;
1138
1139 /*!
1140 * @brief CGC system clock source for HIFI4 in LPAV.
1141 */
1142 typedef enum _cgc_hifi_sys_clk_src
1143 {
1144 kCGC_HifiSysClkSrcFro = 0U, /*!< FRO192. */
1145 kCGC_HifiSysClkSrcPll4 = 1U, /*!< PLL4. */
1146 kCGC_HifiSysClkSrcPll4Pfd0 = 2U, /*!< PLL4 PFD0. */
1147 kCGC_HifiSysClkSrcSysOsc = 3U, /*!< System OSC. */
1148 kCGC_HifiSysClkSrcLvds = 4U, /*!< LVDS XCVR. */
1149 } cgc_hifi_sys_clk_src_t;
1150
1151 /*!
1152 * @brief CGC system clock source for LPAV.
1153 */
1154 typedef enum _cgc_lpav_sys_clk_src
1155 {
1156 kCGC_LpavSysClkSrcFro = 0U, /*!< FRO192. */
1157 kCGC_LpavSysClkSrcPll4Pfd1 = 1U, /*!< PLL4 PFD1. */
1158 kCGC_LpavSysClkSrcSysOsc = 2U, /*!< System OSC. */
1159 kCGC_LpavSysClkSrcLvds = 3U, /*!< LVDS XCVR. */
1160 } cgc_lpav_sys_clk_src_t;
1161
1162 /*!
1163 * @brief CGC system clock source for DDR.
1164 */
1165 typedef enum _cgc_ddr_sys_clk_src
1166 {
1167 kCGC_DdrSysClkSrcFro = 0U, /*!< FRO192. */
1168 kCGC_DdrSysClkSrcPll4Pfd1 = 1U, /*!< PLL4 PFD1. */
1169 kCGC_DdrSysClkSrcSysOsc = 2U, /*!< System OSC. */
1170 kCGC_DdrSysClkSrcLvds = 3U, /*!< LVDS XCVR. */
1171 } cgc_ddr_sys_clk_src_t;
1172
1173 /*!
1174 * @brief CGC system clock configuration for RTD.
1175 */
1176 typedef struct _cgc_rtd_sys_clk_config
1177 {
1178 uint32_t divSlow : 6; /*!< Slow clock divider, selected division is the value of the field + 1 */
1179 uint32_t : 1; /*!< Reserved. */
1180 uint32_t divBus : 6; /*!< Bus clock divider, selected division is the value of the field + 1. */
1181 uint32_t : 8; /*!< Reserved. */
1182 uint32_t divCore : 6; /*!< Core/Platform clock divider, selected division is the value of the field + 1. */
1183 uint32_t switchFin : 1; /*!< 1: Clock is running. 0: Clock is not running. */
1184 uint32_t src : 3; /*!< System clock source, see @ref cgc_rtd_sys_clk_src_t. */
1185 uint32_t locked : 1; /*!< Clock register locked. */
1186 } cgc_rtd_sys_clk_config_t;
1187
1188 /*!
1189 * @brief CGC system clock configuration for HIFI4 DSP.
1190 */
1191 typedef struct _cgc_hifi_sys_clk_config
1192 {
1193 uint32_t : 14; /*!< Reserved. */
1194 uint32_t divPlat : 6; /*!< Platform clock divider, selected division is the value of the field + 1. */
1195 uint32_t : 1; /*!< Reserved. */
1196 uint32_t divCore : 6; /*!< Core clock divider, selected division is the value of the field + 1. */
1197 uint32_t switchFin : 1; /*!< 1: Clock is running. 0: Clock is not running. */
1198 uint32_t src : 3; /*!< System clock source, see @ref cgc_hifi_sys_clk_src_t. */
1199 uint32_t locked : 1; /*!< Clock register locked. */
1200 } cgc_hifi_sys_clk_config_t;
1201
1202 /*!
1203 * @brief CGC system clock configuration for LPAV.
1204 */
1205 typedef struct _cgc_lpav_sys_clk_config
1206 {
1207 uint32_t : 7; /*!< Reserved. */
1208 uint32_t divBus : 6; /*!< Platform clock divider, selected division is the value of the field + 1. */
1209 uint32_t : 1; /*!< Reserved. */
1210 uint32_t divAhb : 6; /*!< Platform clock divider, selected division is the value of the field + 1. */
1211 uint32_t : 1; /*!< Reserved. */
1212 uint32_t divAxi : 6; /*!< Core clock divider, selected division is the value of the field + 1. */
1213 uint32_t switchFin : 1; /*!< 1: Clock is running. 0: Clock is not running. */
1214 uint32_t src : 2; /*!< System clock source, see @ref cgc_lpav_sys_clk_src_t. */
1215 uint32_t : 1; /*!< Reserved. */
1216 uint32_t locked : 1; /*!< Clock register locked. */
1217 } cgc_lpav_sys_clk_config_t;
1218
1219 /*!
1220 * @brief CGC system clock configuration for DDR in LPAV.
1221 */
1222 typedef struct _cgc_ddr_sys_clk_config
1223 {
1224 uint32_t : 21; /*!< Reserved. */
1225 uint32_t divDdr : 6; /*!< DDR clock divider, selected division is the value of the field + 1. */
1226 uint32_t switchFin : 1; /*!< 1: Clock is running. 0: Clock is not running. */
1227 uint32_t src : 3; /*!< System clock source, see @ref cgc_lpav_sys_clk_src_t. */
1228 uint32_t locked : 1; /*!< Clock register locked. */
1229 } cgc_ddr_sys_clk_config_t;
1230
1231 /*!
1232 * @brief CGC clock out configuration (CLKOUTCFG) in RTD.
1233 */
1234 typedef enum _clock_rtd_clkout_src
1235 {
1236 kClockRtdClkoutSelCm33Core = 0U, /*!< CGC CM33 Core/Platform clock. */
1237 kClockRtdClkoutSelCm33Bus = 1U, /*!< CGC CM33 Bus clock. */
1238 kClockRtdClkoutSelCm33Slow = 2U, /*!< CGC CM33 Slow clock. */
1239 kClockRtdClkoutSelFusionDspCore = 3U, /*!< CGC Fusion DSP Core/Platform clock. */
1240 kClockRtdClkoutSelFusionDspBus = 4U, /*!< CGC Fusion DSP Bus clock. */
1241 kClockRtdClkoutSelFusionDspSlow = 5U, /*!< CGC Fusion DSP Slow clock. */
1242 kClockRtdClkoutSelFro48 = 6U, /*!< FRO48: kCLOCK_FroClk/4. */
1243 kClockRtdClkoutSelPll0VcoDiv = 7U, /*!< PLL0 VCO DIV: kCLOCK_Pll0VcoDivClk. */
1244 kClockRtdClkoutSelPll1VcoDiv = 8U, /*!< PLL1 VCO DIV: kCLOCK_Pll1VcoDivClk. */
1245 kClockRtdClkoutSelSysOsc = 9U, /*!< System OSC. */
1246 kClockRtdClkoutSelLpOsc = 10U, /*!< CGC LPOSC clock. */
1247 } clock_rtd_clkout_src_t;
1248
1249 /*!
1250 * @brief CGC clock out configuration (CLKOUTCFG) in LPAV.
1251 */
1252 typedef enum _clock_lpav_clkout_src
1253 {
1254 kClockLpavClkoutSelHifi4 = 0U, /*!< CGC HIFI4 core clock. */
1255 kClockLpavClkoutSelNicHifi = 1U, /*!< CGC HIFI4 platform clock. */
1256 kClockLpavClkoutSelLpavAxi = 2U, /*!< CGC NIC LPAV AXI clock. */
1257 kClockLpavClkoutSelLpavAhb = 3U, /*!< CGC NIC LPAV AHB clock. */
1258 kClockLpavClkoutSelLpavBus = 4U, /*!< CGC LPAV Bus clock. */
1259 kClockLpavClkoutSelDdr = 5U, /*!< CGC DDR clock. */
1260 kClockLpavClkoutSelFro48 = 6U, /*!< FRO48: kCLOCK_FroClk/4. */
1261 kClockLpavClkoutSelPll4VcoDiv = 7U, /*!< PLL4 VCO DIV: kCLOCK_Pll4VcoDivClk. */
1262 kClockLpavClkoutSelSysOsc = 9U, /*!< System OSC. */
1263 kClockLpavClkoutSelLpOsc = 10U, /*!< CGC LPOSC clock. */
1264 } clock_lpav_clkout_src_t;
1265
1266 /*!
1267 * @brief CGC asynchronous clock type.
1268 */
1269 typedef enum _cgc_async_clk
1270 {
1271 kCGC_AsyncDiv1Clk = 1U, /*!< The async clock by DIV1, e.g. SOSCDIV1_CLK, FRODIV1_CLK. */
1272 kCGC_AsyncDiv2Clk = 2U, /*!< The async clock by DIV2, e.g. SOSCDIV2_CLK, FRODIV2_CLK. */
1273 kCGC_AsyncDiv3Clk = 3U, /*!< The async clock by DIV3, e.g. SOSCDIV3_CLK, FRODIV3_CLK. */
1274 kCGC_AsyncVcoClk = 4U, /*!< The async clock by PLL VCO DIV. */
1275 kCGC_AsyncPfd0Div1Clk = 5U, /*!< The async clock by PLL PFD0 DIV1. */
1276 kCGC_AsyncPfd0Div2Clk = 6U, /*!< The async clock by PLL PFD0 DIV2. */
1277 kCGC_AsyncPfd1Div1Clk = 7U, /*!< The async clock by PLL PFD1 DIV or DIV1. */
1278 kCGC_AsyncPfd1Div2Clk = 8U, /*!< The async clock by PLL PFD1 DIV2. */
1279 kCGC_AsyncPfd2Div1Clk = 9U, /*!< The async clock by PLL PFD2 DIV or DIV1. */
1280 kCGC_AsyncPfd2Div2Clk = 10U, /*!< The async clock by PLL PFD2 DIV2. */
1281 kCGC_AsyncPfd3Div1Clk = 11U, /*!< The async clock by PLL PFD3 DIV1. */
1282 kCGC_AsyncPfd3Div2Clk = 12U, /*!< The async clock by PLL PFD3 DIV2. */
1283 } cgc_async_clk_t;
1284
1285 /*!
1286 * @brief CGC system OSC monitor mode.
1287 */
1288 typedef enum _cgc_sosc_monitor_mode
1289 {
1290 kCGC_SysOscMonitorDisable = 0U, /*!< Monitor disabled. */
1291 kCGC_SysOscMonitorInt = CGC_SOSCCSR_SOSCCM_MASK, /*!< Interrupt when the system OSC error is detected. */
1292 kCGC_SysOscMonitorReset =
1293 CGC_SOSCCSR_SOSCCM_MASK | CGC_SOSCCSR_SOSCCMRE_MASK /*!< Reset when the system OSC error is detected. */
1294 } cgc_sosc_monitor_mode_t;
1295
1296 /*! @brief OSC work mode. */
1297 typedef enum _cgc_sosc_mode
1298 {
1299 kCGC_SysOscModeExt = CGC_SOSCCFG_SYSOSC_BYPASS_EN_MASK, /*!< Use external clock. */
1300 kCGC_SysOscModeOscLowPower = 0, /*!< Oscillator low power. */
1301 kCGC_SysOscModeOscHighGain = CGC_SOSCCFG_HGO_MASK /*!< Oscillator high gain. */
1302 } cgc_sosc_mode_t;
1303
1304 /*! @brief OSC enable mode. */
1305 enum _cgc_sosc_enable_mode
1306 {
1307 kCGC_SysOscEnableInDeepSleep = CGC_SOSCCSR_SOSCDSEN_MASK, /*!< Enable OSC in deep sleep mode. */
1308 kCGC_SysOscEnableInPowerDown = CGC_SOSCCSR_SOSCPDEN_MASK, /*!< Enable OSC in low power mode. */
1309 };
1310
1311 /*!
1312 * @brief CGC system OSC configuration.
1313 */
1314 typedef struct _cgc_sosc_config
1315 {
1316 uint32_t freq; /*!< System OSC frequency. */
1317 cgc_sosc_monitor_mode_t monitorMode; /*!< Clock monitor mode selected. */
1318 uint8_t enableMode; /*!< Enable mode, OR'ed value of _cgc_sosc_enable_mode. */
1319
1320 cgc_sosc_mode_t workMode; /*!< OSC work mode. */
1321 } cgc_sosc_config_t;
1322
1323 /*! @brief FRO enable mode. */
1324 enum _cgc_fro_enable_mode
1325 {
1326 kCGC_FroEnableInDeepSleep = CGC_FROCSR_FRODSEN_MASK, /*!< Enable FRO in deep sleep mode. */
1327 };
1328
1329 /*!
1330 * @brief CGC FRO clock configuration.
1331 */
1332 typedef struct _cgc_fro_config
1333 {
1334 uint32_t enableMode; /*!< Enable mode, OR'ed value of _cgc_fro_enable_mode. */
1335 } cgc_fro_config_t;
1336
1337 /*! @brief LPOSC enable mode. */
1338 enum _cgc_lposc_enable_mode
1339 {
1340 kCGC_LposcEnableInDeepSleep = CGC_LPOSCCSR_LPOSCDSEN_MASK, /*!< Enable OSC in deep sleep mode. */
1341 kCGC_LposcEnableInPowerDown = CGC_LPOSCCSR_LPOSCPDEN_MASK, /*!< Enable OSC in low power mode. */
1342 };
1343
1344 /*!
1345 * @brief CGC LPOSC clock configuration.
1346 */
1347 typedef struct _cgc_lposc_config
1348 {
1349 uint32_t enableMode; /*!< Enable mode, OR'ed value of _cgc_lposc_enable_mode. */
1350 } cgc_lposc_config_t;
1351
1352 /*!
1353 * @brief CGC PLL clock source.
1354 */
1355 typedef enum _cgc_pll_src
1356 {
1357 kCGC_PllSrcSysOsc, /*!< PLL clock source is system OSC. */
1358 kCGC_PllSrcFro24M, /*!< PLL clock source is FRO 24M. */
1359 } cgc_pll_src_t;
1360
1361 /*! @brief PLL enable mode. */
1362 enum _cgc_pll_enable_mode
1363 {
1364 kCGC_PllEnable = CGC_PLL0CSR_PLL0EN_MASK, /*!< Enable PLL clock. */
1365 kCGC_PllEnableInDeepSleep = CGC_PLL0CSR_PLL0DSEN_MASK /*!< Enable PLL in deep sleep mode. */
1366 };
1367
1368 /*!
1369 * @brief CGC PLL PFD clouk out select.
1370 */
1371 typedef enum _cgc_pll_pfd_clkout
1372 {
1373 kCGC_PllPfd0Clk = 0U, /*!< PFD0 output clock selected. */
1374 kCGC_PllPfd1Clk = 8U, /*!< PFD1 output clock selected. */
1375 kCGC_PllPfd2Clk = 16U, /*!< PFD2 output clock selected. */
1376 kCGC_PllPfd3Clk = 24U /*!< PFD3 output clock selected. */
1377 } cgc_pll_pfd_clkout_t;
1378
1379 /*! @brief PLL0 Multiplication Factor */
1380 typedef enum _cgc_pll0_mult
1381 {
1382 kCGC_Pll0Mult15 = 1U, /*!< Divide by 15 */
1383 kCGC_Pll0Mult16 = 2U, /*!< Divide by 16 */
1384 kCGC_Pll0Mult20 = 3U, /*!< Divide by 20 */
1385 kCGC_Pll0Mult22 = 4U, /*!< Divide by 22 */
1386 kCGC_Pll0Mult25 = 5U, /*!< Divide by 25 */
1387 kCGC_Pll0Mult30 = 6U, /*!< Divide by 30 */
1388 } cgc_pll0_mult_t;
1389
1390 /*!
1391 * @brief CGC PLL0 configuration.
1392 */
1393 typedef struct _cgc_pll0_config
1394 {
1395 uint8_t enableMode; /*!< Enable mode, OR'ed value of _cgc_pll_enable_mode */
1396
1397 uint8_t div1; /*!< PLLDIV_VCO divider value. Disabled when div1 == 0. */
1398 uint8_t pfd1Div; /*!< PLLDIV_PFD_0 DIV1 divider value. Disabled when pfd1Div == 0. */
1399 uint8_t pfd2Div; /*!< PLLDIV_PFD_0 DIV2 divider value. Disabled when pfd2Div == 0. */
1400
1401 cgc_pll_src_t src; /*!< Clock source. */
1402 cgc_pll0_mult_t mult; /*!< PLL multiplier. */
1403 } cgc_pll0_config_t;
1404
1405 /*!
1406 * @brief CGC RTC OSC monitor mode.
1407 */
1408 typedef enum _cgc_rosc_monitor_mode
1409 {
1410 kCGC_RtcOscMonitorDisable = 0U, /*!< Monitor disabled. */
1411 kCGC_RtcOscMonitorInt = CGC_ROSCCTRL_ROSCCM_MASK, /*!< Interrupt when the RTC OSC error is detected. */
1412 kCGC_RtcOscMonitorReset =
1413 CGC_ROSCCTRL_ROSCCM_MASK | CGC_ROSCCTRL_ROSCCMRE_MASK /*!< Reset when the RTC OSC error is detected. */
1414 } cgc_rosc_monitor_mode_t;
1415
1416 /*!
1417 * @brief CGC RTC OSC configuration.
1418 */
1419 typedef struct _cgc_rosc_config
1420 {
1421 cgc_rosc_monitor_mode_t monitorMode; /*!< Clock monitor mode selected. */
1422 } cgc_rosc_config_t;
1423
1424 /*! @brief PLL1 Multiplication Factor */
1425 typedef enum _cgc_pll1_mult
1426 {
1427 kCGC_Pll1Mult16 = 16U, /*!< Divide by 16 */
1428 kCGC_Pll1Mult17 = 17U, /*!< Divide by 17 */
1429 kCGC_Pll1Mult20 = 20U, /*!< Divide by 20 */
1430 kCGC_Pll1Mult22 = 22U, /*!< Divide by 22 */
1431 kCGC_Pll1Mult27 = 27U, /*!< Divide by 27 */
1432 kCGC_Pll1Mult33 = 33U, /*!< Divide by 33 */
1433 } cgc_pll1_mult_t;
1434
1435 /*!
1436 * @brief CGC PLL1 configuration.
1437 */
1438 typedef struct _cgc_pll1_config
1439 {
1440 uint8_t enableMode; /*!< Enable mode, OR'ed value of _cgc_pll_enable_mode */
1441
1442 uint8_t div1; /*!< PLLDIV_VCO divider value. Disabled when div1 == 0. */
1443 uint8_t pfd1Div; /*!< PLLDIV_PFD_0 DIV1 divider value. Disabled when pfd1Div == 0. */
1444 uint8_t pfd2Div; /*!< PLLDIV_PFD_0 DIV2 divider value. Disabled when pfd2Div == 0. */
1445
1446 cgc_pll_src_t src; /*!< Clock source. */
1447 cgc_pll1_mult_t mult; /*!< PLL1 multiplier. */
1448
1449 uint32_t num : 30; /*!< 30-bit numerator of the PLL1 Fractional-Loop divider. */
1450 uint32_t denom : 30; /*!< 30-bit denominator of the PLL1 Fractional-Loop divider. */
1451 } cgc_pll1_config_t;
1452
1453 /*! @brief PLL4 Multiplication Factor */
1454 typedef enum _cgc_pll4_mult
1455 {
1456 kCGC_Pll4Mult16 = 16U, /*!< Divide by 16 */
1457 kCGC_Pll4Mult17 = 17U, /*!< Divide by 17 */
1458 kCGC_Pll4Mult20 = 20U, /*!< Divide by 20 */
1459 kCGC_Pll4Mult22 = 22U, /*!< Divide by 22 */
1460 kCGC_Pll4Mult27 = 27U, /*!< Divide by 27 */
1461 kCGC_Pll4Mult33 = 33U, /*!< Divide by 33 */
1462 } cgc_pll4_mult_t;
1463
1464 /*!
1465 * @brief CGC PLL4 configuration.
1466 */
1467 typedef struct _cgc_pll4_config
1468 {
1469 uint8_t enableMode; /*!< Enable mode, OR'ed value of _cgc_pll_enable_mode */
1470
1471 uint8_t div1; /*!< PLLDIV_VCO divider value. Disabled when div1 == 0. */
1472 uint8_t pfd0Div1; /*!< PLLDIV_PFD_0 DIV1 divider value. Disabled when pfd0Div1 == 0. */
1473 uint8_t pfd0Div2; /*!< PLLDIV_PFD_0 DIV2 divider value. Disabled when pfd0Div2 == 0. */
1474 uint8_t pfd1Div1; /*!< PLLDIV_PFD_0 DIV3 divider value. Disabled when pfd1Div1 == 0. */
1475 uint8_t pfd1Div2; /*!< PLLDIV_PFD_0 DIV4 divider value. Disabled when pfd1Div2 == 0. */
1476 uint8_t pfd2Div1; /*!< PLLDIV_PFD_1 DIV1 divider value. Disabled when pfd2Div1 == 0. */
1477 uint8_t pfd2Div2; /*!< PLLDIV_PFD_1 DIV2 divider value. Disabled when pfd2Div2 == 0. */
1478 uint8_t pfd3Div1; /*!< PLLDIV_PFD_2 DIV3 divider value. Disabled when pfd3Div1 == 0. */
1479 uint8_t pfd3Div2; /*!< PLLDIV_PFD_2 DIV4 divider value. Disabled when pfd3Div2 == 0. */
1480
1481 cgc_pll_src_t src; /*!< Clock source. */
1482 cgc_pll4_mult_t mult; /*!< PLL4 multiplier. */
1483
1484 uint32_t num : 30; /*!< 30-bit numerator of the PLL4 Fractional-Loop divider. */
1485 uint32_t denom : 30; /*!< 30-bit denominator of the PLL4 Fractional-Loop divider. */
1486 } cgc_pll4_config_t;
1487
1488 /*! @brief AUD_CLK0 source in RTD */
1489 typedef enum _cgc_rtd_audclk_src
1490 {
1491 kCGC_RtdAudClkSrcExtMclk0 = 0, /*!< External audio master clock input 0 from pin. */
1492 kCGC_RtdAudClkSrcExtMclk1 = 1, /*!< External audio master clock input 1 from pin. */
1493 kCGC_RtdAudClkSrcSai0RxBclk = 2, /*!< SAI0 receiver serial bit clock. */
1494 kCGC_RtdAudClkSrcSai0TxBclk = 3, /*!< SAI0 transmitter serial bit clock. */
1495 kCGC_RtdAudClkSrcSai1RxBclk = 4, /*!< SAI1 receiver serial bit clock. */
1496 kCGC_RtdAudClkSrcSai1TxBclk = 5, /*!< SAI1 transmitter serial bit clock. */
1497 kCGC_RtdAudClkSrcSai2RxBclk = 6, /*!< SAI2 receiver serial bit clock. */
1498 kCGC_RtdAudClkSrcSai2TxBclk = 7, /*!< SAI2 transmitter serial bit clock. */
1499 kCGC_RtdAudClkSrcSai3RxBclk = 8, /*!< SAI3 receiver serial bit clock. */
1500 kCGC_RtdAudClkSrcSai3TxBclk = 9, /*!< SAI3 transmitter serial bit clock. */
1501 } cgc_rtd_audclk_src_t;
1502
1503 /*! @brief AUD_CLK1 source in AD */
1504 typedef enum _cgc_ad_audclk_src
1505 {
1506 kCGC_AdAudClkSrcExtMclk2 = 0, /*!< External audio master clock input 2 from pin. */
1507 kCGC_AdAudClkSrcSai4RxBclk = 1, /*!< SAI4 receiver serial bit clock. */
1508 kCGC_AdAudClkSrcSai4TxBclk = 2, /*!< SAI4 transmitter serial bit clock. */
1509 kCGC_AdAudClkSrcSai5RxBclk = 3, /*!< SAI5 receiver serial bit clock. */
1510 kCGC_AdAudClkSrcSai5TxBclk = 4, /*!< SAI5 transmitter serial bit clock. */
1511 } cgc_ad_audclk_src_t;
1512
1513 /*! @brief AUD_CLK2 source in LPAV */
1514 typedef enum _cgc_lpav_audclk_src
1515 {
1516 kCGC_LpavAudClkSrcExtMclk3 = 0, /*!< External audio master clock input 3 from pin. */
1517 kCGC_LpavAudClkSrcSai6RxBclk = 1, /*!< SAI6 receiver serial bit clock. */
1518 kCGC_LpavAudClkSrcSai6TxBclk = 2, /*!< SAI6 transmitter serial bit clock. */
1519 kCGC_LpavAudClkSrcSai7RxBclk = 3, /*!< SAI7 receiver serial bit clock. */
1520 kCGC_LpavAudClkSrcSai7TxBclk = 4, /*!< SAI7 transmitter serial bit clock. */
1521 kCGC_LpavAudClkSrcSpdifRx = 5, /*!< SPDIF receiver clock. */
1522 } cgc_lpav_audclk_src_t;
1523
1524 /*******************************************************************************
1525 * API
1526 ******************************************************************************/
1527
1528 #if defined(__cplusplus)
1529 extern "C" {
1530 #endif /* __cplusplus */
1531
1532 /*!
1533 * @brief Enable the clock for specific IP.
1534 *
1535 * @param name Which clock to enable, see \ref clock_ip_name_t.
1536 */
CLOCK_EnableClock(clock_ip_name_t name)1537 static inline void CLOCK_EnableClock(clock_ip_name_t name)
1538 {
1539 assert(((uint32_t)name & IP_NAME_NON_PCC_FLAG_MASK) == 0U);
1540 assert(PCC_REG(name) & PCC_CLKCFG_PR_MASK);
1541
1542 PCC_REG(name) |= PCC_CLKCFG_CGC_MASK;
1543 }
1544
1545 /*!
1546 * @brief Disable the clock for specific IP.
1547 *
1548 * @param name Which clock to disable, see \ref clock_ip_name_t.
1549 */
CLOCK_DisableClock(clock_ip_name_t name)1550 static inline void CLOCK_DisableClock(clock_ip_name_t name)
1551 {
1552 assert(((uint32_t)name & IP_NAME_NON_PCC_FLAG_MASK) == 0U);
1553 assert(PCC_REG(name) & PCC_CLKCFG_PR_MASK);
1554
1555 PCC_REG(name) &= ~PCC_CLKCFG_CGC_MASK;
1556 }
1557
1558 /*!
1559 * @brief Check whether the clock is already enabled and configured by
1560 * any other core.
1561 *
1562 * @param name Which peripheral to check, see \ref clock_ip_name_t.
1563 * @return True if clock is already enabled, otherwise false.
1564 */
CLOCK_IsEnabledByOtherCore(clock_ip_name_t name)1565 static inline bool CLOCK_IsEnabledByOtherCore(clock_ip_name_t name)
1566 {
1567 assert(((uint32_t)name & IP_NAME_NON_PCC_FLAG_MASK) == 0U);
1568 assert(PCC_REG(name) & PCC_CLKCFG_PR_MASK);
1569
1570 return ((PCC_REG(name) & PCC_CLKCFG_INUSE_MASK) != 0UL) ? true : false;
1571 }
1572
1573 /*!
1574 * @brief Set the clock source for specific IP module.
1575 *
1576 * Set the clock source for specific IP, not all modules need to set the
1577 * clock source, should only use this function for the modules need source
1578 * setting.
1579 *
1580 * @param name Which peripheral to check, see \ref clock_ip_name_t.
1581 * @param src Clock source to set.
1582 */
1583 void CLOCK_SetIpSrc(clock_ip_name_t name, clock_ip_src_t src);
1584
1585 /*!
1586 * @brief Set the clock source and divider for specific IP module.
1587 *
1588 * Set the clock source and divider for specific IP, not all modules need to
1589 * set the clock source and divider, should only use this function for the
1590 * modules need source and divider setting.
1591 *
1592 * Divider output clock = Divider input clock x [(fracValue+1)/(divValue+1)]).
1593 *
1594 * @param name Which peripheral to check, see \ref clock_ip_name_t.
1595 * @param src Clock source to set.
1596 * @param divValue The divider value.
1597 * @param fracValue The fraction multiply value.
1598 */
1599 void CLOCK_SetIpSrcDiv(clock_ip_name_t name, clock_ip_src_t src, uint8_t divValue, uint8_t fracValue);
1600
1601 /*!
1602 * @brief Set the AUD_CLK0 source in RTD.
1603 * NOTE: The audio clock pin frequency is decided by SAI, but clock driver cannot depend on
1604 * SAI driver to get its pin frequencies, user need to explicitly set the MCLK/BCLK
1605 * frequencies if other modules use the AUD_CLK0 source and need to get correct frequency.
1606 *
1607 * @param src Clock source to set.
1608 */
CLOCK_SetRtdAudClkSrc(cgc_rtd_audclk_src_t src)1609 static inline void CLOCK_SetRtdAudClkSrc(cgc_rtd_audclk_src_t src)
1610 {
1611 CGC_RTD->AUD_CLK0 = CGC_AUD_CLK0_AUD_CLK0(src);
1612 }
1613
1614 /*!
1615 * @brief Set the AUD_CLK1 source in AD.
1616 * NOTE: The audio clock pin frequency is decided by SAI, but clock driver cannot depend on
1617 * SAI driver to get its pin frequencies, user need to explicitly set the MCLK/BCLK
1618 * frequencies if other modules use the AUD_CLK1 source and need to get correct frequency.
1619 *
1620 * @param src Clock source to set.
1621 */
CLOCK_SetAdAudClkSrc(cgc_ad_audclk_src_t src)1622 static inline void CLOCK_SetAdAudClkSrc(cgc_ad_audclk_src_t src)
1623 {
1624 CGC_AD->AUD_CLK1 = CGC_AD_AUD_CLK1_AUD_CLK1(src);
1625 }
1626
1627 /*!
1628 * @brief Set the AUD_CLK2 source in LPAV.
1629 * NOTE: The audio clock pin frequency is decided by SAI, but clock driver cannot depend on
1630 * SAI driver to get its pin frequencies, user need to explicitly set the MCLK/BCLK
1631 * frequencies if other modules use the AUD_CLK2 source and need to get correct frequency.
1632 *
1633 * @param src Clock source to set.
1634 */
CLOCK_SetLpavAudClkSrc(cgc_lpav_audclk_src_t src)1635 static inline void CLOCK_SetLpavAudClkSrc(cgc_lpav_audclk_src_t src)
1636 {
1637 CGC_LPAV->AUD_CLK2 = CGC_LPAV_AUD_CLK2_AUD_CLK2(src);
1638 }
1639
1640 /*!
1641 * @brief Gets the clock frequency for a specific clock name.
1642 *
1643 * This function checks the current clock configurations and then calculates
1644 * the clock frequency for a specific clock name defined in clock_name_t.
1645 *
1646 * @param clockName Clock names defined in clock_name_t
1647 * @return Clock frequency value in hertz
1648 */
1649 uint32_t CLOCK_GetFreq(clock_name_t clockName);
1650
1651 /*!
1652 * @brief Get the CM33 core/platform clock frequency.
1653 *
1654 * @return Clock frequency in Hz.
1655 */
1656 uint32_t CLOCK_GetCm33CorePlatClkFreq(void);
1657
1658 /*!
1659 * @brief Get the CM33 bus clock frequency.
1660 *
1661 * @return Clock frequency in Hz.
1662 */
1663 uint32_t CLOCK_GetCm33BusClkFreq(void);
1664
1665 /*!
1666 * @brief Get the CM33 slow clock frequency.
1667 *
1668 * @return Clock frequency in Hz.
1669 */
1670 uint32_t CLOCK_GetCm33SlowClkFreq(void);
1671
1672 /*!
1673 * @brief Get the Fusion DSP core/platform clock frequency.
1674 *
1675 * @return Clock frequency in Hz.
1676 */
1677 uint32_t CLOCK_GetFusionDspCorePlatClkFreq(void);
1678
1679 /*!
1680 * @brief Get the Fusion DSP bus clock frequency.
1681 *
1682 * @return Clock frequency in Hz.
1683 */
1684 uint32_t CLOCK_GetFusionDspBusClkFreq(void);
1685
1686 /*!
1687 * @brief Get the Fusion DSP slow clock frequency.
1688 *
1689 * @return Clock frequency in Hz.
1690 */
1691 uint32_t CLOCK_GetFusionDspSlowClkFreq(void);
1692
1693 /*!
1694 * @brief Get the external LVDS pad clock frequency (LVDS).
1695 *
1696 * @return Clock frequency in Hz.
1697 */
1698 uint32_t CLOCK_GetLvdsClkFreq(void);
1699
1700 /*!
1701 * @brief Gets the clock frequency for a specific IP module.
1702 *
1703 * This function gets the IP module clock frequency. It is only used for the IP
1704 * modules which could select clock source by CLOCK_SetIpSrc().
1705 *
1706 * @param name Which peripheral to get, see \ref clock_ip_name_t.
1707 * @return Clock frequency value in hertz
1708 */
1709 uint32_t CLOCK_GetIpFreq(clock_ip_name_t name);
1710
1711 /*!
1712 * @name MCU System Clock.
1713 * @{
1714 */
1715
1716 /*!
1717 * @brief Gets the CGC CM33 system clock frequency.
1718 *
1719 * This function gets the CGC CM33 system clock frequency. These clocks are used for
1720 * core, platform, bus and slow clock domains.
1721 *
1722 * @param type Which type of clock to get.
1723 * @return Clock frequency.
1724 */
1725 uint32_t CLOCK_GetCm33SysClkFreq(cgc_sys_clk_t type);
1726
1727 /*!
1728 * @brief Sets the system clock configuration for CM33 domain.
1729 *
1730 * This function sets the system clock configuration for CM33 domain.
1731 *
1732 * @param config Pointer to the configuration.
1733 */
CLOCK_SetCm33SysClkConfig(cgc_rtd_sys_clk_config_t * config)1734 static inline void CLOCK_SetCm33SysClkConfig(cgc_rtd_sys_clk_config_t *config)
1735 {
1736 assert(config);
1737 /* CM33 slow clock must be slower and an integer division of CM33 system IP bus. */
1738 assert(config->divSlow > config->divBus);
1739 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U);
1740
1741 CGC_RTD->CM33CLK = *(const uint32_t *)(uint32_t)config;
1742 }
1743
1744 /*!
1745 * @brief Gets the CGC Fusion DSP system clock frequency.
1746 *
1747 * This function gets the CGC Fusion DSP system clock frequency. These clocks are used for
1748 * core, platform, bus and slow clock domains.
1749 *
1750 * @param type Which type of clock to get.
1751 * @return Clock frequency.
1752 */
1753 uint32_t CLOCK_GetFusionDspSysClkFreq(cgc_sys_clk_t type);
1754
1755 /*!
1756 * @brief Sets the system clock configuration for FusionF1 DSP domain.
1757 *
1758 * This function sets the system clock configuration for FusionF1 DSP domain.
1759 *
1760 * @param config Pointer to the configuration.
1761 */
CLOCK_SetFusionSysClkConfig(const cgc_rtd_sys_clk_config_t * config)1762 static inline void CLOCK_SetFusionSysClkConfig(const cgc_rtd_sys_clk_config_t *config)
1763 {
1764 assert(config);
1765 /* Fusion DSP slow clock must be slower and an integer division of DSP system IP bus. */
1766 assert(config->divSlow > config->divBus);
1767 assert((config->divSlow + 1U) % (config->divBus + 1U) == 0U);
1768 CGC_RTD->FUSIONCLK = *(const uint32_t *)(uint32_t)config;
1769 }
1770
1771 /*!
1772 * @brief Gets the system clock configuration for CM33 domain.
1773 *
1774 * This function gets the system configuration for CM33 domain.
1775 *
1776 * @param config Pointer to the configuration.
1777 */
CLOCK_GetCm33SysClkConfig(cgc_rtd_sys_clk_config_t * config)1778 static inline void CLOCK_GetCm33SysClkConfig(cgc_rtd_sys_clk_config_t *config)
1779 {
1780 assert(config);
1781
1782 *(uint32_t *)(uint32_t)config = CGC_RTD->CM33CLK;
1783 }
1784
1785 /*!
1786 * @brief Gets the system clock configuration for FusionF1 DSP domain.
1787 *
1788 * This function gets the system configuration for FusionF1 DSP domain.
1789 *
1790 * @param config Pointer to the configuration.
1791 */
CLOCK_GetFusionDspSysClkConfig(cgc_rtd_sys_clk_config_t * config)1792 static inline void CLOCK_GetFusionDspSysClkConfig(cgc_rtd_sys_clk_config_t *config)
1793 {
1794 assert(config);
1795
1796 *(uint32_t *)(uint32_t)config = CGC_RTD->FUSIONCLK;
1797 }
1798
1799 /*!
1800 * @brief Sets the clock out configuration in RTD.
1801 *
1802 * This function sets the clock out configuration.
1803 *
1804 * @param setting The selection to set.
1805 * @param div The divider to set (div > 0).
1806 * @param enable Enable clock out.
1807 */
CLOCK_SetRtdClkOutConfig(clock_rtd_clkout_src_t setting,uint8_t div,bool enable)1808 static inline void CLOCK_SetRtdClkOutConfig(clock_rtd_clkout_src_t setting, uint8_t div, bool enable)
1809 {
1810 assert(div > 0U);
1811
1812 CGC_RTD->CLKOUTCFG = CGC_CLKOUTCFG_CLKOUT_SEL(setting) | CGC_CLKOUTCFG_CLKOUT_DIV((uint32_t)div - 1U) |
1813 (enable ? CGC_CLKOUTCFG_CLKOUT_EN_MASK : 0U);
1814 }
1815
1816 /*!
1817 * @brief Sets the RTC_CLOCKOUT configuration.
1818 *
1819 * This function sets the RTC_CLOCKOUT configuration.
1820 *
1821 * @param div The divider to set (div > 0).
1822 */
CLOCK_SetRtcClkOutConfig(uint8_t div)1823 static inline void CLOCK_SetRtcClkOutConfig(uint8_t div)
1824 {
1825 assert(div > 0U);
1826
1827 CGC_RTD->RTCDIV = CGC_RTCDIV_DIV1((uint32_t)div - 1U);
1828 }
1829
1830 /*!
1831 * @brief Gets the CGC XBAR bus clock frequency in AD.
1832 *
1833 * This function gets the CGC XBAR bus clock frequency.
1834 *
1835 * @return Clock frequency.
1836 */
1837 uint32_t CLOCK_GetXbarBusClkFreq(void);
1838
1839 /*!
1840 * @brief Gets the CGC HIFI DSP system clock frequency in LPAV.
1841 *
1842 * This function gets the CGC HIFI DSP system clock frequency. These clocks are used for
1843 * core, platform domains.
1844 *
1845 * @param type Which type of clock to get.
1846 * @return Clock frequency.
1847 */
1848 uint32_t CLOCK_GetHifiDspSysClkFreq(cgc_sys_clk_t type);
1849
1850 /*!
1851 * @brief Sets the system clock configuration for HIFI4 DSP domain.
1852 *
1853 * This function sets the system clock configuration for HIFI4 DSP domain.
1854 *
1855 * @param config Pointer to the configuration.
1856 */
CLOCK_SetHifiDspSysClkConfig(const cgc_hifi_sys_clk_config_t * config)1857 static inline void CLOCK_SetHifiDspSysClkConfig(const cgc_hifi_sys_clk_config_t *config)
1858 {
1859 assert(config);
1860
1861 CGC_LPAV->HIFICLK = *(const uint32_t *)(uint32_t)config;
1862 }
1863
1864 /*!
1865 * @brief Gets the system clock configuration for HIFI4 DSP domain.
1866 *
1867 * This function gets the system configuration for HIFI4 DSP domain.
1868 *
1869 * @param config Pointer to the configuration.
1870 */
CLOCK_GetHifiDspSysClkConfig(cgc_hifi_sys_clk_config_t * config)1871 static inline void CLOCK_GetHifiDspSysClkConfig(cgc_hifi_sys_clk_config_t *config)
1872 {
1873 assert(config);
1874
1875 *(uint32_t *)(uint32_t)config = CGC_LPAV->HIFICLK;
1876 }
1877
1878 /*!
1879 * @brief Gets the CGC NIC LPAV system clock frequency in LPAV.
1880 *
1881 * This function gets the CGC NIC LPAV system clock frequency. These clocks are used for
1882 * AXI, AHB, Bus domains.
1883 *
1884 * @param type Which type of clock to get.
1885 * @return Clock frequency.
1886 */
1887 uint32_t CLOCK_GetLpavSysClkFreq(cgc_sys_clk_t type);
1888
1889 /*!
1890 * @brief Sets the system clock configuration for NIC LPAV domain.
1891 *
1892 * This function sets the system clock configuration for NIC LPAV domain.
1893 *
1894 * @param config Pointer to the configuration.
1895 */
CLOCK_SetLpavSysClkConfig(const cgc_lpav_sys_clk_config_t * config)1896 static inline void CLOCK_SetLpavSysClkConfig(const cgc_lpav_sys_clk_config_t *config)
1897 {
1898 assert(config);
1899 /* Clock ratio must be integers between NIC_LPAV_AHB_CLK and LPAV_BUS_CLK */
1900 assert((config->divBus + 1U) % (config->divAhb + 1U) == 0U);
1901
1902 CGC_LPAV->NICLPAVCLK = *(const uint32_t *)(uint32_t)config;
1903 }
1904
1905 /*!
1906 * @brief Gets the system clock configuration for NIC LPAV domain.
1907 *
1908 * This function gets the system configuration for NIC LPAV domain.
1909 *
1910 * @param config Pointer to the configuration.
1911 */
CLOCK_GetLpavSysClkConfig(cgc_lpav_sys_clk_config_t * config)1912 static inline void CLOCK_GetLpavSysClkConfig(cgc_lpav_sys_clk_config_t *config)
1913 {
1914 assert(config);
1915
1916 *(uint32_t *)(uint32_t)config = CGC_LPAV->NICLPAVCLK;
1917 }
1918
1919 /*!
1920 * @brief Gets the CGC DDR clock frequency in LPAV.
1921 *
1922 * This function gets the CGC DDR clock frequency.
1923 *
1924 * @return Clock frequency.
1925 */
1926 uint32_t CLOCK_GetDdrClkFreq(void);
1927
1928 /*!
1929 * @brief Sets the clock out configuration in LPAV.
1930 *
1931 * This function sets the clock out configuration.
1932 *
1933 * @param setting The selection to set.
1934 * @param div The divider to set (div > 0).
1935 * @param enable Enable clock out.
1936 */
CLOCK_SetLpavClkOutConfig(clock_lpav_clkout_src_t setting,uint8_t div,bool enable)1937 static inline void CLOCK_SetLpavClkOutConfig(clock_lpav_clkout_src_t setting, uint8_t div, bool enable)
1938 {
1939 assert(div > 0U);
1940
1941 CGC_LPAV->CLKOUTCFG = CGC_LPAV_CLKOUTCFG_CLKOUT_SEL(setting) | CGC_LPAV_CLKOUTCFG_CLKOUT_DIV((uint32_t)div - 1U) |
1942 (enable ? CGC_LPAV_CLKOUTCFG_CLKOUT_EN_MASK : 0U);
1943 }
1944 /* @} */
1945
1946 /*!
1947 * @name CGC System OSC Clock.
1948 * @{
1949 */
1950
1951 /*!
1952 * @brief Initializes the CGC system OSC.
1953 *
1954 * This function enables the CGC system OSC clock according to the
1955 * configuration.
1956 *
1957 * @param config Pointer to the configuration structure.
1958 * @retval kStatus_Success System OSC is initialized.
1959 * @retval kStatus_CGC_Busy System OSC has been enabled and is used by the system clock.
1960 * @retval kStatus_ReadOnly System OSC control register is locked.
1961 *
1962 * @note This function can't detect whether the system OSC has been enabled and
1963 * used by an IP.
1964 */
1965 status_t CLOCK_InitSysOsc(const cgc_sosc_config_t *config);
1966
1967 /*!
1968 * @brief De-initializes the CGC system OSC.
1969 *
1970 * This function disables the CGC system OSC clock.
1971 *
1972 * @retval kStatus_Success System OSC is deinitialized.
1973 * @retval kStatus_CGC_Busy System OSC is used by the system clock.
1974 * @retval kStatus_ReadOnly System OSC control register is locked.
1975 *
1976 * @note This function can't detect whether the system OSC is used by an IP.
1977 */
1978 status_t CLOCK_DeinitSysOsc(void);
1979
1980 /*!
1981 * @brief Set the asynchronous clock divider in RTD.
1982 *
1983 * @param asyncClk Which asynchronous clock to configure.
1984 * @param divider The divider value to set. Disabled when divider == 0.
1985 *
1986 * @note There might be glitch when changing the asynchronous divider, so make sure
1987 * the asynchronous clock is not used while changing divider.
1988 */
1989 void CLOCK_SetRtdSysOscAsyncClkDiv(cgc_async_clk_t asyncClk, uint8_t divider);
1990
1991 /*!
1992 * @brief Set the asynchronous clock divider in AD.
1993 *
1994 * @param asyncClk Which asynchronous clock to configure.
1995 * @param divider The divider value to set. Disabled when divider == 0.
1996 *
1997 * @note There might be glitch when changing the asynchronous divider, so make sure
1998 * the asynchronous clock is not used while changing divider.
1999 */
2000 void CLOCK_SetAdSysOscAsyncClkDiv(cgc_async_clk_t asyncClk, uint8_t divider);
2001
2002 /*!
2003 * @brief Set the asynchronous clock divider in LPAV.
2004 *
2005 * @param asyncClk Which asynchronous clock to configure.
2006 * @param divider The divider value to set. Disabled when divider == 0.
2007 *
2008 * @note There might be glitch when changing the asynchronous divider, so make sure
2009 * the asynchronous clock is not used while changing divider.
2010 */
2011 void CLOCK_SetLpavSysOscAsyncClkDiv(cgc_async_clk_t asyncClk, uint8_t divider);
2012
2013 /*!
2014 * @brief Gets the CGC system OSC clock frequency (SYSOSC).
2015 *
2016 * @return Clock frequency; If the clock is invalid, returns 0.
2017 */
2018 uint32_t CLOCK_GetSysOscFreq(void);
2019
2020 /*!
2021 * @brief Gets the CGC asynchronous clock frequency from the system OSC in RTD.
2022 *
2023 * @param type The asynchronous clock type.
2024 * @return Clock frequency; If the clock is invalid, returns 0.
2025 */
2026 uint32_t CLOCK_GetRtdSysOscAsyncFreq(cgc_async_clk_t type);
2027
2028 /*!
2029 * @brief Gets the CGC asynchronous clock frequency from the system OSC in AD.
2030 *
2031 * @param type The asynchronous clock type.
2032 * @return Clock frequency; If the clock is invalid, returns 0.
2033 */
2034 uint32_t CLOCK_GetAdSysOscAsyncFreq(cgc_async_clk_t type);
2035
2036 /*!
2037 * @brief Gets the CGC asynchronous clock frequency from the system OSC in LPAV.
2038 *
2039 * @param type The asynchronous clock type.
2040 * @return Clock frequency; If the clock is invalid, returns 0.
2041 */
2042 uint32_t CLOCK_GetLpavSysOscAsyncFreq(cgc_async_clk_t type);
2043
2044 /*!
2045 * @brief Checks whether the system OSC clock error occurs.
2046 *
2047 * @return True if the error occurs, false if not.
2048 */
CLOCK_IsSysOscErr(void)2049 static inline bool CLOCK_IsSysOscErr(void)
2050 {
2051 return ((CGC_RTD->SOSCCSR & CGC_SOSCCSR_SOSCERR_MASK) == CGC_SOSCCSR_SOSCERR_MASK);
2052 }
2053
2054 /*!
2055 * @brief Clears the system OSC clock error.
2056 */
CLOCK_ClearSysOscErr(void)2057 static inline void CLOCK_ClearSysOscErr(void)
2058 {
2059 CGC_RTD->SOSCCSR |= CGC_SOSCCSR_SOSCERR_MASK;
2060 }
2061
2062 /*!
2063 * @brief Sets the system OSC monitor mode.
2064 *
2065 * This function sets the system OSC monitor mode. The mode can be disabled,
2066 * it can generate an interrupt when the error is disabled, or reset when the error is detected.
2067 *
2068 * @param mode Monitor mode to set.
2069 */
CLOCK_SetSysOscMonitorMode(cgc_sosc_monitor_mode_t mode)2070 static inline void CLOCK_SetSysOscMonitorMode(cgc_sosc_monitor_mode_t mode)
2071 {
2072 uint32_t reg = CGC_RTD->SOSCCSR;
2073
2074 reg &= ~(CGC_SOSCCSR_SOSCCM_MASK | CGC_SOSCCSR_SOSCCMRE_MASK);
2075
2076 reg |= (uint32_t)mode;
2077
2078 CGC_RTD->SOSCCSR = reg;
2079 }
2080
2081 /*!
2082 * @brief Checks whether the system OSC clock is used as clock source.
2083 *
2084 * @return True if system OSC is used as clock source, false if not.
2085 */
CLOCK_IsSysOscSelected(void)2086 static inline bool CLOCK_IsSysOscSelected(void)
2087 {
2088 return ((CGC_RTD->SOSCCSR & CGC_SOSCCSR_SOSCSEL_MASK) == CGC_SOSCCSR_SOSCSEL_MASK);
2089 }
2090
2091 /*!
2092 * @brief Checks whether the system OSC clock is valid.
2093 *
2094 * @return True if clock is valid, false if not.
2095 */
CLOCK_IsSysOscValid(void)2096 static inline bool CLOCK_IsSysOscValid(void)
2097 {
2098 return ((CGC_RTD->SOSCCSR & CGC_SOSCCSR_SOSCVLD_MASK) == CGC_SOSCCSR_SOSCVLD_MASK);
2099 }
2100 /* @} */
2101
2102 /*!
2103 * @name CGC FRO Clock.
2104 * @{
2105 */
2106
2107 /*!
2108 * @brief Initializes the CGC FRO clock.
2109 *
2110 * This function initializes the CGC FRO clock according to the
2111 * configuration.
2112 *
2113 * @param config Pointer to the configuration structure.
2114 * @retval kStatus_Success FRO is initialized.
2115 * @retval kStatus_CGC_Busy FRO has been enabled and is used by system clock.
2116 * @retval kStatus_ReadOnly FRO control register is locked.
2117 *
2118 * @note This function can't detect whether the FRO has been enabled and
2119 * used by an IP.
2120 */
2121 status_t CLOCK_InitFro(const cgc_fro_config_t *config);
2122
2123 /*!
2124 * @brief De-initializes the CGC FRO.
2125 *
2126 * This function deinitializes the CGC FRO.
2127 *
2128 * @retval kStatus_Success FRO is deinitialized.
2129 * @retval kStatus_CGC_Busy FRO is used by system clock.
2130 * @retval kStatus_ReadOnly FRO control register is locked.
2131 *
2132 * @note This function can't detect whether the FRO is used by an IP.
2133 */
2134 status_t CLOCK_DeinitFro(void);
2135
2136 /*!
2137 * @brief Set the asynchronous clock divider in RTD.
2138 *
2139 * @param asyncClk Which asynchronous clock to configure.
2140 * @param divider The divider value to set. Disabled when divider == 0.
2141 *
2142 * @note There might be glitch when changing the asynchronous divider, so make sure
2143 * the asynchronous clock is not used while changing divider.
2144 */
2145 void CLOCK_SetRtdFroAsyncClkDiv(cgc_async_clk_t asyncClk, uint8_t divider);
2146
2147 /*!
2148 * @brief Set the asynchronous clock divider in AD.
2149 *
2150 * @param asyncClk Which asynchronous clock to configure.
2151 * @param divider The divider value to set. Disabled when divider == 0.
2152 *
2153 * @note There might be glitch when changing the asynchronous divider, so make sure
2154 * the asynchronous clock is not used while changing divider.
2155 */
2156 void CLOCK_SetAdFroAsyncClkDiv(cgc_async_clk_t asyncClk, uint8_t divider);
2157
2158 /*!
2159 * @brief Set the asynchronous clock divider in LPAV.
2160 *
2161 * @param asyncClk Which asynchronous clock to configure.
2162 * @param divider The divider value to set. Disabled when divider == 0.
2163 *
2164 * @note There might be glitch when changing the asynchronous divider, so make sure
2165 * the asynchronous clock is not used while changing divider.
2166 */
2167 void CLOCK_SetLpavFroAsyncClkDiv(cgc_async_clk_t asyncClk, uint8_t divider);
2168
2169 /*! @brief Enable/Disable FRO tuning.
2170 * On enable, the function will wait until FRO is close to the target frequency.
2171 */
2172 void CLOCK_EnableFroTuning(bool enable);
2173
2174 /*!
2175 * @brief Gets the CGC FRO clock frequency.
2176 *
2177 * @return Clock frequency; If the clock is invalid, returns 0.
2178 */
2179 uint32_t CLOCK_GetFroFreq(void);
2180
2181 /*!
2182 * @brief Gets the CGC asynchronous clock frequency from the FRO in RTD.
2183 *
2184 * @param type The asynchronous clock type.
2185 * @return Clock frequency; If the clock is invalid, returns 0.
2186 */
2187 uint32_t CLOCK_GetRtdFroAsyncFreq(cgc_async_clk_t type);
2188
2189 /*!
2190 * @brief Gets the CGC asynchronous clock frequency from the FRO in AD.
2191 *
2192 * @param type The asynchronous clock type.
2193 * @return Clock frequency; If the clock is invalid, returns 0.
2194 */
2195 uint32_t CLOCK_GetAdFroAsyncFreq(cgc_async_clk_t type);
2196
2197 /*!
2198 * @brief Gets the CGC asynchronous clock frequency from the FRO in LPAV.
2199 *
2200 * @param type The asynchronous clock type.
2201 * @return Clock frequency; If the clock is invalid, returns 0.
2202 */
2203 uint32_t CLOCK_GetLpavFroAsyncFreq(cgc_async_clk_t type);
2204
2205 /*!
2206 * @brief Checks whether the FRO clock is used as clock source.
2207 *
2208 * @return True if FRO is used as clock source, false if not.
2209 */
CLOCK_IsFroSelected(void)2210 static inline bool CLOCK_IsFroSelected(void)
2211 {
2212 return ((CGC_RTD->FROCSR & CGC_FROCSR_FROSEL_MASK) == CGC_FROCSR_FROSEL_MASK);
2213 }
2214
2215 /*!
2216 * @brief Checks whether the FRO clock is valid.
2217 *
2218 * @return True if clock is valid, false if not.
2219 */
CLOCK_IsFroValid(void)2220 static inline bool CLOCK_IsFroValid(void)
2221 {
2222 return ((CGC_RTD->FROCSR & CGC_FROCSR_FROVLD_MASK) == CGC_FROCSR_FROVLD_MASK);
2223 }
2224 /* @} */
2225
2226 /*!
2227 * @name CGC LPOSC Clock.
2228 * @{
2229 */
2230
2231 /*!
2232 * @brief Initializes the CGC LPOSC clock.
2233 *
2234 * This function initializes the CGC LPOSC clock according to the
2235 * configuration.
2236 *
2237 * @param config Pointer to the configuration structure.
2238 * @retval kStatus_Success LPOSC is initialized.
2239 * @retval kStatus_ReadOnly FRO control register is locked.
2240 *
2241 * @note This function can't detect whether the LPOSC has been enabled and
2242 * used by an IP.
2243 */
2244 status_t CLOCK_InitLposc(const cgc_lposc_config_t *config);
2245
2246 /*!
2247 * @brief De-initializes the CGC LPOSC.
2248 *
2249 * This function deinitializes the CGC LPOSC.
2250 *
2251 * @retval kStatus_Success LPOSC is deinitialized.
2252 * @retval kStatus_ReadOnly LPOSC control register is locked.
2253 *
2254 * @note This function can't detect whether the LPOSC is used by an IP.
2255 */
2256 status_t CLOCK_DeinitLposc(void);
2257
2258 /*!
2259 * @brief Checks whether the LPOSC clock is valid.
2260 *
2261 * @return True if clock is valid, false if not.
2262 */
CLOCK_IsLpOscValid(void)2263 static inline bool CLOCK_IsLpOscValid(void)
2264 {
2265 return ((CGC_RTD->LPOSCCSR & CGC_LPOSCCSR_LPOSCVLD_MASK) == CGC_LPOSCCSR_LPOSCVLD_MASK);
2266 }
2267
2268 /*!
2269 * @brief Gets the CGC LPOSC clock frequency.
2270 *
2271 * @return Clock frequency; If the clock is invalid, returns 0.
2272 */
2273 uint32_t CLOCK_GetLpOscFreq(void);
2274 /* @} */
2275
2276 /*!
2277 * @name CGC RTCOSC Clock.
2278 * @{
2279 */
2280
2281 /*!
2282 * @brief Gets the CGC RTC OSC clock frequency.
2283 *
2284 * @return Clock frequency; If the clock is invalid, returns 0.
2285 */
2286 uint32_t CLOCK_GetRtcOscFreq(void);
2287
2288 /*!
2289 * @brief Checks whether the RTC OSC clock error occurs.
2290 *
2291 * @return True if error occurs, false if not.
2292 */
CLOCK_IsRtcOscErr(void)2293 static inline bool CLOCK_IsRtcOscErr(void)
2294 {
2295 return ((CGC_RTD->ROSCCTRL & CGC_ROSCCTRL_ROSCERR_MASK) == CGC_ROSCCTRL_ROSCERR_MASK);
2296 }
2297
2298 /*!
2299 * @brief Clears the RTC OSC clock error.
2300 */
CLOCK_ClearRtcOscErr(void)2301 static inline void CLOCK_ClearRtcOscErr(void)
2302 {
2303 CGC_RTD->ROSCCTRL |= CGC_ROSCCTRL_ROSCERR_MASK;
2304 }
2305
2306 /*!
2307 * @brief Sets the RTC OSC monitor mode.
2308 *
2309 * This function sets the RTC OSC monitor mode. The mode can be disabled.
2310 * It can generate an interrupt when the error is disabled, or reset when the error is detected.
2311 *
2312 * @param mode Monitor mode to set.
2313 */
2314 void CLOCK_SetRtcOscMonitorMode(cgc_rosc_monitor_mode_t mode);
2315
2316 /*!
2317 * @brief Checks whether the RTCOSC clock is used as clock source.
2318 *
2319 * @return True if RTCOSC is used as clock source, false if not.
2320 */
CLOCK_IsRtcOscSelected(void)2321 static inline bool CLOCK_IsRtcOscSelected(void)
2322 {
2323 return ((CGC_RTD->ROSCCTRL & CGC_ROSCCTRL_ROSCSEL_MASK) == CGC_ROSCCTRL_ROSCSEL_MASK);
2324 }
2325
2326 /*!
2327 * @brief Checks whether the RTC OSC clock is valid.
2328 *
2329 * @return True if the clock is valid, false if not.
2330 */
CLOCK_IsRtcOscValid(void)2331 static inline bool CLOCK_IsRtcOscValid(void)
2332 {
2333 return ((CGC_RTD->ROSCCTRL & CGC_ROSCCTRL_ROSCVLD_MASK) == CGC_ROSCCTRL_ROSCVLD_MASK);
2334 }
2335 /* @} */
2336
2337 /*!
2338 * @name CGC PLL0 Clock.
2339 * @{
2340 */
2341
2342 /*!
2343 * @brief Initializes the CGC PLL0.
2344 *
2345 * This function enables the CGC PLL0 clock according to the
2346 * configuration. The PLL0 can use the OSC or FRO as
2347 * the clock source. Ensure that the source clock is valid before
2348 * calling this function.
2349 *
2350 * Example code for initializing PLL0 clock output:
2351 * @code
2352 * const cgc_pll0_config_t g_cgcPll0Config = {.enableMode = kCGC_PllEnable,
2353 * .div1 = 1U,
2354 * .pfd1Div = 2U,
2355 * .pfd2Div = 0U,
2356 * .src = kCGC_PllSrcSysOsc,
2357 * .mult = kCGC_Pll0Mult20};
2358 * CLOCK_InitPll0(&g_cgcPll0Config);
2359 * @endcode
2360 *
2361 * @param config Pointer to the configuration structure.
2362 * @retval kStatus_Success PLL0 is initialized.
2363 * @retval kStatus_CGC_Busy PLL0 has been enabled and is used by the system clock.
2364 * @retval kStatus_ReadOnly PLL0 control register is locked.
2365 *
2366 * @note This function can't detect whether the PLL0 has been enabled and
2367 * used by an IP.
2368 */
2369 status_t CLOCK_InitPll0(const cgc_pll0_config_t *config);
2370
2371 /*!
2372 * @brief De-initializes the CGC PLL0.
2373 *
2374 * This function disables the CGC PLL0.
2375 *
2376 * @retval kStatus_Success PLL0 is deinitialized.
2377 * @retval kStatus_CGC_Busy PLL0 is used by the system clock.
2378 * @retval kStatus_ReadOnly PLL0 control register is locked.
2379 *
2380 * @note This function can't detect whether the PLL0 is used by an IP.
2381 */
2382 status_t CLOCK_DeinitPll0(void);
2383
2384 /*!
2385 * @brief Set the asynchronous clock divider.
2386 *
2387 * @param asyncClk Which asynchronous clock to configure.
2388 * @param divider The divider value to set. Disabled when divider == 0.
2389 *
2390 * @note There might be glitch when changing the asynchronous divider, so make sure
2391 * the asynchronous clock is not used while changing divider.
2392 */
2393 void CLOCK_SetPll0AsyncClkDiv(cgc_async_clk_t asyncClk, uint8_t divider);
2394
2395 /*!
2396 * @brief Gets the CGC PLL0 clock frequency.
2397 *
2398 * @return Clock frequency; If the clock is invalid, returns 0.
2399 */
2400 uint32_t CLOCK_GetPll0Freq(void);
2401
2402 /*!
2403 * @brief Gets the CGC asynchronous clock frequency from the PLL0.
2404 *
2405 * @param type The asynchronous clock type.
2406 * @return Clock frequency; If the clock is invalid, returns 0.
2407 */
2408 uint32_t CLOCK_GetPll0AsyncFreq(cgc_async_clk_t type);
2409
2410 /*!
2411 * @brief Gets the CGC PLL0 PFD clock frequency.
2412 *
2413 * @param pfdClkout The selected PFD clock out. See "cgc_pll_pfd_clkout_t".
2414 * @return Clock frequency; If the clock is invalid, returns 0.
2415 */
2416 uint32_t CLOCK_GetPll0PfdFreq(cgc_pll_pfd_clkout_t pfdClkout);
2417
2418 /*!
2419 * @brief Enables the CGC PLL0 Fractional Divide (PFD) clock out with configurations.
2420 *
2421 * PLL Frequency = Fref * MULT
2422 * PFD Clock Frequency = PLL output frequency * 18/frac value
2423 *
2424 * @code
2425 * Example code for configuring PLL0 PFD0 clock output:
2426 * const cgc_pll0_config_t g_cgcPll0Config = {.enableMode = kCGC_PllEnable,
2427 * .div1 = 1U,
2428 * .pfd1Div = 2U,
2429 * .pfd2Div = 0U,
2430 * .src = kCGC_PllSrcSysOsc,
2431 * .mult = kCGC_Pll0Mult20};
2432 * CLOCK_InitPll0(&g_cgcPll0Config);
2433 * CLOCK_EnablePll0PfdClkout(kCGC_PllPfd0Clk, 15U);
2434 * @endcode
2435 *
2436 * @param pfdClkout PLL0 PFD clock out select.
2437 * @param fracValue Fractional Divider value. Recommended to be kept between 12-35 for all PFDs.
2438 */
2439 void CLOCK_EnablePll0PfdClkout(cgc_pll_pfd_clkout_t pfdClkout, uint8_t fracValue);
2440
2441 /*!
2442 * @brief Disables the CGC PLL0 Fractional Divide (PFD) clock out.
2443 */
CLOCK_DisablePll0PfdClkout(cgc_pll_pfd_clkout_t pfdClkout)2444 static inline void CLOCK_DisablePll0PfdClkout(cgc_pll_pfd_clkout_t pfdClkout)
2445 {
2446 CGC_RTD->PLL0PFDCFG |= CGC_PLLPFD_PFD_CLKGATE_MASK(pfdClkout);
2447 }
2448
2449 /*!
2450 * @brief Sets the CGC PLL0 lock time.
2451 *
2452 * @param lockTime Reference clocks to count before PLL0 is considered locked and valid.
2453 */
CLOCK_SetPll0LockTime(uint16_t lockTime)2454 static inline void CLOCK_SetPll0LockTime(uint16_t lockTime)
2455 {
2456 CGC_RTD->PLL0LOCK = CGC_PLL0LOCK_LOCK_TIME(lockTime);
2457 }
2458
2459 /*!
2460 * @brief Checks whether the PLL0 clock is used as clock source.
2461 *
2462 * @return True if PLL0 is used as clock source, false if not.
2463 */
CLOCK_IsPll0Selected(void)2464 static inline bool CLOCK_IsPll0Selected(void)
2465 {
2466 return ((CGC_RTD->PLL0CSR & CGC_PLL0CSR_PLLSEL_MASK) == CGC_PLL0CSR_PLLSEL_MASK);
2467 }
2468
2469 /*!
2470 * @brief Checks whether the PLL0 clock is valid.
2471 *
2472 * @return True if the clock is valid, false if not.
2473 */
CLOCK_IsPll0Valid(void)2474 static inline bool CLOCK_IsPll0Valid(void)
2475 {
2476 return ((CGC_RTD->PLL0CSR & CGC_PLL0CSR_PLLVLD_MASK) == CGC_PLL0CSR_PLLVLD_MASK);
2477 }
2478 /* @} */
2479
2480 /*!
2481 * @name CGC PLL1 Clock.
2482 * @{
2483 */
2484
2485 /*!
2486 * @brief Initializes the CGC PLL1.
2487 *
2488 * This function enables the CGC PLL1 clock according to the
2489 * configuration. The PLL1 can use the system OSC or FRO as
2490 * the clock source. Ensure that the source clock is valid before
2491 * calling this function.
2492 *
2493 * Example code for initializing PLL1 clock output:
2494 * @code
2495 * const cgc_pll1_config_t g_cgcPll1Config = {.enableMode = kCGC_PllEnable,
2496 * .div1 = 0U,
2497 * .pfd1Div = 0U,
2498 * .pfd2Div = 0U,
2499 * .src = kCGC_PllSrcFro24M,
2500 * .mult = kCGC_Pll1Mult22,
2501 * .num = 578,
2502 * .denom = 1000};
2503 * CLOCK_InitPll1(&g_cgcPll1Config);
2504 * @endcode
2505 *
2506 * @param config Pointer to the configuration structure.
2507 * @retval kStatus_Success PLL1 is initialized.
2508 * @retval kStatus_CGC_Busy PLL1 has been enabled and is used by the system clock.
2509 * @retval kStatus_ReadOnly PLL1 control register is locked.
2510 *
2511 * @note This function can't detect whether the PLL1 has been enabled and
2512 * is used by an IP.
2513 */
2514 status_t CLOCK_InitPll1(const cgc_pll1_config_t *config);
2515
2516 /*!
2517 * @brief De-initializes the CGC PLL1.
2518 *
2519 * This function disables the CGC PLL1.
2520 *
2521 * @retval kStatus_Success PLL1 is deinitialized.
2522 * @retval kStatus_CGC_Busy PLL1 is used by the system clock.
2523 * @retval kStatus_ReadOnly PLL1 control register is locked.
2524 *
2525 * @note This function can't detect whether the PLL1 is used by an IP.
2526 */
2527 status_t CLOCK_DeinitPll1(void);
2528
2529 /*!
2530 * @brief Set the asynchronous clock divider.
2531 *
2532 * @param asyncClk Which asynchronous clock to configure.
2533 * @param divider The divider value to set. Disabled when divider == 0.
2534 *
2535 * @note There might be glitch when changing the asynchronous divider, so make sure
2536 * the asynchronous clock is not used while changing divider.
2537 */
2538 void CLOCK_SetPll1AsyncClkDiv(cgc_async_clk_t asyncClk, uint8_t divider);
2539
2540 /*!
2541 * @brief Gets the CGC PLL1 clock frequency.
2542 *
2543 * @return Clock frequency; If the clock is invalid, returns 0.
2544 */
2545 uint32_t CLOCK_GetPll1Freq(void);
2546
2547 /*!
2548 * @brief Gets the CGC asynchronous clock frequency from the PLL1.
2549 *
2550 * @param type The asynchronous clock type.
2551 * @return Clock frequency; If the clock is invalid, returns 0.
2552 */
2553 uint32_t CLOCK_GetPll1AsyncFreq(cgc_async_clk_t type);
2554
2555 /*!
2556 * @brief Gets the CGC PLL1 PFD clock frequency.
2557 *
2558 * @param pfdClkout The selected PFD clocks out. See "cgc_pll_pfd_clkout_t".
2559 * @return Clock frequency; If the clock is invalid, returns 0.
2560 */
2561 uint32_t CLOCK_GetPll1PfdFreq(cgc_pll_pfd_clkout_t pfdClkout);
2562
2563 /*!
2564 * @brief Enables the CGC PLL1 Fractional Divide (PFD) clock out with configurations.
2565 *
2566 * PLL1 Frequency = Fref * (MULT + NUM/DENOM)
2567 * PFD Clock Frequency = PLL output frequency * 18/frac value
2568 *
2569 * Example code for configuring PLL1 as PLL1 PFD clock output:
2570 * @code
2571 * const cgc_pll1_config_t g_cgcPll1Config = {.enableMode = kCGC_PllEnable,
2572 * .div1 = 0U,
2573 * .pfd1Div = 0U,
2574 * .pfd2Div = 0U,
2575 * .src = kCGC_PllSrcFro24M,
2576 * .mult = kCGC_Pll1Mult22,
2577 * .num = 578,
2578 * .denom = 1000};
2579 * CLOCK_InitPll1(&g_cgcPll1Config);
2580 * CLOCK_EnablePll1PfdClkout(kCGC_PllPfd0Clk, 15U);
2581 * @endcode
2582 *
2583 * @param pfdClkout PLL1 PFD clock out select.
2584 * @param fracValue Fractional Divider value. Recommended to be kept between 12-35 for all PFDs.
2585 */
2586 void CLOCK_EnablePll1PfdClkout(cgc_pll_pfd_clkout_t pfdClkout, uint8_t fracValue);
2587
2588 /*!
2589 * @brief Disables the CGC PLL1 Fractional Divide (PFD) clock out.
2590 */
CLOCK_DisablePll1PfdClkout(cgc_pll_pfd_clkout_t pfdClkout)2591 static inline void CLOCK_DisablePll1PfdClkout(cgc_pll_pfd_clkout_t pfdClkout)
2592 {
2593 CGC_RTD->PLL1PFDCFG |= CGC_PLLPFD_PFD_CLKGATE_MASK(pfdClkout);
2594 }
2595
2596 /*!
2597 * @brief Enables the CGC PLL1 spread spectrum modulation feature with configurations.
2598 *
2599 * This function sets the CGC PLL1 spread spectrum modulation configurations.
2600 * STOP and STEP together control the modulation depth (maximum frequency change)
2601 * and modulation frequency.
2602 *
2603 * Modulation Depth = (STOP/MFD)*Fref where MFD is the DENOM field value in DENOM register.
2604 * Modulation Frequency = (STEP/(2*STOP))*Fref.
2605 *
2606 * @param step PLL1 Spread Spectrum STEP.
2607 * @param stop PLL1 Spread Spectrum STOP.
2608 */
CLOCK_EnablePll1SpectrumModulation(uint16_t step,uint16_t stop)2609 static inline void CLOCK_EnablePll1SpectrumModulation(uint16_t step, uint16_t stop)
2610 {
2611 CGC_RTD->PLL1SS = (CGC_RTD->PLL1SS & ~(CGC_PLL1SS_STEP_MASK | CGC_PLL1SS_STOP_MASK)) |
2612 (CGC_PLL1SS_STEP(step) | CGC_PLL1SS_STOP(stop) | CGC_PLL1SS_ENABLE_MASK);
2613 }
2614
2615 /*!
2616 * @brief Disables the CGC PLL1 spread spectrum modulation.
2617 *
2618 */
CLOCK_DisablePll1SpectrumModulation(void)2619 static inline void CLOCK_DisablePll1SpectrumModulation(void)
2620 {
2621 CGC_RTD->PLL1SS &= ~CGC_PLL1SS_ENABLE_MASK;
2622 }
2623
2624 /*!
2625 * @brief Sets the CGC PLL1 lock time.
2626 *
2627 * @param lockTime Reference clocks to count before PLL1 is considered locked and valid.
2628 */
CLOCK_SetPll1LockTime(uint16_t lockTime)2629 static inline void CLOCK_SetPll1LockTime(uint16_t lockTime)
2630 {
2631 CGC_RTD->PLL1LOCK = CGC_PLL1LOCK_LOCK_TIME(lockTime);
2632 }
2633
2634 /*!
2635 * @brief Checks whether the PLL1 clock is used as clock source.
2636 *
2637 * @return True if PLL1 is used as clock source, false if not.
2638 */
CLOCK_IsPll1Selected(void)2639 static inline bool CLOCK_IsPll1Selected(void)
2640 {
2641 return ((CGC_RTD->PLL1CSR & CGC_PLL1CSR_PLLSEL_MASK) == CGC_PLL1CSR_PLLSEL_MASK);
2642 }
2643
2644 /*!
2645 * @brief Checks whether the PLL1 clock is valid.
2646 *
2647 * @return True if the clock is valid, false if not.
2648 */
CLOCK_IsPll1Valid(void)2649 static inline bool CLOCK_IsPll1Valid(void)
2650 {
2651 return ((CGC_RTD->PLL1CSR & CGC_PLL1CSR_PLLVLD_MASK) == CGC_PLL1CSR_PLLVLD_MASK);
2652 }
2653 /* @} */
2654
2655 /*!
2656 * @name CGC PLL3 Clock.
2657 * @{
2658 */
2659
2660 /*!
2661 * @brief Gets the CGC PLL3 clock frequency.
2662 *
2663 * @return Clock frequency; If the clock is invalid, returns 0.
2664 */
2665 uint32_t CLOCK_GetPll3Freq(void);
2666
2667 /*!
2668 * @brief Gets the CGC asynchronous clock frequency from the PLL3.
2669 *
2670 * @param type The asynchronous clock type.
2671 * @return Clock frequency; If the clock is invalid, returns 0.
2672 */
2673 uint32_t CLOCK_GetPll3AsyncFreq(cgc_async_clk_t type);
2674
2675 /*!
2676 * @brief Gets the CGC PLL3 PFD clock frequency.
2677 *
2678 * @param pfdClkout The selected PFD clock out. See "cgc_pll_pfd_clkout_t".
2679 * @return Clock frequency; If the clock is invalid, returns 0.
2680 */
2681 uint32_t CLOCK_GetPll3PfdFreq(cgc_pll_pfd_clkout_t pfdClkout);
2682 /* @} */
2683
2684 /*!
2685 * @name CGC PLL4 Clock.
2686 * @{
2687 */
2688
2689 /*!
2690 * @brief Initializes the CGC PLL4.
2691 *
2692 * This function enables the CGC PLL4 clock according to the
2693 * configuration. The PLL4 can use the OSC or FRO as
2694 * the clock source. Ensure that the source clock is valid before
2695 * calling this function.
2696 *
2697 * Example code for initializing PLL4 clock output:
2698 * @code
2699 * const cgc_pll4_config_t g_cgcPll4Config = {.enableMode = kCGC_PllEnable,
2700 * .div1 = 0U,
2701 * .pfd0Div1 = 0U,
2702 * .pfd0Div2 = 0U,
2703 * .pfd1Div1 = 0U,
2704 * .pfd1Div2 = 0U,
2705 * .pfd2Div1 = 0U,
2706 * .pfd2Div2 = 0U,
2707 * .pfd3Div1 = 0U,
2708 * .pfd3Div2 = 0U,
2709 * .src = kCGC_PllSrcFro24M,
2710 * .mult = kCGC_Pll4Mult22,
2711 * .num = 578,
2712 * .denom = 1000};
2713 * CLOCK_InitPll4(&g_cgcPll4Config);
2714 * @endcode
2715 *
2716 * @param config Pointer to the configuration structure.
2717 * @retval kStatus_Success PLL4 is initialized.
2718 * @retval kStatus_CGC_Busy PLL4 has been enabled and is used by the system clock.
2719 * @retval kStatus_ReadOnly PLL4 control register is locked.
2720 *
2721 * @note This function can't detect whether the PLL4 has been enabled and
2722 * used by an IP.
2723 */
2724 status_t CLOCK_InitPll4(const cgc_pll4_config_t *config);
2725
2726 /*!
2727 * @brief De-initializes the CGC PLL4.
2728 *
2729 * This function disables the CGC PLL4.
2730 *
2731 * @retval kStatus_Success PLL4 is deinitialized.
2732 * @retval kStatus_CGC_Busy PLL4 is used by the system clock.
2733 * @retval kStatus_ReadOnly PLL4 control register is locked.
2734 *
2735 * @note This function can't detect whether the PLL4 is used by an IP.
2736 */
2737 status_t CLOCK_DeinitPll4(void);
2738
2739 /*!
2740 * @brief Set the asynchronous clock divider.
2741 *
2742 * @param asyncClk Which asynchronous clock to configure.
2743 * @param divider The divider value to set. Disabled when divider == 0.
2744 *
2745 * @note There might be glitch when changing the asynchronous divider, so make sure
2746 * the asynchronous clock is not used while changing divider.
2747 */
2748 void CLOCK_SetPll4AsyncClkDiv(cgc_async_clk_t asyncClk, uint8_t divider);
2749
2750 /*!
2751 * @brief Gets the CGC PLL4 clock frequency.
2752 *
2753 * @return Clock frequency; If the clock is invalid, returns 0.
2754 */
2755 uint32_t CLOCK_GetPll4Freq(void);
2756
2757 /*!
2758 * @brief Gets the CGC asynchronous clock frequency from the PLL4.
2759 *
2760 * @param type The asynchronous clock type.
2761 * @return Clock frequency; If the clock is invalid, returns 0.
2762 */
2763 uint32_t CLOCK_GetPll4AsyncFreq(cgc_async_clk_t type);
2764
2765 /*!
2766 * @brief Gets the CGC PLL4 PFD clock frequency.
2767 *
2768 * @param pfdClkout The selected PFD clock out. See "cgc_pll_pfd_clkout_t".
2769 * @return Clock frequency; If the clock is invalid, returns 0.
2770 */
2771 uint32_t CLOCK_GetPll4PfdFreq(cgc_pll_pfd_clkout_t pfdClkout);
2772
2773 /*!
2774 * @brief Enables the CGC PLL4 Fractional Divide (PFD) clock out with configurations.
2775 *
2776 * PLL Frequency = Fref * MULT
2777 * PFD Clock Frequency = PLL output frequency * 18/frac value
2778 *
2779 * @code
2780 * Example code for configuring PLL4 PFD0 clock output:
2781 * const cgc_pll4_config_t g_cgcPll4Config = {.enableMode = kCGC_PllEnable,
2782 * .div1 = 0U,
2783 * .pfd0Div1 = 0U,
2784 * .pfd0Div2 = 0U,
2785 * .pfd1Div1 = 0U,
2786 * .pfd1Div2 = 0U,
2787 * .pfd2Div1 = 0U,
2788 * .pfd2Div2 = 0U,
2789 * .pfd3Div1 = 0U,
2790 * .pfd3Div2 = 0U,
2791 * .src = kCGC_PllSrcFro24M,
2792 * .mult = kCGC_Pll4Mult22,
2793 * .num = 578,
2794 * .denom = 1000};
2795 * CLOCK_InitPll4(&g_cgcPll4Config);
2796 * CLOCK_EnablePll4PfdClkout(kCGC_PllPfd0Clk, 15U);
2797 * @endcode
2798 *
2799 * @param pfdClkout PLL4 PFD clock out select.
2800 * @param fracValue Fractional Divider value. Recommended to be kept between 12-35 for all PFDs.
2801 */
2802 void CLOCK_EnablePll4PfdClkout(cgc_pll_pfd_clkout_t pfdClkout, uint8_t fracValue);
2803
2804 /*!
2805 * @brief Disables the CGC PLL4 Fractional Divide (PFD) clock out.
2806 */
CLOCK_DisablePll4PfdClkout(cgc_pll_pfd_clkout_t pfdClkout)2807 static inline void CLOCK_DisablePll4PfdClkout(cgc_pll_pfd_clkout_t pfdClkout)
2808 {
2809 CGC_LPAV->PLL4PFDCFG |= CGC_PLLPFD_PFD_CLKGATE_MASK(pfdClkout);
2810 }
2811
2812 /*!
2813 * @brief Enables the CGC PLL4 spread spectrum modulation feature with configurations.
2814 *
2815 * This function sets the CGC PLL4 spread spectrum modulation configurations.
2816 * STOP and STEP together control the modulation depth (maximum frequency change)
2817 * and modulation frequency.
2818 *
2819 * Modulation Depth = (STOP/MFD)*Fref where MFD is the DENOM field value in DENOM register.
2820 * Modulation Frequency = (STEP/(2*STOP))*Fref.
2821 *
2822 * @param step PLL4 Spread Spectrum STEP.
2823 * @param stop PLL4 Spread Spectrum STOP.
2824 */
CLOCK_EnablePll4SpectrumModulation(uint16_t step,uint16_t stop)2825 static inline void CLOCK_EnablePll4SpectrumModulation(uint16_t step, uint16_t stop)
2826 {
2827 CGC_LPAV->PLL4SS = (CGC_LPAV->PLL4SS & ~(CGC_LPAV_PLL4SS_STEP_MASK | CGC_LPAV_PLL4SS_STOP_MASK)) |
2828 (CGC_LPAV_PLL4SS_STEP(step) | CGC_LPAV_PLL4SS_STOP(stop) | CGC_LPAV_PLL4SS_ENABLE_MASK);
2829 }
2830 /*!
2831 * @brief Sets the CGC PLL4 lock time.
2832 *
2833 * @param lockTime Reference clocks to count before PLL4 is considered locked and valid.
2834 */
CLOCK_SetPll4LockTime(uint16_t lockTime)2835 static inline void CLOCK_SetPll4LockTime(uint16_t lockTime)
2836 {
2837 CGC_LPAV->PLL4LOCK = CGC_LPAV_PLL4LOCK_LOCK_TIME(lockTime);
2838 }
2839
2840 /*!
2841 * @brief Checks whether the PLL4 clock is used as clock source.
2842 *
2843 * @return True if PLL4 is used as clock source, false if not.
2844 */
CLOCK_IsPll4Selected(void)2845 static inline bool CLOCK_IsPll4Selected(void)
2846 {
2847 return ((CGC_LPAV->PLL4CSR & CGC_LPAV_PLL4CSR_PLLSEL_MASK) == CGC_LPAV_PLL4CSR_PLLSEL_MASK);
2848 }
2849
2850 /*!
2851 * @brief Checks whether the PLL4 clock is valid.
2852 *
2853 * @return True if the clock is valid, false if not.
2854 */
CLOCK_IsPll4Valid(void)2855 static inline bool CLOCK_IsPll4Valid(void)
2856 {
2857 return ((CGC_LPAV->PLL4CSR & CGC_LPAV_PLL4CSR_PLLVLD_MASK) == CGC_LPAV_PLL4CSR_PLLVLD_MASK);
2858 }
2859 /* @} */
2860
2861 /*!
2862 * @name External clock frequency
2863 * @{
2864 */
2865
2866 /*!
2867 * @brief Sets the XTAL0 frequency based on board settings.
2868 *
2869 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
2870 */
CLOCK_SetXtal0Freq(uint32_t freq)2871 static inline void CLOCK_SetXtal0Freq(uint32_t freq)
2872 {
2873 g_xtal0Freq = freq;
2874 }
2875
2876 /*!
2877 * @brief Sets the XTAL32 frequency based on board settings.
2878 *
2879 * @param freq The XTAL32/EXTAL32 input clock frequency in Hz.
2880 */
CLOCK_SetXtal32Freq(uint32_t freq)2881 static inline void CLOCK_SetXtal32Freq(uint32_t freq)
2882 {
2883 g_xtal32Freq = freq;
2884 }
2885
2886 /*!
2887 * @brief Sets the LVDS pad frequency based on board settings.
2888 *
2889 * @param freq The LVDS pad input clock frequency in Hz.
2890 */
CLOCK_SetLvdsFreq(uint32_t freq)2891 static inline void CLOCK_SetLvdsFreq(uint32_t freq)
2892 {
2893 g_lvdsFreq = freq;
2894 }
2895
2896 /*!
2897 * @brief Sets the MCLK pad frequency based on Audio settings.
2898 *
2899 * @param index The MCLK index.
2900 * @param freq The MCLK pad input clock frequency in Hz.
2901 */
CLOCK_SetMclkFreq(uint32_t index,uint32_t freq)2902 static inline void CLOCK_SetMclkFreq(uint32_t index, uint32_t freq)
2903 {
2904 assert(index < ARRAY_SIZE(g_mclkFreq));
2905
2906 g_mclkFreq[index] = freq;
2907 }
2908
2909 /*!
2910 * @brief Sets the RX_BCLK pad frequency based on Audio settings.
2911 *
2912 * @param instance The SAI instance to contribute to this RX_BCLK pad.
2913 * @param freq The RX_BCLK pad input clock frequency in Hz.
2914 */
CLOCK_SetRxBclkFreq(uint32_t instance,uint32_t freq)2915 static inline void CLOCK_SetRxBclkFreq(uint32_t instance, uint32_t freq)
2916 {
2917 assert(instance < ARRAY_SIZE(g_rxBclkFreq));
2918
2919 g_rxBclkFreq[instance] = freq;
2920 }
2921
2922 /*!
2923 * @brief Sets the TX_BCLK pad frequency based on Audio settings.
2924 *
2925 * @param instance The SAI instance to contribute to this TX_BCLK pad.
2926 * @param freq The TX_BCLK pad input clock frequency in Hz.
2927 */
CLOCK_SetTxBclkFreq(uint32_t instance,uint32_t freq)2928 static inline void CLOCK_SetTxBclkFreq(uint32_t instance, uint32_t freq)
2929 {
2930 assert(instance < ARRAY_SIZE(g_txBclkFreq));
2931
2932 g_txBclkFreq[instance] = freq;
2933 }
2934
2935 /*!
2936 * @brief Sets the SPDIF_RX frequency based on Audio settings.
2937 *
2938 * @param freq The SPDIF_RX input clock frequency in Hz.
2939 */
CLOCK_SetSpdifRxFreq(uint32_t freq)2940 static inline void CLOCK_SetSpdifRxFreq(uint32_t freq)
2941 {
2942 g_spdifRxFreq = freq;
2943 }
2944
2945 /* @} */
2946
2947 /*!
2948 * @name Get peripheral frequency
2949 * @{
2950 */
2951
2952 /*!
2953 * @brief Gets the WDOG clock frequency in RTD and LPAV.
2954 *
2955 * @param instance The WDOG instance (0-2,5).
2956 * @return Clock frequency; If the clock is invalid, returns 0.
2957 */
2958 uint32_t CLOCK_GetWdogClkFreq(uint32_t instance);
2959
2960 /*!
2961 * @brief Gets the FlexSPI clock frequency in RTD.
2962 *
2963 * @param instance The FlexSPI instance (0-1).
2964 * @return Clock frequency; If the clock is invalid, returns 0.
2965 */
2966 uint32_t CLOCK_GetFlexspiClkFreq(uint32_t instance);
2967
2968 /*!
2969 * @brief Gets the LPIT clock frequency in RTD.
2970 *
2971 * @return Clock frequency; If the clock is invalid, returns 0.
2972 */
2973 uint32_t CLOCK_GetLpitClkFreq(void);
2974
2975 /*!
2976 * @brief Gets the FlexIO clock frequency in RTD.
2977 *
2978 * @return Clock frequency; If the clock is invalid, returns 0.
2979 */
2980 uint32_t CLOCK_GetFlexioClkFreq(void);
2981
2982 /*!
2983 * @brief Gets the I3C clock frequency in RTD and LPAV.
2984 *
2985 * @param instance The I3C instance (0-1).
2986 * @return Clock frequency; If the clock is invalid, returns 0.
2987 */
2988 uint32_t CLOCK_GetI3cClkFreq(uint32_t instance);
2989
2990 /*!
2991 * @brief Gets the LPSPI clock frequency in RTD.
2992 *
2993 * @param instance The LPSPI instance (0-3).
2994 * @return Clock frequency; If the clock is invalid, returns 0.
2995 */
2996 uint32_t CLOCK_GetLpspiClkFreq(uint32_t instance);
2997
2998 /*!
2999 * @brief Gets the ADC clock frequency.
3000 *
3001 * @param instance The ADC instance (0-1).
3002 * @return Clock frequency; If the clock is invalid, returns 0.
3003 */
3004 uint32_t CLOCK_GetAdcClkFreq(uint32_t instance);
3005
3006 /*!
3007 * @brief Gets the DAC clock frequency.
3008 *
3009 * @param instance The DAC instance (0-1).
3010 * @return Clock frequency; If the clock is invalid, returns 0.
3011 */
3012 uint32_t CLOCK_GetDacClkFreq(uint32_t instance);
3013
3014 /*!
3015 * @brief Gets the TPIU clock frequency.
3016 *
3017 * @return Clock frequency; If the clock is invalid, returns 0.
3018 */
3019 uint32_t CLOCK_GetTpiuClkFreq(void);
3020
3021 /*!
3022 * @brief Gets the SWO clock frequency.
3023 *
3024 * @return Clock frequency; If the clock is invalid, returns 0.
3025 */
3026 uint32_t CLOCK_GetSwoClkFreq(void);
3027
3028 /*!
3029 * @brief Gets the TPM clock frequency.
3030 *
3031 * @param instance The TPM instance (0-8).
3032 * @return Clock frequency; If the clock is invalid, returns 0.
3033 */
3034 uint32_t CLOCK_GetTpmClkFreq(uint32_t instance);
3035
3036 /*!
3037 * @brief Gets the LPI2C clock frequency in RTD.
3038 *
3039 * @param instance The LPI2C instance (0-3).
3040 * @return Clock frequency; If the clock is invalid, returns 0.
3041 */
3042 uint32_t CLOCK_GetLpi2cClkFreq(uint32_t instance);
3043
3044 /*!
3045 * @brief Gets the LPUART clock frequency in RTD.
3046 *
3047 * @param instance The LPUART instance (0-3).
3048 * @return Clock frequency; If the clock is invalid, returns 0.
3049 */
3050 uint32_t CLOCK_GetLpuartClkFreq(uint32_t instance);
3051
3052 /*!
3053 * @brief Gets the FlexCAN clock frequency.
3054 *
3055 * @return Clock frequency; If the clock is invalid, returns 0.
3056 */
3057 uint32_t CLOCK_GetFlexcanClkFreq(void);
3058
3059 /*!
3060 * @brief Gets the CSI clock frequency.
3061 *
3062 * @return Clock frequency; If the clock is invalid, returns 0.
3063 */
3064 uint32_t CLOCK_GetCsiClkFreq(void);
3065
3066 /*!
3067 * @brief Gets the DSI clock frequency.
3068 *
3069 * @return Clock frequency; If the clock is invalid, returns 0.
3070 */
3071 uint32_t CLOCK_GetDsiClkFreq(void);
3072
3073 /*!
3074 * @brief Gets the EPDC clock frequency.
3075 *
3076 * @return Clock frequency; If the clock is invalid, returns 0.
3077 */
3078 uint32_t CLOCK_GetEpdcClkFreq(void);
3079
3080 /*!
3081 * @brief Gets the GPU2D clock frequency.
3082 *
3083 * @return Clock frequency; If the clock is invalid, returns 0.
3084 */
3085 uint32_t CLOCK_GetGpu2dClkFreq(void);
3086
3087 /*!
3088 * @brief Gets the GPU3D clock frequency.
3089 *
3090 * @return Clock frequency; If the clock is invalid, returns 0.
3091 */
3092 uint32_t CLOCK_GetGpu3dClkFreq(void);
3093
3094 /*!
3095 * @brief Gets the DC Nano clock frequency.
3096 *
3097 * @return Clock frequency; If the clock is invalid, returns 0.
3098 */
3099 uint32_t CLOCK_GetDcnanoClkFreq(void);
3100
3101 /*!
3102 * @brief Gets the CSI clk_ui clock frequency.
3103 *
3104 * @return Clock frequency; If the clock is invalid, returns 0.
3105 */
3106 uint32_t CLOCK_GetCsiUiClkFreq(void);
3107
3108 /*!
3109 * @brief Gets the CSI clk_esc clock frequency.
3110 *
3111 * @return Clock frequency; If the clock is invalid, returns 0.
3112 */
3113 uint32_t CLOCK_GetCsiEscClkFreq(void);
3114
3115 /*!
3116 * @brief Gets the audio clock frequency in RTD.
3117 *
3118 * @return Clock frequency; If the clock is invalid, returns 0.
3119 */
3120 uint32_t CLOCK_GetRtdAudClkFreq(void);
3121
3122 /*!
3123 * @brief Gets the audio clock frequency in AD.
3124 *
3125 * @return Clock frequency; If the clock is invalid, returns 0.
3126 */
3127 uint32_t CLOCK_GetAdAudClkFreq(void);
3128
3129 /*!
3130 * @brief Gets the audio clock frequency in LPAV.
3131 *
3132 * @return Clock frequency; If the clock is invalid, returns 0.
3133 */
3134 uint32_t CLOCK_GetLpavAudClkFreq(void);
3135
3136 /*!
3137 * @brief Gets the SAI clock frequency.
3138 *
3139 * @param instance The SAI instance (0-7).
3140 * @return Clock frequency; If the clock is invalid, returns 0.
3141 */
3142 uint32_t CLOCK_GetSaiFreq(uint32_t instance);
3143
3144 /*!
3145 * @brief Gets the SPDIF clock frequency.
3146 *
3147 * @return Clock frequency; If the clock is invalid, returns 0.
3148 */
3149 uint32_t CLOCK_GetSpdifFreq(void);
3150
3151 /*!
3152 * @brief Gets the MQS clock frequency.
3153 *
3154 * @param instance The MQS instance (0-1).
3155 * @return Clock frequency; If the clock is invalid, returns 0.
3156 */
3157 uint32_t CLOCK_GetMqsFreq(uint32_t instance);
3158
3159 /*!
3160 * @brief Gets the EMICFIL clock frequency.
3161 *
3162 * @return Clock frequency; If the clock is invalid, returns 0.
3163 */
3164 uint32_t CLOCK_GetMicfilFreq(void);
3165
3166 /*!
3167 * @brief Gets the MRT clock frequency.
3168 *
3169 * @return Clock frequency; If the clock is invalid, returns 0.
3170 */
3171 uint32_t CLOCK_GetMrtFreq(void);
3172 /* @} */
3173
3174 /*!
3175 * @brief Gets the CGC system clock frequency in RTD.
3176 *
3177 * This function gets the CGC system clock frequency. These clocks are used for
3178 * core, platform, bus and slow clock domains.
3179 *
3180 * @param config Config value from CGC register.
3181 * @param type Which type of clock to get.
3182 * @return Clock frequency.
3183 */
3184 uint32_t CLOCK_GetRtdSysClkFreq(uint32_t config, cgc_sys_clk_t type);
3185 #if defined(__cplusplus)
3186 }
3187 #endif /* __cplusplus */
3188
3189 /*! @} */
3190
3191 #endif /* _FSL_CLOCK_H_ */
3192
