1 /*
2 * Copyright 2017 - 2022, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_device_registers.h"
12 #include <stdint.h>
13 #include <stdbool.h>
14 #include <stddef.h>
15 #include <assert.h>
16
17 /*!
18 * @addtogroup clock
19 * @{
20 */
21
22 /*******************************************************************************
23 * Definitions
24 ******************************************************************************/
25
26 /*! @name Driver version */
27 /*@{*/
28 /*! @brief CLOCK driver version 2.4.1. */
29 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
30 /*@}*/
31
32 /* Definition for delay API in clock driver, users can redefine it to the real application. */
33 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
34 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (400000000UL)
35 #endif
36
37 /*!
38 * @brief XTAL 25M clock frequency.
39 */
40 #define OSC25M_CLK_FREQ 25000000U
41
42 /*!
43 * @brief XTAL 27M clock frequency.
44 */
45 #define OSC27M_CLK_FREQ 27000000U
46
47 /*!
48 * @brief HDMI PHY 27M clock frequency.
49 */
50 #define HDMI_PHY_27M_FREQ 27000000U
51
52 /*!
53 * @brief clock1PN frequency.
54 */
55 #define CLKPN_FREQ 0U
56
57 /*! @brief Clock ip name array for ECSPI. */
58 #define ECSPI_CLOCKS \
59 { \
60 kCLOCK_IpInvalid, kCLOCK_Ecspi1, kCLOCK_Ecspi2, kCLOCK_Ecspi3, \
61 }
62
63 /*! @brief Clock ip name array for GPIO. */
64 #define GPIO_CLOCKS \
65 { \
66 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5, \
67 }
68
69 /*! @brief Clock ip name array for GPT. */
70 #define GPT_CLOCKS \
71 { \
72 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6, \
73 }
74
75 /*! @brief Clock ip name array for I2C. */
76 #define I2C_CLOCKS \
77 { \
78 kCLOCK_IpInvalid, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, \
79 }
80
81 /*! @brief Clock ip name array for IOMUX. */
82 #define IOMUX_CLOCKS \
83 { \
84 kCLOCK_Iomux, \
85 }
86
87 /*! @brief Clock ip name array for IPMUX. */
88 #define IPMUX_CLOCKS \
89 { \
90 kCLOCK_Ipmux1, kCLOCK_Ipmux2, kCLOCK_Ipmux3, kCLOCK_Ipmux4, \
91 }
92
93 /*! @brief Clock ip name array for PWM. */
94 #define PWM_CLOCKS \
95 { \
96 kCLOCK_IpInvalid, kCLOCK_Pwm1, kCLOCK_Pwm2, kCLOCK_Pwm3, kCLOCK_Pwm4, \
97 }
98
99 /*! @brief Clock ip name array for RDC. */
100 #define RDC_CLOCKS \
101 { \
102 kCLOCK_Rdc, \
103 }
104
105 /*! @brief Clock ip name array for SAI. */
106 #define SAI_CLOCKS \
107 { \
108 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4, kCLOCK_Sai5, kCLOCK_Sai6, \
109 }
110
111 /*! @brief Clock ip name array for RDC SEMA42. */
112 #define RDC_SEMA42_CLOCKS \
113 { \
114 kCLOCK_IpInvalid, kCLOCK_Sema42_1, kCLOCK_Sema42_2 \
115 }
116
117 /*! @brief Clock ip name array for UART. */
118 #define UART_CLOCKS \
119 { \
120 kCLOCK_IpInvalid, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, \
121 }
122
123 /*! @brief Clock ip name array for USDHC. */
124 #define USDHC_CLOCKS \
125 { \
126 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
127 }
128
129 /*! @brief Clock ip name array for WDOG. */
130 #define WDOG_CLOCKS \
131 { \
132 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3 \
133 }
134
135 /*! @brief Clock ip name array for TEMPSENSOR. */
136 #define TMU_CLOCKS \
137 { \
138 kCLOCK_TempSensor, \
139 }
140
141 /*! @brief Clock ip name array for SDMA. */
142 #define SDMA_CLOCKS \
143 { \
144 kCLOCK_Sdma1, kCLOCK_Sdma2 \
145 }
146
147 /*! @brief Clock ip name array for MU. */
148 #define MU_CLOCKS \
149 { \
150 kCLOCK_Mu \
151 }
152
153 /*! @brief Clock ip name array for QSPI. */
154 #define QSPI_CLOCKS \
155 { \
156 kCLOCK_Qspi \
157 }
158
159 /*!
160 * @brief CCM reg macros to extract corresponding registers bit field.
161 */
162 #define CCM_BIT_FIELD_EXTRACTION(val, mask, shift) (((val) & (mask)) >> (shift))
163
164 /*!
165 * @brief CCM reg macros to map corresponding registers.
166 */
167 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)(root) + (off))))
168 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
169 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
170 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
171
172 /*!
173 * @brief CCM Analog registers offset.
174 */
175 #define AUDIO_PLL1_CFG0_OFFSET 0x00
176 #define AUDIO_PLL2_CFG0_OFFSET 0x08
177 #define VIDEO_PLL1_CFG0_OFFSET 0x10
178 #define GPU_PLL_CFG0_OFFSET 0x18
179 #define VPU_PLL_CFG0_OFFSET 0x20
180 #define ARM_PLL_CFG0_OFFSET 0x28
181 #define SYS_PLL1_CFG0_OFFSET 0x30
182 #define SYS_PLL2_CFG0_OFFSET 0x3C
183 #define SYS_PLL3_CFG0_OFFSET 0x48
184 #define VIDEO_PLL2_CFG0_OFFSET 0x54
185 #define DRAM_PLL_CFG0_OFFSET 0x60
186 #define OSC_MISC_CFG_OFFSET 0x70
187
188 /*!
189 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
190 */
191 #define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFFU) << 16U) | (shift))
192 #define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)(tuple)) & 0x1FU)
193 #define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
194 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFFU) + (off))))
195 #define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
196
197 /*!
198 * @brief CCM CCGR and root tuple
199 */
200 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root))
201 #define CCM_TUPLE_CCGR(tuple) ((uint32_t)(&(CCM)->CCGR[(uint32_t)(tuple) >> 16U].CCGR))
202 #define CCM_TUPLE_ROOT(tuple) ((uint32_t)(&(CCM)->ROOT[(uint32_t)(tuple)&0xFFFFU].TARGET_ROOT))
203
204 /*!
205 * @brief clock root source
206 */
207 #define CLOCK_ROOT_SOURCE \
208 { \
209 {kCLOCK_Osc25MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll2Div4Clk, kCLOCK_SysPll1Div3Clk, kCLOCK_SysPll1Clk, \
210 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll3Clk}, /* Cortex-M4 Clock Root. */ \
211 { \
212 kCLOCK_Osc25MClk, kCLOCK_SysPll2Div3Clk, kCLOCK_SysPll1Clk, \
213 kCLOCK_SysPll2Div4Clk, kCLOCK_SysPll2Clk, kCLOCK_AudioPll1Clk, \
214 kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div8Clk}, /* AXI Clock Root. */ \
215 {kCLOCK_Osc25MClk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, kCLOCK_SysPll2Clk, kCLOCK_SysPll2Div2Clk, \
216 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, kCLOCK_AudioPll2Clk}, /* NOC Clock Root. */ \
217 { \
218 kCLOCK_Osc25MClk, kCLOCK_SysPll1Div6Clk, kCLOCK_SysPll1Clk, \
219 kCLOCK_SysPll1Div2Clk, kCLOCK_SysPll2Div8Clk, kCLOCK_SysPll3Clk, \
220 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk}, /* AHB Clock Root. */ \
221 { \
222 kCLOCK_Osc25MClk, kCLOCK_SysPll1Div6Clk, kCLOCK_SysPll1Clk, \
223 kCLOCK_SysPll1Div2Clk, kCLOCK_SysPll2Div8Clk, kCLOCK_SysPll3Clk, \
224 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk}, /* IPG Clock Root. */ \
225 {kCLOCK_Osc25MClk, kCLOCK_SysPll1Clk, kCLOCK_SysPll1Div8Clk, \
226 kCLOCK_SysPll2Div2Clk, kCLOCK_SysPll2Div4Clk, kCLOCK_SysPll1Div2Clk, \
227 kCLOCK_AudioPll1Clk, kCLOCK_SysPll1Div3Clk}, /* DRAM ALT Clock Root */ \
228 {kCLOCK_Osc25MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
229 kCLOCK_SysPll1Div6Clk, kCLOCK_Osc27MClk, kCLOCK_ExtClk1, kCLOCK_ExtClk2}, /* SAI1 Clock Root */ \
230 {kCLOCK_Osc25MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
231 kCLOCK_SysPll1Div6Clk, kCLOCK_Osc27MClk, kCLOCK_ExtClk2, kCLOCK_ExtClk3}, /* SAI2 Clock Root */ \
232 {kCLOCK_Osc25MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
233 kCLOCK_SysPll1Div6Clk, kCLOCK_Osc27MClk, kCLOCK_ExtClk3, kCLOCK_ExtClk4}, /* SAI3 Clock Root */ \
234 {kCLOCK_Osc25MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
235 kCLOCK_SysPll1Div6Clk, kCLOCK_Osc27MClk, kCLOCK_ExtClk1, kCLOCK_ExtClk2}, /* SAI4 Clock Root */ \
236 {kCLOCK_Osc25MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
237 kCLOCK_SysPll1Div6Clk, kCLOCK_Osc27MClk, kCLOCK_ExtClk2, kCLOCK_ExtClk3}, /* SAI5 Clock Root. */ \
238 {kCLOCK_Osc25MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
239 kCLOCK_SysPll1Div6Clk, kCLOCK_Osc27MClk, kCLOCK_ExtClk3, kCLOCK_ExtClk4}, /* SAI6 Clock Root */ \
240 {kCLOCK_Osc25MClk, kCLOCK_SysPll1Div2Clk, kCLOCK_SysPll1Clk, \
241 kCLOCK_SysPll2Div2Clk, kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div3Clk, \
242 kCLOCK_SysPll3Clk, kCLOCK_SysPll1Div8Clk}, /* QSPI Clock Root */ \
243 { \
244 kCLOCK_Osc25MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
245 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
246 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C1 Clock Root */ \
247 { \
248 kCLOCK_Osc25MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
249 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
250 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C2 Clock Root */ \
251 { \
252 kCLOCK_Osc25MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
253 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
254 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C3 Clock Root */ \
255 { \
256 kCLOCK_Osc25MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
257 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
258 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C4 Clock Root */ \
259 { \
260 kCLOCK_Osc25MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
261 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
262 kCLOCK_ExtClk4, kCLOCK_AudioPll2Clk}, /* UART1 Clock Root */ \
263 { \
264 kCLOCK_Osc25MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
265 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
266 kCLOCK_ExtClk3, kCLOCK_AudioPll2Clk}, /* UART2 Clock Root */ \
267 { \
268 kCLOCK_Osc25MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
269 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
270 kCLOCK_ExtClk4, kCLOCK_AudioPll2Clk}, /* UART3 Clock Root */ \
271 { \
272 kCLOCK_Osc25MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
273 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
274 kCLOCK_ExtClk3, kCLOCK_AudioPll2Clk}, /* UART4 Clock Root */ \
275 { \
276 kCLOCK_Osc25MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div20Clk, \
277 kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, \
278 kCLOCK_SysPll2Div4Clk, kCLOCK_AudioPll2Clk}, /* ECSPI1 Clock ROOT */ \
279 { \
280 kCLOCK_Osc25MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div20Clk, \
281 kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, \
282 kCLOCK_SysPll2Div4Clk, kCLOCK_AudioPll2Clk}, /* ECSPI2 Clock ROOT */ \
283 { \
284 kCLOCK_Osc25MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div20Clk, \
285 kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, \
286 kCLOCK_SysPll2Div4Clk, kCLOCK_AudioPll2Clk}, /* ECSPI3 Clock ROOT */ \
287 { \
288 kCLOCK_Osc25MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
289 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk1, \
290 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM1 Clock ROOT */ \
291 { \
292 kCLOCK_Osc25MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
293 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk1, \
294 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM2 Clock ROOT */ \
295 { \
296 kCLOCK_Osc25MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
297 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
298 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM3 Clock ROOT */ \
299 { \
300 kCLOCK_Osc25MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
301 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
302 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM4 Clock ROOT */ \
303 { \
304 kCLOCK_Osc25MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
305 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
306 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk1}, /* GPT1 Clock ROOT */ \
307 { \
308 kCLOCK_Osc25MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
309 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
310 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk2}, /* GPT2 Clock ROOT */ \
311 { \
312 kCLOCK_Osc25MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
313 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
314 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk3}, /* GPT3 Clock ROOT */ \
315 { \
316 kCLOCK_Osc25MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
317 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
318 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk1}, /* GPT4 Clock ROOT */ \
319 { \
320 kCLOCK_Osc25MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
321 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
322 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk2}, /* GPT5 Clock ROOT */ \
323 { \
324 kCLOCK_Osc25MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
325 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
326 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk3}, /* GPT6 Clock ROOT */ \
327 { \
328 kCLOCK_Osc25MClk, kCLOCK_SysPll1Div6Clk, kCLOCK_SysPll1Div5Clk, \
329 kCLOCK_VpuPllClk, kCLOCK_SysPll2Div8Clk, kCLOCK_SysPll3Clk, \
330 kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div6Clk}, /* WDOG Clock ROOT */ \
331 }
332
333 #define CLOCK_ROOT_CONTROL_TUPLE \
334 { \
335 kCLOCK_RootM4, kCLOCK_RootAxi, kCLOCK_RootNoc, kCLOCK_RootAhb, kCLOCK_RootAhb, kCLOCK_RootDramAlt, \
336 kCLOCK_RootSai1, kCLOCK_RootSai2, kCLOCK_RootSai3, kCLOCK_RootSai4, kCLOCK_RootSai5, kCLOCK_RootSai6, \
337 kCLOCK_RootQspi, kCLOCK_RootI2c1, kCLOCK_RootI2c2, kCLOCK_RootI2c3, kCLOCK_RootI2c4, kCLOCK_RootUart1, \
338 kCLOCK_RootUart2, kCLOCK_RootUart3, kCLOCK_RootUart4, kCLOCK_RootEcspi1, kCLOCK_RootEcspi2, \
339 kCLOCK_RootEcspi3, kCLOCK_RootPwm1, kCLOCK_RootPwm2, kCLOCK_RootPwm3, kCLOCK_RootPwm4, kCLOCK_RootGpt1, \
340 kCLOCK_RootGpt2, kCLOCK_RootGpt3, kCLOCK_RootGpt4, kCLOCK_RootGpt5, kCLOCK_RootGpt6, kCLOCK_RootWdog, \
341 }
342
343 /*! @brief Clock name used to get clock frequency. */
344 typedef enum _clock_name
345 {
346 kCLOCK_CoreM4Clk, /*!< ARM M4 Core clock */
347
348 kCLOCK_AxiClk, /*!< Main AXI bus clock. */
349 kCLOCK_AhbClk, /*!< AHB bus clock. */
350 kCLOCK_IpgClk, /*!< IPG bus clock. */
351 kCLOCK_Osc25MClk, /*!< OSC 25M clock. */
352 kCLOCK_Osc27MClk, /*!< OSC 27M clock. */
353 kCLOCK_ArmPllClk, /*!< Arm PLL clock. */
354 kCLOCK_VpuPllClk, /*!< Vpu PLL clock. */
355 kCLOCK_DramPllClk, /*!< Dram PLL clock. */
356 kCLOCK_SysPll1Clk, /*!< Sys PLL1 clock. */
357 kCLOCK_SysPll1Div2Clk, /*!< Sys PLL1 clock divided by 2. */
358 kCLOCK_SysPll1Div3Clk, /*!< Sys PLL1 clock divided by 3. */
359 kCLOCK_SysPll1Div4Clk, /*!< Sys PLL1 clock divided by 4. */
360 kCLOCK_SysPll1Div5Clk, /*!< Sys PLL1 clock divided by 5. */
361 kCLOCK_SysPll1Div6Clk, /*!< Sys PLL1 clock divided by 6. */
362 kCLOCK_SysPll1Div8Clk, /*!< Sys PLL1 clock divided by 8. */
363 kCLOCK_SysPll1Div10Clk, /*!< Sys PLL1 clock divided by 10. */
364 kCLOCK_SysPll1Div20Clk, /*!< Sys PLL1 clock divided by 20. */
365 kCLOCK_SysPll2Clk, /*!< Sys PLL2 clock. */
366 kCLOCK_SysPll2Div2Clk, /*!< Sys PLL2 clock divided by 2. */
367 kCLOCK_SysPll2Div3Clk, /*!< Sys PLL2 clock divided by 3. */
368 kCLOCK_SysPll2Div4Clk, /*!< Sys PLL2 clock divided by 4. */
369 kCLOCK_SysPll2Div5Clk, /*!< Sys PLL2 clock divided by 5. */
370 kCLOCK_SysPll2Div6Clk, /*!< Sys PLL2 clock divided by 6. */
371 kCLOCK_SysPll2Div8Clk, /*!< Sys PLL2 clock divided by 8. */
372 kCLOCK_SysPll2Div10Clk, /*!< Sys PLL2 clock divided by 10. */
373 kCLOCK_SysPll2Div20Clk, /*!< Sys PLL2 clock divided by 20. */
374 kCLOCK_SysPll3Clk, /*!< Sys PLL3 clock. */
375 kCLOCK_AudioPll1Clk, /*!< Audio PLL1 clock. */
376 kCLOCK_AudioPll2Clk, /*!< Audio PLL2 clock. */
377 kCLOCK_VideoPll1Clk, /*!< Video PLL1 clock. */
378 kCLOCK_ExtClk1, /*!< External clock1. */
379 kCLOCK_ExtClk2, /*!< External clock2. */
380 kCLOCK_ExtClk3, /*!< External clock3. */
381 kCLOCK_ExtClk4, /*!< External clock4. */
382 kCLOCK_NoneName, /*!< None Clock Name. */
383 /* -------------------------------- Other clock --------------------------*/
384 } clock_name_t;
385
386 #define kCLOCK_CoreSysClk kCLOCK_CoreM4Clk /*!< For compatible with other platforms without CCM. */
387 #define CLOCK_GetCoreSysClkFreq CLOCK_GetCoreM4Freq /*!< For compatible with other platforms without CCM. */
388
389 /*! @brief CCM CCGR gate control. */
390 typedef enum _clock_ip_name
391 {
392 kCLOCK_IpInvalid = -1,
393
394 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
395
396 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
397
398 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
399 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
400 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
401
402 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
403 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
404 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
405 kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U), /*!< GPIO4 Clock Gate.*/
406 kCLOCK_Gpio5 = CCM_TUPLE(15U, 33U), /*!< GPIO5 Clock Gate.*/
407
408 kCLOCK_Gpt1 = CCM_TUPLE(16U, 107U), /*!< GPT1 Clock Gate.*/
409 kCLOCK_Gpt2 = CCM_TUPLE(17U, 108U), /*!< GPT2 Clock Gate.*/
410 kCLOCK_Gpt3 = CCM_TUPLE(18U, 109U), /*!< GPT3 Clock Gate.*/
411 kCLOCK_Gpt4 = CCM_TUPLE(19U, 110U), /*!< GPT4 Clock Gate.*/
412 kCLOCK_Gpt5 = CCM_TUPLE(20U, 111U), /*!< GPT5 Clock Gate.*/
413 kCLOCK_Gpt6 = CCM_TUPLE(21U, 112U), /*!< GPT6 Clock Gate.*/
414
415 kCLOCK_I2c1 = CCM_TUPLE(23U, 90U), /*!< I2C1 Clock Gate.*/
416 kCLOCK_I2c2 = CCM_TUPLE(24U, 91U), /*!< I2C2 Clock Gate.*/
417 kCLOCK_I2c3 = CCM_TUPLE(25U, 92U), /*!< I2C3 Clock Gate.*/
418 kCLOCK_I2c4 = CCM_TUPLE(26U, 93U), /*!< I2C4 Clock Gate.*/
419
420 kCLOCK_Iomux = CCM_TUPLE(27U, 33U), /*!< IOMUX Clock Gate.*/
421 kCLOCK_Ipmux1 = CCM_TUPLE(28U, 33U), /*!< IPMUX1 Clock Gate.*/
422 kCLOCK_Ipmux2 = CCM_TUPLE(29U, 33U), /*!< IPMUX2 Clock Gate.*/
423 kCLOCK_Ipmux3 = CCM_TUPLE(30U, 33U), /*!< IPMUX3 Clock Gate.*/
424 kCLOCK_Ipmux4 = CCM_TUPLE(31U, 33U), /*!< IPMUX4 Clock Gate.*/
425
426 kCLOCK_M4 = CCM_TUPLE(32U, 1U), /*!< M4 Clock Gate.*/
427
428 kCLOCK_Mu = CCM_TUPLE(33U, 33U), /*!< MU Clock Gate.*/
429
430 kCLOCK_Ocram = CCM_TUPLE(35U, 16U), /*!< OCRAM Clock Gate.*/
431 kCLOCK_OcramS = CCM_TUPLE(36U, 32U), /*!< OCRAM S Clock Gate.*/
432
433 kCLOCK_Pwm1 = CCM_TUPLE(40U, 103U), /*!< PWM1 Clock Gate.*/
434 kCLOCK_Pwm2 = CCM_TUPLE(41U, 104U), /*!< PWM2 Clock Gate.*/
435 kCLOCK_Pwm3 = CCM_TUPLE(42U, 105U), /*!< PWM3 Clock Gate.*/
436 kCLOCK_Pwm4 = CCM_TUPLE(43U, 106U), /*!< PWM4 Clock Gate.*/
437
438 kCLOCK_Qspi = CCM_TUPLE(47U, 87U), /*!< QSPI Clock Gate.*/
439
440 kCLOCK_Rdc = CCM_TUPLE(49U, 33U), /*!< RDC Clock Gate.*/
441
442 kCLOCK_Sai1 = CCM_TUPLE(51U, 75U), /*!< SAI1 Clock Gate.*/
443 kCLOCK_Sai2 = CCM_TUPLE(52U, 76U), /*!< SAI2 Clock Gate.*/
444 kCLOCK_Sai3 = CCM_TUPLE(53U, 77U), /*!< SAI3 Clock Gate.*/
445 kCLOCK_Sai4 = CCM_TUPLE(54U, 78U), /*!< SAI4 Clock Gate.*/
446 kCLOCK_Sai5 = CCM_TUPLE(55U, 79U), /*!< SAI5 Clock Gate.*/
447 kCLOCK_Sai6 = CCM_TUPLE(56U, 80U), /*!< SAI6 Clock Gate.*/
448
449 kCLOCK_Sdma1 = CCM_TUPLE(58U, 33U), /*!< SDMA1 Clock Gate.*/
450 kCLOCK_Sdma2 = CCM_TUPLE(59U, 35U), /*!< SDMA2 Clock Gate.*/
451
452 kCLOCK_Sec_Debug = CCM_TUPLE(60U, 33U), /*!< SEC_DEBUG Clock Gate.*/
453
454 kCLOCK_Sema42_1 = CCM_TUPLE(61U, 33U), /*!< RDC SEMA42 Clock Gate.*/
455 kCLOCK_Sema42_2 = CCM_TUPLE(62U, 33U), /*!< RDC SEMA42 Clock Gate.*/
456
457 kCLOCK_Sim_display = CCM_TUPLE(63U, 16U), /*!< SIM_Display Clock Gate.*/
458 kCLOCK_Sim_m = CCM_TUPLE(65U, 32U), /*!< SIM_M Clock Gate.*/
459 kCLOCK_Sim_main = CCM_TUPLE(66U, 16U), /*!< SIM_MAIN Clock Gate.*/
460 kCLOCK_Sim_s = CCM_TUPLE(67U, 32U), /*!< SIM_S Clock Gate.*/
461 kCLOCK_Sim_wakeup = CCM_TUPLE(68U, 32U), /*!< SIM_WAKEUP Clock Gate.*/
462
463 kCLOCK_Uart1 = CCM_TUPLE(73U, 94U), /*!< UART1 Clock Gate.*/
464 kCLOCK_Uart2 = CCM_TUPLE(74U, 95U), /*!< UART2 Clock Gate.*/
465 kCLOCK_Uart3 = CCM_TUPLE(75U, 96U), /*!< UART3 Clock Gate.*/
466 kCLOCK_Uart4 = CCM_TUPLE(76U, 97U), /*!< UART4 Clock Gate.*/
467
468 kCLOCK_Wdog1 = CCM_TUPLE(83U, 114U), /*!< WDOG1 Clock Gate.*/
469 kCLOCK_Wdog2 = CCM_TUPLE(84U, 114U), /*!< WDOG2 Clock Gate.*/
470 kCLOCK_Wdog3 = CCM_TUPLE(85U, 114U), /*!< WDOG3 Clock Gate.*/
471
472 kCLOCK_TempSensor = CCM_TUPLE(98U, 0xFFFF), /*!< TempSensor Clock Gate.*/
473
474 } clock_ip_name_t;
475
476 /*! @brief ccm root name used to get clock frequency. */
477 typedef enum _clock_root_control
478 {
479 kCLOCK_RootM4 =
480 (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[1].TARGET_ROOT), /*!< ARM Cortex-M4 Clock control name.*/
481 kCLOCK_RootAxi = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[16].TARGET_ROOT), /*!< AXI Clock control name.*/
482 kCLOCK_RootNoc = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[26].TARGET_ROOT), /*!< NOC Clock control name.*/
483 kCLOCK_RootAhb = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[32].TARGET_ROOT), /*!< AHB Clock control name.*/
484 kCLOCK_RootIpg = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[33].TARGET_ROOT), /*!< IPG Clock control name.*/
485 kCLOCK_RootDramAlt =
486 (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[64].TARGET_ROOT), /*!< DRAM ALT Clock control name.*/
487
488 kCLOCK_RootSai1 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[75].TARGET_ROOT), /*!< SAI1 Clock control name.*/
489 kCLOCK_RootSai2 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[76].TARGET_ROOT), /*!< SAI2 Clock control name.*/
490 kCLOCK_RootSai3 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[77].TARGET_ROOT), /*!< SAI3 Clock control name.*/
491 kCLOCK_RootSai4 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[78].TARGET_ROOT), /*!< SAI4 Clock control name.*/
492 kCLOCK_RootSai5 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[79].TARGET_ROOT), /*!< SAI5 Clock control name.*/
493 kCLOCK_RootSai6 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[80].TARGET_ROOT), /*!< SAI6 Clock control name.*/
494
495 kCLOCK_RootQspi = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[87].TARGET_ROOT), /*!< QSPI Clock control name.*/
496
497 kCLOCK_RootI2c1 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[90].TARGET_ROOT), /*!< I2C1 Clock control name.*/
498 kCLOCK_RootI2c2 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[91].TARGET_ROOT), /*!< I2C2 Clock control name.*/
499 kCLOCK_RootI2c3 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[92].TARGET_ROOT), /*!< I2C3 Clock control name.*/
500 kCLOCK_RootI2c4 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[93].TARGET_ROOT), /*!< I2C4 Clock control name.*/
501
502 kCLOCK_RootUart1 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[94].TARGET_ROOT), /*!< UART1 Clock control name.*/
503 kCLOCK_RootUart2 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[95].TARGET_ROOT), /*!< UART2 Clock control name.*/
504 kCLOCK_RootUart3 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[96].TARGET_ROOT), /*!< UART3 Clock control name.*/
505 kCLOCK_RootUart4 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[97].TARGET_ROOT), /*!< UART4 Clock control name.*/
506
507 kCLOCK_RootEcspi1 =
508 (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[101].TARGET_ROOT), /*!< ECSPI1 Clock control name.*/
509 kCLOCK_RootEcspi2 =
510 (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[102].TARGET_ROOT), /*!< ECSPI2 Clock control name.*/
511 kCLOCK_RootEcspi3 =
512 (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[131].TARGET_ROOT), /*!< ECSPI3 Clock control name.*/
513
514 kCLOCK_RootPwm1 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[103].TARGET_ROOT), /*!< PWM1 Clock control name.*/
515 kCLOCK_RootPwm2 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[104].TARGET_ROOT), /*!< PWM2 Clock control name.*/
516 kCLOCK_RootPwm3 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[105].TARGET_ROOT), /*!< PWM3 Clock control name.*/
517 kCLOCK_RootPwm4 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[106].TARGET_ROOT), /*!< PWM4 Clock control name.*/
518
519 kCLOCK_RootGpt1 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[107].TARGET_ROOT), /*!< GPT1 Clock control name.*/
520 kCLOCK_RootGpt2 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[108].TARGET_ROOT), /*!< GPT2 Clock control name.*/
521 kCLOCK_RootGpt3 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[109].TARGET_ROOT), /*!< GPT3 Clock control name.*/
522 kCLOCK_RootGpt4 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[110].TARGET_ROOT), /*!< GPT4 Clock control name.*/
523 kCLOCK_RootGpt5 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[111].TARGET_ROOT), /*!< GPT5 Clock control name.*/
524 kCLOCK_RootGpt6 = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[112].TARGET_ROOT), /*!< GPT6 Clock control name.*/
525
526 kCLOCK_RootWdog = (uint32_t)CCM_BASE + offsetof(CCM_Type, ROOT[114].TARGET_ROOT), /*!< WDOG Clock control name.*/
527 } clock_root_control_t;
528
529 /*! @brief ccm clock root used to get clock frequency. */
530 typedef enum _clock_root
531 {
532 kCLOCK_M4ClkRoot = 0, /*!< ARM Cortex-M4 Clock control name.*/
533 kCLOCK_AxiClkRoot, /*!< AXI Clock control name.*/
534 kCLOCK_NocClkRoot, /*!< NOC Clock control name.*/
535 kCLOCK_AhbClkRoot, /*!< AHB Clock control name.*/
536 kCLOCK_IpgClkRoot, /*!< IPG Clock control name.*/
537 kCLOCK_DramAltClkRoot, /*!< DRAM ALT Clock control name.*/
538
539 kCLOCK_Sai1ClkRoot, /*!< SAI1 Clock control name.*/
540 kCLOCK_Sai2ClkRoot, /*!< SAI2 Clock control name.*/
541 kCLOCK_Sai3ClkRoot, /*!< SAI3 Clock control name.*/
542 kCLOCK_Sai4ClkRoot, /*!< SAI4 Clock control name.*/
543 kCLOCK_Sai5ClkRoot, /*!< SAI5 Clock control name.*/
544 kCLOCK_Sai6ClkRoot, /*!< SAI6 Clock control name.*/
545
546 kCLOCK_QspiClkRoot, /*!< QSPI Clock control name.*/
547
548 kCLOCK_I2c1ClkRoot, /*!< I2C1 Clock control name.*/
549 kCLOCK_I2c2ClkRoot, /*!< I2C2 Clock control name.*/
550 kCLOCK_I2c3ClkRoot, /*!< I2C3 Clock control name.*/
551 kCLOCK_I2c4ClkRoot, /*!< I2C4 Clock control name.*/
552
553 kCLOCK_Uart1ClkRoot, /*!< UART1 Clock control name.*/
554 kCLOCK_Uart2ClkRoot, /*!< UART2 Clock control name.*/
555 kCLOCK_Uart3ClkRoot, /*!< UART3 Clock control name.*/
556 kCLOCK_Uart4ClkRoot, /*!< UART4 Clock control name.*/
557
558 kCLOCK_Ecspi1ClkRoot, /*!< ECSPI1 Clock control name.*/
559 kCLOCK_Ecspi2ClkRoot, /*!< ECSPI2 Clock control name.*/
560 kCLOCK_Ecspi3ClkRoot, /*!< ECSPI3 Clock control name.*/
561
562 kCLOCK_Pwm1ClkRoot, /*!< PWM1 Clock control name.*/
563 kCLOCK_Pwm2ClkRoot, /*!< PWM2 Clock control name.*/
564 kCLOCK_Pwm3ClkRoot, /*!< PWM3 Clock control name.*/
565 kCLOCK_Pwm4ClkRoot, /*!< PWM4 Clock control name.*/
566
567 kCLOCK_Gpt1ClkRoot, /*!< GPT1 Clock control name.*/
568 kCLOCK_Gpt2ClkRoot, /*!< GPT2 Clock control name.*/
569 kCLOCK_Gpt3ClkRoot, /*!< GPT3 Clock control name.*/
570 kCLOCK_Gpt4ClkRoot, /*!< GPT4 Clock control name.*/
571 kCLOCK_Gpt5ClkRoot, /*!< GPT5 Clock control name.*/
572 kCLOCK_Gpt6ClkRoot, /*!< GPT6 Clock control name.*/
573
574 kCLOCK_WdogClkRoot, /*!< WDOG Clock control name.*/
575 } clock_root_t;
576
577 /*! @brief Root clock select enumeration for ARM Cortex-M4 core. */
578 typedef enum _clock_rootmux_m4_clk_sel
579 {
580 kCLOCK_M4RootmuxOsc25m = 0U, /*!< ARM Cortex-M4 Clock from OSC 25M.*/
581 kCLOCK_M4RootmuxSysPll2Div5 = 1U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 5.*/
582 kCLOCK_M4RootmuxSysPll2Div4 = 2U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 4.*/
583 kCLOCK_M4RootmuxSysPll1Div3 = 3U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL1 divided by 3.*/
584 kCLOCK_M4RootmuxSysPll1 = 4U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL1.*/
585 kCLOCK_M4RootmuxAudioPll1 = 5U, /*!< ARM Cortex-M4 Clock from AUDIO PLL1.*/
586 kCLOCK_M4RootmuxVideoPll1 = 6U, /*!< ARM Cortex-M4 Clock from VIDEO PLL1.*/
587 kCLOCK_M4RootmuxSysPll3 = 7U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL3.*/
588 } clock_rootmux_m4_clk_sel_t;
589
590 /*! @brief Root clock select enumeration for AXI bus. */
591 typedef enum _clock_rootmux_axi_clk_sel
592 {
593 kCLOCK_AxiRootmuxOsc25m = 0U, /*!< ARM AXI Clock from OSC 25M.*/
594 kCLOCK_AxiRootmuxSysPll2Div3 = 1U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 3.*/
595 kCLOCK_AxiRootmuxSysPll1 = 2U, /*!< ARM AXI Clock from SYSTEM PLL1.*/
596 kCLOCK_AxiRootmuxSysPll2Div4 = 3U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 4.*/
597 kCLOCK_AxiRootmuxSysPll2 = 4U, /*!< ARM AXI Clock from SYSTEM PLL2.*/
598 kCLOCK_AxiRootmuxAudioPll1 = 5U, /*!< ARM AXI Clock from AUDIO PLL1.*/
599 kCLOCK_AxiRootmuxVideoPll1 = 6U, /*!< ARM AXI Clock from VIDEO PLL1.*/
600 kCLOCK_AxiRootmuxSysPll1Div8 = 7U, /*!< ARM AXI Clock from SYSTEM PLL1 divided by 8.*/
601 } clock_rootmux_axi_clk_sel_t;
602
603 /*! @brief Root clock select enumeration for AHB bus. */
604 typedef enum _clock_rootmux_ahb_clk_sel
605 {
606 kCLOCK_AhbRootmuxOsc25m = 0U, /*!< ARM AHB Clock from OSC 25M.*/
607 kCLOCK_AhbRootmuxSysPll1Div6 = 1U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 6.*/
608 kCLOCK_AhbRootmuxSysPll1 = 2U, /*!< ARM AHB Clock from SYSTEM PLL1.*/
609 kCLOCK_AhbRootmuxSysPll1Div2 = 3U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 2.*/
610 kCLOCK_AhbRootmuxSysPll2Div8 = 4U, /*!< ARM AHB Clock from SYSTEM PLL2 divided by 8.*/
611 kCLOCK_AhbRootmuxSysPll3 = 5U, /*!< ARM AHB Clock from SYSTEM PLL3.*/
612 kCLOCK_AhbRootmuxAudioPll1 = 6U, /*!< ARM AHB Clock from AUDIO PLL1.*/
613 kCLOCK_AhbRootmuxVideoPll1 = 7U, /*!< ARM AHB Clock from VIDEO PLL1.*/
614 } clock_rootmux_ahb_clk_sel_t;
615
616 /*! @brief Root clock select enumeration for QSPI peripheral. */
617 typedef enum _clock_rootmux_qspi_clk_sel
618 {
619 kCLOCK_QspiRootmuxOsc25m = 0U, /*!< ARM QSPI Clock from OSC 25M.*/
620 kCLOCK_QspiRootmuxSysPll1Div2 = 1U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 2.*/
621 kCLOCK_QspiRootmuxSysPll1 = 2U, /*!< ARM QSPI Clock from SYSTEM PLL1.*/
622 kCLOCK_QspiRootmuxSysPll2Div2 = 3U, /*!< ARM QSPI Clock from SYSTEM PLL2 divided by 2.*/
623 kCLOCK_QspiRootmuxAudioPll2 = 4, /*!< ARM QSPI Clock from AUDIO PLL2.*/
624 kCLOCK_QspiRootmuxSysPll1Div3 = 5U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 3 */
625 kCLOCK_QspiRootmuxSysPll3 = 6U, /*!< ARM QSPI Clock from SYSTEM PLL3.*/
626 kCLOCK_QspiRootmuxSysPll1Div8 = 7U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 8.*/
627 } clock_rootmux_qspi_clk_sel_t;
628
629 /*! @brief Root clock select enumeration for ECSPI peripheral. */
630 typedef enum _clock_rootmux_ecspi_clk_sel
631 {
632 kCLOCK_EcspiRootmuxOsc25m = 0U, /*!< ECSPI Clock from OSC 25M.*/
633 kCLOCK_EcspiRootmuxSysPll2Div5 = 1U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 5.*/
634 kCLOCK_EcspiRootmuxSysPll1Div20 = 2U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 20.*/
635 kCLOCK_EcspiRootmuxSysPll1Div5 = 3U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 5.*/
636 kCLOCK_EcspiRootmuxSysPll1 = 4U, /*!< ECSPI Clock from SYSTEM PLL1.*/
637 kCLOCK_EcspiRootmuxSysPll3 = 5U, /*!< ECSPI Clock from SYSTEM PLL3.*/
638 kCLOCK_EcspiRootmuxSysPll2Div4 = 6U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 4.*/
639 kCLOCK_EcspiRootmuxAudioPll2 = 7U, /*!< ECSPI Clock from AUDIO PLL2.*/
640 } clock_rootmux_ecspi_clk_sel_t;
641
642 /*! @brief Root clock select enumeration for I2C peripheral. */
643 typedef enum _clock_rootmux_i2c_clk_sel
644 {
645 kCLOCK_I2cRootmuxOsc25m = 0U, /*!< I2C Clock from OSC 25M.*/
646 kCLOCK_I2cRootmuxSysPll1Div5 = 1U, /*!< I2C Clock from SYSTEM PLL1 divided by 5.*/
647 kCLOCK_I2cRootmuxSysPll2Div20 = 2U, /*!< I2C Clock from SYSTEM PLL2 divided by 20.*/
648 kCLOCK_I2cRootmuxSysPll3 = 3U, /*!< I2C Clock from SYSTEM PLL3 .*/
649 kCLOCK_I2cRootmuxAudioPll1 = 4U, /*!< I2C Clock from AUDIO PLL1.*/
650 kCLOCK_I2cRootmuxVideoPll1 = 5U, /*!< I2C Clock from VIDEO PLL1.*/
651 kCLOCK_I2cRootmuxAudioPll2 = 6U, /*!< I2C Clock from AUDIO PLL2.*/
652 kCLOCK_I2cRootmuxSysPll1Div6 = 7U, /*!< I2C Clock from SYSTEM PLL1 divided by 6.*/
653 } clock_rootmux_i2c_clk_sel_t;
654
655 /*! @brief Root clock select enumeration for UART peripheral. */
656 typedef enum _clock_rootmux_uart_clk_sel
657 {
658 kCLOCK_UartRootmuxOsc25m = 0U, /*!< UART Clock from OSC 25M.*/
659 kCLOCK_UartRootmuxSysPll1Div10 = 1U, /*!< UART Clock from SYSTEM PLL1 divided by 10.*/
660 kCLOCK_UartRootmuxSysPll2Div5 = 2U, /*!< UART Clock from SYSTEM PLL2 divided by 5.*/
661 kCLOCK_UartRootmuxSysPll2Div10 = 3U, /*!< UART Clock from SYSTEM PLL2 divided by 10.*/
662 kCLOCK_UartRootmuxSysPll3 = 4U, /*!< UART Clock from SYSTEM PLL3.*/
663 kCLOCK_UartRootmuxExtClk2 = 5U, /*!< UART Clock from External Clock 2.*/
664 kCLOCK_UartRootmuxExtClk34 = 6U, /*!< UART Clock from External Clock 3, External Clock 4.*/
665 kCLOCK_UartRootmuxAudioPll2 = 7U, /*!< UART Clock from Audio PLL2.*/
666 } clock_rootmux_uart_clk_sel_t;
667
668 /*! @brief Root clock select enumeration for GPT peripheral. */
669 typedef enum _clock_rootmux_gpt
670 {
671 kCLOCK_GptRootmuxOsc25m = 0U, /*!< GPT Clock from OSC 25M.*/
672 kCLOCK_GptRootmuxSystemPll2Div10 = 1U, /*!< GPT Clock from SYSTEM PLL2 divided by 10.*/
673 kCLOCK_GptRootmuxSysPll1Div2 = 2U, /*!< GPT Clock from SYSTEM PLL1 divided by 2.*/
674 kCLOCK_GptRootmuxSysPll1Div20 = 3U, /*!< GPT Clock from SYSTEM PLL1 divided by 20.*/
675 kCLOCK_GptRootmuxVideoPll1 = 4U, /*!< GPT Clock from VIDEO PLL1.*/
676 kCLOCK_GptRootmuxSystemPll1Div10 = 5U, /*!< GPT Clock from SYSTEM PLL1 divided by 10.*/
677 kCLOCK_GptRootmuxAudioPll1 = 6U, /*!< GPT Clock from AUDIO PLL1.*/
678 kCLOCK_GptRootmuxExtClk123 = 7U, /*!< GPT Clock from External Clock1, External Clock2, External Clock3.*/
679 } clock_rootmux_gpt_t;
680
681 /*! @brief Root clock select enumeration for WDOG peripheral. */
682 typedef enum _clock_rootmux_wdog_clk_sel
683 {
684 kCLOCK_WdogRootmuxOsc25m = 0U, /*!< WDOG Clock from OSC 25M.*/
685 kCLOCK_WdogRootmuxSysPll1Div6 = 1U, /*!< WDOG Clock from SYSTEM PLL1 divided by 6.*/
686 kCLOCK_WdogRootmuxSysPll1Div5 = 2U, /*!< WDOG Clock from SYSTEM PLL1 divided by 5.*/
687 kCLOCK_WdogRootmuxVpuPll = 3U, /*!< WDOG Clock from VPU DLL.*/
688 kCLOCK_WdogRootmuxSystemPll2Div8 = 4U, /*!< WDOG Clock from SYSTEM PLL2 divided by 8.*/
689 kCLOCK_WdogRootmuxSystemPll3 = 5U, /*!< WDOG Clock from SYSTEM PLL3.*/
690 kCLOCK_WdogRootmuxSystemPll1Div10 = 6U, /*!< WDOG Clock from SYSTEM PLL1 divided by 10.*/
691 kCLOCK_WdogRootmuxSystemPll2Div6 = 7U, /*!< WDOG Clock from SYSTEM PLL2 divided by 6.*/
692 } clock_rootmux_wdog_clk_sel_t;
693
694 /*! @brief Root clock select enumeration for PWM peripheral. */
695 typedef enum _clock_rootmux_pwm_clk_sel
696 {
697 kCLOCK_PwmRootmuxOsc25m = 0U, /*!< PWM Clock from OSC 25M.*/
698 kCLOCK_PwmRootmuxSysPll2Div10 = 1U, /*!< PWM Clock from SYSTEM PLL2 divided by 10.*/
699 kCLOCK_PwmRootmuxSysPll1Div5 = 2U, /*!< PWM Clock from SYSTEM PLL1 divided by 5.*/
700 kCLOCK_PwmRootmuxSysPll1Div20 = 3U, /*!< PWM Clock from SYSTEM PLL1 divided by 20.*/
701 kCLOCK_PwmRootmuxSystemPll3 = 4U, /*!< PWM Clock from SYSTEM PLL3.*/
702 kCLOCK_PwmRootmuxExtClk12 = 5U, /*!< PWM Clock from External Clock1, External Clock2.*/
703 kCLOCK_PwmRootmuxSystemPll1Div10 = 6U, /*!< PWM Clock from SYSTEM PLL1 divided by 10.*/
704 kCLOCK_PwmRootmuxVideoPll1 = 7U, /*!< PWM Clock from VIDEO PLL1.*/
705 } clock_rootmux_Pwm_clk_sel_t;
706
707 /*! @brief Root clock select enumeration for SAI peripheral. */
708 typedef enum _clock_rootmux_sai_clk_sel
709 {
710 kCLOCK_SaiRootmuxOsc25m = 0U, /*!< SAI Clock from OSC 25M.*/
711 kCLOCK_SaiRootmuxAudioPll1 = 1U, /*!< SAI Clock from AUDIO PLL1.*/
712 kCLOCK_SaiRootmuxAudioPll2 = 2U, /*!< SAI Clock from AUDIO PLL2.*/
713 kCLOCK_SaiRootmuxVideoPll1 = 3U, /*!< SAI Clock from VIDEO PLL1.*/
714 kCLOCK_SaiRootmuxSysPll1Div6 = 4U, /*!< SAI Clock from SYSTEM PLL1 divided by 6.*/
715 kCLOCK_SaiRootmuxOsc27m = 5U, /*!< SAI Clock from OSC 27M.*/
716 kCLOCK_SaiRootmuxExtClk123 = 6U, /*!< SAI Clock from External Clock1, External Clock2, External Clock3.*/
717 kCLOCK_SaiRootmuxExtClk234 = 7U, /*!< SAI Clock from External Clock2, External Clock3, External Clock4.*/
718 } clock_rootmux_sai_clk_sel_t;
719
720 /*! @brief Root clock select enumeration for NOC CLK. */
721 typedef enum _clock_rootmux_noc_clk_sel
722 {
723 kCLOCK_NocRootmuxOsc25m = 0U, /*!< NOC Clock from OSC 25M.*/
724 kCLOCK_NocRootmuxSysPll1 = 1U, /*!< NOC Clock from SYSTEM PLL1.*/
725 kCLOCK_NocRootmuxSysPll3 = 2U, /*!< NOC Clock from SYSTEM PLL3.*/
726 kCLOCK_NocRootmuxSysPll2 = 3U, /*!< NOC Clock from SYSTEM PLL2.*/
727 kCLOCK_NocRootmuxSysPll2Div2 = 4U, /*!< NOC Clock from SYSTEM PLL2 divided by 2.*/
728 kCLOCK_NocRootmuxAudioPll1 = 5U, /*!< NOC Clock from AUDIO PLL1.*/
729 kCLOCK_NocRootmuxVideoPll1 = 6U, /*!< NOC Clock from VIDEO PLL1.*/
730 kCLOCK_NocRootmuxAudioPll2 = 7U, /*!< NOC Clock from AUDIO PLL2.*/
731
732 } clock_rootmux_noc_clk_sel_t;
733
734 /*! @brief CCM PLL gate control. */
735 typedef enum _clock_pll_gate
736 {
737 kCLOCK_ArmPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /*!< ARM PLL Gate.*/
738
739 kCLOCK_GpuPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /*!< GPU PLL Gate.*/
740 kCLOCK_VpuPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /*!< VPU PLL Gate.*/
741 kCLOCK_DramPllGate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /*!< DRAM PLL1 Gate.*/
742
743 kCLOCK_SysPll1Gate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /*!< SYSTEM PLL1 Gate.*/
744 kCLOCK_SysPll1Div2Gate =
745 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /*!< SYSTEM PLL1 Div2 Gate.*/
746 kCLOCK_SysPll1Div3Gate =
747 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /*!< SYSTEM PLL1 Div3 Gate.*/
748 kCLOCK_SysPll1Div4Gate =
749 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /*!< SYSTEM PLL1 Div4 Gate.*/
750 kCLOCK_SysPll1Div5Gate =
751 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /*!< SYSTEM PLL1 Div5 Gate.*/
752 kCLOCK_SysPll1Div6Gate =
753 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /*!< SYSTEM PLL1 Div6 Gate.*/
754 kCLOCK_SysPll1Div8Gate =
755 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[22].PLL_CTRL), /*!< SYSTEM PLL1 Div8 Gate.*/
756 kCLOCK_SysPll1Div10Gate =
757 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[23].PLL_CTRL), /*!< SYSTEM PLL1 Div10 Gate.*/
758 kCLOCK_SysPll1Div20Gate =
759 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[24].PLL_CTRL), /*!< SYSTEM PLL1 Div20 Gate.*/
760
761 kCLOCK_SysPll2Gate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[25].PLL_CTRL), /*!< SYSTEM PLL2 Gate.*/
762 kCLOCK_SysPll2Div2Gate =
763 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[26].PLL_CTRL), /*!< SYSTEM PLL2 Div2 Gate.*/
764 kCLOCK_SysPll2Div3Gate =
765 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[27].PLL_CTRL), /*!< SYSTEM PLL2 Div3 Gate.*/
766 kCLOCK_SysPll2Div4Gate =
767 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[28].PLL_CTRL), /*!< SYSTEM PLL2 Div4 Gate.*/
768 kCLOCK_SysPll2Div5Gate =
769 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[29].PLL_CTRL), /*!< SYSTEM PLL2 Div5 Gate.*/
770 kCLOCK_SysPll2Div6Gate =
771 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[30].PLL_CTRL), /*!< SYSTEM PLL2 Div6 Gate.*/
772 kCLOCK_SysPll2Div8Gate =
773 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[31].PLL_CTRL), /*!< SYSTEM PLL2 Div8 Gate.*/
774 kCLOCK_SysPll2Div10Gate =
775 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[32].PLL_CTRL), /*!< SYSTEM PLL2 Div10 Gate.*/
776 kCLOCK_SysPll2Div20Gate =
777 (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[33].PLL_CTRL), /*!< SYSTEM PLL2 Div20 Gate.*/
778
779 kCLOCK_SysPll3Gate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[34].PLL_CTRL), /*!< SYSTEM PLL3 Gate.*/
780
781 kCLOCK_AudioPll1Gate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[35].PLL_CTRL), /*!< AUDIO PLL1 Gate.*/
782 kCLOCK_AudioPll2Gate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[36].PLL_CTRL), /*!< AUDIO PLL2 Gate.*/
783 kCLOCK_VideoPll1Gate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[37].PLL_CTRL), /*!< VIDEO PLL1 Gate.*/
784 kCLOCK_VideoPll2Gate = (uint32_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[38].PLL_CTRL), /*!< VIDEO PLL2 Gate.*/
785 } clock_pll_gate_t;
786
787 /*! @brief CCM gate control value. */
788 typedef enum _clock_gate_value
789 {
790 kCLOCK_ClockNotNeeded = 0x0U, /*!< Clock always disabled.*/
791 kCLOCK_ClockNeededRun = 0x1111U, /*!< Clock enabled when CPU is running.*/
792 kCLOCK_ClockNeededRunWait = 0x2222U, /*!< Clock enabled when CPU is running or in WAIT mode.*/
793 kCLOCK_ClockNeededAll = 0x3333U, /*!< Clock always enabled.*/
794 } clock_gate_value_t;
795
796 /*!
797 * @brief PLL control names for PLL bypass.
798 *
799 * These constants define the PLL control names for PLL bypass.\n
800 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
801 * - 16:20: bypass bit shift.
802 */
803 typedef enum _clock_pll_bypass_ctrl
804 {
805 kCLOCK_AudioPll1BypassCtrl = CCM_ANALOG_TUPLE(
806 AUDIO_PLL1_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL1 bypass Control.*/
807 kCLOCK_AudioPll2BypassCtrl = CCM_ANALOG_TUPLE(
808 AUDIO_PLL2_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL2 bypass Control.*/
809 kCLOCK_VideoPll1BypassCtrl = CCM_ANALOG_TUPLE(
810 VIDEO_PLL1_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Video Pll1 bypass Control.*/
811 kCLOCK_GpuPLLPwrBypassCtrl = CCM_ANALOG_TUPLE(
812 GPU_PLL_CFG0_OFFSET, CCM_ANALOG_GPU_PLL_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Gpu PLL bypass Control.*/
813 kCLOCK_VpuPllPwrBypassCtrl = CCM_ANALOG_TUPLE(
814 VPU_PLL_CFG0_OFFSET, CCM_ANALOG_VPU_PLL_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Vpu PLL bypass Control.*/
815 kCLOCK_ArmPllPwrBypassCtrl = CCM_ANALOG_TUPLE(
816 ARM_PLL_CFG0_OFFSET, CCM_ANALOG_ARM_PLL_CFG0_PLL_BYPASS_SHIFT), /*!< CCM Arm PLL bypass Control.*/
817
818 kCLOCK_SysPll1InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
819 SYS_PLL1_CFG0_OFFSET,
820 CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM System PLL1 internal pll1 bypass Control.*/
821 kCLOCK_SysPll1InternalPll2BypassCtrl = CCM_ANALOG_TUPLE(
822 SYS_PLL1_CFG0_OFFSET,
823 CCM_ANALOG_SYS_PLL1_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM System PLL1 internal pll2 bypass Control.*/
824
825 kCLOCK_SysPll2InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
826 SYS_PLL2_CFG0_OFFSET,
827 CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog System PLL1 internal pll1 bypass Control.*/
828 kCLOCK_SysPll2InternalPll2BypassCtrl = CCM_ANALOG_TUPLE(
829 SYS_PLL2_CFG0_OFFSET,
830 CCM_ANALOG_SYS_PLL2_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog VIDEO System PLL1 internal pll1 bypass Control.*/
831
832 kCLOCK_SysPll3InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
833 SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog VIDEO PLL bypass Control.*/
834 kCLOCK_SysPll3InternalPll2BypassCtrl = CCM_ANALOG_TUPLE(
835 SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog VIDEO PLL bypass Control.*/
836
837 kCLOCK_VideoPll2InternalPll1BypassCtrl =
838 CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET,
839 CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/
840 kCLOCK_VideoPll2InternalPll2BypassCtrl =
841 CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET,
842 CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/
843
844 kCLOCK_DramPllInternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
845 DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS1_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/
846 kCLOCK_DramPllInternalPll2BypassCtrl = CCM_ANALOG_TUPLE(
847 DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_BYPASS2_SHIFT), /*!< CCM Analog 480M PLL bypass Control.*/
848 } clock_pll_bypass_ctrl_t;
849
850 /*!
851 * @brief PLL clock names for clock enable/disable settings.
852 *
853 * These constants define the PLL clock names for PLL clock enable/disable operations.\n
854 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
855 * - 16:20: Clock enable bit shift.
856 */
857 typedef enum _ccm_analog_pll_clke
858 {
859 kCLOCK_AudioPll1Clke =
860 CCM_ANALOG_TUPLE(AUDIO_PLL1_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_CLKE_SHIFT), /*!< Audio pll1 clke */
861 kCLOCK_AudioPll2Clke =
862 CCM_ANALOG_TUPLE(AUDIO_PLL2_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_CLKE_SHIFT), /*!< Audio pll2 clke */
863 kCLOCK_VideoPll1Clke =
864 CCM_ANALOG_TUPLE(VIDEO_PLL1_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_CLKE_SHIFT), /*!< Video pll1 clke */
865 kCLOCK_GpuPllClke =
866 CCM_ANALOG_TUPLE(GPU_PLL_CFG0_OFFSET, CCM_ANALOG_GPU_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Gpu pll clke */
867 kCLOCK_VpuPllClke =
868 CCM_ANALOG_TUPLE(VPU_PLL_CFG0_OFFSET, CCM_ANALOG_VPU_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Vpu pll clke */
869 kCLOCK_ArmPllClke =
870 CCM_ANALOG_TUPLE(ARM_PLL_CFG0_OFFSET, CCM_ANALOG_ARM_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Arm pll clke */
871
872 kCLOCK_SystemPll1Clke =
873 CCM_ANALOG_TUPLE(SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_CLKE_SHIFT), /*!< System pll1 clke */
874 kCLOCK_SystemPll1Div2Clke = CCM_ANALOG_TUPLE(
875 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV2_CLKE_SHIFT), /*!< System pll1 Div2 clke */
876 kCLOCK_SystemPll1Div3Clke = CCM_ANALOG_TUPLE(
877 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV3_CLKE_SHIFT), /*!< System pll1 Div3 clke */
878 kCLOCK_SystemPll1Div4Clke = CCM_ANALOG_TUPLE(
879 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV4_CLKE_SHIFT), /*!< System pll1 Div4 clke */
880 kCLOCK_SystemPll1Div5Clke = CCM_ANALOG_TUPLE(
881 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV5_CLKE_SHIFT), /*!< System pll1 Div5 clke */
882 kCLOCK_SystemPll1Div6Clke = CCM_ANALOG_TUPLE(
883 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV6_CLKE_SHIFT), /*!< System pll1 Div6 clke */
884 kCLOCK_SystemPll1Div8Clke = CCM_ANALOG_TUPLE(
885 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV8_CLKE_SHIFT), /*!< System pll1 Div8 clke */
886 kCLOCK_SystemPll1Div10Clke = CCM_ANALOG_TUPLE(
887 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV10_CLKE_SHIFT), /*!< System pll1 Div10 clke */
888 kCLOCK_SystemPll1Div20Clke = CCM_ANALOG_TUPLE(
889 SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_DIV20_CLKE_SHIFT), /*!< System pll1 Div20 clke */
890
891 kCLOCK_SystemPll2Clke =
892 CCM_ANALOG_TUPLE(SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_CLKE_SHIFT), /*!< System pll2 clke */
893 kCLOCK_SystemPll2Div2Clke = CCM_ANALOG_TUPLE(
894 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV2_CLKE_SHIFT), /*!< System pll2 Div2 clke */
895 kCLOCK_SystemPll2Div3Clke = CCM_ANALOG_TUPLE(
896 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV3_CLKE_SHIFT), /*!< System pll2 Div3 clke */
897 kCLOCK_SystemPll2Div4Clke = CCM_ANALOG_TUPLE(
898 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV4_CLKE_SHIFT), /*!< System pll2 Div4 clke */
899 kCLOCK_SystemPll2Div5Clke = CCM_ANALOG_TUPLE(
900 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV5_CLKE_SHIFT), /*!< System pll2 Div5 clke */
901 kCLOCK_SystemPll2Div6Clke = CCM_ANALOG_TUPLE(
902 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV6_CLKE_SHIFT), /*!< System pll2 Div6 clke */
903 kCLOCK_SystemPll2Div8Clke = CCM_ANALOG_TUPLE(
904 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV8_CLKE_SHIFT), /*!< System pll2 Div8 clke */
905 kCLOCK_SystemPll2Div10Clke = CCM_ANALOG_TUPLE(
906 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV10_CLKE_SHIFT), /*!< System pll2 Div10 clke */
907 kCLOCK_SystemPll2Div20Clke = CCM_ANALOG_TUPLE(
908 SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_DIV20_CLKE_SHIFT), /*!< System pll2 Div20 clke */
909
910 kCLOCK_SystemPll3Clke =
911 CCM_ANALOG_TUPLE(SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_CLKE_SHIFT), /*!< System pll3 clke */
912 kCLOCK_VideoPll2Clke =
913 CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_CLKE_SHIFT), /*!< Video pll2 clke */
914 kCLOCK_DramPllClke =
915 CCM_ANALOG_TUPLE(DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_CLKE_SHIFT), /*!< Dram pll clke */
916 kCLOCK_OSC25MClke =
917 CCM_ANALOG_TUPLE(OSC_MISC_CFG_OFFSET, CCM_ANALOG_OSC_MISC_CFG_OSC_25M_CLKE_SHIFT), /*!< OSC25M clke */
918 kCLOCK_OSC27MClke =
919 CCM_ANALOG_TUPLE(OSC_MISC_CFG_OFFSET, CCM_ANALOG_OSC_MISC_CFG_OSC_27M_CLKE_SHIFT), /*!< OSC27M clke */
920
921 } clock_pll_clke_t;
922
923 /*!
924 * @brief ANALOG Power down override control.
925 */
926 typedef enum _clock_pll_ctrl
927 {
928 kCLOCK_AudioPll1Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL1_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_PD_SHIFT),
929 kCLOCK_AudioPll2Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL2_CFG0_OFFSET, CCM_ANALOG_AUDIO_PLL2_CFG0_PLL_PD_SHIFT),
930 kCLOCK_VideoPll1Ctrl = CCM_ANALOG_TUPLE(VIDEO_PLL1_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL1_CFG0_PLL_PD_SHIFT),
931 kCLOCK_GpuPllCtrl = CCM_ANALOG_TUPLE(GPU_PLL_CFG0_OFFSET, CCM_ANALOG_GPU_PLL_CFG0_PLL_PD_SHIFT),
932 kCLOCK_VpuPllCtrl = CCM_ANALOG_TUPLE(VPU_PLL_CFG0_OFFSET, CCM_ANALOG_VPU_PLL_CFG0_PLL_PD_SHIFT),
933 kCLOCK_ArmPllCtrl = CCM_ANALOG_TUPLE(ARM_PLL_CFG0_OFFSET, CCM_ANALOG_ARM_PLL_CFG0_PLL_PD_SHIFT),
934
935 kCLOCK_SystemPll1Ctrl = CCM_ANALOG_TUPLE(SYS_PLL1_CFG0_OFFSET, CCM_ANALOG_SYS_PLL1_CFG0_PLL_PD_SHIFT),
936 kCLOCK_SystemPll2Ctrl = CCM_ANALOG_TUPLE(SYS_PLL2_CFG0_OFFSET, CCM_ANALOG_SYS_PLL2_CFG0_PLL_PD_SHIFT),
937 kCLOCK_SystemPll3Ctrl = CCM_ANALOG_TUPLE(SYS_PLL3_CFG0_OFFSET, CCM_ANALOG_SYS_PLL3_CFG0_PLL_PD_SHIFT),
938 kCLOCK_VideoPll2Ctrl = CCM_ANALOG_TUPLE(VIDEO_PLL2_CFG0_OFFSET, CCM_ANALOG_VIDEO_PLL2_CFG0_PLL_PD_SHIFT),
939 kCLOCK_DramPllCtrl = CCM_ANALOG_TUPLE(DRAM_PLL_CFG0_OFFSET, CCM_ANALOG_DRAM_PLL_CFG0_PLL_PD_SHIFT),
940
941 } clock_pll_ctrl_t;
942
943 /*! @brief OSC work mode. */
944 enum _osc_mode
945 {
946 kOSC_OscMode = 0U, /*!< OSC oscillator mode */
947 kOSC_ExtMode = 1U, /*!< OSC external mode */
948 };
949
950 /*! @brief OSC 32K input select. */
951 typedef enum _osc32_src
952 {
953 kOSC32_Src25MDiv800 = 0U, /*!< source from 25M divide 800 */
954 kOSC32_SrcRTC, /*!< source from RTC */
955 } osc32_src_t;
956
957 /*! @brief PLL reference clock select. */
958 enum _ccm_analog_pll_ref_clk
959 {
960 kANALOG_PllRefOsc25M = 0U, /*!< reference OSC 25M */
961 kANALOG_PllRefOsc27M = 1U, /*!< reference OSC 27M */
962 kANALOG_PllRefOscHdmiPhy27M = 2U, /*!< reference HDMI PHY 27M */
963 kANALOG_PllRefClkPN = 3U, /*!< reference CLK_P_N */
964 };
965
966 /*!
967 * @brief OSC configuration structure.
968 */
969 typedef struct _osc_config
970 {
971 uint8_t oscMode; /*!< ext or osc mode */
972 uint8_t oscDiv; /*!< osc divider */
973 } osc_config_t;
974
975 /*!
976 * @brief Fractional-N PLL configuration.
977 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
978 * value
979 */
980 typedef struct _ccm_analog_frac_pll_config
981 {
982 uint8_t refSel; /*!< pll reference clock sel */
983
984 uint8_t refDiv; /*!< A 6bit divider to make sure the REF must be within the range 10MHZ~300MHZ */
985
986 uint32_t fractionDiv; /*!< Inlcude fraction divider(divider:1:2^24) output clock
987 range is 2000MHZ-4000MHZ */
988 uint8_t intDiv; /*and integer divide(divider: 1:32)*/
989 uint8_t outDiv; /*!< output clock divide, output clock range is 30MHZ to 2000MHZ, must be a even value */
990
991 } ccm_analog_frac_pll_config_t;
992
993 /*!
994 * @brief SSCG PLL configuration.
995 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
996 * value
997 */
998 typedef struct _ccm_analog_sscg_pll_config
999 {
1000 uint8_t refSel; /*!< pll reference clock sel */
1001
1002 uint8_t refDiv1; /*!< A 3bit divider to make sure the REF must be within the range 25MHZ~235MHZ ,post_divide REF
1003 must be within the range 25MHZ~54MHZ */
1004 uint8_t refDiv2; /*!< A 6bit divider to make sure the post_divide REF must be within the range 54MHZ~75MHZ */
1005
1006 uint32_t loopDivider1; /*!< A 6bit internal PLL1 feedback clock divider, output clock range must be within the range
1007 1600MHZ-2400MHZ */
1008 uint32_t loopDivider2; /*!< A 6bit internal PLL2 feedback clock divider, output clock range must be within the range
1009 1200MHZ-2400MHZ */
1010
1011 uint8_t outDiv; /*!< A 6bit output clock divide, output clock range is 20MHZ to 1200MHZ */
1012
1013 } ccm_analog_sscg_pll_config_t;
1014
1015 /*******************************************************************************
1016 * API
1017 ******************************************************************************/
1018
1019 #if defined(__cplusplus)
1020 extern "C" {
1021 #endif
1022
1023 /*!
1024 * @name CCM Root Clock Setting
1025 * @{
1026 */
1027
1028 /*!
1029 * @brief Set clock root mux.
1030 * User maybe need to set more than one mux ROOT according to the clock tree
1031 * description in the reference manual.
1032 *
1033 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
1034 * @param mux Root mux value (see _ccm_rootmux_xxx enumeration).
1035 */
CLOCK_SetRootMux(clock_root_control_t rootClk,uint32_t mux)1036 static inline void CLOCK_SetRootMux(clock_root_control_t rootClk, uint32_t mux)
1037 {
1038 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux);
1039 }
1040
1041 /*!
1042 * @brief Get clock root mux.
1043 * In order to get the clock source of root, user maybe need to get more than one
1044 * ROOT's mux value to obtain the final clock source of root.
1045 *
1046 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
1047 * @return Root mux value (see _ccm_rootmux_xxx enumeration).
1048 */
CLOCK_GetRootMux(clock_root_control_t rootClk)1049 static inline uint32_t CLOCK_GetRootMux(clock_root_control_t rootClk)
1050 {
1051 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT;
1052 }
1053
1054 /*!
1055 * @brief Enable clock root
1056 *
1057 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration)
1058 */
CLOCK_EnableRoot(clock_root_control_t rootClk)1059 static inline void CLOCK_EnableRoot(clock_root_control_t rootClk)
1060 {
1061 CCM_REG_SET(rootClk) = CCM_TARGET_ROOT_SET_ENABLE_MASK;
1062 }
1063
1064 /*!
1065 * @brief Disable clock root
1066 *
1067 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
1068 */
CLOCK_DisableRoot(clock_root_control_t rootClk)1069 static inline void CLOCK_DisableRoot(clock_root_control_t rootClk)
1070 {
1071 CCM_REG_CLR(rootClk) = CCM_TARGET_ROOT_CLR_ENABLE_MASK;
1072 }
1073
1074 /*!
1075 * @brief Check whether clock root is enabled
1076 *
1077 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
1078 * @return CCM root enabled or not.
1079 * - true: Clock root is enabled.
1080 * - false: Clock root is disabled.
1081 */
CLOCK_IsRootEnabled(clock_root_control_t rootClk)1082 static inline bool CLOCK_IsRootEnabled(clock_root_control_t rootClk)
1083 {
1084 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK);
1085 }
1086
1087 /*!
1088 * @brief Update clock root in one step, for dynamical clock switching
1089 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
1090 *
1091 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
1092 * @param mux root mux value (see _ccm_rootmux_xxx enumeration)
1093 * @param pre Pre divider value (0-7, divider=n+1)
1094 * @param post Post divider value (0-63, divider=n+1)
1095 */
1096 void CLOCK_UpdateRoot(clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post);
1097
1098 /*!
1099 * @brief Set root clock divider
1100 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
1101 *
1102 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
1103 * @param pre Pre divider value (1-8)
1104 * @param post Post divider value (1-64)
1105 */
1106 void CLOCK_SetRootDivider(clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post);
1107
1108 /*!
1109 * @brief Get clock root PRE_PODF.
1110 * In order to get the clock source of root, user maybe need to get more than one
1111 * ROOT's mux value to obtain the final clock source of root.
1112 *
1113 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
1114 * @return Root Pre divider value.
1115 */
CLOCK_GetRootPreDivider(clock_root_control_t rootClk)1116 static inline uint32_t CLOCK_GetRootPreDivider(clock_root_control_t rootClk)
1117 {
1118 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U;
1119 }
1120
1121 /*!
1122 * @brief Get clock root POST_PODF.
1123 * In order to get the clock source of root, user maybe need to get more than one
1124 * ROOT's mux value to obtain the final clock source of root.
1125 *
1126 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
1127 * @return Root Post divider value.
1128 */
CLOCK_GetRootPostDivider(clock_root_control_t rootClk)1129 static inline uint32_t CLOCK_GetRootPostDivider(clock_root_control_t rootClk)
1130 {
1131 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + 1U;
1132 }
1133
1134 /*!
1135 * @name OSC setting
1136 * @{
1137 */
1138 /*!
1139 * @brief OSC25M init
1140 *
1141 * @param config osc configuration.
1142 */
1143 void CLOCK_InitOSC25M(const osc_config_t *config);
1144
1145 /*!
1146 * @brief OSC25M deinit
1147 *
1148 */
1149 void CLOCK_DeinitOSC25M(void);
1150
1151 /*!
1152 * @brief OSC27M init
1153 * @param config osc configuration.
1154 *
1155 */
1156 void CLOCK_InitOSC27M(const osc_config_t *config);
1157
1158 /*!
1159 * @brief OSC27M deinit
1160 *
1161 */
1162 void CLOCK_DeinitOSC27M(void);
1163
1164 /*!
1165 * @brief switch 32KHZ OSC input
1166 * @param sel OSC32 input clock select
1167 */
CLOCK_SwitchOSC32Src(osc32_src_t sel)1168 static inline void CLOCK_SwitchOSC32Src(osc32_src_t sel)
1169 {
1170 CCM_ANALOG->OSC_MISC_CFG = (CCM_ANALOG->OSC_MISC_CFG & (~CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK)) | (uint32_t)sel;
1171 }
1172
1173 /*!
1174 * @name CCM Gate Control
1175 * @{
1176 */
1177
1178 /*!
1179 * @brief Set PLL or CCGR gate control
1180 *
1181 * @param ccmGate Gate control (see @ref clock_pll_gate_t and @ref clock_ip_name_t enumeration)
1182 * @param control Gate control value (see @ref clock_gate_value_t)
1183 */
CLOCK_ControlGate(uint32_t ccmGate,clock_gate_value_t control)1184 static inline void CLOCK_ControlGate(uint32_t ccmGate, clock_gate_value_t control)
1185 {
1186 CCM_REG(ccmGate) = (uint32_t)control;
1187 }
1188
1189 /*!
1190 * @brief Enable CCGR clock gate and root clock gate for each module
1191 * User should set specific gate for each module according to the description
1192 * of the table of system clocks, gating and override in CCM chapter of
1193 * reference manual. Take care of that one module may need to set more than
1194 * one clock gate.
1195 *
1196 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
1197 */
1198 void CLOCK_EnableClock(clock_ip_name_t ccmGate);
1199
1200 /*!
1201 * @brief Disable CCGR clock gate for the each module
1202 * User should set specific gate for each module according to the description
1203 * of the table of system clocks, gating and override in CCM chapter of
1204 * reference manual. Take care of that one module may need to set more than
1205 * one clock gate.
1206 *
1207 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
1208 */
1209 void CLOCK_DisableClock(clock_ip_name_t ccmGate);
1210
1211 /*!
1212 * @name CCM Analog PLL Operatoin Functions
1213 * @{
1214 */
1215
1216 /*!
1217 * @brief Power up PLL
1218 *
1219 * @param base CCM_ANALOG base pointer.
1220 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
1221 */
CLOCK_PowerUpPll(CCM_ANALOG_Type * base,clock_pll_ctrl_t pllControl)1222 static inline void CLOCK_PowerUpPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
1223 {
1224 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
1225 }
1226
1227 /*!
1228 * @brief Power down PLL
1229 *
1230 * @param base CCM_ANALOG base pointer.
1231 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
1232 */
CLOCK_PowerDownPll(CCM_ANALOG_Type * base,clock_pll_ctrl_t pllControl)1233 static inline void CLOCK_PowerDownPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
1234 {
1235 CCM_ANALOG_TUPLE_REG(base, pllControl) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl);
1236 }
1237
1238 /*!
1239 * @brief PLL bypass setting
1240 *
1241 * @param base CCM_ANALOG base pointer.
1242 * @param pllControl PLL control name (see ccm_analog_pll_control_t enumeration)
1243 * @param bypass Bypass the PLL.
1244 * - true: Bypass the PLL.
1245 * - false: Do not bypass the PLL.
1246 */
CLOCK_SetPllBypass(CCM_ANALOG_Type * base,clock_pll_bypass_ctrl_t pllControl,bool bypass)1247 static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl, bool bypass)
1248 {
1249 if (bypass)
1250 {
1251 CCM_ANALOG_TUPLE_REG(base, pllControl) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl);
1252 }
1253 else
1254 {
1255 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
1256 }
1257 }
1258
1259 /*!
1260 * @brief Check if PLL is bypassed
1261 *
1262 * @param base CCM_ANALOG base pointer.
1263 * @param pllControl PLL control name (see ccm_analog_pll_control_t enumeration)
1264 * @return PLL bypass status.
1265 * - true: The PLL is bypassed.
1266 * - false: The PLL is not bypassed.
1267 */
CLOCK_IsPllBypassed(CCM_ANALOG_Type * base,clock_pll_bypass_ctrl_t pllControl)1268 static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl)
1269 {
1270 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl)));
1271 }
1272
1273 /*!
1274 * @brief Check if PLL clock is locked
1275 *
1276 * @param base CCM_ANALOG base pointer.
1277 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
1278 * @return PLL lock status.
1279 * - true: The PLL clock is locked.
1280 * - false: The PLL clock is not locked.
1281 */
CLOCK_IsPllLocked(CCM_ANALOG_Type * base,clock_pll_ctrl_t pllControl)1282 static inline bool CLOCK_IsPllLocked(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
1283 {
1284 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_AUDIO_PLL1_CFG0_PLL_LOCK_MASK);
1285 }
1286
1287 /*!
1288 * @brief Enable PLL clock
1289 *
1290 * @param base CCM_ANALOG base pointer.
1291 * @param pllClock PLL clock name (see ccm_analog_pll_clock_t enumeration)
1292 */
CLOCK_EnableAnalogClock(CCM_ANALOG_Type * base,clock_pll_clke_t pllClock)1293 static inline void CLOCK_EnableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
1294 {
1295 CCM_ANALOG_TUPLE_REG(base, pllClock) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock);
1296 }
1297
1298 /*!
1299 * @brief Disable PLL clock
1300 *
1301 * @param base CCM_ANALOG base pointer.
1302 * @param pllClock PLL clock name (see ccm_analog_pll_clock_t enumeration)
1303 */
CLOCK_DisableAnalogClock(CCM_ANALOG_Type * base,clock_pll_clke_t pllClock)1304 static inline void CLOCK_DisableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
1305 {
1306 CCM_ANALOG_TUPLE_REG(base, pllClock) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock));
1307 }
1308
1309 /*!
1310 * @brief Override PLL clock output enable
1311 *
1312 * @param base CCM_ANALOG base pointer.
1313 * @param ovClock PLL clock name (see @ref clock_pll_clke_t enumeration)
1314 * @param override Override the PLL.
1315 * - true: Override the PLL clke, CCM will handle it.
1316 * - false: Do not override the PLL clke.
1317 */
CLOCK_OverrideAnalogClke(CCM_ANALOG_Type * base,clock_pll_clke_t ovClock,bool override)1318 static inline void CLOCK_OverrideAnalogClke(CCM_ANALOG_Type *base, clock_pll_clke_t ovClock, bool override)
1319 {
1320 if (override)
1321 {
1322 CCM_ANALOG_TUPLE_REG(base, ovClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL);
1323 }
1324 else
1325 {
1326 CCM_ANALOG_TUPLE_REG(base, ovClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL));
1327 }
1328 }
1329
1330 /*!
1331 * @brief Override PLL power down
1332 *
1333 * @param base CCM_ANALOG base pointer.
1334 * @param pdClock PLL clock name (see @ref clock_pll_ctrl_t enumeration)
1335 * @param override Override the PLL.
1336 * - true: Override the PLL clke, CCM will handle it.
1337 * - false: Do not override the PLL clke.
1338 */
CLOCK_OverridePllPd(CCM_ANALOG_Type * base,clock_pll_ctrl_t pdClock,bool override)1339 static inline void CLOCK_OverridePllPd(CCM_ANALOG_Type *base, clock_pll_ctrl_t pdClock, bool override)
1340 {
1341 if (override)
1342 {
1343 CCM_ANALOG_TUPLE_REG(base, pdClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL);
1344 }
1345 else
1346 {
1347 CCM_ANALOG_TUPLE_REG(base, pdClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL));
1348 }
1349 }
1350
1351 /*!
1352 * @brief Initializes the ANALOG ARM PLL.
1353 *
1354 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1355 *
1356 * @note This function can't detect whether the Arm PLL has been enabled and
1357 * used by some IPs.
1358 */
1359 void CLOCK_InitArmPll(const ccm_analog_frac_pll_config_t *config);
1360
1361 /*!
1362 * @brief De-initialize the ARM PLL.
1363 */
1364 void CLOCK_DeinitArmPll(void);
1365
1366 /*!
1367 * @brief Initializes the ANALOG SYS PLL1.
1368 *
1369 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1370 *
1371 * @note This function can't detect whether the SYS PLL has been enabled and
1372 * used by some IPs.
1373 */
1374 void CLOCK_InitSysPll1(const ccm_analog_sscg_pll_config_t *config);
1375
1376 /*!
1377 * @brief De-initialize the System PLL1.
1378 */
1379 void CLOCK_DeinitSysPll1(void);
1380
1381 /*!
1382 * @brief Initializes the ANALOG SYS PLL2.
1383 *
1384 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1385 *
1386 * @note This function can't detect whether the SYS PLL has been enabled and
1387 * used by some IPs.
1388 */
1389 void CLOCK_InitSysPll2(const ccm_analog_sscg_pll_config_t *config);
1390
1391 /*!
1392 * @brief De-initialize the System PLL2.
1393 */
1394 void CLOCK_DeinitSysPll2(void);
1395
1396 /*!
1397 * @brief Initializes the ANALOG SYS PLL3.
1398 *
1399 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1400 *
1401 * @note This function can't detect whether the SYS PLL has been enabled and
1402 * used by some IPs.
1403 */
1404 void CLOCK_InitSysPll3(const ccm_analog_sscg_pll_config_t *config);
1405
1406 /*!
1407 * @brief De-initialize the System PLL3.
1408 */
1409 void CLOCK_DeinitSysPll3(void);
1410
1411 /*!
1412 * @brief Initializes the ANALOG DDR PLL.
1413 *
1414 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1415 *
1416 * @note This function can't detect whether the DDR PLL has been enabled and
1417 * used by some IPs.
1418 */
1419 void CLOCK_InitDramPll(const ccm_analog_sscg_pll_config_t *config);
1420
1421 /*!
1422 * @brief De-initialize the Dram PLL.
1423 */
1424 void CLOCK_DeinitDramPll(void);
1425
1426 /*!
1427 * @brief Initializes the ANALOG AUDIO PLL1.
1428 *
1429 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1430 *
1431 * @note This function can't detect whether the AUDIO PLL has been enabled and
1432 * used by some IPs.
1433 */
1434 void CLOCK_InitAudioPll1(const ccm_analog_frac_pll_config_t *config);
1435
1436 /*!
1437 * @brief De-initialize the Audio PLL1.
1438 */
1439 void CLOCK_DeinitAudioPll1(void);
1440
1441 /*!
1442 * @brief Initializes the ANALOG AUDIO PLL2.
1443 *
1444 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1445 *
1446 * @note This function can't detect whether the AUDIO PLL has been enabled and
1447 * used by some IPs.
1448 */
1449 void CLOCK_InitAudioPll2(const ccm_analog_frac_pll_config_t *config);
1450
1451 /*!
1452 * @brief De-initialize the Audio PLL2.
1453 */
1454 void CLOCK_DeinitAudioPll2(void);
1455
1456 /*!
1457 * @brief Initializes the ANALOG VIDEO PLL1.
1458 *
1459 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1460 *
1461 */
1462 void CLOCK_InitVideoPll1(const ccm_analog_frac_pll_config_t *config);
1463
1464 /*!
1465 * @brief De-initialize the Video PLL1.
1466 */
1467 void CLOCK_DeinitVideoPll1(void);
1468
1469 /*!
1470 * @brief Initializes the ANALOG VIDEO PLL2.
1471 *
1472 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1473 *
1474 * @note This function can't detect whether the VIDEO PLL has been enabled and
1475 * used by some IPs.
1476 */
1477 void CLOCK_InitVideoPll2(const ccm_analog_sscg_pll_config_t *config);
1478
1479 /*!
1480 * @brief De-initialize the Video PLL2.
1481 */
1482 void CLOCK_DeinitVideoPll2(void);
1483
1484 /*!
1485 * @brief Initializes the ANALOG SSCG PLL.
1486 *
1487 * @param base CCM ANALOG base address
1488 * @param config Pointer to the configuration structure(see @ref ccm_analog_sscg_pll_config_t enumeration).
1489 * @param type sscg pll type
1490 *
1491 */
1492 void CLOCK_InitSSCGPll(CCM_ANALOG_Type *base, const ccm_analog_sscg_pll_config_t *config, clock_pll_ctrl_t type);
1493
1494 /*!
1495 * @brief Get the ANALOG SSCG PLL clock frequency.
1496 *
1497 * @param base CCM ANALOG base address.
1498 * @param type sscg pll type
1499 * @param refClkFreq reference clock frequency
1500 * @param pll1Bypass pll1 bypass flag
1501 *
1502 * @return Clock frequency
1503 */
1504 uint32_t CLOCK_GetSSCGPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass);
1505
1506 /*!
1507 * @brief Initializes the ANALOG Fractional PLL.
1508 *
1509 * @param base CCM ANALOG base address.
1510 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1511 * @param type fractional pll type.
1512 *
1513 */
1514 void CLOCK_InitFracPll(CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type);
1515
1516 /*!
1517 * @brief Gets the ANALOG Fractional PLL clock frequency.
1518 *
1519 * @param base CCM_ANALOG base pointer.
1520 * @param type fractional pll type.
1521 * @param refClkFreq reference clock frequency
1522 *
1523 * @return Clock frequency
1524 */
1525 uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq);
1526
1527 /*!
1528 * @brief Gets PLL clock frequency.
1529 *
1530 * @param pll fractional pll type.
1531
1532 * @return Clock frequency
1533 */
1534 uint32_t CLOCK_GetPllFreq(clock_pll_ctrl_t pll);
1535
1536 /*!
1537 * @brief Gets PLL reference clock frequency.
1538 *
1539 * @param ctrl fractional pll type.
1540
1541 * @return Clock frequency
1542 */
1543 uint32_t CLOCK_GetPllRefClkFreq(clock_pll_ctrl_t ctrl);
1544
1545 /*!
1546 * @name CCM Get frequency
1547 * @{
1548 */
1549
1550 /*!
1551 * @brief Gets the clock frequency for a specific clock name.
1552 *
1553 * This function checks the current clock configurations and then calculates
1554 * the clock frequency for a specific clock name defined in clock_name_t.
1555 *
1556 * @param clockName Clock names defined in clock_name_t
1557 * @return Clock frequency value in hertz
1558 */
1559 uint32_t CLOCK_GetFreq(clock_name_t clockName);
1560
1561 /*!
1562 * @brief Gets the frequency of selected clock root.
1563 *
1564 * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
1565 * @return The frequency of selected clock root.
1566 */
1567 uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
1568
1569 /*!
1570 * @brief Get the CCM Cortex M4 core frequency.
1571 *
1572 * @return Clock frequency; If the clock is invalid, returns 0.
1573 */
1574 uint32_t CLOCK_GetCoreM4Freq(void);
1575
1576 /*!
1577 * @brief Get the CCM Axi bus frequency.
1578 *
1579 * @return Clock frequency; If the clock is invalid, returns 0.
1580 */
1581 uint32_t CLOCK_GetAxiFreq(void);
1582
1583 /*!
1584 * @brief Get the CCM Ahb bus frequency.
1585 *
1586 * @return Clock frequency; If the clock is invalid, returns 0.
1587 */
1588 uint32_t CLOCK_GetAhbFreq(void);
1589
1590 /* @} */
1591
1592 #if defined(__cplusplus)
1593 }
1594 #endif
1595 /* @} */
1596 #endif
1597
