1 /*
2 * Copyright 2018-2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_device_registers.h"
12 #include "fsl_common.h"
13 #include <stdint.h>
14 #include <stdbool.h>
15 #include <stddef.h>
16 #include <assert.h>
17
18 /*!
19 * @addtogroup clock
20 * @{
21 */
22
23 /*******************************************************************************
24 * Definitions
25 ******************************************************************************/
26
27 /*! @name Driver version */
28 /*@{*/
29 /*! @brief CLOCK driver version 2.4.0. */
30 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
31 /*@}*/
32
33 /* Definition for delay API in clock driver, users can redefine it to the real application. */
34 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
35 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
36 #endif
37
38 /*!
39 * @brief XTAL 24M clock frequency.
40 */
41 #define OSC24M_CLK_FREQ 24000000U
42 /*!
43 * @brief pad clock frequency.
44 */
45 #define CLKPAD_FREQ 0U
46
47 /*! @brief Clock ip name array for ECSPI. */
48 #define ECSPI_CLOCKS \
49 { \
50 kCLOCK_IpInvalid, kCLOCK_Ecspi1, kCLOCK_Ecspi2, kCLOCK_Ecspi3, \
51 }
52
53 /*! @brief Clock ip name array for ENET. */
54 #define ENET_CLOCKS \
55 { \
56 kCLOCK_Enet1, \
57 }
58
59 /*! @brief Clock ip name array for GPIO. */
60 #define GPIO_CLOCKS \
61 { \
62 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5, \
63 }
64
65 /*! @brief Clock ip name array for GPT. */
66 #define GPT_CLOCKS \
67 { \
68 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6, \
69 }
70
71 /*! @brief Clock ip name array for I2C. */
72 #define I2C_CLOCKS \
73 { \
74 kCLOCK_IpInvalid, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, \
75 }
76
77 /*! @brief Clock ip name array for IOMUX. */
78 #define IOMUX_CLOCKS \
79 { \
80 kCLOCK_Iomux, \
81 }
82
83 /*! @brief Clock ip name array for IPMUX. */
84 #define IPMUX_CLOCKS \
85 { \
86 kCLOCK_Ipmux1, kCLOCK_Ipmux2, kCLOCK_Ipmux3, kCLOCK_Ipmux4, \
87 }
88
89 /*! @brief Clock ip name array for PWM. */
90 #define PWM_CLOCKS \
91 { \
92 kCLOCK_IpInvalid, kCLOCK_Pwm1, kCLOCK_Pwm2, kCLOCK_Pwm3, kCLOCK_Pwm4, \
93 }
94
95 /*! @brief Clock ip name array for RDC. */
96 #define RDC_CLOCKS \
97 { \
98 kCLOCK_Rdc, \
99 }
100
101 /*! @brief Clock ip name array for SAI. */
102 #define SAI_CLOCKS \
103 { \
104 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_IpInvalid, kCLOCK_Sai5, kCLOCK_Sai6, \
105 kCLOCK_Sai7 \
106 }
107
108 /*! @brief Clock ip name array for RDC SEMA42. */
109 #define RDC_SEMA42_CLOCKS \
110 { \
111 kCLOCK_IpInvalid, kCLOCK_Sema42_1, kCLOCK_Sema42_2 \
112 }
113
114 /*! @brief Clock ip name array for UART. */
115 #define UART_CLOCKS \
116 { \
117 kCLOCK_IpInvalid, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, \
118 }
119
120 /*! @brief Clock ip name array for USDHC. */
121 #define USDHC_CLOCKS \
122 { \
123 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2, kCLOCK_Usdhc3 \
124 }
125
126 /*! @brief Clock ip name array for WDOG. */
127 #define WDOG_CLOCKS \
128 { \
129 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3 \
130 }
131
132 /*! @brief Clock ip name array for TEMPSENSOR. */
133 #define TMU_CLOCKS \
134 { \
135 kCLOCK_TempSensor, \
136 }
137
138 /*! @brief Clock ip name array for SDMA. */
139 #define SDMA_CLOCKS \
140 { \
141 kCLOCK_Sdma1, kCLOCK_Sdma2, kCLOCK_Sdma3 \
142 }
143
144 /*! @brief Clock ip name array for MU. */
145 #define MU_CLOCKS \
146 { \
147 kCLOCK_Mu \
148 }
149
150 /*! @brief Clock ip name array for QSPI. */
151 #define QSPI_CLOCKS \
152 { \
153 kCLOCK_Qspi \
154 }
155
156 /*! @brief Clock ip name array for PDM. */
157 #define PDM_CLOCKS \
158 { \
159 kCLOCK_Pdm \
160 }
161
162 /*! @brief Clock ip name array for ASRC. */
163 #define ASRC_CLOCKS \
164 { \
165 kCLOCK_Asrc \
166 }
167
168 /*!
169 * @brief CCM reg macros to extract corresponding registers bit field.
170 */
171 #define CCM_BIT_FIELD_EXTRACTION(val, mask, shift) (((val) & (mask)) >> (shift))
172
173 /*!
174 * @brief CCM reg macros to map corresponding registers.
175 */
176 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off))))
177 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
178 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
179 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
180
181 /*!
182 * @brief CCM Analog registers offset.
183 */
184 #define AUDIO_PLL1_GEN_CTRL_OFFSET 0x00
185 #define AUDIO_PLL2_GEN_CTRL_OFFSET 0x14
186 #define VIDEO_PLL1_GEN_CTRL_OFFSET 0x28
187 #define GPU_PLL_GEN_CTRL_OFFSET 0x64
188 #define VPU_PLL_GEN_CTRL_OFFSET 0x74
189 #define ARM_PLL_GEN_CTRL_OFFSET 0x84
190 #define SYS_PLL1_GEN_CTRL_OFFSET 0x94
191 #define SYS_PLL2_GEN_CTRL_OFFSET 0x104
192 #define SYS_PLL3_GEN_CTRL_OFFSET 0x114
193 #define DRAM_PLL_GEN_CTRL_OFFSET 0x50
194
195 /*!
196 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
197 */
198 #define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFFU) << 16U) | ((shift)))
199 #define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)(tuple)) & 0x1FU)
200 #define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
201 (*((volatile uint32_t *)((uintptr_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFFU) + (off))))
202 #define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
203
204 /*!
205 * @brief CCM CCGR and root tuple
206 */
207 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root))
208 #define CCM_TUPLE_CCGR(tuple) ((uintptr_t)(&(CCM)->CCGR[(uint32_t)(tuple) >> 16U].CCGR))
209 #define CCM_TUPLE_ROOT(tuple) ((uintptr_t)(&(CCM)->ROOT[(uint32_t)(tuple)&0xFFFFU].TARGET_ROOT))
210
211 /*!
212 * @brief clock root source
213 */
214 #define CLOCK_ROOT_SOURCE \
215 { \
216 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll2Div4Clk, kCLOCK_SysPll1Div3Clk, kCLOCK_SysPll1Clk, \
217 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll3Clk}, /* Cortex-M7 Clock Root. */ \
218 { \
219 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div3Clk, kCLOCK_SysPll1Clk, \
220 kCLOCK_SysPll2Div4Clk, kCLOCK_SysPll2Clk, kCLOCK_AudioPll1Clk, \
221 kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div8Clk}, /* AXI Clock Root. */ \
222 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, kCLOCK_SysPll2Clk, kCLOCK_SysPll2Div2Clk, \
223 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, kCLOCK_AudioPll2Clk}, /* NOC Clock Root. */ \
224 { \
225 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div6Clk, kCLOCK_SysPll1Clk, \
226 kCLOCK_SysPll1Div2Clk, kCLOCK_SysPll2Div8Clk, kCLOCK_SysPll3Clk, \
227 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk}, /* AHB Clock Root. */ \
228 { \
229 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div6Clk, kCLOCK_SysPll1Clk, \
230 kCLOCK_SysPll1Div2Clk, kCLOCK_SysPll2Div8Clk, kCLOCK_SysPll3Clk, \
231 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk}, /* IPG Clock Root. */ \
232 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div2Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll2Clk, kCLOCK_SysPll2Div6Clk, \
233 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk}, /* Audio AHB Clock Root. */ \
234 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div2Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll2Clk, kCLOCK_SysPll2Div6Clk, \
235 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk}, /* Audio IPG Clock Root. */ \
236 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Clk, kCLOCK_SysPll1Div8Clk, kCLOCK_SysPll2Div2Clk, kCLOCK_SysPll2Clk, \
237 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_SysPll1Div3Clk}, /* DRAM ALT Clock Root */ \
238 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
239 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk2, kCLOCK_ExtClk3}, /* SAI2 Clock Root */ \
240 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
241 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk3, kCLOCK_ExtClk4}, /* SAI3 Clock Root */ \
242 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
243 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk2, kCLOCK_ExtClk3}, /* SAI5 Clock Root */ \
244 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
245 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk3, kCLOCK_ExtClk4}, /* SAI6 Clock Root. */ \
246 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
247 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk3, kCLOCK_ExtClk4}, /* SAI7 Clock Root */ \
248 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Div2Clk, kCLOCK_SysPll2Div3Clk, \
249 kCLOCK_SysPll2Div2Clk, kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div3Clk, \
250 kCLOCK_SysPll3Clk, kCLOCK_SysPll1Div8Clk}, /* QSPI Clock Root */ \
251 { \
252 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
253 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
254 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C1 Clock Root */ \
255 { \
256 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
257 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
258 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C2 Clock Root */ \
259 { \
260 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
261 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
262 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C3 Clock Root */ \
263 { \
264 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
265 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
266 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C4 Clock Root */ \
267 { \
268 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
269 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
270 kCLOCK_ExtClk4, kCLOCK_AudioPll2Clk}, /* UART1 Clock Root */ \
271 { \
272 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
273 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
274 kCLOCK_ExtClk3, kCLOCK_AudioPll2Clk}, /* UART2 Clock Root */ \
275 { \
276 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
277 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
278 kCLOCK_ExtClk4, kCLOCK_AudioPll2Clk}, /* UART3 Clock Root */ \
279 { \
280 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
281 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
282 kCLOCK_ExtClk3, kCLOCK_AudioPll2Clk}, /* UART4 Clock Root */ \
283 { \
284 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div20Clk, \
285 kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, \
286 kCLOCK_SysPll2Div4Clk, kCLOCK_AudioPll2Clk}, /* ECSPI1 Clock ROOT */ \
287 { \
288 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div20Clk, \
289 kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, \
290 kCLOCK_SysPll2Div4Clk, kCLOCK_AudioPll2Clk}, /* ECSPI2 Clock ROOT */ \
291 { \
292 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div20Clk, \
293 kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, \
294 kCLOCK_SysPll2Div4Clk, kCLOCK_AudioPll2Clk}, /* ECSPI3 Clock ROOT */ \
295 { \
296 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
297 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk1, \
298 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM1 Clock ROOT */ \
299 { \
300 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
301 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk1, \
302 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM2 Clock ROOT */ \
303 { \
304 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
305 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
306 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM3 Clock ROOT */ \
307 { \
308 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
309 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
310 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM4 Clock ROOT */ \
311 { \
312 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
313 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
314 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk1}, /* GPT1 Clock ROOT */ \
315 { \
316 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
317 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
318 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk2}, /* GPT2 Clock ROOT */ \
319 { \
320 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
321 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
322 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk3}, /* GPT3 Clock ROOT */ \
323 { \
324 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
325 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
326 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk1}, /* GPT4 Clock ROOT */ \
327 { \
328 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
329 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
330 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk2}, /* GPT5 Clock ROOT */ \
331 { \
332 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
333 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
334 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk3}, /* GPT6 Clock ROOT */ \
335 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Div6Clk, kCLOCK_SysPll1Div5Clk, kCLOCK_NoneName, kCLOCK_SysPll2Div8Clk, \
336 kCLOCK_SysPll3Clk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div6Clk}, /* WDOG Clock ROOT */ \
337 { \
338 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_AudioPll1Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll2Clk, \
339 kCLOCK_SysPll3Clk, kCLOCK_ExtClk3, kCLOCK_AudioPll2Clk}, /* PDM Clock ROOT */ \
340 }
341
342 #define CLOCK_ROOT_CONTROL_TUPLE \
343 { \
344 kCLOCK_RootM7, kCLOCK_RootAxi, kCLOCK_RootNoc, kCLOCK_RootAhb, kCLOCK_RootAhb, kCLOCK_RootAudioAhb, \
345 kCLOCK_RootAudioAhb, kCLOCK_RootDramAlt, kCLOCK_RootSai2, kCLOCK_RootSai3, kCLOCK_RootSai5, \
346 kCLOCK_RootSai6, kCLOCK_RootSai7, kCLOCK_RootQspi, kCLOCK_RootI2c1, kCLOCK_RootI2c2, kCLOCK_RootI2c3, \
347 kCLOCK_RootI2c4, kCLOCK_RootUart1, kCLOCK_RootUart2, kCLOCK_RootUart3, kCLOCK_RootUart4, \
348 kCLOCK_RootEcspi1, kCLOCK_RootEcspi2, kCLOCK_RootEcspi3, kCLOCK_RootPwm1, kCLOCK_RootPwm2, \
349 kCLOCK_RootPwm3, kCLOCK_RootPwm4, kCLOCK_RootGpt1, kCLOCK_RootGpt2, kCLOCK_RootGpt3, kCLOCK_RootGpt4, \
350 kCLOCK_RootGpt5, kCLOCK_RootGpt6, kCLOCK_RootWdog, kCLOCK_RootPdm, \
351 }
352
353 /*! @brief Clock name used to get clock frequency. */
354 typedef enum _clock_name
355 {
356 kCLOCK_CoreM7Clk, /*!< ARM M7 Core clock */
357
358 kCLOCK_AxiClk, /*!< Main AXI bus clock. */
359 kCLOCK_AhbClk, /*!< AHB bus clock. */
360 kCLOCK_IpgClk, /*!< IPG bus clock. */
361 kCLOCK_PerClk, /*!< Peripheral Clock. */
362 kCLOCK_EnetIpgClk, /*!< ENET IPG Clock. */
363 kCLOCK_Osc24MClk, /*!< OSC 24M clock. */
364 kCLOCK_ArmPllClk, /*!< Arm PLL clock. */
365 kCLOCK_DramPllClk, /*!< Dram PLL clock. */
366 kCLOCK_SysPll1Clk, /*!< Sys PLL1 clock. */
367 kCLOCK_SysPll1Div2Clk, /*!< Sys PLL1 clock divided by 2. */
368 kCLOCK_SysPll1Div3Clk, /*!< Sys PLL1 clock divided by 3. */
369 kCLOCK_SysPll1Div4Clk, /*!< Sys PLL1 clock divided by 4. */
370 kCLOCK_SysPll1Div5Clk, /*!< Sys PLL1 clock divided by 5. */
371 kCLOCK_SysPll1Div6Clk, /*!< Sys PLL1 clock divided by 6. */
372 kCLOCK_SysPll1Div8Clk, /*!< Sys PLL1 clock divided by 8. */
373 kCLOCK_SysPll1Div10Clk, /*!< Sys PLL1 clock divided by 10. */
374 kCLOCK_SysPll1Div20Clk, /*!< Sys PLL1 clock divided by 20. */
375 kCLOCK_SysPll2Clk, /*!< Sys PLL2 clock. */
376 kCLOCK_SysPll2Div2Clk, /*!< Sys PLL2 clock divided by 2. */
377 kCLOCK_SysPll2Div3Clk, /*!< Sys PLL2 clock divided by 3. */
378 kCLOCK_SysPll2Div4Clk, /*!< Sys PLL2 clock divided by 4. */
379 kCLOCK_SysPll2Div5Clk, /*!< Sys PLL2 clock divided by 5. */
380 kCLOCK_SysPll2Div6Clk, /*!< Sys PLL2 clock divided by 6. */
381 kCLOCK_SysPll2Div8Clk, /*!< Sys PLL2 clock divided by 8. */
382 kCLOCK_SysPll2Div10Clk, /*!< Sys PLL2 clock divided by 10. */
383 kCLOCK_SysPll2Div20Clk, /*!< Sys PLL2 clock divided by 20. */
384 kCLOCK_SysPll3Clk, /*!< Sys PLL3 clock. */
385 kCLOCK_AudioPll1Clk, /*!< Audio PLL1 clock. */
386 kCLOCK_AudioPll2Clk, /*!< Audio PLL2 clock. */
387 kCLOCK_VideoPll1Clk, /*!< Video PLL1 clock. */
388 kCLOCK_ExtClk1, /*!< External clock1. */
389 kCLOCK_ExtClk2, /*!< External clock2. */
390 kCLOCK_ExtClk3, /*!< External clock3. */
391 kCLOCK_ExtClk4, /*!< External clock4. */
392 kCLOCK_NoneName, /*!< None Clock Name. */
393 /* -------------------------------- Other clock --------------------------*/
394 } clock_name_t;
395
396 #define kCLOCK_CoreSysClk kCLOCK_CoreM7Clk /*!< For compatible with other platforms without CCM. */
397 #define CLOCK_GetCoreSysClkFreq CLOCK_GetCoreM7Freq /*!< For compatible with other platforms without CCM. */
398
399 /*! @brief CCM CCGR gate control. */
400 typedef enum _clock_ip_name
401 {
402 kCLOCK_IpInvalid = -1,
403
404 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
405
406 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
407
408 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
409 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
410 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
411
412 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
413
414 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
415 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
416 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
417 kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U), /*!< GPIO4 Clock Gate.*/
418 kCLOCK_Gpio5 = CCM_TUPLE(15U, 33U), /*!< GPIO5 Clock Gate.*/
419
420 kCLOCK_Gpt1 = CCM_TUPLE(16U, 107U), /*!< GPT1 Clock Gate.*/
421 kCLOCK_Gpt2 = CCM_TUPLE(17U, 108U), /*!< GPT2 Clock Gate.*/
422 kCLOCK_Gpt3 = CCM_TUPLE(18U, 109U), /*!< GPT3 Clock Gate.*/
423 kCLOCK_Gpt4 = CCM_TUPLE(19U, 110U), /*!< GPT4 Clock Gate.*/
424 kCLOCK_Gpt5 = CCM_TUPLE(20U, 111U), /*!< GPT5 Clock Gate.*/
425 kCLOCK_Gpt6 = CCM_TUPLE(21U, 112U), /*!< GPT6 Clock Gate.*/
426
427 kCLOCK_I2c1 = CCM_TUPLE(23U, 90U), /*!< I2C1 Clock Gate.*/
428 kCLOCK_I2c2 = CCM_TUPLE(24U, 91U), /*!< I2C2 Clock Gate.*/
429 kCLOCK_I2c3 = CCM_TUPLE(25U, 92U), /*!< I2C3 Clock Gate.*/
430 kCLOCK_I2c4 = CCM_TUPLE(26U, 93U), /*!< I2C4 Clock Gate.*/
431
432 kCLOCK_Iomux = CCM_TUPLE(27U, 33U), /*!< IOMUX Clock Gate.*/
433 kCLOCK_Ipmux1 = CCM_TUPLE(28U, 33U), /*!< IPMUX1 Clock Gate.*/
434 kCLOCK_Ipmux2 = CCM_TUPLE(29U, 33U), /*!< IPMUX2 Clock Gate.*/
435 kCLOCK_Ipmux3 = CCM_TUPLE(30U, 33U), /*!< IPMUX3 Clock Gate.*/
436 kCLOCK_Ipmux4 = CCM_TUPLE(31U, 33U), /*!< IPMUX4 Clock Gate.*/
437
438 kCLOCK_Mu = CCM_TUPLE(33U, 33U), /*!< MU Clock Gate.*/
439
440 kCLOCK_Ocram = CCM_TUPLE(35U, 16U), /*!< OCRAM Clock Gate.*/
441 kCLOCK_OcramS = CCM_TUPLE(36U, 32U), /*!< OCRAM S Clock Gate.*/
442
443 kCLOCK_Pwm1 = CCM_TUPLE(40U, 103U), /*!< PWM1 Clock Gate.*/
444 kCLOCK_Pwm2 = CCM_TUPLE(41U, 104U), /*!< PWM2 Clock Gate.*/
445 kCLOCK_Pwm3 = CCM_TUPLE(42U, 105U), /*!< PWM3 Clock Gate.*/
446 kCLOCK_Pwm4 = CCM_TUPLE(43U, 106U), /*!< PWM4 Clock Gate.*/
447
448 kCLOCK_Qspi = CCM_TUPLE(47U, 87U), /*!< QSPI Clock Gate.*/
449
450 kCLOCK_Rdc = CCM_TUPLE(49U, 33U), /*!< RDC Clock Gate.*/
451
452 kCLOCK_Sai2 = CCM_TUPLE(52U, 76U), /*!< SAI2 Clock Gate.*/
453 kCLOCK_Sai3 = CCM_TUPLE(53U, 77U), /*!< SAI3 Clock Gate.*/
454 kCLOCK_Sai5 = CCM_TUPLE(55U, 79U), /*!< SAI5 Clock Gate.*/
455 kCLOCK_Sai6 = CCM_TUPLE(56U, 80U), /*!< SAI6 Clock Gate.*/
456 kCLOCK_Sai7 = CCM_TUPLE(101U, 134U), /*!< SAI7 Clock Gate.*/
457
458 kCLOCK_Sdma1 = CCM_TUPLE(58U, 33U), /*!< SDMA1 Clock Gate.*/
459 kCLOCK_Sdma2 = CCM_TUPLE(59U, 35U), /*!< SDMA2 Clock Gate.*/
460
461 kCLOCK_Sec_Debug = CCM_TUPLE(60U, 33U), /*!< SEC_DEBUG Clock Gate.*/
462
463 kCLOCK_Sema42_1 = CCM_TUPLE(61U, 33U), /*!< RDC SEMA42 Clock Gate.*/
464 kCLOCK_Sema42_2 = CCM_TUPLE(62U, 33U), /*!< RDC SEMA42 Clock Gate.*/
465
466 kCLOCK_Sim_display = CCM_TUPLE(63U, 16U), /*!< SIM_Display Clock Gate.*/
467 kCLOCK_Sim_m = CCM_TUPLE(65U, 32U), /*!< SIM_M Clock Gate.*/
468 kCLOCK_Sim_main = CCM_TUPLE(66U, 16U), /*!< SIM_MAIN Clock Gate.*/
469 kCLOCK_Sim_s = CCM_TUPLE(67U, 32U), /*!< SIM_S Clock Gate.*/
470 kCLOCK_Sim_wakeup = CCM_TUPLE(68U, 32U), /*!< SIM_WAKEUP Clock Gate.*/
471
472 kCLOCK_Uart1 = CCM_TUPLE(73U, 94U), /*!< UART1 Clock Gate.*/
473 kCLOCK_Uart2 = CCM_TUPLE(74U, 95U), /*!< UART2 Clock Gate.*/
474 kCLOCK_Uart3 = CCM_TUPLE(75U, 96U), /*!< UART3 Clock Gate.*/
475 kCLOCK_Uart4 = CCM_TUPLE(76U, 97U), /*!< UART4 Clock Gate.*/
476
477 kCLOCK_Usdhc1 = CCM_TUPLE(81U, 88U), /*!< USDHC1 Clock Gate.*/
478 kCLOCK_Usdhc2 = CCM_TUPLE(82U, 89U), /*!< USDHC2 Clock Gate.*/
479 kCLOCK_Wdog1 = CCM_TUPLE(83U, 114U), /*!< WDOG1 Clock Gate.*/
480 kCLOCK_Wdog2 = CCM_TUPLE(84U, 114U), /*!< WDOG2 Clock Gate.*/
481 kCLOCK_Wdog3 = CCM_TUPLE(85U, 114U), /*!< WDOG3 Clock Gate.*/
482
483 kCLOCK_Asrc = CCM_TUPLE(88U, 33U), /*!< ASRC Clock Gate.*/
484 kCLOCK_Pdm = CCM_TUPLE(91U, 132U), /*!< PDM Clock Gate.*/
485 kCLOCK_Usdhc3 = CCM_TUPLE(94U, 121U), /*!< USDHC3 Clock Gate.*/
486 kCLOCK_Sdma3 = CCM_TUPLE(95U, 35U), /*!< SDMA3 Clock Gate.*/
487
488 kCLOCK_TempSensor = CCM_TUPLE(98U, 0xFFFF), /*!< TempSensor Clock Gate.*/
489
490 } clock_ip_name_t;
491
492 /*! @brief ccm root name used to get clock frequency. */
493 typedef enum _clock_root_control
494 {
495 kCLOCK_RootM7 =
496 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[1].TARGET_ROOT), /*!< ARM Cortex-M7 Clock control name.*/
497 kCLOCK_RootAxi = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[16].TARGET_ROOT), /*!< AXI Clock control name.*/
498 kCLOCK_RootEnetAxi = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[17].TARGET_ROOT), /*!< ENET AXI Clock control name.*/
499 kCLOCK_RootNoc = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[26].TARGET_ROOT), /*!< NOC Clock control name.*/
500 kCLOCK_RootAhb = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[32].TARGET_ROOT), /*!< AHB Clock control name.*/
501 kCLOCK_RootIpg = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[33].TARGET_ROOT), /*!< IPG Clock control name.*/
502 kCLOCK_RootAudioAhb =
503 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[34].TARGET_ROOT), /*!< Audio AHB Clock control name.*/
504 kCLOCK_RootAudioIpg =
505 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[35].TARGET_ROOT), /*!< Audio IPG Clock control name.*/
506 kCLOCK_RootDramAlt =
507 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[64].TARGET_ROOT), /*!< DRAM ALT Clock control name.*/
508
509 kCLOCK_RootSai2 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[76].TARGET_ROOT), /*!< SAI2 Clock control name.*/
510 kCLOCK_RootSai3 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[77].TARGET_ROOT), /*!< SAI3 Clock control name.*/
511 kCLOCK_RootSai5 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[79].TARGET_ROOT), /*!< SAI5 Clock control name.*/
512 kCLOCK_RootSai6 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[80].TARGET_ROOT), /*!< SAI6 Clock control name.*/
513 kCLOCK_RootSai7 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[134].TARGET_ROOT), /*!< SAI7 Clock control name.*/
514
515 kCLOCK_RootEnetRef = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[83].TARGET_ROOT), /*!< ENET Clock control name.*/
516 kCLOCK_RootEnetTimer = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[84].TARGET_ROOT), /*!< ENET TIMER Clock control name.*/
517 kCLOCK_RootEnetPhy = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[85].TARGET_ROOT), /*!< ENET PHY Clock control name.*/
518
519 kCLOCK_RootQspi = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[87].TARGET_ROOT), /*!< QSPI Clock control name.*/
520
521 kCLOCK_RootI2c1 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[90].TARGET_ROOT), /*!< I2C1 Clock control name.*/
522 kCLOCK_RootI2c2 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[91].TARGET_ROOT), /*!< I2C2 Clock control name.*/
523 kCLOCK_RootI2c3 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[92].TARGET_ROOT), /*!< I2C3 Clock control name.*/
524 kCLOCK_RootI2c4 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[93].TARGET_ROOT), /*!< I2C4 Clock control name.*/
525
526 kCLOCK_RootUart1 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[94].TARGET_ROOT), /*!< UART1 Clock control name.*/
527 kCLOCK_RootUart2 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[95].TARGET_ROOT), /*!< UART2 Clock control name.*/
528 kCLOCK_RootUart3 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[96].TARGET_ROOT), /*!< UART3 Clock control name.*/
529 kCLOCK_RootUart4 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[97].TARGET_ROOT), /*!< UART4 Clock control name.*/
530
531 kCLOCK_RootEcspi1 =
532 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[101].TARGET_ROOT), /*!< ECSPI1 Clock control name.*/
533 kCLOCK_RootEcspi2 =
534 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[102].TARGET_ROOT), /*!< ECSPI2 Clock control name.*/
535 kCLOCK_RootEcspi3 =
536 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[131].TARGET_ROOT), /*!< ECSPI3 Clock control name.*/
537
538 kCLOCK_RootPwm1 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[103].TARGET_ROOT), /*!< PWM1 Clock control name.*/
539 kCLOCK_RootPwm2 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[104].TARGET_ROOT), /*!< PWM2 Clock control name.*/
540 kCLOCK_RootPwm3 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[105].TARGET_ROOT), /*!< PWM3 Clock control name.*/
541 kCLOCK_RootPwm4 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[106].TARGET_ROOT), /*!< PWM4 Clock control name.*/
542
543 kCLOCK_RootGpt1 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[107].TARGET_ROOT), /*!< GPT1 Clock control name.*/
544 kCLOCK_RootGpt2 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[108].TARGET_ROOT), /*!< GPT2 Clock control name.*/
545 kCLOCK_RootGpt3 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[109].TARGET_ROOT), /*!< GPT3 Clock control name.*/
546 kCLOCK_RootGpt4 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[110].TARGET_ROOT), /*!< GPT4 Clock control name.*/
547 kCLOCK_RootGpt5 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[111].TARGET_ROOT), /*!< GPT5 Clock control name.*/
548 kCLOCK_RootGpt6 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[112].TARGET_ROOT), /*!< GPT6 Clock control name.*/
549
550 kCLOCK_RootWdog = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[114].TARGET_ROOT), /*!< WDOG Clock control name.*/
551
552 kCLOCK_RootPdm = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[132].TARGET_ROOT), /*!< PDM Clock control name.*/
553
554 } clock_root_control_t;
555
556 /*! @brief ccm clock root index used to get clock frequency. */
557 typedef enum _clock_root
558 {
559 kCLOCK_M7ClkRoot = 0, /*!< ARM Cortex-M7 Clock control name.*/
560 kCLOCK_AxiClkRoot, /*!< AXI Clock control name.*/
561 kCLOCK_NocClkRoot, /*!< NOC Clock control name.*/
562 kCLOCK_AhbClkRoot, /*!< AHB Clock control name.*/
563 kCLOCK_IpgClkRoot, /*!< IPG Clock control name.*/
564 kCLOCK_AudioAhbClkRoot, /*!< Audio AHB Clock control name.*/
565 kCLOCK_AudioIpgClkRoot, /*!< Audio IPG Clock control name.*/
566 kCLOCK_DramAltClkRoot, /*!< DRAM ALT Clock control name.*/
567
568 kCLOCK_Sai2ClkRoot, /*!< SAI2 Clock control name.*/
569 kCLOCK_Sai3ClkRoot, /*!< SAI3 Clock control name.*/
570 kCLOCK_Sai5ClkRoot, /*!< SAI5 Clock control name.*/
571 kCLOCK_Sai6ClkRoot, /*!< SAI6 Clock control name.*/
572 kCLOCK_Sai7ClkRoot, /*!< SAI7 Clock control name.*/
573
574 kCLOCK_QspiClkRoot, /*!< QSPI Clock control name.*/
575
576 kCLOCK_I2c1ClkRoot, /*!< I2C1 Clock control name.*/
577 kCLOCK_I2c2ClkRoot, /*!< I2C2 Clock control name.*/
578 kCLOCK_I2c3ClkRoot, /*!< I2C3 Clock control name.*/
579 kCLOCK_I2c4ClkRoot, /*!< I2C4 Clock control name.*/
580
581 kCLOCK_Uart1ClkRoot, /*!< UART1 Clock control name.*/
582 kCLOCK_Uart2ClkRoot, /*!< UART2 Clock control name.*/
583 kCLOCK_Uart3ClkRoot, /*!< UART3 Clock control name.*/
584 kCLOCK_Uart4ClkRoot, /*!< UART4 Clock control name.*/
585
586 kCLOCK_Ecspi1ClkRoot, /*!< ECSPI1 Clock control name.*/
587 kCLOCK_Ecspi2ClkRoot, /*!< ECSPI2 Clock control name.*/
588 kCLOCK_Ecspi3ClkRoot, /*!< ECSPI3 Clock control name.*/
589
590 kCLOCK_Pwm1ClkRoot, /*!< PWM1 Clock control name.*/
591 kCLOCK_Pwm2ClkRoot, /*!< PWM2 Clock control name.*/
592 kCLOCK_Pwm3ClkRoot, /*!< PWM3 Clock control name.*/
593 kCLOCK_Pwm4ClkRoot, /*!< PWM4 Clock control name.*/
594
595 kCLOCK_Gpt1ClkRoot, /*!< GPT1 Clock control name.*/
596 kCLOCK_Gpt2ClkRoot, /*!< GPT2 Clock control name.*/
597 kCLOCK_Gpt3ClkRoot, /*!< GPT3 Clock control name.*/
598 kCLOCK_Gpt4ClkRoot, /*!< GPT4 Clock control name.*/
599 kCLOCK_Gpt5ClkRoot, /*!< GPT5 Clock control name.*/
600 kCLOCK_Gpt6ClkRoot, /*!< GPT6 Clock control name.*/
601
602 kCLOCK_WdogClkRoot, /*!< WDOG Clock control name.*/
603
604 kCLOCK_PdmClkRoot, /*!< PDM Clock control name.*/
605
606 } clock_root_t;
607
608 /*! @brief Root clock select enumeration for ARM Cortex-M7 core. */
609 typedef enum _clock_rootmux_m7_clk_sel
610 {
611 kCLOCK_M7RootmuxOsc24M = 0U, /*!< ARM Cortex-M7 Clock from OSC 24M.*/
612 kCLOCK_M7RootmuxSysPll2Div5 = 1U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL2 divided by 5.*/
613 kCLOCK_M7RootmuxSysPll2Div4 = 2U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL2 divided by 4.*/
614 kCLOCK_M7RootmuxSysPll1Div3 = 3U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL1 divided by 3.*/
615 kCLOCK_M7RootmuxSysPll1 = 4U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL1.*/
616 kCLOCK_M7RootmuxAudioPll1 = 5U, /*!< ARM Cortex-M7 Clock from AUDIO PLL1.*/
617 kCLOCK_M7RootmuxVideoPll1 = 6U, /*!< ARM Cortex-M7 Clock from VIDEO PLL1.*/
618 kCLOCK_M7RootmuxSysPll3 = 7U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL3.*/
619 } clock_rootmux_m7_clk_sel_t;
620
621 /*! @brief Root clock select enumeration for AXI bus. */
622 typedef enum _clock_rootmux_axi_clk_sel
623 {
624 kCLOCK_AxiRootmuxOsc24M = 0U, /*!< ARM AXI Clock from OSC 24M.*/
625 kCLOCK_AxiRootmuxSysPll2Div3 = 1U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 3.*/
626 kCLOCK_AxiRootmuxSysPll1 = 2U, /*!< ARM AXI Clock from SYSTEM PLL1.*/
627 kCLOCK_AxiRootmuxSysPll2Div4 = 3U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 4.*/
628 kCLOCK_AxiRootmuxSysPll2 = 4U, /*!< ARM AXI Clock from SYSTEM PLL2.*/
629 kCLOCK_AxiRootmuxAudioPll1 = 5U, /*!< ARM AXI Clock from AUDIO PLL1.*/
630 kCLOCK_AxiRootmuxVideoPll1 = 6U, /*!< ARM AXI Clock from VIDEO PLL1.*/
631 kCLOCK_AxiRootmuxSysPll1Div8 = 7U, /*!< ARM AXI Clock from SYSTEM PLL1 divided by 8.*/
632 } clock_rootmux_axi_clk_sel_t;
633
634 /*! @brief Root clock select enumeration for AHB bus. */
635 typedef enum _clock_rootmux_ahb_clk_sel
636 {
637 kCLOCK_AhbRootmuxOsc24M = 0U, /*!< ARM AHB Clock from OSC 24M.*/
638 kCLOCK_AhbRootmuxSysPll1Div6 = 1U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 6.*/
639 kCLOCK_AhbRootmuxSysPll1 = 2U, /*!< ARM AHB Clock from SYSTEM PLL1.*/
640 kCLOCK_AhbRootmuxSysPll1Div2 = 3U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 2.*/
641 kCLOCK_AhbRootmuxSysPll2Div8 = 4U, /*!< ARM AHB Clock from SYSTEM PLL2 divided by 8.*/
642 kCLOCK_AhbRootmuxSysPll3 = 5U, /*!< ARM AHB Clock from SYSTEM PLL3.*/
643 kCLOCK_AhbRootmuxAudioPll1 = 6U, /*!< ARM AHB Clock from AUDIO PLL1.*/
644 kCLOCK_AhbRootmuxVideoPll1 = 7U, /*!< ARM AHB Clock from VIDEO PLL1.*/
645 } clock_rootmux_ahb_clk_sel_t;
646
647 /*! @brief Root clock select enumeration for Audio AHB bus. */
648 typedef enum _clock_rootmux_audio_ahb_clk_sel
649 {
650 kCLOCK_AudioAhbRootmuxOsc24M = 0U, /*!< ARM Audio AHB Clock from OSC 24M.*/
651 kCLOCK_AudioAhbRootmuxSysPll2Div2 = 1U, /*!< ARM Audio AHB Clock from SYSTEM PLL2 divided by 2.*/
652 kCLOCK_AudioAhbRootmuxSysPll1 = 2U, /*!< ARM Audio AHB Clock from SYSTEM PLL1.*/
653 kCLOCK_AudioAhbRootmuxSysPll2 = 3U, /*!< ARM Audio AHB Clock from SYSTEM PLL2.*/
654 kCLOCK_AudioAhbRootmuxSysPll2Div6 = 4U, /*!< ARM Audio AHB Clock from SYSTEM PLL2 divided by 6.*/
655 kCLOCK_AudioAhbRootmuxSysPll3 = 5U, /*!< ARM Audio AHB Clock from SYSTEM PLL3.*/
656 kCLOCK_AudioAhbRootmuxAudioPll1 = 6U, /*!< ARM Audio AHB Clock from AUDIO PLL1.*/
657 kCLOCK_AudioAhbRootmuxVideoPll1 = 7U, /*!< ARM Audio AHB Clock from VIDEO PLL1.*/
658 } clock_rootmux_audio_ahb_clk_sel_t;
659 /*! @brief Root clock select enumeration for QSPI peripheral. */
660 typedef enum _clock_rootmux_qspi_clk_sel
661 {
662 kCLOCK_QspiRootmuxOsc24M = 0U, /*!< ARM QSPI Clock from OSC 24M.*/
663 kCLOCK_QspiRootmuxSysPll1Div2 = 1U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 2.*/
664 kCLOCK_QspiRootmuxSysPll2Div3 = 2U, /*!< ARM QSPI Clock from SYSTEM PLL2 divided by 3.*/
665 kCLOCK_QspiRootmuxSysPll2Div2 = 3U, /*!< ARM QSPI Clock from SYSTEM PLL2 divided by 2.*/
666 kCLOCK_QspiRootmuxAudioPll2 = 4U, /*!< ARM QSPI Clock from AUDIO PLL2.*/
667 kCLOCK_QspiRootmuxSysPll1Div3 = 5U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 3 */
668 kCLOCK_QspiRootmuxSysPll3 = 6, /*!< ARM QSPI Clock from SYSTEM PLL3.*/
669 kCLOCK_QspiRootmuxSysPll1Div8 = 7U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 8.*/
670 } clock_rootmux_qspi_clk_sel_t;
671
672 /*! @brief Root clock select enumeration for ECSPI peripheral. */
673 typedef enum _clock_rootmux_ecspi_clk_sel
674 {
675 kCLOCK_EcspiRootmuxOsc24M = 0U, /*!< ECSPI Clock from OSC 24M.*/
676 kCLOCK_EcspiRootmuxSysPll2Div5 = 1U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 5.*/
677 kCLOCK_EcspiRootmuxSysPll1Div20 = 2U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 20.*/
678 kCLOCK_EcspiRootmuxSysPll1Div5 = 3U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 5.*/
679 kCLOCK_EcspiRootmuxSysPll1 = 4U, /*!< ECSPI Clock from SYSTEM PLL1.*/
680 kCLOCK_EcspiRootmuxSysPll3 = 5U, /*!< ECSPI Clock from SYSTEM PLL3.*/
681 kCLOCK_EcspiRootmuxSysPll2Div4 = 6U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 4.*/
682 kCLOCK_EcspiRootmuxAudioPll2 = 7U, /*!< ECSPI Clock from AUDIO PLL2.*/
683 } clock_rootmux_ecspi_clk_sel_t;
684
685 /*! @brief Root clock select enumeration for ENET AXI bus. */
686 typedef enum _clock_rootmux_enet_axi_clk_sel
687 {
688 kCLOCK_EnetAxiRootmuxOsc24M = 0U, /*!< ENET AXI Clock from OSC 24M.*/
689 kCLOCK_EnetAxiRootmuxSysPll1Div3 = 1U, /*!< ENET AXI Clock from SYSTEM PLL1 divided by 3.*/
690 kCLOCK_EnetAxiRootmuxSysPll1 = 2U, /*!< ENET AXI Clock from SYSTEM PLL1.*/
691 kCLOCK_EnetAxiRootmuxSysPll2Div4 = 3U, /*!< ENET AXI Clock from SYSTEM PLL2 divided by 4.*/
692 kCLOCK_EnetAxiRootmuxSysPll2Div5 = 4U, /*!< ENET AXI Clock from SYSTEM PLL2 divided by 5.*/
693 kCLOCK_EnetAxiRootmuxAudioPll1 = 5U, /*!< ENET AXI Clock from AUDIO PLL1.*/
694 kCLOCK_EnetAxiRootmuxVideoPll1 = 6U, /*!< ENET AXI Clock from VIDEO PLL1.*/
695 kCLOCK_EnetAxiRootmuxSysPll3 = 7U, /*!< ENET AXI Clock from SYSTEM PLL3.*/
696 } clock_rootmux_enet_axi_clk_sel_t;
697
698 /*! @brief Root clock select enumeration for ENET REF Clcok. */
699 typedef enum _clock_rootmux_enet_ref_clk_sel
700 {
701 kCLOCK_EnetRefRootmuxOsc24M = 0U, /*!< ENET REF Clock from OSC 24M.*/
702 kCLOCK_EnetRefRootmuxSysPll2Div8 = 1U, /*!< ENET REF Clock from SYSTEM PLL2 divided by 8.*/
703 kCLOCK_EnetRefRootmuxSysPll2Div20 = 2U, /*!< ENET REF Clock from SYSTEM PLL2 divided by 20.*/
704 kCLOCK_EnetRefRootmuxSysPll2Div10 = 3U, /*!< ENET REF Clock from SYSTEM PLL2 divided by 10.*/
705 kCLOCK_EnetRefRootmuxSysPll1Div5 = 4U, /*!< ENET REF Clock from SYSTEM PLL1 divided by 5.*/
706 kCLOCK_EnetRefRootmuxAudioPll1 = 5U, /*!< ENET REF Clock from AUDIO PLL1.*/
707 kCLOCK_EnetRefRootmuxVideoPll1 = 6U, /*!< ENET REF Clock from VIDEO PLL1.*/
708 kCLOCK_EnetRefRootmuxExtClk4 = 7U, /*!< ENET REF Clock from External Clock 4.*/
709 } clock_rootmux_enet_ref_clk_sel_t;
710
711 /*! @brief Root clock select enumeration for ENET TIMER Clcok. */
712 typedef enum _clock_rootmux_enet_timer_clk_sel
713 {
714 kCLOCK_EnetTimerRootmuxOsc24M = 0U, /*!< ENET TIMER Clock from OSC 24M.*/
715 kCLOCK_EnetTimerRootmuxSysPll2Div10 = 1U, /*!< ENET TIMER Clock from SYSTEM PLL2 divided by 10.*/
716 kCLOCK_EnetTimerRootmuxAudioPll1 = 2U, /*!< ENET TIMER Clock from AUDIO PLL1.*/
717 kCLOCK_EnetTimerRootmuxExtClk1 = 3U, /*!< ENET TIMER Clock from External Clock 1.*/
718 kCLOCK_EnetTimerRootmuxExtClk2 = 4U, /*!< ENET TIMER Clock External Clock 2.*/
719 kCLOCK_EnetTimerRootmuxExtClk3 = 5U, /*!< ENET TIMER Clock from External Clock 3.*/
720 kCLOCK_EnetTimerRootmuxExtClk4 = 6U, /*!< ENET TIMER Clock from External Clock 4.*/
721 kCLOCK_EnetTimerRootmuxVideoPll1 = 7U, /*!< ENET TIMER Clock from VIDEO PLL1.*/
722 } clock_rootmux_enet_timer_clk_sel_t;
723
724 /*! @brief Root clock select enumeration for ENET PHY Clcok. */
725 typedef enum _clock_rootmux_enet_phy_clk_sel
726 {
727 kCLOCK_EnetPhyRootmuxOsc24M = 0U, /*!< ENET PHY Clock from OSC 24M.*/
728 kCLOCK_EnetPhyRootmuxSysPll2Div20 = 1U, /*!< ENET PHY Clock from SYSTEM PLL2 divided by 20.*/
729 kCLOCK_EnetPhyRootmuxSysPll2Div8 = 2U, /*!< ENET PHY Clock from SYSTEM PLL2 divided by 8.*/
730 kCLOCK_EnetPhyRootmuxSysPll2Div5 = 3U, /*!< ENET PHY Clock from SYSTEM PLL2 divided by 5.*/
731 kCLOCK_EnetPhyRootmuxSysPll2Div2 = 4U, /*!< ENET PHY Clock from SYSTEM PLL2 divided by 2.*/
732 kCLOCK_EnetPhyRootmuxAudioPll1 = 5U, /*!< ENET PHY Clock from AUDIO PLL1.*/
733 kCLOCK_EnetPhyRootmuxVideoPll1 = 6U, /*!< ENET PHY Clock from VIDEO PLL1.*/
734 kCLOCK_EnetPhyRootmuxAudioPll2 = 7U, /*!< ENET PHY Clock from AUDIO PLL2.*/
735 } clock_rootmux_enet_phy_clk_sel_t;
736
737 /*! @brief Root clock select enumeration for I2C peripheral. */
738 typedef enum _clock_rootmux_i2c_clk_sel
739 {
740 kCLOCK_I2cRootmuxOsc24M = 0U, /*!< I2C Clock from OSC 24M.*/
741 kCLOCK_I2cRootmuxSysPll1Div5 = 1U, /*!< I2C Clock from SYSTEM PLL1 divided by 5.*/
742 kCLOCK_I2cRootmuxSysPll2Div20 = 2U, /*!< I2C Clock from SYSTEM PLL2 divided by 20.*/
743 kCLOCK_I2cRootmuxSysPll3 = 3U, /*!< I2C Clock from SYSTEM PLL3 .*/
744 kCLOCK_I2cRootmuxAudioPll1 = 4U, /*!< I2C Clock from AUDIO PLL1.*/
745 kCLOCK_I2cRootmuxVideoPll1 = 5U, /*!< I2C Clock from VIDEO PLL1.*/
746 kCLOCK_I2cRootmuxAudioPll2 = 6U, /*!< I2C Clock from AUDIO PLL2.*/
747 kCLOCK_I2cRootmuxSysPll1Div6 = 7U, /*!< I2C Clock from SYSTEM PLL1 divided by 6.*/
748 } clock_rootmux_i2c_clk_sel_t;
749
750 /*! @brief Root clock select enumeration for UART peripheral. */
751 typedef enum _clock_rootmux_uart_clk_sel
752 {
753 kCLOCK_UartRootmuxOsc24M = 0U, /*!< UART Clock from OSC 24M.*/
754 kCLOCK_UartRootmuxSysPll1Div10 = 1U, /*!< UART Clock from SYSTEM PLL1 divided by 10.*/
755 kCLOCK_UartRootmuxSysPll2Div5 = 2U, /*!< UART Clock from SYSTEM PLL2 divided by 5.*/
756 kCLOCK_UartRootmuxSysPll2Div10 = 3U, /*!< UART Clock from SYSTEM PLL2 divided by 10.*/
757 kCLOCK_UartRootmuxSysPll3 = 4U, /*!< UART Clock from SYSTEM PLL3.*/
758 kCLOCK_UartRootmuxExtClk2 = 5U, /*!< UART Clock from External Clock 2.*/
759 kCLOCK_UartRootmuxExtClk34 = 6U, /*!< UART Clock from External Clock 3, External Clock 4.*/
760 kCLOCK_UartRootmuxAudioPll2 = 7U, /*!< UART Clock from Audio PLL2.*/
761 } clock_rootmux_uart_clk_sel_t;
762
763 /*! @brief Root clock select enumeration for GPT peripheral. */
764 typedef enum _clock_rootmux_gpt
765 {
766 kCLOCK_GptRootmuxOsc24M = 0U, /*!< GPT Clock from OSC 24M.*/
767 kCLOCK_GptRootmuxSystemPll2Div10 = 1U, /*!< GPT Clock from SYSTEM PLL2 divided by 10.*/
768 kCLOCK_GptRootmuxSysPll1Div2 = 2U, /*!< GPT Clock from SYSTEM PLL1 divided by 2.*/
769 kCLOCK_GptRootmuxSysPll1Div20 = 3U, /*!< GPT Clock from SYSTEM PLL1 divided by 20.*/
770 kCLOCK_GptRootmuxVideoPll1 = 4U, /*!< GPT Clock from VIDEO PLL1.*/
771 kCLOCK_GptRootmuxSystemPll1Div10 = 5U, /*!< GPT Clock from SYSTEM PLL1 divided by 10.*/
772 kCLOCK_GptRootmuxAudioPll1 = 6U, /*!< GPT Clock from AUDIO PLL1.*/
773 kCLOCK_GptRootmuxExtClk123 = 7U, /*!< GPT Clock from External Clock1, External Clock2, External Clock3.*/
774 } clock_rootmux_gpt_t;
775
776 /*! @brief Root clock select enumeration for WDOG peripheral. */
777 typedef enum _clock_rootmux_wdog_clk_sel
778 {
779 kCLOCK_WdogRootmuxOsc24M = 0U, /*!< WDOG Clock from OSC 24M.*/
780 kCLOCK_WdogRootmuxSysPll1Div6 = 1U, /*!< WDOG Clock from SYSTEM PLL1 divided by 6.*/
781 kCLOCK_WdogRootmuxSysPll1Div5 = 2U, /*!< WDOG Clock from SYSTEM PLL1 divided by 5.*/
782 kCLOCK_WdogRootmuxVpuPll = 3U, /*!< WDOG Clock from VPU DLL.*/
783 kCLOCK_WdogRootmuxSystemPll2Div8 = 4U, /*!< WDOG Clock from SYSTEM PLL2 divided by 8.*/
784 kCLOCK_WdogRootmuxSystemPll3 = 5U, /*!< WDOG Clock from SYSTEM PLL3.*/
785 kCLOCK_WdogRootmuxSystemPll1Div10 = 6U, /*!< WDOG Clock from SYSTEM PLL1 divided by 10.*/
786 kCLOCK_WdogRootmuxSystemPll2Div6 = 7U, /*!< WDOG Clock from SYSTEM PLL2 divided by 6.*/
787 } clock_rootmux_wdog_clk_sel_t;
788
789 /*! @brief Root clock select enumeration for PWM peripheral. */
790 typedef enum _clock_rootmux_pwm_clk_sel
791 {
792 kCLOCK_PwmRootmuxOsc24M = 0U, /*!< PWM Clock from OSC 24M.*/
793 kCLOCK_PwmRootmuxSysPll2Div10 = 1U, /*!< PWM Clock from SYSTEM PLL2 divided by 10.*/
794 kCLOCK_PwmRootmuxSysPll1Div5 = 2U, /*!< PWM Clock from SYSTEM PLL1 divided by 5.*/
795 kCLOCK_PwmRootmuxSysPll1Div20 = 3U, /*!< PWM Clock from SYSTEM PLL1 divided by 20.*/
796 kCLOCK_PwmRootmuxSystemPll3 = 4U, /*!< PWM Clock from SYSTEM PLL3.*/
797 kCLOCK_PwmRootmuxExtClk12 = 5U, /*!< PWM Clock from External Clock1, External Clock2.*/
798 kCLOCK_PwmRootmuxSystemPll1Div10 = 6U, /*!< PWM Clock from SYSTEM PLL1 divided by 10.*/
799 kCLOCK_PwmRootmuxVideoPll1 = 7U, /*!< PWM Clock from VIDEO PLL1.*/
800 } clock_rootmux_Pwm_clk_sel_t;
801
802 /*! @brief Root clock select enumeration for SAI peripheral. */
803 typedef enum _clock_rootmux_sai_clk_sel
804 {
805 kCLOCK_SaiRootmuxOsc24M = 0U, /*!< SAI Clock from OSC 24M.*/
806 kCLOCK_SaiRootmuxAudioPll1 = 1U, /*!< SAI Clock from AUDIO PLL1.*/
807 kCLOCK_SaiRootmuxAudioPll2 = 2U, /*!< SAI Clock from AUDIO PLL2.*/
808 kCLOCK_SaiRootmuxVideoPll1 = 3U, /*!< SAI Clock from VIDEO PLL1.*/
809 kCLOCK_SaiRootmuxSysPll1Div6 = 4U, /*!< SAI Clock from SYSTEM PLL1 divided by 6.*/
810 kCLOCK_SaiRootmuxOsc26m = 5U, /*!< SAI Clock from OSC HDMI 26M.*/
811 kCLOCK_SaiRootmuxExtClk1 = 6U, /*!< SAI Clock from External Clock1, External Clock2, External Clock3.*/
812 kCLOCK_SaiRootmuxExtClk2 = 7U, /*!< SAI Clock from External Clock2, External Clock3, External Clock4.*/
813 } clock_rootmux_sai_clk_sel_t;
814
815 /*! @brief Root clock select enumeration for PDM peripheral. */
816 typedef enum _clock_rootmux_pdm_clk_sel
817 {
818 kCLOCK_PdmRootmuxOsc24M = 0U, /*!< GPT Clock from OSC 24M.*/
819 kCLOCK_PdmRootmuxSystemPll2 = 1U, /*!< GPT Clock from SYSTEM PLL2 divided by 10.*/
820 kCLOCK_PdmRootmuxAudioPll1 = 2U, /*!< GPT Clock from SYSTEM PLL1 divided by 2.*/
821 kCLOCK_PdmRootmuxSysPll1 = 3U, /*!< GPT Clock from SYSTEM PLL1 divided by 20.*/
822 kCLOCK_PdmRootmuxSysPll2 = 4U, /*!< GPT Clock from VIDEO PLL1.*/
823 kCLOCK_PdmRootmuxSysPll3 = 5U, /*!< GPT Clock from SYSTEM PLL1 divided by 10.*/
824 kCLOCK_PdmRootmuxExtClk3 = 6U, /*!< GPT Clock from AUDIO PLL1.*/
825 kCLOCK_PdmRootmuxAudioPll2 = 7U, /*!< GPT Clock from External Clock1, External Clock2, External Clock3.*/
826 } clock_rootmux_pdm_clk_sel_t;
827
828 /*! @brief Root clock select enumeration for NOC CLK. */
829 typedef enum _clock_rootmux_noc_clk_sel
830 {
831 kCLOCK_NocRootmuxOsc24M = 0U, /*!< NOC Clock from OSC 24M.*/
832 kCLOCK_NocRootmuxSysPll1 = 1U, /*!< NOC Clock from SYSTEM PLL1.*/
833 kCLOCK_NocRootmuxSysPll3 = 2U, /*!< NOC Clock from SYSTEM PLL3.*/
834 kCLOCK_NocRootmuxSysPll2 = 3U, /*!< NOC Clock from SYSTEM PLL2.*/
835 kCLOCK_NocRootmuxSysPll2Div2 = 4U, /*!< NOC Clock from SYSTEM PLL2 divided by 2.*/
836 kCLOCK_NocRootmuxAudioPll1 = 5U, /*!< NOC Clock from AUDIO PLL1.*/
837 kCLOCK_NocRootmuxVideoPll1 = 6U, /*!< NOC Clock from VIDEO PLL1.*/
838 kCLOCK_NocRootmuxAudioPll2 = 7U, /*!< NOC Clock from AUDIO PLL2.*/
839
840 } clock_rootmux_noc_clk_sel_t;
841
842 /*! @brief CCM PLL gate control. */
843 typedef enum _clock_pll_gate
844 {
845 kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /*!< ARM PLL Gate.*/
846
847 kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /*!< GPU PLL Gate.*/
848 kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /*!< VPU PLL Gate.*/
849 kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /*!< DRAM PLL1 Gate.*/
850
851 kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /*!< SYSTEM PLL1 Gate.*/
852 kCLOCK_SysPll1Div2Gate =
853 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /*!< SYSTEM PLL1 Div2 Gate.*/
854 kCLOCK_SysPll1Div3Gate =
855 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /*!< SYSTEM PLL1 Div3 Gate.*/
856 kCLOCK_SysPll1Div4Gate =
857 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /*!< SYSTEM PLL1 Div4 Gate.*/
858 kCLOCK_SysPll1Div5Gate =
859 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /*!< SYSTEM PLL1 Div5 Gate.*/
860 kCLOCK_SysPll1Div6Gate =
861 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /*!< SYSTEM PLL1 Div6 Gate.*/
862 kCLOCK_SysPll1Div8Gate =
863 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[22].PLL_CTRL), /*!< SYSTEM PLL1 Div8 Gate.*/
864 kCLOCK_SysPll1Div10Gate =
865 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[23].PLL_CTRL), /*!< SYSTEM PLL1 Div10 Gate.*/
866 kCLOCK_SysPll1Div20Gate =
867 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[24].PLL_CTRL), /*!< SYSTEM PLL1 Div20 Gate.*/
868
869 kCLOCK_SysPll2Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[25].PLL_CTRL), /*!< SYSTEM PLL2 Gate.*/
870 kCLOCK_SysPll2Div2Gate =
871 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[26].PLL_CTRL), /*!< SYSTEM PLL2 Div2 Gate.*/
872 kCLOCK_SysPll2Div3Gate =
873 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[27].PLL_CTRL), /*!< SYSTEM PLL2 Div3 Gate.*/
874 kCLOCK_SysPll2Div4Gate =
875 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[28].PLL_CTRL), /*!< SYSTEM PLL2 Div4 Gate.*/
876 kCLOCK_SysPll2Div5Gate =
877 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[29].PLL_CTRL), /*!< SYSTEM PLL2 Div5 Gate.*/
878 kCLOCK_SysPll2Div6Gate =
879 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[30].PLL_CTRL), /*!< SYSTEM PLL2 Div6 Gate.*/
880 kCLOCK_SysPll2Div8Gate =
881 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[31].PLL_CTRL), /*!< SYSTEM PLL2 Div8 Gate.*/
882 kCLOCK_SysPll2Div10Gate =
883 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[32].PLL_CTRL), /*!< SYSTEM PLL2 Div10 Gate.*/
884 kCLOCK_SysPll2Div20Gate =
885 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[33].PLL_CTRL), /*!< SYSTEM PLL2 Div20 Gate.*/
886
887 kCLOCK_SysPll3Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[34].PLL_CTRL), /*!< SYSTEM PLL3 Gate.*/
888
889 kCLOCK_AudioPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[35].PLL_CTRL), /*!< AUDIO PLL1 Gate.*/
890 kCLOCK_AudioPll2Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[36].PLL_CTRL), /*!< AUDIO PLL2 Gate.*/
891 kCLOCK_VideoPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[37].PLL_CTRL), /*!< VIDEO PLL1 Gate.*/
892 kCLOCK_VideoPll2Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[38].PLL_CTRL), /*!< VIDEO PLL2 Gate.*/
893 } clock_pll_gate_t;
894
895 /*! @brief CCM gate control value. */
896 typedef enum _clock_gate_value
897 {
898 kCLOCK_ClockNotNeeded = 0x0U, /*!< Clock always disabled.*/
899 kCLOCK_ClockNeededRun = 0x1111U, /*!< Clock enabled when CPU is running.*/
900 kCLOCK_ClockNeededRunWait = 0x2222U, /*!< Clock enabled when CPU is running or in WAIT mode.*/
901 kCLOCK_ClockNeededAll = 0x3333U, /*!< Clock always enabled.*/
902 } clock_gate_value_t;
903
904 /*!
905 * @brief PLL control names for PLL bypass.
906 *
907 * These constants define the PLL control names for PLL bypass.\n
908 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
909 * - 16:20: bypass bit shift.
910 */
911 typedef enum _clock_pll_bypass_ctrl
912 {
913 kCLOCK_AudioPll1BypassCtrl =
914 CCM_ANALOG_TUPLE(AUDIO_PLL1_GEN_CTRL_OFFSET,
915 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL1 bypass Control.*/
916
917 kCLOCK_AudioPll2BypassCtrl =
918 CCM_ANALOG_TUPLE(AUDIO_PLL2_GEN_CTRL_OFFSET,
919 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL2 bypass Control.*/
920
921 kCLOCK_VideoPll1BypassCtrl =
922 CCM_ANALOG_TUPLE(VIDEO_PLL1_GEN_CTRL_OFFSET,
923 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Video Pll1 bypass Control.*/
924
925 kCLOCK_DramPllInternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
926 DRAM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM DRAM PLL bypass Control.*/
927
928 kCLOCK_ArmPllPwrBypassCtrl = CCM_ANALOG_TUPLE(
929 ARM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Arm PLL bypass Control.*/
930
931 kCLOCK_SysPll1InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
932 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM System PLL1 bypass Control.*/
933
934 kCLOCK_SysPll2InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
935 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM System PLL2 bypass Control.*/
936
937 kCLOCK_SysPll3InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
938 SYS_PLL3_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM System PLL3 bypass Control.*/
939 } clock_pll_bypass_ctrl_t;
940
941 /*!
942 * @brief PLL clock names for clock enable/disable settings.
943 *
944 * These constants define the PLL clock names for PLL clock enable/disable operations.\n
945 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
946 * - 16:20: Clock enable bit shift.
947 */
948 typedef enum _ccm_analog_pll_clke
949 {
950 kCLOCK_AudioPll1Clke = CCM_ANALOG_TUPLE(AUDIO_PLL1_GEN_CTRL_OFFSET,
951 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Audio pll1 clke */
952 kCLOCK_AudioPll2Clke = CCM_ANALOG_TUPLE(AUDIO_PLL2_GEN_CTRL_OFFSET,
953 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Audio pll2 clke */
954 kCLOCK_VideoPll1Clke = CCM_ANALOG_TUPLE(VIDEO_PLL1_GEN_CTRL_OFFSET,
955 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Video pll1 clke */
956 kCLOCK_DramPllClke =
957 CCM_ANALOG_TUPLE(DRAM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Dram pll clke */
958
959 kCLOCK_ArmPllClke =
960 CCM_ANALOG_TUPLE(ARM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Arm pll clke */
961
962 kCLOCK_SystemPll1Clke = CCM_ANALOG_TUPLE(SYS_PLL1_GEN_CTRL_OFFSET,
963 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT), /*!< System pll1 clke */
964 kCLOCK_SystemPll1Div2Clke = CCM_ANALOG_TUPLE(
965 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT), /*!< System pll1 Div2 clke */
966 kCLOCK_SystemPll1Div3Clke = CCM_ANALOG_TUPLE(
967 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT), /*!< System pll1 Div3 clke */
968 kCLOCK_SystemPll1Div4Clke = CCM_ANALOG_TUPLE(
969 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT), /*!< System pll1 Div4 clke */
970 kCLOCK_SystemPll1Div5Clke = CCM_ANALOG_TUPLE(
971 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT), /*!< System pll1 Div5 clke */
972 kCLOCK_SystemPll1Div6Clke = CCM_ANALOG_TUPLE(
973 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT), /*!< System pll1 Div6 clke */
974 kCLOCK_SystemPll1Div8Clke = CCM_ANALOG_TUPLE(
975 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT), /*!< System pll1 Div8 clke */
976 kCLOCK_SystemPll1Div10Clke = CCM_ANALOG_TUPLE(
977 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT), /*!< System pll1 Div10 clke */
978 kCLOCK_SystemPll1Div20Clke = CCM_ANALOG_TUPLE(
979 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT), /*!< System pll1 Div20 clke */
980
981 kCLOCK_SystemPll2Clke = CCM_ANALOG_TUPLE(SYS_PLL2_GEN_CTRL_OFFSET,
982 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT), /*!< System pll2 clke */
983 kCLOCK_SystemPll2Div2Clke = CCM_ANALOG_TUPLE(
984 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT), /*!< System pll2 Div2 clke */
985 kCLOCK_SystemPll2Div3Clke = CCM_ANALOG_TUPLE(
986 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT), /*!< System pll2 Div3 clke */
987 kCLOCK_SystemPll2Div4Clke = CCM_ANALOG_TUPLE(
988 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT), /*!< System pll2 Div4 clke */
989 kCLOCK_SystemPll2Div5Clke = CCM_ANALOG_TUPLE(
990 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT), /*!< System pll2 Div5 clke */
991 kCLOCK_SystemPll2Div6Clke = CCM_ANALOG_TUPLE(
992 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT), /*!< System pll2 Div6 clke */
993 kCLOCK_SystemPll2Div8Clke = CCM_ANALOG_TUPLE(
994 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT), /*!< System pll2 Div8 clke */
995 kCLOCK_SystemPll2Div10Clke = CCM_ANALOG_TUPLE(
996 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT), /*!< System pll2 Div10 clke */
997 kCLOCK_SystemPll2Div20Clke = CCM_ANALOG_TUPLE(
998 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT), /*!< System pll2 Div20 clke */
999
1000 kCLOCK_SystemPll3Clke = CCM_ANALOG_TUPLE(SYS_PLL3_GEN_CTRL_OFFSET,
1001 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT), /*!< System pll3 clke */
1002 } clock_pll_clke_t;
1003
1004 /*!
1005 * @brief ANALOG Power down override control.
1006 */
1007 typedef enum _clock_pll_ctrl
1008 {
1009 /* Fractional PLL frequency */
1010 kCLOCK_AudioPll1Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT),
1011 kCLOCK_AudioPll2Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT),
1012 kCLOCK_VideoPll1Ctrl = CCM_ANALOG_TUPLE(VIDEO_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT),
1013 kCLOCK_DramPllCtrl = CCM_ANALOG_TUPLE(DRAM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT),
1014 /* Integer PLL frequency */
1015 kCLOCK_ArmPllCtrl = CCM_ANALOG_TUPLE(ARM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT),
1016 kCLOCK_SystemPll1Ctrl = CCM_ANALOG_TUPLE(SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT),
1017 kCLOCK_SystemPll2Ctrl = CCM_ANALOG_TUPLE(SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT),
1018 kCLOCK_SystemPll3Ctrl = CCM_ANALOG_TUPLE(SYS_PLL3_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT),
1019 } clock_pll_ctrl_t;
1020
1021 /*! @brief PLL reference clock select. */
1022 enum
1023 {
1024 kANALOG_PllRefOsc24M = 0U, /*!< reference OSC 24M */
1025 kANALOG_PllPadClk = 1U, /*!< reference PAD CLK */
1026 };
1027
1028 /*!
1029 * @brief Fractional-N PLL configuration.
1030 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
1031 * value
1032 */
1033 typedef struct _ccm_analog_frac_pll_config
1034 {
1035 uint8_t refSel; /*!< pll reference clock sel */
1036
1037 uint32_t mainDiv; /*!< Value of the 10-bit programmable main-divider, range must be 64~1023 */
1038
1039 uint32_t dsm; /*!< Value of 16-bit DSM */
1040
1041 uint8_t preDiv; /*!< Value of the 6-bit programmable pre-divider, range must be 1~63 */
1042
1043 uint8_t postDiv; /*!< Value of the 3-bit programmable Scaler, range must be 0~6 */
1044 } ccm_analog_frac_pll_config_t;
1045
1046 /*!
1047 * @brief Integer PLL configuration.
1048 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
1049 * value
1050 */
1051 typedef struct _ccm_analog_integer_pll_config
1052 {
1053 uint8_t refSel; /*!< pll reference clock sel */
1054
1055 uint32_t mainDiv; /*!< Value of the 10-bit programmable main-divider, range must be 64~1023 */
1056
1057 uint8_t preDiv; /*!< Value of the 6-bit programmable pre-divider, range must be 1~63 */
1058
1059 uint8_t postDiv; /*!< Value of the 3-bit programmable Scaler, range must be 0~6 */
1060
1061 } ccm_analog_integer_pll_config_t;
1062
1063 /*******************************************************************************
1064 * API
1065 ******************************************************************************/
1066
1067 #if defined(__cplusplus)
1068 extern "C" {
1069 #endif
1070
1071 /*!
1072 * @name CCM Root Clock Setting
1073 * @{
1074 */
1075
1076 /*!
1077 * @brief Set clock root mux.
1078 * User maybe need to set more than one mux ROOT according to the clock tree
1079 * description in the reference manual.
1080 *
1081 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
1082 * @param mux Root mux value, refer to _ccm_rootmux_xxx enumeration.
1083 */
CLOCK_SetRootMux(clock_root_control_t rootClk,uint32_t mux)1084 static inline void CLOCK_SetRootMux(clock_root_control_t rootClk, uint32_t mux)
1085 {
1086 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux);
1087 }
1088
1089 /*!
1090 * @brief Get clock root mux.
1091 * In order to get the clock source of root, user maybe need to get more than one
1092 * ROOT's mux value to obtain the final clock source of root.
1093 *
1094 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
1095 * @return Root mux value, refer to _ccm_rootmux_xxx enumeration.
1096 */
CLOCK_GetRootMux(clock_root_control_t rootClk)1097 static inline uint32_t CLOCK_GetRootMux(clock_root_control_t rootClk)
1098 {
1099 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT;
1100 }
1101
1102 /*!
1103 * @brief Enable clock root
1104 *
1105 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration)
1106 */
CLOCK_EnableRoot(clock_root_control_t rootClk)1107 static inline void CLOCK_EnableRoot(clock_root_control_t rootClk)
1108 {
1109 CCM_REG_SET(rootClk) = CCM_TARGET_ROOT_SET_ENABLE_MASK;
1110 }
1111
1112 /*!
1113 * @brief Disable clock root
1114 *
1115 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
1116 */
CLOCK_DisableRoot(clock_root_control_t rootClk)1117 static inline void CLOCK_DisableRoot(clock_root_control_t rootClk)
1118 {
1119 CCM_REG_CLR(rootClk) = CCM_TARGET_ROOT_CLR_ENABLE_MASK;
1120 }
1121
1122 /*!
1123 * @brief Check whether clock root is enabled
1124 *
1125 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
1126 * @return CCM root enabled or not.
1127 * - true: Clock root is enabled.
1128 * - false: Clock root is disabled.
1129 */
CLOCK_IsRootEnabled(clock_root_control_t rootClk)1130 static inline bool CLOCK_IsRootEnabled(clock_root_control_t rootClk)
1131 {
1132 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK);
1133 }
1134
1135 /*!
1136 * @brief Update clock root in one step, for dynamical clock switching
1137 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
1138 *
1139 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
1140 * @param mux Root mux value, refer to _ccm_rootmux_xxx enumeration
1141 * @param pre Pre divider value (0-7, divider=n+1)
1142 * @param post Post divider value (0-63, divider=n+1)
1143 */
1144 void CLOCK_UpdateRoot(clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post);
1145
1146 /*!
1147 * @brief Set root clock divider
1148 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
1149 *
1150 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
1151 * @param pre Pre divider value (1-8)
1152 * @param post Post divider value (1-64)
1153 */
1154 void CLOCK_SetRootDivider(clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post);
1155
1156 /*!
1157 * @brief Get clock root PRE_PODF.
1158 * In order to get the clock source of root, user maybe need to get more than one
1159 * ROOT's mux value to obtain the final clock source of root.
1160 *
1161 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
1162 * @return Root Pre divider value.
1163 */
CLOCK_GetRootPreDivider(clock_root_control_t rootClk)1164 static inline uint32_t CLOCK_GetRootPreDivider(clock_root_control_t rootClk)
1165 {
1166 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U;
1167 }
1168
1169 /*!
1170 * @brief Get clock root POST_PODF.
1171 * In order to get the clock source of root, user maybe need to get more than one
1172 * ROOT's mux value to obtain the final clock source of root.
1173 *
1174 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
1175 * @return Root Post divider value.
1176 */
CLOCK_GetRootPostDivider(clock_root_control_t rootClk)1177 static inline uint32_t CLOCK_GetRootPostDivider(clock_root_control_t rootClk)
1178 {
1179 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + 1U;
1180 }
1181
1182 /*!
1183 * @name CCM Gate Control
1184 * @{
1185 */
1186
1187 /*!
1188 * lockrief Set PLL or CCGR gate control
1189 *
1190 * @param ccmGate Gate control (see @ref clock_pll_gate_t and @ref clock_ip_name_t enumeration)
1191 * @param control Gate control value (see @ref clock_gate_value_t)
1192 */
CLOCK_ControlGate(uintptr_t ccmGate,clock_gate_value_t control)1193 static inline void CLOCK_ControlGate(uintptr_t ccmGate, clock_gate_value_t control)
1194 {
1195 CCM_REG(ccmGate) = (uint32_t)control;
1196 }
1197
1198 /*!
1199 * @brief Enable CCGR clock gate and root clock gate for each module
1200 * User should set specific gate for each module according to the description
1201 * of the table of system clocks, gating and override in CCM chapter of
1202 * reference manual. Take care of that one module may need to set more than
1203 * one clock gate.
1204 *
1205 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
1206 */
1207 void CLOCK_EnableClock(clock_ip_name_t ccmGate);
1208
1209 /*!
1210 * @brief Disable CCGR clock gate for the each module
1211 * User should set specific gate for each module according to the description
1212 * of the table of system clocks, gating and override in CCM chapter of
1213 * reference manual. Take care of that one module may need to set more than
1214 * one clock gate.
1215 *
1216 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
1217 */
1218 void CLOCK_DisableClock(clock_ip_name_t ccmGate);
1219
1220 /*!
1221 * @name CCM Analog PLL Operatoin Functions
1222 * @{
1223 */
1224
1225 /*!
1226 * @brief Power up PLL
1227 *
1228 * @param base CCM_ANALOG base pointer.
1229 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
1230 */
CLOCK_PowerUpPll(CCM_ANALOG_Type * base,clock_pll_ctrl_t pllControl)1231 static inline void CLOCK_PowerUpPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
1232 {
1233 CCM_ANALOG_TUPLE_REG(base, pllControl) |= (1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
1234 }
1235
1236 /*!
1237 * @brief Power down PLL
1238 *
1239 * @param base CCM_ANALOG base pointer.
1240 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
1241 */
CLOCK_PowerDownPll(CCM_ANALOG_Type * base,clock_pll_ctrl_t pllControl)1242 static inline void CLOCK_PowerDownPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
1243 {
1244 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
1245 }
1246
1247 /*!
1248 * @brief PLL bypass setting
1249 *
1250 * @param base CCM_ANALOG base pointer.
1251 * @param pllControl PLL control name, refer to ccm_analog_pll_control_t enumeration
1252 * @param bypass Bypass the PLL.
1253 * - true: Bypass the PLL.
1254 * - false: Do not bypass the PLL.
1255 */
CLOCK_SetPllBypass(CCM_ANALOG_Type * base,clock_pll_bypass_ctrl_t pllControl,bool bypass)1256 static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl, bool bypass)
1257 {
1258 if (bypass)
1259 {
1260 CCM_ANALOG_TUPLE_REG(base, pllControl) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl);
1261 }
1262 else
1263 {
1264 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
1265 }
1266 }
1267
1268 /*!
1269 * @brief Check if PLL is bypassed
1270 *
1271 * @param base CCM_ANALOG base pointer.
1272 * @param pllControl PLL control name, refer to ccm_analog_pll_control_t enumeration
1273 * @return PLL bypass status.
1274 * - true: The PLL is bypassed.
1275 * - false: The PLL is not bypassed.
1276 */
CLOCK_IsPllBypassed(CCM_ANALOG_Type * base,clock_pll_bypass_ctrl_t pllControl)1277 static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl)
1278 {
1279 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl)));
1280 }
1281
1282 /*!
1283 * @brief Check if PLL clock is locked
1284 *
1285 * @param base CCM_ANALOG base pointer.
1286 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
1287 * @return PLL lock status.
1288 * - true: The PLL clock is locked.
1289 * - false: The PLL clock is not locked.
1290 */
CLOCK_IsPllLocked(CCM_ANALOG_Type * base,clock_pll_ctrl_t pllControl)1291 static inline bool CLOCK_IsPllLocked(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
1292 {
1293 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK);
1294 }
1295
1296 /*!
1297 * @brief Enable PLL clock
1298 *
1299 * @param base CCM_ANALOG base pointer.
1300 * @param pllClock PLL clock name, refer to ccm_analog_pll_clock_t enumeration
1301 */
CLOCK_EnableAnalogClock(CCM_ANALOG_Type * base,clock_pll_clke_t pllClock)1302 static inline void CLOCK_EnableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
1303 {
1304 CCM_ANALOG_TUPLE_REG(base, pllClock) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock);
1305 }
1306
1307 /*!
1308 * @brief Disable PLL clock
1309 *
1310 * @param base CCM_ANALOG base pointer.
1311 * @param pllClock PLL clock name, refer to ccm_analog_pll_clock_t enumeration
1312 */
CLOCK_DisableAnalogClock(CCM_ANALOG_Type * base,clock_pll_clke_t pllClock)1313 static inline void CLOCK_DisableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
1314 {
1315 CCM_ANALOG_TUPLE_REG(base, pllClock) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock));
1316 }
1317
1318 /*!
1319 * @brief Override PLL clock output enable
1320 *
1321 * @param base CCM_ANALOG base pointer.
1322 * @param ovClock PLL clock name (see @ref clock_pll_clke_t enumeration)
1323 * @param override Override the PLL.
1324 * - true: Override the PLL clke, CCM will handle it.
1325 * - false: Do not override the PLL clke.
1326 */
CLOCK_OverridePllClke(CCM_ANALOG_Type * base,clock_pll_clke_t ovClock,bool override)1327 static inline void CLOCK_OverridePllClke(CCM_ANALOG_Type *base, clock_pll_clke_t ovClock, bool override)
1328 {
1329 if (override)
1330 {
1331 CCM_ANALOG_TUPLE_REG(base, ovClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL);
1332 }
1333 else
1334 {
1335 CCM_ANALOG_TUPLE_REG(base, ovClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL));
1336 }
1337 }
1338
1339 /*!
1340 * @brief Override PLL power down
1341 *
1342 * @param base CCM_ANALOG base pointer.
1343 * @param pdClock PLL clock name (see @ref clock_pll_ctrl_t enumeration)
1344 * @param override Override the PLL.
1345 * - true: Override the PLL clke, CCM will handle it.
1346 * - false: Do not override the PLL clke.
1347 */
CLOCK_OverridePllPd(CCM_ANALOG_Type * base,clock_pll_ctrl_t pdClock,bool override)1348 static inline void CLOCK_OverridePllPd(CCM_ANALOG_Type *base, clock_pll_ctrl_t pdClock, bool override)
1349 {
1350 if (override)
1351 {
1352 CCM_ANALOG_TUPLE_REG(base, pdClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL);
1353 }
1354 else
1355 {
1356 CCM_ANALOG_TUPLE_REG(base, pdClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL));
1357 }
1358 }
1359
1360 /*!
1361 * @brief Initializes the ANALOG ARM PLL.
1362 *
1363 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1364 *
1365 * @note This function can't detect whether the Arm PLL has been enabled and
1366 * used by some IPs.
1367 */
1368 void CLOCK_InitArmPll(const ccm_analog_integer_pll_config_t *config);
1369
1370 /*!
1371 * @brief De-initialize the ARM PLL.
1372 */
1373 void CLOCK_DeinitArmPll(void);
1374
1375 /*!
1376 * @brief Initializes the ANALOG SYS PLL1.
1377 *
1378 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1379 *
1380 * @note This function can't detect whether the SYS PLL has been enabled and
1381 * used by some IPs.
1382 */
1383 void CLOCK_InitSysPll1(const ccm_analog_integer_pll_config_t *config);
1384
1385 /*!
1386 * @brief De-initialize the System PLL1.
1387 */
1388 void CLOCK_DeinitSysPll1(void);
1389
1390 /*!
1391 * @brief Initializes the ANALOG SYS PLL2.
1392 *
1393 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1394 *
1395 * @note This function can't detect whether the SYS PLL has been enabled and
1396 * used by some IPs.
1397 */
1398 void CLOCK_InitSysPll2(const ccm_analog_integer_pll_config_t *config);
1399
1400 /*!
1401 * @brief De-initialize the System PLL2.
1402 */
1403 void CLOCK_DeinitSysPll2(void);
1404
1405 /*!
1406 * @brief Initializes the ANALOG SYS PLL3.
1407 *
1408 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1409 *
1410 * @note This function can't detect whether the SYS PLL has been enabled and
1411 * used by some IPs.
1412 */
1413 void CLOCK_InitSysPll3(const ccm_analog_integer_pll_config_t *config);
1414
1415 /*!
1416 * @brief De-initialize the System PLL3.
1417 */
1418 void CLOCK_DeinitSysPll3(void);
1419
1420 /*!
1421 * @brief Initializes the ANALOG AUDIO PLL1.
1422 *
1423 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1424 *
1425 * @note This function can't detect whether the AUDIO PLL has been enabled and
1426 * used by some IPs.
1427 */
1428 void CLOCK_InitAudioPll1(const ccm_analog_frac_pll_config_t *config);
1429
1430 /*!
1431 * @brief De-initialize the Audio PLL1.
1432 */
1433 void CLOCK_DeinitAudioPll1(void);
1434
1435 /*!
1436 * @brief Initializes the ANALOG AUDIO PLL2.
1437 *
1438 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1439 *
1440 * @note This function can't detect whether the AUDIO PLL has been enabled and
1441 * used by some IPs.
1442 */
1443 void CLOCK_InitAudioPll2(const ccm_analog_frac_pll_config_t *config);
1444
1445 /*!
1446 * @brief De-initialize the Audio PLL2.
1447 */
1448 void CLOCK_DeinitAudioPll2(void);
1449
1450 /*!
1451 * @brief Initializes the ANALOG VIDEO PLL1.
1452 *
1453 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1454 *
1455 */
1456 void CLOCK_InitVideoPll1(const ccm_analog_frac_pll_config_t *config);
1457
1458 /*!
1459 * @brief De-initialize the Video PLL1.
1460 */
1461 void CLOCK_DeinitVideoPll1(void);
1462
1463 /*!
1464 * @brief Initializes the ANALOG Integer PLL.
1465 *
1466 * @param base CCM ANALOG base address
1467 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1468 * @param type integer pll type
1469 *
1470 */
1471 void CLOCK_InitIntegerPll(CCM_ANALOG_Type *base, const ccm_analog_integer_pll_config_t *config, clock_pll_ctrl_t type);
1472
1473 /*!
1474 * @brief Get the ANALOG Integer PLL clock frequency.
1475 *
1476 * @param base CCM ANALOG base address.
1477 * @param type integer pll type
1478 * @param refClkFreq pll reference clock frequency
1479 * @param pll1Bypass pll1 bypass flag
1480 *
1481 * @return Clock frequency
1482 */
1483 uint32_t CLOCK_GetIntegerPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass);
1484
1485 /*!
1486 * @brief Initializes the ANALOG Fractional PLL.
1487 *
1488 * @param base CCM ANALOG base address.
1489 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1490 * @param type fractional pll type.
1491 *
1492 */
1493 void CLOCK_InitFracPll(CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type);
1494
1495 /*!
1496 * @brief Gets the ANALOG Fractional PLL clock frequency.
1497 *
1498 * @param base CCM_ANALOG base pointer.
1499 * @param type Fractional pll type.
1500 * @param refClkFreq Pll reference clock frequency
1501 *
1502 * @return Clock frequency
1503 */
1504 uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq);
1505
1506 /*!
1507 * @brief Gets PLL clock frequency.
1508 *
1509 * @param pll Fractional pll type.
1510
1511 * @return Clock frequency
1512 */
1513 uint32_t CLOCK_GetPllFreq(clock_pll_ctrl_t pll);
1514
1515 /*!
1516 * @brief Gets PLL reference clock frequency.
1517 *
1518 * @param ctrl Fractional pll type.
1519
1520 * @return Clock frequency
1521 */
1522 uint32_t CLOCK_GetPllRefClkFreq(clock_pll_ctrl_t ctrl);
1523
1524 /*!
1525 * @name CCM Get frequency
1526 * @{
1527 */
1528
1529 /*!
1530 * @brief Gets the clock frequency for a specific clock name.
1531 *
1532 * This function checks the current clock configurations and then calculates
1533 * the clock frequency for a specific clock name defined in clock_name_t.
1534 *
1535 * @param clockName Clock names defined in clock_name_t
1536 * @return Clock frequency value in hertz
1537 */
1538 uint32_t CLOCK_GetFreq(clock_name_t clockName);
1539
1540 /*!
1541 * @brief Gets the frequency of selected clock root.
1542 *
1543 * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
1544 * @return The frequency of selected clock root.
1545 */
1546 uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
1547
1548 /*!
1549 * @brief Get the CCM Cortex M7 core frequency.
1550 *
1551 * @return Clock frequency; If the clock is invalid, returns 0.
1552 */
1553 uint32_t CLOCK_GetCoreM7Freq(void);
1554
1555 /*!
1556 * @brief Get the CCM Axi bus frequency.
1557 *
1558 * @return Clock frequency; If the clock is invalid, returns 0.
1559 */
1560 uint32_t CLOCK_GetAxiFreq(void);
1561
1562 /*!
1563 * @brief Get the CCM Ahb bus frequency.
1564 *
1565 * @return Clock frequency; If the clock is invalid, returns 0.
1566 */
1567 uint32_t CLOCK_GetAhbFreq(void);
1568
1569 /*!
1570 * brief Get the CCM Enet AXI bus frequency.
1571 *
1572 * return Clock frequency; If the clock is invalid, returns 0.
1573 */
1574 uint32_t CLOCK_GetEnetAxiFreq(void);
1575
1576 /* @} */
1577
1578 #if defined(__cplusplus)
1579 }
1580 #endif
1581 /* @} */
1582 #endif
1583
