1 /*
2 * Copyright 2018-2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CLOCK_H_
9 #define _FSL_CLOCK_H_
10
11 #include "fsl_device_registers.h"
12 #include "fsl_common.h"
13 #include <stdint.h>
14 #include <stdbool.h>
15 #include <stddef.h>
16 #include <assert.h>
17
18 /*!
19 * @addtogroup clock
20 * @{
21 */
22
23 /*******************************************************************************
24 * Definitions
25 ******************************************************************************/
26
27 /*! @name Driver version */
28 /*@{*/
29 /*! @brief CLOCK driver version 2.4.0. */
30 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
31 /*@}*/
32
33 /* Definition for delay API in clock driver, users can redefine it to the real application. */
34 #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
35 #define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (400000000UL)
36 #endif
37
38 /*!
39 * @brief XTAL 24M clock frequency.
40 */
41 #define OSC24M_CLK_FREQ 24000000U
42 /*!
43 * @brief pad clock frequency.
44 */
45 #define CLKPAD_FREQ 0U
46
47 /*! @brief Clock ip name array for ECSPI. */
48 #define ECSPI_CLOCKS \
49 { \
50 kCLOCK_IpInvalid, kCLOCK_Ecspi1, kCLOCK_Ecspi2, kCLOCK_Ecspi3, \
51 }
52
53 /*! @brief Clock ip name array for ENET. */
54 #define ENET_CLOCKS \
55 { \
56 kCLOCK_Enet1, \
57 }
58
59 /*! @brief Clock ip name array for GPIO. */
60 #define GPIO_CLOCKS \
61 { \
62 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5, \
63 }
64
65 /*! @brief Clock ip name array for GPT. */
66 #define GPT_CLOCKS \
67 { \
68 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6, \
69 }
70
71 /*! @brief Clock ip name array for I2C. */
72 #define I2C_CLOCKS \
73 { \
74 kCLOCK_IpInvalid, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, \
75 }
76
77 /*! @brief Clock ip name array for IOMUX. */
78 #define IOMUX_CLOCKS \
79 { \
80 kCLOCK_Iomux, \
81 }
82
83 /*! @brief Clock ip name array for IPMUX. */
84 #define IPMUX_CLOCKS \
85 { \
86 kCLOCK_Ipmux1, kCLOCK_Ipmux2, kCLOCK_Ipmux3, kCLOCK_Ipmux4, \
87 }
88
89 /*! @brief Clock ip name array for PWM. */
90 #define PWM_CLOCKS \
91 { \
92 kCLOCK_IpInvalid, kCLOCK_Pwm1, kCLOCK_Pwm2, kCLOCK_Pwm3, kCLOCK_Pwm4, \
93 }
94
95 /*! @brief Clock ip name array for RDC. */
96 #define RDC_CLOCKS \
97 { \
98 kCLOCK_Rdc, \
99 }
100
101 /*! @brief Clock ip name array for SAI. */
102 #define SAI_CLOCKS \
103 { \
104 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4, kCLOCK_Sai5, kCLOCK_Sai6, \
105 }
106
107 /*! @brief Clock ip name array for RDC SEMA42. */
108 #define RDC_SEMA42_CLOCKS \
109 { \
110 kCLOCK_IpInvalid, kCLOCK_Sema42_1, kCLOCK_Sema42_2 \
111 }
112
113 /*! @brief Clock ip name array for UART. */
114 #define UART_CLOCKS \
115 { \
116 kCLOCK_IpInvalid, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, \
117 }
118
119 /*! @brief Clock ip name array for USDHC. */
120 #define USDHC_CLOCKS \
121 { \
122 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2, kCLOCK_Usdhc3 \
123 }
124
125 /*! @brief Clock ip name array for WDOG. */
126 #define WDOG_CLOCKS \
127 { \
128 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3 \
129 }
130
131 /*! @brief Clock ip name array for TEMPSENSOR. */
132 #define TMU_CLOCKS \
133 { \
134 kCLOCK_TempSensor, \
135 }
136
137 /*! @brief Clock ip name array for SDMA. */
138 #define SDMA_CLOCKS \
139 { \
140 kCLOCK_Sdma1, kCLOCK_Sdma2, kCLOCK_Sdma3 \
141 }
142
143 /*! @brief Clock ip name array for MU. */
144 #define MU_CLOCKS \
145 { \
146 kCLOCK_Mu \
147 }
148
149 /*! @brief Clock ip name array for QSPI. */
150 #define QSPI_CLOCKS \
151 { \
152 kCLOCK_Qspi \
153 }
154
155 /*! @brief Clock ip name array for PDM. */
156 #define PDM_CLOCKS \
157 { \
158 kCLOCK_Pdm \
159 }
160
161 /*!
162 * @brief CCM reg macros to extract corresponding registers bit field.
163 */
164 #define CCM_BIT_FIELD_EXTRACTION(val, mask, shift) (((val) & (mask)) >> (shift))
165
166 /*!
167 * @brief CCM reg macros to map corresponding registers.
168 */
169 #define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uintptr_t)(root) + (off))))
170 #define CCM_REG(root) CCM_REG_OFF(root, 0U)
171 #define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
172 #define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
173
174 /*!
175 * @brief CCM Analog registers offset.
176 */
177 #define AUDIO_PLL1_GEN_CTRL_OFFSET 0x00
178 #define AUDIO_PLL2_GEN_CTRL_OFFSET 0x14
179 #define VIDEO_PLL1_GEN_CTRL_OFFSET 0x28
180 #define GPU_PLL_GEN_CTRL_OFFSET 0x64
181 #define VPU_PLL_GEN_CTRL_OFFSET 0x74
182 #define ARM_PLL_GEN_CTRL_OFFSET 0x84
183 #define SYS_PLL1_GEN_CTRL_OFFSET 0x94
184 #define SYS_PLL2_GEN_CTRL_OFFSET 0x104
185 #define SYS_PLL3_GEN_CTRL_OFFSET 0x114
186 #define DRAM_PLL_GEN_CTRL_OFFSET 0x50
187
188 /*!
189 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
190 */
191 #define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFFU) << 16U) | ((shift)))
192 #define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)(tuple)) & 0x1FU)
193 #define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
194 (*((volatile uint32_t *)((uintptr_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFFU) + (off))))
195 #define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
196
197 /*!
198 * @brief CCM CCGR and root tuple
199 */
200 #define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root))
201 #define CCM_TUPLE_CCGR(tuple) ((uintptr_t)(&(CCM)->CCGR[(uint32_t)(tuple) >> 16U].CCGR))
202 #define CCM_TUPLE_ROOT(tuple) ((uintptr_t)(&(CCM)->ROOT[(uint32_t)(tuple)&0xFFFFU].TARGET_ROOT))
203
204 /*!
205 * @brief clock root source
206 */
207 #define CLOCK_ROOT_SOURCE \
208 { \
209 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll2Div4Clk, kCLOCK_SysPll1Div3Clk, kCLOCK_SysPll1Clk, \
210 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll3Clk}, /* Cortex-M4 Clock Root. */ \
211 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div3Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll2Div4Clk, \
212 kCLOCK_SysPll2Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, kCLOCK_NoneName}, /* AXI Clock Root. */ \
213 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, kCLOCK_SysPll2Clk, kCLOCK_SysPll2Div2Clk, \
214 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, kCLOCK_AudioPll2Clk}, /* NOC Clock Root. */ \
215 { \
216 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div6Clk, kCLOCK_SysPll1Clk, \
217 kCLOCK_SysPll1Div2Clk, kCLOCK_SysPll2Div8Clk, kCLOCK_SysPll3Clk, \
218 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk}, /* AHB Clock Root. */ \
219 { \
220 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div6Clk, kCLOCK_SysPll1Clk, \
221 kCLOCK_SysPll1Div2Clk, kCLOCK_SysPll2Div8Clk, kCLOCK_SysPll3Clk, \
222 kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk}, /* IPG Clock Root. */ \
223 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div2Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll2Clk, kCLOCK_SysPll2Div6Clk, \
224 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk}, /* Audio AHB Clock Root. */ \
225 {kCLOCK_Osc24MClk, kCLOCK_SysPll2Div2Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll2Clk, kCLOCK_SysPll2Div6Clk, \
226 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk}, /* Audio IPG Clock Root. */ \
227 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Clk, kCLOCK_SysPll1Div8Clk, kCLOCK_SysPll2Div2Clk, kCLOCK_SysPll2Clk, \
228 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_SysPll1Div3Clk}, /* DRAM ALT Clock Root */ \
229 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
230 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk1, kCLOCK_ExtClk2}, /* SAI1 Clock Root */ \
231 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
232 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk2, kCLOCK_ExtClk3}, /* SAI2 Clock Root */ \
233 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
234 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk3, kCLOCK_ExtClk4}, /* SAI3 Clock Root */ \
235 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
236 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk1, kCLOCK_ExtClk2}, /* SAI4 Clock Root */ \
237 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
238 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk2, kCLOCK_ExtClk3}, /* SAI5 Clock Root. */ \
239 {kCLOCK_Osc24MClk, kCLOCK_AudioPll1Clk, kCLOCK_AudioPll2Clk, kCLOCK_VideoPll1Clk, \
240 kCLOCK_SysPll1Div6Clk, kCLOCK_NoneName, kCLOCK_ExtClk3, kCLOCK_ExtClk4}, /* SAI6 Clock Root */ \
241 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Div2Clk, kCLOCK_SysPll2Div3Clk, \
242 kCLOCK_SysPll2Div2Clk, kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div3Clk, \
243 kCLOCK_SysPll3Clk, kCLOCK_SysPll1Div8Clk}, /* QSPI Clock Root */ \
244 { \
245 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
246 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
247 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C1 Clock Root */ \
248 { \
249 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
250 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
251 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C2 Clock Root */ \
252 { \
253 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
254 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
255 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C3 Clock Root */ \
256 { \
257 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll2Div20Clk, \
258 kCLOCK_SysPll3Clk, kCLOCK_AudioPll1Clk, kCLOCK_VideoPll1Clk, \
259 kCLOCK_AudioPll2Clk, kCLOCK_SysPll1Div6Clk}, /* I2C4 Clock Root */ \
260 { \
261 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
262 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
263 kCLOCK_ExtClk4, kCLOCK_AudioPll2Clk}, /* UART1 Clock Root */ \
264 { \
265 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
266 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
267 kCLOCK_ExtClk3, kCLOCK_AudioPll2Clk}, /* UART2 Clock Root */ \
268 { \
269 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
270 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
271 kCLOCK_ExtClk4, kCLOCK_AudioPll2Clk}, /* UART3 Clock Root */ \
272 { \
273 kCLOCK_Osc24MClk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div5Clk, \
274 kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
275 kCLOCK_ExtClk3, kCLOCK_AudioPll2Clk}, /* UART4 Clock Root */ \
276 { \
277 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div20Clk, \
278 kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, \
279 kCLOCK_SysPll2Div4Clk, kCLOCK_AudioPll2Clk}, /* ECSPI1 Clock ROOT */ \
280 { \
281 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div20Clk, \
282 kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, \
283 kCLOCK_SysPll2Div4Clk, kCLOCK_AudioPll2Clk}, /* ECSPI2 Clock ROOT */ \
284 { \
285 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div5Clk, kCLOCK_SysPll1Div20Clk, \
286 kCLOCK_SysPll1Div5Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll3Clk, \
287 kCLOCK_SysPll2Div4Clk, kCLOCK_AudioPll2Clk}, /* ECSPI3 Clock ROOT */ \
288 { \
289 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
290 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk1, \
291 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM1 Clock ROOT */ \
292 { \
293 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
294 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk1, \
295 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM2 Clock ROOT */ \
296 { \
297 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
298 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
299 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM3 Clock ROOT */ \
300 { \
301 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div5Clk, \
302 kCLOCK_SysPll1Div20Clk, kCLOCK_SysPll3Clk, kCLOCK_ExtClk2, \
303 kCLOCK_SysPll1Div10Clk, kCLOCK_VideoPll1Clk}, /* PWM4 Clock ROOT */ \
304 { \
305 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
306 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
307 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk1}, /* GPT1 Clock ROOT */ \
308 { \
309 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
310 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
311 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk2}, /* GPT2 Clock ROOT */ \
312 { \
313 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
314 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
315 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk3}, /* GPT3 Clock ROOT */ \
316 { \
317 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
318 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
319 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk1}, /* GPT4 Clock ROOT */ \
320 { \
321 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
322 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
323 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk2}, /* GPT5 Clock ROOT */ \
324 { \
325 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_SysPll1Div2Clk, \
326 kCLOCK_SysPll1Div20Clk, kCLOCK_VideoPll1Clk, kCLOCK_SysPll1Div10Clk, \
327 kCLOCK_AudioPll1Clk, kCLOCK_ExtClk3}, /* GPT6 Clock ROOT */ \
328 {kCLOCK_Osc24MClk, kCLOCK_SysPll1Div6Clk, kCLOCK_SysPll1Div5Clk, kCLOCK_NoneName, kCLOCK_SysPll2Div8Clk, \
329 kCLOCK_SysPll3Clk, kCLOCK_SysPll1Div10Clk, kCLOCK_SysPll2Div6Clk}, /* WDOG Clock ROOT */ \
330 { \
331 kCLOCK_Osc24MClk, kCLOCK_SysPll2Div10Clk, kCLOCK_AudioPll1Clk, kCLOCK_SysPll1Clk, kCLOCK_SysPll2Clk, \
332 kCLOCK_SysPll3Clk, kCLOCK_ExtClk3, kCLOCK_AudioPll2Clk}, /* PDM Clock ROOT */ \
333 }
334
335 #define CLOCK_ROOT_CONTROL_TUPLE \
336 { \
337 kCLOCK_RootM4, kCLOCK_RootAxi, kCLOCK_RootNoc, kCLOCK_RootAhb, kCLOCK_RootAhb, kCLOCK_RootAudioAhb, \
338 kCLOCK_RootAudioAhb, kCLOCK_RootDramAlt, kCLOCK_RootSai1, kCLOCK_RootSai2, kCLOCK_RootSai3, \
339 kCLOCK_RootSai4, kCLOCK_RootSai5, kCLOCK_RootSai6, kCLOCK_RootQspi, kCLOCK_RootI2c1, kCLOCK_RootI2c2, \
340 kCLOCK_RootI2c3, kCLOCK_RootI2c4, kCLOCK_RootUart1, kCLOCK_RootUart2, kCLOCK_RootUart3, kCLOCK_RootUart4, \
341 kCLOCK_RootEcspi1, kCLOCK_RootEcspi2, kCLOCK_RootEcspi3, kCLOCK_RootPwm1, kCLOCK_RootPwm2, \
342 kCLOCK_RootPwm3, kCLOCK_RootPwm4, kCLOCK_RootGpt1, kCLOCK_RootGpt2, kCLOCK_RootGpt3, kCLOCK_RootGpt4, \
343 kCLOCK_RootGpt5, kCLOCK_RootGpt6, kCLOCK_RootWdog, kCLOCK_RootPdm, \
344 }
345
346 /*! @brief Clock name used to get clock frequency. */
347 typedef enum _clock_name
348 {
349 kCLOCK_CoreM4Clk, /*!< ARM M4 Core clock */
350
351 kCLOCK_AxiClk, /*!< Main AXI bus clock. */
352 kCLOCK_AhbClk, /*!< AHB bus clock. */
353 kCLOCK_IpgClk, /*!< IPG bus clock. */
354 kCLOCK_PerClk, /*!< Peripheral Clock. */
355 kCLOCK_EnetIpgClk, /*!< ENET IPG Clock. */
356 kCLOCK_Osc24MClk, /*!< OSC 24M clock. */
357 kCLOCK_ArmPllClk, /*!< Arm PLL clock. */
358 kCLOCK_DramPllClk, /*!< Dram PLL clock. */
359 kCLOCK_SysPll1Clk, /*!< Sys PLL1 clock. */
360 kCLOCK_SysPll1Div2Clk, /*!< Sys PLL1 clock divided by 2. */
361 kCLOCK_SysPll1Div3Clk, /*!< Sys PLL1 clock divided by 3. */
362 kCLOCK_SysPll1Div4Clk, /*!< Sys PLL1 clock divided by 4. */
363 kCLOCK_SysPll1Div5Clk, /*!< Sys PLL1 clock divided by 5. */
364 kCLOCK_SysPll1Div6Clk, /*!< Sys PLL1 clock divided by 6. */
365 kCLOCK_SysPll1Div8Clk, /*!< Sys PLL1 clock divided by 8. */
366 kCLOCK_SysPll1Div10Clk, /*!< Sys PLL1 clock divided by 10. */
367 kCLOCK_SysPll1Div20Clk, /*!< Sys PLL1 clock divided by 20. */
368 kCLOCK_SysPll2Clk, /*!< Sys PLL2 clock. */
369 kCLOCK_SysPll2Div2Clk, /*!< Sys PLL2 clock divided by 2. */
370 kCLOCK_SysPll2Div3Clk, /*!< Sys PLL2 clock divided by 3. */
371 kCLOCK_SysPll2Div4Clk, /*!< Sys PLL2 clock divided by 4. */
372 kCLOCK_SysPll2Div5Clk, /*!< Sys PLL2 clock divided by 5. */
373 kCLOCK_SysPll2Div6Clk, /*!< Sys PLL2 clock divided by 6. */
374 kCLOCK_SysPll2Div8Clk, /*!< Sys PLL2 clock divided by 8. */
375 kCLOCK_SysPll2Div10Clk, /*!< Sys PLL2 clock divided by 10. */
376 kCLOCK_SysPll2Div20Clk, /*!< Sys PLL2 clock divided by 20. */
377 kCLOCK_SysPll3Clk, /*!< Sys PLL3 clock. */
378 kCLOCK_AudioPll1Clk, /*!< Audio PLL1 clock. */
379 kCLOCK_AudioPll2Clk, /*!< Audio PLL2 clock. */
380 kCLOCK_VideoPll1Clk, /*!< Video PLL1 clock. */
381 kCLOCK_ExtClk1, /*!< External clock1. */
382 kCLOCK_ExtClk2, /*!< External clock2. */
383 kCLOCK_ExtClk3, /*!< External clock3. */
384 kCLOCK_ExtClk4, /*!< External clock4. */
385 kCLOCK_NoneName, /*!< None Clock Name. */
386 /* -------------------------------- Other clock --------------------------*/
387 } clock_name_t;
388
389 #define kCLOCK_CoreSysClk kCLOCK_CoreM4Clk /*!< For compatible with other platforms without CCM. */
390 #define CLOCK_GetCoreSysClkFreq CLOCK_GetCoreM4Freq /*!< For compatible with other platforms without CCM. */
391
392 /*! @brief CCM CCGR gate control. */
393 typedef enum _clock_ip_name
394 {
395 kCLOCK_IpInvalid = -1,
396
397 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
398
399 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
400
401 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
402 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
403 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
404
405 kCLOCK_Enet1 = CCM_TUPLE(10U, 17U), /*!< ENET1 Clock Gate.*/
406
407 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
408 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
409 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
410 kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U), /*!< GPIO4 Clock Gate.*/
411 kCLOCK_Gpio5 = CCM_TUPLE(15U, 33U), /*!< GPIO5 Clock Gate.*/
412
413 kCLOCK_Gpt1 = CCM_TUPLE(16U, 107U), /*!< GPT1 Clock Gate.*/
414 kCLOCK_Gpt2 = CCM_TUPLE(17U, 108U), /*!< GPT2 Clock Gate.*/
415 kCLOCK_Gpt3 = CCM_TUPLE(18U, 109U), /*!< GPT3 Clock Gate.*/
416 kCLOCK_Gpt4 = CCM_TUPLE(19U, 110U), /*!< GPT4 Clock Gate.*/
417 kCLOCK_Gpt5 = CCM_TUPLE(20U, 111U), /*!< GPT5 Clock Gate.*/
418 kCLOCK_Gpt6 = CCM_TUPLE(21U, 112U), /*!< GPT6 Clock Gate.*/
419
420 kCLOCK_I2c1 = CCM_TUPLE(23U, 90U), /*!< I2C1 Clock Gate.*/
421 kCLOCK_I2c2 = CCM_TUPLE(24U, 91U), /*!< I2C2 Clock Gate.*/
422 kCLOCK_I2c3 = CCM_TUPLE(25U, 92U), /*!< I2C3 Clock Gate.*/
423 kCLOCK_I2c4 = CCM_TUPLE(26U, 93U), /*!< I2C4 Clock Gate.*/
424
425 kCLOCK_Iomux = CCM_TUPLE(27U, 33U), /*!< IOMUX Clock Gate.*/
426 kCLOCK_Ipmux1 = CCM_TUPLE(28U, 33U), /*!< IPMUX1 Clock Gate.*/
427 kCLOCK_Ipmux2 = CCM_TUPLE(29U, 33U), /*!< IPMUX2 Clock Gate.*/
428 kCLOCK_Ipmux3 = CCM_TUPLE(30U, 33U), /*!< IPMUX3 Clock Gate.*/
429 kCLOCK_Ipmux4 = CCM_TUPLE(31U, 33U), /*!< IPMUX4 Clock Gate.*/
430
431 kCLOCK_Mu = CCM_TUPLE(33U, 33U), /*!< MU Clock Gate.*/
432
433 kCLOCK_Ocram = CCM_TUPLE(35U, 16U), /*!< OCRAM Clock Gate.*/
434 kCLOCK_OcramS = CCM_TUPLE(36U, 32U), /*!< OCRAM S Clock Gate.*/
435
436 kCLOCK_Pwm1 = CCM_TUPLE(40U, 103U), /*!< PWM1 Clock Gate.*/
437 kCLOCK_Pwm2 = CCM_TUPLE(41U, 104U), /*!< PWM2 Clock Gate.*/
438 kCLOCK_Pwm3 = CCM_TUPLE(42U, 105U), /*!< PWM3 Clock Gate.*/
439 kCLOCK_Pwm4 = CCM_TUPLE(43U, 106U), /*!< PWM4 Clock Gate.*/
440
441 kCLOCK_Qspi = CCM_TUPLE(47U, 87U), /*!< QSPI Clock Gate.*/
442
443 kCLOCK_Rdc = CCM_TUPLE(49U, 33U), /*!< RDC Clock Gate.*/
444
445 kCLOCK_Sai1 = CCM_TUPLE(51U, 75U), /*!< SAI1 Clock Gate.*/
446 kCLOCK_Sai2 = CCM_TUPLE(52U, 76U), /*!< SAI2 Clock Gate.*/
447 kCLOCK_Sai3 = CCM_TUPLE(53U, 77U), /*!< SAI3 Clock Gate.*/
448 kCLOCK_Sai4 = CCM_TUPLE(54U, 78U), /*!< SAI4 Clock Gate.*/
449 kCLOCK_Sai5 = CCM_TUPLE(55U, 79U), /*!< SAI5 Clock Gate.*/
450 kCLOCK_Sai6 = CCM_TUPLE(56U, 80U), /*!< SAI6 Clock Gate.*/
451
452 kCLOCK_Sdma1 = CCM_TUPLE(58U, 33U), /*!< SDMA1 Clock Gate.*/
453 kCLOCK_Sdma2 = CCM_TUPLE(59U, 35U), /*!< SDMA2 Clock Gate.*/
454
455 kCLOCK_Sec_Debug = CCM_TUPLE(60U, 33U), /*!< SEC_DEBUG Clock Gate.*/
456
457 kCLOCK_Sema42_1 = CCM_TUPLE(61U, 33U), /*!< RDC SEMA42 Clock Gate.*/
458 kCLOCK_Sema42_2 = CCM_TUPLE(62U, 33U), /*!< RDC SEMA42 Clock Gate.*/
459
460 kCLOCK_Sim_display = CCM_TUPLE(63U, 16U), /*!< SIM_Display Clock Gate.*/
461 kCLOCK_Sim_m = CCM_TUPLE(65U, 32U), /*!< SIM_M Clock Gate.*/
462 kCLOCK_Sim_main = CCM_TUPLE(66U, 16U), /*!< SIM_MAIN Clock Gate.*/
463 kCLOCK_Sim_s = CCM_TUPLE(67U, 32U), /*!< SIM_S Clock Gate.*/
464 kCLOCK_Sim_wakeup = CCM_TUPLE(68U, 32U), /*!< SIM_WAKEUP Clock Gate.*/
465
466 kCLOCK_Uart1 = CCM_TUPLE(73U, 94U), /*!< UART1 Clock Gate.*/
467 kCLOCK_Uart2 = CCM_TUPLE(74U, 95U), /*!< UART2 Clock Gate.*/
468 kCLOCK_Uart3 = CCM_TUPLE(75U, 96U), /*!< UART3 Clock Gate.*/
469 kCLOCK_Uart4 = CCM_TUPLE(76U, 97U), /*!< UART4 Clock Gate.*/
470
471 kCLOCK_Usdhc1 = CCM_TUPLE(81U, 88U), /*!< USDHC1 Clock Gate.*/
472 kCLOCK_Usdhc2 = CCM_TUPLE(82U, 89U), /*!< USDHC2 Clock Gate.*/
473 kCLOCK_Wdog1 = CCM_TUPLE(83U, 114U), /*!< WDOG1 Clock Gate.*/
474 kCLOCK_Wdog2 = CCM_TUPLE(84U, 114U), /*!< WDOG2 Clock Gate.*/
475 kCLOCK_Wdog3 = CCM_TUPLE(85U, 114U), /*!< WDOG3 Clock Gate.*/
476
477 kCLOCK_Pdm = CCM_TUPLE(91U, 132U), /*!< PDM Clock Gate.*/
478 kCLOCK_Usdhc3 = CCM_TUPLE(94U, 121U), /*!< USDHC3 Clock Gate.*/
479 kCLOCK_Sdma3 = CCM_TUPLE(95U, 35U), /*!< SDMA3 Clock Gate.*/
480
481 kCLOCK_TempSensor = CCM_TUPLE(98U, 0xFFFF), /*!< TempSensor Clock Gate.*/
482
483 } clock_ip_name_t;
484
485 /*! @brief ccm root name used to get clock frequency. */
486 typedef enum _clock_root_control
487 {
488 kCLOCK_RootM4 =
489 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[1].TARGET_ROOT), /*!< ARM Cortex-M4 Clock control name.*/
490 kCLOCK_RootAxi = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[16].TARGET_ROOT), /*!< AXI Clock control name.*/
491 kCLOCK_RootEnetAxi = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[17].TARGET_ROOT), /*!< ENET AXI Clock control name.*/
492 kCLOCK_RootNoc = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[26].TARGET_ROOT), /*!< NOC Clock control name.*/
493 kCLOCK_RootAhb = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[32].TARGET_ROOT), /*!< AHB Clock control name.*/
494 kCLOCK_RootIpg = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[33].TARGET_ROOT), /*!< IPG Clock control name.*/
495 kCLOCK_RootAudioAhb =
496 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[34].TARGET_ROOT), /*!< Audio AHB Clock control name.*/
497 kCLOCK_RootAudioIpg =
498 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[35].TARGET_ROOT), /*!< Audio IPG Clock control name.*/
499 kCLOCK_RootDramAlt =
500 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[64].TARGET_ROOT), /*!< DRAM ALT Clock control name.*/
501
502 kCLOCK_RootSai1 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[75].TARGET_ROOT), /*!< SAI1 Clock control name.*/
503 kCLOCK_RootSai2 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[76].TARGET_ROOT), /*!< SAI2 Clock control name.*/
504 kCLOCK_RootSai3 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[77].TARGET_ROOT), /*!< SAI3 Clock control name.*/
505 kCLOCK_RootSai4 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[78].TARGET_ROOT), /*!< SAI4 Clock control name.*/
506 kCLOCK_RootSai5 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[79].TARGET_ROOT), /*!< SAI5 Clock control name.*/
507 kCLOCK_RootSai6 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[80].TARGET_ROOT), /*!< SAI6 Clock control name.*/
508
509 kCLOCK_RootEnetRef = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[83].TARGET_ROOT), /*!< ENET Clock control name.*/
510 kCLOCK_RootEnetTimer = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[84].TARGET_ROOT), /*!< ENET TIMER Clock control name.*/
511 kCLOCK_RootEnetPhy = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[85].TARGET_ROOT), /*!< ENET PHY Clock control name.*/
512
513 kCLOCK_RootQspi = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[87].TARGET_ROOT), /*!< QSPI Clock control name.*/
514
515 kCLOCK_RootI2c1 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[90].TARGET_ROOT), /*!< I2C1 Clock control name.*/
516 kCLOCK_RootI2c2 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[91].TARGET_ROOT), /*!< I2C2 Clock control name.*/
517 kCLOCK_RootI2c3 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[92].TARGET_ROOT), /*!< I2C3 Clock control name.*/
518 kCLOCK_RootI2c4 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[93].TARGET_ROOT), /*!< I2C4 Clock control name.*/
519
520 kCLOCK_RootUart1 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[94].TARGET_ROOT), /*!< UART1 Clock control name.*/
521 kCLOCK_RootUart2 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[95].TARGET_ROOT), /*!< UART2 Clock control name.*/
522 kCLOCK_RootUart3 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[96].TARGET_ROOT), /*!< UART3 Clock control name.*/
523 kCLOCK_RootUart4 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[97].TARGET_ROOT), /*!< UART4 Clock control name.*/
524
525 kCLOCK_RootEcspi1 =
526 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[101].TARGET_ROOT), /*!< ECSPI1 Clock control name.*/
527 kCLOCK_RootEcspi2 =
528 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[102].TARGET_ROOT), /*!< ECSPI2 Clock control name.*/
529 kCLOCK_RootEcspi3 =
530 (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[131].TARGET_ROOT), /*!< ECSPI3 Clock control name.*/
531
532 kCLOCK_RootPwm1 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[103].TARGET_ROOT), /*!< PWM1 Clock control name.*/
533 kCLOCK_RootPwm2 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[104].TARGET_ROOT), /*!< PWM2 Clock control name.*/
534 kCLOCK_RootPwm3 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[105].TARGET_ROOT), /*!< PWM3 Clock control name.*/
535 kCLOCK_RootPwm4 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[106].TARGET_ROOT), /*!< PWM4 Clock control name.*/
536
537 kCLOCK_RootGpt1 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[107].TARGET_ROOT), /*!< GPT1 Clock control name.*/
538 kCLOCK_RootGpt2 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[108].TARGET_ROOT), /*!< GPT2 Clock control name.*/
539 kCLOCK_RootGpt3 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[109].TARGET_ROOT), /*!< GPT3 Clock control name.*/
540 kCLOCK_RootGpt4 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[110].TARGET_ROOT), /*!< GPT4 Clock control name.*/
541 kCLOCK_RootGpt5 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[111].TARGET_ROOT), /*!< GPT5 Clock control name.*/
542 kCLOCK_RootGpt6 = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[112].TARGET_ROOT), /*!< GPT6 Clock control name.*/
543
544 kCLOCK_RootWdog = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[114].TARGET_ROOT), /*!< WDOG Clock control name.*/
545
546 kCLOCK_RootPdm = (uintptr_t)CCM_BASE + offsetof(CCM_Type, ROOT[132].TARGET_ROOT), /*!< PDM Clock control name.*/
547
548 } clock_root_control_t;
549
550 /*! @brief ccm clock root used to get clock frequency. */
551 typedef enum _clock_root
552 {
553 kCLOCK_M4ClkRoot = 0, /*!< ARM Cortex-M4 Clock control name.*/
554 kCLOCK_AxiClkRoot, /*!< AXI Clock control name.*/
555 kCLOCK_NocClkRoot, /*!< NOC Clock control name.*/
556 kCLOCK_AhbClkRoot, /*!< AHB Clock control name.*/
557 kCLOCK_IpgClkRoot, /*!< IPG Clock control name.*/
558 kCLOCK_AudioAhbClkRoot, /*!< Audio AHB Clock control name.*/
559 kCLOCK_AudioIpgClkRoot, /*!< Audio IPG Clock control name.*/
560 kCLOCK_DramAltClkRoot, /*!< DRAM ALT Clock control name.*/
561
562 kCLOCK_Sai1ClkRoot, /*!< SAI1 Clock control name.*/
563 kCLOCK_Sai2ClkRoot, /*!< SAI2 Clock control name.*/
564 kCLOCK_Sai3ClkRoot, /*!< SAI3 Clock control name.*/
565 kCLOCK_Sai4ClkRoot, /*!< SAI4 Clock control name.*/
566 kCLOCK_Sai5ClkRoot, /*!< SAI5 Clock control name.*/
567 kCLOCK_Sai6ClkRoot, /*!< SAI6 Clock control name.*/
568
569 kCLOCK_QspiClkRoot, /*!< QSPI Clock control name.*/
570
571 kCLOCK_I2c1ClkRoot, /*!< I2C1 Clock control name.*/
572 kCLOCK_I2c2ClkRoot, /*!< I2C2 Clock control name.*/
573 kCLOCK_I2c3ClkRoot, /*!< I2C3 Clock control name.*/
574 kCLOCK_I2c4ClkRoot, /*!< I2C4 Clock control name.*/
575
576 kCLOCK_Uart1ClkRoot, /*!< UART1 Clock control name.*/
577 kCLOCK_Uart2ClkRoot, /*!< UART2 Clock control name.*/
578 kCLOCK_Uart3ClkRoot, /*!< UART3 Clock control name.*/
579 kCLOCK_Uart4ClkRoot, /*!< UART4 Clock control name.*/
580
581 kCLOCK_Ecspi1ClkRoot, /*!< ECSPI1 Clock control name.*/
582 kCLOCK_Ecspi2ClkRoot, /*!< ECSPI2 Clock control name.*/
583 kCLOCK_Ecspi3ClkRoot, /*!< ECSPI3 Clock control name.*/
584
585 kCLOCK_Pwm1ClkRoot, /*!< PWM1 Clock control name.*/
586 kCLOCK_Pwm2ClkRoot, /*!< PWM2 Clock control name.*/
587 kCLOCK_Pwm3ClkRoot, /*!< PWM3 Clock control name.*/
588 kCLOCK_Pwm4ClkRoot, /*!< PWM4 Clock control name.*/
589
590 kCLOCK_Gpt1ClkRoot, /*!< GPT1 Clock control name.*/
591 kCLOCK_Gpt2ClkRoot, /*!< GPT2 Clock control name.*/
592 kCLOCK_Gpt3ClkRoot, /*!< GPT3 Clock control name.*/
593 kCLOCK_Gpt4ClkRoot, /*!< GPT4 Clock control name.*/
594 kCLOCK_Gpt5ClkRoot, /*!< GPT5 Clock control name.*/
595 kCLOCK_Gpt6ClkRoot, /*!< GPT6 Clock control name.*/
596
597 kCLOCK_WdogClkRoot, /*!< WDOG Clock control name.*/
598
599 kCLOCK_PdmClkRoot, /*!< PDM Clock control name.*/
600
601 } clock_root_t;
602
603 /*! @brief Root clock select enumeration for ARM Cortex-M4 core. */
604 typedef enum _clock_rootmux_m4_clk_sel
605 {
606 kCLOCK_M4RootmuxOsc24M = 0U, /*!< ARM Cortex-M4 Clock from OSC 24M.*/
607 kCLOCK_M4RootmuxSysPll2Div5 = 1U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 5.*/
608 kCLOCK_M4RootmuxSysPll2Div4 = 2U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL2 divided by 4.*/
609 kCLOCK_M4RootmuxSysPll1Div3 = 3U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL1 divided by 3.*/
610 kCLOCK_M4RootmuxSysPll1 = 4U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL1.*/
611 kCLOCK_M4RootmuxAudioPll1 = 5U, /*!< ARM Cortex-M4 Clock from AUDIO PLL1.*/
612 kCLOCK_M4RootmuxVideoPll1 = 6U, /*!< ARM Cortex-M4 Clock from VIDEO PLL1.*/
613 kCLOCK_M4RootmuxSysPll3 = 7U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL3.*/
614 } clock_rootmux_m4_clk_sel_t;
615
616 /*! @brief Root clock select enumeration for AXI bus. */
617 typedef enum _clock_rootmux_axi_clk_sel
618 {
619 kCLOCK_AxiRootmuxOsc24M = 0U, /*!< ARM AXI Clock from OSC 24M.*/
620 kCLOCK_AxiRootmuxSysPll2Div3 = 1U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 3.*/
621 kCLOCK_AxiRootmuxSysPll1 = 2U, /*!< ARM AXI Clock from SYSTEM PLL1.*/
622 kCLOCK_AxiRootmuxSysPll2Div4 = 3U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 4.*/
623 kCLOCK_AxiRootmuxSysPll2 = 4U, /*!< ARM AXI Clock from SYSTEM PLL2.*/
624 kCLOCK_AxiRootmuxAudioPll1 = 5U, /*!< ARM AXI Clock from AUDIO PLL1.*/
625 kCLOCK_AxiRootmuxVideoPll1 = 6U, /*!< ARM AXI Clock from VIDEO PLL1.*/
626 kCLOCK_AxiRootmuxSysPll1Div8 = 7U, /*!< ARM AXI Clock from SYSTEM PLL1 divided by 8.*/
627 } clock_rootmux_axi_clk_sel_t;
628
629 /*! @brief Root clock select enumeration for AHB bus. */
630 typedef enum _clock_rootmux_ahb_clk_sel
631 {
632 kCLOCK_AhbRootmuxOsc24M = 0U, /*!< ARM AHB Clock from OSC 24M.*/
633 kCLOCK_AhbRootmuxSysPll1Div6 = 1U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 6.*/
634 kCLOCK_AhbRootmuxSysPll1 = 2U, /*!< ARM AHB Clock from SYSTEM PLL1.*/
635 kCLOCK_AhbRootmuxSysPll1Div2 = 3U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 2.*/
636 kCLOCK_AhbRootmuxSysPll2Div8 = 4U, /*!< ARM AHB Clock from SYSTEM PLL2 divided by 8.*/
637 kCLOCK_AhbRootmuxSysPll3 = 5U, /*!< ARM AHB Clock from SYSTEM PLL3.*/
638 kCLOCK_AhbRootmuxAudioPll1 = 6U, /*!< ARM AHB Clock from AUDIO PLL1.*/
639 kCLOCK_AhbRootmuxVideoPll1 = 7U, /*!< ARM AHB Clock from VIDEO PLL1.*/
640 } clock_rootmux_ahb_clk_sel_t;
641
642 /*! @brief Root clock select enumeration for Audio AHB bus. */
643 typedef enum _clock_rootmux_audio_ahb_clk_sel
644 {
645 kCLOCK_AudioAhbRootmuxOsc24M = 0U, /*!< ARM Audio AHB Clock from OSC 24M.*/
646 kCLOCK_AudioAhbRootmuxSysPll2Div2 = 1U, /*!< ARM Audio AHB Clock from SYSTEM PLL2 divided by 2.*/
647 kCLOCK_AudioAhbRootmuxSysPll1 = 2U, /*!< ARM Audio AHB Clock from SYSTEM PLL1.*/
648 kCLOCK_AudioAhbRootmuxSysPll2 = 3U, /*!< ARM Audio AHB Clock from SYSTEM PLL2.*/
649 kCLOCK_AudioAhbRootmuxSysPll2Div6 = 4U, /*!< ARM Audio AHB Clock from SYSTEM PLL2 divided by 6.*/
650 kCLOCK_AudioAhbRootmuxSysPll3 = 5U, /*!< ARM Audio AHB Clock from SYSTEM PLL3.*/
651 kCLOCK_AudioAhbRootmuxAudioPll1 = 6U, /*!< ARM Audio AHB Clock from AUDIO PLL1.*/
652 kCLOCK_AudioAhbRootmuxVideoPll1 = 7U, /*!< ARM Audio AHB Clock from VIDEO PLL1.*/
653 } clock_rootmux_audio_ahb_clk_sel_t;
654 /*! @brief Root clock select enumeration for QSPI peripheral. */
655 typedef enum _clock_rootmux_qspi_clk_sel
656 {
657 kCLOCK_QspiRootmuxOsc24M = 0U, /*!< ARM QSPI Clock from OSC 24M.*/
658 kCLOCK_QspiRootmuxSysPll1Div2 = 1U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 2.*/
659 kCLOCK_QspiRootmuxSysPll2Div3 = 2U, /*!< ARM QSPI Clock from SYSTEM PLL2 divided by 3.*/
660 kCLOCK_QspiRootmuxSysPll2Div2 = 3U, /*!< ARM QSPI Clock from SYSTEM PLL2 divided by 2.*/
661 kCLOCK_QspiRootmuxAudioPll2 = 4U, /*!< ARM QSPI Clock from AUDIO PLL2.*/
662 kCLOCK_QspiRootmuxSysPll1Div3 = 5U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 3 */
663 kCLOCK_QspiRootmuxSysPll3 = 6, /*!< ARM QSPI Clock from SYSTEM PLL3.*/
664 kCLOCK_QspiRootmuxSysPll1Div8 = 7U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 8.*/
665 } clock_rootmux_qspi_clk_sel_t;
666
667 /*! @brief Root clock select enumeration for ECSPI peripheral. */
668 typedef enum _clock_rootmux_ecspi_clk_sel
669 {
670 kCLOCK_EcspiRootmuxOsc24M = 0U, /*!< ECSPI Clock from OSC 24M.*/
671 kCLOCK_EcspiRootmuxSysPll2Div5 = 1U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 5.*/
672 kCLOCK_EcspiRootmuxSysPll1Div20 = 2U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 20.*/
673 kCLOCK_EcspiRootmuxSysPll1Div5 = 3U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 5.*/
674 kCLOCK_EcspiRootmuxSysPll1 = 4U, /*!< ECSPI Clock from SYSTEM PLL1.*/
675 kCLOCK_EcspiRootmuxSysPll3 = 5U, /*!< ECSPI Clock from SYSTEM PLL3.*/
676 kCLOCK_EcspiRootmuxSysPll2Div4 = 6U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 4.*/
677 kCLOCK_EcspiRootmuxAudioPll2 = 7U, /*!< ECSPI Clock from AUDIO PLL2.*/
678 } clock_rootmux_ecspi_clk_sel_t;
679
680 /*! @brief Root clock select enumeration for ENET AXI bus. */
681 typedef enum _clock_rootmux_enet_axi_clk_sel
682 {
683 kCLOCK_EnetAxiRootmuxOsc24M = 0U, /*!< ENET AXI Clock from OSC 24M.*/
684 kCLOCK_EnetAxiRootmuxSysPll1Div3 = 1U, /*!< ENET AXI Clock from SYSTEM PLL1 divided by 3.*/
685 kCLOCK_EnetAxiRootmuxSysPll1 = 2U, /*!< ENET AXI Clock from SYSTEM PLL1.*/
686 kCLOCK_EnetAxiRootmuxSysPll2Div4 = 3U, /*!< ENET AXI Clock from SYSTEM PLL2 divided by 4.*/
687 kCLOCK_EnetAxiRootmuxSysPll2Div5 = 4U, /*!< ENET AXI Clock from SYSTEM PLL2 divided by 5.*/
688 kCLOCK_EnetAxiRootmuxAudioPll1 = 5U, /*!< ENET AXI Clock from AUDIO PLL1.*/
689 kCLOCK_EnetAxiRootmuxVideoPll1 = 6U, /*!< ENET AXI Clock from VIDEO PLL1.*/
690 kCLOCK_EnetAxiRootmuxSysPll3 = 7U, /*!< ENET AXI Clock from SYSTEM PLL3.*/
691 } clock_rootmux_enet_axi_clk_sel_t;
692
693 /*! @brief Root clock select enumeration for ENET REF Clcok. */
694 typedef enum _clock_rootmux_enet_ref_clk_sel
695 {
696 kCLOCK_EnetRefRootmuxOsc24M = 0U, /*!< ENET REF Clock from OSC 24M.*/
697 kCLOCK_EnetRefRootmuxSysPll2Div8 = 1U, /*!< ENET REF Clock from SYSTEM PLL2 divided by 8.*/
698 kCLOCK_EnetRefRootmuxSysPll2Div20 = 2U, /*!< ENET REF Clock from SYSTEM PLL2 divided by 20.*/
699 kCLOCK_EnetRefRootmuxSysPll2Div10 = 3U, /*!< ENET REF Clock from SYSTEM PLL2 divided by 10.*/
700 kCLOCK_EnetRefRootmuxSysPll1Div5 = 4U, /*!< ENET REF Clock from SYSTEM PLL1 divided by 5.*/
701 kCLOCK_EnetRefRootmuxAudioPll1 = 5U, /*!< ENET REF Clock from AUDIO PLL1.*/
702 kCLOCK_EnetRefRootmuxVideoPll1 = 6U, /*!< ENET REF Clock from VIDEO PLL1.*/
703 kCLOCK_EnetRefRootmuxExtClk4 = 7U, /*!< ENET REF Clock from External Clock 4.*/
704 } clock_rootmux_enet_ref_clk_sel_t;
705
706 /*! @brief Root clock select enumeration for ENET TIMER Clcok. */
707 typedef enum _clock_rootmux_enet_timer_clk_sel
708 {
709 kCLOCK_EnetTimerRootmuxOsc24M = 0U, /*!< ENET TIMER Clock from OSC 24M.*/
710 kCLOCK_EnetTimerRootmuxSysPll2Div10 = 1U, /*!< ENET TIMER Clock from SYSTEM PLL2 divided by 10.*/
711 kCLOCK_EnetTimerRootmuxAudioPll1 = 2U, /*!< ENET TIMER Clock from AUDIO PLL1.*/
712 kCLOCK_EnetTimerRootmuxExtClk1 = 3U, /*!< ENET TIMER Clock from External Clock 1.*/
713 kCLOCK_EnetTimerRootmuxExtClk2 = 4U, /*!< ENET TIMER Clock External Clock 2.*/
714 kCLOCK_EnetTimerRootmuxExtClk3 = 5U, /*!< ENET TIMER Clock from External Clock 3.*/
715 kCLOCK_EnetTimerRootmuxExtClk4 = 6U, /*!< ENET TIMER Clock from External Clock 4.*/
716 kCLOCK_EnetTimerRootmuxVideoPll1 = 7U, /*!< ENET TIMER Clock from VIDEO PLL1.*/
717 } clock_rootmux_enet_timer_clk_sel_t;
718
719 /*! @brief Root clock select enumeration for ENET PHY Clcok. */
720 typedef enum _clock_rootmux_enet_phy_clk_sel
721 {
722 kCLOCK_EnetPhyRootmuxOsc24M = 0U, /*!< ENET PHY Clock from OSC 24M.*/
723 kCLOCK_EnetPhyRootmuxSysPll2Div20 = 1U, /*!< ENET PHY Clock from SYSTEM PLL2 divided by 20.*/
724 kCLOCK_EnetPhyRootmuxSysPll2Div8 = 2U, /*!< ENET PHY Clock from SYSTEM PLL2 divided by 8.*/
725 kCLOCK_EnetPhyRootmuxSysPll2Div5 = 3U, /*!< ENET PHY Clock from SYSTEM PLL2 divided by 5.*/
726 kCLOCK_EnetPhyRootmuxSysPll2Div2 = 4U, /*!< ENET PHY Clock from SYSTEM PLL2 divided by 2.*/
727 kCLOCK_EnetPhyRootmuxAudioPll1 = 5U, /*!< ENET PHY Clock from AUDIO PLL1.*/
728 kCLOCK_EnetPhyRootmuxVideoPll1 = 6U, /*!< ENET PHY Clock from VIDEO PLL1.*/
729 kCLOCK_EnetPhyRootmuxAudioPll2 = 7U, /*!< ENET PHY Clock from AUDIO PLL2.*/
730 } clock_rootmux_enet_phy_clk_sel_t;
731
732 /*! @brief Root clock select enumeration for I2C peripheral. */
733 typedef enum _clock_rootmux_i2c_clk_sel
734 {
735 kCLOCK_I2cRootmuxOsc24M = 0U, /*!< I2C Clock from OSC 24M.*/
736 kCLOCK_I2cRootmuxSysPll1Div5 = 1U, /*!< I2C Clock from SYSTEM PLL1 divided by 5.*/
737 kCLOCK_I2cRootmuxSysPll2Div20 = 2U, /*!< I2C Clock from SYSTEM PLL2 divided by 20.*/
738 kCLOCK_I2cRootmuxSysPll3 = 3U, /*!< I2C Clock from SYSTEM PLL3 .*/
739 kCLOCK_I2cRootmuxAudioPll1 = 4U, /*!< I2C Clock from AUDIO PLL1.*/
740 kCLOCK_I2cRootmuxVideoPll1 = 5U, /*!< I2C Clock from VIDEO PLL1.*/
741 kCLOCK_I2cRootmuxAudioPll2 = 6U, /*!< I2C Clock from AUDIO PLL2.*/
742 kCLOCK_I2cRootmuxSysPll1Div6 = 7U, /*!< I2C Clock from SYSTEM PLL1 divided by 6.*/
743 } clock_rootmux_i2c_clk_sel_t;
744
745 /*! @brief Root clock select enumeration for UART peripheral. */
746 typedef enum _clock_rootmux_uart_clk_sel
747 {
748 kCLOCK_UartRootmuxOsc24M = 0U, /*!< UART Clock from OSC 24M.*/
749 kCLOCK_UartRootmuxSysPll1Div10 = 1U, /*!< UART Clock from SYSTEM PLL1 divided by 10.*/
750 kCLOCK_UartRootmuxSysPll2Div5 = 2U, /*!< UART Clock from SYSTEM PLL2 divided by 5.*/
751 kCLOCK_UartRootmuxSysPll2Div10 = 3U, /*!< UART Clock from SYSTEM PLL2 divided by 10.*/
752 kCLOCK_UartRootmuxSysPll3 = 4U, /*!< UART Clock from SYSTEM PLL3.*/
753 kCLOCK_UartRootmuxExtClk2 = 5U, /*!< UART Clock from External Clock 2.*/
754 kCLOCK_UartRootmuxExtClk34 = 6U, /*!< UART Clock from External Clock 3, External Clock 4.*/
755 kCLOCK_UartRootmuxAudioPll2 = 7U, /*!< UART Clock from Audio PLL2.*/
756 } clock_rootmux_uart_clk_sel_t;
757
758 /*! @brief Root clock select enumeration for GPT peripheral. */
759 typedef enum _clock_rootmux_gpt
760 {
761 kCLOCK_GptRootmuxOsc24M = 0U, /*!< GPT Clock from OSC 24M.*/
762 kCLOCK_GptRootmuxSystemPll2Div10 = 1U, /*!< GPT Clock from SYSTEM PLL2 divided by 10.*/
763 kCLOCK_GptRootmuxSysPll1Div2 = 2U, /*!< GPT Clock from SYSTEM PLL1 divided by 2.*/
764 kCLOCK_GptRootmuxSysPll1Div20 = 3U, /*!< GPT Clock from SYSTEM PLL1 divided by 20.*/
765 kCLOCK_GptRootmuxVideoPll1 = 4U, /*!< GPT Clock from VIDEO PLL1.*/
766 kCLOCK_GptRootmuxSystemPll1Div10 = 5U, /*!< GPT Clock from SYSTEM PLL1 divided by 10.*/
767 kCLOCK_GptRootmuxAudioPll1 = 6U, /*!< GPT Clock from AUDIO PLL1.*/
768 kCLOCK_GptRootmuxExtClk123 = 7U, /*!< GPT Clock from External Clock1, External Clock2, External Clock3.*/
769 } clock_rootmux_gpt_t;
770
771 /*! @brief Root clock select enumeration for WDOG peripheral. */
772 typedef enum _clock_rootmux_wdog_clk_sel
773 {
774 kCLOCK_WdogRootmuxOsc24M = 0U, /*!< WDOG Clock from OSC 24M.*/
775 kCLOCK_WdogRootmuxSysPll1Div6 = 1U, /*!< WDOG Clock from SYSTEM PLL1 divided by 6.*/
776 kCLOCK_WdogRootmuxSysPll1Div5 = 2U, /*!< WDOG Clock from SYSTEM PLL1 divided by 5.*/
777 kCLOCK_WdogRootmuxVpuPll = 3U, /*!< WDOG Clock from VPU DLL.*/
778 kCLOCK_WdogRootmuxSystemPll2Div8 = 4U, /*!< WDOG Clock from SYSTEM PLL2 divided by 8.*/
779 kCLOCK_WdogRootmuxSystemPll3 = 5U, /*!< WDOG Clock from SYSTEM PLL3.*/
780 kCLOCK_WdogRootmuxSystemPll1Div10 = 6U, /*!< WDOG Clock from SYSTEM PLL1 divided by 10.*/
781 kCLOCK_WdogRootmuxSystemPll2Div6 = 7U, /*!< WDOG Clock from SYSTEM PLL2 divided by 6.*/
782 } clock_rootmux_wdog_clk_sel_t;
783
784 /*! @brief Root clock select enumeration for PWM peripheral. */
785 typedef enum _clock_rootmux_pwm_clk_sel
786 {
787 kCLOCK_PwmRootmuxOsc24M = 0U, /*!< PWM Clock from OSC 24M.*/
788 kCLOCK_PwmRootmuxSysPll2Div10 = 1U, /*!< PWM Clock from SYSTEM PLL2 divided by 10.*/
789 kCLOCK_PwmRootmuxSysPll1Div5 = 2U, /*!< PWM Clock from SYSTEM PLL1 divided by 5.*/
790 kCLOCK_PwmRootmuxSysPll1Div20 = 3U, /*!< PWM Clock from SYSTEM PLL1 divided by 20.*/
791 kCLOCK_PwmRootmuxSystemPll3 = 4U, /*!< PWM Clock from SYSTEM PLL3.*/
792 kCLOCK_PwmRootmuxExtClk12 = 5U, /*!< PWM Clock from External Clock1, External Clock2.*/
793 kCLOCK_PwmRootmuxSystemPll1Div10 = 6U, /*!< PWM Clock from SYSTEM PLL1 divided by 10.*/
794 kCLOCK_PwmRootmuxVideoPll1 = 7U, /*!< PWM Clock from VIDEO PLL1.*/
795 } clock_rootmux_Pwm_clk_sel_t;
796
797 /*! @brief Root clock select enumeration for SAI peripheral. */
798 typedef enum _clock_rootmux_sai_clk_sel
799 {
800 kCLOCK_SaiRootmuxOsc24M = 0U, /*!< SAI Clock from OSC 24M.*/
801 kCLOCK_SaiRootmuxAudioPll1 = 1U, /*!< SAI Clock from AUDIO PLL1.*/
802 kCLOCK_SaiRootmuxAudioPll2 = 2U, /*!< SAI Clock from AUDIO PLL2.*/
803 kCLOCK_SaiRootmuxVideoPll1 = 3U, /*!< SAI Clock from VIDEO PLL1.*/
804 kCLOCK_SaiRootmuxSysPll1Div6 = 4U, /*!< SAI Clock from SYSTEM PLL1 divided by 6.*/
805 kCLOCK_SaiRootmuxOsc26m = 5U, /*!< SAI Clock from OSC HDMI 26M.*/
806 kCLOCK_SaiRootmuxExtClk1 = 6U, /*!< SAI Clock from External Clock1, External Clock2, External Clock3.*/
807 kCLOCK_SaiRootmuxExtClk2 = 7U, /*!< SAI Clock from External Clock2, External Clock3, External Clock4.*/
808 } clock_rootmux_sai_clk_sel_t;
809
810 /*! @brief Root clock select enumeration for PDM peripheral. */
811 typedef enum _clock_rootmux_pdm_clk_sel
812 {
813 kCLOCK_PdmRootmuxOsc24M = 0U, /*!< GPT Clock from OSC 24M.*/
814 kCLOCK_PdmRootmuxSystemPll2 = 1U, /*!< GPT Clock from SYSTEM PLL2 divided by 10.*/
815 kCLOCK_PdmRootmuxAudioPll1 = 2U, /*!< GPT Clock from SYSTEM PLL1 divided by 2.*/
816 kCLOCK_PdmRootmuxSysPll1 = 3U, /*!< GPT Clock from SYSTEM PLL1 divided by 20.*/
817 kCLOCK_PdmRootmuxSysPll2 = 4U, /*!< GPT Clock from VIDEO PLL1.*/
818 kCLOCK_PdmRootmuxSysPll3 = 5U, /*!< GPT Clock from SYSTEM PLL1 divided by 10.*/
819 kCLOCK_PdmRootmuxExtClk3 = 6U, /*!< GPT Clock from AUDIO PLL1.*/
820 kCLOCK_PdmRootmuxAudioPll2 = 7U, /*!< GPT Clock from External Clock1, External Clock2, External Clock3.*/
821 } clock_rootmux_pdm_clk_sel_t;
822
823 /*! @brief Root clock select enumeration for NOC CLK. */
824 typedef enum _clock_rootmux_noc_clk_sel
825 {
826 kCLOCK_NocRootmuxOsc24M = 0U, /*!< NOC Clock from OSC 24M.*/
827 kCLOCK_NocRootmuxSysPll1 = 1U, /*!< NOC Clock from SYSTEM PLL1.*/
828 kCLOCK_NocRootmuxSysPll3 = 2U, /*!< NOC Clock from SYSTEM PLL3.*/
829 kCLOCK_NocRootmuxSysPll2 = 3U, /*!< NOC Clock from SYSTEM PLL2.*/
830 kCLOCK_NocRootmuxSysPll2Div2 = 4U, /*!< NOC Clock from SYSTEM PLL2 divided by 2.*/
831 kCLOCK_NocRootmuxAudioPll1 = 5U, /*!< NOC Clock from AUDIO PLL1.*/
832 kCLOCK_NocRootmuxVideoPll1 = 6U, /*!< NOC Clock from VIDEO PLL1.*/
833 kCLOCK_NocRootmuxAudioPll2 = 7U, /*!< NOC Clock from AUDIO PLL2.*/
834
835 } clock_rootmux_noc_clk_sel_t;
836
837 /*! @brief CCM PLL gate control. */
838 typedef enum _clock_pll_gate
839 {
840 kCLOCK_ArmPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[12].PLL_CTRL), /*!< ARM PLL Gate.*/
841
842 kCLOCK_GpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[13].PLL_CTRL), /*!< GPU PLL Gate.*/
843 kCLOCK_VpuPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[14].PLL_CTRL), /*!< VPU PLL Gate.*/
844 kCLOCK_DramPllGate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[15].PLL_CTRL), /*!< DRAM PLL1 Gate.*/
845
846 kCLOCK_SysPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[16].PLL_CTRL), /*!< SYSTEM PLL1 Gate.*/
847 kCLOCK_SysPll1Div2Gate =
848 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[17].PLL_CTRL), /*!< SYSTEM PLL1 Div2 Gate.*/
849 kCLOCK_SysPll1Div3Gate =
850 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[18].PLL_CTRL), /*!< SYSTEM PLL1 Div3 Gate.*/
851 kCLOCK_SysPll1Div4Gate =
852 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[19].PLL_CTRL), /*!< SYSTEM PLL1 Div4 Gate.*/
853 kCLOCK_SysPll1Div5Gate =
854 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[20].PLL_CTRL), /*!< SYSTEM PLL1 Div5 Gate.*/
855 kCLOCK_SysPll1Div6Gate =
856 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[21].PLL_CTRL), /*!< SYSTEM PLL1 Div6 Gate.*/
857 kCLOCK_SysPll1Div8Gate =
858 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[22].PLL_CTRL), /*!< SYSTEM PLL1 Div8 Gate.*/
859 kCLOCK_SysPll1Div10Gate =
860 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[23].PLL_CTRL), /*!< SYSTEM PLL1 Div10 Gate.*/
861 kCLOCK_SysPll1Div20Gate =
862 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[24].PLL_CTRL), /*!< SYSTEM PLL1 Div20 Gate.*/
863
864 kCLOCK_SysPll2Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[25].PLL_CTRL), /*!< SYSTEM PLL2 Gate.*/
865 kCLOCK_SysPll2Div2Gate =
866 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[26].PLL_CTRL), /*!< SYSTEM PLL2 Div2 Gate.*/
867 kCLOCK_SysPll2Div3Gate =
868 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[27].PLL_CTRL), /*!< SYSTEM PLL2 Div3 Gate.*/
869 kCLOCK_SysPll2Div4Gate =
870 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[28].PLL_CTRL), /*!< SYSTEM PLL2 Div4 Gate.*/
871 kCLOCK_SysPll2Div5Gate =
872 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[29].PLL_CTRL), /*!< SYSTEM PLL2 Div5 Gate.*/
873 kCLOCK_SysPll2Div6Gate =
874 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[30].PLL_CTRL), /*!< SYSTEM PLL2 Div6 Gate.*/
875 kCLOCK_SysPll2Div8Gate =
876 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[31].PLL_CTRL), /*!< SYSTEM PLL2 Div8 Gate.*/
877 kCLOCK_SysPll2Div10Gate =
878 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[32].PLL_CTRL), /*!< SYSTEM PLL2 Div10 Gate.*/
879 kCLOCK_SysPll2Div20Gate =
880 (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[33].PLL_CTRL), /*!< SYSTEM PLL2 Div20 Gate.*/
881
882 kCLOCK_SysPll3Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[34].PLL_CTRL), /*!< SYSTEM PLL3 Gate.*/
883
884 kCLOCK_AudioPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[35].PLL_CTRL), /*!< AUDIO PLL1 Gate.*/
885 kCLOCK_AudioPll2Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[36].PLL_CTRL), /*!< AUDIO PLL2 Gate.*/
886 kCLOCK_VideoPll1Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[37].PLL_CTRL), /*!< VIDEO PLL1 Gate.*/
887 kCLOCK_VideoPll2Gate = (uintptr_t)CCM_BASE + offsetof(CCM_Type, PLL_CTRL[38].PLL_CTRL), /*!< VIDEO PLL2 Gate.*/
888 } clock_pll_gate_t;
889
890 /*! @brief CCM gate control value. */
891 typedef enum _clock_gate_value
892 {
893 kCLOCK_ClockNotNeeded = 0x0U, /*!< Clock always disabled.*/
894 kCLOCK_ClockNeededRun = 0x1111U, /*!< Clock enabled when CPU is running.*/
895 kCLOCK_ClockNeededRunWait = 0x2222U, /*!< Clock enabled when CPU is running or in WAIT mode.*/
896 kCLOCK_ClockNeededAll = 0x3333U, /*!< Clock always enabled.*/
897 } clock_gate_value_t;
898
899 /*!
900 * @brief PLL control names for PLL bypass.
901 *
902 * These constants define the PLL control names for PLL bypass.\n
903 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
904 * - 16:20: bypass bit shift.
905 */
906 typedef enum _clock_pll_bypass_ctrl
907 {
908 kCLOCK_AudioPll1BypassCtrl =
909 CCM_ANALOG_TUPLE(AUDIO_PLL1_GEN_CTRL_OFFSET,
910 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL1 bypass Control.*/
911
912 kCLOCK_AudioPll2BypassCtrl =
913 CCM_ANALOG_TUPLE(AUDIO_PLL2_GEN_CTRL_OFFSET,
914 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL2 bypass Control.*/
915
916 kCLOCK_VideoPll1BypassCtrl =
917 CCM_ANALOG_TUPLE(VIDEO_PLL1_GEN_CTRL_OFFSET,
918 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Video Pll1 bypass Control.*/
919
920 kCLOCK_DramPllInternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
921 DRAM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM DRAM PLL bypass Control.*/
922
923 kCLOCK_GpuPLLPwrBypassCtrl = CCM_ANALOG_TUPLE(
924 GPU_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Gpu PLL bypass Control.*/
925
926 kCLOCK_VpuPllPwrBypassCtrl = CCM_ANALOG_TUPLE(
927 VPU_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Vpu PLL bypass Control.*/
928
929 kCLOCK_ArmPllPwrBypassCtrl = CCM_ANALOG_TUPLE(
930 ARM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Arm PLL bypass Control.*/
931
932 kCLOCK_SysPll1InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
933 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM System PLL1 bypass Control.*/
934
935 kCLOCK_SysPll2InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
936 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM System PLL2 bypass Control.*/
937
938 kCLOCK_SysPll3InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
939 SYS_PLL3_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM System PLL3 bypass Control.*/
940 } clock_pll_bypass_ctrl_t;
941
942 /*!
943 * @brief PLL clock names for clock enable/disable settings.
944 *
945 * These constants define the PLL clock names for PLL clock enable/disable operations.\n
946 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
947 * - 16:20: Clock enable bit shift.
948 */
949 typedef enum _ccm_analog_pll_clke
950 {
951 kCLOCK_AudioPll1Clke = CCM_ANALOG_TUPLE(AUDIO_PLL1_GEN_CTRL_OFFSET,
952 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Audio pll1 clke */
953 kCLOCK_AudioPll2Clke = CCM_ANALOG_TUPLE(AUDIO_PLL2_GEN_CTRL_OFFSET,
954 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Audio pll2 clke */
955 kCLOCK_VideoPll1Clke = CCM_ANALOG_TUPLE(VIDEO_PLL1_GEN_CTRL_OFFSET,
956 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Video pll1 clke */
957 kCLOCK_DramPllClke =
958 CCM_ANALOG_TUPLE(DRAM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Dram pll clke */
959
960 kCLOCK_GpuPllClke =
961 CCM_ANALOG_TUPLE(GPU_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Gpu pll clke */
962 kCLOCK_VpuPllClke =
963 CCM_ANALOG_TUPLE(VPU_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Vpu pll clke */
964 kCLOCK_ArmPllClke =
965 CCM_ANALOG_TUPLE(ARM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Arm pll clke */
966
967 kCLOCK_SystemPll1Clke = CCM_ANALOG_TUPLE(SYS_PLL1_GEN_CTRL_OFFSET,
968 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT), /*!< System pll1 clke */
969 kCLOCK_SystemPll1Div2Clke = CCM_ANALOG_TUPLE(
970 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT), /*!< System pll1 Div2 clke */
971 kCLOCK_SystemPll1Div3Clke = CCM_ANALOG_TUPLE(
972 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT), /*!< System pll1 Div3 clke */
973 kCLOCK_SystemPll1Div4Clke = CCM_ANALOG_TUPLE(
974 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT), /*!< System pll1 Div4 clke */
975 kCLOCK_SystemPll1Div5Clke = CCM_ANALOG_TUPLE(
976 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT), /*!< System pll1 Div5 clke */
977 kCLOCK_SystemPll1Div6Clke = CCM_ANALOG_TUPLE(
978 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT), /*!< System pll1 Div6 clke */
979 kCLOCK_SystemPll1Div8Clke = CCM_ANALOG_TUPLE(
980 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT), /*!< System pll1 Div8 clke */
981 kCLOCK_SystemPll1Div10Clke = CCM_ANALOG_TUPLE(
982 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT), /*!< System pll1 Div10 clke */
983 kCLOCK_SystemPll1Div20Clke = CCM_ANALOG_TUPLE(
984 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT), /*!< System pll1 Div20 clke */
985
986 kCLOCK_SystemPll2Clke = CCM_ANALOG_TUPLE(SYS_PLL2_GEN_CTRL_OFFSET,
987 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT), /*!< System pll2 clke */
988 kCLOCK_SystemPll2Div2Clke = CCM_ANALOG_TUPLE(
989 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT), /*!< System pll2 Div2 clke */
990 kCLOCK_SystemPll2Div3Clke = CCM_ANALOG_TUPLE(
991 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT), /*!< System pll2 Div3 clke */
992 kCLOCK_SystemPll2Div4Clke = CCM_ANALOG_TUPLE(
993 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT), /*!< System pll2 Div4 clke */
994 kCLOCK_SystemPll2Div5Clke = CCM_ANALOG_TUPLE(
995 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT), /*!< System pll2 Div5 clke */
996 kCLOCK_SystemPll2Div6Clke = CCM_ANALOG_TUPLE(
997 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT), /*!< System pll2 Div6 clke */
998 kCLOCK_SystemPll2Div8Clke = CCM_ANALOG_TUPLE(
999 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT), /*!< System pll2 Div8 clke */
1000 kCLOCK_SystemPll2Div10Clke = CCM_ANALOG_TUPLE(
1001 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT), /*!< System pll2 Div10 clke */
1002 kCLOCK_SystemPll2Div20Clke = CCM_ANALOG_TUPLE(
1003 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT), /*!< System pll2 Div20 clke */
1004
1005 kCLOCK_SystemPll3Clke = CCM_ANALOG_TUPLE(SYS_PLL3_GEN_CTRL_OFFSET,
1006 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT), /*!< System pll3 clke */
1007 } clock_pll_clke_t;
1008
1009 /*!
1010 * @brief ANALOG Power down override control.
1011 */
1012 typedef enum _clock_pll_ctrl
1013 {
1014 /* Fractional PLL frequency */
1015 kCLOCK_AudioPll1Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT),
1016 kCLOCK_AudioPll2Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT),
1017 kCLOCK_VideoPll1Ctrl = CCM_ANALOG_TUPLE(VIDEO_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT),
1018 kCLOCK_DramPllCtrl = CCM_ANALOG_TUPLE(DRAM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT),
1019 /* Integer PLL frequency */
1020 kCLOCK_GpuPllCtrl = CCM_ANALOG_TUPLE(GPU_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT),
1021 kCLOCK_VpuPllCtrl = CCM_ANALOG_TUPLE(VPU_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_VPU_PLL_GEN_CTRL_PLL_RST_SHIFT),
1022 kCLOCK_ArmPllCtrl = CCM_ANALOG_TUPLE(ARM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT),
1023 kCLOCK_SystemPll1Ctrl = CCM_ANALOG_TUPLE(SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT),
1024 kCLOCK_SystemPll2Ctrl = CCM_ANALOG_TUPLE(SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT),
1025 kCLOCK_SystemPll3Ctrl = CCM_ANALOG_TUPLE(SYS_PLL3_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT),
1026 } clock_pll_ctrl_t;
1027
1028 /*! @brief PLL reference clock select. */
1029 enum
1030 {
1031 kANALOG_PllRefOsc24M = 0U, /*!< reference OSC 24M */
1032 kANALOG_PllPadClk = 1U, /*!< reference PAD CLK */
1033 };
1034
1035 /*!
1036 * @brief Fractional-N PLL configuration.
1037 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
1038 * value
1039 */
1040 typedef struct _ccm_analog_frac_pll_config
1041 {
1042 uint8_t refSel; /*!< pll reference clock sel */
1043
1044 uint32_t mainDiv; /*!< Value of the 10-bit programmable main-divider, range must be 64~1023 */
1045
1046 uint32_t dsm; /*!< Value of 16-bit DSM */
1047
1048 uint8_t preDiv; /*!< Value of the 6-bit programmable pre-divider, range must be 1~63 */
1049
1050 uint8_t postDiv; /*!< Value of the 3-bit programmable Scaler, range must be 0~6 */
1051 } ccm_analog_frac_pll_config_t;
1052
1053 /*!
1054 * @brief Integer PLL configuration.
1055 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
1056 * value
1057 */
1058 typedef struct _ccm_analog_integer_pll_config
1059 {
1060 uint8_t refSel; /*!< pll reference clock sel */
1061
1062 uint32_t mainDiv; /*!< Value of the 10-bit programmable main-divider, range must be 64~1023 */
1063
1064 uint8_t preDiv; /*!< Value of the 6-bit programmable pre-divider, range must be 1~63 */
1065
1066 uint8_t postDiv; /*!< Value of the 3-bit programmable Scaler, range must be 0~6 */
1067
1068 } ccm_analog_integer_pll_config_t;
1069
1070 /*******************************************************************************
1071 * API
1072 ******************************************************************************/
1073
1074 #if defined(__cplusplus)
1075 extern "C" {
1076 #endif
1077
1078 /*!
1079 * @name CCM Root Clock Setting
1080 * @{
1081 */
1082
1083 /*!
1084 * @brief Set clock root mux.
1085 * User maybe need to set more than one mux ROOT according to the clock tree
1086 * description in the reference manual.
1087 *
1088 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
1089 * @param mux Root mux value (see _ccm_rootmux_xxx enumeration).
1090 */
CLOCK_SetRootMux(clock_root_control_t rootClk,uint32_t mux)1091 static inline void CLOCK_SetRootMux(clock_root_control_t rootClk, uint32_t mux)
1092 {
1093 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux);
1094 }
1095
1096 /*!
1097 * @brief Get clock root mux.
1098 * In order to get the clock source of root, user maybe need to get more than one
1099 * ROOT's mux value to obtain the final clock source of root.
1100 *
1101 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
1102 * @return Root mux value (see _ccm_rootmux_xxx enumeration).
1103 */
CLOCK_GetRootMux(clock_root_control_t rootClk)1104 static inline uint32_t CLOCK_GetRootMux(clock_root_control_t rootClk)
1105 {
1106 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT;
1107 }
1108
1109 /*!
1110 * @brief Enable clock root
1111 *
1112 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration)
1113 */
CLOCK_EnableRoot(clock_root_control_t rootClk)1114 static inline void CLOCK_EnableRoot(clock_root_control_t rootClk)
1115 {
1116 CCM_REG_SET(rootClk) = CCM_TARGET_ROOT_SET_ENABLE_MASK;
1117 }
1118
1119 /*!
1120 * @brief Disable clock root
1121 *
1122 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
1123 */
CLOCK_DisableRoot(clock_root_control_t rootClk)1124 static inline void CLOCK_DisableRoot(clock_root_control_t rootClk)
1125 {
1126 CCM_REG_CLR(rootClk) = CCM_TARGET_ROOT_CLR_ENABLE_MASK;
1127 }
1128
1129 /*!
1130 * @brief Check whether clock root is enabled
1131 *
1132 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
1133 * @return CCM root enabled or not.
1134 * - true: Clock root is enabled.
1135 * - false: Clock root is disabled.
1136 */
CLOCK_IsRootEnabled(clock_root_control_t rootClk)1137 static inline bool CLOCK_IsRootEnabled(clock_root_control_t rootClk)
1138 {
1139 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK);
1140 }
1141
1142 /*!
1143 * @brief Update clock root in one step, for dynamical clock switching
1144 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
1145 *
1146 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
1147 * @param mux Root mux value (see _ccm_rootmux_xxx enumeration)
1148 * @param pre Pre divider value (0-7, divider=n+1)
1149 * @param post Post divider value (0-63, divider=n+1)
1150 */
1151 void CLOCK_UpdateRoot(clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post);
1152
1153 /*!
1154 * @brief Set root clock divider
1155 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
1156 *
1157 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
1158 * @param pre Pre divider value (1-8)
1159 * @param post Post divider value (1-64)
1160 */
1161 void CLOCK_SetRootDivider(clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post);
1162
1163 /*!
1164 * @brief Get clock root PRE_PODF.
1165 * In order to get the clock source of root, user maybe need to get more than one
1166 * ROOT's mux value to obtain the final clock source of root.
1167 *
1168 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
1169 * @return Root Pre divider value.
1170 */
CLOCK_GetRootPreDivider(clock_root_control_t rootClk)1171 static inline uint32_t CLOCK_GetRootPreDivider(clock_root_control_t rootClk)
1172 {
1173 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U;
1174 }
1175
1176 /*!
1177 * @brief Get clock root POST_PODF.
1178 * In order to get the clock source of root, user maybe need to get more than one
1179 * ROOT's mux value to obtain the final clock source of root.
1180 *
1181 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
1182 * @return Root Post divider value.
1183 */
CLOCK_GetRootPostDivider(clock_root_control_t rootClk)1184 static inline uint32_t CLOCK_GetRootPostDivider(clock_root_control_t rootClk)
1185 {
1186 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + 1U;
1187 }
1188
1189 /*!
1190 * @name CCM Gate Control
1191 * @{
1192 */
1193
1194 /*!
1195 * @brief Set PLL or CCGR gate control
1196 *
1197 * @param ccmGate Gate control (see @ref clock_pll_gate_t and @ref clock_ip_name_t enumeration)
1198 * @param control Gate control value (see @ref clock_gate_value_t)
1199 */
CLOCK_ControlGate(uintptr_t ccmGate,clock_gate_value_t control)1200 static inline void CLOCK_ControlGate(uintptr_t ccmGate, clock_gate_value_t control)
1201 {
1202 CCM_REG(ccmGate) = (uint32_t)control;
1203 }
1204
1205 /*!
1206 * @brief Enable CCGR clock gate and root clock gate for each module
1207 * User should set specific gate for each module according to the description
1208 * of the table of system clocks, gating and override in CCM chapter of
1209 * reference manual. Take care of that one module may need to set more than
1210 * one clock gate.
1211 *
1212 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
1213 */
1214 void CLOCK_EnableClock(clock_ip_name_t ccmGate);
1215
1216 /*!
1217 * @brief Disable CCGR clock gate for the each module
1218 * User should set specific gate for each module according to the description
1219 * of the table of system clocks, gating and override in CCM chapter of
1220 * reference manual. Take care of that one module may need to set more than
1221 * one clock gate.
1222 *
1223 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
1224 */
1225 void CLOCK_DisableClock(clock_ip_name_t ccmGate);
1226
1227 /*!
1228 * @name CCM Analog PLL Operatoin Functions
1229 * @{
1230 */
1231
1232 /*!
1233 * @brief Power up PLL
1234 *
1235 * @param base CCM_ANALOG base pointer.
1236 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
1237 */
CLOCK_PowerUpPll(CCM_ANALOG_Type * base,clock_pll_ctrl_t pllControl)1238 static inline void CLOCK_PowerUpPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
1239 {
1240 CCM_ANALOG_TUPLE_REG(base, pllControl) |= (1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
1241 }
1242
1243 /*!
1244 * @brief Power down PLL
1245 *
1246 * @param base CCM_ANALOG base pointer.
1247 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
1248 */
CLOCK_PowerDownPll(CCM_ANALOG_Type * base,clock_pll_ctrl_t pllControl)1249 static inline void CLOCK_PowerDownPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
1250 {
1251 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
1252 }
1253
1254 /*!
1255 * @brief PLL bypass setting
1256 *
1257 * @param base CCM_ANALOG base pointer.
1258 * @param pllControl PLL control name (see ccm_analog_pll_control_t enumeration)
1259 * @param bypass Bypass the PLL.
1260 * - true: Bypass the PLL.
1261 * - false: Do not bypass the PLL.
1262 */
CLOCK_SetPllBypass(CCM_ANALOG_Type * base,clock_pll_bypass_ctrl_t pllControl,bool bypass)1263 static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl, bool bypass)
1264 {
1265 if (bypass)
1266 {
1267 CCM_ANALOG_TUPLE_REG(base, pllControl) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl);
1268 }
1269 else
1270 {
1271 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
1272 }
1273 }
1274
1275 /*!
1276 * @brief Check if PLL is bypassed
1277 *
1278 * @param base CCM_ANALOG base pointer.
1279 * @param pllControl PLL control name (see ccm_analog_pll_control_t enumeration)
1280 * @return PLL bypass status.
1281 * - true: The PLL is bypassed.
1282 * - false: The PLL is not bypassed.
1283 */
CLOCK_IsPllBypassed(CCM_ANALOG_Type * base,clock_pll_bypass_ctrl_t pllControl)1284 static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl)
1285 {
1286 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl)));
1287 }
1288
1289 /*!
1290 * @brief Check if PLL clock is locked
1291 *
1292 * @param base CCM_ANALOG base pointer.
1293 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
1294 * @return PLL lock status.
1295 * - true: The PLL clock is locked.
1296 * - false: The PLL clock is not locked.
1297 */
CLOCK_IsPllLocked(CCM_ANALOG_Type * base,clock_pll_ctrl_t pllControl)1298 static inline bool CLOCK_IsPllLocked(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
1299 {
1300 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK);
1301 }
1302
1303 /*!
1304 * @brief Enable PLL clock
1305 *
1306 * @param base CCM_ANALOG base pointer.
1307 * @param pllClock PLL clock name (see ccm_analog_pll_clock_t enumeration)
1308 */
CLOCK_EnableAnalogClock(CCM_ANALOG_Type * base,clock_pll_clke_t pllClock)1309 static inline void CLOCK_EnableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
1310 {
1311 CCM_ANALOG_TUPLE_REG(base, pllClock) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock);
1312 }
1313
1314 /*!
1315 * @brief Disable PLL clock
1316 *
1317 * @param base CCM_ANALOG base pointer.
1318 * @param pllClock PLL clock name (see ccm_analog_pll_clock_t enumeration)
1319 */
CLOCK_DisableAnalogClock(CCM_ANALOG_Type * base,clock_pll_clke_t pllClock)1320 static inline void CLOCK_DisableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
1321 {
1322 CCM_ANALOG_TUPLE_REG(base, pllClock) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock));
1323 }
1324
1325 /*!
1326 * @brief Override PLL clock output enable
1327 *
1328 * @param base CCM_ANALOG base pointer.
1329 * @param ovClock PLL clock name (see @ref clock_pll_clke_t enumeration)
1330 * @param override Override the PLL.
1331 * - true: Override the PLL clke, CCM will handle it.
1332 * - false: Do not override the PLL clke.
1333 */
CLOCK_OverridePllClke(CCM_ANALOG_Type * base,clock_pll_clke_t ovClock,bool override)1334 static inline void CLOCK_OverridePllClke(CCM_ANALOG_Type *base, clock_pll_clke_t ovClock, bool override)
1335 {
1336 if (override)
1337 {
1338 CCM_ANALOG_TUPLE_REG(base, ovClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL);
1339 }
1340 else
1341 {
1342 CCM_ANALOG_TUPLE_REG(base, ovClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL));
1343 }
1344 }
1345
1346 /*!
1347 * @brief Override PLL power down
1348 *
1349 * @param base CCM_ANALOG base pointer.
1350 * @param pdClock PLL clock name (see @ref clock_pll_ctrl_t enumeration)
1351 * @param override Override the PLL.
1352 * - true: Override the PLL clke, CCM will handle it.
1353 * - false: Do not override the PLL clke.
1354 */
CLOCK_OverridePllPd(CCM_ANALOG_Type * base,clock_pll_ctrl_t pdClock,bool override)1355 static inline void CLOCK_OverridePllPd(CCM_ANALOG_Type *base, clock_pll_ctrl_t pdClock, bool override)
1356 {
1357 if (override)
1358 {
1359 CCM_ANALOG_TUPLE_REG(base, pdClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL);
1360 }
1361 else
1362 {
1363 CCM_ANALOG_TUPLE_REG(base, pdClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL));
1364 }
1365 }
1366
1367 /*!
1368 * @brief Initializes the ANALOG ARM PLL.
1369 *
1370 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1371 *
1372 * @note This function can't detect whether the Arm PLL has been enabled and
1373 * used by some IPs.
1374 */
1375 void CLOCK_InitArmPll(const ccm_analog_integer_pll_config_t *config);
1376
1377 /*!
1378 * @brief De-initialize the ARM PLL.
1379 */
1380 void CLOCK_DeinitArmPll(void);
1381
1382 /*!
1383 * @brief Initializes the ANALOG SYS PLL1.
1384 *
1385 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1386 *
1387 * @note This function can't detect whether the SYS PLL has been enabled and
1388 * used by some IPs.
1389 */
1390 void CLOCK_InitSysPll1(const ccm_analog_integer_pll_config_t *config);
1391
1392 /*!
1393 * @brief De-initialize the System PLL1.
1394 */
1395 void CLOCK_DeinitSysPll1(void);
1396
1397 /*!
1398 * @brief Initializes the ANALOG SYS PLL2.
1399 *
1400 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1401 *
1402 * @note This function can't detect whether the SYS PLL has been enabled and
1403 * used by some IPs.
1404 */
1405 void CLOCK_InitSysPll2(const ccm_analog_integer_pll_config_t *config);
1406
1407 /*!
1408 * @brief De-initialize the System PLL2.
1409 */
1410 void CLOCK_DeinitSysPll2(void);
1411
1412 /*!
1413 * @brief Initializes the ANALOG SYS PLL3.
1414 *
1415 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1416 *
1417 * @note This function can't detect whether the SYS PLL has been enabled and
1418 * used by some IPs.
1419 */
1420 void CLOCK_InitSysPll3(const ccm_analog_integer_pll_config_t *config);
1421
1422 /*!
1423 * @brief De-initialize the System PLL3.
1424 */
1425 void CLOCK_DeinitSysPll3(void);
1426
1427 /*!
1428 * @brief Initializes the ANALOG AUDIO PLL1.
1429 *
1430 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1431 *
1432 * @note This function can't detect whether the AUDIO PLL has been enabled and
1433 * used by some IPs.
1434 */
1435 void CLOCK_InitAudioPll1(const ccm_analog_frac_pll_config_t *config);
1436
1437 /*!
1438 * @brief De-initialize the Audio PLL1.
1439 */
1440 void CLOCK_DeinitAudioPll1(void);
1441
1442 /*!
1443 * @brief Initializes the ANALOG AUDIO PLL2.
1444 *
1445 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1446 *
1447 * @note This function can't detect whether the AUDIO PLL has been enabled and
1448 * used by some IPs.
1449 */
1450 void CLOCK_InitAudioPll2(const ccm_analog_frac_pll_config_t *config);
1451
1452 /*!
1453 * @brief De-initialize the Audio PLL2.
1454 */
1455 void CLOCK_DeinitAudioPll2(void);
1456
1457 /*!
1458 * @brief Initializes the ANALOG VIDEO PLL1.
1459 *
1460 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1461 *
1462 */
1463 void CLOCK_InitVideoPll1(const ccm_analog_frac_pll_config_t *config);
1464
1465 /*!
1466 * @brief De-initialize the Video PLL1.
1467 */
1468 void CLOCK_DeinitVideoPll1(void);
1469
1470 /*!
1471 * @brief Initializes the ANALOG Integer PLL.
1472 *
1473 * @param base CCM ANALOG base address
1474 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1475 * @param type integer pll type
1476 *
1477 */
1478 void CLOCK_InitIntegerPll(CCM_ANALOG_Type *base, const ccm_analog_integer_pll_config_t *config, clock_pll_ctrl_t type);
1479
1480 /*!
1481 * @brief Get the ANALOG Integer PLL clock frequency.
1482 *
1483 * @param base CCM ANALOG base address.
1484 * @param type integer pll type
1485 * @param pll1Bypass pll1 bypass flag
1486 * @param refClkFreq Reference clock frequency.
1487 *
1488 * @return Clock frequency
1489 */
1490 uint32_t CLOCK_GetIntegerPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass);
1491
1492 /*!
1493 * @brief Initializes the ANALOG Fractional PLL.
1494 *
1495 * @param base CCM ANALOG base address.
1496 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1497 * @param type fractional pll type.
1498 *
1499 */
1500 void CLOCK_InitFracPll(CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type);
1501
1502 /*!
1503 * @brief Gets the ANALOG Fractional PLL clock frequency.
1504 *
1505 * @param base CCM_ANALOG base pointer.
1506 * @param type fractional pll type.
1507 * @param refClkFreq Reference clock frequency.
1508 *
1509 * @return Clock frequency
1510 */
1511 uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq);
1512
1513 /*!
1514 * @brief Gets PLL clock frequency.
1515 *
1516 * @param pll fractional pll type.
1517
1518 * @return Clock frequency
1519 */
1520 uint32_t CLOCK_GetPllFreq(clock_pll_ctrl_t pll);
1521
1522 /*!
1523 * @brief Gets PLL reference clock frequency.
1524 *
1525 * @param ctrl The pll control.
1526
1527 * @return Clock frequency
1528 */
1529 uint32_t CLOCK_GetPllRefClkFreq(clock_pll_ctrl_t ctrl);
1530
1531 /*!
1532 * @name CCM Get frequency
1533 * @{
1534 */
1535
1536 /*!
1537 * @brief Gets the clock frequency for a specific clock name.
1538 *
1539 * This function checks the current clock configurations and then calculates
1540 * the clock frequency for a specific clock name defined in clock_name_t.
1541 *
1542 * @param clockName Clock names defined in clock_name_t
1543 * @return Clock frequency value in hertz
1544 */
1545 uint32_t CLOCK_GetFreq(clock_name_t clockName);
1546
1547 /*!
1548 * @brief Gets the frequency of selected clock root.
1549 *
1550 * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
1551 * @return The frequency of selected clock root.
1552 */
1553 uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
1554
1555 /*!
1556 * @brief Get the CCM Cortex M4 core frequency.
1557 *
1558 * @return Clock frequency; If the clock is invalid, returns 0.
1559 */
1560 uint32_t CLOCK_GetCoreM4Freq(void);
1561
1562 /*!
1563 * @brief Get the CCM Axi bus frequency.
1564 *
1565 * @return Clock frequency; If the clock is invalid, returns 0.
1566 */
1567 uint32_t CLOCK_GetAxiFreq(void);
1568
1569 /*!
1570 * @brief Get the CCM Ahb bus frequency.
1571 *
1572 * @return Clock frequency; If the clock is invalid, returns 0.
1573 */
1574 uint32_t CLOCK_GetAhbFreq(void);
1575
1576 /*!
1577 * brief Get the CCM Enet AXI bus frequency.
1578 *
1579 * return Clock frequency; If the clock is invalid, returns 0.
1580 */
1581 uint32_t CLOCK_GetEnetAxiFreq(void);
1582
1583 /* @} */
1584
1585 #if defined(__cplusplus)
1586 }
1587 #endif
1588 /* @} */
1589 #endif
1590
