1/* ------------------------------------------------------------------------- */ 2/* @file: startup_MIMX8MM5_cm4.s */ 3/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ 4/* MIMX8MM5_cm4 */ 5/* @version: 4.0 */ 6/* @date: 2019-2-18 */ 7/* @build: b231019 */ 8/* ------------------------------------------------------------------------- */ 9/* */ 10/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ 11/* Copyright 2016-2023 NXP */ 12/* SPDX-License-Identifier: BSD-3-Clause */ 13/*****************************************************************************/ 14/* Version: GCC for ARM Embedded Processors */ 15/*****************************************************************************/ 16 .syntax unified 17 .arch armv7-m 18 19 .section .isr_vector, "a" 20 .align 2 21 .globl __isr_vector 22__isr_vector: 23 .long __StackTop /* Top of Stack */ 24 .long Reset_Handler /* Reset Handler */ 25 .long NMI_Handler /* NMI Handler*/ 26 .long HardFault_Handler /* Hard Fault Handler*/ 27 .long MemManage_Handler /* MPU Fault Handler*/ 28 .long BusFault_Handler /* Bus Fault Handler*/ 29 .long UsageFault_Handler /* Usage Fault Handler*/ 30 .long 0 /* Reserved*/ 31 .long 0 /* Reserved*/ 32 .long 0 /* Reserved*/ 33 .long 0 /* Reserved*/ 34 .long SVC_Handler /* SVCall Handler*/ 35 .long DebugMon_Handler /* Debug Monitor Handler*/ 36 .long 0 /* Reserved*/ 37 .long PendSV_Handler /* PendSV Handler*/ 38 .long SysTick_Handler /* SysTick Handler*/ 39 40 /* External Interrupts*/ 41 .long GPR_IRQ_IRQHandler /* GPR Interrupt. Used to notify cores on exception condition while boot.*/ 42 .long DAP_IRQHandler /* DAP Interrupt*/ 43 .long SDMA1_IRQHandler /* AND of all 48 SDMA1 interrupts (events) from all the channels*/ 44 .long GPU3D_IRQHandler /* GPU3D Interrupt*/ 45 .long SNVS_IRQHandler /* ON-OFF button press shorter than 5 seconds (pulse event)*/ 46 .long LCDIF_IRQHandler /* LCDIF Interrupt*/ 47 .long SPDIF1_IRQHandler /* SPDIF1 RZX/TX Interrupt*/ 48 .long VPU_G1_IRQHandler /* VPU G1 Decoder Interrupt*/ 49 .long VPU_G2_IRQHandler /* VPU G2 Decoder Interrupt*/ 50 .long QOS_IRQHandler /* QOS interrupt*/ 51 .long WDOG3_IRQHandler /* Watchdog Timer reset*/ 52 .long HS_CP1_IRQHandler /* HS Interrupt Request*/ 53 .long APBHDMA_IRQHandler /* GPMI operation channel 0-3 description complete interrupt*/ 54 .long Reserved29_IRQHandler /* Reserved*/ 55 .long BCH_IRQHandler /* BCH operation complete interrupt*/ 56 .long GPMI_IRQHandler /* GPMI operation TIMEOUT ERROR interrupt*/ 57 .long CSI1_IRQHandler /* CSI Interrupt*/ 58 .long MIPI_CSI1_IRQHandler /* MIPI CSI Interrupt*/ 59 .long MIPI_DSI_IRQHandler /* MIPI DSI Interrupt*/ 60 .long SNVS_Consolidated_IRQHandler /* SRTC Consolidated Interrupt. Non TZ.*/ 61 .long SNVS_Security_IRQHandler /* SRTC Security Interrupt. TZ.*/ 62 .long CSU_IRQHandler /* CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted.*/ 63 .long USDHC1_IRQHandler /* uSDHC1 Enhanced SDHC Interrupt Request*/ 64 .long USDHC2_IRQHandler /* uSDHC2 Enhanced SDHC Interrupt Request*/ 65 .long USDHC3_IRQHandler /* uSDHC3 Enhanced SDHC Interrupt Request*/ 66 .long GPU2D_IRQHandler /* GPU2D Interrupt*/ 67 .long UART1_IRQHandler /* UART-1 ORed interrupt*/ 68 .long UART2_IRQHandler /* UART-2 ORed interrupt*/ 69 .long UART3_IRQHandler /* UART-3 ORed interrupt*/ 70 .long UART4_IRQHandler /* UART-4 ORed interrupt*/ 71 .long VPU_H1_IRQHandler /* VPU H1 Encoder Interrupt*/ 72 .long ECSPI1_IRQHandler /* ECSPI1 interrupt request line to the core.*/ 73 .long ECSPI2_IRQHandler /* ECSPI2 interrupt request line to the core.*/ 74 .long ECSPI3_IRQHandler /* ECSPI3 interrupt request line to the core.*/ 75 .long SDMA3_IRQHandler /* AND of all 48 SDMA3 interrupts (events) from all the channels*/ 76 .long I2C1_IRQHandler /* I2C-1 Interrupt*/ 77 .long I2C2_IRQHandler /* I2C-2 Interrupt*/ 78 .long I2C3_IRQHandler /* I2C-3 Interrupt*/ 79 .long I2C4_IRQHandler /* I2C-4 Interrupt*/ 80 .long RDC_IRQHandler /* RDC interrupt*/ 81 .long USB1_IRQHandler /* USB1 Interrupt*/ 82 .long USB2_IRQHandler /* USB1 Interrupt*/ 83 .long Reserved58_IRQHandler /* Reserved interrupt*/ 84 .long Reserved59_IRQHandler /* Reserved interrupt*/ 85 .long PDM_HWVAD_EVENT_IRQHandler /* Digital Microphone interface voice activity detector event interrupt*/ 86 .long PDM_HWVAD_ERROR_IRQHandler /* Digital Microphone interface voice activity detector error interrupt*/ 87 .long GPT6_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 88 .long SCTR_IRQ0_IRQHandler /* System Counter Interrupt 0*/ 89 .long SCTR_IRQ1_IRQHandler /* System Counter Interrupt 1*/ 90 .long TEMPMON_LOW_IRQHandler /* TempSensor (Temperature low alarm).*/ 91 .long I2S3_IRQHandler /* SAI3 Receive / Transmit Interrupt*/ 92 .long GPT5_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 93 .long GPT4_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 94 .long GPT3_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 95 .long GPT2_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 96 .long GPT1_IRQHandler /* OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines*/ 97 .long GPIO1_INT7_IRQHandler /* Active HIGH Interrupt from INT7 from GPIO*/ 98 .long GPIO1_INT6_IRQHandler /* Active HIGH Interrupt from INT6 from GPIO*/ 99 .long GPIO1_INT5_IRQHandler /* Active HIGH Interrupt from INT5 from GPIO*/ 100 .long GPIO1_INT4_IRQHandler /* Active HIGH Interrupt from INT4 from GPIO*/ 101 .long GPIO1_INT3_IRQHandler /* Active HIGH Interrupt from INT3 from GPIO*/ 102 .long GPIO1_INT2_IRQHandler /* Active HIGH Interrupt from INT2 from GPIO*/ 103 .long GPIO1_INT1_IRQHandler /* Active HIGH Interrupt from INT1 from GPIO*/ 104 .long GPIO1_INT0_IRQHandler /* Active HIGH Interrupt from INT0 from GPIO*/ 105 .long GPIO1_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/ 106 .long GPIO1_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/ 107 .long GPIO2_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/ 108 .long GPIO2_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/ 109 .long GPIO3_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/ 110 .long GPIO3_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/ 111 .long GPIO4_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/ 112 .long GPIO4_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/ 113 .long GPIO5_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/ 114 .long GPIO5_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/ 115 .long Reserved90_IRQHandler /* Reserved interrupt*/ 116 .long Reserved91_IRQHandler /* Reserved interrupt*/ 117 .long Reserved92_IRQHandler /* Reserved interrupt*/ 118 .long Reserved93_IRQHandler /* Reserved interrupt*/ 119 .long WDOG1_IRQHandler /* Watchdog Timer reset*/ 120 .long WDOG2_IRQHandler /* Watchdog Timer reset*/ 121 .long Reserved96_IRQHandler /* Reserved interrupt*/ 122 .long PWM1_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 123 .long PWM2_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 124 .long PWM3_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 125 .long PWM4_IRQHandler /* Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line.*/ 126 .long CCM_IRQ1_IRQHandler /* CCM Interrupt Request 1*/ 127 .long CCM_IRQ2_IRQHandler /* CCM Interrupt Request 2*/ 128 .long GPC_IRQHandler /* GPC Interrupt Request 1*/ 129 .long MU_A53_IRQHandler /* Interrupt to A53*/ 130 .long SRC_IRQHandler /* SRC interrupt request*/ 131 .long I2S56_IRQHandler /* SAI5/6 Receive / Transmit Interrupt*/ 132 .long RTIC_IRQHandler /* RTIC Interrupt*/ 133 .long CPU_PerformanceUnit_IRQHandler /* Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n]*/ 134 .long CPU_CTI_Trigger_IRQHandler /* CTI trigger outputs (internal: nCTIIRQ[n]*/ 135 .long SRC_Combined_IRQHandler /* Combined CPU wdog interrupts (4x) out of SRC.*/ 136 .long I2S1_IRQHandler /* SAI1 Receive / Transmit Interrupt*/ 137 .long I2S2_IRQHandler /* SAI2 Receive / Transmit Interrupt*/ 138 .long MU_M4_IRQHandler /* Interrupt to M4*/ 139 .long DDR_PerformanceMonitor_IRQHandler /* ddr Interrupt for performance monitor*/ 140 .long DDR_IRQHandler /* ddr Interrupt*/ 141 .long Reserved116_IRQHandler /* Reserved interrupt*/ 142 .long CPU_Error_AXI_IRQHandler /* CPU Error indicator for AXI transaction with a write response error condition*/ 143 .long CPU_Error_L2RAM_IRQHandler /* CPU Error indicator for L2 RAM double-bit ECC error*/ 144 .long SDMA2_IRQHandler /* AND of all 48 SDMA2 interrupts (events) from all the channels*/ 145 .long SJC_IRQHandler /* Interrupt triggered by SJC register*/ 146 .long CAAM_IRQ0_IRQHandler /* CAAM interrupt queue for JQ*/ 147 .long CAAM_IRQ1_IRQHandler /* CAAM interrupt queue for JQ*/ 148 .long QSPI_IRQHandler /* QSPI Interrupt*/ 149 .long TZASC_IRQHandler /* TZASC (PL380) interrupt*/ 150 .long PDM_EVENT_IRQHandler /* Digital Microphone interface interrupt*/ 151 .long PDM_ERROR_IRQHandler /* Digital Microphone interface error interrupt*/ 152 .long Reserved127_IRQHandler /* Reserved interrupt*/ 153 .long PERFMON1_IRQHandler /* General Interrupt*/ 154 .long PERFMON2_IRQHandler /* General Interrupt*/ 155 .long CAAM_IRQ2_IRQHandler /* CAAM interrupt queue for JQ*/ 156 .long CAAM_ERROR_IRQHandler /* Recoverable error interrupt*/ 157 .long HS_CP0_IRQHandler /* HS Interrupt Request*/ 158 .long Reserved133_IRQHandler /* Reserved interrupt*/ 159 .long ENET1_MAC0_Rx_Tx_Done1_IRQHandler /* MAC 0 Receive / Trasmit Frame / Buffer Done*/ 160 .long ENET1_MAC0_Rx_Tx_Done2_IRQHandler /* MAC 0 Receive / Trasmit Frame / Buffer Done*/ 161 .long ENET1_IRQHandler /* MAC 0 IRQ*/ 162 .long ENET1_1588_Timer_IRQHandler /* MAC 0 1588 Timer Interrupt - synchronous*/ 163 .long PCIE_CTRL1_IRQ0_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 164 .long PCIE_CTRL1_IRQ1_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 165 .long PCIE_CTRL1_IRQ2_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 166 .long PCIE_CTRL1_IRQ3_IRQHandler /* Coming from GLUE logic, of set / reset FF, driven by PCIE signals.*/ 167 .long Reserved142_IRQHandler /* Reserved*/ 168 .long PCIE_CTRL1_IRQHandler /* Channels [63:32] interrupts requests*/ 169 170 .size __isr_vector, . - __isr_vector 171 172 .text 173 .thumb 174 175#if defined (__cplusplus) 176#ifdef __REDLIB__ 177#error Redlib does not support C++ 178#endif 179#endif 180/* Reset Handler */ 181 182 .thumb_func 183 .align 2 184 .globl Reset_Handler 185 .weak Reset_Handler 186 .type Reset_Handler, %function 187Reset_Handler: 188 cpsid i /* Mask interrupts */ 189 .equ VTOR, 0xE000ED08 190 ldr r0, =VTOR 191 ldr r1, =__isr_vector 192 str r1, [r0] 193 ldr r2, [r1] 194 msr msp, r2 195#ifndef __NO_SYSTEM_INIT 196 ldr r0,=SystemInit 197 blx r0 198#endif 199/* Loop to copy data from read only memory to RAM. The ranges 200 * of copy from/to are specified by following symbols evaluated in 201 * linker script. 202 * __etext: End of code section, i.e., begin of data sections to copy from. 203 * __data_start__/__data_end__: RAM address range that data should be 204 * __noncachedata_start__/__noncachedata_end__ : none cachable region 205 * copied to. Both must be aligned to 4 bytes boundary. */ 206 207 ldr r1, =__etext 208 ldr r2, =__data_start__ 209 ldr r3, =__data_end__ 210 211#if 1 212/* Here are two copies of loop implemenations. First one favors code size 213 * and the second one favors performance. Default uses the first one. 214 * Change to "#if 0" to use the second one */ 215.LC0: 216 cmp r2, r3 217 ittt lt 218 ldrlt r0, [r1], #4 219 strlt r0, [r2], #4 220 blt .LC0 221#else 222 subs r3, r2 223 ble .LC1 224.LC0: 225 subs r3, #4 226 ldr r0, [r1, r3] 227 str r0, [r2, r3] 228 bgt .LC0 229.LC1: 230#endif 231 232#ifdef __STARTUP_INITIALIZE_NONCACHEDATA 233 ldr r2, =__noncachedata_start__ 234 ldr r3, =__noncachedata_init_end__ 235#if 1 236.LC2: 237 cmp r2, r3 238 ittt lt 239 ldrlt r0, [r1], #4 240 strlt r0, [r2], #4 241 blt .LC2 242#else 243 subs r3, r2 244 ble .LC3 245.LC2: 246 subs r3, #4 247 ldr r0, [r1, r3] 248 str r0, [r2, r3] 249 bgt .LC2 250.LC3: 251#endif 252/* zero inited ncache section initialization */ 253 ldr r3, =__noncachedata_end__ 254 movs r0,0 255.LC4: 256 cmp r2,r3 257 itt lt 258 strlt r0,[r2],#4 259 blt .LC4 260#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */ 261 262#ifdef __STARTUP_CLEAR_BSS 263/* This part of work usually is done in C library startup code. Otherwise, 264 * define this macro to enable it in this startup. 265 * 266 * Loop to zero out BSS section, which uses following symbols 267 * in linker script: 268 * __bss_start__: start of BSS section. Must align to 4 269 * __bss_end__: end of BSS section. Must align to 4 270 */ 271 ldr r1, =__bss_start__ 272 ldr r2, =__bss_end__ 273 274 movs r0, 0 275.LC5: 276 cmp r1, r2 277 itt lt 278 strlt r0, [r1], #4 279 blt .LC5 280#endif /* __STARTUP_CLEAR_BSS */ 281 282 cpsie i /* Unmask interrupts */ 283#ifndef __START 284#ifdef __REDLIB__ 285#define __START __main 286#else 287#define __START _start 288#endif 289#endif 290#ifndef __ATOLLIC__ 291 ldr r0,=__START 292 blx r0 293#else 294 ldr r0,=__libc_init_array 295 blx r0 296 ldr r0,=main 297 bx r0 298#endif 299 .pool 300 .size Reset_Handler, . - Reset_Handler 301 302 .align 1 303 .thumb_func 304 .weak DefaultISR 305 .type DefaultISR, %function 306DefaultISR: 307 b DefaultISR 308 .size DefaultISR, . - DefaultISR 309 310 .align 1 311 .thumb_func 312 .weak NMI_Handler 313 .type NMI_Handler, %function 314NMI_Handler: 315 ldr r0,=NMI_Handler 316 bx r0 317 .size NMI_Handler, . - NMI_Handler 318 319 .align 1 320 .thumb_func 321 .weak HardFault_Handler 322 .type HardFault_Handler, %function 323HardFault_Handler: 324 ldr r0,=HardFault_Handler 325 bx r0 326 .size HardFault_Handler, . - HardFault_Handler 327 328 .align 1 329 .thumb_func 330 .weak SVC_Handler 331 .type SVC_Handler, %function 332SVC_Handler: 333 ldr r0,=SVC_Handler 334 bx r0 335 .size SVC_Handler, . - SVC_Handler 336 337 .align 1 338 .thumb_func 339 .weak PendSV_Handler 340 .type PendSV_Handler, %function 341PendSV_Handler: 342 ldr r0,=PendSV_Handler 343 bx r0 344 .size PendSV_Handler, . - PendSV_Handler 345 346 .align 1 347 .thumb_func 348 .weak SysTick_Handler 349 .type SysTick_Handler, %function 350SysTick_Handler: 351 ldr r0,=SysTick_Handler 352 bx r0 353 .size SysTick_Handler, . - SysTick_Handler 354 355 .align 1 356 .thumb_func 357 .weak SDMA1_IRQHandler 358 .type SDMA1_IRQHandler, %function 359SDMA1_IRQHandler: 360 ldr r0,=SDMA1_DriverIRQHandler 361 bx r0 362 .size SDMA1_IRQHandler, . - SDMA1_IRQHandler 363 364 .align 1 365 .thumb_func 366 .weak SPDIF1_IRQHandler 367 .type SPDIF1_IRQHandler, %function 368SPDIF1_IRQHandler: 369 ldr r0,=SPDIF1_DriverIRQHandler 370 bx r0 371 .size SPDIF1_IRQHandler, . - SPDIF1_IRQHandler 372 373 .align 1 374 .thumb_func 375 .weak APBHDMA_IRQHandler 376 .type APBHDMA_IRQHandler, %function 377APBHDMA_IRQHandler: 378 ldr r0,=APBHDMA_DriverIRQHandler 379 bx r0 380 .size APBHDMA_IRQHandler, . - APBHDMA_IRQHandler 381 382 .align 1 383 .thumb_func 384 .weak USDHC1_IRQHandler 385 .type USDHC1_IRQHandler, %function 386USDHC1_IRQHandler: 387 ldr r0,=USDHC1_DriverIRQHandler 388 bx r0 389 .size USDHC1_IRQHandler, . - USDHC1_IRQHandler 390 391 .align 1 392 .thumb_func 393 .weak USDHC2_IRQHandler 394 .type USDHC2_IRQHandler, %function 395USDHC2_IRQHandler: 396 ldr r0,=USDHC2_DriverIRQHandler 397 bx r0 398 .size USDHC2_IRQHandler, . - USDHC2_IRQHandler 399 400 .align 1 401 .thumb_func 402 .weak USDHC3_IRQHandler 403 .type USDHC3_IRQHandler, %function 404USDHC3_IRQHandler: 405 ldr r0,=USDHC3_DriverIRQHandler 406 bx r0 407 .size USDHC3_IRQHandler, . - USDHC3_IRQHandler 408 409 .align 1 410 .thumb_func 411 .weak UART1_IRQHandler 412 .type UART1_IRQHandler, %function 413UART1_IRQHandler: 414 ldr r0,=UART1_DriverIRQHandler 415 bx r0 416 .size UART1_IRQHandler, . - UART1_IRQHandler 417 418 .align 1 419 .thumb_func 420 .weak UART2_IRQHandler 421 .type UART2_IRQHandler, %function 422UART2_IRQHandler: 423 ldr r0,=UART2_DriverIRQHandler 424 bx r0 425 .size UART2_IRQHandler, . - UART2_IRQHandler 426 427 .align 1 428 .thumb_func 429 .weak UART3_IRQHandler 430 .type UART3_IRQHandler, %function 431UART3_IRQHandler: 432 ldr r0,=UART3_DriverIRQHandler 433 bx r0 434 .size UART3_IRQHandler, . - UART3_IRQHandler 435 436 .align 1 437 .thumb_func 438 .weak UART4_IRQHandler 439 .type UART4_IRQHandler, %function 440UART4_IRQHandler: 441 ldr r0,=UART4_DriverIRQHandler 442 bx r0 443 .size UART4_IRQHandler, . - UART4_IRQHandler 444 445 .align 1 446 .thumb_func 447 .weak ECSPI1_IRQHandler 448 .type ECSPI1_IRQHandler, %function 449ECSPI1_IRQHandler: 450 ldr r0,=ECSPI1_DriverIRQHandler 451 bx r0 452 .size ECSPI1_IRQHandler, . - ECSPI1_IRQHandler 453 454 .align 1 455 .thumb_func 456 .weak ECSPI2_IRQHandler 457 .type ECSPI2_IRQHandler, %function 458ECSPI2_IRQHandler: 459 ldr r0,=ECSPI2_DriverIRQHandler 460 bx r0 461 .size ECSPI2_IRQHandler, . - ECSPI2_IRQHandler 462 463 .align 1 464 .thumb_func 465 .weak ECSPI3_IRQHandler 466 .type ECSPI3_IRQHandler, %function 467ECSPI3_IRQHandler: 468 ldr r0,=ECSPI3_DriverIRQHandler 469 bx r0 470 .size ECSPI3_IRQHandler, . - ECSPI3_IRQHandler 471 472 .align 1 473 .thumb_func 474 .weak SDMA3_IRQHandler 475 .type SDMA3_IRQHandler, %function 476SDMA3_IRQHandler: 477 ldr r0,=SDMA3_DriverIRQHandler 478 bx r0 479 .size SDMA3_IRQHandler, . - SDMA3_IRQHandler 480 481 .align 1 482 .thumb_func 483 .weak I2C1_IRQHandler 484 .type I2C1_IRQHandler, %function 485I2C1_IRQHandler: 486 ldr r0,=I2C1_DriverIRQHandler 487 bx r0 488 .size I2C1_IRQHandler, . - I2C1_IRQHandler 489 490 .align 1 491 .thumb_func 492 .weak I2C2_IRQHandler 493 .type I2C2_IRQHandler, %function 494I2C2_IRQHandler: 495 ldr r0,=I2C2_DriverIRQHandler 496 bx r0 497 .size I2C2_IRQHandler, . - I2C2_IRQHandler 498 499 .align 1 500 .thumb_func 501 .weak I2C3_IRQHandler 502 .type I2C3_IRQHandler, %function 503I2C3_IRQHandler: 504 ldr r0,=I2C3_DriverIRQHandler 505 bx r0 506 .size I2C3_IRQHandler, . - I2C3_IRQHandler 507 508 .align 1 509 .thumb_func 510 .weak I2C4_IRQHandler 511 .type I2C4_IRQHandler, %function 512I2C4_IRQHandler: 513 ldr r0,=I2C4_DriverIRQHandler 514 bx r0 515 .size I2C4_IRQHandler, . - I2C4_IRQHandler 516 517 .align 1 518 .thumb_func 519 .weak PDM_HWVAD_EVENT_IRQHandler 520 .type PDM_HWVAD_EVENT_IRQHandler, %function 521PDM_HWVAD_EVENT_IRQHandler: 522 ldr r0,=PDM_HWVAD_EVENT_DriverIRQHandler 523 bx r0 524 .size PDM_HWVAD_EVENT_IRQHandler, . - PDM_HWVAD_EVENT_IRQHandler 525 526 .align 1 527 .thumb_func 528 .weak PDM_HWVAD_ERROR_IRQHandler 529 .type PDM_HWVAD_ERROR_IRQHandler, %function 530PDM_HWVAD_ERROR_IRQHandler: 531 ldr r0,=PDM_HWVAD_ERROR_DriverIRQHandler 532 bx r0 533 .size PDM_HWVAD_ERROR_IRQHandler, . - PDM_HWVAD_ERROR_IRQHandler 534 535 .align 1 536 .thumb_func 537 .weak I2S3_IRQHandler 538 .type I2S3_IRQHandler, %function 539I2S3_IRQHandler: 540 ldr r0,=I2S3_DriverIRQHandler 541 bx r0 542 .size I2S3_IRQHandler, . - I2S3_IRQHandler 543 544 .align 1 545 .thumb_func 546 .weak I2S56_IRQHandler 547 .type I2S56_IRQHandler, %function 548I2S56_IRQHandler: 549 ldr r0,=I2S56_DriverIRQHandler 550 bx r0 551 .size I2S56_IRQHandler, . - I2S56_IRQHandler 552 553 .align 1 554 .thumb_func 555 .weak I2S1_IRQHandler 556 .type I2S1_IRQHandler, %function 557I2S1_IRQHandler: 558 ldr r0,=I2S1_DriverIRQHandler 559 bx r0 560 .size I2S1_IRQHandler, . - I2S1_IRQHandler 561 562 .align 1 563 .thumb_func 564 .weak I2S2_IRQHandler 565 .type I2S2_IRQHandler, %function 566I2S2_IRQHandler: 567 ldr r0,=I2S2_DriverIRQHandler 568 bx r0 569 .size I2S2_IRQHandler, . - I2S2_IRQHandler 570 571 .align 1 572 .thumb_func 573 .weak SDMA2_IRQHandler 574 .type SDMA2_IRQHandler, %function 575SDMA2_IRQHandler: 576 ldr r0,=SDMA2_DriverIRQHandler 577 bx r0 578 .size SDMA2_IRQHandler, . - SDMA2_IRQHandler 579 580 .align 1 581 .thumb_func 582 .weak QSPI_IRQHandler 583 .type QSPI_IRQHandler, %function 584QSPI_IRQHandler: 585 ldr r0,=QSPI_DriverIRQHandler 586 bx r0 587 .size QSPI_IRQHandler, . - QSPI_IRQHandler 588 589 .align 1 590 .thumb_func 591 .weak PDM_EVENT_IRQHandler 592 .type PDM_EVENT_IRQHandler, %function 593PDM_EVENT_IRQHandler: 594 ldr r0,=PDM_EVENT_DriverIRQHandler 595 bx r0 596 .size PDM_EVENT_IRQHandler, . - PDM_EVENT_IRQHandler 597 598 .align 1 599 .thumb_func 600 .weak ENET1_MAC0_Rx_Tx_Done1_IRQHandler 601 .type ENET1_MAC0_Rx_Tx_Done1_IRQHandler, %function 602ENET1_MAC0_Rx_Tx_Done1_IRQHandler: 603 ldr r0,=ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler 604 bx r0 605 .size ENET1_MAC0_Rx_Tx_Done1_IRQHandler, . - ENET1_MAC0_Rx_Tx_Done1_IRQHandler 606 607 .align 1 608 .thumb_func 609 .weak ENET1_MAC0_Rx_Tx_Done2_IRQHandler 610 .type ENET1_MAC0_Rx_Tx_Done2_IRQHandler, %function 611ENET1_MAC0_Rx_Tx_Done2_IRQHandler: 612 ldr r0,=ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler 613 bx r0 614 .size ENET1_MAC0_Rx_Tx_Done2_IRQHandler, . - ENET1_MAC0_Rx_Tx_Done2_IRQHandler 615 616 .align 1 617 .thumb_func 618 .weak ENET1_IRQHandler 619 .type ENET1_IRQHandler, %function 620ENET1_IRQHandler: 621 ldr r0,=ENET1_DriverIRQHandler 622 bx r0 623 .size ENET1_IRQHandler, . - ENET1_IRQHandler 624 625 .align 1 626 .thumb_func 627 .weak ENET1_1588_Timer_IRQHandler 628 .type ENET1_1588_Timer_IRQHandler, %function 629ENET1_1588_Timer_IRQHandler: 630 ldr r0,=ENET1_1588_Timer_DriverIRQHandler 631 bx r0 632 .size ENET1_1588_Timer_IRQHandler, . - ENET1_1588_Timer_IRQHandler 633 634 635/* Macro to define default handlers. Default handler 636 * will be weak symbol and just dead loops. They can be 637 * overwritten by other handlers */ 638 .macro def_irq_handler handler_name 639 .weak \handler_name 640 .set \handler_name, DefaultISR 641 .endm 642/* Exception Handlers */ 643 def_irq_handler MemManage_Handler 644 def_irq_handler BusFault_Handler 645 def_irq_handler UsageFault_Handler 646 def_irq_handler DebugMon_Handler 647 def_irq_handler GPR_IRQ_IRQHandler 648 def_irq_handler DAP_IRQHandler 649 def_irq_handler SDMA1_DriverIRQHandler 650 def_irq_handler GPU3D_IRQHandler 651 def_irq_handler SNVS_IRQHandler 652 def_irq_handler LCDIF_IRQHandler 653 def_irq_handler SPDIF1_DriverIRQHandler 654 def_irq_handler VPU_G1_IRQHandler 655 def_irq_handler VPU_G2_IRQHandler 656 def_irq_handler QOS_IRQHandler 657 def_irq_handler WDOG3_IRQHandler 658 def_irq_handler HS_CP1_IRQHandler 659 def_irq_handler APBHDMA_DriverIRQHandler 660 def_irq_handler Reserved29_IRQHandler 661 def_irq_handler BCH_IRQHandler 662 def_irq_handler GPMI_IRQHandler 663 def_irq_handler CSI1_IRQHandler 664 def_irq_handler MIPI_CSI1_IRQHandler 665 def_irq_handler MIPI_DSI_IRQHandler 666 def_irq_handler SNVS_Consolidated_IRQHandler 667 def_irq_handler SNVS_Security_IRQHandler 668 def_irq_handler CSU_IRQHandler 669 def_irq_handler USDHC1_DriverIRQHandler 670 def_irq_handler USDHC2_DriverIRQHandler 671 def_irq_handler USDHC3_DriverIRQHandler 672 def_irq_handler GPU2D_IRQHandler 673 def_irq_handler UART1_DriverIRQHandler 674 def_irq_handler UART2_DriverIRQHandler 675 def_irq_handler UART3_DriverIRQHandler 676 def_irq_handler UART4_DriverIRQHandler 677 def_irq_handler VPU_H1_IRQHandler 678 def_irq_handler ECSPI1_DriverIRQHandler 679 def_irq_handler ECSPI2_DriverIRQHandler 680 def_irq_handler ECSPI3_DriverIRQHandler 681 def_irq_handler SDMA3_DriverIRQHandler 682 def_irq_handler I2C1_DriverIRQHandler 683 def_irq_handler I2C2_DriverIRQHandler 684 def_irq_handler I2C3_DriverIRQHandler 685 def_irq_handler I2C4_DriverIRQHandler 686 def_irq_handler RDC_IRQHandler 687 def_irq_handler USB1_IRQHandler 688 def_irq_handler USB2_IRQHandler 689 def_irq_handler Reserved58_IRQHandler 690 def_irq_handler Reserved59_IRQHandler 691 def_irq_handler PDM_HWVAD_EVENT_DriverIRQHandler 692 def_irq_handler PDM_HWVAD_ERROR_DriverIRQHandler 693 def_irq_handler GPT6_IRQHandler 694 def_irq_handler SCTR_IRQ0_IRQHandler 695 def_irq_handler SCTR_IRQ1_IRQHandler 696 def_irq_handler TEMPMON_LOW_IRQHandler 697 def_irq_handler I2S3_DriverIRQHandler 698 def_irq_handler GPT5_IRQHandler 699 def_irq_handler GPT4_IRQHandler 700 def_irq_handler GPT3_IRQHandler 701 def_irq_handler GPT2_IRQHandler 702 def_irq_handler GPT1_IRQHandler 703 def_irq_handler GPIO1_INT7_IRQHandler 704 def_irq_handler GPIO1_INT6_IRQHandler 705 def_irq_handler GPIO1_INT5_IRQHandler 706 def_irq_handler GPIO1_INT4_IRQHandler 707 def_irq_handler GPIO1_INT3_IRQHandler 708 def_irq_handler GPIO1_INT2_IRQHandler 709 def_irq_handler GPIO1_INT1_IRQHandler 710 def_irq_handler GPIO1_INT0_IRQHandler 711 def_irq_handler GPIO1_Combined_0_15_IRQHandler 712 def_irq_handler GPIO1_Combined_16_31_IRQHandler 713 def_irq_handler GPIO2_Combined_0_15_IRQHandler 714 def_irq_handler GPIO2_Combined_16_31_IRQHandler 715 def_irq_handler GPIO3_Combined_0_15_IRQHandler 716 def_irq_handler GPIO3_Combined_16_31_IRQHandler 717 def_irq_handler GPIO4_Combined_0_15_IRQHandler 718 def_irq_handler GPIO4_Combined_16_31_IRQHandler 719 def_irq_handler GPIO5_Combined_0_15_IRQHandler 720 def_irq_handler GPIO5_Combined_16_31_IRQHandler 721 def_irq_handler Reserved90_IRQHandler 722 def_irq_handler Reserved91_IRQHandler 723 def_irq_handler Reserved92_IRQHandler 724 def_irq_handler Reserved93_IRQHandler 725 def_irq_handler WDOG1_IRQHandler 726 def_irq_handler WDOG2_IRQHandler 727 def_irq_handler Reserved96_IRQHandler 728 def_irq_handler PWM1_IRQHandler 729 def_irq_handler PWM2_IRQHandler 730 def_irq_handler PWM3_IRQHandler 731 def_irq_handler PWM4_IRQHandler 732 def_irq_handler CCM_IRQ1_IRQHandler 733 def_irq_handler CCM_IRQ2_IRQHandler 734 def_irq_handler GPC_IRQHandler 735 def_irq_handler MU_A53_IRQHandler 736 def_irq_handler SRC_IRQHandler 737 def_irq_handler I2S56_DriverIRQHandler 738 def_irq_handler RTIC_IRQHandler 739 def_irq_handler CPU_PerformanceUnit_IRQHandler 740 def_irq_handler CPU_CTI_Trigger_IRQHandler 741 def_irq_handler SRC_Combined_IRQHandler 742 def_irq_handler I2S1_DriverIRQHandler 743 def_irq_handler I2S2_DriverIRQHandler 744 def_irq_handler MU_M4_IRQHandler 745 def_irq_handler DDR_PerformanceMonitor_IRQHandler 746 def_irq_handler DDR_IRQHandler 747 def_irq_handler Reserved116_IRQHandler 748 def_irq_handler CPU_Error_AXI_IRQHandler 749 def_irq_handler CPU_Error_L2RAM_IRQHandler 750 def_irq_handler SDMA2_DriverIRQHandler 751 def_irq_handler SJC_IRQHandler 752 def_irq_handler CAAM_IRQ0_IRQHandler 753 def_irq_handler CAAM_IRQ1_IRQHandler 754 def_irq_handler QSPI_DriverIRQHandler 755 def_irq_handler TZASC_IRQHandler 756 def_irq_handler PDM_EVENT_DriverIRQHandler 757 def_irq_handler PDM_ERROR_IRQHandler 758 def_irq_handler Reserved127_IRQHandler 759 def_irq_handler PERFMON1_IRQHandler 760 def_irq_handler PERFMON2_IRQHandler 761 def_irq_handler CAAM_IRQ2_IRQHandler 762 def_irq_handler CAAM_ERROR_IRQHandler 763 def_irq_handler HS_CP0_IRQHandler 764 def_irq_handler Reserved133_IRQHandler 765 def_irq_handler ENET1_MAC0_Rx_Tx_Done1_DriverIRQHandler 766 def_irq_handler ENET1_MAC0_Rx_Tx_Done2_DriverIRQHandler 767 def_irq_handler ENET1_DriverIRQHandler 768 def_irq_handler ENET1_1588_Timer_DriverIRQHandler 769 def_irq_handler PCIE_CTRL1_IRQ0_IRQHandler 770 def_irq_handler PCIE_CTRL1_IRQ1_IRQHandler 771 def_irq_handler PCIE_CTRL1_IRQ2_IRQHandler 772 def_irq_handler PCIE_CTRL1_IRQ3_IRQHandler 773 def_irq_handler Reserved142_IRQHandler 774 def_irq_handler PCIE_CTRL1_IRQHandler 775 776 .end 777
